1#ifndef _dcn_3_0_0_OFFSET_HEADER 2#define _dcn_3_0_0_OFFSET_HEADER 3 4 5 6// addressBlock: dce_dc_mmhubbub_vga_dispdec 7// base address: 0x0 8#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000 9#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000 10#define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0 11#define mmVGA_MEM_READ_PAGE_ADDR 0x0001 12#define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0 13#define mmVGA_RENDER_CONTROL 0x0000 14#define mmVGA_RENDER_CONTROL_BASE_IDX 1 15#define mmVGA_SEQUENCER_RESET_CONTROL 0x0001 16#define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1 17#define mmVGA_MODE_CONTROL 0x0002 18#define mmVGA_MODE_CONTROL_BASE_IDX 1 19#define mmVGA_SURFACE_PITCH_SELECT 0x0003 20#define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX 1 21#define mmVGA_MEMORY_BASE_ADDRESS 0x0004 22#define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1 23#define mmVGA_DISPBUF1_SURFACE_ADDR 0x0006 24#define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1 25#define mmVGA_DISPBUF2_SURFACE_ADDR 0x0008 26#define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1 27#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009 28#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1 29#define mmVGA_HDP_CONTROL 0x000a 30#define mmVGA_HDP_CONTROL_BASE_IDX 1 31#define mmVGA_CACHE_CONTROL 0x000b 32#define mmVGA_CACHE_CONTROL_BASE_IDX 1 33#define mmD1VGA_CONTROL 0x000c 34#define mmD1VGA_CONTROL_BASE_IDX 1 35#define mmD2VGA_CONTROL 0x000e 36#define mmD2VGA_CONTROL_BASE_IDX 1 37#define mmVGA_STATUS 0x0010 38#define mmVGA_STATUS_BASE_IDX 1 39#define mmVGA_INTERRUPT_CONTROL 0x0011 40#define mmVGA_INTERRUPT_CONTROL_BASE_IDX 1 41#define mmVGA_STATUS_CLEAR 0x0012 42#define mmVGA_STATUS_CLEAR_BASE_IDX 1 43#define mmVGA_INTERRUPT_STATUS 0x0013 44#define mmVGA_INTERRUPT_STATUS_BASE_IDX 1 45#define mmVGA_MAIN_CONTROL 0x0014 46#define mmVGA_MAIN_CONTROL_BASE_IDX 1 47#define mmVGA_TEST_CONTROL 0x0015 48#define mmVGA_TEST_CONTROL_BASE_IDX 1 49#define mmVGA_QOS_CTRL 0x0018 50#define mmVGA_QOS_CTRL_BASE_IDX 1 51#define mmCRTC8_IDX 0x002d 52#define mmCRTC8_IDX_BASE_IDX 1 53#define mmCRTC8_DATA 0x002d 54#define mmCRTC8_DATA_BASE_IDX 1 55#define mmGENFC_WT 0x002e 56#define mmGENFC_WT_BASE_IDX 1 57#define mmGENS1 0x002e 58#define mmGENS1_BASE_IDX 1 59#define mmATTRDW 0x0030 60#define mmATTRDW_BASE_IDX 1 61#define mmATTRX 0x0030 62#define mmATTRX_BASE_IDX 1 63#define mmATTRDR 0x0030 64#define mmATTRDR_BASE_IDX 1 65#define mmGENMO_WT 0x0030 66#define mmGENMO_WT_BASE_IDX 1 67#define mmGENS0 0x0030 68#define mmGENS0_BASE_IDX 1 69#define mmGENENB 0x0030 70#define mmGENENB_BASE_IDX 1 71#define mmSEQ8_IDX 0x0031 72#define mmSEQ8_IDX_BASE_IDX 1 73#define mmSEQ8_DATA 0x0031 74#define mmSEQ8_DATA_BASE_IDX 1 75#define mmDAC_MASK 0x0031 76#define mmDAC_MASK_BASE_IDX 1 77#define mmDAC_R_INDEX 0x0031 78#define mmDAC_R_INDEX_BASE_IDX 1 79#define mmDAC_W_INDEX 0x0032 80#define mmDAC_W_INDEX_BASE_IDX 1 81#define mmDAC_DATA 0x0032 82#define mmDAC_DATA_BASE_IDX 1 83#define mmGENFC_RD 0x0032 84#define mmGENFC_RD_BASE_IDX 1 85#define mmGENMO_RD 0x0033 86#define mmGENMO_RD_BASE_IDX 1 87#define mmGRPH8_IDX 0x0033 88#define mmGRPH8_IDX_BASE_IDX 1 89#define mmGRPH8_DATA 0x0033 90#define mmGRPH8_DATA_BASE_IDX 1 91#define mmCRTC8_IDX_1 0x0035 92#define mmCRTC8_IDX_1_BASE_IDX 1 93#define mmCRTC8_DATA_1 0x0035 94#define mmCRTC8_DATA_1_BASE_IDX 1 95#define mmGENFC_WT_1 0x0036 96#define mmGENFC_WT_1_BASE_IDX 1 97#define mmGENS1_1 0x0036 98#define mmGENS1_1_BASE_IDX 1 99#define mmD3VGA_CONTROL 0x0038 100#define mmD3VGA_CONTROL_BASE_IDX 1 101#define mmD4VGA_CONTROL 0x0039 102#define mmD4VGA_CONTROL_BASE_IDX 1 103#define mmD5VGA_CONTROL 0x003a 104#define mmD5VGA_CONTROL_BASE_IDX 1 105#define mmD6VGA_CONTROL 0x003b 106#define mmD6VGA_CONTROL_BASE_IDX 1 107#define mmVGA_SOURCE_SELECT 0x003c 108#define mmVGA_SOURCE_SELECT_BASE_IDX 1 109 110 111// addressBlock: dce_dc_dccg_dccg_dispdec 112// base address: 0x0 113#define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040 114#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1 115#define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041 116#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1 117#define mmPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042 118#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1 119#define mmPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043 120#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1 121#define mmDP_DTO_DBUF_EN 0x0044 122#define mmDP_DTO_DBUF_EN_BASE_IDX 1 123#define mmDSCCLK3_DTO_PARAM 0x0045 124#define mmDSCCLK3_DTO_PARAM_BASE_IDX 1 125#define mmDSCCLK4_DTO_PARAM 0x0046 126#define mmDSCCLK4_DTO_PARAM_BASE_IDX 1 127#define mmDSCCLK5_DTO_PARAM 0x0047 128#define mmDSCCLK5_DTO_PARAM_BASE_IDX 1 129#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048 130#define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 131#define mmREFCLK_CNTL 0x0049 132#define mmREFCLK_CNTL_BASE_IDX 1 133#define mmREFCLK_CGTT_BLK_CTRL_REG 0x004b 134#define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 135#define mmPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c 136#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1 137#define mmDCCG_PERFMON_CNTL2 0x004e 138#define mmDCCG_PERFMON_CNTL2_BASE_IDX 1 139#define mmDCCG_DS_DTO_INCR 0x0053 140#define mmDCCG_DS_DTO_INCR_BASE_IDX 1 141#define mmDCCG_DS_DTO_MODULO 0x0054 142#define mmDCCG_DS_DTO_MODULO_BASE_IDX 1 143#define mmDCCG_DS_CNTL 0x0055 144#define mmDCCG_DS_CNTL_BASE_IDX 1 145#define mmDCCG_DS_HW_CAL_INTERVAL 0x0056 146#define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1 147#define mmDPREFCLK_CNTL 0x0058 148#define mmDPREFCLK_CNTL_BASE_IDX 1 149#define mmDCE_VERSION 0x005e 150#define mmDCE_VERSION_BASE_IDX 1 151#define mmDCCG_GTC_CNTL 0x0060 152#define mmDCCG_GTC_CNTL_BASE_IDX 1 153#define mmDCCG_GTC_DTO_INCR 0x0061 154#define mmDCCG_GTC_DTO_INCR_BASE_IDX 1 155#define mmDCCG_GTC_DTO_MODULO 0x0062 156#define mmDCCG_GTC_DTO_MODULO_BASE_IDX 1 157#define mmDCCG_GTC_CURRENT 0x0063 158#define mmDCCG_GTC_CURRENT_BASE_IDX 1 159#define mmDSCCLK0_DTO_PARAM 0x006c 160#define mmDSCCLK0_DTO_PARAM_BASE_IDX 1 161#define mmDSCCLK1_DTO_PARAM 0x006d 162#define mmDSCCLK1_DTO_PARAM_BASE_IDX 1 163#define mmDSCCLK2_DTO_PARAM 0x006e 164#define mmDSCCLK2_DTO_PARAM_BASE_IDX 1 165#define mmMILLISECOND_TIME_BASE_DIV 0x0070 166#define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX 1 167#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0071 168#define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1 169#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072 170#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1 171#define mmDCCG_PERFMON_CNTL 0x0073 172#define mmDCCG_PERFMON_CNTL_BASE_IDX 1 173#define mmDCCG_GATE_DISABLE_CNTL 0x0074 174#define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX 1 175#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0075 176#define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 177#define mmSOCCLK_CGTT_BLK_CTRL_REG 0x0076 178#define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 179#define mmDCCG_CAC_STATUS 0x0077 180#define mmDCCG_CAC_STATUS_BASE_IDX 1 181#define mmMICROSECOND_TIME_BASE_DIV 0x007b 182#define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX 1 183#define mmDCCG_GATE_DISABLE_CNTL2 0x007c 184#define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1 185#define mmSYMCLK_CGTT_BLK_CTRL_REG 0x007d 186#define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 187#define mmPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e 188#define mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1 189#define mmDCCG_DISP_CNTL_REG 0x007f 190#define mmDCCG_DISP_CNTL_REG_BASE_IDX 1 191#define mmOTG0_PIXEL_RATE_CNTL 0x0080 192#define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX 1 193#define mmDP_DTO0_PHASE 0x0081 194#define mmDP_DTO0_PHASE_BASE_IDX 1 195#define mmDP_DTO0_MODULO 0x0082 196#define mmDP_DTO0_MODULO_BASE_IDX 1 197#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083 198#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 199#define mmOTG1_PIXEL_RATE_CNTL 0x0084 200#define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX 1 201#define mmDP_DTO1_PHASE 0x0085 202#define mmDP_DTO1_PHASE_BASE_IDX 1 203#define mmDP_DTO1_MODULO 0x0086 204#define mmDP_DTO1_MODULO_BASE_IDX 1 205#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087 206#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 207#define mmOTG2_PIXEL_RATE_CNTL 0x0088 208#define mmOTG2_PIXEL_RATE_CNTL_BASE_IDX 1 209#define mmDP_DTO2_PHASE 0x0089 210#define mmDP_DTO2_PHASE_BASE_IDX 1 211#define mmDP_DTO2_MODULO 0x008a 212#define mmDP_DTO2_MODULO_BASE_IDX 1 213#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b 214#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 215#define mmOTG3_PIXEL_RATE_CNTL 0x008c 216#define mmOTG3_PIXEL_RATE_CNTL_BASE_IDX 1 217#define mmDP_DTO3_PHASE 0x008d 218#define mmDP_DTO3_PHASE_BASE_IDX 1 219#define mmDP_DTO3_MODULO 0x008e 220#define mmDP_DTO3_MODULO_BASE_IDX 1 221#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f 222#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 223#define mmOTG4_PIXEL_RATE_CNTL 0x0090 224#define mmOTG4_PIXEL_RATE_CNTL_BASE_IDX 1 225#define mmDP_DTO4_PHASE 0x0091 226#define mmDP_DTO4_PHASE_BASE_IDX 1 227#define mmDP_DTO4_MODULO 0x0092 228#define mmDP_DTO4_MODULO_BASE_IDX 1 229#define mmOTG4_PHYPLL_PIXEL_RATE_CNTL 0x0093 230#define mmOTG4_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 231#define mmOTG5_PIXEL_RATE_CNTL 0x0094 232#define mmOTG5_PIXEL_RATE_CNTL_BASE_IDX 1 233#define mmDP_DTO5_PHASE 0x0095 234#define mmDP_DTO5_PHASE_BASE_IDX 1 235#define mmDP_DTO5_MODULO 0x0096 236#define mmDP_DTO5_MODULO_BASE_IDX 1 237#define mmOTG5_PHYPLL_PIXEL_RATE_CNTL 0x0097 238#define mmOTG5_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 239#define mmDPPCLK_CGTT_BLK_CTRL_REG 0x0098 240#define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 241#define mmDPPCLK0_DTO_PARAM 0x0099 242#define mmDPPCLK0_DTO_PARAM_BASE_IDX 1 243#define mmDPPCLK1_DTO_PARAM 0x009a 244#define mmDPPCLK1_DTO_PARAM_BASE_IDX 1 245#define mmDPPCLK2_DTO_PARAM 0x009b 246#define mmDPPCLK2_DTO_PARAM_BASE_IDX 1 247#define mmDPPCLK3_DTO_PARAM 0x009c 248#define mmDPPCLK3_DTO_PARAM_BASE_IDX 1 249#define mmDPPCLK4_DTO_PARAM 0x009d 250#define mmDPPCLK4_DTO_PARAM_BASE_IDX 1 251#define mmDPPCLK5_DTO_PARAM 0x009e 252#define mmDPPCLK5_DTO_PARAM_BASE_IDX 1 253#define mmDCCG_CAC_STATUS2 0x009f 254#define mmDCCG_CAC_STATUS2_BASE_IDX 1 255#define mmSYMCLKA_CLOCK_ENABLE 0x00a0 256#define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX 1 257#define mmSYMCLKB_CLOCK_ENABLE 0x00a1 258#define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX 1 259#define mmSYMCLKC_CLOCK_ENABLE 0x00a2 260#define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX 1 261#define mmSYMCLKD_CLOCK_ENABLE 0x00a3 262#define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX 1 263#define mmSYMCLKE_CLOCK_ENABLE 0x00a4 264#define mmSYMCLKE_CLOCK_ENABLE_BASE_IDX 1 265#define mmSYMCLKF_CLOCK_ENABLE 0x00a5 266#define mmSYMCLKF_CLOCK_ENABLE_BASE_IDX 1 267#define mmDCCG_SOFT_RESET 0x00a6 268#define mmDCCG_SOFT_RESET_BASE_IDX 1 269#define mmDSCCLK_DTO_CTRL 0x00a7 270#define mmDSCCLK_DTO_CTRL_BASE_IDX 1 271#define mmDCCG_AUDIO_DTO_SOURCE 0x00ab 272#define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1 273#define mmDCCG_AUDIO_DTO0_PHASE 0x00ac 274#define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1 275#define mmDCCG_AUDIO_DTO0_MODULE 0x00ad 276#define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1 277#define mmDCCG_AUDIO_DTO1_PHASE 0x00ae 278#define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1 279#define mmDCCG_AUDIO_DTO1_MODULE 0x00af 280#define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1 281#define mmDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0 282#define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1 283#define mmDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1 284#define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1 285#define mmDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2 286#define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1 287#define mmDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3 288#define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1 289#define mmDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4 290#define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1 291#define mmDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5 292#define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1 293#define mmDPPCLK_DTO_CTRL 0x00b6 294#define mmDPPCLK_DTO_CTRL_BASE_IDX 1 295#define mmDCCG_VSYNC_CNT_CTRL 0x00b8 296#define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX 1 297#define mmDCCG_VSYNC_CNT_INT_CTRL 0x00b9 298#define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1 299#define mmFORCE_SYMCLK_DISABLE 0x00ba 300#define mmFORCE_SYMCLK_DISABLE_BASE_IDX 1 301#define mmPHYASYMCLK_CLOCK_CNTL 0x0052 302#define mmPHYASYMCLK_CLOCK_CNTL_BASE_IDX 2 303#define mmPHYBSYMCLK_CLOCK_CNTL 0x0053 304#define mmPHYBSYMCLK_CLOCK_CNTL_BASE_IDX 2 305#define mmPHYCSYMCLK_CLOCK_CNTL 0x0054 306#define mmPHYCSYMCLK_CLOCK_CNTL_BASE_IDX 2 307#define mmPHYDSYMCLK_CLOCK_CNTL 0x0055 308#define mmPHYDSYMCLK_CLOCK_CNTL_BASE_IDX 2 309#define mmPHYESYMCLK_CLOCK_CNTL 0x0056 310#define mmPHYESYMCLK_CLOCK_CNTL_BASE_IDX 2 311#define mmPHYFSYMCLK_CLOCK_CNTL 0x0057 312#define mmPHYFSYMCLK_CLOCK_CNTL_BASE_IDX 2 313 314 315// addressBlock: dce_dc_dccg_dccg_dfs_dispdec 316// base address: 0x0 317#define mmDENTIST_DISPCLK_CNTL 0x0064 318#define mmDENTIST_DISPCLK_CNTL_BASE_IDX 1 319 320 321// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec 322// base address: 0x0 323#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x0000 324#define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2 325#define mmDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001 326#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2 327#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x0002 328#define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2 329#define mmDC_PERFMON0_PERFMON_CNTL 0x0003 330#define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2 331#define mmDC_PERFMON0_PERFMON_CNTL2 0x0004 332#define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2 333#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005 334#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 335#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006 336#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2 337#define mmDC_PERFMON0_PERFMON_HI 0x0007 338#define mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2 339#define mmDC_PERFMON0_PERFMON_LOW 0x0008 340#define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2 341 342 343// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec 344// base address: 0x30 345#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x000c 346#define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2 347#define mmDC_PERFMON1_PERFCOUNTER_CNTL2 0x000d 348#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2 349#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x000e 350#define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2 351#define mmDC_PERFMON1_PERFMON_CNTL 0x000f 352#define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2 353#define mmDC_PERFMON1_PERFMON_CNTL2 0x0010 354#define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2 355#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x0011 356#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 357#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x0012 358#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2 359#define mmDC_PERFMON1_PERFMON_HI 0x0013 360#define mmDC_PERFMON1_PERFMON_HI_BASE_IDX 2 361#define mmDC_PERFMON1_PERFMON_LOW 0x0014 362#define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX 2 363 364 365// addressBlock: dce_dc_dmu_dc_pg_dispdec 366// base address: 0x0 367#define mmDOMAIN0_PG_CONFIG 0x0080 368#define mmDOMAIN0_PG_CONFIG_BASE_IDX 2 369#define mmDOMAIN0_PG_STATUS 0x0081 370#define mmDOMAIN0_PG_STATUS_BASE_IDX 2 371#define mmDOMAIN1_PG_CONFIG 0x0082 372#define mmDOMAIN1_PG_CONFIG_BASE_IDX 2 373#define mmDOMAIN1_PG_STATUS 0x0083 374#define mmDOMAIN1_PG_STATUS_BASE_IDX 2 375#define mmDOMAIN2_PG_CONFIG 0x0084 376#define mmDOMAIN2_PG_CONFIG_BASE_IDX 2 377#define mmDOMAIN2_PG_STATUS 0x0085 378#define mmDOMAIN2_PG_STATUS_BASE_IDX 2 379#define mmDOMAIN3_PG_CONFIG 0x0086 380#define mmDOMAIN3_PG_CONFIG_BASE_IDX 2 381#define mmDOMAIN3_PG_STATUS 0x0087 382#define mmDOMAIN3_PG_STATUS_BASE_IDX 2 383#define mmDOMAIN4_PG_CONFIG 0x0088 384#define mmDOMAIN4_PG_CONFIG_BASE_IDX 2 385#define mmDOMAIN4_PG_STATUS 0x0089 386#define mmDOMAIN4_PG_STATUS_BASE_IDX 2 387#define mmDOMAIN5_PG_CONFIG 0x008a 388#define mmDOMAIN5_PG_CONFIG_BASE_IDX 2 389#define mmDOMAIN5_PG_STATUS 0x008b 390#define mmDOMAIN5_PG_STATUS_BASE_IDX 2 391#define mmDOMAIN6_PG_CONFIG 0x008c 392#define mmDOMAIN6_PG_CONFIG_BASE_IDX 2 393#define mmDOMAIN6_PG_STATUS 0x008d 394#define mmDOMAIN6_PG_STATUS_BASE_IDX 2 395#define mmDOMAIN7_PG_CONFIG 0x008e 396#define mmDOMAIN7_PG_CONFIG_BASE_IDX 2 397#define mmDOMAIN7_PG_STATUS 0x008f 398#define mmDOMAIN7_PG_STATUS_BASE_IDX 2 399#define mmDOMAIN8_PG_CONFIG 0x0090 400#define mmDOMAIN8_PG_CONFIG_BASE_IDX 2 401#define mmDOMAIN8_PG_STATUS 0x0091 402#define mmDOMAIN8_PG_STATUS_BASE_IDX 2 403#define mmDOMAIN9_PG_CONFIG 0x0092 404#define mmDOMAIN9_PG_CONFIG_BASE_IDX 2 405#define mmDOMAIN9_PG_STATUS 0x0093 406#define mmDOMAIN9_PG_STATUS_BASE_IDX 2 407#define mmDOMAIN10_PG_CONFIG 0x0094 408#define mmDOMAIN10_PG_CONFIG_BASE_IDX 2 409#define mmDOMAIN10_PG_STATUS 0x0095 410#define mmDOMAIN10_PG_STATUS_BASE_IDX 2 411#define mmDOMAIN11_PG_CONFIG 0x0096 412#define mmDOMAIN11_PG_CONFIG_BASE_IDX 2 413#define mmDOMAIN11_PG_STATUS 0x0097 414#define mmDOMAIN11_PG_STATUS_BASE_IDX 2 415#define mmDOMAIN16_PG_CONFIG 0x00a1 416#define mmDOMAIN16_PG_CONFIG_BASE_IDX 2 417#define mmDOMAIN16_PG_STATUS 0x00a2 418#define mmDOMAIN16_PG_STATUS_BASE_IDX 2 419#define mmDOMAIN17_PG_CONFIG 0x00a3 420#define mmDOMAIN17_PG_CONFIG_BASE_IDX 2 421#define mmDOMAIN17_PG_STATUS 0x00a4 422#define mmDOMAIN17_PG_STATUS_BASE_IDX 2 423#define mmDOMAIN18_PG_CONFIG 0x00a5 424#define mmDOMAIN18_PG_CONFIG_BASE_IDX 2 425#define mmDOMAIN18_PG_STATUS 0x00a6 426#define mmDOMAIN18_PG_STATUS_BASE_IDX 2 427#define mmDOMAIN19_PG_CONFIG 0x00a7 428#define mmDOMAIN19_PG_CONFIG_BASE_IDX 2 429#define mmDOMAIN19_PG_STATUS 0x00a8 430#define mmDOMAIN19_PG_STATUS_BASE_IDX 2 431#define mmDOMAIN20_PG_CONFIG 0x00a9 432#define mmDOMAIN20_PG_CONFIG_BASE_IDX 2 433#define mmDOMAIN20_PG_STATUS 0x00aa 434#define mmDOMAIN20_PG_STATUS_BASE_IDX 2 435#define mmDOMAIN21_PG_CONFIG 0x00ab 436#define mmDOMAIN21_PG_CONFIG_BASE_IDX 2 437#define mmDOMAIN21_PG_STATUS 0x00ac 438#define mmDOMAIN21_PG_STATUS_BASE_IDX 2 439#define mmDCPG_INTERRUPT_STATUS 0x00ad 440#define mmDCPG_INTERRUPT_STATUS_BASE_IDX 2 441#define mmDCPG_INTERRUPT_STATUS_2 0x00ae 442#define mmDCPG_INTERRUPT_STATUS_2_BASE_IDX 2 443#define mmDCPG_INTERRUPT_CONTROL_1 0x00af 444#define mmDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2 445#define mmDCPG_INTERRUPT_CONTROL_2 0x00b0 446#define mmDCPG_INTERRUPT_CONTROL_2_BASE_IDX 2 447#define mmDCPG_INTERRUPT_CONTROL_3 0x00b1 448#define mmDCPG_INTERRUPT_CONTROL_3_BASE_IDX 2 449#define mmDC_IP_REQUEST_CNTL 0x00b2 450#define mmDC_IP_REQUEST_CNTL_BASE_IDX 2 451 452 453// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec 454// base address: 0x2f8 455#define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x00be 456#define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2 457#define mmDC_PERFMON2_PERFCOUNTER_CNTL2 0x00bf 458#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2 459#define mmDC_PERFMON2_PERFCOUNTER_STATE 0x00c0 460#define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2 461#define mmDC_PERFMON2_PERFMON_CNTL 0x00c1 462#define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2 463#define mmDC_PERFMON2_PERFMON_CNTL2 0x00c2 464#define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2 465#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x00c3 466#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 467#define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x00c4 468#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2 469#define mmDC_PERFMON2_PERFMON_HI 0x00c5 470#define mmDC_PERFMON2_PERFMON_HI_BASE_IDX 2 471#define mmDC_PERFMON2_PERFMON_LOW 0x00c6 472#define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX 2 473 474 475// addressBlock: dce_dc_dmu_dmu_misc_dispdec 476// base address: 0x0 477#define mmCC_DC_PIPE_DIS 0x00ca 478#define mmCC_DC_PIPE_DIS_BASE_IDX 2 479#define mmDMU_CLK_CNTL 0x00cb 480#define mmDMU_CLK_CNTL_BASE_IDX 2 481#define mmDMU_MEM_PWR_CNTL 0x00cc 482#define mmDMU_MEM_PWR_CNTL_BASE_IDX 2 483#define mmDMCU_SMU_INTERRUPT_CNTL 0x00cd 484#define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 2 485#define mmSMU_INTERRUPT_CONTROL 0x00ce 486#define mmSMU_INTERRUPT_CONTROL_BASE_IDX 2 487#define mmDMU_MISC_ALLOW_DS_FORCE 0x00d6 488#define mmDMU_MISC_ALLOW_DS_FORCE_BASE_IDX 2 489 490 491// addressBlock: dce_dc_dmu_dmcu_dispdec 492// base address: 0x0 493#define mmDMCU_CTRL 0x00da 494#define mmDMCU_CTRL_BASE_IDX 2 495#define mmDMCU_STATUS 0x00db 496#define mmDMCU_STATUS_BASE_IDX 2 497#define mmDMCU_PC_START_ADDR 0x00dc 498#define mmDMCU_PC_START_ADDR_BASE_IDX 2 499#define mmDMCU_FW_START_ADDR 0x00dd 500#define mmDMCU_FW_START_ADDR_BASE_IDX 2 501#define mmDMCU_FW_END_ADDR 0x00de 502#define mmDMCU_FW_END_ADDR_BASE_IDX 2 503#define mmDMCU_FW_ISR_START_ADDR 0x00df 504#define mmDMCU_FW_ISR_START_ADDR_BASE_IDX 2 505#define mmDMCU_FW_CS_HI 0x00e0 506#define mmDMCU_FW_CS_HI_BASE_IDX 2 507#define mmDMCU_FW_CS_LO 0x00e1 508#define mmDMCU_FW_CS_LO_BASE_IDX 2 509#define mmDMCU_RAM_ACCESS_CTRL 0x00e2 510#define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX 2 511#define mmDMCU_ERAM_WR_CTRL 0x00e3 512#define mmDMCU_ERAM_WR_CTRL_BASE_IDX 2 513#define mmDMCU_ERAM_WR_DATA 0x00e4 514#define mmDMCU_ERAM_WR_DATA_BASE_IDX 2 515#define mmDMCU_ERAM_RD_CTRL 0x00e5 516#define mmDMCU_ERAM_RD_CTRL_BASE_IDX 2 517#define mmDMCU_ERAM_RD_DATA 0x00e6 518#define mmDMCU_ERAM_RD_DATA_BASE_IDX 2 519#define mmDMCU_IRAM_WR_CTRL 0x00e7 520#define mmDMCU_IRAM_WR_CTRL_BASE_IDX 2 521#define mmDMCU_IRAM_WR_DATA 0x00e8 522#define mmDMCU_IRAM_WR_DATA_BASE_IDX 2 523#define mmDMCU_IRAM_RD_CTRL 0x00e9 524#define mmDMCU_IRAM_RD_CTRL_BASE_IDX 2 525#define mmDMCU_IRAM_RD_DATA 0x00ea 526#define mmDMCU_IRAM_RD_DATA_BASE_IDX 2 527#define mmDMCU_EVENT_TRIGGER 0x00eb 528#define mmDMCU_EVENT_TRIGGER_BASE_IDX 2 529#define mmDMCU_UC_INTERNAL_INT_STATUS 0x00ec 530#define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2 531#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x00ed 532#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2 533#define mmDMCU_INTERRUPT_STATUS 0x00ee 534#define mmDMCU_INTERRUPT_STATUS_BASE_IDX 2 535#define mmDMCU_INTERRUPT_STATUS_1 0x00ef 536#define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX 2 537#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x00f0 538#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2 539#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x00f1 540#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2 541#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x00f2 542#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2 543#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x00f3 544#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2 545#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x00f4 546#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2 547#define mmDC_DMCU_SCRATCH 0x00f5 548#define mmDC_DMCU_SCRATCH_BASE_IDX 2 549#define mmDMCU_INT_CNT 0x00f6 550#define mmDMCU_INT_CNT_BASE_IDX 2 551#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x00f7 552#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2 553#define mmDMCU_UC_CLK_GATING_CNTL 0x00f8 554#define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2 555#define mmMASTER_COMM_DATA_REG1 0x00f9 556#define mmMASTER_COMM_DATA_REG1_BASE_IDX 2 557#define mmMASTER_COMM_DATA_REG2 0x00fa 558#define mmMASTER_COMM_DATA_REG2_BASE_IDX 2 559#define mmMASTER_COMM_DATA_REG3 0x00fb 560#define mmMASTER_COMM_DATA_REG3_BASE_IDX 2 561#define mmMASTER_COMM_CMD_REG 0x00fc 562#define mmMASTER_COMM_CMD_REG_BASE_IDX 2 563#define mmMASTER_COMM_CNTL_REG 0x00fd 564#define mmMASTER_COMM_CNTL_REG_BASE_IDX 2 565#define mmSLAVE_COMM_DATA_REG1 0x00fe 566#define mmSLAVE_COMM_DATA_REG1_BASE_IDX 2 567#define mmSLAVE_COMM_DATA_REG2 0x00ff 568#define mmSLAVE_COMM_DATA_REG2_BASE_IDX 2 569#define mmSLAVE_COMM_DATA_REG3 0x0100 570#define mmSLAVE_COMM_DATA_REG3_BASE_IDX 2 571#define mmSLAVE_COMM_CMD_REG 0x0101 572#define mmSLAVE_COMM_CMD_REG_BASE_IDX 2 573#define mmSLAVE_COMM_CNTL_REG 0x0102 574#define mmSLAVE_COMM_CNTL_REG_BASE_IDX 2 575#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x0105 576#define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2 577#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x0106 578#define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2 579#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x0107 580#define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2 581#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x0108 582#define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2 583#define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x0109 584#define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2 585#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x010a 586#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 587#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x010b 588#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2 589#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x010c 590#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2 591#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x010d 592#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2 593#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x010e 594#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2 595#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x010f 596#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 597#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x0110 598#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2 599#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0111 600#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2 601#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0112 602#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2 603#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0113 604#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2 605#define mmDMCU_DPRX_INTERRUPT_STATUS1 0x0114 606#define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2 607#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x0115 608#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 609#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x0116 610#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 611#define mmDMCU_INTERRUPT_STATUS_CONTINUE 0x0119 612#define mmDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 613#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE 0x011a 614#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX 2 615#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE 0x011b 616#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX 2 617#define mmDMCU_INT_CNT_CONTINUE 0x011c 618#define mmDMCU_INT_CNT_CONTINUE_BASE_IDX 2 619#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2 0x011d 620#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2_BASE_IDX 2 621#define mmDMCU_INTERRUPT_STATUS_2 0x011e 622#define mmDMCU_INTERRUPT_STATUS_2_BASE_IDX 2 623#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2 0x011f 624#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2_BASE_IDX 2 625#define mmDMCU_INT_CNT_CONT2 0x0120 626#define mmDMCU_INT_CNT_CONT2_BASE_IDX 2 627#define mmDMCU_INT_CNT_CONT3 0x0121 628#define mmDMCU_INT_CNT_CONT3_BASE_IDX 2 629#define mmDMCU_INT_CNT_CONT4 0x0122 630#define mmDMCU_INT_CNT_CONT4_BASE_IDX 2 631#define mmDMCU_INT_CNT_CONT5 0x0123 632#define mmDMCU_INT_CNT_CONT5_BASE_IDX 2 633 634 635// addressBlock: dce_dc_dmu_ihc_dispdec 636// base address: 0x0 637#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126 638#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2 639#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127 640#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2 641#define mmDC_GPU_TIMER_READ 0x0128 642#define mmDC_GPU_TIMER_READ_BASE_IDX 2 643#define mmDC_GPU_TIMER_READ_CNTL 0x0129 644#define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX 2 645#define mmDISP_INTERRUPT_STATUS 0x012a 646#define mmDISP_INTERRUPT_STATUS_BASE_IDX 2 647#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x012b 648#define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 649#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x012c 650#define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2 651#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x012d 652#define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2 653#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x012e 654#define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2 655#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x012f 656#define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2 657#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x0130 658#define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2 659#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x0131 660#define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2 661#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x0132 662#define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2 663#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x0133 664#define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2 665#define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x0134 666#define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2 667#define mmDISP_INTERRUPT_STATUS_CONTINUE11 0x0135 668#define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2 669#define mmDISP_INTERRUPT_STATUS_CONTINUE12 0x0136 670#define mmDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2 671#define mmDISP_INTERRUPT_STATUS_CONTINUE13 0x0137 672#define mmDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2 673#define mmDISP_INTERRUPT_STATUS_CONTINUE14 0x0138 674#define mmDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2 675#define mmDISP_INTERRUPT_STATUS_CONTINUE15 0x0139 676#define mmDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2 677#define mmDISP_INTERRUPT_STATUS_CONTINUE16 0x013a 678#define mmDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2 679#define mmDISP_INTERRUPT_STATUS_CONTINUE17 0x013b 680#define mmDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2 681#define mmDISP_INTERRUPT_STATUS_CONTINUE18 0x013c 682#define mmDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2 683#define mmDISP_INTERRUPT_STATUS_CONTINUE19 0x013d 684#define mmDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2 685#define mmDISP_INTERRUPT_STATUS_CONTINUE20 0x013e 686#define mmDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2 687#define mmDISP_INTERRUPT_STATUS_CONTINUE21 0x013f 688#define mmDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2 689#define mmDISP_INTERRUPT_STATUS_CONTINUE22 0x0140 690#define mmDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2 691#define mmDC_GPU_TIMER_START_POSITION_VREADY 0x0141 692#define mmDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2 693#define mmDC_GPU_TIMER_START_POSITION_FLIP 0x0142 694#define mmDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2 695#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143 696#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2 697#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144 698#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2 699#define mmDISP_INTERRUPT_STATUS_CONTINUE23 0x0145 700#define mmDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX 2 701#define mmDISP_INTERRUPT_STATUS_CONTINUE24 0x0146 702#define mmDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX 2 703#define mmDISP_INTERRUPT_STATUS_CONTINUE25 0x0147 704#define mmDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX 2 705#define mmDCCG_INTERRUPT_DEST 0x0148 706#define mmDCCG_INTERRUPT_DEST_BASE_IDX 2 707#define mmDMU_INTERRUPT_DEST 0x0149 708#define mmDMU_INTERRUPT_DEST_BASE_IDX 2 709#define mmDMU_INTERRUPT_DEST2 0x014a 710#define mmDMU_INTERRUPT_DEST2_BASE_IDX 2 711#define mmDCPG_INTERRUPT_DEST 0x014b 712#define mmDCPG_INTERRUPT_DEST_BASE_IDX 2 713#define mmDCPG_INTERRUPT_DEST2 0x014c 714#define mmDCPG_INTERRUPT_DEST2_BASE_IDX 2 715#define mmMMHUBBUB_INTERRUPT_DEST 0x014d 716#define mmMMHUBBUB_INTERRUPT_DEST_BASE_IDX 2 717#define mmWB_INTERRUPT_DEST 0x014e 718#define mmWB_INTERRUPT_DEST_BASE_IDX 2 719#define mmDCHUB_INTERRUPT_DEST 0x014f 720#define mmDCHUB_INTERRUPT_DEST_BASE_IDX 2 721#define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST 0x0150 722#define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 723#define mmDCHUB_INTERRUPT_DEST2 0x0151 724#define mmDCHUB_INTERRUPT_DEST2_BASE_IDX 2 725#define mmDPP_PERFCOUNTER_INTERRUPT_DEST 0x0152 726#define mmDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 727#define mmMPC_INTERRUPT_DEST 0x0153 728#define mmMPC_INTERRUPT_DEST_BASE_IDX 2 729#define mmOPP_INTERRUPT_DEST 0x0154 730#define mmOPP_INTERRUPT_DEST_BASE_IDX 2 731#define mmOPTC_INTERRUPT_DEST 0x0155 732#define mmOPTC_INTERRUPT_DEST_BASE_IDX 2 733#define mmOTG0_INTERRUPT_DEST 0x0156 734#define mmOTG0_INTERRUPT_DEST_BASE_IDX 2 735#define mmOTG1_INTERRUPT_DEST 0x0157 736#define mmOTG1_INTERRUPT_DEST_BASE_IDX 2 737#define mmOTG2_INTERRUPT_DEST 0x0158 738#define mmOTG2_INTERRUPT_DEST_BASE_IDX 2 739#define mmOTG3_INTERRUPT_DEST 0x0159 740#define mmOTG3_INTERRUPT_DEST_BASE_IDX 2 741#define mmOTG4_INTERRUPT_DEST 0x015a 742#define mmOTG4_INTERRUPT_DEST_BASE_IDX 2 743#define mmOTG5_INTERRUPT_DEST 0x015b 744#define mmOTG5_INTERRUPT_DEST_BASE_IDX 2 745#define mmDIG_INTERRUPT_DEST 0x015c 746#define mmDIG_INTERRUPT_DEST_BASE_IDX 2 747#define mmI2C_DDC_HPD_INTERRUPT_DEST 0x015d 748#define mmI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX 2 749#define mmDIO_INTERRUPT_DEST 0x015f 750#define mmDIO_INTERRUPT_DEST_BASE_IDX 2 751#define mmDCIO_INTERRUPT_DEST 0x0160 752#define mmDCIO_INTERRUPT_DEST_BASE_IDX 2 753#define mmHPD_INTERRUPT_DEST 0x0161 754#define mmHPD_INTERRUPT_DEST_BASE_IDX 2 755#define mmAZ_INTERRUPT_DEST 0x0162 756#define mmAZ_INTERRUPT_DEST_BASE_IDX 2 757#define mmAUX_INTERRUPT_DEST 0x0163 758#define mmAUX_INTERRUPT_DEST_BASE_IDX 2 759#define mmDSC_INTERRUPT_DEST 0x0164 760#define mmDSC_INTERRUPT_DEST_BASE_IDX 2 761 762 763// addressBlock: dce_dc_dmu_fgsec_dispdec 764// base address: 0x0 765#define mmDMCUB_RBBMIF_SEC_CNTL 0x017a 766#define mmDMCUB_RBBMIF_SEC_CNTL_BASE_IDX 2 767 768 769// addressBlock: dce_dc_dmu_rbbmif_dispdec 770// base address: 0x0 771#define mmRBBMIF_TIMEOUT 0x017f 772#define mmRBBMIF_TIMEOUT_BASE_IDX 2 773#define mmRBBMIF_STATUS 0x0180 774#define mmRBBMIF_STATUS_BASE_IDX 2 775#define mmRBBMIF_STATUS_2 0x0181 776#define mmRBBMIF_STATUS_2_BASE_IDX 2 777#define mmRBBMIF_INT_STATUS 0x0182 778#define mmRBBMIF_INT_STATUS_BASE_IDX 2 779#define mmRBBMIF_TIMEOUT_DIS 0x0183 780#define mmRBBMIF_TIMEOUT_DIS_BASE_IDX 2 781#define mmRBBMIF_TIMEOUT_DIS_2 0x0184 782#define mmRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2 783#define mmRBBMIF_STATUS_FLAG 0x0185 784#define mmRBBMIF_STATUS_FLAG_BASE_IDX 2 785 786 787// addressBlock: dce_dc_dmu_dmcub_dispdec 788// base address: 0x0 789#define mmDMCUB_REGION0_OFFSET 0x018e 790#define mmDMCUB_REGION0_OFFSET_BASE_IDX 2 791#define mmDMCUB_REGION0_OFFSET_HIGH 0x018f 792#define mmDMCUB_REGION0_OFFSET_HIGH_BASE_IDX 2 793#define mmDMCUB_REGION1_OFFSET 0x0190 794#define mmDMCUB_REGION1_OFFSET_BASE_IDX 2 795#define mmDMCUB_REGION1_OFFSET_HIGH 0x0191 796#define mmDMCUB_REGION1_OFFSET_HIGH_BASE_IDX 2 797#define mmDMCUB_REGION2_OFFSET 0x0192 798#define mmDMCUB_REGION2_OFFSET_BASE_IDX 2 799#define mmDMCUB_REGION2_OFFSET_HIGH 0x0193 800#define mmDMCUB_REGION2_OFFSET_HIGH_BASE_IDX 2 801#define mmDMCUB_REGION4_OFFSET 0x0196 802#define mmDMCUB_REGION4_OFFSET_BASE_IDX 2 803#define mmDMCUB_REGION4_OFFSET_HIGH 0x0197 804#define mmDMCUB_REGION4_OFFSET_HIGH_BASE_IDX 2 805#define mmDMCUB_REGION5_OFFSET 0x0198 806#define mmDMCUB_REGION5_OFFSET_BASE_IDX 2 807#define mmDMCUB_REGION5_OFFSET_HIGH 0x0199 808#define mmDMCUB_REGION5_OFFSET_HIGH_BASE_IDX 2 809#define mmDMCUB_REGION6_OFFSET 0x019a 810#define mmDMCUB_REGION6_OFFSET_BASE_IDX 2 811#define mmDMCUB_REGION6_OFFSET_HIGH 0x019b 812#define mmDMCUB_REGION6_OFFSET_HIGH_BASE_IDX 2 813#define mmDMCUB_REGION7_OFFSET 0x019c 814#define mmDMCUB_REGION7_OFFSET_BASE_IDX 2 815#define mmDMCUB_REGION7_OFFSET_HIGH 0x019d 816#define mmDMCUB_REGION7_OFFSET_HIGH_BASE_IDX 2 817#define mmDMCUB_REGION0_TOP_ADDRESS 0x019e 818#define mmDMCUB_REGION0_TOP_ADDRESS_BASE_IDX 2 819#define mmDMCUB_REGION1_TOP_ADDRESS 0x019f 820#define mmDMCUB_REGION1_TOP_ADDRESS_BASE_IDX 2 821#define mmDMCUB_REGION2_TOP_ADDRESS 0x01a0 822#define mmDMCUB_REGION2_TOP_ADDRESS_BASE_IDX 2 823#define mmDMCUB_REGION4_TOP_ADDRESS 0x01a1 824#define mmDMCUB_REGION4_TOP_ADDRESS_BASE_IDX 2 825#define mmDMCUB_REGION5_TOP_ADDRESS 0x01a2 826#define mmDMCUB_REGION5_TOP_ADDRESS_BASE_IDX 2 827#define mmDMCUB_REGION6_TOP_ADDRESS 0x01a3 828#define mmDMCUB_REGION6_TOP_ADDRESS_BASE_IDX 2 829#define mmDMCUB_REGION7_TOP_ADDRESS 0x01a4 830#define mmDMCUB_REGION7_TOP_ADDRESS_BASE_IDX 2 831#define mmDMCUB_REGION3_CW0_BASE_ADDRESS 0x01a5 832#define mmDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX 2 833#define mmDMCUB_REGION3_CW1_BASE_ADDRESS 0x01a6 834#define mmDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX 2 835#define mmDMCUB_REGION3_CW2_BASE_ADDRESS 0x01a7 836#define mmDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX 2 837#define mmDMCUB_REGION3_CW3_BASE_ADDRESS 0x01a8 838#define mmDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX 2 839#define mmDMCUB_REGION3_CW4_BASE_ADDRESS 0x01a9 840#define mmDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX 2 841#define mmDMCUB_REGION3_CW5_BASE_ADDRESS 0x01aa 842#define mmDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX 2 843#define mmDMCUB_REGION3_CW6_BASE_ADDRESS 0x01ab 844#define mmDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX 2 845#define mmDMCUB_REGION3_CW7_BASE_ADDRESS 0x01ac 846#define mmDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX 2 847#define mmDMCUB_REGION3_CW0_TOP_ADDRESS 0x01ad 848#define mmDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX 2 849#define mmDMCUB_REGION3_CW1_TOP_ADDRESS 0x01ae 850#define mmDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX 2 851#define mmDMCUB_REGION3_CW2_TOP_ADDRESS 0x01af 852#define mmDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX 2 853#define mmDMCUB_REGION3_CW3_TOP_ADDRESS 0x01b0 854#define mmDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX 2 855#define mmDMCUB_REGION3_CW4_TOP_ADDRESS 0x01b1 856#define mmDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX 2 857#define mmDMCUB_REGION3_CW5_TOP_ADDRESS 0x01b2 858#define mmDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX 2 859#define mmDMCUB_REGION3_CW6_TOP_ADDRESS 0x01b3 860#define mmDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX 2 861#define mmDMCUB_REGION3_CW7_TOP_ADDRESS 0x01b4 862#define mmDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX 2 863#define mmDMCUB_REGION3_CW0_OFFSET 0x01b5 864#define mmDMCUB_REGION3_CW0_OFFSET_BASE_IDX 2 865#define mmDMCUB_REGION3_CW0_OFFSET_HIGH 0x01b6 866#define mmDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX 2 867#define mmDMCUB_REGION3_CW1_OFFSET 0x01b7 868#define mmDMCUB_REGION3_CW1_OFFSET_BASE_IDX 2 869#define mmDMCUB_REGION3_CW1_OFFSET_HIGH 0x01b8 870#define mmDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX 2 871#define mmDMCUB_REGION3_CW2_OFFSET 0x01b9 872#define mmDMCUB_REGION3_CW2_OFFSET_BASE_IDX 2 873#define mmDMCUB_REGION3_CW2_OFFSET_HIGH 0x01ba 874#define mmDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX 2 875#define mmDMCUB_REGION3_CW3_OFFSET 0x01bb 876#define mmDMCUB_REGION3_CW3_OFFSET_BASE_IDX 2 877#define mmDMCUB_REGION3_CW3_OFFSET_HIGH 0x01bc 878#define mmDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX 2 879#define mmDMCUB_REGION3_CW4_OFFSET 0x01bd 880#define mmDMCUB_REGION3_CW4_OFFSET_BASE_IDX 2 881#define mmDMCUB_REGION3_CW4_OFFSET_HIGH 0x01be 882#define mmDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX 2 883#define mmDMCUB_REGION3_CW5_OFFSET 0x01bf 884#define mmDMCUB_REGION3_CW5_OFFSET_BASE_IDX 2 885#define mmDMCUB_REGION3_CW5_OFFSET_HIGH 0x01c0 886#define mmDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX 2 887#define mmDMCUB_REGION3_CW6_OFFSET 0x01c1 888#define mmDMCUB_REGION3_CW6_OFFSET_BASE_IDX 2 889#define mmDMCUB_REGION3_CW6_OFFSET_HIGH 0x01c2 890#define mmDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX 2 891#define mmDMCUB_REGION3_CW7_OFFSET 0x01c3 892#define mmDMCUB_REGION3_CW7_OFFSET_BASE_IDX 2 893#define mmDMCUB_REGION3_CW7_OFFSET_HIGH 0x01c4 894#define mmDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX 2 895#define mmDMCUB_INTERRUPT_ENABLE 0x01c5 896#define mmDMCUB_INTERRUPT_ENABLE_BASE_IDX 2 897#define mmDMCUB_INTERRUPT_ACK 0x01c6 898#define mmDMCUB_INTERRUPT_ACK_BASE_IDX 2 899#define mmDMCUB_INTERRUPT_STATUS 0x01c7 900#define mmDMCUB_INTERRUPT_STATUS_BASE_IDX 2 901#define mmDMCUB_INTERRUPT_TYPE 0x01c8 902#define mmDMCUB_INTERRUPT_TYPE_BASE_IDX 2 903#define mmDMCUB_EXT_INTERRUPT_STATUS 0x01c9 904#define mmDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX 2 905#define mmDMCUB_EXT_INTERRUPT_CTXID 0x01ca 906#define mmDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX 2 907#define mmDMCUB_EXT_INTERRUPT_ACK 0x01cb 908#define mmDMCUB_EXT_INTERRUPT_ACK_BASE_IDX 2 909#define mmDMCUB_INST_FETCH_FAULT_ADDR 0x01cc 910#define mmDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX 2 911#define mmDMCUB_DATA_WRITE_FAULT_ADDR 0x01cd 912#define mmDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX 2 913#define mmDMCUB_SEC_CNTL 0x01ce 914#define mmDMCUB_SEC_CNTL_BASE_IDX 2 915#define mmDMCUB_MEM_CNTL 0x01cf 916#define mmDMCUB_MEM_CNTL_BASE_IDX 2 917#define mmDMCUB_INBOX0_BASE_ADDRESS 0x01d0 918#define mmDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX 2 919#define mmDMCUB_INBOX0_SIZE 0x01d1 920#define mmDMCUB_INBOX0_SIZE_BASE_IDX 2 921#define mmDMCUB_INBOX0_WPTR 0x01d2 922#define mmDMCUB_INBOX0_WPTR_BASE_IDX 2 923#define mmDMCUB_INBOX0_RPTR 0x01d3 924#define mmDMCUB_INBOX0_RPTR_BASE_IDX 2 925#define mmDMCUB_INBOX1_BASE_ADDRESS 0x01d4 926#define mmDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX 2 927#define mmDMCUB_INBOX1_SIZE 0x01d5 928#define mmDMCUB_INBOX1_SIZE_BASE_IDX 2 929#define mmDMCUB_INBOX1_WPTR 0x01d6 930#define mmDMCUB_INBOX1_WPTR_BASE_IDX 2 931#define mmDMCUB_INBOX1_RPTR 0x01d7 932#define mmDMCUB_INBOX1_RPTR_BASE_IDX 2 933#define mmDMCUB_OUTBOX0_BASE_ADDRESS 0x01d8 934#define mmDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX 2 935#define mmDMCUB_OUTBOX0_SIZE 0x01d9 936#define mmDMCUB_OUTBOX0_SIZE_BASE_IDX 2 937#define mmDMCUB_OUTBOX0_WPTR 0x01da 938#define mmDMCUB_OUTBOX0_WPTR_BASE_IDX 2 939#define mmDMCUB_OUTBOX0_RPTR 0x01db 940#define mmDMCUB_OUTBOX0_RPTR_BASE_IDX 2 941#define mmDMCUB_OUTBOX1_BASE_ADDRESS 0x01dc 942#define mmDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX 2 943#define mmDMCUB_OUTBOX1_SIZE 0x01dd 944#define mmDMCUB_OUTBOX1_SIZE_BASE_IDX 2 945#define mmDMCUB_OUTBOX1_WPTR 0x01de 946#define mmDMCUB_OUTBOX1_WPTR_BASE_IDX 2 947#define mmDMCUB_OUTBOX1_RPTR 0x01df 948#define mmDMCUB_OUTBOX1_RPTR_BASE_IDX 2 949#define mmDMCUB_TIMER_TRIGGER0 0x01e0 950#define mmDMCUB_TIMER_TRIGGER0_BASE_IDX 2 951#define mmDMCUB_TIMER_TRIGGER1 0x01e1 952#define mmDMCUB_TIMER_TRIGGER1_BASE_IDX 2 953#define mmDMCUB_TIMER_WINDOW 0x01e2 954#define mmDMCUB_TIMER_WINDOW_BASE_IDX 2 955#define mmDMCUB_SCRATCH0 0x01e3 956#define mmDMCUB_SCRATCH0_BASE_IDX 2 957#define mmDMCUB_SCRATCH1 0x01e4 958#define mmDMCUB_SCRATCH1_BASE_IDX 2 959#define mmDMCUB_SCRATCH2 0x01e5 960#define mmDMCUB_SCRATCH2_BASE_IDX 2 961#define mmDMCUB_SCRATCH3 0x01e6 962#define mmDMCUB_SCRATCH3_BASE_IDX 2 963#define mmDMCUB_SCRATCH4 0x01e7 964#define mmDMCUB_SCRATCH4_BASE_IDX 2 965#define mmDMCUB_SCRATCH5 0x01e8 966#define mmDMCUB_SCRATCH5_BASE_IDX 2 967#define mmDMCUB_SCRATCH6 0x01e9 968#define mmDMCUB_SCRATCH6_BASE_IDX 2 969#define mmDMCUB_SCRATCH7 0x01ea 970#define mmDMCUB_SCRATCH7_BASE_IDX 2 971#define mmDMCUB_SCRATCH8 0x01eb 972#define mmDMCUB_SCRATCH8_BASE_IDX 2 973#define mmDMCUB_SCRATCH9 0x01ec 974#define mmDMCUB_SCRATCH9_BASE_IDX 2 975#define mmDMCUB_SCRATCH10 0x01ed 976#define mmDMCUB_SCRATCH10_BASE_IDX 2 977#define mmDMCUB_SCRATCH11 0x01ee 978#define mmDMCUB_SCRATCH11_BASE_IDX 2 979#define mmDMCUB_SCRATCH12 0x01ef 980#define mmDMCUB_SCRATCH12_BASE_IDX 2 981#define mmDMCUB_SCRATCH13 0x01f0 982#define mmDMCUB_SCRATCH13_BASE_IDX 2 983#define mmDMCUB_SCRATCH14 0x01f1 984#define mmDMCUB_SCRATCH14_BASE_IDX 2 985#define mmDMCUB_SCRATCH15 0x01f2 986#define mmDMCUB_SCRATCH15_BASE_IDX 2 987#define mmDMCUB_CNTL 0x01f6 988#define mmDMCUB_CNTL_BASE_IDX 2 989#define mmDMCUB_GPINT_DATAIN0 0x01f7 990#define mmDMCUB_GPINT_DATAIN0_BASE_IDX 2 991#define mmDMCUB_GPINT_DATAIN1 0x01f8 992#define mmDMCUB_GPINT_DATAIN1_BASE_IDX 2 993#define mmDMCUB_GPINT_DATAOUT 0x01f9 994#define mmDMCUB_GPINT_DATAOUT_BASE_IDX 2 995#define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0x01fa 996#define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX 2 997#define mmDMCUB_LS_WAKE_INT_ENABLE 0x01fb 998#define mmDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX 2 999#define mmDMCUB_MEM_PWR_CNTL 0x01fc 1000#define mmDMCUB_MEM_PWR_CNTL_BASE_IDX 2
1001#define mmDMCUB_TIMER_CURRENT 0x01fd 1002#define mmDMCUB_TIMER_CURRENT_BASE_IDX 2 1003#define mmDMCUB_PROC_ID 0x01ff 1004#define mmDMCUB_PROC_ID_BASE_IDX 2 1005 1006 1007// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec 1008// base address: 0x0 1009#define mmMCIF_WB_BUFMGR_SW_CONTROL 0x0272 1010#define mmMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 1011#define mmMCIF_WB_BUFMGR_STATUS 0x0274 1012#define mmMCIF_WB_BUFMGR_STATUS_BASE_IDX 2 1013#define mmMCIF_WB_BUF_PITCH 0x0275 1014#define mmMCIF_WB_BUF_PITCH_BASE_IDX 2 1015#define mmMCIF_WB_BUF_1_STATUS 0x0276 1016#define mmMCIF_WB_BUF_1_STATUS_BASE_IDX 2 1017#define mmMCIF_WB_BUF_1_STATUS2 0x0277 1018#define mmMCIF_WB_BUF_1_STATUS2_BASE_IDX 2 1019#define mmMCIF_WB_BUF_2_STATUS 0x0278 1020#define mmMCIF_WB_BUF_2_STATUS_BASE_IDX 2 1021#define mmMCIF_WB_BUF_2_STATUS2 0x0279 1022#define mmMCIF_WB_BUF_2_STATUS2_BASE_IDX 2 1023#define mmMCIF_WB_BUF_3_STATUS 0x027a 1024#define mmMCIF_WB_BUF_3_STATUS_BASE_IDX 2 1025#define mmMCIF_WB_BUF_3_STATUS2 0x027b 1026#define mmMCIF_WB_BUF_3_STATUS2_BASE_IDX 2 1027#define mmMCIF_WB_BUF_4_STATUS 0x027c 1028#define mmMCIF_WB_BUF_4_STATUS_BASE_IDX 2 1029#define mmMCIF_WB_BUF_4_STATUS2 0x027d 1030#define mmMCIF_WB_BUF_4_STATUS2_BASE_IDX 2 1031#define mmMCIF_WB_ARBITRATION_CONTROL 0x027e 1032#define mmMCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 1033#define mmMCIF_WB_SCLK_CHANGE 0x027f 1034#define mmMCIF_WB_SCLK_CHANGE_BASE_IDX 2 1035#define mmMCIF_WB_BUF_1_ADDR_Y 0x0282 1036#define mmMCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 1037#define mmMCIF_WB_BUF_1_ADDR_C 0x0284 1038#define mmMCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 1039#define mmMCIF_WB_BUF_2_ADDR_Y 0x0286 1040#define mmMCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 1041#define mmMCIF_WB_BUF_2_ADDR_C 0x0288 1042#define mmMCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 1043#define mmMCIF_WB_BUF_3_ADDR_Y 0x028a 1044#define mmMCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 1045#define mmMCIF_WB_BUF_3_ADDR_C 0x028c 1046#define mmMCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 1047#define mmMCIF_WB_BUF_4_ADDR_Y 0x028e 1048#define mmMCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 1049#define mmMCIF_WB_BUF_4_ADDR_C 0x0290 1050#define mmMCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 1051#define mmMCIF_WB_BUFMGR_VCE_CONTROL 0x0292 1052#define mmMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 1053#define mmMCIF_WB_NB_PSTATE_CONTROL 0x0293 1054#define mmMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 1055#define mmMCIF_WB_CLOCK_GATER_CONTROL 0x0294 1056#define mmMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 1057#define mmMCIF_WB_SELF_REFRESH_CONTROL 0x0296 1058#define mmMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 1059#define mmMULTI_LEVEL_QOS_CTRL 0x0297 1060#define mmMULTI_LEVEL_QOS_CTRL_BASE_IDX 2 1061#define mmMCIF_WB_BUF_LUMA_SIZE 0x0299 1062#define mmMCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 1063#define mmMCIF_WB_BUF_CHROMA_SIZE 0x029a 1064#define mmMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 1065#define mmMCIF_WB_BUF_1_ADDR_Y_HIGH 0x029b 1066#define mmMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2 1067#define mmMCIF_WB_BUF_1_ADDR_C_HIGH 0x029c 1068#define mmMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2 1069#define mmMCIF_WB_BUF_2_ADDR_Y_HIGH 0x029d 1070#define mmMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2 1071#define mmMCIF_WB_BUF_2_ADDR_C_HIGH 0x029e 1072#define mmMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2 1073#define mmMCIF_WB_BUF_3_ADDR_Y_HIGH 0x029f 1074#define mmMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2 1075#define mmMCIF_WB_BUF_3_ADDR_C_HIGH 0x02a0 1076#define mmMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2 1077#define mmMCIF_WB_BUF_4_ADDR_Y_HIGH 0x02a1 1078#define mmMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2 1079#define mmMCIF_WB_BUF_4_ADDR_C_HIGH 0x02a2 1080#define mmMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2 1081#define mmMCIF_WB_BUF_1_RESOLUTION 0x02a3 1082#define mmMCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2 1083#define mmMCIF_WB_BUF_2_RESOLUTION 0x02a4 1084#define mmMCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2 1085#define mmMCIF_WB_BUF_3_RESOLUTION 0x02a5 1086#define mmMCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2 1087#define mmMCIF_WB_BUF_4_RESOLUTION 0x02a6 1088#define mmMCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2 1089#define mmMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI 0x02a7 1090#define mmMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI_BASE_IDX 2 1091#define mmMCIF_WB_VMID_CONTROL 0x02a8 1092#define mmMCIF_WB_VMID_CONTROL_BASE_IDX 2 1093#define mmMCIF_WB_MIN_TTO 0x02a9 1094#define mmMCIF_WB_MIN_TTO_BASE_IDX 2 1095 1096 1097// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec 1098// base address: 0x0 1099#define mmMCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02aa 1100#define mmMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 1101#define mmMCIF_WB_WATERMARK 0x02ab 1102#define mmMCIF_WB_WATERMARK_BASE_IDX 2 1103#define mmMMHUBBUB_WARMUP_CONFIG 0x02ac 1104#define mmMMHUBBUB_WARMUP_CONFIG_BASE_IDX 2 1105#define mmMMHUBBUB_WARMUP_CONTROL_STATUS 0x02ad 1106#define mmMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX 2 1107#define mmMMHUBBUB_WARMUP_BASE_ADDR_LOW 0x02ae 1108#define mmMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX 2 1109#define mmMMHUBBUB_WARMUP_BASE_ADDR_HIGH 0x02af 1110#define mmMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX 2 1111#define mmMMHUBBUB_WARMUP_ADDR_REGION 0x02b0 1112#define mmMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX 2 1113#define mmMMHUBBUB_MIN_TTO 0x02b1 1114#define mmMMHUBBUB_MIN_TTO_BASE_IDX 2 1115#define mmWBIF_SMU_WM_CONTROL 0x0333 1116#define mmWBIF_SMU_WM_CONTROL_BASE_IDX 2 1117#define mmWBIF0_MISC_CTRL 0x0334 1118#define mmWBIF0_MISC_CTRL_BASE_IDX 2 1119#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0335 1120#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 1121#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0336 1122#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 1123#define mmVGA_SRC_SPLIT_CNTL 0x033d 1124#define mmVGA_SRC_SPLIT_CNTL_BASE_IDX 2 1125#define mmMMHUBBUB_MEM_PWR_STATUS 0x033e 1126#define mmMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 1127#define mmMMHUBBUB_MEM_PWR_CNTL 0x033f 1128#define mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2 1129#define mmMMHUBBUB_CLOCK_CNTL 0x0340 1130#define mmMMHUBBUB_CLOCK_CNTL_BASE_IDX 2 1131#define mmMMHUBBUB_SOFT_RESET 0x0341 1132#define mmMMHUBBUB_SOFT_RESET_BASE_IDX 2 1133#define mmDMU_IF_ERR_STATUS 0x0345 1134#define mmDMU_IF_ERR_STATUS_BASE_IDX 2 1135#define mmMMHUBBUB_CLIENT_UNIT_ID 0x0346 1136#define mmMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX 2 1137#define mmMMHUBBUB_WARMUP_VMID_CONTROL 0x0348 1138#define mmMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX 2 1139 1140 1141// addressBlock: dce_dc_mmhubbub_vgaif_dispdec 1142// base address: 0x0 1143#define mmMCIF_CONTROL 0x034a 1144#define mmMCIF_CONTROL_BASE_IDX 2 1145#define mmMCIF_WRITE_COMBINE_CONTROL 0x034b 1146#define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2 1147#define mmMCIF_PHASE0_OUTSTANDING_COUNTER 0x034e 1148#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 1149#define mmMCIF_PHASE1_OUTSTANDING_COUNTER 0x034f 1150#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 1151#define mmMCIF_PHASE2_OUTSTANDING_COUNTER 0x0350 1152#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2 1153 1154 1155// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec 1156// base address: 0xd48 1157#define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x0352 1158#define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2 1159#define mmDC_PERFMON3_PERFCOUNTER_CNTL2 0x0353 1160#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2 1161#define mmDC_PERFMON3_PERFCOUNTER_STATE 0x0354 1162#define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2 1163#define mmDC_PERFMON3_PERFMON_CNTL 0x0355 1164#define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2 1165#define mmDC_PERFMON3_PERFMON_CNTL2 0x0356 1166#define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2 1167#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x0357 1168#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1169#define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x0358 1170#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2 1171#define mmDC_PERFMON3_PERFMON_HI 0x0359 1172#define mmDC_PERFMON3_PERFMON_HI_BASE_IDX 2 1173#define mmDC_PERFMON3_PERFMON_LOW 0x035a 1174#define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX 2 1175 1176 1177// addressBlock: dce_dc_hda_azf0stream0_dispdec 1178// base address: 0x0 1179#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e 1180#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2 1181#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x035f 1182#define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2 1183 1184 1185// addressBlock: dce_dc_hda_azf0stream1_dispdec 1186// base address: 0x8 1187#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360 1188#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2 1189#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x0361 1190#define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2 1191 1192 1193// addressBlock: dce_dc_hda_azf0stream2_dispdec 1194// base address: 0x10 1195#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362 1196#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2 1197#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x0363 1198#define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2 1199 1200 1201// addressBlock: dce_dc_hda_azf0stream3_dispdec 1202// base address: 0x18 1203#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364 1204#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2 1205#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x0365 1206#define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2 1207 1208 1209// addressBlock: dce_dc_hda_azf0stream4_dispdec 1210// base address: 0x20 1211#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366 1212#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2 1213#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x0367 1214#define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2 1215 1216 1217// addressBlock: dce_dc_hda_azf0stream5_dispdec 1218// base address: 0x28 1219#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368 1220#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2 1221#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x0369 1222#define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2 1223 1224 1225// addressBlock: dce_dc_hda_azf0stream6_dispdec 1226// base address: 0x30 1227#define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a 1228#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2 1229#define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x036b 1230#define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2 1231 1232 1233// addressBlock: dce_dc_hda_azf0stream7_dispdec 1234// base address: 0x38 1235#define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c 1236#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2 1237#define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x036d 1238#define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2 1239 1240 1241// addressBlock: dce_dc_hda_az_misc_dispdec 1242// base address: 0x0 1243#define mmAZ_CLOCK_CNTL 0x0372 1244#define mmAZ_CLOCK_CNTL_BASE_IDX 2 1245 1246 1247// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec 1248// base address: 0xde8 1249#define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x037a 1250#define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2 1251#define mmDC_PERFMON4_PERFCOUNTER_CNTL2 0x037b 1252#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2 1253#define mmDC_PERFMON4_PERFCOUNTER_STATE 0x037c 1254#define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2 1255#define mmDC_PERFMON4_PERFMON_CNTL 0x037d 1256#define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2 1257#define mmDC_PERFMON4_PERFMON_CNTL2 0x037e 1258#define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2 1259#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x037f 1260#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1261#define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x0380 1262#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2 1263#define mmDC_PERFMON4_PERFMON_HI 0x0381 1264#define mmDC_PERFMON4_PERFMON_HI_BASE_IDX 2 1265#define mmDC_PERFMON4_PERFMON_LOW 0x0382 1266#define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX 2 1267 1268 1269// addressBlock: dce_dc_hda_azf0endpoint0_dispdec 1270// base address: 0x0 1271#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386 1272#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1273#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387 1274#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1275 1276 1277// addressBlock: dce_dc_hda_azf0endpoint1_dispdec 1278// base address: 0x18 1279#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c 1280#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1281#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d 1282#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1283 1284 1285// addressBlock: dce_dc_hda_azf0endpoint2_dispdec 1286// base address: 0x30 1287#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392 1288#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1289#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393 1290#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1291 1292 1293// addressBlock: dce_dc_hda_azf0endpoint3_dispdec 1294// base address: 0x48 1295#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398 1296#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1297#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399 1298#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1299 1300 1301// addressBlock: dce_dc_hda_azf0endpoint4_dispdec 1302// base address: 0x60 1303#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e 1304#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1305#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f 1306#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1307 1308 1309// addressBlock: dce_dc_hda_azf0endpoint5_dispdec 1310// base address: 0x78 1311#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4 1312#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1313#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5 1314#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1315 1316 1317// addressBlock: dce_dc_hda_azf0endpoint6_dispdec 1318// base address: 0x90 1319#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa 1320#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1321#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab 1322#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1323 1324 1325// addressBlock: dce_dc_hda_azf0endpoint7_dispdec 1326// base address: 0xa8 1327#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0 1328#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1329#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1 1330#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1331 1332 1333// addressBlock: dce_dc_hda_azf0controller_dispdec 1334// base address: 0x0 1335#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x03c2 1336#define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2 1337#define mmAZALIA_AUDIO_DTO 0x03c3 1338#define mmAZALIA_AUDIO_DTO_BASE_IDX 2 1339#define mmAZALIA_AUDIO_DTO_CONTROL 0x03c4 1340#define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2 1341#define mmAZALIA_SOCCLK_CONTROL 0x03c5 1342#define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2 1343#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6 1344#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2 1345#define mmAZALIA_DATA_DMA_CONTROL 0x03c7 1346#define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX 2 1347#define mmAZALIA_BDL_DMA_CONTROL 0x03c8 1348#define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX 2 1349#define mmAZALIA_RIRB_AND_DP_CONTROL 0x03c9 1350#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2 1351#define mmAZALIA_CORB_DMA_CONTROL 0x03ca 1352#define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX 2 1353#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x03d1 1354#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2 1355#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x03d2 1356#define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2 1357#define mmAZALIA_GLOBAL_CAPABILITIES 0x03d3 1358#define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2 1359#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4 1360#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 1361#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5 1362#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2 1363#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6 1364#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 1365#define mmAZALIA_INPUT_CRC0_CONTROL0 0x03d9 1366#define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2 1367#define mmAZALIA_INPUT_CRC0_CONTROL1 0x03da 1368#define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2 1369#define mmAZALIA_INPUT_CRC0_CONTROL2 0x03db 1370#define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2 1371#define mmAZALIA_INPUT_CRC0_CONTROL3 0x03dc 1372#define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2 1373#define mmAZALIA_INPUT_CRC0_RESULT 0x03dd 1374#define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2 1375#define mmAZALIA_INPUT_CRC1_CONTROL0 0x03de 1376#define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2 1377#define mmAZALIA_INPUT_CRC1_CONTROL1 0x03df 1378#define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2 1379#define mmAZALIA_INPUT_CRC1_CONTROL2 0x03e0 1380#define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2 1381#define mmAZALIA_INPUT_CRC1_CONTROL3 0x03e1 1382#define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2 1383#define mmAZALIA_INPUT_CRC1_RESULT 0x03e2 1384#define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2 1385#define mmAZALIA_CRC0_CONTROL0 0x03e3 1386#define mmAZALIA_CRC0_CONTROL0_BASE_IDX 2 1387#define mmAZALIA_CRC0_CONTROL1 0x03e4 1388#define mmAZALIA_CRC0_CONTROL1_BASE_IDX 2 1389#define mmAZALIA_CRC0_CONTROL2 0x03e5 1390#define mmAZALIA_CRC0_CONTROL2_BASE_IDX 2 1391#define mmAZALIA_CRC0_CONTROL3 0x03e6 1392#define mmAZALIA_CRC0_CONTROL3_BASE_IDX 2 1393#define mmAZALIA_CRC0_RESULT 0x03e7 1394#define mmAZALIA_CRC0_RESULT_BASE_IDX 2 1395#define mmAZALIA_CRC1_CONTROL0 0x03e8 1396#define mmAZALIA_CRC1_CONTROL0_BASE_IDX 2 1397#define mmAZALIA_CRC1_CONTROL1 0x03e9 1398#define mmAZALIA_CRC1_CONTROL1_BASE_IDX 2 1399#define mmAZALIA_CRC1_CONTROL2 0x03ea 1400#define mmAZALIA_CRC1_CONTROL2_BASE_IDX 2 1401#define mmAZALIA_CRC1_CONTROL3 0x03eb 1402#define mmAZALIA_CRC1_CONTROL3_BASE_IDX 2 1403#define mmAZALIA_CRC1_RESULT 0x03ec 1404#define mmAZALIA_CRC1_RESULT_BASE_IDX 2 1405#define mmAZALIA_MEM_PWR_CTRL 0x03ee 1406#define mmAZALIA_MEM_PWR_CTRL_BASE_IDX 2 1407#define mmAZALIA_MEM_PWR_STATUS 0x03ef 1408#define mmAZALIA_MEM_PWR_STATUS_BASE_IDX 2 1409 1410 1411// addressBlock: dce_dc_hda_azf0root_dispdec 1412// base address: 0x0 1413#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406 1414#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2 1415#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407 1416#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2 1417#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408 1418#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2 1419#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409 1420#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2 1421#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a 1422#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2 1423#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b 1424#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2 1425#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c 1426#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2 1427#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d 1428#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2 1429#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e 1430#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2 1431#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f 1432#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2 1433#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410 1434#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2 1435#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411 1436#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2 1437#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412 1438#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 1439#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413 1440#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 1441#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x0415 1442#define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2 1443#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x0416 1444#define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2 1445#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x0417 1446#define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2 1447#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x0418 1448#define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2 1449#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x0419 1450#define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2 1451#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x041a 1452#define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2 1453#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x041b 1454#define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2 1455#define mmREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c 1456#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 1457#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d 1458#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 1459 1460 1461// addressBlock: dce_dc_hda_azf0stream8_dispdec 1462// base address: 0x320 1463#define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426 1464#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2 1465#define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x0427 1466#define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2 1467 1468 1469// addressBlock: dce_dc_hda_azf0stream9_dispdec 1470// base address: 0x328 1471#define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428 1472#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2 1473#define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x0429 1474#define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2 1475 1476 1477// addressBlock: dce_dc_hda_azf0stream10_dispdec 1478// base address: 0x330 1479#define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a 1480#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2 1481#define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x042b 1482#define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2 1483 1484 1485// addressBlock: dce_dc_hda_azf0stream11_dispdec 1486// base address: 0x338 1487#define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c 1488#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2 1489#define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x042d 1490#define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2 1491 1492 1493// addressBlock: dce_dc_hda_azf0stream12_dispdec 1494// base address: 0x340 1495#define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e 1496#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2 1497#define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x042f 1498#define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2 1499 1500 1501// addressBlock: dce_dc_hda_azf0stream13_dispdec 1502// base address: 0x348 1503#define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430 1504#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2 1505#define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x0431 1506#define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2 1507 1508 1509// addressBlock: dce_dc_hda_azf0stream14_dispdec 1510// base address: 0x350 1511#define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432 1512#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2 1513#define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x0433 1514#define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2 1515 1516 1517// addressBlock: dce_dc_hda_azf0stream15_dispdec 1518// base address: 0x358 1519#define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434 1520#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2 1521#define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x0435 1522#define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2 1523 1524 1525// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec 1526// base address: 0x0 1527#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a 1528#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1529#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b 1530#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1531 1532 1533// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec 1534// base address: 0x10 1535#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e 1536#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1537#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f 1538#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1539 1540 1541// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec 1542// base address: 0x20 1543#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442 1544#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1545#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443 1546#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1547 1548 1549// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec 1550// base address: 0x30 1551#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446 1552#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1553#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447 1554#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1555 1556 1557// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec 1558// base address: 0x40 1559#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a 1560#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1561#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b 1562#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1563 1564 1565// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec 1566// base address: 0x50 1567#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e 1568#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1569#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f 1570#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1571 1572 1573// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec 1574// base address: 0x60 1575#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452 1576#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1577#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453 1578#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1579 1580 1581// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec 1582// base address: 0x70 1583#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456 1584#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1585#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457 1586#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1587 1588 1589// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec 1590// base address: 0x0 1591#define mmDCHUBBUB_SDPIF_CFG0 0x048f 1592#define mmDCHUBBUB_SDPIF_CFG0_BASE_IDX 2 1593#define mmVM_REQUEST_PHYSICAL 0x0490 1594#define mmVM_REQUEST_PHYSICAL_BASE_IDX 2 1595#define mmDCHUBBUB_FORCE_IO_STATUS_0 0x0491 1596#define mmDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2 1597#define mmDCHUBBUB_FORCE_IO_STATUS_1 0x0492 1598#define mmDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2 1599#define mmDCN_VM_FB_LOCATION_BASE 0x0493 1600#define mmDCN_VM_FB_LOCATION_BASE_BASE_IDX 2 1601#define mmDCN_VM_FB_LOCATION_TOP 0x0494 1602#define mmDCN_VM_FB_LOCATION_TOP_BASE_IDX 2 1603#define mmDCN_VM_FB_OFFSET 0x0495 1604#define mmDCN_VM_FB_OFFSET_BASE_IDX 2 1605#define mmDCN_VM_AGP_BOT 0x0496 1606#define mmDCN_VM_AGP_BOT_BASE_IDX 2 1607#define mmDCN_VM_AGP_TOP 0x0497 1608#define mmDCN_VM_AGP_TOP_BASE_IDX 2 1609#define mmDCN_VM_AGP_BASE 0x0498 1610#define mmDCN_VM_AGP_BASE_BASE_IDX 2 1611#define mmDCN_VM_LOCAL_HBM_ADDRESS_START 0x0499 1612#define mmDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 2 1613#define mmDCN_VM_LOCAL_HBM_ADDRESS_END 0x049a 1614#define mmDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 2 1615#define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x049b 1616#define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 2 1617#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x04ba 1618#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2 1619#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x04bb 1620#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2 1621#define mmDCHUBBUB_SDPIF_CFG1 0x04bf 1622#define mmDCHUBBUB_SDPIF_CFG1_BASE_IDX 2 1623#define mmDCHUBBUB_SDPIF_CFG2 0x04c0 1624#define mmDCHUBBUB_SDPIF_CFG2_BASE_IDX 2 1625 1626 1627// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec 1628// base address: 0x0 1629#define mmDCHUBBUB_RET_PATH_DCC_CFG 0x04cf 1630#define mmDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX 2 1631#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0 0x04d0 1632#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX 2 1633#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1 0x04d1 1634#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX 2 1635#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0 0x04d2 1636#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX 2 1637#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1 0x04d3 1638#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX 2 1639#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0 0x04d4 1640#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX 2 1641#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1 0x04d5 1642#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX 2 1643#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0 0x04d6 1644#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX 2 1645#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1 0x04d7 1646#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX 2 1647#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0 0x04d8 1648#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX 2 1649#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1 0x04d9 1650#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX 2 1651#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0 0x04da 1652#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX 2 1653#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1 0x04db 1654#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX 2 1655#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0 0x04dc 1656#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX 2 1657#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1 0x04dd 1658#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX 2 1659#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0 0x04de 1660#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX 2 1661#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1 0x04df 1662#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX 2 1663#define mmDCHUBBUB_RET_PATH_DCC_CFG8_0 0x04e0 1664#define mmDCHUBBUB_RET_PATH_DCC_CFG8_0_BASE_IDX 2 1665#define mmDCHUBBUB_RET_PATH_DCC_CFG8_1 0x04e1 1666#define mmDCHUBBUB_RET_PATH_DCC_CFG8_1_BASE_IDX 2 1667#define mmDCHUBBUB_RET_PATH_DCC_CFG9_0 0x04e2 1668#define mmDCHUBBUB_RET_PATH_DCC_CFG9_0_BASE_IDX 2 1669#define mmDCHUBBUB_RET_PATH_DCC_CFG9_1 0x04e3 1670#define mmDCHUBBUB_RET_PATH_DCC_CFG9_1_BASE_IDX 2 1671#define mmDCHUBBUB_RET_PATH_DCC_CFG10_0 0x04e4 1672#define mmDCHUBBUB_RET_PATH_DCC_CFG10_0_BASE_IDX 2 1673#define mmDCHUBBUB_RET_PATH_DCC_CFG10_1 0x04e5 1674#define mmDCHUBBUB_RET_PATH_DCC_CFG10_1_BASE_IDX 2 1675#define mmDCHUBBUB_RET_PATH_DCC_CFG11_0 0x04e6 1676#define mmDCHUBBUB_RET_PATH_DCC_CFG11_0_BASE_IDX 2 1677#define mmDCHUBBUB_RET_PATH_DCC_CFG11_1 0x04e7 1678#define mmDCHUBBUB_RET_PATH_DCC_CFG11_1_BASE_IDX 2 1679#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04ef 1680#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2 1681#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04f0 1682#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2 1683#define mmDCHUBBUB_CRC_CTRL 0x04f1 1684#define mmDCHUBBUB_CRC_CTRL_BASE_IDX 2 1685#define mmDCHUBBUB_CRC0_VAL_R_G 0x04f2 1686#define mmDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2 1687#define mmDCHUBBUB_CRC0_VAL_B_A 0x04f3 1688#define mmDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2 1689#define mmDCHUBBUB_CRC1_VAL_R_G 0x04f4 1690#define mmDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2 1691#define mmDCHUBBUB_CRC1_VAL_B_A 0x04f5 1692#define mmDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2 1693 1694 1695// addressBlock: dce_dc_dchubbub_hubbub_dispdec 1696// base address: 0x0 1697#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x0505 1698#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2 1699#define mmDCHUBBUB_ARB_SAT_LEVEL 0x0506 1700#define mmDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2 1701#define mmDCHUBBUB_ARB_QOS_FORCE 0x0507 1702#define mmDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2 1703#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL 0x0508 1704#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2 1705#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x0509 1706#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2 1707#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A 0x050a 1708#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX 2 1709#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x050b 1710#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2 1711#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x050c 1712#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2 1713#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0x050d 1714#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX 2 1715#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x050e 1716#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2 1717#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B 0x050f 1718#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX 2 1719#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x0510 1720#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2 1721#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x0511 1722#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2 1723#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0x0512 1724#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX 2 1725#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x0513 1726#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2 1727#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C 0x0514 1728#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX 2 1729#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0515 1730#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2 1731#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0516 1732#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2 1733#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0x0517 1734#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX 2 1735#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0518 1736#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2 1737#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D 0x0519 1738#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX 2 1739#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x051a 1740#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2 1741#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x051b 1742#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2 1743#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0x051c 1744#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX 2 1745#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x051d 1746#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2 1747#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE 0x051e 1748#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2 1749#define mmDCHUBBUB_GLOBAL_TIMER_CNTL 0x051f 1750#define mmDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2 1751#define mmSURFACE_CHECK0_ADDRESS_LSB 0x0520 1752#define mmSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2 1753#define mmSURFACE_CHECK0_ADDRESS_MSB 0x0521 1754#define mmSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2 1755#define mmSURFACE_CHECK1_ADDRESS_LSB 0x0522 1756#define mmSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2 1757#define mmSURFACE_CHECK1_ADDRESS_MSB 0x0523 1758#define mmSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2 1759#define mmSURFACE_CHECK2_ADDRESS_LSB 0x0524 1760#define mmSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2 1761#define mmSURFACE_CHECK2_ADDRESS_MSB 0x0525 1762#define mmSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2 1763#define mmSURFACE_CHECK3_ADDRESS_LSB 0x0526 1764#define mmSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2 1765#define mmSURFACE_CHECK3_ADDRESS_MSB 0x0527 1766#define mmSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2 1767#define mmVTG0_CONTROL 0x0528 1768#define mmVTG0_CONTROL_BASE_IDX 2 1769#define mmVTG1_CONTROL 0x0529 1770#define mmVTG1_CONTROL_BASE_IDX 2 1771#define mmVTG2_CONTROL 0x052a 1772#define mmVTG2_CONTROL_BASE_IDX 2 1773#define mmVTG3_CONTROL 0x052b 1774#define mmVTG3_CONTROL_BASE_IDX 2 1775#define mmVTG4_CONTROL 0x052c 1776#define mmVTG4_CONTROL_BASE_IDX 2 1777#define mmVTG5_CONTROL 0x052d 1778#define mmVTG5_CONTROL_BASE_IDX 2 1779#define mmDCHUBBUB_SOFT_RESET 0x052e 1780#define mmDCHUBBUB_SOFT_RESET_BASE_IDX 2 1781#define mmDCHUBBUB_CLOCK_CNTL 0x052f 1782#define mmDCHUBBUB_CLOCK_CNTL_BASE_IDX 2 1783#define mmDCFCLK_CNTL 0x0530 1784#define mmDCFCLK_CNTL_BASE_IDX 2 1785#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0531 1786#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2 1787#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0532 1788#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2 1789#define mmDCHUBBUB_VLINE_SNAPSHOT 0x0533 1790#define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2 1791#define mmDCHUBBUB_CTRL_STATUS 0x0534 1792#define mmDCHUBBUB_CTRL_STATUS_BASE_IDX 2 1793#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x053a 1794#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2 1795#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x053b 1796#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2 1797#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS 0x053c 1798#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2 1799#define mmDCHUBBUB_TEST_DEBUG_INDEX 0x053d 1800#define mmDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2 1801#define mmDCHUBBUB_TEST_DEBUG_DATA 0x053e 1802#define mmDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2 1803#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A 0x053f 1804#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX 2 1805#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A 0x0540 1806#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX 2 1807#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B 0x0541 1808#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX 2 1809#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B 0x0542 1810#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX 2 1811#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C 0x0543 1812#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX 2 1813#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C 0x0544 1814#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX 2 1815#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D 0x0545 1816#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX 2 1817#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D 0x0546 1818#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX 2 1819#define mmFMON_CTRL 0x0548 1820#define mmFMON_CTRL_BASE_IDX 2 1821#define mmFMON_CTRL_1 0x0548 1822#define mmFMON_CTRL_1_BASE_IDX 2 1823 1824 1825// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec 1826// base address: 0x1534 1827#define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x054d 1828#define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2 1829#define mmDC_PERFMON5_PERFCOUNTER_CNTL2 0x054e 1830#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2 1831#define mmDC_PERFMON5_PERFCOUNTER_STATE 0x054f 1832#define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2 1833#define mmDC_PERFMON5_PERFMON_CNTL 0x0550 1834#define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2 1835#define mmDC_PERFMON5_PERFMON_CNTL2 0x0551 1836#define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2 1837#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x0552 1838#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1839#define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x0553 1840#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2 1841#define mmDC_PERFMON5_PERFMON_HI 0x0554 1842#define mmDC_PERFMON5_PERFMON_HI_BASE_IDX 2 1843#define mmDC_PERFMON5_PERFMON_LOW 0x0555 1844#define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX 2 1845 1846 1847// addressBlock: dce_dc_dchubbub_hubbub_vmrq_if_dispdec 1848// base address: 0x0 1849#define mmDCN_VM_CONTEXT0_CNTL 0x0559 1850#define mmDCN_VM_CONTEXT0_CNTL_BASE_IDX 2 1851#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x055a 1852#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1853#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x055b 1854#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1855#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x055c 1856#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1857#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x055d 1858#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1859#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x055e 1860#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1861#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x055f 1862#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1863#define mmDCN_VM_CONTEXT1_CNTL 0x0560 1864#define mmDCN_VM_CONTEXT1_CNTL_BASE_IDX 2 1865#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0561 1866#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1867#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0562 1868#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1869#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0563 1870#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1871#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0564 1872#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1873#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0565 1874#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1875#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0566 1876#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1877#define mmDCN_VM_CONTEXT2_CNTL 0x0567 1878#define mmDCN_VM_CONTEXT2_CNTL_BASE_IDX 2 1879#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0568 1880#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1881#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0569 1882#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1883#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x056a 1884#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1885#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x056b 1886#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1887#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x056c 1888#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1889#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x056d 1890#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1891#define mmDCN_VM_CONTEXT3_CNTL 0x056e 1892#define mmDCN_VM_CONTEXT3_CNTL_BASE_IDX 2 1893#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x056f 1894#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1895#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0570 1896#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1897#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0571 1898#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1899#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0572 1900#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1901#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0573 1902#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1903#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0574 1904#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1905#define mmDCN_VM_CONTEXT4_CNTL 0x0575 1906#define mmDCN_VM_CONTEXT4_CNTL_BASE_IDX 2 1907#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0576 1908#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1909#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0577 1910#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1911#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0578 1912#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1913#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0579 1914#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1915#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x057a 1916#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1917#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x057b 1918#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1919#define mmDCN_VM_CONTEXT5_CNTL 0x057c 1920#define mmDCN_VM_CONTEXT5_CNTL_BASE_IDX 2 1921#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x057d 1922#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1923#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x057e 1924#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1925#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x057f 1926#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1927#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0580 1928#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1929#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0581 1930#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1931#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0582 1932#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1933#define mmDCN_VM_CONTEXT6_CNTL 0x0583 1934#define mmDCN_VM_CONTEXT6_CNTL_BASE_IDX 2 1935#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0584 1936#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1937#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0585 1938#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1939#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0586 1940#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1941#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0587 1942#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1943#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0588 1944#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1945#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0589 1946#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1947#define mmDCN_VM_CONTEXT7_CNTL 0x058a 1948#define mmDCN_VM_CONTEXT7_CNTL_BASE_IDX 2 1949#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x058b 1950#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1951#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x058c 1952#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1953#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x058d 1954#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1955#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x058e 1956#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1957#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x058f 1958#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1959#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0590 1960#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1961#define mmDCN_VM_CONTEXT8_CNTL 0x0591 1962#define mmDCN_VM_CONTEXT8_CNTL_BASE_IDX 2 1963#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0592 1964#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1965#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0593 1966#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1967#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0594 1968#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1969#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0595 1970#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1971#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0596 1972#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1973#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0597 1974#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1975#define mmDCN_VM_CONTEXT9_CNTL 0x0598 1976#define mmDCN_VM_CONTEXT9_CNTL_BASE_IDX 2 1977#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0599 1978#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1979#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x059a 1980#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1981#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x059b 1982#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1983#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x059c 1984#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1985#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x059d 1986#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1987#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x059e 1988#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1989#define mmDCN_VM_CONTEXT10_CNTL 0x059f 1990#define mmDCN_VM_CONTEXT10_CNTL_BASE_IDX 2 1991#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05a0 1992#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1993#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05a1 1994#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1995#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x05a2 1996#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1997#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x05a3 1998#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1999#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x05a4 2000#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
2001#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x05a5 2002#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2003#define mmDCN_VM_CONTEXT11_CNTL 0x05a6 2004#define mmDCN_VM_CONTEXT11_CNTL_BASE_IDX 2 2005#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05a7 2006#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2007#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05a8 2008#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2009#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x05a9 2010#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2011#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x05aa 2012#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2013#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x05ab 2014#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2015#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x05ac 2016#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2017#define mmDCN_VM_CONTEXT12_CNTL 0x05ad 2018#define mmDCN_VM_CONTEXT12_CNTL_BASE_IDX 2 2019#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05ae 2020#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2021#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05af 2022#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2023#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x05b0 2024#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2025#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x05b1 2026#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2027#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x05b2 2028#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2029#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x05b3 2030#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2031#define mmDCN_VM_CONTEXT13_CNTL 0x05b4 2032#define mmDCN_VM_CONTEXT13_CNTL_BASE_IDX 2 2033#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05b5 2034#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2035#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05b6 2036#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2037#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x05b7 2038#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2039#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x05b8 2040#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2041#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x05b9 2042#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2043#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x05ba 2044#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2045#define mmDCN_VM_CONTEXT14_CNTL 0x05bb 2046#define mmDCN_VM_CONTEXT14_CNTL_BASE_IDX 2 2047#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05bc 2048#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2049#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05bd 2050#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2051#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x05be 2052#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2053#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x05bf 2054#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2055#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x05c0 2056#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2057#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x05c1 2058#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2059#define mmDCN_VM_CONTEXT15_CNTL 0x05c2 2060#define mmDCN_VM_CONTEXT15_CNTL_BASE_IDX 2 2061#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05c3 2062#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2063#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05c4 2064#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2065#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x05c5 2066#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2067#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x05c6 2068#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2069#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x05c7 2070#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2071#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x05c8 2072#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2073#define mmDCN_VM_DEFAULT_ADDR_MSB 0x05c9 2074#define mmDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX 2 2075#define mmDCN_VM_DEFAULT_ADDR_LSB 0x05ca 2076#define mmDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX 2 2077#define mmDCN_VM_FAULT_CNTL 0x05cb 2078#define mmDCN_VM_FAULT_CNTL_BASE_IDX 2 2079#define mmDCN_VM_FAULT_STATUS 0x05cc 2080#define mmDCN_VM_FAULT_STATUS_BASE_IDX 2 2081#define mmDCN_VM_FAULT_ADDR_MSB 0x05cd 2082#define mmDCN_VM_FAULT_ADDR_MSB_BASE_IDX 2 2083#define mmDCN_VM_FAULT_ADDR_LSB 0x05ce 2084#define mmDCN_VM_FAULT_ADDR_LSB_BASE_IDX 2 2085 2086 2087// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec 2088// base address: 0x0 2089#define mmHUBP0_DCSURF_SURFACE_CONFIG 0x05e5 2090#define mmHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2091#define mmHUBP0_DCSURF_ADDR_CONFIG 0x05e6 2092#define mmHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2 2093#define mmHUBP0_DCSURF_TILING_CONFIG 0x05e7 2094#define mmHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2 2095#define mmHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9 2096#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2097#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05ea 2098#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2099#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05eb 2100#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2101#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ec 2102#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2103#define mmHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ed 2104#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2105#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ee 2106#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2107#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05ef 2108#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2109#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f0 2110#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2111#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f1 2112#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2113#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f2 2114#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2115#define mmHUBP0_DCHUBP_CNTL 0x05f3 2116#define mmHUBP0_DCHUBP_CNTL_BASE_IDX 2 2117#define mmHUBP0_HUBP_CLK_CNTL 0x05f4 2118#define mmHUBP0_HUBP_CLK_CNTL_BASE_IDX 2 2119#define mmHUBP0_DCHUBP_VMPG_CONFIG 0x05f5 2120#define mmHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2 2121#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x05fb 2122#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 2123#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x05fc 2124#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 2125#define mmHUBP0_HUBPREQ_DEBUG_DB 0x05f6 2126#define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2 2127#define mmHUBP0_HUBPREQ_DEBUG 0x05f7 2128#define mmHUBP0_HUBPREQ_DEBUG_BASE_IDX 2 2129 2130 2131// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec 2132// base address: 0x0 2133#define mmHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607 2134#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2 2135#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608 2136#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 2137#define mmHUBPREQ0_VMID_SETTINGS_0 0x0609 2138#define mmHUBPREQ0_VMID_SETTINGS_0_BASE_IDX 2 2139#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a 2140#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 2141#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b 2142#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2143#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c 2144#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 2145#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d 2146#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2147#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e 2148#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 2149#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f 2150#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2151#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610 2152#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 2153#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611 2154#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2155#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0612 2156#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 2157#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0613 2158#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2159#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0614 2160#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2161#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0615 2162#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2163#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0616 2164#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 2165#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0617 2166#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2167#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0618 2168#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2169#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0619 2170#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2171#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL 0x061a 2172#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2 2173#define mmHUBPREQ0_DCSURF_FLIP_CONTROL 0x061b 2174#define mmHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2 2175#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2 0x061c 2176#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2 2177#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x0620 2178#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 2179#define mmHUBPREQ0_DCSURF_SURFACE_INUSE 0x0621 2180#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2 2181#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0622 2182#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 2183#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0623 2184#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 2185#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0624 2186#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 2187#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0625 2188#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 2189#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0626 2190#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 2191#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0627 2192#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 2193#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0628 2194#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 2195#define mmHUBPREQ0_DCN_EXPANSION_MODE 0x0629 2196#define mmHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2 2197#define mmHUBPREQ0_DCN_TTU_QOS_WM 0x062a 2198#define mmHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2 2199#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x062b 2200#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 2201#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x062c 2202#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 2203#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x062d 2204#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 2205#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x062e 2206#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 2207#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x062f 2208#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 2209#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x0630 2210#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 2211#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0631 2212#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 2213#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0 0x0632 2214#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 2215#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1 0x0633 2216#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 2217#define mmHUBPREQ0_DCN_DMDATA_VM_CNTL 0x0634 2218#define mmHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX 2 2219#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0635 2220#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 2221#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0636 2222#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 2223#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x0643 2224#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 2225#define mmHUBPREQ0_BLANK_OFFSET_0 0x0644 2226#define mmHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2 2227#define mmHUBPREQ0_BLANK_OFFSET_1 0x0645 2228#define mmHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2 2229#define mmHUBPREQ0_DST_DIMENSIONS 0x0646 2230#define mmHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2 2231#define mmHUBPREQ0_DST_AFTER_SCALER 0x0647 2232#define mmHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2 2233#define mmHUBPREQ0_PREFETCH_SETTINGS 0x0648 2234#define mmHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2 2235#define mmHUBPREQ0_PREFETCH_SETTINGS_C 0x0649 2236#define mmHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2 2237#define mmHUBPREQ0_VBLANK_PARAMETERS_0 0x064a 2238#define mmHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2 2239#define mmHUBPREQ0_VBLANK_PARAMETERS_1 0x064b 2240#define mmHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2 2241#define mmHUBPREQ0_VBLANK_PARAMETERS_2 0x064c 2242#define mmHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2 2243#define mmHUBPREQ0_VBLANK_PARAMETERS_3 0x064d 2244#define mmHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2 2245#define mmHUBPREQ0_VBLANK_PARAMETERS_4 0x064e 2246#define mmHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2 2247#define mmHUBPREQ0_FLIP_PARAMETERS_0 0x064f 2248#define mmHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2 2249#define mmHUBPREQ0_FLIP_PARAMETERS_1 0x0650 2250#define mmHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX 2 2251#define mmHUBPREQ0_FLIP_PARAMETERS_2 0x0651 2252#define mmHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2 2253#define mmHUBPREQ0_NOM_PARAMETERS_0 0x0652 2254#define mmHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2 2255#define mmHUBPREQ0_NOM_PARAMETERS_1 0x0653 2256#define mmHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2 2257#define mmHUBPREQ0_NOM_PARAMETERS_2 0x0654 2258#define mmHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2 2259#define mmHUBPREQ0_NOM_PARAMETERS_3 0x0655 2260#define mmHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2 2261#define mmHUBPREQ0_NOM_PARAMETERS_4 0x0656 2262#define mmHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2 2263#define mmHUBPREQ0_NOM_PARAMETERS_5 0x0657 2264#define mmHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2 2265#define mmHUBPREQ0_NOM_PARAMETERS_6 0x0658 2266#define mmHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2 2267#define mmHUBPREQ0_NOM_PARAMETERS_7 0x0659 2268#define mmHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2 2269#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE 0x065a 2270#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2 2271#define mmHUBPREQ0_PER_LINE_DELIVERY 0x065b 2272#define mmHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2 2273#define mmHUBPREQ0_CURSOR_SETTINGS 0x065c 2274#define mmHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2 2275#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x065d 2276#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 2277#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x065e 2278#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 2279#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x065f 2280#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 2281#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x0660 2282#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 2283#define mmHUBPREQ0_VBLANK_PARAMETERS_5 0x0663 2284#define mmHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX 2 2285#define mmHUBPREQ0_VBLANK_PARAMETERS_6 0x0664 2286#define mmHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX 2 2287#define mmHUBPREQ0_FLIP_PARAMETERS_3 0x0665 2288#define mmHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX 2 2289#define mmHUBPREQ0_FLIP_PARAMETERS_4 0x0666 2290#define mmHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX 2 2291#define mmHUBPREQ0_FLIP_PARAMETERS_5 0x0667 2292#define mmHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX 2 2293#define mmHUBPREQ0_FLIP_PARAMETERS_6 0x0668 2294#define mmHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX 2 2295 2296 2297// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec 2298// base address: 0x0 2299#define mmHUBPRET0_HUBPRET_CONTROL 0x066c 2300#define mmHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2 2301#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066d 2302#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 2303#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066e 2304#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 2305#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x066f 2306#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 2307#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x0670 2308#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 2309#define mmHUBPRET0_HUBPRET_READ_LINE0 0x0671 2310#define mmHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2 2311#define mmHUBPRET0_HUBPRET_READ_LINE1 0x0672 2312#define mmHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2 2313#define mmHUBPRET0_HUBPRET_INTERRUPT 0x0673 2314#define mmHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2 2315#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0674 2316#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 2317#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0675 2318#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 2319 2320 2321// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec 2322// base address: 0x0 2323#define mmCURSOR0_0_CURSOR_CONTROL 0x0678 2324#define mmCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2 2325#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x0679 2326#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 2327#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067a 2328#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2329#define mmCURSOR0_0_CURSOR_SIZE 0x067b 2330#define mmCURSOR0_0_CURSOR_SIZE_BASE_IDX 2 2331#define mmCURSOR0_0_CURSOR_POSITION 0x067c 2332#define mmCURSOR0_0_CURSOR_POSITION_BASE_IDX 2 2333#define mmCURSOR0_0_CURSOR_HOT_SPOT 0x067d 2334#define mmCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2 2335#define mmCURSOR0_0_CURSOR_STEREO_CONTROL 0x067e 2336#define mmCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2 2337#define mmCURSOR0_0_CURSOR_DST_OFFSET 0x067f 2338#define mmCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2 2339#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0680 2340#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 2341#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0681 2342#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 2343#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0682 2344#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2 2345#define mmCURSOR0_0_DMDATA_ADDRESS_LOW 0x0683 2346#define mmCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2 2347#define mmCURSOR0_0_DMDATA_CNTL 0x0684 2348#define mmCURSOR0_0_DMDATA_CNTL_BASE_IDX 2 2349#define mmCURSOR0_0_DMDATA_QOS_CNTL 0x0685 2350#define mmCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2 2351#define mmCURSOR0_0_DMDATA_STATUS 0x0686 2352#define mmCURSOR0_0_DMDATA_STATUS_BASE_IDX 2 2353#define mmCURSOR0_0_DMDATA_SW_CNTL 0x0687 2354#define mmCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2 2355#define mmCURSOR0_0_DMDATA_SW_DATA 0x0688 2356#define mmCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2 2357 2358 2359// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 2360// base address: 0x1a74 2361#define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x069d 2362#define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2 2363#define mmDC_PERFMON6_PERFCOUNTER_CNTL2 0x069e 2364#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2 2365#define mmDC_PERFMON6_PERFCOUNTER_STATE 0x069f 2366#define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2 2367#define mmDC_PERFMON6_PERFMON_CNTL 0x06a0 2368#define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2 2369#define mmDC_PERFMON6_PERFMON_CNTL2 0x06a1 2370#define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2 2371#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x06a2 2372#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 2373#define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x06a3 2374#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2 2375#define mmDC_PERFMON6_PERFMON_HI 0x06a4 2376#define mmDC_PERFMON6_PERFMON_HI_BASE_IDX 2 2377#define mmDC_PERFMON6_PERFMON_LOW 0x06a5 2378#define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX 2 2379 2380 2381// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec 2382// base address: 0x370 2383#define mmHUBP1_DCSURF_SURFACE_CONFIG 0x06c1 2384#define mmHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2385#define mmHUBP1_DCSURF_ADDR_CONFIG 0x06c2 2386#define mmHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2 2387#define mmHUBP1_DCSURF_TILING_CONFIG 0x06c3 2388#define mmHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2 2389#define mmHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5 2390#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2391#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c6 2392#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2393#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c7 2394#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2395#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c8 2396#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2397#define mmHUBP1_DCSURF_SEC_VIEWPORT_START 0x06c9 2398#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2399#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06ca 2400#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2401#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cb 2402#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2403#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cc 2404#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2405#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06cd 2406#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2407#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06ce 2408#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2409#define mmHUBP1_DCHUBP_CNTL 0x06cf 2410#define mmHUBP1_DCHUBP_CNTL_BASE_IDX 2 2411#define mmHUBP1_HUBP_CLK_CNTL 0x06d0 2412#define mmHUBP1_HUBP_CLK_CNTL_BASE_IDX 2 2413#define mmHUBP1_DCHUBP_VMPG_CONFIG 0x06d1 2414#define mmHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2 2415#define mmHUBP1_HUBPREQ_DEBUG_DB 0x06d2 2416#define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2 2417#define mmHUBP1_HUBPREQ_DEBUG 0x06d3 2418#define mmHUBP1_HUBPREQ_DEBUG_BASE_IDX 2 2419#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06d7 2420#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 2421#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06d8 2422#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 2423 2424 2425// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec 2426// base address: 0x370 2427#define mmHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3 2428#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2 2429#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4 2430#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 2431#define mmHUBPREQ1_VMID_SETTINGS_0 0x06e5 2432#define mmHUBPREQ1_VMID_SETTINGS_0_BASE_IDX 2 2433#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6 2434#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 2435#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7 2436#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2437#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8 2438#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 2439#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9 2440#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2441#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea 2442#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 2443#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb 2444#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2445#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec 2446#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 2447#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed 2448#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2449#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x06ee 2450#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 2451#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x06ef 2452#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2453#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x06f0 2454#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2455#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x06f1 2456#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2457#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x06f2 2458#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 2459#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x06f3 2460#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2461#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x06f4 2462#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2463#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x06f5 2464#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2465#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06f6 2466#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2 2467#define mmHUBPREQ1_DCSURF_FLIP_CONTROL 0x06f7 2468#define mmHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2 2469#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f8 2470#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2 2471#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06fc 2472#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 2473#define mmHUBPREQ1_DCSURF_SURFACE_INUSE 0x06fd 2474#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2 2475#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06fe 2476#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 2477#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06ff 2478#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 2479#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x0700 2480#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 2481#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x0701 2482#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 2483#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0702 2484#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 2485#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0703 2486#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 2487#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0704 2488#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 2489#define mmHUBPREQ1_DCN_EXPANSION_MODE 0x0705 2490#define mmHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2 2491#define mmHUBPREQ1_DCN_TTU_QOS_WM 0x0706 2492#define mmHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2 2493#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x0707 2494#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 2495#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x0708 2496#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 2497#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x0709 2498#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 2499#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x070a 2500#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 2501#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x070b 2502#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 2503#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x070c 2504#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 2505#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x070d 2506#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 2507#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x070e 2508#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 2509#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x070f 2510#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 2511#define mmHUBPREQ1_DCN_DMDATA_VM_CNTL 0x0710 2512#define mmHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX 2 2513#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0711 2514#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 2515#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0712 2516#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 2517#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x071f 2518#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 2519#define mmHUBPREQ1_BLANK_OFFSET_0 0x0720 2520#define mmHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2 2521#define mmHUBPREQ1_BLANK_OFFSET_1 0x0721 2522#define mmHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2 2523#define mmHUBPREQ1_DST_DIMENSIONS 0x0722 2524#define mmHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2 2525#define mmHUBPREQ1_DST_AFTER_SCALER 0x0723 2526#define mmHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2 2527#define mmHUBPREQ1_PREFETCH_SETTINGS 0x0724 2528#define mmHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2 2529#define mmHUBPREQ1_PREFETCH_SETTINGS_C 0x0725 2530#define mmHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2 2531#define mmHUBPREQ1_VBLANK_PARAMETERS_0 0x0726 2532#define mmHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2 2533#define mmHUBPREQ1_VBLANK_PARAMETERS_1 0x0727 2534#define mmHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2 2535#define mmHUBPREQ1_VBLANK_PARAMETERS_2 0x0728 2536#define mmHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2 2537#define mmHUBPREQ1_VBLANK_PARAMETERS_3 0x0729 2538#define mmHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2 2539#define mmHUBPREQ1_VBLANK_PARAMETERS_4 0x072a 2540#define mmHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2 2541#define mmHUBPREQ1_FLIP_PARAMETERS_0 0x072b 2542#define mmHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2 2543#define mmHUBPREQ1_FLIP_PARAMETERS_1 0x072c 2544#define mmHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX 2 2545#define mmHUBPREQ1_FLIP_PARAMETERS_2 0x072d 2546#define mmHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2 2547#define mmHUBPREQ1_NOM_PARAMETERS_0 0x072e 2548#define mmHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2 2549#define mmHUBPREQ1_NOM_PARAMETERS_1 0x072f 2550#define mmHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2 2551#define mmHUBPREQ1_NOM_PARAMETERS_2 0x0730 2552#define mmHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2 2553#define mmHUBPREQ1_NOM_PARAMETERS_3 0x0731 2554#define mmHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2 2555#define mmHUBPREQ1_NOM_PARAMETERS_4 0x0732 2556#define mmHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2 2557#define mmHUBPREQ1_NOM_PARAMETERS_5 0x0733 2558#define mmHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2 2559#define mmHUBPREQ1_NOM_PARAMETERS_6 0x0734 2560#define mmHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2 2561#define mmHUBPREQ1_NOM_PARAMETERS_7 0x0735 2562#define mmHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2 2563#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE 0x0736 2564#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2 2565#define mmHUBPREQ1_PER_LINE_DELIVERY 0x0737 2566#define mmHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2 2567#define mmHUBPREQ1_CURSOR_SETTINGS 0x0738 2568#define mmHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2 2569#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x0739 2570#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 2571#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x073a 2572#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 2573#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x073b 2574#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 2575#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x073c 2576#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 2577#define mmHUBPREQ1_VBLANK_PARAMETERS_5 0x073f 2578#define mmHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX 2 2579#define mmHUBPREQ1_VBLANK_PARAMETERS_6 0x0740 2580#define mmHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX 2 2581#define mmHUBPREQ1_FLIP_PARAMETERS_3 0x0741 2582#define mmHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX 2 2583#define mmHUBPREQ1_FLIP_PARAMETERS_4 0x0742 2584#define mmHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX 2 2585#define mmHUBPREQ1_FLIP_PARAMETERS_5 0x0743 2586#define mmHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX 2 2587#define mmHUBPREQ1_FLIP_PARAMETERS_6 0x0744 2588#define mmHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX 2 2589 2590 2591// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec 2592// base address: 0x370 2593#define mmHUBPRET1_HUBPRET_CONTROL 0x0748 2594#define mmHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2 2595#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x0749 2596#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 2597#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x074a 2598#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 2599#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x074b 2600#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 2601#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074c 2602#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 2603#define mmHUBPRET1_HUBPRET_READ_LINE0 0x074d 2604#define mmHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2 2605#define mmHUBPRET1_HUBPRET_READ_LINE1 0x074e 2606#define mmHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2 2607#define mmHUBPRET1_HUBPRET_INTERRUPT 0x074f 2608#define mmHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2 2609#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE 0x0750 2610#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 2611#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS 0x0751 2612#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 2613 2614 2615// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec 2616// base address: 0x370 2617#define mmCURSOR0_1_CURSOR_CONTROL 0x0754 2618#define mmCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2 2619#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0755 2620#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 2621#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0756 2622#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2623#define mmCURSOR0_1_CURSOR_SIZE 0x0757 2624#define mmCURSOR0_1_CURSOR_SIZE_BASE_IDX 2 2625#define mmCURSOR0_1_CURSOR_POSITION 0x0758 2626#define mmCURSOR0_1_CURSOR_POSITION_BASE_IDX 2 2627#define mmCURSOR0_1_CURSOR_HOT_SPOT 0x0759 2628#define mmCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2 2629#define mmCURSOR0_1_CURSOR_STEREO_CONTROL 0x075a 2630#define mmCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2 2631#define mmCURSOR0_1_CURSOR_DST_OFFSET 0x075b 2632#define mmCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2 2633#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075c 2634#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 2635#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075d 2636#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 2637#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075e 2638#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2 2639#define mmCURSOR0_1_DMDATA_ADDRESS_LOW 0x075f 2640#define mmCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2 2641#define mmCURSOR0_1_DMDATA_CNTL 0x0760 2642#define mmCURSOR0_1_DMDATA_CNTL_BASE_IDX 2 2643#define mmCURSOR0_1_DMDATA_QOS_CNTL 0x0761 2644#define mmCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2 2645#define mmCURSOR0_1_DMDATA_STATUS 0x0762 2646#define mmCURSOR0_1_DMDATA_STATUS_BASE_IDX 2 2647#define mmCURSOR0_1_DMDATA_SW_CNTL 0x0763 2648#define mmCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2 2649#define mmCURSOR0_1_DMDATA_SW_DATA 0x0764 2650#define mmCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2 2651 2652 2653// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 2654// base address: 0x1de4 2655#define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x0779 2656#define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2 2657#define mmDC_PERFMON7_PERFCOUNTER_CNTL2 0x077a 2658#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2 2659#define mmDC_PERFMON7_PERFCOUNTER_STATE 0x077b 2660#define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2 2661#define mmDC_PERFMON7_PERFMON_CNTL 0x077c 2662#define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2 2663#define mmDC_PERFMON7_PERFMON_CNTL2 0x077d 2664#define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2 2665#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x077e 2666#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 2667#define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x077f 2668#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2 2669#define mmDC_PERFMON7_PERFMON_HI 0x0780 2670#define mmDC_PERFMON7_PERFMON_HI_BASE_IDX 2 2671#define mmDC_PERFMON7_PERFMON_LOW 0x0781 2672#define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX 2 2673 2674 2675// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec 2676// base address: 0x6e0 2677#define mmHUBP2_DCSURF_SURFACE_CONFIG 0x079d 2678#define mmHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2679#define mmHUBP2_DCSURF_ADDR_CONFIG 0x079e 2680#define mmHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2 2681#define mmHUBP2_DCSURF_TILING_CONFIG 0x079f 2682#define mmHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2 2683#define mmHUBP2_DCSURF_PRI_VIEWPORT_START 0x07a1 2684#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2685#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a2 2686#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2687#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x07a3 2688#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2689#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07a4 2690#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2691#define mmHUBP2_DCSURF_SEC_VIEWPORT_START 0x07a5 2692#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2693#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x07a6 2694#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2695#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x07a7 2696#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2697#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07a8 2698#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2699#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x07a9 2700#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2701#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x07aa 2702#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2703#define mmHUBP2_DCHUBP_CNTL 0x07ab 2704#define mmHUBP2_DCHUBP_CNTL_BASE_IDX 2 2705#define mmHUBP2_HUBP_CLK_CNTL 0x07ac 2706#define mmHUBP2_HUBP_CLK_CNTL_BASE_IDX 2 2707#define mmHUBP2_DCHUBP_VMPG_CONFIG 0x07ad 2708#define mmHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2 2709#define mmHUBP2_HUBPREQ_DEBUG_DB 0x07ae 2710#define mmHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2 2711#define mmHUBP2_HUBPREQ_DEBUG 0x07af 2712#define mmHUBP2_HUBPREQ_DEBUG_BASE_IDX 2 2713#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07b3 2714#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 2715#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07b4 2716#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 2717 2718 2719// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec 2720// base address: 0x6e0 2721#define mmHUBPREQ2_DCSURF_SURFACE_PITCH 0x07bf 2722#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2 2723#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x07c0 2724#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 2725#define mmHUBPREQ2_VMID_SETTINGS_0 0x07c1 2726#define mmHUBPREQ2_VMID_SETTINGS_0_BASE_IDX 2 2727#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c2 2728#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 2729#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07c3 2730#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2731#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07c4 2732#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 2733#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07c5 2734#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2735#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07c6 2736#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 2737#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07c7 2738#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2739#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07c8 2740#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 2741#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07c9 2742#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2743#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07ca 2744#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 2745#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07cb 2746#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2747#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07cc 2748#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2749#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07cd 2750#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2751#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07ce 2752#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 2753#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07cf 2754#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2755#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d0 2756#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2757#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d1 2758#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2759#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL 0x07d2 2760#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2 2761#define mmHUBPREQ2_DCSURF_FLIP_CONTROL 0x07d3 2762#define mmHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2 2763#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2 0x07d4 2764#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2 2765#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x07d8 2766#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 2767#define mmHUBPREQ2_DCSURF_SURFACE_INUSE 0x07d9 2768#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2 2769#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x07da 2770#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 2771#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x07db 2772#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 2773#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x07dc 2774#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 2775#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x07dd 2776#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 2777#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07de 2778#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 2779#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07df 2780#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 2781#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07e0 2782#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 2783#define mmHUBPREQ2_DCN_EXPANSION_MODE 0x07e1 2784#define mmHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2 2785#define mmHUBPREQ2_DCN_TTU_QOS_WM 0x07e2 2786#define mmHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2 2787#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x07e3 2788#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 2789#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x07e4 2790#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 2791#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x07e5 2792#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 2793#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x07e6 2794#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 2795#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x07e7 2796#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 2797#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x07e8 2798#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 2799#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x07e9 2800#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 2801#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0 0x07ea 2802#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 2803#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1 0x07eb 2804#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 2805#define mmHUBPREQ2_DCN_DMDATA_VM_CNTL 0x07ec 2806#define mmHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX 2 2807#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x07ed 2808#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 2809#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x07ee 2810#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 2811#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x07fb 2812#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 2813#define mmHUBPREQ2_BLANK_OFFSET_0 0x07fc 2814#define mmHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2 2815#define mmHUBPREQ2_BLANK_OFFSET_1 0x07fd 2816#define mmHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2 2817#define mmHUBPREQ2_DST_DIMENSIONS 0x07fe 2818#define mmHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2 2819#define mmHUBPREQ2_DST_AFTER_SCALER 0x07ff 2820#define mmHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2 2821#define mmHUBPREQ2_PREFETCH_SETTINGS 0x0800 2822#define mmHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX 2 2823#define mmHUBPREQ2_PREFETCH_SETTINGS_C 0x0801 2824#define mmHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX 2 2825#define mmHUBPREQ2_VBLANK_PARAMETERS_0 0x0802 2826#define mmHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2 2827#define mmHUBPREQ2_VBLANK_PARAMETERS_1 0x0803 2828#define mmHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2 2829#define mmHUBPREQ2_VBLANK_PARAMETERS_2 0x0804 2830#define mmHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2 2831#define mmHUBPREQ2_VBLANK_PARAMETERS_3 0x0805 2832#define mmHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2 2833#define mmHUBPREQ2_VBLANK_PARAMETERS_4 0x0806 2834#define mmHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2 2835#define mmHUBPREQ2_FLIP_PARAMETERS_0 0x0807 2836#define mmHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX 2 2837#define mmHUBPREQ2_FLIP_PARAMETERS_1 0x0808 2838#define mmHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX 2 2839#define mmHUBPREQ2_FLIP_PARAMETERS_2 0x0809 2840#define mmHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX 2 2841#define mmHUBPREQ2_NOM_PARAMETERS_0 0x080a 2842#define mmHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2 2843#define mmHUBPREQ2_NOM_PARAMETERS_1 0x080b 2844#define mmHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2 2845#define mmHUBPREQ2_NOM_PARAMETERS_2 0x080c 2846#define mmHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2 2847#define mmHUBPREQ2_NOM_PARAMETERS_3 0x080d 2848#define mmHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2 2849#define mmHUBPREQ2_NOM_PARAMETERS_4 0x080e 2850#define mmHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2 2851#define mmHUBPREQ2_NOM_PARAMETERS_5 0x080f 2852#define mmHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2 2853#define mmHUBPREQ2_NOM_PARAMETERS_6 0x0810 2854#define mmHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2 2855#define mmHUBPREQ2_NOM_PARAMETERS_7 0x0811 2856#define mmHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2 2857#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0812 2858#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2 2859#define mmHUBPREQ2_PER_LINE_DELIVERY 0x0813 2860#define mmHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2 2861#define mmHUBPREQ2_CURSOR_SETTINGS 0x0814 2862#define mmHUBPREQ2_CURSOR_SETTINGS_BASE_IDX 2 2863#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0815 2864#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 2865#define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT 0x0816 2866#define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 2867#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0817 2868#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 2869#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x0818 2870#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 2871#define mmHUBPREQ2_VBLANK_PARAMETERS_5 0x081b 2872#define mmHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX 2 2873#define mmHUBPREQ2_VBLANK_PARAMETERS_6 0x081c 2874#define mmHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX 2 2875#define mmHUBPREQ2_FLIP_PARAMETERS_3 0x081d 2876#define mmHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX 2 2877#define mmHUBPREQ2_FLIP_PARAMETERS_4 0x081e 2878#define mmHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX 2 2879#define mmHUBPREQ2_FLIP_PARAMETERS_5 0x081f 2880#define mmHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX 2 2881#define mmHUBPREQ2_FLIP_PARAMETERS_6 0x0820 2882#define mmHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX 2 2883 2884 2885// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec 2886// base address: 0x6e0 2887#define mmHUBPRET2_HUBPRET_CONTROL 0x0824 2888#define mmHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2 2889#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0825 2890#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 2891#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x0826 2892#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 2893#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x0827 2894#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 2895#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x0828 2896#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 2897#define mmHUBPRET2_HUBPRET_READ_LINE0 0x0829 2898#define mmHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2 2899#define mmHUBPRET2_HUBPRET_READ_LINE1 0x082a 2900#define mmHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2 2901#define mmHUBPRET2_HUBPRET_INTERRUPT 0x082b 2902#define mmHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2 2903#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE 0x082c 2904#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 2905#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS 0x082d 2906#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 2907 2908 2909// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec 2910// base address: 0x6e0 2911#define mmCURSOR0_2_CURSOR_CONTROL 0x0830 2912#define mmCURSOR0_2_CURSOR_CONTROL_BASE_IDX 2 2913#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS 0x0831 2914#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 2915#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH 0x0832 2916#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2917#define mmCURSOR0_2_CURSOR_SIZE 0x0833 2918#define mmCURSOR0_2_CURSOR_SIZE_BASE_IDX 2 2919#define mmCURSOR0_2_CURSOR_POSITION 0x0834 2920#define mmCURSOR0_2_CURSOR_POSITION_BASE_IDX 2 2921#define mmCURSOR0_2_CURSOR_HOT_SPOT 0x0835 2922#define mmCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX 2 2923#define mmCURSOR0_2_CURSOR_STEREO_CONTROL 0x0836 2924#define mmCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX 2 2925#define mmCURSOR0_2_CURSOR_DST_OFFSET 0x0837 2926#define mmCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX 2 2927#define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL 0x0838 2928#define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 2929#define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS 0x0839 2930#define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 2931#define mmCURSOR0_2_DMDATA_ADDRESS_HIGH 0x083a 2932#define mmCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX 2 2933#define mmCURSOR0_2_DMDATA_ADDRESS_LOW 0x083b 2934#define mmCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX 2 2935#define mmCURSOR0_2_DMDATA_CNTL 0x083c 2936#define mmCURSOR0_2_DMDATA_CNTL_BASE_IDX 2 2937#define mmCURSOR0_2_DMDATA_QOS_CNTL 0x083d 2938#define mmCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX 2 2939#define mmCURSOR0_2_DMDATA_STATUS 0x083e 2940#define mmCURSOR0_2_DMDATA_STATUS_BASE_IDX 2 2941#define mmCURSOR0_2_DMDATA_SW_CNTL 0x083f 2942#define mmCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX 2 2943#define mmCURSOR0_2_DMDATA_SW_DATA 0x0840 2944#define mmCURSOR0_2_DMDATA_SW_DATA_BASE_IDX 2 2945 2946 2947// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 2948// base address: 0x2154 2949#define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x0855 2950#define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2 2951#define mmDC_PERFMON8_PERFCOUNTER_CNTL2 0x0856 2952#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2 2953#define mmDC_PERFMON8_PERFCOUNTER_STATE 0x0857 2954#define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2 2955#define mmDC_PERFMON8_PERFMON_CNTL 0x0858 2956#define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2 2957#define mmDC_PERFMON8_PERFMON_CNTL2 0x0859 2958#define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2 2959#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x085a 2960#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 2961#define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x085b 2962#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2 2963#define mmDC_PERFMON8_PERFMON_HI 0x085c 2964#define mmDC_PERFMON8_PERFMON_HI_BASE_IDX 2 2965#define mmDC_PERFMON8_PERFMON_LOW 0x085d 2966#define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX 2 2967 2968 2969// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec 2970// base address: 0xa50 2971#define mmHUBP3_DCSURF_SURFACE_CONFIG 0x0879 2972#define mmHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2973#define mmHUBP3_DCSURF_ADDR_CONFIG 0x087a 2974#define mmHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2 2975#define mmHUBP3_DCSURF_TILING_CONFIG 0x087b 2976#define mmHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2 2977#define mmHUBP3_DCSURF_PRI_VIEWPORT_START 0x087d 2978#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2979#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x087e 2980#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2981#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x087f 2982#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2983#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0880 2984#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2985#define mmHUBP3_DCSURF_SEC_VIEWPORT_START 0x0881 2986#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2987#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x0882 2988#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2989#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x0883 2990#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2991#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0884 2992#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2993#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x0885 2994#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2995#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x0886 2996#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2997#define mmHUBP3_DCHUBP_CNTL 0x0887 2998#define mmHUBP3_DCHUBP_CNTL_BASE_IDX 2 2999#define mmHUBP3_HUBP_CLK_CNTL 0x0888 3000#define mmHUBP3_HUBP_CLK_CNTL_BASE_IDX 2
3001#define mmHUBP3_DCHUBP_VMPG_CONFIG 0x0889 3002#define mmHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2 3003#define mmHUBP3_HUBPREQ_DEBUG_DB 0x088a 3004#define mmHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2 3005#define mmHUBP3_HUBPREQ_DEBUG 0x088b 3006#define mmHUBP3_HUBPREQ_DEBUG_BASE_IDX 2 3007#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x088f 3008#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 3009#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0890 3010#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 3011 3012 3013// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec 3014// base address: 0xa50 3015#define mmHUBPREQ3_DCSURF_SURFACE_PITCH 0x089b 3016#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2 3017#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x089c 3018#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 3019#define mmHUBPREQ3_VMID_SETTINGS_0 0x089d 3020#define mmHUBPREQ3_VMID_SETTINGS_0_BASE_IDX 2 3021#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x089e 3022#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 3023#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x089f 3024#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3025#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x08a0 3026#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 3027#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x08a1 3028#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3029#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x08a2 3030#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 3031#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x08a3 3032#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3033#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x08a4 3034#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 3035#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x08a5 3036#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3037#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x08a6 3038#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 3039#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x08a7 3040#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3041#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x08a8 3042#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3043#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x08a9 3044#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3045#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x08aa 3046#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 3047#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x08ab 3048#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3049#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x08ac 3050#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3051#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x08ad 3052#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3053#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL 0x08ae 3054#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2 3055#define mmHUBPREQ3_DCSURF_FLIP_CONTROL 0x08af 3056#define mmHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2 3057#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2 0x08b0 3058#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2 3059#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x08b4 3060#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 3061#define mmHUBPREQ3_DCSURF_SURFACE_INUSE 0x08b5 3062#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2 3063#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x08b6 3064#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 3065#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x08b7 3066#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 3067#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x08b8 3068#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 3069#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x08b9 3070#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 3071#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x08ba 3072#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 3073#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x08bb 3074#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 3075#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x08bc 3076#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 3077#define mmHUBPREQ3_DCN_EXPANSION_MODE 0x08bd 3078#define mmHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2 3079#define mmHUBPREQ3_DCN_TTU_QOS_WM 0x08be 3080#define mmHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2 3081#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x08bf 3082#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 3083#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x08c0 3084#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 3085#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x08c1 3086#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 3087#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x08c2 3088#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 3089#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x08c3 3090#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 3091#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x08c4 3092#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 3093#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x08c5 3094#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 3095#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL0 0x08c6 3096#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 3097#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL1 0x08c7 3098#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 3099#define mmHUBPREQ3_DCN_DMDATA_VM_CNTL 0x08c8 3100#define mmHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX 2 3101#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x08c9 3102#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 3103#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08ca 3104#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 3105#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x08d7 3106#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 3107#define mmHUBPREQ3_BLANK_OFFSET_0 0x08d8 3108#define mmHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2 3109#define mmHUBPREQ3_BLANK_OFFSET_1 0x08d9 3110#define mmHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2 3111#define mmHUBPREQ3_DST_DIMENSIONS 0x08da 3112#define mmHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2 3113#define mmHUBPREQ3_DST_AFTER_SCALER 0x08db 3114#define mmHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2 3115#define mmHUBPREQ3_PREFETCH_SETTINGS 0x08dc 3116#define mmHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX 2 3117#define mmHUBPREQ3_PREFETCH_SETTINGS_C 0x08dd 3118#define mmHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX 2 3119#define mmHUBPREQ3_VBLANK_PARAMETERS_0 0x08de 3120#define mmHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2 3121#define mmHUBPREQ3_VBLANK_PARAMETERS_1 0x08df 3122#define mmHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2 3123#define mmHUBPREQ3_VBLANK_PARAMETERS_2 0x08e0 3124#define mmHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2 3125#define mmHUBPREQ3_VBLANK_PARAMETERS_3 0x08e1 3126#define mmHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2 3127#define mmHUBPREQ3_VBLANK_PARAMETERS_4 0x08e2 3128#define mmHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2 3129#define mmHUBPREQ3_FLIP_PARAMETERS_0 0x08e3 3130#define mmHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX 2 3131#define mmHUBPREQ3_FLIP_PARAMETERS_1 0x08e4 3132#define mmHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX 2 3133#define mmHUBPREQ3_FLIP_PARAMETERS_2 0x08e5 3134#define mmHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX 2 3135#define mmHUBPREQ3_NOM_PARAMETERS_0 0x08e6 3136#define mmHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2 3137#define mmHUBPREQ3_NOM_PARAMETERS_1 0x08e7 3138#define mmHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2 3139#define mmHUBPREQ3_NOM_PARAMETERS_2 0x08e8 3140#define mmHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2 3141#define mmHUBPREQ3_NOM_PARAMETERS_3 0x08e9 3142#define mmHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2 3143#define mmHUBPREQ3_NOM_PARAMETERS_4 0x08ea 3144#define mmHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2 3145#define mmHUBPREQ3_NOM_PARAMETERS_5 0x08eb 3146#define mmHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2 3147#define mmHUBPREQ3_NOM_PARAMETERS_6 0x08ec 3148#define mmHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2 3149#define mmHUBPREQ3_NOM_PARAMETERS_7 0x08ed 3150#define mmHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2 3151#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE 0x08ee 3152#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2 3153#define mmHUBPREQ3_PER_LINE_DELIVERY 0x08ef 3154#define mmHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2 3155#define mmHUBPREQ3_CURSOR_SETTINGS 0x08f0 3156#define mmHUBPREQ3_CURSOR_SETTINGS_BASE_IDX 2 3157#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x08f1 3158#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 3159#define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT 0x08f2 3160#define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 3161#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x08f3 3162#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 3163#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x08f4 3164#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 3165#define mmHUBPREQ3_VBLANK_PARAMETERS_5 0x08f7 3166#define mmHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX 2 3167#define mmHUBPREQ3_VBLANK_PARAMETERS_6 0x08f8 3168#define mmHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX 2 3169#define mmHUBPREQ3_FLIP_PARAMETERS_3 0x08f9 3170#define mmHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX 2 3171#define mmHUBPREQ3_FLIP_PARAMETERS_4 0x08fa 3172#define mmHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX 2 3173#define mmHUBPREQ3_FLIP_PARAMETERS_5 0x08fb 3174#define mmHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX 2 3175#define mmHUBPREQ3_FLIP_PARAMETERS_6 0x08fc 3176#define mmHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX 2 3177 3178 3179// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec 3180// base address: 0xa50 3181#define mmHUBPRET3_HUBPRET_CONTROL 0x0900 3182#define mmHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2 3183#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x0901 3184#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 3185#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x0902 3186#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 3187#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x0903 3188#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 3189#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0904 3190#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 3191#define mmHUBPRET3_HUBPRET_READ_LINE0 0x0905 3192#define mmHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2 3193#define mmHUBPRET3_HUBPRET_READ_LINE1 0x0906 3194#define mmHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2 3195#define mmHUBPRET3_HUBPRET_INTERRUPT 0x0907 3196#define mmHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2 3197#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0908 3198#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 3199#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0909 3200#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 3201 3202 3203// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec 3204// base address: 0xa50 3205#define mmCURSOR0_3_CURSOR_CONTROL 0x090c 3206#define mmCURSOR0_3_CURSOR_CONTROL_BASE_IDX 2 3207#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS 0x090d 3208#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 3209#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH 0x090e 3210#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3211#define mmCURSOR0_3_CURSOR_SIZE 0x090f 3212#define mmCURSOR0_3_CURSOR_SIZE_BASE_IDX 2 3213#define mmCURSOR0_3_CURSOR_POSITION 0x0910 3214#define mmCURSOR0_3_CURSOR_POSITION_BASE_IDX 2 3215#define mmCURSOR0_3_CURSOR_HOT_SPOT 0x0911 3216#define mmCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX 2 3217#define mmCURSOR0_3_CURSOR_STEREO_CONTROL 0x0912 3218#define mmCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX 2 3219#define mmCURSOR0_3_CURSOR_DST_OFFSET 0x0913 3220#define mmCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX 2 3221#define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL 0x0914 3222#define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 3223#define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS 0x0915 3224#define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 3225#define mmCURSOR0_3_DMDATA_ADDRESS_HIGH 0x0916 3226#define mmCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX 2 3227#define mmCURSOR0_3_DMDATA_ADDRESS_LOW 0x0917 3228#define mmCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX 2 3229#define mmCURSOR0_3_DMDATA_CNTL 0x0918 3230#define mmCURSOR0_3_DMDATA_CNTL_BASE_IDX 2 3231#define mmCURSOR0_3_DMDATA_QOS_CNTL 0x0919 3232#define mmCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX 2 3233#define mmCURSOR0_3_DMDATA_STATUS 0x091a 3234#define mmCURSOR0_3_DMDATA_STATUS_BASE_IDX 2 3235#define mmCURSOR0_3_DMDATA_SW_CNTL 0x091b 3236#define mmCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX 2 3237#define mmCURSOR0_3_DMDATA_SW_DATA 0x091c 3238#define mmCURSOR0_3_DMDATA_SW_DATA_BASE_IDX 2 3239 3240 3241// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 3242// base address: 0x24c4 3243#define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x0931 3244#define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2 3245#define mmDC_PERFMON9_PERFCOUNTER_CNTL2 0x0932 3246#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2 3247#define mmDC_PERFMON9_PERFCOUNTER_STATE 0x0933 3248#define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2 3249#define mmDC_PERFMON9_PERFMON_CNTL 0x0934 3250#define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2 3251#define mmDC_PERFMON9_PERFMON_CNTL2 0x0935 3252#define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2 3253#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x0936 3254#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3255#define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x0937 3256#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2 3257#define mmDC_PERFMON9_PERFMON_HI 0x0938 3258#define mmDC_PERFMON9_PERFMON_HI_BASE_IDX 2 3259#define mmDC_PERFMON9_PERFMON_LOW 0x0939 3260#define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX 2 3261 3262 3263// addressBlock: dce_dc_dcbubp4_dispdec_hubp_dispdec 3264// base address: 0xdc0 3265#define mmHUBP4_DCSURF_SURFACE_CONFIG 0x0955 3266#define mmHUBP4_DCSURF_SURFACE_CONFIG_BASE_IDX 2 3267#define mmHUBP4_DCSURF_ADDR_CONFIG 0x0956 3268#define mmHUBP4_DCSURF_ADDR_CONFIG_BASE_IDX 2 3269#define mmHUBP4_DCSURF_TILING_CONFIG 0x0957 3270#define mmHUBP4_DCSURF_TILING_CONFIG_BASE_IDX 2 3271#define mmHUBP4_DCSURF_PRI_VIEWPORT_START 0x0959 3272#define mmHUBP4_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 3273#define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION 0x095a 3274#define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 3275#define mmHUBP4_DCSURF_PRI_VIEWPORT_START_C 0x095b 3276#define mmHUBP4_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 3277#define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x095c 3278#define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 3279#define mmHUBP4_DCSURF_SEC_VIEWPORT_START 0x095d 3280#define mmHUBP4_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 3281#define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION 0x095e 3282#define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 3283#define mmHUBP4_DCSURF_SEC_VIEWPORT_START_C 0x095f 3284#define mmHUBP4_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 3285#define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0960 3286#define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 3287#define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG 0x0961 3288#define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 3289#define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG_C 0x0962 3290#define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 3291#define mmHUBP4_DCHUBP_CNTL 0x0963 3292#define mmHUBP4_DCHUBP_CNTL_BASE_IDX 2 3293#define mmHUBP4_HUBP_CLK_CNTL 0x0964 3294#define mmHUBP4_HUBP_CLK_CNTL_BASE_IDX 2 3295#define mmHUBP4_DCHUBP_VMPG_CONFIG 0x0965 3296#define mmHUBP4_DCHUBP_VMPG_CONFIG_BASE_IDX 2 3297#define mmHUBP4_HUBPREQ_DEBUG_DB 0x0966 3298#define mmHUBP4_HUBPREQ_DEBUG_DB_BASE_IDX 2 3299#define mmHUBP4_HUBPREQ_DEBUG 0x0967 3300#define mmHUBP4_HUBPREQ_DEBUG_BASE_IDX 2 3301#define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x096b 3302#define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 3303#define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x096c 3304#define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 3305 3306 3307// addressBlock: dce_dc_dcbubp4_dispdec_hubpreq_dispdec 3308// base address: 0xdc0 3309#define mmHUBPREQ4_DCSURF_SURFACE_PITCH 0x0977 3310#define mmHUBPREQ4_DCSURF_SURFACE_PITCH_BASE_IDX 2 3311#define mmHUBPREQ4_DCSURF_SURFACE_PITCH_C 0x0978 3312#define mmHUBPREQ4_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 3313#define mmHUBPREQ4_VMID_SETTINGS_0 0x0979 3314#define mmHUBPREQ4_VMID_SETTINGS_0_BASE_IDX 2 3315#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS 0x097a 3316#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 3317#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x097b 3318#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3319#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x097c 3320#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 3321#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x097d 3322#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3323#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS 0x097e 3324#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 3325#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x097f 3326#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3327#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0980 3328#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 3329#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0981 3330#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3331#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0982 3332#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 3333#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0983 3334#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3335#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0984 3336#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3337#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0985 3338#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3339#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0986 3340#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 3341#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0987 3342#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3343#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0988 3344#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3345#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0989 3346#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3347#define mmHUBPREQ4_DCSURF_SURFACE_CONTROL 0x098a 3348#define mmHUBPREQ4_DCSURF_SURFACE_CONTROL_BASE_IDX 2 3349#define mmHUBPREQ4_DCSURF_FLIP_CONTROL 0x098b 3350#define mmHUBPREQ4_DCSURF_FLIP_CONTROL_BASE_IDX 2 3351#define mmHUBPREQ4_DCSURF_FLIP_CONTROL2 0x098c 3352#define mmHUBPREQ4_DCSURF_FLIP_CONTROL2_BASE_IDX 2 3353#define mmHUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT 0x0990 3354#define mmHUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 3355#define mmHUBPREQ4_DCSURF_SURFACE_INUSE 0x0991 3356#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_BASE_IDX 2 3357#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH 0x0992 3358#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 3359#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_C 0x0993 3360#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 3361#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH_C 0x0994 3362#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 3363#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE 0x0995 3364#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 3365#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0996 3366#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 3367#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0997 3368#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 3369#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0998 3370#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 3371#define mmHUBPREQ4_DCN_EXPANSION_MODE 0x0999 3372#define mmHUBPREQ4_DCN_EXPANSION_MODE_BASE_IDX 2 3373#define mmHUBPREQ4_DCN_TTU_QOS_WM 0x099a 3374#define mmHUBPREQ4_DCN_TTU_QOS_WM_BASE_IDX 2 3375#define mmHUBPREQ4_DCN_GLOBAL_TTU_CNTL 0x099b 3376#define mmHUBPREQ4_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 3377#define mmHUBPREQ4_DCN_SURF0_TTU_CNTL0 0x099c 3378#define mmHUBPREQ4_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 3379#define mmHUBPREQ4_DCN_SURF0_TTU_CNTL1 0x099d 3380#define mmHUBPREQ4_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 3381#define mmHUBPREQ4_DCN_SURF1_TTU_CNTL0 0x099e 3382#define mmHUBPREQ4_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 3383#define mmHUBPREQ4_DCN_SURF1_TTU_CNTL1 0x099f 3384#define mmHUBPREQ4_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 3385#define mmHUBPREQ4_DCN_CUR0_TTU_CNTL0 0x09a0 3386#define mmHUBPREQ4_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 3387#define mmHUBPREQ4_DCN_CUR0_TTU_CNTL1 0x09a1 3388#define mmHUBPREQ4_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 3389#define mmHUBPREQ4_DCN_CUR1_TTU_CNTL0 0x09a2 3390#define mmHUBPREQ4_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 3391#define mmHUBPREQ4_DCN_CUR1_TTU_CNTL1 0x09a3 3392#define mmHUBPREQ4_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 3393#define mmHUBPREQ4_DCN_DMDATA_VM_CNTL 0x09a4 3394#define mmHUBPREQ4_DCN_DMDATA_VM_CNTL_BASE_IDX 2 3395#define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x09a5 3396#define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 3397#define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x09a6 3398#define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 3399#define mmHUBPREQ4_DCN_VM_MX_L1_TLB_CNTL 0x09b3 3400#define mmHUBPREQ4_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 3401#define mmHUBPREQ4_BLANK_OFFSET_0 0x09b4 3402#define mmHUBPREQ4_BLANK_OFFSET_0_BASE_IDX 2 3403#define mmHUBPREQ4_BLANK_OFFSET_1 0x09b5 3404#define mmHUBPREQ4_BLANK_OFFSET_1_BASE_IDX 2 3405#define mmHUBPREQ4_DST_DIMENSIONS 0x09b6 3406#define mmHUBPREQ4_DST_DIMENSIONS_BASE_IDX 2 3407#define mmHUBPREQ4_DST_AFTER_SCALER 0x09b7 3408#define mmHUBPREQ4_DST_AFTER_SCALER_BASE_IDX 2 3409#define mmHUBPREQ4_PREFETCH_SETTINGS 0x09b8 3410#define mmHUBPREQ4_PREFETCH_SETTINGS_BASE_IDX 2 3411#define mmHUBPREQ4_PREFETCH_SETTINGS_C 0x09b9 3412#define mmHUBPREQ4_PREFETCH_SETTINGS_C_BASE_IDX 2 3413#define mmHUBPREQ4_VBLANK_PARAMETERS_0 0x09ba 3414#define mmHUBPREQ4_VBLANK_PARAMETERS_0_BASE_IDX 2 3415#define mmHUBPREQ4_VBLANK_PARAMETERS_1 0x09bb 3416#define mmHUBPREQ4_VBLANK_PARAMETERS_1_BASE_IDX 2 3417#define mmHUBPREQ4_VBLANK_PARAMETERS_2 0x09bc 3418#define mmHUBPREQ4_VBLANK_PARAMETERS_2_BASE_IDX 2 3419#define mmHUBPREQ4_VBLANK_PARAMETERS_3 0x09bd 3420#define mmHUBPREQ4_VBLANK_PARAMETERS_3_BASE_IDX 2 3421#define mmHUBPREQ4_VBLANK_PARAMETERS_4 0x09be 3422#define mmHUBPREQ4_VBLANK_PARAMETERS_4_BASE_IDX 2 3423#define mmHUBPREQ4_FLIP_PARAMETERS_0 0x09bf 3424#define mmHUBPREQ4_FLIP_PARAMETERS_0_BASE_IDX 2 3425#define mmHUBPREQ4_FLIP_PARAMETERS_1 0x09c0 3426#define mmHUBPREQ4_FLIP_PARAMETERS_1_BASE_IDX 2 3427#define mmHUBPREQ4_FLIP_PARAMETERS_2 0x09c1 3428#define mmHUBPREQ4_FLIP_PARAMETERS_2_BASE_IDX 2 3429#define mmHUBPREQ4_NOM_PARAMETERS_0 0x09c2 3430#define mmHUBPREQ4_NOM_PARAMETERS_0_BASE_IDX 2 3431#define mmHUBPREQ4_NOM_PARAMETERS_1 0x09c3 3432#define mmHUBPREQ4_NOM_PARAMETERS_1_BASE_IDX 2 3433#define mmHUBPREQ4_NOM_PARAMETERS_2 0x09c4 3434#define mmHUBPREQ4_NOM_PARAMETERS_2_BASE_IDX 2 3435#define mmHUBPREQ4_NOM_PARAMETERS_3 0x09c5 3436#define mmHUBPREQ4_NOM_PARAMETERS_3_BASE_IDX 2 3437#define mmHUBPREQ4_NOM_PARAMETERS_4 0x09c6 3438#define mmHUBPREQ4_NOM_PARAMETERS_4_BASE_IDX 2 3439#define mmHUBPREQ4_NOM_PARAMETERS_5 0x09c7 3440#define mmHUBPREQ4_NOM_PARAMETERS_5_BASE_IDX 2 3441#define mmHUBPREQ4_NOM_PARAMETERS_6 0x09c8 3442#define mmHUBPREQ4_NOM_PARAMETERS_6_BASE_IDX 2 3443#define mmHUBPREQ4_NOM_PARAMETERS_7 0x09c9 3444#define mmHUBPREQ4_NOM_PARAMETERS_7_BASE_IDX 2 3445#define mmHUBPREQ4_PER_LINE_DELIVERY_PRE 0x09ca 3446#define mmHUBPREQ4_PER_LINE_DELIVERY_PRE_BASE_IDX 2 3447#define mmHUBPREQ4_PER_LINE_DELIVERY 0x09cb 3448#define mmHUBPREQ4_PER_LINE_DELIVERY_BASE_IDX 2 3449#define mmHUBPREQ4_CURSOR_SETTINGS 0x09cc 3450#define mmHUBPREQ4_CURSOR_SETTINGS_BASE_IDX 2 3451#define mmHUBPREQ4_REF_FREQ_TO_PIX_FREQ 0x09cd 3452#define mmHUBPREQ4_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 3453#define mmHUBPREQ4_DST_Y_DELTA_DRQ_LIMIT 0x09ce 3454#define mmHUBPREQ4_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 3455#define mmHUBPREQ4_HUBPREQ_MEM_PWR_CTRL 0x09cf 3456#define mmHUBPREQ4_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 3457#define mmHUBPREQ4_HUBPREQ_MEM_PWR_STATUS 0x09d0 3458#define mmHUBPREQ4_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 3459#define mmHUBPREQ4_VBLANK_PARAMETERS_5 0x09d3 3460#define mmHUBPREQ4_VBLANK_PARAMETERS_5_BASE_IDX 2 3461#define mmHUBPREQ4_VBLANK_PARAMETERS_6 0x09d4 3462#define mmHUBPREQ4_VBLANK_PARAMETERS_6_BASE_IDX 2 3463#define mmHUBPREQ4_FLIP_PARAMETERS_3 0x09d5 3464#define mmHUBPREQ4_FLIP_PARAMETERS_3_BASE_IDX 2 3465#define mmHUBPREQ4_FLIP_PARAMETERS_4 0x09d6 3466#define mmHUBPREQ4_FLIP_PARAMETERS_4_BASE_IDX 2 3467#define mmHUBPREQ4_FLIP_PARAMETERS_5 0x09d7 3468#define mmHUBPREQ4_FLIP_PARAMETERS_5_BASE_IDX 2 3469#define mmHUBPREQ4_FLIP_PARAMETERS_6 0x09d8 3470#define mmHUBPREQ4_FLIP_PARAMETERS_6_BASE_IDX 2 3471 3472 3473// addressBlock: dce_dc_dcbubp4_dispdec_hubpret_dispdec 3474// base address: 0xdc0 3475#define mmHUBPRET4_HUBPRET_CONTROL 0x09dc 3476#define mmHUBPRET4_HUBPRET_CONTROL_BASE_IDX 2 3477#define mmHUBPRET4_HUBPRET_MEM_PWR_CTRL 0x09dd 3478#define mmHUBPRET4_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 3479#define mmHUBPRET4_HUBPRET_MEM_PWR_STATUS 0x09de 3480#define mmHUBPRET4_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 3481#define mmHUBPRET4_HUBPRET_READ_LINE_CTRL0 0x09df 3482#define mmHUBPRET4_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 3483#define mmHUBPRET4_HUBPRET_READ_LINE_CTRL1 0x09e0 3484#define mmHUBPRET4_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 3485#define mmHUBPRET4_HUBPRET_READ_LINE0 0x09e1 3486#define mmHUBPRET4_HUBPRET_READ_LINE0_BASE_IDX 2 3487#define mmHUBPRET4_HUBPRET_READ_LINE1 0x09e2 3488#define mmHUBPRET4_HUBPRET_READ_LINE1_BASE_IDX 2 3489#define mmHUBPRET4_HUBPRET_INTERRUPT 0x09e3 3490#define mmHUBPRET4_HUBPRET_INTERRUPT_BASE_IDX 2 3491#define mmHUBPRET4_HUBPRET_READ_LINE_VALUE 0x09e4 3492#define mmHUBPRET4_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 3493#define mmHUBPRET4_HUBPRET_READ_LINE_STATUS 0x09e5 3494#define mmHUBPRET4_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 3495 3496 3497// addressBlock: dce_dc_dcbubp4_dispdec_cursor0_dispdec 3498// base address: 0xdc0 3499#define mmCURSOR0_4_CURSOR_CONTROL 0x09e8 3500#define mmCURSOR0_4_CURSOR_CONTROL_BASE_IDX 2 3501#define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS 0x09e9 3502#define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 3503#define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS_HIGH 0x09ea 3504#define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3505#define mmCURSOR0_4_CURSOR_SIZE 0x09eb 3506#define mmCURSOR0_4_CURSOR_SIZE_BASE_IDX 2 3507#define mmCURSOR0_4_CURSOR_POSITION 0x09ec 3508#define mmCURSOR0_4_CURSOR_POSITION_BASE_IDX 2 3509#define mmCURSOR0_4_CURSOR_HOT_SPOT 0x09ed 3510#define mmCURSOR0_4_CURSOR_HOT_SPOT_BASE_IDX 2 3511#define mmCURSOR0_4_CURSOR_STEREO_CONTROL 0x09ee 3512#define mmCURSOR0_4_CURSOR_STEREO_CONTROL_BASE_IDX 2 3513#define mmCURSOR0_4_CURSOR_DST_OFFSET 0x09ef 3514#define mmCURSOR0_4_CURSOR_DST_OFFSET_BASE_IDX 2 3515#define mmCURSOR0_4_CURSOR_MEM_PWR_CTRL 0x09f0 3516#define mmCURSOR0_4_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 3517#define mmCURSOR0_4_CURSOR_MEM_PWR_STATUS 0x09f1 3518#define mmCURSOR0_4_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 3519#define mmCURSOR0_4_DMDATA_ADDRESS_HIGH 0x09f2 3520#define mmCURSOR0_4_DMDATA_ADDRESS_HIGH_BASE_IDX 2 3521#define mmCURSOR0_4_DMDATA_ADDRESS_LOW 0x09f3 3522#define mmCURSOR0_4_DMDATA_ADDRESS_LOW_BASE_IDX 2 3523#define mmCURSOR0_4_DMDATA_CNTL 0x09f4 3524#define mmCURSOR0_4_DMDATA_CNTL_BASE_IDX 2 3525#define mmCURSOR0_4_DMDATA_QOS_CNTL 0x09f5 3526#define mmCURSOR0_4_DMDATA_QOS_CNTL_BASE_IDX 2 3527#define mmCURSOR0_4_DMDATA_STATUS 0x09f6 3528#define mmCURSOR0_4_DMDATA_STATUS_BASE_IDX 2 3529#define mmCURSOR0_4_DMDATA_SW_CNTL 0x09f7 3530#define mmCURSOR0_4_DMDATA_SW_CNTL_BASE_IDX 2 3531#define mmCURSOR0_4_DMDATA_SW_DATA 0x09f8 3532#define mmCURSOR0_4_DMDATA_SW_DATA_BASE_IDX 2 3533 3534 3535// addressBlock: dce_dc_dcbubp4_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 3536// base address: 0x2834 3537#define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x0a0d 3538#define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2 3539#define mmDC_PERFMON10_PERFCOUNTER_CNTL2 0x0a0e 3540#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2 3541#define mmDC_PERFMON10_PERFCOUNTER_STATE 0x0a0f 3542#define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2 3543#define mmDC_PERFMON10_PERFMON_CNTL 0x0a10 3544#define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2 3545#define mmDC_PERFMON10_PERFMON_CNTL2 0x0a11 3546#define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2 3547#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x0a12 3548#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3549#define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x0a13 3550#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2 3551#define mmDC_PERFMON10_PERFMON_HI 0x0a14 3552#define mmDC_PERFMON10_PERFMON_HI_BASE_IDX 2 3553#define mmDC_PERFMON10_PERFMON_LOW 0x0a15 3554#define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX 2 3555 3556 3557// addressBlock: dce_dc_dcbubp5_dispdec_hubp_dispdec 3558// base address: 0x1130 3559#define mmHUBP5_DCSURF_SURFACE_CONFIG 0x0a31 3560#define mmHUBP5_DCSURF_SURFACE_CONFIG_BASE_IDX 2 3561#define mmHUBP5_DCSURF_ADDR_CONFIG 0x0a32 3562#define mmHUBP5_DCSURF_ADDR_CONFIG_BASE_IDX 2 3563#define mmHUBP5_DCSURF_TILING_CONFIG 0x0a33 3564#define mmHUBP5_DCSURF_TILING_CONFIG_BASE_IDX 2 3565#define mmHUBP5_DCSURF_PRI_VIEWPORT_START 0x0a35 3566#define mmHUBP5_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 3567#define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION 0x0a36 3568#define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 3569#define mmHUBP5_DCSURF_PRI_VIEWPORT_START_C 0x0a37 3570#define mmHUBP5_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 3571#define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0a38 3572#define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 3573#define mmHUBP5_DCSURF_SEC_VIEWPORT_START 0x0a39 3574#define mmHUBP5_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 3575#define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION 0x0a3a 3576#define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 3577#define mmHUBP5_DCSURF_SEC_VIEWPORT_START_C 0x0a3b 3578#define mmHUBP5_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 3579#define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0a3c 3580#define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 3581#define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG 0x0a3d 3582#define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 3583#define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG_C 0x0a3e 3584#define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 3585#define mmHUBP5_DCHUBP_CNTL 0x0a3f 3586#define mmHUBP5_DCHUBP_CNTL_BASE_IDX 2 3587#define mmHUBP5_HUBP_CLK_CNTL 0x0a40 3588#define mmHUBP5_HUBP_CLK_CNTL_BASE_IDX 2 3589#define mmHUBP5_DCHUBP_VMPG_CONFIG 0x0a41 3590#define mmHUBP5_DCHUBP_VMPG_CONFIG_BASE_IDX 2 3591#define mmHUBP5_HUBPREQ_DEBUG_DB 0x0a42 3592#define mmHUBP5_HUBPREQ_DEBUG_DB_BASE_IDX 2 3593#define mmHUBP5_HUBPREQ_DEBUG 0x0a43 3594#define mmHUBP5_HUBPREQ_DEBUG_BASE_IDX 2 3595#define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x0a47 3596#define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 3597#define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0a48 3598#define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 3599 3600 3601// addressBlock: dce_dc_dcbubp5_dispdec_hubpreq_dispdec 3602// base address: 0x1130 3603#define mmHUBPREQ5_DCSURF_SURFACE_PITCH 0x0a53 3604#define mmHUBPREQ5_DCSURF_SURFACE_PITCH_BASE_IDX 2 3605#define mmHUBPREQ5_DCSURF_SURFACE_PITCH_C 0x0a54 3606#define mmHUBPREQ5_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 3607#define mmHUBPREQ5_VMID_SETTINGS_0 0x0a55 3608#define mmHUBPREQ5_VMID_SETTINGS_0_BASE_IDX 2 3609#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS 0x0a56 3610#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 3611#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x0a57 3612#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3613#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x0a58 3614#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 3615#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x0a59 3616#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3617#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS 0x0a5a 3618#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 3619#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x0a5b 3620#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3621#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0a5c 3622#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 3623#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0a5d 3624#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3625#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0a5e 3626#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 3627#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0a5f 3628#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3629#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0a60 3630#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3631#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0a61 3632#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3633#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0a62 3634#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 3635#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0a63 3636#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3637#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0a64 3638#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3639#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0a65 3640#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3641#define mmHUBPREQ5_DCSURF_SURFACE_CONTROL 0x0a66 3642#define mmHUBPREQ5_DCSURF_SURFACE_CONTROL_BASE_IDX 2 3643#define mmHUBPREQ5_DCSURF_FLIP_CONTROL 0x0a67 3644#define mmHUBPREQ5_DCSURF_FLIP_CONTROL_BASE_IDX 2 3645#define mmHUBPREQ5_DCSURF_FLIP_CONTROL2 0x0a68 3646#define mmHUBPREQ5_DCSURF_FLIP_CONTROL2_BASE_IDX 2 3647#define mmHUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT 0x0a6c 3648#define mmHUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 3649#define mmHUBPREQ5_DCSURF_SURFACE_INUSE 0x0a6d 3650#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_BASE_IDX 2 3651#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH 0x0a6e 3652#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 3653#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_C 0x0a6f 3654#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 3655#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH_C 0x0a70 3656#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 3657#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE 0x0a71 3658#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 3659#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0a72 3660#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 3661#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0a73 3662#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 3663#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0a74 3664#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 3665#define mmHUBPREQ5_DCN_EXPANSION_MODE 0x0a75 3666#define mmHUBPREQ5_DCN_EXPANSION_MODE_BASE_IDX 2 3667#define mmHUBPREQ5_DCN_TTU_QOS_WM 0x0a76 3668#define mmHUBPREQ5_DCN_TTU_QOS_WM_BASE_IDX 2 3669#define mmHUBPREQ5_DCN_GLOBAL_TTU_CNTL 0x0a77 3670#define mmHUBPREQ5_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 3671#define mmHUBPREQ5_DCN_SURF0_TTU_CNTL0 0x0a78 3672#define mmHUBPREQ5_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 3673#define mmHUBPREQ5_DCN_SURF0_TTU_CNTL1 0x0a79 3674#define mmHUBPREQ5_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 3675#define mmHUBPREQ5_DCN_SURF1_TTU_CNTL0 0x0a7a 3676#define mmHUBPREQ5_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 3677#define mmHUBPREQ5_DCN_SURF1_TTU_CNTL1 0x0a7b 3678#define mmHUBPREQ5_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 3679#define mmHUBPREQ5_DCN_CUR0_TTU_CNTL0 0x0a7c 3680#define mmHUBPREQ5_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 3681#define mmHUBPREQ5_DCN_CUR0_TTU_CNTL1 0x0a7d 3682#define mmHUBPREQ5_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 3683#define mmHUBPREQ5_DCN_CUR1_TTU_CNTL0 0x0a7e 3684#define mmHUBPREQ5_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 3685#define mmHUBPREQ5_DCN_CUR1_TTU_CNTL1 0x0a7f 3686#define mmHUBPREQ5_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 3687#define mmHUBPREQ5_DCN_DMDATA_VM_CNTL 0x0a80 3688#define mmHUBPREQ5_DCN_DMDATA_VM_CNTL_BASE_IDX 2 3689#define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0a81 3690#define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 3691#define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0a82 3692#define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 3693#define mmHUBPREQ5_DCN_VM_MX_L1_TLB_CNTL 0x0a8f 3694#define mmHUBPREQ5_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 3695#define mmHUBPREQ5_BLANK_OFFSET_0 0x0a90 3696#define mmHUBPREQ5_BLANK_OFFSET_0_BASE_IDX 2 3697#define mmHUBPREQ5_BLANK_OFFSET_1 0x0a91 3698#define mmHUBPREQ5_BLANK_OFFSET_1_BASE_IDX 2 3699#define mmHUBPREQ5_DST_DIMENSIONS 0x0a92 3700#define mmHUBPREQ5_DST_DIMENSIONS_BASE_IDX 2 3701#define mmHUBPREQ5_DST_AFTER_SCALER 0x0a93 3702#define mmHUBPREQ5_DST_AFTER_SCALER_BASE_IDX 2 3703#define mmHUBPREQ5_PREFETCH_SETTINGS 0x0a94 3704#define mmHUBPREQ5_PREFETCH_SETTINGS_BASE_IDX 2 3705#define mmHUBPREQ5_PREFETCH_SETTINGS_C 0x0a95 3706#define mmHUBPREQ5_PREFETCH_SETTINGS_C_BASE_IDX 2 3707#define mmHUBPREQ5_VBLANK_PARAMETERS_0 0x0a96 3708#define mmHUBPREQ5_VBLANK_PARAMETERS_0_BASE_IDX 2 3709#define mmHUBPREQ5_VBLANK_PARAMETERS_1 0x0a97 3710#define mmHUBPREQ5_VBLANK_PARAMETERS_1_BASE_IDX 2 3711#define mmHUBPREQ5_VBLANK_PARAMETERS_2 0x0a98 3712#define mmHUBPREQ5_VBLANK_PARAMETERS_2_BASE_IDX 2 3713#define mmHUBPREQ5_VBLANK_PARAMETERS_3 0x0a99 3714#define mmHUBPREQ5_VBLANK_PARAMETERS_3_BASE_IDX 2 3715#define mmHUBPREQ5_VBLANK_PARAMETERS_4 0x0a9a 3716#define mmHUBPREQ5_VBLANK_PARAMETERS_4_BASE_IDX 2 3717#define mmHUBPREQ5_FLIP_PARAMETERS_0 0x0a9b 3718#define mmHUBPREQ5_FLIP_PARAMETERS_0_BASE_IDX 2 3719#define mmHUBPREQ5_FLIP_PARAMETERS_1 0x0a9c 3720#define mmHUBPREQ5_FLIP_PARAMETERS_1_BASE_IDX 2 3721#define mmHUBPREQ5_FLIP_PARAMETERS_2 0x0a9d 3722#define mmHUBPREQ5_FLIP_PARAMETERS_2_BASE_IDX 2 3723#define mmHUBPREQ5_NOM_PARAMETERS_0 0x0a9e 3724#define mmHUBPREQ5_NOM_PARAMETERS_0_BASE_IDX 2 3725#define mmHUBPREQ5_NOM_PARAMETERS_1 0x0a9f 3726#define mmHUBPREQ5_NOM_PARAMETERS_1_BASE_IDX 2 3727#define mmHUBPREQ5_NOM_PARAMETERS_2 0x0aa0 3728#define mmHUBPREQ5_NOM_PARAMETERS_2_BASE_IDX 2 3729#define mmHUBPREQ5_NOM_PARAMETERS_3 0x0aa1 3730#define mmHUBPREQ5_NOM_PARAMETERS_3_BASE_IDX 2 3731#define mmHUBPREQ5_NOM_PARAMETERS_4 0x0aa2 3732#define mmHUBPREQ5_NOM_PARAMETERS_4_BASE_IDX 2 3733#define mmHUBPREQ5_NOM_PARAMETERS_5 0x0aa3 3734#define mmHUBPREQ5_NOM_PARAMETERS_5_BASE_IDX 2 3735#define mmHUBPREQ5_NOM_PARAMETERS_6 0x0aa4 3736#define mmHUBPREQ5_NOM_PARAMETERS_6_BASE_IDX 2 3737#define mmHUBPREQ5_NOM_PARAMETERS_7 0x0aa5 3738#define mmHUBPREQ5_NOM_PARAMETERS_7_BASE_IDX 2 3739#define mmHUBPREQ5_PER_LINE_DELIVERY_PRE 0x0aa6 3740#define mmHUBPREQ5_PER_LINE_DELIVERY_PRE_BASE_IDX 2 3741#define mmHUBPREQ5_PER_LINE_DELIVERY 0x0aa7 3742#define mmHUBPREQ5_PER_LINE_DELIVERY_BASE_IDX 2 3743#define mmHUBPREQ5_CURSOR_SETTINGS 0x0aa8 3744#define mmHUBPREQ5_CURSOR_SETTINGS_BASE_IDX 2 3745#define mmHUBPREQ5_REF_FREQ_TO_PIX_FREQ 0x0aa9 3746#define mmHUBPREQ5_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 3747#define mmHUBPREQ5_DST_Y_DELTA_DRQ_LIMIT 0x0aaa 3748#define mmHUBPREQ5_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 3749#define mmHUBPREQ5_HUBPREQ_MEM_PWR_CTRL 0x0aab 3750#define mmHUBPREQ5_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 3751#define mmHUBPREQ5_HUBPREQ_MEM_PWR_STATUS 0x0aac 3752#define mmHUBPREQ5_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 3753#define mmHUBPREQ5_VBLANK_PARAMETERS_5 0x0aaf 3754#define mmHUBPREQ5_VBLANK_PARAMETERS_5_BASE_IDX 2 3755#define mmHUBPREQ5_VBLANK_PARAMETERS_6 0x0ab0 3756#define mmHUBPREQ5_VBLANK_PARAMETERS_6_BASE_IDX 2 3757#define mmHUBPREQ5_FLIP_PARAMETERS_3 0x0ab1 3758#define mmHUBPREQ5_FLIP_PARAMETERS_3_BASE_IDX 2 3759#define mmHUBPREQ5_FLIP_PARAMETERS_4 0x0ab2 3760#define mmHUBPREQ5_FLIP_PARAMETERS_4_BASE_IDX 2 3761#define mmHUBPREQ5_FLIP_PARAMETERS_5 0x0ab3 3762#define mmHUBPREQ5_FLIP_PARAMETERS_5_BASE_IDX 2 3763#define mmHUBPREQ5_FLIP_PARAMETERS_6 0x0ab4 3764#define mmHUBPREQ5_FLIP_PARAMETERS_6_BASE_IDX 2 3765 3766 3767// addressBlock: dce_dc_dcbubp5_dispdec_hubpret_dispdec 3768// base address: 0x1130 3769#define mmHUBPRET5_HUBPRET_CONTROL 0x0ab8 3770#define mmHUBPRET5_HUBPRET_CONTROL_BASE_IDX 2 3771#define mmHUBPRET5_HUBPRET_MEM_PWR_CTRL 0x0ab9 3772#define mmHUBPRET5_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 3773#define mmHUBPRET5_HUBPRET_MEM_PWR_STATUS 0x0aba 3774#define mmHUBPRET5_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 3775#define mmHUBPRET5_HUBPRET_READ_LINE_CTRL0 0x0abb 3776#define mmHUBPRET5_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 3777#define mmHUBPRET5_HUBPRET_READ_LINE_CTRL1 0x0abc 3778#define mmHUBPRET5_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 3779#define mmHUBPRET5_HUBPRET_READ_LINE0 0x0abd 3780#define mmHUBPRET5_HUBPRET_READ_LINE0_BASE_IDX 2 3781#define mmHUBPRET5_HUBPRET_READ_LINE1 0x0abe 3782#define mmHUBPRET5_HUBPRET_READ_LINE1_BASE_IDX 2 3783#define mmHUBPRET5_HUBPRET_INTERRUPT 0x0abf 3784#define mmHUBPRET5_HUBPRET_INTERRUPT_BASE_IDX 2 3785#define mmHUBPRET5_HUBPRET_READ_LINE_VALUE 0x0ac0 3786#define mmHUBPRET5_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 3787#define mmHUBPRET5_HUBPRET_READ_LINE_STATUS 0x0ac1 3788#define mmHUBPRET5_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 3789 3790 3791// addressBlock: dce_dc_dcbubp5_dispdec_cursor0_dispdec 3792// base address: 0x1130 3793#define mmCURSOR0_5_CURSOR_CONTROL 0x0ac4 3794#define mmCURSOR0_5_CURSOR_CONTROL_BASE_IDX 2 3795#define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS 0x0ac5 3796#define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 3797#define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS_HIGH 0x0ac6 3798#define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3799#define mmCURSOR0_5_CURSOR_SIZE 0x0ac7 3800#define mmCURSOR0_5_CURSOR_SIZE_BASE_IDX 2 3801#define mmCURSOR0_5_CURSOR_POSITION 0x0ac8 3802#define mmCURSOR0_5_CURSOR_POSITION_BASE_IDX 2 3803#define mmCURSOR0_5_CURSOR_HOT_SPOT 0x0ac9 3804#define mmCURSOR0_5_CURSOR_HOT_SPOT_BASE_IDX 2 3805#define mmCURSOR0_5_CURSOR_STEREO_CONTROL 0x0aca 3806#define mmCURSOR0_5_CURSOR_STEREO_CONTROL_BASE_IDX 2 3807#define mmCURSOR0_5_CURSOR_DST_OFFSET 0x0acb 3808#define mmCURSOR0_5_CURSOR_DST_OFFSET_BASE_IDX 2 3809#define mmCURSOR0_5_CURSOR_MEM_PWR_CTRL 0x0acc 3810#define mmCURSOR0_5_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 3811#define mmCURSOR0_5_CURSOR_MEM_PWR_STATUS 0x0acd 3812#define mmCURSOR0_5_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 3813#define mmCURSOR0_5_DMDATA_ADDRESS_HIGH 0x0ace 3814#define mmCURSOR0_5_DMDATA_ADDRESS_HIGH_BASE_IDX 2 3815#define mmCURSOR0_5_DMDATA_ADDRESS_LOW 0x0acf 3816#define mmCURSOR0_5_DMDATA_ADDRESS_LOW_BASE_IDX 2 3817#define mmCURSOR0_5_DMDATA_CNTL 0x0ad0 3818#define mmCURSOR0_5_DMDATA_CNTL_BASE_IDX 2 3819#define mmCURSOR0_5_DMDATA_QOS_CNTL 0x0ad1 3820#define mmCURSOR0_5_DMDATA_QOS_CNTL_BASE_IDX 2 3821#define mmCURSOR0_5_DMDATA_STATUS 0x0ad2 3822#define mmCURSOR0_5_DMDATA_STATUS_BASE_IDX 2 3823#define mmCURSOR0_5_DMDATA_SW_CNTL 0x0ad3 3824#define mmCURSOR0_5_DMDATA_SW_CNTL_BASE_IDX 2 3825#define mmCURSOR0_5_DMDATA_SW_DATA 0x0ad4 3826#define mmCURSOR0_5_DMDATA_SW_DATA_BASE_IDX 2 3827 3828 3829// addressBlock: dce_dc_dcbubp5_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 3830// base address: 0x2ba4 3831#define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x0ae9 3832#define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2 3833#define mmDC_PERFMON11_PERFCOUNTER_CNTL2 0x0aea 3834#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2 3835#define mmDC_PERFMON11_PERFCOUNTER_STATE 0x0aeb 3836#define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2 3837#define mmDC_PERFMON11_PERFMON_CNTL 0x0aec 3838#define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2 3839#define mmDC_PERFMON11_PERFMON_CNTL2 0x0aed 3840#define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2 3841#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x0aee 3842#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3843#define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x0aef 3844#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2 3845#define mmDC_PERFMON11_PERFMON_HI 0x0af0 3846#define mmDC_PERFMON11_PERFMON_HI_BASE_IDX 2 3847#define mmDC_PERFMON11_PERFMON_LOW 0x0af1 3848#define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX 2 3849 3850 3851// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec 3852// base address: 0x0 3853#define mmDPP_TOP0_DPP_CONTROL 0x0cc5 3854#define mmDPP_TOP0_DPP_CONTROL_BASE_IDX 2 3855#define mmDPP_TOP0_DPP_SOFT_RESET 0x0cc6 3856#define mmDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2 3857#define mmDPP_TOP0_DPP_CRC_VAL_R_G 0x0cc7 3858#define mmDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2 3859#define mmDPP_TOP0_DPP_CRC_VAL_B_A 0x0cc8 3860#define mmDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2 3861#define mmDPP_TOP0_DPP_CRC_CTRL 0x0cc9 3862#define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2 3863#define mmDPP_TOP0_HOST_READ_CONTROL 0x0cca 3864#define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2 3865 3866 3867// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec 3868// base address: 0x0 3869#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0ccf 3870#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 3871#define mmCNVC_CFG0_FORMAT_CONTROL 0x0cd0 3872#define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2 3873#define mmCNVC_CFG0_FCNV_FP_BIAS_R 0x0cd1 3874#define mmCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX 2 3875#define mmCNVC_CFG0_FCNV_FP_BIAS_G 0x0cd2 3876#define mmCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX 2 3877#define mmCNVC_CFG0_FCNV_FP_BIAS_B 0x0cd3 3878#define mmCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX 2 3879#define mmCNVC_CFG0_FCNV_FP_SCALE_R 0x0cd4 3880#define mmCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX 2 3881#define mmCNVC_CFG0_FCNV_FP_SCALE_G 0x0cd5 3882#define mmCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX 2 3883#define mmCNVC_CFG0_FCNV_FP_SCALE_B 0x0cd6 3884#define mmCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX 2 3885#define mmCNVC_CFG0_COLOR_KEYER_CONTROL 0x0cd7 3886#define mmCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2 3887#define mmCNVC_CFG0_COLOR_KEYER_ALPHA 0x0cd8 3888#define mmCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2 3889#define mmCNVC_CFG0_COLOR_KEYER_RED 0x0cd9 3890#define mmCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2 3891#define mmCNVC_CFG0_COLOR_KEYER_GREEN 0x0cda 3892#define mmCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2 3893#define mmCNVC_CFG0_COLOR_KEYER_BLUE 0x0cdb 3894#define mmCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2 3895#define mmCNVC_CFG0_ALPHA_2BIT_LUT 0x0cdd 3896#define mmCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX 2 3897#define mmCNVC_CFG0_PRE_DEALPHA 0x0cde 3898#define mmCNVC_CFG0_PRE_DEALPHA_BASE_IDX 2 3899#define mmCNVC_CFG0_PRE_CSC_MODE 0x0cdf 3900#define mmCNVC_CFG0_PRE_CSC_MODE_BASE_IDX 2 3901#define mmCNVC_CFG0_PRE_CSC_C11_C12 0x0ce0 3902#define mmCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX 2 3903#define mmCNVC_CFG0_PRE_CSC_C13_C14 0x0ce1 3904#define mmCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX 2 3905#define mmCNVC_CFG0_PRE_CSC_C21_C22 0x0ce2 3906#define mmCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX 2 3907#define mmCNVC_CFG0_PRE_CSC_C23_C24 0x0ce3 3908#define mmCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX 2 3909#define mmCNVC_CFG0_PRE_CSC_C31_C32 0x0ce4 3910#define mmCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX 2 3911#define mmCNVC_CFG0_PRE_CSC_C33_C34 0x0ce5 3912#define mmCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX 2 3913#define mmCNVC_CFG0_PRE_CSC_B_C11_C12 0x0ce6 3914#define mmCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX 2 3915#define mmCNVC_CFG0_PRE_CSC_B_C13_C14 0x0ce7 3916#define mmCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX 2 3917#define mmCNVC_CFG0_PRE_CSC_B_C21_C22 0x0ce8 3918#define mmCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX 2 3919#define mmCNVC_CFG0_PRE_CSC_B_C23_C24 0x0ce9 3920#define mmCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX 2 3921#define mmCNVC_CFG0_PRE_CSC_B_C31_C32 0x0cea 3922#define mmCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX 2 3923#define mmCNVC_CFG0_PRE_CSC_B_C33_C34 0x0ceb 3924#define mmCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX 2 3925#define mmCNVC_CFG0_CNVC_COEF_FORMAT 0x0cec 3926#define mmCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX 2 3927#define mmCNVC_CFG0_PRE_DEGAM 0x0ced 3928#define mmCNVC_CFG0_PRE_DEGAM_BASE_IDX 2 3929#define mmCNVC_CFG0_PRE_REALPHA 0x0cee 3930#define mmCNVC_CFG0_PRE_REALPHA_BASE_IDX 2 3931 3932 3933// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec 3934// base address: 0x0 3935#define mmCNVC_CUR0_CURSOR0_CONTROL 0x0cf1 3936#define mmCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2 3937#define mmCNVC_CUR0_CURSOR0_COLOR0 0x0cf2 3938#define mmCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2 3939#define mmCNVC_CUR0_CURSOR0_COLOR1 0x0cf3 3940#define mmCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2 3941#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0cf4 3942#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 3943 3944 3945// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec 3946// base address: 0x0 3947#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0cf9 3948#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 3949#define mmDSCL0_SCL_COEF_RAM_TAP_DATA 0x0cfa 3950#define mmDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 3951#define mmDSCL0_SCL_MODE 0x0cfb 3952#define mmDSCL0_SCL_MODE_BASE_IDX 2 3953#define mmDSCL0_SCL_TAP_CONTROL 0x0cfc 3954#define mmDSCL0_SCL_TAP_CONTROL_BASE_IDX 2 3955#define mmDSCL0_DSCL_CONTROL 0x0cfd 3956#define mmDSCL0_DSCL_CONTROL_BASE_IDX 2 3957#define mmDSCL0_DSCL_2TAP_CONTROL 0x0cfe 3958#define mmDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2 3959#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0cff 3960#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 3961#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0d00 3962#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 3963#define mmDSCL0_SCL_HORZ_FILTER_INIT 0x0d01 3964#define mmDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2 3965#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0d02 3966#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 3967#define mmDSCL0_SCL_HORZ_FILTER_INIT_C 0x0d03 3968#define mmDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 3969#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0d04 3970#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 3971#define mmDSCL0_SCL_VERT_FILTER_INIT 0x0d05 3972#define mmDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2 3973#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0d06 3974#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 3975#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0d07 3976#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 3977#define mmDSCL0_SCL_VERT_FILTER_INIT_C 0x0d08 3978#define mmDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 3979#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0d09 3980#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 3981#define mmDSCL0_SCL_BLACK_COLOR 0x0d0a 3982#define mmDSCL0_SCL_BLACK_COLOR_BASE_IDX 2 3983#define mmDSCL0_DSCL_UPDATE 0x0d0b 3984#define mmDSCL0_DSCL_UPDATE_BASE_IDX 2 3985#define mmDSCL0_DSCL_AUTOCAL 0x0d0c 3986#define mmDSCL0_DSCL_AUTOCAL_BASE_IDX 2 3987#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0d0d 3988#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 3989#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0d0e 3990#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 3991#define mmDSCL0_OTG_H_BLANK 0x0d0f 3992#define mmDSCL0_OTG_H_BLANK_BASE_IDX 2 3993#define mmDSCL0_OTG_V_BLANK 0x0d10 3994#define mmDSCL0_OTG_V_BLANK_BASE_IDX 2 3995#define mmDSCL0_RECOUT_START 0x0d11 3996#define mmDSCL0_RECOUT_START_BASE_IDX 2 3997#define mmDSCL0_RECOUT_SIZE 0x0d12 3998#define mmDSCL0_RECOUT_SIZE_BASE_IDX 2 3999#define mmDSCL0_MPC_SIZE 0x0d13 4000#define mmDSCL0_MPC_SIZE_BASE_IDX 2
4001#define mmDSCL0_LB_DATA_FORMAT 0x0d14 4002#define mmDSCL0_LB_DATA_FORMAT_BASE_IDX 2 4003#define mmDSCL0_LB_MEMORY_CTRL 0x0d15 4004#define mmDSCL0_LB_MEMORY_CTRL_BASE_IDX 2 4005#define mmDSCL0_LB_V_COUNTER 0x0d16 4006#define mmDSCL0_LB_V_COUNTER_BASE_IDX 2 4007#define mmDSCL0_DSCL_MEM_PWR_CTRL 0x0d17 4008#define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2 4009#define mmDSCL0_DSCL_MEM_PWR_STATUS 0x0d18 4010#define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2 4011#define mmDSCL0_OBUF_CONTROL 0x0d19 4012#define mmDSCL0_OBUF_CONTROL_BASE_IDX 2 4013#define mmDSCL0_OBUF_MEM_PWR_CTRL 0x0d1a 4014#define mmDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2 4015 4016 4017// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec 4018// base address: 0x0 4019#define mmCM0_CM_CONTROL 0x0d20 4020#define mmCM0_CM_CONTROL_BASE_IDX 2 4021#define mmCM0_CM_POST_CSC_CONTROL 0x0d21 4022#define mmCM0_CM_POST_CSC_CONTROL_BASE_IDX 2 4023#define mmCM0_CM_POST_CSC_C11_C12 0x0d22 4024#define mmCM0_CM_POST_CSC_C11_C12_BASE_IDX 2 4025#define mmCM0_CM_POST_CSC_C13_C14 0x0d23 4026#define mmCM0_CM_POST_CSC_C13_C14_BASE_IDX 2 4027#define mmCM0_CM_POST_CSC_C21_C22 0x0d24 4028#define mmCM0_CM_POST_CSC_C21_C22_BASE_IDX 2 4029#define mmCM0_CM_POST_CSC_C23_C24 0x0d25 4030#define mmCM0_CM_POST_CSC_C23_C24_BASE_IDX 2 4031#define mmCM0_CM_POST_CSC_C31_C32 0x0d26 4032#define mmCM0_CM_POST_CSC_C31_C32_BASE_IDX 2 4033#define mmCM0_CM_POST_CSC_C33_C34 0x0d27 4034#define mmCM0_CM_POST_CSC_C33_C34_BASE_IDX 2 4035#define mmCM0_CM_POST_CSC_B_C11_C12 0x0d28 4036#define mmCM0_CM_POST_CSC_B_C11_C12_BASE_IDX 2 4037#define mmCM0_CM_POST_CSC_B_C13_C14 0x0d29 4038#define mmCM0_CM_POST_CSC_B_C13_C14_BASE_IDX 2 4039#define mmCM0_CM_POST_CSC_B_C21_C22 0x0d2a 4040#define mmCM0_CM_POST_CSC_B_C21_C22_BASE_IDX 2 4041#define mmCM0_CM_POST_CSC_B_C23_C24 0x0d2b 4042#define mmCM0_CM_POST_CSC_B_C23_C24_BASE_IDX 2 4043#define mmCM0_CM_POST_CSC_B_C31_C32 0x0d2c 4044#define mmCM0_CM_POST_CSC_B_C31_C32_BASE_IDX 2 4045#define mmCM0_CM_POST_CSC_B_C33_C34 0x0d2d 4046#define mmCM0_CM_POST_CSC_B_C33_C34_BASE_IDX 2 4047#define mmCM0_CM_GAMUT_REMAP_CONTROL 0x0d2e 4048#define mmCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 4049#define mmCM0_CM_GAMUT_REMAP_C11_C12 0x0d2f 4050#define mmCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 4051#define mmCM0_CM_GAMUT_REMAP_C13_C14 0x0d30 4052#define mmCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 4053#define mmCM0_CM_GAMUT_REMAP_C21_C22 0x0d31 4054#define mmCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 4055#define mmCM0_CM_GAMUT_REMAP_C23_C24 0x0d32 4056#define mmCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 4057#define mmCM0_CM_GAMUT_REMAP_C31_C32 0x0d33 4058#define mmCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 4059#define mmCM0_CM_GAMUT_REMAP_C33_C34 0x0d34 4060#define mmCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 4061#define mmCM0_CM_GAMUT_REMAP_B_C11_C12 0x0d35 4062#define mmCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 4063#define mmCM0_CM_GAMUT_REMAP_B_C13_C14 0x0d36 4064#define mmCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 4065#define mmCM0_CM_GAMUT_REMAP_B_C21_C22 0x0d37 4066#define mmCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 4067#define mmCM0_CM_GAMUT_REMAP_B_C23_C24 0x0d38 4068#define mmCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 4069#define mmCM0_CM_GAMUT_REMAP_B_C31_C32 0x0d39 4070#define mmCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 4071#define mmCM0_CM_GAMUT_REMAP_B_C33_C34 0x0d3a 4072#define mmCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 4073#define mmCM0_CM_BIAS_CR_R 0x0d3b 4074#define mmCM0_CM_BIAS_CR_R_BASE_IDX 2 4075#define mmCM0_CM_BIAS_Y_G_CB_B 0x0d3c 4076#define mmCM0_CM_BIAS_Y_G_CB_B_BASE_IDX 2 4077#define mmCM0_CM_GAMCOR_CONTROL 0x0d3d 4078#define mmCM0_CM_GAMCOR_CONTROL_BASE_IDX 2 4079#define mmCM0_CM_GAMCOR_LUT_INDEX 0x0d3e 4080#define mmCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 4081#define mmCM0_CM_GAMCOR_LUT_DATA 0x0d3f 4082#define mmCM0_CM_GAMCOR_LUT_DATA_BASE_IDX 2 4083#define mmCM0_CM_GAMCOR_LUT_CONTROL 0x0d40 4084#define mmCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 4085#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_B 0x0d41 4086#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 4087#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_G 0x0d42 4088#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 4089#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_R 0x0d43 4090#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 4091#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0d44 4092#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 4093#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0d45 4094#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 4095#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0d46 4096#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 4097#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0d47 4098#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 4099#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0d48 4100#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 4101#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0d49 4102#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 4103#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_B 0x0d4a 4104#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 4105#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_B 0x0d4b 4106#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 4107#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_G 0x0d4c 4108#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 4109#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_G 0x0d4d 4110#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 4111#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_R 0x0d4e 4112#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 4113#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_R 0x0d4f 4114#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 4115#define mmCM0_CM_GAMCOR_RAMA_OFFSET_B 0x0d50 4116#define mmCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 4117#define mmCM0_CM_GAMCOR_RAMA_OFFSET_G 0x0d51 4118#define mmCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 4119#define mmCM0_CM_GAMCOR_RAMA_OFFSET_R 0x0d52 4120#define mmCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 4121#define mmCM0_CM_GAMCOR_RAMA_REGION_0_1 0x0d53 4122#define mmCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 4123#define mmCM0_CM_GAMCOR_RAMA_REGION_2_3 0x0d54 4124#define mmCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 4125#define mmCM0_CM_GAMCOR_RAMA_REGION_4_5 0x0d55 4126#define mmCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 4127#define mmCM0_CM_GAMCOR_RAMA_REGION_6_7 0x0d56 4128#define mmCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 4129#define mmCM0_CM_GAMCOR_RAMA_REGION_8_9 0x0d57 4130#define mmCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 4131#define mmCM0_CM_GAMCOR_RAMA_REGION_10_11 0x0d58 4132#define mmCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 4133#define mmCM0_CM_GAMCOR_RAMA_REGION_12_13 0x0d59 4134#define mmCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 4135#define mmCM0_CM_GAMCOR_RAMA_REGION_14_15 0x0d5a 4136#define mmCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 4137#define mmCM0_CM_GAMCOR_RAMA_REGION_16_17 0x0d5b 4138#define mmCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 4139#define mmCM0_CM_GAMCOR_RAMA_REGION_18_19 0x0d5c 4140#define mmCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 4141#define mmCM0_CM_GAMCOR_RAMA_REGION_20_21 0x0d5d 4142#define mmCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 4143#define mmCM0_CM_GAMCOR_RAMA_REGION_22_23 0x0d5e 4144#define mmCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 4145#define mmCM0_CM_GAMCOR_RAMA_REGION_24_25 0x0d5f 4146#define mmCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 4147#define mmCM0_CM_GAMCOR_RAMA_REGION_26_27 0x0d60 4148#define mmCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 4149#define mmCM0_CM_GAMCOR_RAMA_REGION_28_29 0x0d61 4150#define mmCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 4151#define mmCM0_CM_GAMCOR_RAMA_REGION_30_31 0x0d62 4152#define mmCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 4153#define mmCM0_CM_GAMCOR_RAMA_REGION_32_33 0x0d63 4154#define mmCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 4155#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_B 0x0d64 4156#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 4157#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_G 0x0d65 4158#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 4159#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_R 0x0d66 4160#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 4161#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0d67 4162#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 4163#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0d68 4164#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 4165#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0d69 4166#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 4167#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0d6a 4168#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 4169#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0d6b 4170#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 4171#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0d6c 4172#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 4173#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_B 0x0d6d 4174#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 4175#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_B 0x0d6e 4176#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 4177#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_G 0x0d6f 4178#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 4179#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_G 0x0d70 4180#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 4181#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_R 0x0d71 4182#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 4183#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_R 0x0d72 4184#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 4185#define mmCM0_CM_GAMCOR_RAMB_OFFSET_B 0x0d73 4186#define mmCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 4187#define mmCM0_CM_GAMCOR_RAMB_OFFSET_G 0x0d74 4188#define mmCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 4189#define mmCM0_CM_GAMCOR_RAMB_OFFSET_R 0x0d75 4190#define mmCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 4191#define mmCM0_CM_GAMCOR_RAMB_REGION_0_1 0x0d76 4192#define mmCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 4193#define mmCM0_CM_GAMCOR_RAMB_REGION_2_3 0x0d77 4194#define mmCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 4195#define mmCM0_CM_GAMCOR_RAMB_REGION_4_5 0x0d78 4196#define mmCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 4197#define mmCM0_CM_GAMCOR_RAMB_REGION_6_7 0x0d79 4198#define mmCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 4199#define mmCM0_CM_GAMCOR_RAMB_REGION_8_9 0x0d7a 4200#define mmCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 4201#define mmCM0_CM_GAMCOR_RAMB_REGION_10_11 0x0d7b 4202#define mmCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 4203#define mmCM0_CM_GAMCOR_RAMB_REGION_12_13 0x0d7c 4204#define mmCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 4205#define mmCM0_CM_GAMCOR_RAMB_REGION_14_15 0x0d7d 4206#define mmCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 4207#define mmCM0_CM_GAMCOR_RAMB_REGION_16_17 0x0d7e 4208#define mmCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 4209#define mmCM0_CM_GAMCOR_RAMB_REGION_18_19 0x0d7f 4210#define mmCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 4211#define mmCM0_CM_GAMCOR_RAMB_REGION_20_21 0x0d80 4212#define mmCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 4213#define mmCM0_CM_GAMCOR_RAMB_REGION_22_23 0x0d81 4214#define mmCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 4215#define mmCM0_CM_GAMCOR_RAMB_REGION_24_25 0x0d82 4216#define mmCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 4217#define mmCM0_CM_GAMCOR_RAMB_REGION_26_27 0x0d83 4218#define mmCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 4219#define mmCM0_CM_GAMCOR_RAMB_REGION_28_29 0x0d84 4220#define mmCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 4221#define mmCM0_CM_GAMCOR_RAMB_REGION_30_31 0x0d85 4222#define mmCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 4223#define mmCM0_CM_GAMCOR_RAMB_REGION_32_33 0x0d86 4224#define mmCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 4225#define mmCM0_CM_BLNDGAM_CONTROL 0x0d87 4226#define mmCM0_CM_BLNDGAM_CONTROL_BASE_IDX 2 4227#define mmCM0_CM_BLNDGAM_LUT_INDEX 0x0d88 4228#define mmCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 4229#define mmCM0_CM_BLNDGAM_LUT_DATA 0x0d89 4230#define mmCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 4231#define mmCM0_CM_BLNDGAM_LUT_CONTROL 0x0d8a 4232#define mmCM0_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 4233#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B 0x0d8b 4234#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 4235#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G 0x0d8c 4236#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 4237#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R 0x0d8d 4238#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 4239#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x0d8e 4240#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 4241#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x0d8f 4242#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 4243#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x0d90 4244#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 4245#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x0d91 4246#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 4247#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x0d92 4248#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 4249#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x0d93 4250#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 4251#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0d94 4252#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 4253#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0d95 4254#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 4255#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0d96 4256#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 4257#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0d97 4258#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 4259#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0d98 4260#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 4261#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0d99 4262#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 4263#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_B 0x0d9a 4264#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 4265#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_G 0x0d9b 4266#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 4267#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_R 0x0d9c 4268#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 4269#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1 0x0d9d 4270#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 4271#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3 0x0d9e 4272#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 4273#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5 0x0d9f 4274#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 4275#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7 0x0da0 4276#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 4277#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9 0x0da1 4278#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 4279#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11 0x0da2 4280#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 4281#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13 0x0da3 4282#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 4283#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15 0x0da4 4284#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 4285#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17 0x0da5 4286#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 4287#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19 0x0da6 4288#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 4289#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21 0x0da7 4290#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 4291#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23 0x0da8 4292#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 4293#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25 0x0da9 4294#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 4295#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27 0x0daa 4296#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 4297#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29 0x0dab 4298#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 4299#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31 0x0dac 4300#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 4301#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33 0x0dad 4302#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 4303#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B 0x0dae 4304#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 4305#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G 0x0daf 4306#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 4307#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R 0x0db0 4308#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 4309#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x0db1 4310#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 4311#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x0db2 4312#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 4313#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x0db3 4314#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 4315#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x0db4 4316#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 4317#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x0db5 4318#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 4319#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x0db6 4320#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 4321#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0db7 4322#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 4323#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0db8 4324#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 4325#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0db9 4326#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 4327#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0dba 4328#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 4329#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0dbb 4330#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 4331#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0dbc 4332#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 4333#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_B 0x0dbd 4334#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 4335#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_G 0x0dbe 4336#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 4337#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_R 0x0dbf 4338#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 4339#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1 0x0dc0 4340#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 4341#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3 0x0dc1 4342#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 4343#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5 0x0dc2 4344#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 4345#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7 0x0dc3 4346#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 4347#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9 0x0dc4 4348#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 4349#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11 0x0dc5 4350#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 4351#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13 0x0dc6 4352#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 4353#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15 0x0dc7 4354#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 4355#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17 0x0dc8 4356#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 4357#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19 0x0dc9 4358#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 4359#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21 0x0dca 4360#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 4361#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23 0x0dcb 4362#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 4363#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25 0x0dcc 4364#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 4365#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27 0x0dcd 4366#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 4367#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29 0x0dce 4368#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 4369#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31 0x0dcf 4370#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 4371#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33 0x0dd0 4372#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 4373#define mmCM0_CM_HDR_MULT_COEF 0x0dd1 4374#define mmCM0_CM_HDR_MULT_COEF_BASE_IDX 2 4375#define mmCM0_CM_MEM_PWR_CTRL 0x0dd2 4376#define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX 2 4377#define mmCM0_CM_MEM_PWR_STATUS 0x0dd3 4378#define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX 2 4379#define mmCM0_CM_DEALPHA 0x0dd5 4380#define mmCM0_CM_DEALPHA_BASE_IDX 2 4381#define mmCM0_CM_COEF_FORMAT 0x0dd6 4382#define mmCM0_CM_COEF_FORMAT_BASE_IDX 2 4383#define mmCM0_CM_SHAPER_CONTROL 0x0dd7 4384#define mmCM0_CM_SHAPER_CONTROL_BASE_IDX 2 4385#define mmCM0_CM_SHAPER_OFFSET_R 0x0dd8 4386#define mmCM0_CM_SHAPER_OFFSET_R_BASE_IDX 2 4387#define mmCM0_CM_SHAPER_OFFSET_G 0x0dd9 4388#define mmCM0_CM_SHAPER_OFFSET_G_BASE_IDX 2 4389#define mmCM0_CM_SHAPER_OFFSET_B 0x0dda 4390#define mmCM0_CM_SHAPER_OFFSET_B_BASE_IDX 2 4391#define mmCM0_CM_SHAPER_SCALE_R 0x0ddb 4392#define mmCM0_CM_SHAPER_SCALE_R_BASE_IDX 2 4393#define mmCM0_CM_SHAPER_SCALE_G_B 0x0ddc 4394#define mmCM0_CM_SHAPER_SCALE_G_B_BASE_IDX 2 4395#define mmCM0_CM_SHAPER_LUT_INDEX 0x0ddd 4396#define mmCM0_CM_SHAPER_LUT_INDEX_BASE_IDX 2 4397#define mmCM0_CM_SHAPER_LUT_DATA 0x0dde 4398#define mmCM0_CM_SHAPER_LUT_DATA_BASE_IDX 2 4399#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK 0x0ddf 4400#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 4401#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B 0x0de0 4402#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 4403#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G 0x0de1 4404#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 4405#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R 0x0de2 4406#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 4407#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B 0x0de3 4408#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 4409#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G 0x0de4 4410#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 4411#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R 0x0de5 4412#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 4413#define mmCM0_CM_SHAPER_RAMA_REGION_0_1 0x0de6 4414#define mmCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 4415#define mmCM0_CM_SHAPER_RAMA_REGION_2_3 0x0de7 4416#define mmCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 4417#define mmCM0_CM_SHAPER_RAMA_REGION_4_5 0x0de8 4418#define mmCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 4419#define mmCM0_CM_SHAPER_RAMA_REGION_6_7 0x0de9 4420#define mmCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 4421#define mmCM0_CM_SHAPER_RAMA_REGION_8_9 0x0dea 4422#define mmCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 4423#define mmCM0_CM_SHAPER_RAMA_REGION_10_11 0x0deb 4424#define mmCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 4425#define mmCM0_CM_SHAPER_RAMA_REGION_12_13 0x0dec 4426#define mmCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 4427#define mmCM0_CM_SHAPER_RAMA_REGION_14_15 0x0ded 4428#define mmCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 4429#define mmCM0_CM_SHAPER_RAMA_REGION_16_17 0x0dee 4430#define mmCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 4431#define mmCM0_CM_SHAPER_RAMA_REGION_18_19 0x0def 4432#define mmCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 4433#define mmCM0_CM_SHAPER_RAMA_REGION_20_21 0x0df0 4434#define mmCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 4435#define mmCM0_CM_SHAPER_RAMA_REGION_22_23 0x0df1 4436#define mmCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 4437#define mmCM0_CM_SHAPER_RAMA_REGION_24_25 0x0df2 4438#define mmCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 4439#define mmCM0_CM_SHAPER_RAMA_REGION_26_27 0x0df3 4440#define mmCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 4441#define mmCM0_CM_SHAPER_RAMA_REGION_28_29 0x0df4 4442#define mmCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 4443#define mmCM0_CM_SHAPER_RAMA_REGION_30_31 0x0df5 4444#define mmCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 4445#define mmCM0_CM_SHAPER_RAMA_REGION_32_33 0x0df6 4446#define mmCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 4447#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B 0x0df7 4448#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 4449#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G 0x0df8 4450#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 4451#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R 0x0df9 4452#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 4453#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B 0x0dfa 4454#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 4455#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G 0x0dfb 4456#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 4457#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R 0x0dfc 4458#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 4459#define mmCM0_CM_SHAPER_RAMB_REGION_0_1 0x0dfd 4460#define mmCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 4461#define mmCM0_CM_SHAPER_RAMB_REGION_2_3 0x0dfe 4462#define mmCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 4463#define mmCM0_CM_SHAPER_RAMB_REGION_4_5 0x0dff 4464#define mmCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 4465#define mmCM0_CM_SHAPER_RAMB_REGION_6_7 0x0e00 4466#define mmCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 4467#define mmCM0_CM_SHAPER_RAMB_REGION_8_9 0x0e01 4468#define mmCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 4469#define mmCM0_CM_SHAPER_RAMB_REGION_10_11 0x0e02 4470#define mmCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 4471#define mmCM0_CM_SHAPER_RAMB_REGION_12_13 0x0e03 4472#define mmCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 4473#define mmCM0_CM_SHAPER_RAMB_REGION_14_15 0x0e04 4474#define mmCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 4475#define mmCM0_CM_SHAPER_RAMB_REGION_16_17 0x0e05 4476#define mmCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 4477#define mmCM0_CM_SHAPER_RAMB_REGION_18_19 0x0e06 4478#define mmCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 4479#define mmCM0_CM_SHAPER_RAMB_REGION_20_21 0x0e07 4480#define mmCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 4481#define mmCM0_CM_SHAPER_RAMB_REGION_22_23 0x0e08 4482#define mmCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 4483#define mmCM0_CM_SHAPER_RAMB_REGION_24_25 0x0e09 4484#define mmCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 4485#define mmCM0_CM_SHAPER_RAMB_REGION_26_27 0x0e0a 4486#define mmCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 4487#define mmCM0_CM_SHAPER_RAMB_REGION_28_29 0x0e0b 4488#define mmCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 4489#define mmCM0_CM_SHAPER_RAMB_REGION_30_31 0x0e0c 4490#define mmCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 4491#define mmCM0_CM_SHAPER_RAMB_REGION_32_33 0x0e0d 4492#define mmCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 4493#define mmCM0_CM_MEM_PWR_CTRL2 0x0e0e 4494#define mmCM0_CM_MEM_PWR_CTRL2_BASE_IDX 2 4495#define mmCM0_CM_MEM_PWR_STATUS2 0x0e0f 4496#define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX 2 4497#define mmCM0_CM_3DLUT_MODE 0x0e10 4498#define mmCM0_CM_3DLUT_MODE_BASE_IDX 2 4499#define mmCM0_CM_3DLUT_INDEX 0x0e11 4500#define mmCM0_CM_3DLUT_INDEX_BASE_IDX 2 4501#define mmCM0_CM_3DLUT_DATA 0x0e12 4502#define mmCM0_CM_3DLUT_DATA_BASE_IDX 2 4503#define mmCM0_CM_3DLUT_DATA_30BIT 0x0e13 4504#define mmCM0_CM_3DLUT_DATA_30BIT_BASE_IDX 2 4505#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL 0x0e14 4506#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 4507#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR 0x0e15 4508#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 4509#define mmCM0_CM_3DLUT_OUT_OFFSET_R 0x0e16 4510#define mmCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 4511#define mmCM0_CM_3DLUT_OUT_OFFSET_G 0x0e17 4512#define mmCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 4513#define mmCM0_CM_3DLUT_OUT_OFFSET_B 0x0e18 4514#define mmCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 4515 4516 4517// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 4518// base address: 0x3890 4519#define mmDC_PERFMON12_PERFCOUNTER_CNTL 0x0e24 4520#define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2 4521#define mmDC_PERFMON12_PERFCOUNTER_CNTL2 0x0e25 4522#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2 4523#define mmDC_PERFMON12_PERFCOUNTER_STATE 0x0e26 4524#define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2 4525#define mmDC_PERFMON12_PERFMON_CNTL 0x0e27 4526#define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2 4527#define mmDC_PERFMON12_PERFMON_CNTL2 0x0e28 4528#define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2 4529#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x0e29 4530#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 4531#define mmDC_PERFMON12_PERFMON_CVALUE_LOW 0x0e2a 4532#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2 4533#define mmDC_PERFMON12_PERFMON_HI 0x0e2b 4534#define mmDC_PERFMON12_PERFMON_HI_BASE_IDX 2 4535#define mmDC_PERFMON12_PERFMON_LOW 0x0e2c 4536#define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX 2 4537 4538 4539// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec 4540// base address: 0x5ac 4541#define mmDPP_TOP1_DPP_CONTROL 0x0e30 4542#define mmDPP_TOP1_DPP_CONTROL_BASE_IDX 2 4543#define mmDPP_TOP1_DPP_SOFT_RESET 0x0e31 4544#define mmDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2 4545#define mmDPP_TOP1_DPP_CRC_VAL_R_G 0x0e32 4546#define mmDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2 4547#define mmDPP_TOP1_DPP_CRC_VAL_B_A 0x0e33 4548#define mmDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2 4549#define mmDPP_TOP1_DPP_CRC_CTRL 0x0e34 4550#define mmDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2 4551#define mmDPP_TOP1_HOST_READ_CONTROL 0x0e35 4552#define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2 4553 4554 4555// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec 4556// base address: 0x5ac 4557#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0e3a 4558#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 4559#define mmCNVC_CFG1_FORMAT_CONTROL 0x0e3b 4560#define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2 4561#define mmCNVC_CFG1_FCNV_FP_BIAS_R 0x0e3c 4562#define mmCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX 2 4563#define mmCNVC_CFG1_FCNV_FP_BIAS_G 0x0e3d 4564#define mmCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX 2 4565#define mmCNVC_CFG1_FCNV_FP_BIAS_B 0x0e3e 4566#define mmCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX 2 4567#define mmCNVC_CFG1_FCNV_FP_SCALE_R 0x0e3f 4568#define mmCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX 2 4569#define mmCNVC_CFG1_FCNV_FP_SCALE_G 0x0e40 4570#define mmCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX 2 4571#define mmCNVC_CFG1_FCNV_FP_SCALE_B 0x0e41 4572#define mmCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX 2 4573#define mmCNVC_CFG1_COLOR_KEYER_CONTROL 0x0e42 4574#define mmCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2 4575#define mmCNVC_CFG1_COLOR_KEYER_ALPHA 0x0e43 4576#define mmCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2 4577#define mmCNVC_CFG1_COLOR_KEYER_RED 0x0e44 4578#define mmCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2 4579#define mmCNVC_CFG1_COLOR_KEYER_GREEN 0x0e45 4580#define mmCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2 4581#define mmCNVC_CFG1_COLOR_KEYER_BLUE 0x0e46 4582#define mmCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2 4583#define mmCNVC_CFG1_ALPHA_2BIT_LUT 0x0e48 4584#define mmCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX 2 4585#define mmCNVC_CFG1_PRE_DEALPHA 0x0e49 4586#define mmCNVC_CFG1_PRE_DEALPHA_BASE_IDX 2 4587#define mmCNVC_CFG1_PRE_CSC_MODE 0x0e4a 4588#define mmCNVC_CFG1_PRE_CSC_MODE_BASE_IDX 2 4589#define mmCNVC_CFG1_PRE_CSC_C11_C12 0x0e4b 4590#define mmCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX 2 4591#define mmCNVC_CFG1_PRE_CSC_C13_C14 0x0e4c 4592#define mmCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX 2 4593#define mmCNVC_CFG1_PRE_CSC_C21_C22 0x0e4d 4594#define mmCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX 2 4595#define mmCNVC_CFG1_PRE_CSC_C23_C24 0x0e4e 4596#define mmCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX 2 4597#define mmCNVC_CFG1_PRE_CSC_C31_C32 0x0e4f 4598#define mmCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX 2 4599#define mmCNVC_CFG1_PRE_CSC_C33_C34 0x0e50 4600#define mmCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX 2 4601#define mmCNVC_CFG1_PRE_CSC_B_C11_C12 0x0e51 4602#define mmCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX 2 4603#define mmCNVC_CFG1_PRE_CSC_B_C13_C14 0x0e52 4604#define mmCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX 2 4605#define mmCNVC_CFG1_PRE_CSC_B_C21_C22 0x0e53 4606#define mmCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX 2 4607#define mmCNVC_CFG1_PRE_CSC_B_C23_C24 0x0e54 4608#define mmCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX 2 4609#define mmCNVC_CFG1_PRE_CSC_B_C31_C32 0x0e55 4610#define mmCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX 2 4611#define mmCNVC_CFG1_PRE_CSC_B_C33_C34 0x0e56 4612#define mmCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX 2 4613#define mmCNVC_CFG1_CNVC_COEF_FORMAT 0x0e57 4614#define mmCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX 2 4615#define mmCNVC_CFG1_PRE_DEGAM 0x0e58 4616#define mmCNVC_CFG1_PRE_DEGAM_BASE_IDX 2 4617#define mmCNVC_CFG1_PRE_REALPHA 0x0e59 4618#define mmCNVC_CFG1_PRE_REALPHA_BASE_IDX 2 4619 4620 4621// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec 4622// base address: 0x5ac 4623#define mmCNVC_CUR1_CURSOR0_CONTROL 0x0e5c 4624#define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2 4625#define mmCNVC_CUR1_CURSOR0_COLOR0 0x0e5d 4626#define mmCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2 4627#define mmCNVC_CUR1_CURSOR0_COLOR1 0x0e5e 4628#define mmCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2 4629#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0e5f 4630#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 4631 4632 4633// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec 4634// base address: 0x5ac 4635#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0e64 4636#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 4637#define mmDSCL1_SCL_COEF_RAM_TAP_DATA 0x0e65 4638#define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 4639#define mmDSCL1_SCL_MODE 0x0e66 4640#define mmDSCL1_SCL_MODE_BASE_IDX 2 4641#define mmDSCL1_SCL_TAP_CONTROL 0x0e67 4642#define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX 2 4643#define mmDSCL1_DSCL_CONTROL 0x0e68 4644#define mmDSCL1_DSCL_CONTROL_BASE_IDX 2 4645#define mmDSCL1_DSCL_2TAP_CONTROL 0x0e69 4646#define mmDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2 4647#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0e6a 4648#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 4649#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0e6b 4650#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 4651#define mmDSCL1_SCL_HORZ_FILTER_INIT 0x0e6c 4652#define mmDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2 4653#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0e6d 4654#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 4655#define mmDSCL1_SCL_HORZ_FILTER_INIT_C 0x0e6e 4656#define mmDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 4657#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0e6f 4658#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 4659#define mmDSCL1_SCL_VERT_FILTER_INIT 0x0e70 4660#define mmDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2 4661#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0e71 4662#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 4663#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0e72 4664#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 4665#define mmDSCL1_SCL_VERT_FILTER_INIT_C 0x0e73 4666#define mmDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 4667#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0e74 4668#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 4669#define mmDSCL1_SCL_BLACK_COLOR 0x0e75 4670#define mmDSCL1_SCL_BLACK_COLOR_BASE_IDX 2 4671#define mmDSCL1_DSCL_UPDATE 0x0e76 4672#define mmDSCL1_DSCL_UPDATE_BASE_IDX 2 4673#define mmDSCL1_DSCL_AUTOCAL 0x0e77 4674#define mmDSCL1_DSCL_AUTOCAL_BASE_IDX 2 4675#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0e78 4676#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 4677#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0e79 4678#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 4679#define mmDSCL1_OTG_H_BLANK 0x0e7a 4680#define mmDSCL1_OTG_H_BLANK_BASE_IDX 2 4681#define mmDSCL1_OTG_V_BLANK 0x0e7b 4682#define mmDSCL1_OTG_V_BLANK_BASE_IDX 2 4683#define mmDSCL1_RECOUT_START 0x0e7c 4684#define mmDSCL1_RECOUT_START_BASE_IDX 2 4685#define mmDSCL1_RECOUT_SIZE 0x0e7d 4686#define mmDSCL1_RECOUT_SIZE_BASE_IDX 2 4687#define mmDSCL1_MPC_SIZE 0x0e7e 4688#define mmDSCL1_MPC_SIZE_BASE_IDX 2 4689#define mmDSCL1_LB_DATA_FORMAT 0x0e7f 4690#define mmDSCL1_LB_DATA_FORMAT_BASE_IDX 2 4691#define mmDSCL1_LB_MEMORY_CTRL 0x0e80 4692#define mmDSCL1_LB_MEMORY_CTRL_BASE_IDX 2 4693#define mmDSCL1_LB_V_COUNTER 0x0e81 4694#define mmDSCL1_LB_V_COUNTER_BASE_IDX 2 4695#define mmDSCL1_DSCL_MEM_PWR_CTRL 0x0e82 4696#define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2 4697#define mmDSCL1_DSCL_MEM_PWR_STATUS 0x0e83 4698#define mmDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2 4699#define mmDSCL1_OBUF_CONTROL 0x0e84 4700#define mmDSCL1_OBUF_CONTROL_BASE_IDX 2 4701#define mmDSCL1_OBUF_MEM_PWR_CTRL 0x0e85 4702#define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2 4703 4704 4705// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec 4706// base address: 0x5ac 4707#define mmCM1_CM_CONTROL 0x0e8b 4708#define mmCM1_CM_CONTROL_BASE_IDX 2 4709#define mmCM1_CM_POST_CSC_CONTROL 0x0e8c 4710#define mmCM1_CM_POST_CSC_CONTROL_BASE_IDX 2 4711#define mmCM1_CM_POST_CSC_C11_C12 0x0e8d 4712#define mmCM1_CM_POST_CSC_C11_C12_BASE_IDX 2 4713#define mmCM1_CM_POST_CSC_C13_C14 0x0e8e 4714#define mmCM1_CM_POST_CSC_C13_C14_BASE_IDX 2 4715#define mmCM1_CM_POST_CSC_C21_C22 0x0e8f 4716#define mmCM1_CM_POST_CSC_C21_C22_BASE_IDX 2 4717#define mmCM1_CM_POST_CSC_C23_C24 0x0e90 4718#define mmCM1_CM_POST_CSC_C23_C24_BASE_IDX 2 4719#define mmCM1_CM_POST_CSC_C31_C32 0x0e91 4720#define mmCM1_CM_POST_CSC_C31_C32_BASE_IDX 2 4721#define mmCM1_CM_POST_CSC_C33_C34 0x0e92 4722#define mmCM1_CM_POST_CSC_C33_C34_BASE_IDX 2 4723#define mmCM1_CM_POST_CSC_B_C11_C12 0x0e93 4724#define mmCM1_CM_POST_CSC_B_C11_C12_BASE_IDX 2 4725#define mmCM1_CM_POST_CSC_B_C13_C14 0x0e94 4726#define mmCM1_CM_POST_CSC_B_C13_C14_BASE_IDX 2 4727#define mmCM1_CM_POST_CSC_B_C21_C22 0x0e95 4728#define mmCM1_CM_POST_CSC_B_C21_C22_BASE_IDX 2 4729#define mmCM1_CM_POST_CSC_B_C23_C24 0x0e96 4730#define mmCM1_CM_POST_CSC_B_C23_C24_BASE_IDX 2 4731#define mmCM1_CM_POST_CSC_B_C31_C32 0x0e97 4732#define mmCM1_CM_POST_CSC_B_C31_C32_BASE_IDX 2 4733#define mmCM1_CM_POST_CSC_B_C33_C34 0x0e98 4734#define mmCM1_CM_POST_CSC_B_C33_C34_BASE_IDX 2 4735#define mmCM1_CM_GAMUT_REMAP_CONTROL 0x0e99 4736#define mmCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 4737#define mmCM1_CM_GAMUT_REMAP_C11_C12 0x0e9a 4738#define mmCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 4739#define mmCM1_CM_GAMUT_REMAP_C13_C14 0x0e9b 4740#define mmCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 4741#define mmCM1_CM_GAMUT_REMAP_C21_C22 0x0e9c 4742#define mmCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 4743#define mmCM1_CM_GAMUT_REMAP_C23_C24 0x0e9d 4744#define mmCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 4745#define mmCM1_CM_GAMUT_REMAP_C31_C32 0x0e9e 4746#define mmCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 4747#define mmCM1_CM_GAMUT_REMAP_C33_C34 0x0e9f 4748#define mmCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 4749#define mmCM1_CM_GAMUT_REMAP_B_C11_C12 0x0ea0 4750#define mmCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 4751#define mmCM1_CM_GAMUT_REMAP_B_C13_C14 0x0ea1 4752#define mmCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 4753#define mmCM1_CM_GAMUT_REMAP_B_C21_C22 0x0ea2 4754#define mmCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 4755#define mmCM1_CM_GAMUT_REMAP_B_C23_C24 0x0ea3 4756#define mmCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 4757#define mmCM1_CM_GAMUT_REMAP_B_C31_C32 0x0ea4 4758#define mmCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 4759#define mmCM1_CM_GAMUT_REMAP_B_C33_C34 0x0ea5 4760#define mmCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 4761#define mmCM1_CM_BIAS_CR_R 0x0ea6 4762#define mmCM1_CM_BIAS_CR_R_BASE_IDX 2 4763#define mmCM1_CM_BIAS_Y_G_CB_B 0x0ea7 4764#define mmCM1_CM_BIAS_Y_G_CB_B_BASE_IDX 2 4765#define mmCM1_CM_GAMCOR_CONTROL 0x0ea8 4766#define mmCM1_CM_GAMCOR_CONTROL_BASE_IDX 2 4767#define mmCM1_CM_GAMCOR_LUT_INDEX 0x0ea9 4768#define mmCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 4769#define mmCM1_CM_GAMCOR_LUT_DATA 0x0eaa 4770#define mmCM1_CM_GAMCOR_LUT_DATA_BASE_IDX 2 4771#define mmCM1_CM_GAMCOR_LUT_CONTROL 0x0eab 4772#define mmCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 4773#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_B 0x0eac 4774#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 4775#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_G 0x0ead 4776#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 4777#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_R 0x0eae 4778#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 4779#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0eaf 4780#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 4781#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0eb0 4782#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 4783#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0eb1 4784#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 4785#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0eb2 4786#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 4787#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0eb3 4788#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 4789#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0eb4 4790#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 4791#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_B 0x0eb5 4792#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 4793#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_B 0x0eb6 4794#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 4795#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_G 0x0eb7 4796#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 4797#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_G 0x0eb8 4798#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 4799#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_R 0x0eb9 4800#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 4801#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_R 0x0eba 4802#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 4803#define mmCM1_CM_GAMCOR_RAMA_OFFSET_B 0x0ebb 4804#define mmCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 4805#define mmCM1_CM_GAMCOR_RAMA_OFFSET_G 0x0ebc 4806#define mmCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 4807#define mmCM1_CM_GAMCOR_RAMA_OFFSET_R 0x0ebd 4808#define mmCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 4809#define mmCM1_CM_GAMCOR_RAMA_REGION_0_1 0x0ebe 4810#define mmCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 4811#define mmCM1_CM_GAMCOR_RAMA_REGION_2_3 0x0ebf 4812#define mmCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 4813#define mmCM1_CM_GAMCOR_RAMA_REGION_4_5 0x0ec0 4814#define mmCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 4815#define mmCM1_CM_GAMCOR_RAMA_REGION_6_7 0x0ec1 4816#define mmCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 4817#define mmCM1_CM_GAMCOR_RAMA_REGION_8_9 0x0ec2 4818#define mmCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 4819#define mmCM1_CM_GAMCOR_RAMA_REGION_10_11 0x0ec3 4820#define mmCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 4821#define mmCM1_CM_GAMCOR_RAMA_REGION_12_13 0x0ec4 4822#define mmCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 4823#define mmCM1_CM_GAMCOR_RAMA_REGION_14_15 0x0ec5 4824#define mmCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 4825#define mmCM1_CM_GAMCOR_RAMA_REGION_16_17 0x0ec6 4826#define mmCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 4827#define mmCM1_CM_GAMCOR_RAMA_REGION_18_19 0x0ec7 4828#define mmCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 4829#define mmCM1_CM_GAMCOR_RAMA_REGION_20_21 0x0ec8 4830#define mmCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 4831#define mmCM1_CM_GAMCOR_RAMA_REGION_22_23 0x0ec9 4832#define mmCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 4833#define mmCM1_CM_GAMCOR_RAMA_REGION_24_25 0x0eca 4834#define mmCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 4835#define mmCM1_CM_GAMCOR_RAMA_REGION_26_27 0x0ecb 4836#define mmCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 4837#define mmCM1_CM_GAMCOR_RAMA_REGION_28_29 0x0ecc 4838#define mmCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 4839#define mmCM1_CM_GAMCOR_RAMA_REGION_30_31 0x0ecd 4840#define mmCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 4841#define mmCM1_CM_GAMCOR_RAMA_REGION_32_33 0x0ece 4842#define mmCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 4843#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_B 0x0ecf 4844#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 4845#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_G 0x0ed0 4846#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 4847#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_R 0x0ed1 4848#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 4849#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0ed2 4850#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 4851#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0ed3 4852#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 4853#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0ed4 4854#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 4855#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0ed5 4856#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 4857#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0ed6 4858#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 4859#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0ed7 4860#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 4861#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_B 0x0ed8 4862#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 4863#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_B 0x0ed9 4864#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 4865#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_G 0x0eda 4866#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 4867#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_G 0x0edb 4868#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 4869#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_R 0x0edc 4870#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 4871#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_R 0x0edd 4872#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 4873#define mmCM1_CM_GAMCOR_RAMB_OFFSET_B 0x0ede 4874#define mmCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 4875#define mmCM1_CM_GAMCOR_RAMB_OFFSET_G 0x0edf 4876#define mmCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 4877#define mmCM1_CM_GAMCOR_RAMB_OFFSET_R 0x0ee0 4878#define mmCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 4879#define mmCM1_CM_GAMCOR_RAMB_REGION_0_1 0x0ee1 4880#define mmCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 4881#define mmCM1_CM_GAMCOR_RAMB_REGION_2_3 0x0ee2 4882#define mmCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 4883#define mmCM1_CM_GAMCOR_RAMB_REGION_4_5 0x0ee3 4884#define mmCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 4885#define mmCM1_CM_GAMCOR_RAMB_REGION_6_7 0x0ee4 4886#define mmCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 4887#define mmCM1_CM_GAMCOR_RAMB_REGION_8_9 0x0ee5 4888#define mmCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 4889#define mmCM1_CM_GAMCOR_RAMB_REGION_10_11 0x0ee6 4890#define mmCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 4891#define mmCM1_CM_GAMCOR_RAMB_REGION_12_13 0x0ee7 4892#define mmCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 4893#define mmCM1_CM_GAMCOR_RAMB_REGION_14_15 0x0ee8 4894#define mmCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 4895#define mmCM1_CM_GAMCOR_RAMB_REGION_16_17 0x0ee9 4896#define mmCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 4897#define mmCM1_CM_GAMCOR_RAMB_REGION_18_19 0x0eea 4898#define mmCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 4899#define mmCM1_CM_GAMCOR_RAMB_REGION_20_21 0x0eeb 4900#define mmCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 4901#define mmCM1_CM_GAMCOR_RAMB_REGION_22_23 0x0eec 4902#define mmCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 4903#define mmCM1_CM_GAMCOR_RAMB_REGION_24_25 0x0eed 4904#define mmCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 4905#define mmCM1_CM_GAMCOR_RAMB_REGION_26_27 0x0eee 4906#define mmCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 4907#define mmCM1_CM_GAMCOR_RAMB_REGION_28_29 0x0eef 4908#define mmCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 4909#define mmCM1_CM_GAMCOR_RAMB_REGION_30_31 0x0ef0 4910#define mmCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 4911#define mmCM1_CM_GAMCOR_RAMB_REGION_32_33 0x0ef1 4912#define mmCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 4913#define mmCM1_CM_BLNDGAM_CONTROL 0x0ef2 4914#define mmCM1_CM_BLNDGAM_CONTROL_BASE_IDX 2 4915#define mmCM1_CM_BLNDGAM_LUT_INDEX 0x0ef3 4916#define mmCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 4917#define mmCM1_CM_BLNDGAM_LUT_DATA 0x0ef4 4918#define mmCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 4919#define mmCM1_CM_BLNDGAM_LUT_CONTROL 0x0ef5 4920#define mmCM1_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 4921#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B 0x0ef6 4922#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 4923#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G 0x0ef7 4924#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 4925#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R 0x0ef8 4926#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 4927#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x0ef9 4928#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 4929#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x0efa 4930#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 4931#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x0efb 4932#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 4933#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x0efc 4934#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 4935#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x0efd 4936#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 4937#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x0efe 4938#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 4939#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0eff 4940#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 4941#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0f00 4942#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 4943#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0f01 4944#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 4945#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0f02 4946#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 4947#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0f03 4948#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 4949#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0f04 4950#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 4951#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_B 0x0f05 4952#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 4953#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_G 0x0f06 4954#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 4955#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_R 0x0f07 4956#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 4957#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1 0x0f08 4958#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 4959#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3 0x0f09 4960#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 4961#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5 0x0f0a 4962#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 4963#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7 0x0f0b 4964#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 4965#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9 0x0f0c 4966#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 4967#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11 0x0f0d 4968#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 4969#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13 0x0f0e 4970#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 4971#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15 0x0f0f 4972#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 4973#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17 0x0f10 4974#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 4975#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19 0x0f11 4976#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 4977#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21 0x0f12 4978#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 4979#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23 0x0f13 4980#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 4981#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25 0x0f14 4982#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 4983#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27 0x0f15 4984#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 4985#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29 0x0f16 4986#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 4987#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31 0x0f17 4988#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 4989#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33 0x0f18 4990#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 4991#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B 0x0f19 4992#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 4993#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G 0x0f1a 4994#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 4995#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R 0x0f1b 4996#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 4997#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x0f1c 4998#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 4999#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x0f1d 5000#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2
5001#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x0f1e 5002#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 5003#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x0f1f 5004#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 5005#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x0f20 5006#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 5007#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x0f21 5008#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 5009#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0f22 5010#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 5011#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0f23 5012#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 5013#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0f24 5014#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 5015#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0f25 5016#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 5017#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0f26 5018#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 5019#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0f27 5020#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 5021#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_B 0x0f28 5022#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 5023#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_G 0x0f29 5024#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 5025#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_R 0x0f2a 5026#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 5027#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1 0x0f2b 5028#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 5029#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3 0x0f2c 5030#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 5031#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5 0x0f2d 5032#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 5033#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7 0x0f2e 5034#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 5035#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9 0x0f2f 5036#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 5037#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11 0x0f30 5038#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 5039#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13 0x0f31 5040#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 5041#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15 0x0f32 5042#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 5043#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17 0x0f33 5044#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 5045#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19 0x0f34 5046#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 5047#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21 0x0f35 5048#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 5049#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23 0x0f36 5050#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 5051#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25 0x0f37 5052#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 5053#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27 0x0f38 5054#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 5055#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29 0x0f39 5056#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 5057#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31 0x0f3a 5058#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 5059#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33 0x0f3b 5060#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 5061#define mmCM1_CM_HDR_MULT_COEF 0x0f3c 5062#define mmCM1_CM_HDR_MULT_COEF_BASE_IDX 2 5063#define mmCM1_CM_MEM_PWR_CTRL 0x0f3d 5064#define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX 2 5065#define mmCM1_CM_MEM_PWR_STATUS 0x0f3e 5066#define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX 2 5067#define mmCM1_CM_DEALPHA 0x0f40 5068#define mmCM1_CM_DEALPHA_BASE_IDX 2 5069#define mmCM1_CM_COEF_FORMAT 0x0f41 5070#define mmCM1_CM_COEF_FORMAT_BASE_IDX 2 5071#define mmCM1_CM_SHAPER_CONTROL 0x0f42 5072#define mmCM1_CM_SHAPER_CONTROL_BASE_IDX 2 5073#define mmCM1_CM_SHAPER_OFFSET_R 0x0f43 5074#define mmCM1_CM_SHAPER_OFFSET_R_BASE_IDX 2 5075#define mmCM1_CM_SHAPER_OFFSET_G 0x0f44 5076#define mmCM1_CM_SHAPER_OFFSET_G_BASE_IDX 2 5077#define mmCM1_CM_SHAPER_OFFSET_B 0x0f45 5078#define mmCM1_CM_SHAPER_OFFSET_B_BASE_IDX 2 5079#define mmCM1_CM_SHAPER_SCALE_R 0x0f46 5080#define mmCM1_CM_SHAPER_SCALE_R_BASE_IDX 2 5081#define mmCM1_CM_SHAPER_SCALE_G_B 0x0f47 5082#define mmCM1_CM_SHAPER_SCALE_G_B_BASE_IDX 2 5083#define mmCM1_CM_SHAPER_LUT_INDEX 0x0f48 5084#define mmCM1_CM_SHAPER_LUT_INDEX_BASE_IDX 2 5085#define mmCM1_CM_SHAPER_LUT_DATA 0x0f49 5086#define mmCM1_CM_SHAPER_LUT_DATA_BASE_IDX 2 5087#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK 0x0f4a 5088#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 5089#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B 0x0f4b 5090#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 5091#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G 0x0f4c 5092#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 5093#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R 0x0f4d 5094#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 5095#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B 0x0f4e 5096#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 5097#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G 0x0f4f 5098#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 5099#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R 0x0f50 5100#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 5101#define mmCM1_CM_SHAPER_RAMA_REGION_0_1 0x0f51 5102#define mmCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 5103#define mmCM1_CM_SHAPER_RAMA_REGION_2_3 0x0f52 5104#define mmCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 5105#define mmCM1_CM_SHAPER_RAMA_REGION_4_5 0x0f53 5106#define mmCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 5107#define mmCM1_CM_SHAPER_RAMA_REGION_6_7 0x0f54 5108#define mmCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 5109#define mmCM1_CM_SHAPER_RAMA_REGION_8_9 0x0f55 5110#define mmCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 5111#define mmCM1_CM_SHAPER_RAMA_REGION_10_11 0x0f56 5112#define mmCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 5113#define mmCM1_CM_SHAPER_RAMA_REGION_12_13 0x0f57 5114#define mmCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 5115#define mmCM1_CM_SHAPER_RAMA_REGION_14_15 0x0f58 5116#define mmCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 5117#define mmCM1_CM_SHAPER_RAMA_REGION_16_17 0x0f59 5118#define mmCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 5119#define mmCM1_CM_SHAPER_RAMA_REGION_18_19 0x0f5a 5120#define mmCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 5121#define mmCM1_CM_SHAPER_RAMA_REGION_20_21 0x0f5b 5122#define mmCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 5123#define mmCM1_CM_SHAPER_RAMA_REGION_22_23 0x0f5c 5124#define mmCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 5125#define mmCM1_CM_SHAPER_RAMA_REGION_24_25 0x0f5d 5126#define mmCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 5127#define mmCM1_CM_SHAPER_RAMA_REGION_26_27 0x0f5e 5128#define mmCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 5129#define mmCM1_CM_SHAPER_RAMA_REGION_28_29 0x0f5f 5130#define mmCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 5131#define mmCM1_CM_SHAPER_RAMA_REGION_30_31 0x0f60 5132#define mmCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 5133#define mmCM1_CM_SHAPER_RAMA_REGION_32_33 0x0f61 5134#define mmCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 5135#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B 0x0f62 5136#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 5137#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G 0x0f63 5138#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 5139#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R 0x0f64 5140#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 5141#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B 0x0f65 5142#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 5143#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G 0x0f66 5144#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 5145#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R 0x0f67 5146#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 5147#define mmCM1_CM_SHAPER_RAMB_REGION_0_1 0x0f68 5148#define mmCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 5149#define mmCM1_CM_SHAPER_RAMB_REGION_2_3 0x0f69 5150#define mmCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 5151#define mmCM1_CM_SHAPER_RAMB_REGION_4_5 0x0f6a 5152#define mmCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 5153#define mmCM1_CM_SHAPER_RAMB_REGION_6_7 0x0f6b 5154#define mmCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 5155#define mmCM1_CM_SHAPER_RAMB_REGION_8_9 0x0f6c 5156#define mmCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 5157#define mmCM1_CM_SHAPER_RAMB_REGION_10_11 0x0f6d 5158#define mmCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 5159#define mmCM1_CM_SHAPER_RAMB_REGION_12_13 0x0f6e 5160#define mmCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 5161#define mmCM1_CM_SHAPER_RAMB_REGION_14_15 0x0f6f 5162#define mmCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 5163#define mmCM1_CM_SHAPER_RAMB_REGION_16_17 0x0f70 5164#define mmCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 5165#define mmCM1_CM_SHAPER_RAMB_REGION_18_19 0x0f71 5166#define mmCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 5167#define mmCM1_CM_SHAPER_RAMB_REGION_20_21 0x0f72 5168#define mmCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 5169#define mmCM1_CM_SHAPER_RAMB_REGION_22_23 0x0f73 5170#define mmCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 5171#define mmCM1_CM_SHAPER_RAMB_REGION_24_25 0x0f74 5172#define mmCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 5173#define mmCM1_CM_SHAPER_RAMB_REGION_26_27 0x0f75 5174#define mmCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 5175#define mmCM1_CM_SHAPER_RAMB_REGION_28_29 0x0f76 5176#define mmCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 5177#define mmCM1_CM_SHAPER_RAMB_REGION_30_31 0x0f77 5178#define mmCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 5179#define mmCM1_CM_SHAPER_RAMB_REGION_32_33 0x0f78 5180#define mmCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 5181#define mmCM1_CM_MEM_PWR_CTRL2 0x0f79 5182#define mmCM1_CM_MEM_PWR_CTRL2_BASE_IDX 2 5183#define mmCM1_CM_MEM_PWR_STATUS2 0x0f7a 5184#define mmCM1_CM_MEM_PWR_STATUS2_BASE_IDX 2 5185#define mmCM1_CM_3DLUT_MODE 0x0f7b 5186#define mmCM1_CM_3DLUT_MODE_BASE_IDX 2 5187#define mmCM1_CM_3DLUT_INDEX 0x0f7c 5188#define mmCM1_CM_3DLUT_INDEX_BASE_IDX 2 5189#define mmCM1_CM_3DLUT_DATA 0x0f7d 5190#define mmCM1_CM_3DLUT_DATA_BASE_IDX 2 5191#define mmCM1_CM_3DLUT_DATA_30BIT 0x0f7e 5192#define mmCM1_CM_3DLUT_DATA_30BIT_BASE_IDX 2 5193#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL 0x0f7f 5194#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 5195#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR 0x0f80 5196#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 5197#define mmCM1_CM_3DLUT_OUT_OFFSET_R 0x0f81 5198#define mmCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 5199#define mmCM1_CM_3DLUT_OUT_OFFSET_G 0x0f82 5200#define mmCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 5201#define mmCM1_CM_3DLUT_OUT_OFFSET_B 0x0f83 5202#define mmCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 5203 5204 5205// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 5206// base address: 0x3e3c 5207#define mmDC_PERFMON13_PERFCOUNTER_CNTL 0x0f8f 5208#define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2 5209#define mmDC_PERFMON13_PERFCOUNTER_CNTL2 0x0f90 5210#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2 5211#define mmDC_PERFMON13_PERFCOUNTER_STATE 0x0f91 5212#define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2 5213#define mmDC_PERFMON13_PERFMON_CNTL 0x0f92 5214#define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2 5215#define mmDC_PERFMON13_PERFMON_CNTL2 0x0f93 5216#define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2 5217#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x0f94 5218#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 5219#define mmDC_PERFMON13_PERFMON_CVALUE_LOW 0x0f95 5220#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2 5221#define mmDC_PERFMON13_PERFMON_HI 0x0f96 5222#define mmDC_PERFMON13_PERFMON_HI_BASE_IDX 2 5223#define mmDC_PERFMON13_PERFMON_LOW 0x0f97 5224#define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX 2 5225 5226 5227// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec 5228// base address: 0xb58 5229#define mmDPP_TOP2_DPP_CONTROL 0x0f9b 5230#define mmDPP_TOP2_DPP_CONTROL_BASE_IDX 2 5231#define mmDPP_TOP2_DPP_SOFT_RESET 0x0f9c 5232#define mmDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2 5233#define mmDPP_TOP2_DPP_CRC_VAL_R_G 0x0f9d 5234#define mmDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2 5235#define mmDPP_TOP2_DPP_CRC_VAL_B_A 0x0f9e 5236#define mmDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2 5237#define mmDPP_TOP2_DPP_CRC_CTRL 0x0f9f 5238#define mmDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2 5239#define mmDPP_TOP2_HOST_READ_CONTROL 0x0fa0 5240#define mmDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2 5241 5242 5243// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec 5244// base address: 0xb58 5245#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0fa5 5246#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 5247#define mmCNVC_CFG2_FORMAT_CONTROL 0x0fa6 5248#define mmCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2 5249#define mmCNVC_CFG2_FCNV_FP_BIAS_R 0x0fa7 5250#define mmCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX 2 5251#define mmCNVC_CFG2_FCNV_FP_BIAS_G 0x0fa8 5252#define mmCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX 2 5253#define mmCNVC_CFG2_FCNV_FP_BIAS_B 0x0fa9 5254#define mmCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX 2 5255#define mmCNVC_CFG2_FCNV_FP_SCALE_R 0x0faa 5256#define mmCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX 2 5257#define mmCNVC_CFG2_FCNV_FP_SCALE_G 0x0fab 5258#define mmCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX 2 5259#define mmCNVC_CFG2_FCNV_FP_SCALE_B 0x0fac 5260#define mmCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX 2 5261#define mmCNVC_CFG2_COLOR_KEYER_CONTROL 0x0fad 5262#define mmCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2 5263#define mmCNVC_CFG2_COLOR_KEYER_ALPHA 0x0fae 5264#define mmCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2 5265#define mmCNVC_CFG2_COLOR_KEYER_RED 0x0faf 5266#define mmCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2 5267#define mmCNVC_CFG2_COLOR_KEYER_GREEN 0x0fb0 5268#define mmCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2 5269#define mmCNVC_CFG2_COLOR_KEYER_BLUE 0x0fb1 5270#define mmCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2 5271#define mmCNVC_CFG2_ALPHA_2BIT_LUT 0x0fb3 5272#define mmCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX 2 5273#define mmCNVC_CFG2_PRE_DEALPHA 0x0fb4 5274#define mmCNVC_CFG2_PRE_DEALPHA_BASE_IDX 2 5275#define mmCNVC_CFG2_PRE_CSC_MODE 0x0fb5 5276#define mmCNVC_CFG2_PRE_CSC_MODE_BASE_IDX 2 5277#define mmCNVC_CFG2_PRE_CSC_C11_C12 0x0fb6 5278#define mmCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX 2 5279#define mmCNVC_CFG2_PRE_CSC_C13_C14 0x0fb7 5280#define mmCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX 2 5281#define mmCNVC_CFG2_PRE_CSC_C21_C22 0x0fb8 5282#define mmCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX 2 5283#define mmCNVC_CFG2_PRE_CSC_C23_C24 0x0fb9 5284#define mmCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX 2 5285#define mmCNVC_CFG2_PRE_CSC_C31_C32 0x0fba 5286#define mmCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX 2 5287#define mmCNVC_CFG2_PRE_CSC_C33_C34 0x0fbb 5288#define mmCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX 2 5289#define mmCNVC_CFG2_PRE_CSC_B_C11_C12 0x0fbc 5290#define mmCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX 2 5291#define mmCNVC_CFG2_PRE_CSC_B_C13_C14 0x0fbd 5292#define mmCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX 2 5293#define mmCNVC_CFG2_PRE_CSC_B_C21_C22 0x0fbe 5294#define mmCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX 2 5295#define mmCNVC_CFG2_PRE_CSC_B_C23_C24 0x0fbf 5296#define mmCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX 2 5297#define mmCNVC_CFG2_PRE_CSC_B_C31_C32 0x0fc0 5298#define mmCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX 2 5299#define mmCNVC_CFG2_PRE_CSC_B_C33_C34 0x0fc1 5300#define mmCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX 2 5301#define mmCNVC_CFG2_CNVC_COEF_FORMAT 0x0fc2 5302#define mmCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX 2 5303#define mmCNVC_CFG2_PRE_DEGAM 0x0fc3 5304#define mmCNVC_CFG2_PRE_DEGAM_BASE_IDX 2 5305#define mmCNVC_CFG2_PRE_REALPHA 0x0fc4 5306#define mmCNVC_CFG2_PRE_REALPHA_BASE_IDX 2 5307 5308 5309// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec 5310// base address: 0xb58 5311#define mmCNVC_CUR2_CURSOR0_CONTROL 0x0fc7 5312#define mmCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX 2 5313#define mmCNVC_CUR2_CURSOR0_COLOR0 0x0fc8 5314#define mmCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX 2 5315#define mmCNVC_CUR2_CURSOR0_COLOR1 0x0fc9 5316#define mmCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX 2 5317#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0x0fca 5318#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 5319 5320// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec 5321// base address: 0xb58 5322#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0fcf 5323#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 5324#define mmDSCL2_SCL_COEF_RAM_TAP_DATA 0x0fd0 5325#define mmDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 5326#define mmDSCL2_SCL_MODE 0x0fd1 5327#define mmDSCL2_SCL_MODE_BASE_IDX 2 5328#define mmDSCL2_SCL_TAP_CONTROL 0x0fd2 5329#define mmDSCL2_SCL_TAP_CONTROL_BASE_IDX 2 5330#define mmDSCL2_DSCL_CONTROL 0x0fd3 5331#define mmDSCL2_DSCL_CONTROL_BASE_IDX 2 5332#define mmDSCL2_DSCL_2TAP_CONTROL 0x0fd4 5333#define mmDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2 5334#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0fd5 5335#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 5336#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0fd6 5337#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 5338#define mmDSCL2_SCL_HORZ_FILTER_INIT 0x0fd7 5339#define mmDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2 5340#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fd8 5341#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 5342#define mmDSCL2_SCL_HORZ_FILTER_INIT_C 0x0fd9 5343#define mmDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 5344#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0fda 5345#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 5346#define mmDSCL2_SCL_VERT_FILTER_INIT 0x0fdb 5347#define mmDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2 5348#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0fdc 5349#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 5350#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fdd 5351#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 5352#define mmDSCL2_SCL_VERT_FILTER_INIT_C 0x0fde 5353#define mmDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 5354#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0fdf 5355#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 5356#define mmDSCL2_SCL_BLACK_COLOR 0x0fe0 5357#define mmDSCL2_SCL_BLACK_COLOR_BASE_IDX 2 5358#define mmDSCL2_DSCL_UPDATE 0x0fe1 5359#define mmDSCL2_DSCL_UPDATE_BASE_IDX 2 5360#define mmDSCL2_DSCL_AUTOCAL 0x0fe2 5361#define mmDSCL2_DSCL_AUTOCAL_BASE_IDX 2 5362#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0fe3 5363#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 5364#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0fe4 5365#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 5366#define mmDSCL2_OTG_H_BLANK 0x0fe5 5367#define mmDSCL2_OTG_H_BLANK_BASE_IDX 2 5368#define mmDSCL2_OTG_V_BLANK 0x0fe6 5369#define mmDSCL2_OTG_V_BLANK_BASE_IDX 2 5370#define mmDSCL2_RECOUT_START 0x0fe7 5371#define mmDSCL2_RECOUT_START_BASE_IDX 2 5372#define mmDSCL2_RECOUT_SIZE 0x0fe8 5373#define mmDSCL2_RECOUT_SIZE_BASE_IDX 2 5374#define mmDSCL2_MPC_SIZE 0x0fe9 5375#define mmDSCL2_MPC_SIZE_BASE_IDX 2 5376#define mmDSCL2_LB_DATA_FORMAT 0x0fea 5377#define mmDSCL2_LB_DATA_FORMAT_BASE_IDX 2 5378#define mmDSCL2_LB_MEMORY_CTRL 0x0feb 5379#define mmDSCL2_LB_MEMORY_CTRL_BASE_IDX 2 5380#define mmDSCL2_LB_V_COUNTER 0x0fec 5381#define mmDSCL2_LB_V_COUNTER_BASE_IDX 2 5382#define mmDSCL2_DSCL_MEM_PWR_CTRL 0x0fed 5383#define mmDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2 5384#define mmDSCL2_DSCL_MEM_PWR_STATUS 0x0fee 5385#define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2 5386#define mmDSCL2_OBUF_CONTROL 0x0fef 5387#define mmDSCL2_OBUF_CONTROL_BASE_IDX 2 5388#define mmDSCL2_OBUF_MEM_PWR_CTRL 0x0ff0 5389#define mmDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2 5390 5391 5392// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec 5393// base address: 0xb58 5394#define mmCM2_CM_CONTROL 0x0ff6 5395#define mmCM2_CM_CONTROL_BASE_IDX 2 5396#define mmCM2_CM_POST_CSC_CONTROL 0x0ff7 5397#define mmCM2_CM_POST_CSC_CONTROL_BASE_IDX 2 5398#define mmCM2_CM_POST_CSC_C11_C12 0x0ff8 5399#define mmCM2_CM_POST_CSC_C11_C12_BASE_IDX 2 5400#define mmCM2_CM_POST_CSC_C13_C14 0x0ff9 5401#define mmCM2_CM_POST_CSC_C13_C14_BASE_IDX 2 5402#define mmCM2_CM_POST_CSC_C21_C22 0x0ffa 5403#define mmCM2_CM_POST_CSC_C21_C22_BASE_IDX 2 5404#define mmCM2_CM_POST_CSC_C23_C24 0x0ffb 5405#define mmCM2_CM_POST_CSC_C23_C24_BASE_IDX 2 5406#define mmCM2_CM_POST_CSC_C31_C32 0x0ffc 5407#define mmCM2_CM_POST_CSC_C31_C32_BASE_IDX 2 5408#define mmCM2_CM_POST_CSC_C33_C34 0x0ffd 5409#define mmCM2_CM_POST_CSC_C33_C34_BASE_IDX 2 5410#define mmCM2_CM_POST_CSC_B_C11_C12 0x0ffe 5411#define mmCM2_CM_POST_CSC_B_C11_C12_BASE_IDX 2 5412#define mmCM2_CM_POST_CSC_B_C13_C14 0x0fff 5413#define mmCM2_CM_POST_CSC_B_C13_C14_BASE_IDX 2 5414#define mmCM2_CM_POST_CSC_B_C21_C22 0x1000 5415#define mmCM2_CM_POST_CSC_B_C21_C22_BASE_IDX 2 5416#define mmCM2_CM_POST_CSC_B_C23_C24 0x1001 5417#define mmCM2_CM_POST_CSC_B_C23_C24_BASE_IDX 2 5418#define mmCM2_CM_POST_CSC_B_C31_C32 0x1002 5419#define mmCM2_CM_POST_CSC_B_C31_C32_BASE_IDX 2 5420#define mmCM2_CM_POST_CSC_B_C33_C34 0x1003 5421#define mmCM2_CM_POST_CSC_B_C33_C34_BASE_IDX 2 5422#define mmCM2_CM_GAMUT_REMAP_CONTROL 0x1004 5423#define mmCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 5424#define mmCM2_CM_GAMUT_REMAP_C11_C12 0x1005 5425#define mmCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 5426#define mmCM2_CM_GAMUT_REMAP_C13_C14 0x1006 5427#define mmCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 5428#define mmCM2_CM_GAMUT_REMAP_C21_C22 0x1007 5429#define mmCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 5430#define mmCM2_CM_GAMUT_REMAP_C23_C24 0x1008 5431#define mmCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 5432#define mmCM2_CM_GAMUT_REMAP_C31_C32 0x1009 5433#define mmCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 5434#define mmCM2_CM_GAMUT_REMAP_C33_C34 0x100a 5435#define mmCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 5436#define mmCM2_CM_GAMUT_REMAP_B_C11_C12 0x100b 5437#define mmCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 5438#define mmCM2_CM_GAMUT_REMAP_B_C13_C14 0x100c 5439#define mmCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 5440#define mmCM2_CM_GAMUT_REMAP_B_C21_C22 0x100d 5441#define mmCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 5442#define mmCM2_CM_GAMUT_REMAP_B_C23_C24 0x100e 5443#define mmCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 5444#define mmCM2_CM_GAMUT_REMAP_B_C31_C32 0x100f 5445#define mmCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 5446#define mmCM2_CM_GAMUT_REMAP_B_C33_C34 0x1010 5447#define mmCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 5448#define mmCM2_CM_BIAS_CR_R 0x1011 5449#define mmCM2_CM_BIAS_CR_R_BASE_IDX 2 5450#define mmCM2_CM_BIAS_Y_G_CB_B 0x1012 5451#define mmCM2_CM_BIAS_Y_G_CB_B_BASE_IDX 2 5452#define mmCM2_CM_GAMCOR_CONTROL 0x1013 5453#define mmCM2_CM_GAMCOR_CONTROL_BASE_IDX 2 5454#define mmCM2_CM_GAMCOR_LUT_INDEX 0x1014 5455#define mmCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 5456#define mmCM2_CM_GAMCOR_LUT_DATA 0x1015 5457#define mmCM2_CM_GAMCOR_LUT_DATA_BASE_IDX 2 5458#define mmCM2_CM_GAMCOR_LUT_CONTROL 0x1016 5459#define mmCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 5460#define mmCM2_CM_GAMCOR_RAMA_START_CNTL_B 0x1017 5461#define mmCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 5462#define mmCM2_CM_GAMCOR_RAMA_START_CNTL_G 0x1018 5463#define mmCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 5464#define mmCM2_CM_GAMCOR_RAMA_START_CNTL_R 0x1019 5465#define mmCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 5466#define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x101a 5467#define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 5468#define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x101b 5469#define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 5470#define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x101c 5471#define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 5472#define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x101d 5473#define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 5474#define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x101e 5475#define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 5476#define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x101f 5477#define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 5478#define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_B 0x1020 5479#define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 5480#define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_B 0x1021 5481#define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 5482#define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_G 0x1022 5483#define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 5484#define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_G 0x1023 5485#define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 5486#define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_R 0x1024 5487#define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 5488#define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_R 0x1025 5489#define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 5490#define mmCM2_CM_GAMCOR_RAMA_OFFSET_B 0x1026 5491#define mmCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 5492#define mmCM2_CM_GAMCOR_RAMA_OFFSET_G 0x1027 5493#define mmCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 5494#define mmCM2_CM_GAMCOR_RAMA_OFFSET_R 0x1028 5495#define mmCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 5496#define mmCM2_CM_GAMCOR_RAMA_REGION_0_1 0x1029 5497#define mmCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 5498#define mmCM2_CM_GAMCOR_RAMA_REGION_2_3 0x102a 5499#define mmCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 5500#define mmCM2_CM_GAMCOR_RAMA_REGION_4_5 0x102b 5501#define mmCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 5502#define mmCM2_CM_GAMCOR_RAMA_REGION_6_7 0x102c 5503#define mmCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 5504#define mmCM2_CM_GAMCOR_RAMA_REGION_8_9 0x102d 5505#define mmCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 5506#define mmCM2_CM_GAMCOR_RAMA_REGION_10_11 0x102e 5507#define mmCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 5508#define mmCM2_CM_GAMCOR_RAMA_REGION_12_13 0x102f 5509#define mmCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 5510#define mmCM2_CM_GAMCOR_RAMA_REGION_14_15 0x1030 5511#define mmCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 5512#define mmCM2_CM_GAMCOR_RAMA_REGION_16_17 0x1031 5513#define mmCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 5514#define mmCM2_CM_GAMCOR_RAMA_REGION_18_19 0x1032 5515#define mmCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 5516#define mmCM2_CM_GAMCOR_RAMA_REGION_20_21 0x1033 5517#define mmCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 5518#define mmCM2_CM_GAMCOR_RAMA_REGION_22_23 0x1034 5519#define mmCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 5520#define mmCM2_CM_GAMCOR_RAMA_REGION_24_25 0x1035 5521#define mmCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 5522#define mmCM2_CM_GAMCOR_RAMA_REGION_26_27 0x1036 5523#define mmCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 5524#define mmCM2_CM_GAMCOR_RAMA_REGION_28_29 0x1037 5525#define mmCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 5526#define mmCM2_CM_GAMCOR_RAMA_REGION_30_31 0x1038 5527#define mmCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 5528#define mmCM2_CM_GAMCOR_RAMA_REGION_32_33 0x1039 5529#define mmCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 5530#define mmCM2_CM_GAMCOR_RAMB_START_CNTL_B 0x103a 5531#define mmCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 5532#define mmCM2_CM_GAMCOR_RAMB_START_CNTL_G 0x103b 5533#define mmCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 5534#define mmCM2_CM_GAMCOR_RAMB_START_CNTL_R 0x103c 5535#define mmCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 5536#define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x103d 5537#define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 5538#define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x103e 5539#define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 5540#define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x103f 5541#define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 5542#define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x1040 5543#define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 5544#define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x1041 5545#define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 5546#define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x1042 5547#define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 5548#define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_B 0x1043 5549#define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 5550#define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_B 0x1044 5551#define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 5552#define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_G 0x1045 5553#define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 5554#define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_G 0x1046 5555#define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 5556#define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_R 0x1047 5557#define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 5558#define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_R 0x1048 5559#define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 5560#define mmCM2_CM_GAMCOR_RAMB_OFFSET_B 0x1049 5561#define mmCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 5562#define mmCM2_CM_GAMCOR_RAMB_OFFSET_G 0x104a 5563#define mmCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 5564#define mmCM2_CM_GAMCOR_RAMB_OFFSET_R 0x104b 5565#define mmCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 5566#define mmCM2_CM_GAMCOR_RAMB_REGION_0_1 0x104c 5567#define mmCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 5568#define mmCM2_CM_GAMCOR_RAMB_REGION_2_3 0x104d 5569#define mmCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 5570#define mmCM2_CM_GAMCOR_RAMB_REGION_4_5 0x104e 5571#define mmCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 5572#define mmCM2_CM_GAMCOR_RAMB_REGION_6_7 0x104f 5573#define mmCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 5574#define mmCM2_CM_GAMCOR_RAMB_REGION_8_9 0x1050 5575#define mmCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 5576#define mmCM2_CM_GAMCOR_RAMB_REGION_10_11 0x1051 5577#define mmCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 5578#define mmCM2_CM_GAMCOR_RAMB_REGION_12_13 0x1052 5579#define mmCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 5580#define mmCM2_CM_GAMCOR_RAMB_REGION_14_15 0x1053 5581#define mmCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 5582#define mmCM2_CM_GAMCOR_RAMB_REGION_16_17 0x1054 5583#define mmCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 5584#define mmCM2_CM_GAMCOR_RAMB_REGION_18_19 0x1055 5585#define mmCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 5586#define mmCM2_CM_GAMCOR_RAMB_REGION_20_21 0x1056 5587#define mmCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 5588#define mmCM2_CM_GAMCOR_RAMB_REGION_22_23 0x1057 5589#define mmCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 5590#define mmCM2_CM_GAMCOR_RAMB_REGION_24_25 0x1058 5591#define mmCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 5592#define mmCM2_CM_GAMCOR_RAMB_REGION_26_27 0x1059 5593#define mmCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 5594#define mmCM2_CM_GAMCOR_RAMB_REGION_28_29 0x105a 5595#define mmCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 5596#define mmCM2_CM_GAMCOR_RAMB_REGION_30_31 0x105b 5597#define mmCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 5598#define mmCM2_CM_GAMCOR_RAMB_REGION_32_33 0x105c 5599#define mmCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 5600#define mmCM2_CM_BLNDGAM_CONTROL 0x105d 5601#define mmCM2_CM_BLNDGAM_CONTROL_BASE_IDX 2 5602#define mmCM2_CM_BLNDGAM_LUT_INDEX 0x105e 5603#define mmCM2_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 5604#define mmCM2_CM_BLNDGAM_LUT_DATA 0x105f 5605#define mmCM2_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 5606#define mmCM2_CM_BLNDGAM_LUT_CONTROL 0x1060 5607#define mmCM2_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 5608#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B 0x1061 5609#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 5610#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G 0x1062 5611#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 5612#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R 0x1063 5613#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 5614#define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x1064 5615#define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 5616#define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x1065 5617#define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 5618#define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x1066 5619#define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 5620#define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x1067 5621#define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 5622#define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x1068 5623#define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 5624#define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x1069 5625#define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 5626#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B 0x106a 5627#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 5628#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B 0x106b 5629#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 5630#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G 0x106c 5631#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 5632#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G 0x106d 5633#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 5634#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R 0x106e 5635#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 5636#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R 0x106f 5637#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 5638#define mmCM2_CM_BLNDGAM_RAMA_OFFSET_B 0x1070 5639#define mmCM2_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 5640#define mmCM2_CM_BLNDGAM_RAMA_OFFSET_G 0x1071 5641#define mmCM2_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 5642#define mmCM2_CM_BLNDGAM_RAMA_OFFSET_R 0x1072 5643#define mmCM2_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 5644#define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1 0x1073 5645#define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 5646#define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3 0x1074 5647#define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 5648#define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5 0x1075 5649#define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 5650#define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7 0x1076 5651#define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 5652#define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9 0x1077 5653#define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 5654#define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11 0x1078 5655#define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 5656#define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13 0x1079 5657#define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 5658#define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15 0x107a 5659#define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 5660#define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17 0x107b 5661#define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 5662#define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19 0x107c 5663#define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 5664#define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21 0x107d 5665#define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 5666#define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23 0x107e 5667#define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 5668#define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25 0x107f 5669#define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 5670#define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27 0x1080 5671#define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 5672#define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29 0x1081 5673#define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 5674#define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31 0x1082 5675#define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 5676#define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33 0x1083 5677#define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 5678#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B 0x1084 5679#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 5680#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G 0x1085 5681#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 5682#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R 0x1086 5683#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 5684#define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x1087 5685#define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 5686#define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x1088 5687#define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 5688#define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x1089 5689#define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 5690#define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x108a 5691#define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 5692#define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x108b 5693#define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 5694#define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x108c 5695#define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 5696#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B 0x108d 5697#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 5698#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B 0x108e 5699#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 5700#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G 0x108f 5701#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 5702#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G 0x1090 5703#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 5704#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R 0x1091 5705#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 5706#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R 0x1092 5707#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 5708#define mmCM2_CM_BLNDGAM_RAMB_OFFSET_B 0x1093 5709#define mmCM2_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 5710#define mmCM2_CM_BLNDGAM_RAMB_OFFSET_G 0x1094 5711#define mmCM2_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 5712#define mmCM2_CM_BLNDGAM_RAMB_OFFSET_R 0x1095 5713#define mmCM2_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 5714#define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1 0x1096 5715#define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 5716#define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3 0x1097 5717#define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 5718#define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5 0x1098 5719#define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 5720#define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7 0x1099 5721#define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 5722#define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9 0x109a 5723#define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 5724#define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11 0x109b 5725#define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 5726#define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13 0x109c 5727#define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 5728#define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15 0x109d 5729#define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 5730#define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17 0x109e 5731#define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 5732#define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19 0x109f 5733#define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 5734#define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21 0x10a0 5735#define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 5736#define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23 0x10a1 5737#define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 5738#define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25 0x10a2 5739#define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 5740#define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27 0x10a3 5741#define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 5742#define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29 0x10a4 5743#define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 5744#define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31 0x10a5 5745#define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 5746#define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33 0x10a6 5747#define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 5748#define mmCM2_CM_HDR_MULT_COEF 0x10a7 5749#define mmCM2_CM_HDR_MULT_COEF_BASE_IDX 2 5750#define mmCM2_CM_MEM_PWR_CTRL 0x10a8 5751#define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX 2 5752#define mmCM2_CM_MEM_PWR_STATUS 0x10a9 5753#define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX 2 5754#define mmCM2_CM_DEALPHA 0x10ab 5755#define mmCM2_CM_DEALPHA_BASE_IDX 2 5756#define mmCM2_CM_COEF_FORMAT 0x10ac 5757#define mmCM2_CM_COEF_FORMAT_BASE_IDX 2 5758#define mmCM2_CM_SHAPER_CONTROL 0x10ad 5759#define mmCM2_CM_SHAPER_CONTROL_BASE_IDX 2 5760#define mmCM2_CM_SHAPER_OFFSET_R 0x10ae 5761#define mmCM2_CM_SHAPER_OFFSET_R_BASE_IDX 2 5762#define mmCM2_CM_SHAPER_OFFSET_G 0x10af 5763#define mmCM2_CM_SHAPER_OFFSET_G_BASE_IDX 2 5764#define mmCM2_CM_SHAPER_OFFSET_B 0x10b0 5765#define mmCM2_CM_SHAPER_OFFSET_B_BASE_IDX 2 5766#define mmCM2_CM_SHAPER_SCALE_R 0x10b1 5767#define mmCM2_CM_SHAPER_SCALE_R_BASE_IDX 2 5768#define mmCM2_CM_SHAPER_SCALE_G_B 0x10b2 5769#define mmCM2_CM_SHAPER_SCALE_G_B_BASE_IDX 2 5770#define mmCM2_CM_SHAPER_LUT_INDEX 0x10b3 5771#define mmCM2_CM_SHAPER_LUT_INDEX_BASE_IDX 2 5772#define mmCM2_CM_SHAPER_LUT_DATA 0x10b4 5773#define mmCM2_CM_SHAPER_LUT_DATA_BASE_IDX 2 5774#define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK 0x10b5 5775#define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 5776#define mmCM2_CM_SHAPER_RAMA_START_CNTL_B 0x10b6 5777#define mmCM2_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 5778#define mmCM2_CM_SHAPER_RAMA_START_CNTL_G 0x10b7 5779#define mmCM2_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 5780#define mmCM2_CM_SHAPER_RAMA_START_CNTL_R 0x10b8 5781#define mmCM2_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 5782#define mmCM2_CM_SHAPER_RAMA_END_CNTL_B 0x10b9 5783#define mmCM2_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 5784#define mmCM2_CM_SHAPER_RAMA_END_CNTL_G 0x10ba 5785#define mmCM2_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 5786#define mmCM2_CM_SHAPER_RAMA_END_CNTL_R 0x10bb 5787#define mmCM2_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 5788#define mmCM2_CM_SHAPER_RAMA_REGION_0_1 0x10bc 5789#define mmCM2_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 5790#define mmCM2_CM_SHAPER_RAMA_REGION_2_3 0x10bd 5791#define mmCM2_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 5792#define mmCM2_CM_SHAPER_RAMA_REGION_4_5 0x10be 5793#define mmCM2_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 5794#define mmCM2_CM_SHAPER_RAMA_REGION_6_7 0x10bf 5795#define mmCM2_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 5796#define mmCM2_CM_SHAPER_RAMA_REGION_8_9 0x10c0 5797#define mmCM2_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 5798#define mmCM2_CM_SHAPER_RAMA_REGION_10_11 0x10c1 5799#define mmCM2_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 5800#define mmCM2_CM_SHAPER_RAMA_REGION_12_13 0x10c2 5801#define mmCM2_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 5802#define mmCM2_CM_SHAPER_RAMA_REGION_14_15 0x10c3 5803#define mmCM2_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 5804#define mmCM2_CM_SHAPER_RAMA_REGION_16_17 0x10c4 5805#define mmCM2_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 5806#define mmCM2_CM_SHAPER_RAMA_REGION_18_19 0x10c5 5807#define mmCM2_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 5808#define mmCM2_CM_SHAPER_RAMA_REGION_20_21 0x10c6 5809#define mmCM2_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 5810#define mmCM2_CM_SHAPER_RAMA_REGION_22_23 0x10c7 5811#define mmCM2_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 5812#define mmCM2_CM_SHAPER_RAMA_REGION_24_25 0x10c8 5813#define mmCM2_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 5814#define mmCM2_CM_SHAPER_RAMA_REGION_26_27 0x10c9 5815#define mmCM2_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 5816#define mmCM2_CM_SHAPER_RAMA_REGION_28_29 0x10ca 5817#define mmCM2_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 5818#define mmCM2_CM_SHAPER_RAMA_REGION_30_31 0x10cb 5819#define mmCM2_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 5820#define mmCM2_CM_SHAPER_RAMA_REGION_32_33 0x10cc 5821#define mmCM2_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 5822#define mmCM2_CM_SHAPER_RAMB_START_CNTL_B 0x10cd 5823#define mmCM2_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 5824#define mmCM2_CM_SHAPER_RAMB_START_CNTL_G 0x10ce 5825#define mmCM2_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 5826#define mmCM2_CM_SHAPER_RAMB_START_CNTL_R 0x10cf 5827#define mmCM2_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 5828#define mmCM2_CM_SHAPER_RAMB_END_CNTL_B 0x10d0 5829#define mmCM2_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 5830#define mmCM2_CM_SHAPER_RAMB_END_CNTL_G 0x10d1 5831#define mmCM2_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 5832#define mmCM2_CM_SHAPER_RAMB_END_CNTL_R 0x10d2 5833#define mmCM2_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 5834#define mmCM2_CM_SHAPER_RAMB_REGION_0_1 0x10d3 5835#define mmCM2_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 5836#define mmCM2_CM_SHAPER_RAMB_REGION_2_3 0x10d4 5837#define mmCM2_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 5838#define mmCM2_CM_SHAPER_RAMB_REGION_4_5 0x10d5 5839#define mmCM2_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 5840#define mmCM2_CM_SHAPER_RAMB_REGION_6_7 0x10d6 5841#define mmCM2_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 5842#define mmCM2_CM_SHAPER_RAMB_REGION_8_9 0x10d7 5843#define mmCM2_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 5844#define mmCM2_CM_SHAPER_RAMB_REGION_10_11 0x10d8 5845#define mmCM2_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 5846#define mmCM2_CM_SHAPER_RAMB_REGION_12_13 0x10d9 5847#define mmCM2_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 5848#define mmCM2_CM_SHAPER_RAMB_REGION_14_15 0x10da 5849#define mmCM2_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 5850#define mmCM2_CM_SHAPER_RAMB_REGION_16_17 0x10db 5851#define mmCM2_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 5852#define mmCM2_CM_SHAPER_RAMB_REGION_18_19 0x10dc 5853#define mmCM2_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 5854#define mmCM2_CM_SHAPER_RAMB_REGION_20_21 0x10dd 5855#define mmCM2_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 5856#define mmCM2_CM_SHAPER_RAMB_REGION_22_23 0x10de 5857#define mmCM2_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 5858#define mmCM2_CM_SHAPER_RAMB_REGION_24_25 0x10df 5859#define mmCM2_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 5860#define mmCM2_CM_SHAPER_RAMB_REGION_26_27 0x10e0 5861#define mmCM2_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 5862#define mmCM2_CM_SHAPER_RAMB_REGION_28_29 0x10e1 5863#define mmCM2_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 5864#define mmCM2_CM_SHAPER_RAMB_REGION_30_31 0x10e2 5865#define mmCM2_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 5866#define mmCM2_CM_SHAPER_RAMB_REGION_32_33 0x10e3 5867#define mmCM2_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 5868#define mmCM2_CM_MEM_PWR_CTRL2 0x10e4 5869#define mmCM2_CM_MEM_PWR_CTRL2_BASE_IDX 2 5870#define mmCM2_CM_MEM_PWR_STATUS2 0x10e5 5871#define mmCM2_CM_MEM_PWR_STATUS2_BASE_IDX 2 5872#define mmCM2_CM_3DLUT_MODE 0x10e6 5873#define mmCM2_CM_3DLUT_MODE_BASE_IDX 2 5874#define mmCM2_CM_3DLUT_INDEX 0x10e7 5875#define mmCM2_CM_3DLUT_INDEX_BASE_IDX 2 5876#define mmCM2_CM_3DLUT_DATA 0x10e8 5877#define mmCM2_CM_3DLUT_DATA_BASE_IDX 2 5878#define mmCM2_CM_3DLUT_DATA_30BIT 0x10e9 5879#define mmCM2_CM_3DLUT_DATA_30BIT_BASE_IDX 2 5880#define mmCM2_CM_3DLUT_READ_WRITE_CONTROL 0x10ea 5881#define mmCM2_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 5882#define mmCM2_CM_3DLUT_OUT_NORM_FACTOR 0x10eb 5883#define mmCM2_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 5884#define mmCM2_CM_3DLUT_OUT_OFFSET_R 0x10ec 5885#define mmCM2_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 5886#define mmCM2_CM_3DLUT_OUT_OFFSET_G 0x10ed 5887#define mmCM2_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 5888#define mmCM2_CM_3DLUT_OUT_OFFSET_B 0x10ee 5889#define mmCM2_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 5890 5891 5892// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 5893// base address: 0x43e8 5894#define mmDC_PERFMON14_PERFCOUNTER_CNTL 0x10fa 5895#define mmDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX 2 5896#define mmDC_PERFMON14_PERFCOUNTER_CNTL2 0x10fb 5897#define mmDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX 2 5898#define mmDC_PERFMON14_PERFCOUNTER_STATE 0x10fc 5899#define mmDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX 2 5900#define mmDC_PERFMON14_PERFMON_CNTL 0x10fd 5901#define mmDC_PERFMON14_PERFMON_CNTL_BASE_IDX 2 5902#define mmDC_PERFMON14_PERFMON_CNTL2 0x10fe 5903#define mmDC_PERFMON14_PERFMON_CNTL2_BASE_IDX 2 5904#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0x10ff 5905#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 5906#define mmDC_PERFMON14_PERFMON_CVALUE_LOW 0x1100 5907#define mmDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX 2 5908#define mmDC_PERFMON14_PERFMON_HI 0x1101 5909#define mmDC_PERFMON14_PERFMON_HI_BASE_IDX 2 5910#define mmDC_PERFMON14_PERFMON_LOW 0x1102 5911#define mmDC_PERFMON14_PERFMON_LOW_BASE_IDX 2 5912 5913 5914// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec 5915// base address: 0x1104 5916#define mmDPP_TOP3_DPP_CONTROL 0x1106 5917#define mmDPP_TOP3_DPP_CONTROL_BASE_IDX 2 5918#define mmDPP_TOP3_DPP_SOFT_RESET 0x1107 5919#define mmDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2 5920#define mmDPP_TOP3_DPP_CRC_VAL_R_G 0x1108 5921#define mmDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2 5922#define mmDPP_TOP3_DPP_CRC_VAL_B_A 0x1109 5923#define mmDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2 5924#define mmDPP_TOP3_DPP_CRC_CTRL 0x110a 5925#define mmDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2 5926#define mmDPP_TOP3_HOST_READ_CONTROL 0x110b 5927#define mmDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2 5928 5929 5930// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec 5931// base address: 0x1104 5932#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x1110 5933#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 5934#define mmCNVC_CFG3_FORMAT_CONTROL 0x1111 5935#define mmCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2 5936#define mmCNVC_CFG3_FCNV_FP_BIAS_R 0x1112 5937#define mmCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX 2 5938#define mmCNVC_CFG3_FCNV_FP_BIAS_G 0x1113 5939#define mmCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX 2 5940#define mmCNVC_CFG3_FCNV_FP_BIAS_B 0x1114 5941#define mmCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX 2 5942#define mmCNVC_CFG3_FCNV_FP_SCALE_R 0x1115 5943#define mmCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX 2 5944#define mmCNVC_CFG3_FCNV_FP_SCALE_G 0x1116 5945#define mmCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX 2 5946#define mmCNVC_CFG3_FCNV_FP_SCALE_B 0x1117 5947#define mmCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX 2 5948#define mmCNVC_CFG3_COLOR_KEYER_CONTROL 0x1118 5949#define mmCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2 5950#define mmCNVC_CFG3_COLOR_KEYER_ALPHA 0x1119 5951#define mmCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2 5952#define mmCNVC_CFG3_COLOR_KEYER_RED 0x111a 5953#define mmCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2 5954#define mmCNVC_CFG3_COLOR_KEYER_GREEN 0x111b 5955#define mmCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2 5956#define mmCNVC_CFG3_COLOR_KEYER_BLUE 0x111c 5957#define mmCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2 5958#define mmCNVC_CFG3_ALPHA_2BIT_LUT 0x111e 5959#define mmCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX 2 5960#define mmCNVC_CFG3_PRE_DEALPHA 0x111f 5961#define mmCNVC_CFG3_PRE_DEALPHA_BASE_IDX 2 5962#define mmCNVC_CFG3_PRE_CSC_MODE 0x1120 5963#define mmCNVC_CFG3_PRE_CSC_MODE_BASE_IDX 2 5964#define mmCNVC_CFG3_PRE_CSC_C11_C12 0x1121 5965#define mmCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX 2 5966#define mmCNVC_CFG3_PRE_CSC_C13_C14 0x1122 5967#define mmCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX 2 5968#define mmCNVC_CFG3_PRE_CSC_C21_C22 0x1123 5969#define mmCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX 2 5970#define mmCNVC_CFG3_PRE_CSC_C23_C24 0x1124 5971#define mmCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX 2 5972#define mmCNVC_CFG3_PRE_CSC_C31_C32 0x1125 5973#define mmCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX 2 5974#define mmCNVC_CFG3_PRE_CSC_C33_C34 0x1126 5975#define mmCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX 2 5976#define mmCNVC_CFG3_PRE_CSC_B_C11_C12 0x1127 5977#define mmCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX 2 5978#define mmCNVC_CFG3_PRE_CSC_B_C13_C14 0x1128 5979#define mmCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX 2 5980#define mmCNVC_CFG3_PRE_CSC_B_C21_C22 0x1129 5981#define mmCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX 2 5982#define mmCNVC_CFG3_PRE_CSC_B_C23_C24 0x112a 5983#define mmCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX 2 5984#define mmCNVC_CFG3_PRE_CSC_B_C31_C32 0x112b 5985#define mmCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX 2 5986#define mmCNVC_CFG3_PRE_CSC_B_C33_C34 0x112c 5987#define mmCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX 2 5988#define mmCNVC_CFG3_CNVC_COEF_FORMAT 0x112d 5989#define mmCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX 2 5990#define mmCNVC_CFG3_PRE_DEGAM 0x112e 5991#define mmCNVC_CFG3_PRE_DEGAM_BASE_IDX 2 5992#define mmCNVC_CFG3_PRE_REALPHA 0x112f 5993#define mmCNVC_CFG3_PRE_REALPHA_BASE_IDX 2 5994 5995 5996// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec 5997// base address: 0x1104 5998#define mmCNVC_CUR3_CURSOR0_CONTROL 0x1132 5999#define mmCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX 2 6000#define mmCNVC_CUR3_CURSOR0_COLOR0 0x1133
6001#define mmCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX 2 6002#define mmCNVC_CUR3_CURSOR0_COLOR1 0x1134 6003#define mmCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX 2 6004#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0x1135 6005#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 6006 6007 6008// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec 6009// base address: 0x1104 6010#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT 0x113a 6011#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 6012#define mmDSCL3_SCL_COEF_RAM_TAP_DATA 0x113b 6013#define mmDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 6014#define mmDSCL3_SCL_MODE 0x113c 6015#define mmDSCL3_SCL_MODE_BASE_IDX 2 6016#define mmDSCL3_SCL_TAP_CONTROL 0x113d 6017#define mmDSCL3_SCL_TAP_CONTROL_BASE_IDX 2 6018#define mmDSCL3_DSCL_CONTROL 0x113e 6019#define mmDSCL3_DSCL_CONTROL_BASE_IDX 2 6020#define mmDSCL3_DSCL_2TAP_CONTROL 0x113f 6021#define mmDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2 6022#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x1140 6023#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 6024#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x1141 6025#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 6026#define mmDSCL3_SCL_HORZ_FILTER_INIT 0x1142 6027#define mmDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2 6028#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1143 6029#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 6030#define mmDSCL3_SCL_HORZ_FILTER_INIT_C 0x1144 6031#define mmDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 6032#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x1145 6033#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 6034#define mmDSCL3_SCL_VERT_FILTER_INIT 0x1146 6035#define mmDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2 6036#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT 0x1147 6037#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 6038#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x1148 6039#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 6040#define mmDSCL3_SCL_VERT_FILTER_INIT_C 0x1149 6041#define mmDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 6042#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x114a 6043#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 6044#define mmDSCL3_SCL_BLACK_COLOR 0x114b 6045#define mmDSCL3_SCL_BLACK_COLOR_BASE_IDX 2 6046#define mmDSCL3_DSCL_UPDATE 0x114c 6047#define mmDSCL3_DSCL_UPDATE_BASE_IDX 2 6048#define mmDSCL3_DSCL_AUTOCAL 0x114d 6049#define mmDSCL3_DSCL_AUTOCAL_BASE_IDX 2 6050#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x114e 6051#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 6052#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x114f 6053#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 6054#define mmDSCL3_OTG_H_BLANK 0x1150 6055#define mmDSCL3_OTG_H_BLANK_BASE_IDX 2 6056#define mmDSCL3_OTG_V_BLANK 0x1151 6057#define mmDSCL3_OTG_V_BLANK_BASE_IDX 2 6058#define mmDSCL3_RECOUT_START 0x1152 6059#define mmDSCL3_RECOUT_START_BASE_IDX 2 6060#define mmDSCL3_RECOUT_SIZE 0x1153 6061#define mmDSCL3_RECOUT_SIZE_BASE_IDX 2 6062#define mmDSCL3_MPC_SIZE 0x1154 6063#define mmDSCL3_MPC_SIZE_BASE_IDX 2 6064#define mmDSCL3_LB_DATA_FORMAT 0x1155 6065#define mmDSCL3_LB_DATA_FORMAT_BASE_IDX 2 6066#define mmDSCL3_LB_MEMORY_CTRL 0x1156 6067#define mmDSCL3_LB_MEMORY_CTRL_BASE_IDX 2 6068#define mmDSCL3_LB_V_COUNTER 0x1157 6069#define mmDSCL3_LB_V_COUNTER_BASE_IDX 2 6070#define mmDSCL3_DSCL_MEM_PWR_CTRL 0x1158 6071#define mmDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2 6072#define mmDSCL3_DSCL_MEM_PWR_STATUS 0x1159 6073#define mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2 6074#define mmDSCL3_OBUF_CONTROL 0x115a 6075#define mmDSCL3_OBUF_CONTROL_BASE_IDX 2 6076#define mmDSCL3_OBUF_MEM_PWR_CTRL 0x115b 6077#define mmDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2 6078 6079 6080// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec 6081// base address: 0x1104 6082#define mmCM3_CM_CONTROL 0x1161 6083#define mmCM3_CM_CONTROL_BASE_IDX 2 6084#define mmCM3_CM_POST_CSC_CONTROL 0x1162 6085#define mmCM3_CM_POST_CSC_CONTROL_BASE_IDX 2 6086#define mmCM3_CM_POST_CSC_C11_C12 0x1163 6087#define mmCM3_CM_POST_CSC_C11_C12_BASE_IDX 2 6088#define mmCM3_CM_POST_CSC_C13_C14 0x1164 6089#define mmCM3_CM_POST_CSC_C13_C14_BASE_IDX 2 6090#define mmCM3_CM_POST_CSC_C21_C22 0x1165 6091#define mmCM3_CM_POST_CSC_C21_C22_BASE_IDX 2 6092#define mmCM3_CM_POST_CSC_C23_C24 0x1166 6093#define mmCM3_CM_POST_CSC_C23_C24_BASE_IDX 2 6094#define mmCM3_CM_POST_CSC_C31_C32 0x1167 6095#define mmCM3_CM_POST_CSC_C31_C32_BASE_IDX 2 6096#define mmCM3_CM_POST_CSC_C33_C34 0x1168 6097#define mmCM3_CM_POST_CSC_C33_C34_BASE_IDX 2 6098#define mmCM3_CM_POST_CSC_B_C11_C12 0x1169 6099#define mmCM3_CM_POST_CSC_B_C11_C12_BASE_IDX 2 6100#define mmCM3_CM_POST_CSC_B_C13_C14 0x116a 6101#define mmCM3_CM_POST_CSC_B_C13_C14_BASE_IDX 2 6102#define mmCM3_CM_POST_CSC_B_C21_C22 0x116b 6103#define mmCM3_CM_POST_CSC_B_C21_C22_BASE_IDX 2 6104#define mmCM3_CM_POST_CSC_B_C23_C24 0x116c 6105#define mmCM3_CM_POST_CSC_B_C23_C24_BASE_IDX 2 6106#define mmCM3_CM_POST_CSC_B_C31_C32 0x116d 6107#define mmCM3_CM_POST_CSC_B_C31_C32_BASE_IDX 2 6108#define mmCM3_CM_POST_CSC_B_C33_C34 0x116e 6109#define mmCM3_CM_POST_CSC_B_C33_C34_BASE_IDX 2 6110#define mmCM3_CM_GAMUT_REMAP_CONTROL 0x116f 6111#define mmCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 6112#define mmCM3_CM_GAMUT_REMAP_C11_C12 0x1170 6113#define mmCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 6114#define mmCM3_CM_GAMUT_REMAP_C13_C14 0x1171 6115#define mmCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 6116#define mmCM3_CM_GAMUT_REMAP_C21_C22 0x1172 6117#define mmCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 6118#define mmCM3_CM_GAMUT_REMAP_C23_C24 0x1173 6119#define mmCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 6120#define mmCM3_CM_GAMUT_REMAP_C31_C32 0x1174 6121#define mmCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 6122#define mmCM3_CM_GAMUT_REMAP_C33_C34 0x1175 6123#define mmCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 6124#define mmCM3_CM_GAMUT_REMAP_B_C11_C12 0x1176 6125#define mmCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 6126#define mmCM3_CM_GAMUT_REMAP_B_C13_C14 0x1177 6127#define mmCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 6128#define mmCM3_CM_GAMUT_REMAP_B_C21_C22 0x1178 6129#define mmCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 6130#define mmCM3_CM_GAMUT_REMAP_B_C23_C24 0x1179 6131#define mmCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 6132#define mmCM3_CM_GAMUT_REMAP_B_C31_C32 0x117a 6133#define mmCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 6134#define mmCM3_CM_GAMUT_REMAP_B_C33_C34 0x117b 6135#define mmCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 6136#define mmCM3_CM_BIAS_CR_R 0x117c 6137#define mmCM3_CM_BIAS_CR_R_BASE_IDX 2 6138#define mmCM3_CM_BIAS_Y_G_CB_B 0x117d 6139#define mmCM3_CM_BIAS_Y_G_CB_B_BASE_IDX 2 6140#define mmCM3_CM_GAMCOR_CONTROL 0x117e 6141#define mmCM3_CM_GAMCOR_CONTROL_BASE_IDX 2 6142#define mmCM3_CM_GAMCOR_LUT_INDEX 0x117f 6143#define mmCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 6144#define mmCM3_CM_GAMCOR_LUT_DATA 0x1180 6145#define mmCM3_CM_GAMCOR_LUT_DATA_BASE_IDX 2 6146#define mmCM3_CM_GAMCOR_LUT_CONTROL 0x1181 6147#define mmCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 6148#define mmCM3_CM_GAMCOR_RAMA_START_CNTL_B 0x1182 6149#define mmCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 6150#define mmCM3_CM_GAMCOR_RAMA_START_CNTL_G 0x1183 6151#define mmCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 6152#define mmCM3_CM_GAMCOR_RAMA_START_CNTL_R 0x1184 6153#define mmCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 6154#define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x1185 6155#define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 6156#define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x1186 6157#define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 6158#define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x1187 6159#define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 6160#define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x1188 6161#define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 6162#define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x1189 6163#define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 6164#define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x118a 6165#define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 6166#define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_B 0x118b 6167#define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 6168#define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_B 0x118c 6169#define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 6170#define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_G 0x118d 6171#define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 6172#define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_G 0x118e 6173#define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 6174#define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_R 0x118f 6175#define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 6176#define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_R 0x1190 6177#define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 6178#define mmCM3_CM_GAMCOR_RAMA_OFFSET_B 0x1191 6179#define mmCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 6180#define mmCM3_CM_GAMCOR_RAMA_OFFSET_G 0x1192 6181#define mmCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 6182#define mmCM3_CM_GAMCOR_RAMA_OFFSET_R 0x1193 6183#define mmCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 6184#define mmCM3_CM_GAMCOR_RAMA_REGION_0_1 0x1194 6185#define mmCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 6186#define mmCM3_CM_GAMCOR_RAMA_REGION_2_3 0x1195 6187#define mmCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 6188#define mmCM3_CM_GAMCOR_RAMA_REGION_4_5 0x1196 6189#define mmCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 6190#define mmCM3_CM_GAMCOR_RAMA_REGION_6_7 0x1197 6191#define mmCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 6192#define mmCM3_CM_GAMCOR_RAMA_REGION_8_9 0x1198 6193#define mmCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 6194#define mmCM3_CM_GAMCOR_RAMA_REGION_10_11 0x1199 6195#define mmCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 6196#define mmCM3_CM_GAMCOR_RAMA_REGION_12_13 0x119a 6197#define mmCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 6198#define mmCM3_CM_GAMCOR_RAMA_REGION_14_15 0x119b 6199#define mmCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 6200#define mmCM3_CM_GAMCOR_RAMA_REGION_16_17 0x119c 6201#define mmCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 6202#define mmCM3_CM_GAMCOR_RAMA_REGION_18_19 0x119d 6203#define mmCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 6204#define mmCM3_CM_GAMCOR_RAMA_REGION_20_21 0x119e 6205#define mmCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 6206#define mmCM3_CM_GAMCOR_RAMA_REGION_22_23 0x119f 6207#define mmCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 6208#define mmCM3_CM_GAMCOR_RAMA_REGION_24_25 0x11a0 6209#define mmCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 6210#define mmCM3_CM_GAMCOR_RAMA_REGION_26_27 0x11a1 6211#define mmCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 6212#define mmCM3_CM_GAMCOR_RAMA_REGION_28_29 0x11a2 6213#define mmCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 6214#define mmCM3_CM_GAMCOR_RAMA_REGION_30_31 0x11a3 6215#define mmCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 6216#define mmCM3_CM_GAMCOR_RAMA_REGION_32_33 0x11a4 6217#define mmCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 6218#define mmCM3_CM_GAMCOR_RAMB_START_CNTL_B 0x11a5 6219#define mmCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 6220#define mmCM3_CM_GAMCOR_RAMB_START_CNTL_G 0x11a6 6221#define mmCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 6222#define mmCM3_CM_GAMCOR_RAMB_START_CNTL_R 0x11a7 6223#define mmCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 6224#define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x11a8 6225#define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 6226#define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x11a9 6227#define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 6228#define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x11aa 6229#define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 6230#define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x11ab 6231#define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 6232#define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x11ac 6233#define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 6234#define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x11ad 6235#define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 6236#define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_B 0x11ae 6237#define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 6238#define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_B 0x11af 6239#define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 6240#define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_G 0x11b0 6241#define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 6242#define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_G 0x11b1 6243#define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 6244#define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_R 0x11b2 6245#define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 6246#define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_R 0x11b3 6247#define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 6248#define mmCM3_CM_GAMCOR_RAMB_OFFSET_B 0x11b4 6249#define mmCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 6250#define mmCM3_CM_GAMCOR_RAMB_OFFSET_G 0x11b5 6251#define mmCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 6252#define mmCM3_CM_GAMCOR_RAMB_OFFSET_R 0x11b6 6253#define mmCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 6254#define mmCM3_CM_GAMCOR_RAMB_REGION_0_1 0x11b7 6255#define mmCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 6256#define mmCM3_CM_GAMCOR_RAMB_REGION_2_3 0x11b8 6257#define mmCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 6258#define mmCM3_CM_GAMCOR_RAMB_REGION_4_5 0x11b9 6259#define mmCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 6260#define mmCM3_CM_GAMCOR_RAMB_REGION_6_7 0x11ba 6261#define mmCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 6262#define mmCM3_CM_GAMCOR_RAMB_REGION_8_9 0x11bb 6263#define mmCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 6264#define mmCM3_CM_GAMCOR_RAMB_REGION_10_11 0x11bc 6265#define mmCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 6266#define mmCM3_CM_GAMCOR_RAMB_REGION_12_13 0x11bd 6267#define mmCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 6268#define mmCM3_CM_GAMCOR_RAMB_REGION_14_15 0x11be 6269#define mmCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 6270#define mmCM3_CM_GAMCOR_RAMB_REGION_16_17 0x11bf 6271#define mmCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 6272#define mmCM3_CM_GAMCOR_RAMB_REGION_18_19 0x11c0 6273#define mmCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 6274#define mmCM3_CM_GAMCOR_RAMB_REGION_20_21 0x11c1 6275#define mmCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 6276#define mmCM3_CM_GAMCOR_RAMB_REGION_22_23 0x11c2 6277#define mmCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 6278#define mmCM3_CM_GAMCOR_RAMB_REGION_24_25 0x11c3 6279#define mmCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 6280#define mmCM3_CM_GAMCOR_RAMB_REGION_26_27 0x11c4 6281#define mmCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 6282#define mmCM3_CM_GAMCOR_RAMB_REGION_28_29 0x11c5 6283#define mmCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 6284#define mmCM3_CM_GAMCOR_RAMB_REGION_30_31 0x11c6 6285#define mmCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 6286#define mmCM3_CM_GAMCOR_RAMB_REGION_32_33 0x11c7 6287#define mmCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 6288#define mmCM3_CM_BLNDGAM_CONTROL 0x11c8 6289#define mmCM3_CM_BLNDGAM_CONTROL_BASE_IDX 2 6290#define mmCM3_CM_BLNDGAM_LUT_INDEX 0x11c9 6291#define mmCM3_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 6292#define mmCM3_CM_BLNDGAM_LUT_DATA 0x11ca 6293#define mmCM3_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 6294#define mmCM3_CM_BLNDGAM_LUT_CONTROL 0x11cb 6295#define mmCM3_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 6296#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B 0x11cc 6297#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 6298#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G 0x11cd 6299#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 6300#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R 0x11ce 6301#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 6302#define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x11cf 6303#define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 6304#define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x11d0 6305#define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 6306#define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x11d1 6307#define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 6308#define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x11d2 6309#define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 6310#define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x11d3 6311#define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 6312#define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x11d4 6313#define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 6314#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B 0x11d5 6315#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 6316#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B 0x11d6 6317#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 6318#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G 0x11d7 6319#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 6320#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G 0x11d8 6321#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 6322#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R 0x11d9 6323#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 6324#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R 0x11da 6325#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 6326#define mmCM3_CM_BLNDGAM_RAMA_OFFSET_B 0x11db 6327#define mmCM3_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 6328#define mmCM3_CM_BLNDGAM_RAMA_OFFSET_G 0x11dc 6329#define mmCM3_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 6330#define mmCM3_CM_BLNDGAM_RAMA_OFFSET_R 0x11dd 6331#define mmCM3_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 6332#define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1 0x11de 6333#define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 6334#define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3 0x11df 6335#define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 6336#define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5 0x11e0 6337#define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 6338#define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7 0x11e1 6339#define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 6340#define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9 0x11e2 6341#define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 6342#define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11 0x11e3 6343#define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 6344#define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13 0x11e4 6345#define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 6346#define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15 0x11e5 6347#define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 6348#define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17 0x11e6 6349#define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 6350#define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19 0x11e7 6351#define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 6352#define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21 0x11e8 6353#define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 6354#define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23 0x11e9 6355#define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 6356#define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25 0x11ea 6357#define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 6358#define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27 0x11eb 6359#define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 6360#define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29 0x11ec 6361#define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 6362#define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31 0x11ed 6363#define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 6364#define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33 0x11ee 6365#define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 6366#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B 0x11ef 6367#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 6368#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G 0x11f0 6369#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 6370#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R 0x11f1 6371#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 6372#define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x11f2 6373#define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 6374#define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x11f3 6375#define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 6376#define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x11f4 6377#define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 6378#define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x11f5 6379#define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 6380#define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x11f6 6381#define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 6382#define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x11f7 6383#define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 6384#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B 0x11f8 6385#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 6386#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B 0x11f9 6387#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 6388#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G 0x11fa 6389#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 6390#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G 0x11fb 6391#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 6392#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R 0x11fc 6393#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 6394#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R 0x11fd 6395#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 6396#define mmCM3_CM_BLNDGAM_RAMB_OFFSET_B 0x11fe 6397#define mmCM3_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 6398#define mmCM3_CM_BLNDGAM_RAMB_OFFSET_G 0x11ff 6399#define mmCM3_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 6400#define mmCM3_CM_BLNDGAM_RAMB_OFFSET_R 0x1200 6401#define mmCM3_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 6402#define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1 0x1201 6403#define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 6404#define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3 0x1202 6405#define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 6406#define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5 0x1203 6407#define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 6408#define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7 0x1204 6409#define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 6410#define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9 0x1205 6411#define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 6412#define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11 0x1206 6413#define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 6414#define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13 0x1207 6415#define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 6416#define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15 0x1208 6417#define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 6418#define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17 0x1209 6419#define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 6420#define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19 0x120a 6421#define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 6422#define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21 0x120b 6423#define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 6424#define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23 0x120c 6425#define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 6426#define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25 0x120d 6427#define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 6428#define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27 0x120e 6429#define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 6430#define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29 0x120f 6431#define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 6432#define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31 0x1210 6433#define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 6434#define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33 0x1211 6435#define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 6436#define mmCM3_CM_HDR_MULT_COEF 0x1212 6437#define mmCM3_CM_HDR_MULT_COEF_BASE_IDX 2 6438#define mmCM3_CM_MEM_PWR_CTRL 0x1213 6439#define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX 2 6440#define mmCM3_CM_MEM_PWR_STATUS 0x1214 6441#define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX 2 6442#define mmCM3_CM_DEALPHA 0x1216 6443#define mmCM3_CM_DEALPHA_BASE_IDX 2 6444#define mmCM3_CM_COEF_FORMAT 0x1217 6445#define mmCM3_CM_COEF_FORMAT_BASE_IDX 2 6446#define mmCM3_CM_SHAPER_CONTROL 0x1218 6447#define mmCM3_CM_SHAPER_CONTROL_BASE_IDX 2 6448#define mmCM3_CM_SHAPER_OFFSET_R 0x1219 6449#define mmCM3_CM_SHAPER_OFFSET_R_BASE_IDX 2 6450#define mmCM3_CM_SHAPER_OFFSET_G 0x121a 6451#define mmCM3_CM_SHAPER_OFFSET_G_BASE_IDX 2 6452#define mmCM3_CM_SHAPER_OFFSET_B 0x121b 6453#define mmCM3_CM_SHAPER_OFFSET_B_BASE_IDX 2 6454#define mmCM3_CM_SHAPER_SCALE_R 0x121c 6455#define mmCM3_CM_SHAPER_SCALE_R_BASE_IDX 2 6456#define mmCM3_CM_SHAPER_SCALE_G_B 0x121d 6457#define mmCM3_CM_SHAPER_SCALE_G_B_BASE_IDX 2 6458#define mmCM3_CM_SHAPER_LUT_INDEX 0x121e 6459#define mmCM3_CM_SHAPER_LUT_INDEX_BASE_IDX 2 6460#define mmCM3_CM_SHAPER_LUT_DATA 0x121f 6461#define mmCM3_CM_SHAPER_LUT_DATA_BASE_IDX 2 6462#define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK 0x1220 6463#define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 6464#define mmCM3_CM_SHAPER_RAMA_START_CNTL_B 0x1221 6465#define mmCM3_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 6466#define mmCM3_CM_SHAPER_RAMA_START_CNTL_G 0x1222 6467#define mmCM3_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 6468#define mmCM3_CM_SHAPER_RAMA_START_CNTL_R 0x1223 6469#define mmCM3_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 6470#define mmCM3_CM_SHAPER_RAMA_END_CNTL_B 0x1224 6471#define mmCM3_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 6472#define mmCM3_CM_SHAPER_RAMA_END_CNTL_G 0x1225 6473#define mmCM3_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 6474#define mmCM3_CM_SHAPER_RAMA_END_CNTL_R 0x1226 6475#define mmCM3_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 6476#define mmCM3_CM_SHAPER_RAMA_REGION_0_1 0x1227 6477#define mmCM3_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 6478#define mmCM3_CM_SHAPER_RAMA_REGION_2_3 0x1228 6479#define mmCM3_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 6480#define mmCM3_CM_SHAPER_RAMA_REGION_4_5 0x1229 6481#define mmCM3_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 6482#define mmCM3_CM_SHAPER_RAMA_REGION_6_7 0x122a 6483#define mmCM3_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 6484#define mmCM3_CM_SHAPER_RAMA_REGION_8_9 0x122b 6485#define mmCM3_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 6486#define mmCM3_CM_SHAPER_RAMA_REGION_10_11 0x122c 6487#define mmCM3_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 6488#define mmCM3_CM_SHAPER_RAMA_REGION_12_13 0x122d 6489#define mmCM3_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 6490#define mmCM3_CM_SHAPER_RAMA_REGION_14_15 0x122e 6491#define mmCM3_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 6492#define mmCM3_CM_SHAPER_RAMA_REGION_16_17 0x122f 6493#define mmCM3_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 6494#define mmCM3_CM_SHAPER_RAMA_REGION_18_19 0x1230 6495#define mmCM3_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 6496#define mmCM3_CM_SHAPER_RAMA_REGION_20_21 0x1231 6497#define mmCM3_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 6498#define mmCM3_CM_SHAPER_RAMA_REGION_22_23 0x1232 6499#define mmCM3_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 6500#define mmCM3_CM_SHAPER_RAMA_REGION_24_25 0x1233 6501#define mmCM3_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 6502#define mmCM3_CM_SHAPER_RAMA_REGION_26_27 0x1234 6503#define mmCM3_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 6504#define mmCM3_CM_SHAPER_RAMA_REGION_28_29 0x1235 6505#define mmCM3_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 6506#define mmCM3_CM_SHAPER_RAMA_REGION_30_31 0x1236 6507#define mmCM3_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 6508#define mmCM3_CM_SHAPER_RAMA_REGION_32_33 0x1237 6509#define mmCM3_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 6510#define mmCM3_CM_SHAPER_RAMB_START_CNTL_B 0x1238 6511#define mmCM3_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 6512#define mmCM3_CM_SHAPER_RAMB_START_CNTL_G 0x1239 6513#define mmCM3_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 6514#define mmCM3_CM_SHAPER_RAMB_START_CNTL_R 0x123a 6515#define mmCM3_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 6516#define mmCM3_CM_SHAPER_RAMB_END_CNTL_B 0x123b 6517#define mmCM3_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 6518#define mmCM3_CM_SHAPER_RAMB_END_CNTL_G 0x123c 6519#define mmCM3_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 6520#define mmCM3_CM_SHAPER_RAMB_END_CNTL_R 0x123d 6521#define mmCM3_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 6522#define mmCM3_CM_SHAPER_RAMB_REGION_0_1 0x123e 6523#define mmCM3_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 6524#define mmCM3_CM_SHAPER_RAMB_REGION_2_3 0x123f 6525#define mmCM3_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 6526#define mmCM3_CM_SHAPER_RAMB_REGION_4_5 0x1240 6527#define mmCM3_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 6528#define mmCM3_CM_SHAPER_RAMB_REGION_6_7 0x1241 6529#define mmCM3_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 6530#define mmCM3_CM_SHAPER_RAMB_REGION_8_9 0x1242 6531#define mmCM3_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 6532#define mmCM3_CM_SHAPER_RAMB_REGION_10_11 0x1243 6533#define mmCM3_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 6534#define mmCM3_CM_SHAPER_RAMB_REGION_12_13 0x1244 6535#define mmCM3_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 6536#define mmCM3_CM_SHAPER_RAMB_REGION_14_15 0x1245 6537#define mmCM3_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 6538#define mmCM3_CM_SHAPER_RAMB_REGION_16_17 0x1246 6539#define mmCM3_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 6540#define mmCM3_CM_SHAPER_RAMB_REGION_18_19 0x1247 6541#define mmCM3_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 6542#define mmCM3_CM_SHAPER_RAMB_REGION_20_21 0x1248 6543#define mmCM3_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 6544#define mmCM3_CM_SHAPER_RAMB_REGION_22_23 0x1249 6545#define mmCM3_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 6546#define mmCM3_CM_SHAPER_RAMB_REGION_24_25 0x124a 6547#define mmCM3_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 6548#define mmCM3_CM_SHAPER_RAMB_REGION_26_27 0x124b 6549#define mmCM3_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 6550#define mmCM3_CM_SHAPER_RAMB_REGION_28_29 0x124c 6551#define mmCM3_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 6552#define mmCM3_CM_SHAPER_RAMB_REGION_30_31 0x124d 6553#define mmCM3_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 6554#define mmCM3_CM_SHAPER_RAMB_REGION_32_33 0x124e 6555#define mmCM3_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 6556#define mmCM3_CM_MEM_PWR_CTRL2 0x124f 6557#define mmCM3_CM_MEM_PWR_CTRL2_BASE_IDX 2 6558#define mmCM3_CM_MEM_PWR_STATUS2 0x1250 6559#define mmCM3_CM_MEM_PWR_STATUS2_BASE_IDX 2 6560#define mmCM3_CM_3DLUT_MODE 0x1251 6561#define mmCM3_CM_3DLUT_MODE_BASE_IDX 2 6562#define mmCM3_CM_3DLUT_INDEX 0x1252 6563#define mmCM3_CM_3DLUT_INDEX_BASE_IDX 2 6564#define mmCM3_CM_3DLUT_DATA 0x1253 6565#define mmCM3_CM_3DLUT_DATA_BASE_IDX 2 6566#define mmCM3_CM_3DLUT_DATA_30BIT 0x1254 6567#define mmCM3_CM_3DLUT_DATA_30BIT_BASE_IDX 2 6568#define mmCM3_CM_3DLUT_READ_WRITE_CONTROL 0x1255 6569#define mmCM3_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 6570#define mmCM3_CM_3DLUT_OUT_NORM_FACTOR 0x1256 6571#define mmCM3_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 6572#define mmCM3_CM_3DLUT_OUT_OFFSET_R 0x1257 6573#define mmCM3_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 6574#define mmCM3_CM_3DLUT_OUT_OFFSET_G 0x1258 6575#define mmCM3_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 6576#define mmCM3_CM_3DLUT_OUT_OFFSET_B 0x1259 6577#define mmCM3_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 6578 6579 6580// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 6581// base address: 0x4994 6582#define mmDC_PERFMON15_PERFCOUNTER_CNTL 0x1265 6583#define mmDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX 2 6584#define mmDC_PERFMON15_PERFCOUNTER_CNTL2 0x1266 6585#define mmDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX 2 6586#define mmDC_PERFMON15_PERFCOUNTER_STATE 0x1267 6587#define mmDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX 2 6588#define mmDC_PERFMON15_PERFMON_CNTL 0x1268 6589#define mmDC_PERFMON15_PERFMON_CNTL_BASE_IDX 2 6590#define mmDC_PERFMON15_PERFMON_CNTL2 0x1269 6591#define mmDC_PERFMON15_PERFMON_CNTL2_BASE_IDX 2 6592#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC 0x126a 6593#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 6594#define mmDC_PERFMON15_PERFMON_CVALUE_LOW 0x126b 6595#define mmDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX 2 6596#define mmDC_PERFMON15_PERFMON_HI 0x126c 6597#define mmDC_PERFMON15_PERFMON_HI_BASE_IDX 2 6598#define mmDC_PERFMON15_PERFMON_LOW 0x126d 6599#define mmDC_PERFMON15_PERFMON_LOW_BASE_IDX 2 6600 6601 6602// addressBlock: dce_dc_dpp4_dispdec_dpp_top_dispdec 6603// base address: 0x16b0 6604#define mmDPP_TOP4_DPP_CONTROL 0x1271 6605#define mmDPP_TOP4_DPP_CONTROL_BASE_IDX 2 6606#define mmDPP_TOP4_DPP_SOFT_RESET 0x1272 6607#define mmDPP_TOP4_DPP_SOFT_RESET_BASE_IDX 2 6608#define mmDPP_TOP4_DPP_CRC_VAL_R_G 0x1273 6609#define mmDPP_TOP4_DPP_CRC_VAL_R_G_BASE_IDX 2 6610#define mmDPP_TOP4_DPP_CRC_VAL_B_A 0x1274 6611#define mmDPP_TOP4_DPP_CRC_VAL_B_A_BASE_IDX 2 6612#define mmDPP_TOP4_DPP_CRC_CTRL 0x1275 6613#define mmDPP_TOP4_DPP_CRC_CTRL_BASE_IDX 2 6614#define mmDPP_TOP4_HOST_READ_CONTROL 0x1276 6615#define mmDPP_TOP4_HOST_READ_CONTROL_BASE_IDX 2 6616 6617 6618// addressBlock: dce_dc_dpp4_dispdec_cnvc_cfg_dispdec 6619// base address: 0x16b0 6620#define mmCNVC_CFG4_CNVC_SURFACE_PIXEL_FORMAT 0x127b 6621#define mmCNVC_CFG4_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 6622#define mmCNVC_CFG4_FORMAT_CONTROL 0x127c 6623#define mmCNVC_CFG4_FORMAT_CONTROL_BASE_IDX 2 6624#define mmCNVC_CFG4_FCNV_FP_BIAS_R 0x127d 6625#define mmCNVC_CFG4_FCNV_FP_BIAS_R_BASE_IDX 2 6626#define mmCNVC_CFG4_FCNV_FP_BIAS_G 0x127e 6627#define mmCNVC_CFG4_FCNV_FP_BIAS_G_BASE_IDX 2 6628#define mmCNVC_CFG4_FCNV_FP_BIAS_B 0x127f 6629#define mmCNVC_CFG4_FCNV_FP_BIAS_B_BASE_IDX 2 6630#define mmCNVC_CFG4_FCNV_FP_SCALE_R 0x1280 6631#define mmCNVC_CFG4_FCNV_FP_SCALE_R_BASE_IDX 2 6632#define mmCNVC_CFG4_FCNV_FP_SCALE_G 0x1281 6633#define mmCNVC_CFG4_FCNV_FP_SCALE_G_BASE_IDX 2 6634#define mmCNVC_CFG4_FCNV_FP_SCALE_B 0x1282 6635#define mmCNVC_CFG4_FCNV_FP_SCALE_B_BASE_IDX 2 6636#define mmCNVC_CFG4_COLOR_KEYER_CONTROL 0x1283 6637#define mmCNVC_CFG4_COLOR_KEYER_CONTROL_BASE_IDX 2 6638#define mmCNVC_CFG4_COLOR_KEYER_ALPHA 0x1284 6639#define mmCNVC_CFG4_COLOR_KEYER_ALPHA_BASE_IDX 2 6640#define mmCNVC_CFG4_COLOR_KEYER_RED 0x1285 6641#define mmCNVC_CFG4_COLOR_KEYER_RED_BASE_IDX 2 6642#define mmCNVC_CFG4_COLOR_KEYER_GREEN 0x1286 6643#define mmCNVC_CFG4_COLOR_KEYER_GREEN_BASE_IDX 2 6644#define mmCNVC_CFG4_COLOR_KEYER_BLUE 0x1287 6645#define mmCNVC_CFG4_COLOR_KEYER_BLUE_BASE_IDX 2 6646#define mmCNVC_CFG4_ALPHA_2BIT_LUT 0x1289 6647#define mmCNVC_CFG4_ALPHA_2BIT_LUT_BASE_IDX 2 6648#define mmCNVC_CFG4_PRE_DEALPHA 0x128a 6649#define mmCNVC_CFG4_PRE_DEALPHA_BASE_IDX 2 6650#define mmCNVC_CFG4_PRE_CSC_MODE 0x128b 6651#define mmCNVC_CFG4_PRE_CSC_MODE_BASE_IDX 2 6652#define mmCNVC_CFG4_PRE_CSC_C11_C12 0x128c 6653#define mmCNVC_CFG4_PRE_CSC_C11_C12_BASE_IDX 2 6654#define mmCNVC_CFG4_PRE_CSC_C13_C14 0x128d 6655#define mmCNVC_CFG4_PRE_CSC_C13_C14_BASE_IDX 2 6656#define mmCNVC_CFG4_PRE_CSC_C21_C22 0x128e 6657#define mmCNVC_CFG4_PRE_CSC_C21_C22_BASE_IDX 2 6658#define mmCNVC_CFG4_PRE_CSC_C23_C24 0x128f 6659#define mmCNVC_CFG4_PRE_CSC_C23_C24_BASE_IDX 2 6660#define mmCNVC_CFG4_PRE_CSC_C31_C32 0x1290 6661#define mmCNVC_CFG4_PRE_CSC_C31_C32_BASE_IDX 2 6662#define mmCNVC_CFG4_PRE_CSC_C33_C34 0x1291 6663#define mmCNVC_CFG4_PRE_CSC_C33_C34_BASE_IDX 2 6664#define mmCNVC_CFG4_PRE_CSC_B_C11_C12 0x1292 6665#define mmCNVC_CFG4_PRE_CSC_B_C11_C12_BASE_IDX 2 6666#define mmCNVC_CFG4_PRE_CSC_B_C13_C14 0x1293 6667#define mmCNVC_CFG4_PRE_CSC_B_C13_C14_BASE_IDX 2 6668#define mmCNVC_CFG4_PRE_CSC_B_C21_C22 0x1294 6669#define mmCNVC_CFG4_PRE_CSC_B_C21_C22_BASE_IDX 2 6670#define mmCNVC_CFG4_PRE_CSC_B_C23_C24 0x1295 6671#define mmCNVC_CFG4_PRE_CSC_B_C23_C24_BASE_IDX 2 6672#define mmCNVC_CFG4_PRE_CSC_B_C31_C32 0x1296 6673#define mmCNVC_CFG4_PRE_CSC_B_C31_C32_BASE_IDX 2 6674#define mmCNVC_CFG4_PRE_CSC_B_C33_C34 0x1297 6675#define mmCNVC_CFG4_PRE_CSC_B_C33_C34_BASE_IDX 2 6676#define mmCNVC_CFG4_CNVC_COEF_FORMAT 0x1298 6677#define mmCNVC_CFG4_CNVC_COEF_FORMAT_BASE_IDX 2 6678#define mmCNVC_CFG4_PRE_DEGAM 0x1299 6679#define mmCNVC_CFG4_PRE_DEGAM_BASE_IDX 2 6680#define mmCNVC_CFG4_PRE_REALPHA 0x129a 6681#define mmCNVC_CFG4_PRE_REALPHA_BASE_IDX 2 6682 6683 6684// addressBlock: dce_dc_dpp4_dispdec_cnvc_cur_dispdec 6685// base address: 0x16b0 6686#define mmCNVC_CUR4_CURSOR0_CONTROL 0x129d 6687#define mmCNVC_CUR4_CURSOR0_CONTROL_BASE_IDX 2 6688#define mmCNVC_CUR4_CURSOR0_COLOR0 0x129e 6689#define mmCNVC_CUR4_CURSOR0_COLOR0_BASE_IDX 2 6690#define mmCNVC_CUR4_CURSOR0_COLOR1 0x129f 6691#define mmCNVC_CUR4_CURSOR0_COLOR1_BASE_IDX 2 6692#define mmCNVC_CUR4_CURSOR0_FP_SCALE_BIAS 0x12a0 6693#define mmCNVC_CUR4_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 6694 6695 6696// addressBlock: dce_dc_dpp4_dispdec_dscl_dispdec 6697// base address: 0x16b0 6698#define mmDSCL4_SCL_COEF_RAM_TAP_SELECT 0x12a5 6699#define mmDSCL4_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 6700#define mmDSCL4_SCL_COEF_RAM_TAP_DATA 0x12a6 6701#define mmDSCL4_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 6702#define mmDSCL4_SCL_MODE 0x12a7 6703#define mmDSCL4_SCL_MODE_BASE_IDX 2 6704#define mmDSCL4_SCL_TAP_CONTROL 0x12a8 6705#define mmDSCL4_SCL_TAP_CONTROL_BASE_IDX 2 6706#define mmDSCL4_DSCL_CONTROL 0x12a9 6707#define mmDSCL4_DSCL_CONTROL_BASE_IDX 2 6708#define mmDSCL4_DSCL_2TAP_CONTROL 0x12aa 6709#define mmDSCL4_DSCL_2TAP_CONTROL_BASE_IDX 2 6710#define mmDSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x12ab 6711#define mmDSCL4_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 6712#define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x12ac 6713#define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 6714#define mmDSCL4_SCL_HORZ_FILTER_INIT 0x12ad 6715#define mmDSCL4_SCL_HORZ_FILTER_INIT_BASE_IDX 2 6716#define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO_C 0x12ae 6717#define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 6718#define mmDSCL4_SCL_HORZ_FILTER_INIT_C 0x12af 6719#define mmDSCL4_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 6720#define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x12b0 6721#define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 6722#define mmDSCL4_SCL_VERT_FILTER_INIT 0x12b1 6723#define mmDSCL4_SCL_VERT_FILTER_INIT_BASE_IDX 2 6724#define mmDSCL4_SCL_VERT_FILTER_INIT_BOT 0x12b2 6725#define mmDSCL4_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 6726#define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO_C 0x12b3 6727#define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 6728#define mmDSCL4_SCL_VERT_FILTER_INIT_C 0x12b4 6729#define mmDSCL4_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 6730#define mmDSCL4_SCL_VERT_FILTER_INIT_BOT_C 0x12b5 6731#define mmDSCL4_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 6732#define mmDSCL4_SCL_BLACK_COLOR 0x12b6 6733#define mmDSCL4_SCL_BLACK_COLOR_BASE_IDX 2 6734#define mmDSCL4_DSCL_UPDATE 0x12b7 6735#define mmDSCL4_DSCL_UPDATE_BASE_IDX 2 6736#define mmDSCL4_DSCL_AUTOCAL 0x12b8 6737#define mmDSCL4_DSCL_AUTOCAL_BASE_IDX 2 6738#define mmDSCL4_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x12b9 6739#define mmDSCL4_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 6740#define mmDSCL4_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x12ba 6741#define mmDSCL4_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 6742#define mmDSCL4_OTG_H_BLANK 0x12bb 6743#define mmDSCL4_OTG_H_BLANK_BASE_IDX 2 6744#define mmDSCL4_OTG_V_BLANK 0x12bc 6745#define mmDSCL4_OTG_V_BLANK_BASE_IDX 2 6746#define mmDSCL4_RECOUT_START 0x12bd 6747#define mmDSCL4_RECOUT_START_BASE_IDX 2 6748#define mmDSCL4_RECOUT_SIZE 0x12be 6749#define mmDSCL4_RECOUT_SIZE_BASE_IDX 2 6750#define mmDSCL4_MPC_SIZE 0x12bf 6751#define mmDSCL4_MPC_SIZE_BASE_IDX 2 6752#define mmDSCL4_LB_DATA_FORMAT 0x12c0 6753#define mmDSCL4_LB_DATA_FORMAT_BASE_IDX 2 6754#define mmDSCL4_LB_MEMORY_CTRL 0x12c1 6755#define mmDSCL4_LB_MEMORY_CTRL_BASE_IDX 2 6756#define mmDSCL4_LB_V_COUNTER 0x12c2 6757#define mmDSCL4_LB_V_COUNTER_BASE_IDX 2 6758#define mmDSCL4_DSCL_MEM_PWR_CTRL 0x12c3 6759#define mmDSCL4_DSCL_MEM_PWR_CTRL_BASE_IDX 2 6760#define mmDSCL4_DSCL_MEM_PWR_STATUS 0x12c4 6761#define mmDSCL4_DSCL_MEM_PWR_STATUS_BASE_IDX 2 6762#define mmDSCL4_OBUF_CONTROL 0x12c5 6763#define mmDSCL4_OBUF_CONTROL_BASE_IDX 2 6764#define mmDSCL4_OBUF_MEM_PWR_CTRL 0x12c6 6765#define mmDSCL4_OBUF_MEM_PWR_CTRL_BASE_IDX 2 6766 6767 6768// addressBlock: dce_dc_dpp4_dispdec_cm_dispdec 6769// base address: 0x16b0 6770#define mmCM4_CM_CONTROL 0x12cc 6771#define mmCM4_CM_CONTROL_BASE_IDX 2 6772#define mmCM4_CM_POST_CSC_CONTROL 0x12cd 6773#define mmCM4_CM_POST_CSC_CONTROL_BASE_IDX 2 6774#define mmCM4_CM_POST_CSC_C11_C12 0x12ce 6775#define mmCM4_CM_POST_CSC_C11_C12_BASE_IDX 2 6776#define mmCM4_CM_POST_CSC_C13_C14 0x12cf 6777#define mmCM4_CM_POST_CSC_C13_C14_BASE_IDX 2 6778#define mmCM4_CM_POST_CSC_C21_C22 0x12d0 6779#define mmCM4_CM_POST_CSC_C21_C22_BASE_IDX 2 6780#define mmCM4_CM_POST_CSC_C23_C24 0x12d1 6781#define mmCM4_CM_POST_CSC_C23_C24_BASE_IDX 2 6782#define mmCM4_CM_POST_CSC_C31_C32 0x12d2 6783#define mmCM4_CM_POST_CSC_C31_C32_BASE_IDX 2 6784#define mmCM4_CM_POST_CSC_C33_C34 0x12d3 6785#define mmCM4_CM_POST_CSC_C33_C34_BASE_IDX 2 6786#define mmCM4_CM_POST_CSC_B_C11_C12 0x12d4 6787#define mmCM4_CM_POST_CSC_B_C11_C12_BASE_IDX 2 6788#define mmCM4_CM_POST_CSC_B_C13_C14 0x12d5 6789#define mmCM4_CM_POST_CSC_B_C13_C14_BASE_IDX 2 6790#define mmCM4_CM_POST_CSC_B_C21_C22 0x12d6 6791#define mmCM4_CM_POST_CSC_B_C21_C22_BASE_IDX 2 6792#define mmCM4_CM_POST_CSC_B_C23_C24 0x12d7 6793#define mmCM4_CM_POST_CSC_B_C23_C24_BASE_IDX 2 6794#define mmCM4_CM_POST_CSC_B_C31_C32 0x12d8 6795#define mmCM4_CM_POST_CSC_B_C31_C32_BASE_IDX 2 6796#define mmCM4_CM_POST_CSC_B_C33_C34 0x12d9 6797#define mmCM4_CM_POST_CSC_B_C33_C34_BASE_IDX 2 6798#define mmCM4_CM_GAMUT_REMAP_CONTROL 0x12da 6799#define mmCM4_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 6800#define mmCM4_CM_GAMUT_REMAP_C11_C12 0x12db 6801#define mmCM4_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 6802#define mmCM4_CM_GAMUT_REMAP_C13_C14 0x12dc 6803#define mmCM4_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 6804#define mmCM4_CM_GAMUT_REMAP_C21_C22 0x12dd 6805#define mmCM4_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 6806#define mmCM4_CM_GAMUT_REMAP_C23_C24 0x12de 6807#define mmCM4_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 6808#define mmCM4_CM_GAMUT_REMAP_C31_C32 0x12df 6809#define mmCM4_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 6810#define mmCM4_CM_GAMUT_REMAP_C33_C34 0x12e0 6811#define mmCM4_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 6812#define mmCM4_CM_GAMUT_REMAP_B_C11_C12 0x12e1 6813#define mmCM4_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 6814#define mmCM4_CM_GAMUT_REMAP_B_C13_C14 0x12e2 6815#define mmCM4_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 6816#define mmCM4_CM_GAMUT_REMAP_B_C21_C22 0x12e3 6817#define mmCM4_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 6818#define mmCM4_CM_GAMUT_REMAP_B_C23_C24 0x12e4 6819#define mmCM4_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 6820#define mmCM4_CM_GAMUT_REMAP_B_C31_C32 0x12e5 6821#define mmCM4_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 6822#define mmCM4_CM_GAMUT_REMAP_B_C33_C34 0x12e6 6823#define mmCM4_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 6824#define mmCM4_CM_BIAS_CR_R 0x12e7 6825#define mmCM4_CM_BIAS_CR_R_BASE_IDX 2 6826#define mmCM4_CM_BIAS_Y_G_CB_B 0x12e8 6827#define mmCM4_CM_BIAS_Y_G_CB_B_BASE_IDX 2 6828#define mmCM4_CM_GAMCOR_CONTROL 0x12e9 6829#define mmCM4_CM_GAMCOR_CONTROL_BASE_IDX 2 6830#define mmCM4_CM_GAMCOR_LUT_INDEX 0x12ea 6831#define mmCM4_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 6832#define mmCM4_CM_GAMCOR_LUT_DATA 0x12eb 6833#define mmCM4_CM_GAMCOR_LUT_DATA_BASE_IDX 2 6834#define mmCM4_CM_GAMCOR_LUT_CONTROL 0x12ec 6835#define mmCM4_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 6836#define mmCM4_CM_GAMCOR_RAMA_START_CNTL_B 0x12ed 6837#define mmCM4_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 6838#define mmCM4_CM_GAMCOR_RAMA_START_CNTL_G 0x12ee 6839#define mmCM4_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 6840#define mmCM4_CM_GAMCOR_RAMA_START_CNTL_R 0x12ef 6841#define mmCM4_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 6842#define mmCM4_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x12f0 6843#define mmCM4_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 6844#define mmCM4_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x12f1 6845#define mmCM4_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 6846#define mmCM4_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x12f2 6847#define mmCM4_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 6848#define mmCM4_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x12f3 6849#define mmCM4_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 6850#define mmCM4_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x12f4 6851#define mmCM4_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 6852#define mmCM4_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x12f5 6853#define mmCM4_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 6854#define mmCM4_CM_GAMCOR_RAMA_END_CNTL1_B 0x12f6 6855#define mmCM4_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 6856#define mmCM4_CM_GAMCOR_RAMA_END_CNTL2_B 0x12f7 6857#define mmCM4_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 6858#define mmCM4_CM_GAMCOR_RAMA_END_CNTL1_G 0x12f8 6859#define mmCM4_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 6860#define mmCM4_CM_GAMCOR_RAMA_END_CNTL2_G 0x12f9 6861#define mmCM4_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 6862#define mmCM4_CM_GAMCOR_RAMA_END_CNTL1_R 0x12fa 6863#define mmCM4_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 6864#define mmCM4_CM_GAMCOR_RAMA_END_CNTL2_R 0x12fb 6865#define mmCM4_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 6866#define mmCM4_CM_GAMCOR_RAMA_OFFSET_B 0x12fc 6867#define mmCM4_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 6868#define mmCM4_CM_GAMCOR_RAMA_OFFSET_G 0x12fd 6869#define mmCM4_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 6870#define mmCM4_CM_GAMCOR_RAMA_OFFSET_R 0x12fe 6871#define mmCM4_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 6872#define mmCM4_CM_GAMCOR_RAMA_REGION_0_1 0x12ff 6873#define mmCM4_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 6874#define mmCM4_CM_GAMCOR_RAMA_REGION_2_3 0x1300 6875#define mmCM4_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 6876#define mmCM4_CM_GAMCOR_RAMA_REGION_4_5 0x1301 6877#define mmCM4_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 6878#define mmCM4_CM_GAMCOR_RAMA_REGION_6_7 0x1302 6879#define mmCM4_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 6880#define mmCM4_CM_GAMCOR_RAMA_REGION_8_9 0x1303 6881#define mmCM4_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 6882#define mmCM4_CM_GAMCOR_RAMA_REGION_10_11 0x1304 6883#define mmCM4_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 6884#define mmCM4_CM_GAMCOR_RAMA_REGION_12_13 0x1305 6885#define mmCM4_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 6886#define mmCM4_CM_GAMCOR_RAMA_REGION_14_15 0x1306 6887#define mmCM4_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 6888#define mmCM4_CM_GAMCOR_RAMA_REGION_16_17 0x1307 6889#define mmCM4_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 6890#define mmCM4_CM_GAMCOR_RAMA_REGION_18_19 0x1308 6891#define mmCM4_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 6892#define mmCM4_CM_GAMCOR_RAMA_REGION_20_21 0x1309 6893#define mmCM4_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 6894#define mmCM4_CM_GAMCOR_RAMA_REGION_22_23 0x130a 6895#define mmCM4_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 6896#define mmCM4_CM_GAMCOR_RAMA_REGION_24_25 0x130b 6897#define mmCM4_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 6898#define mmCM4_CM_GAMCOR_RAMA_REGION_26_27 0x130c 6899#define mmCM4_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 6900#define mmCM4_CM_GAMCOR_RAMA_REGION_28_29 0x130d 6901#define mmCM4_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 6902#define mmCM4_CM_GAMCOR_RAMA_REGION_30_31 0x130e 6903#define mmCM4_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 6904#define mmCM4_CM_GAMCOR_RAMA_REGION_32_33 0x130f 6905#define mmCM4_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 6906#define mmCM4_CM_GAMCOR_RAMB_START_CNTL_B 0x1310 6907#define mmCM4_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 6908#define mmCM4_CM_GAMCOR_RAMB_START_CNTL_G 0x1311 6909#define mmCM4_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 6910#define mmCM4_CM_GAMCOR_RAMB_START_CNTL_R 0x1312 6911#define mmCM4_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 6912#define mmCM4_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x1313 6913#define mmCM4_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 6914#define mmCM4_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x1314 6915#define mmCM4_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 6916#define mmCM4_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x1315 6917#define mmCM4_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 6918#define mmCM4_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x1316 6919#define mmCM4_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 6920#define mmCM4_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x1317 6921#define mmCM4_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 6922#define mmCM4_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x1318 6923#define mmCM4_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 6924#define mmCM4_CM_GAMCOR_RAMB_END_CNTL1_B 0x1319 6925#define mmCM4_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 6926#define mmCM4_CM_GAMCOR_RAMB_END_CNTL2_B 0x131a 6927#define mmCM4_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 6928#define mmCM4_CM_GAMCOR_RAMB_END_CNTL1_G 0x131b 6929#define mmCM4_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 6930#define mmCM4_CM_GAMCOR_RAMB_END_CNTL2_G 0x131c 6931#define mmCM4_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 6932#define mmCM4_CM_GAMCOR_RAMB_END_CNTL1_R 0x131d 6933#define mmCM4_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 6934#define mmCM4_CM_GAMCOR_RAMB_END_CNTL2_R 0x131e 6935#define mmCM4_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 6936#define mmCM4_CM_GAMCOR_RAMB_OFFSET_B 0x131f 6937#define mmCM4_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 6938#define mmCM4_CM_GAMCOR_RAMB_OFFSET_G 0x1320 6939#define mmCM4_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 6940#define mmCM4_CM_GAMCOR_RAMB_OFFSET_R 0x1321 6941#define mmCM4_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 6942#define mmCM4_CM_GAMCOR_RAMB_REGION_0_1 0x1322 6943#define mmCM4_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 6944#define mmCM4_CM_GAMCOR_RAMB_REGION_2_3 0x1323 6945#define mmCM4_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 6946#define mmCM4_CM_GAMCOR_RAMB_REGION_4_5 0x1324 6947#define mmCM4_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 6948#define mmCM4_CM_GAMCOR_RAMB_REGION_6_7 0x1325 6949#define mmCM4_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 6950#define mmCM4_CM_GAMCOR_RAMB_REGION_8_9 0x1326 6951#define mmCM4_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 6952#define mmCM4_CM_GAMCOR_RAMB_REGION_10_11 0x1327 6953#define mmCM4_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 6954#define mmCM4_CM_GAMCOR_RAMB_REGION_12_13 0x1328 6955#define mmCM4_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 6956#define mmCM4_CM_GAMCOR_RAMB_REGION_14_15 0x1329 6957#define mmCM4_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 6958#define mmCM4_CM_GAMCOR_RAMB_REGION_16_17 0x132a 6959#define mmCM4_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 6960#define mmCM4_CM_GAMCOR_RAMB_REGION_18_19 0x132b 6961#define mmCM4_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 6962#define mmCM4_CM_GAMCOR_RAMB_REGION_20_21 0x132c 6963#define mmCM4_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 6964#define mmCM4_CM_GAMCOR_RAMB_REGION_22_23 0x132d 6965#define mmCM4_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 6966#define mmCM4_CM_GAMCOR_RAMB_REGION_24_25 0x132e 6967#define mmCM4_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 6968#define mmCM4_CM_GAMCOR_RAMB_REGION_26_27 0x132f 6969#define mmCM4_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 6970#define mmCM4_CM_GAMCOR_RAMB_REGION_28_29 0x1330 6971#define mmCM4_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 6972#define mmCM4_CM_GAMCOR_RAMB_REGION_30_31 0x1331 6973#define mmCM4_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 6974#define mmCM4_CM_GAMCOR_RAMB_REGION_32_33 0x1332 6975#define mmCM4_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 6976#define mmCM4_CM_BLNDGAM_CONTROL 0x1333 6977#define mmCM4_CM_BLNDGAM_CONTROL_BASE_IDX 2 6978#define mmCM4_CM_BLNDGAM_LUT_INDEX 0x1334 6979#define mmCM4_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 6980#define mmCM4_CM_BLNDGAM_LUT_DATA 0x1335 6981#define mmCM4_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 6982#define mmCM4_CM_BLNDGAM_LUT_CONTROL 0x1336 6983#define mmCM4_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 6984#define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_B 0x1337 6985#define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 6986#define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_G 0x1338 6987#define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 6988#define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_R 0x1339 6989#define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 6990#define mmCM4_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x133a 6991#define mmCM4_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 6992#define mmCM4_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x133b 6993#define mmCM4_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 6994#define mmCM4_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x133c 6995#define mmCM4_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 6996#define mmCM4_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x133d 6997#define mmCM4_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 6998#define mmCM4_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x133e 6999#define mmCM4_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 7000#define mmCM4_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x133f
7001#define mmCM4_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 7002#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_B 0x1340 7003#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 7004#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_B 0x1341 7005#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 7006#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_G 0x1342 7007#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 7008#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_G 0x1343 7009#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 7010#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_R 0x1344 7011#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 7012#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_R 0x1345 7013#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 7014#define mmCM4_CM_BLNDGAM_RAMA_OFFSET_B 0x1346 7015#define mmCM4_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 7016#define mmCM4_CM_BLNDGAM_RAMA_OFFSET_G 0x1347 7017#define mmCM4_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 7018#define mmCM4_CM_BLNDGAM_RAMA_OFFSET_R 0x1348 7019#define mmCM4_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 7020#define mmCM4_CM_BLNDGAM_RAMA_REGION_0_1 0x1349 7021#define mmCM4_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 7022#define mmCM4_CM_BLNDGAM_RAMA_REGION_2_3 0x134a 7023#define mmCM4_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 7024#define mmCM4_CM_BLNDGAM_RAMA_REGION_4_5 0x134b 7025#define mmCM4_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 7026#define mmCM4_CM_BLNDGAM_RAMA_REGION_6_7 0x134c 7027#define mmCM4_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 7028#define mmCM4_CM_BLNDGAM_RAMA_REGION_8_9 0x134d 7029#define mmCM4_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 7030#define mmCM4_CM_BLNDGAM_RAMA_REGION_10_11 0x134e 7031#define mmCM4_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 7032#define mmCM4_CM_BLNDGAM_RAMA_REGION_12_13 0x134f 7033#define mmCM4_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 7034#define mmCM4_CM_BLNDGAM_RAMA_REGION_14_15 0x1350 7035#define mmCM4_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 7036#define mmCM4_CM_BLNDGAM_RAMA_REGION_16_17 0x1351 7037#define mmCM4_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 7038#define mmCM4_CM_BLNDGAM_RAMA_REGION_18_19 0x1352 7039#define mmCM4_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 7040#define mmCM4_CM_BLNDGAM_RAMA_REGION_20_21 0x1353 7041#define mmCM4_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 7042#define mmCM4_CM_BLNDGAM_RAMA_REGION_22_23 0x1354 7043#define mmCM4_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 7044#define mmCM4_CM_BLNDGAM_RAMA_REGION_24_25 0x1355 7045#define mmCM4_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 7046#define mmCM4_CM_BLNDGAM_RAMA_REGION_26_27 0x1356 7047#define mmCM4_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 7048#define mmCM4_CM_BLNDGAM_RAMA_REGION_28_29 0x1357 7049#define mmCM4_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 7050#define mmCM4_CM_BLNDGAM_RAMA_REGION_30_31 0x1358 7051#define mmCM4_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 7052#define mmCM4_CM_BLNDGAM_RAMA_REGION_32_33 0x1359 7053#define mmCM4_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 7054#define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_B 0x135a 7055#define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 7056#define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_G 0x135b 7057#define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 7058#define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_R 0x135c 7059#define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 7060#define mmCM4_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x135d 7061#define mmCM4_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 7062#define mmCM4_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x135e 7063#define mmCM4_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 7064#define mmCM4_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x135f 7065#define mmCM4_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 7066#define mmCM4_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x1360 7067#define mmCM4_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 7068#define mmCM4_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x1361 7069#define mmCM4_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 7070#define mmCM4_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x1362 7071#define mmCM4_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 7072#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_B 0x1363 7073#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 7074#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_B 0x1364 7075#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 7076#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_G 0x1365 7077#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 7078#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_G 0x1366 7079#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 7080#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_R 0x1367 7081#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 7082#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_R 0x1368 7083#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 7084#define mmCM4_CM_BLNDGAM_RAMB_OFFSET_B 0x1369 7085#define mmCM4_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 7086#define mmCM4_CM_BLNDGAM_RAMB_OFFSET_G 0x136a 7087#define mmCM4_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 7088#define mmCM4_CM_BLNDGAM_RAMB_OFFSET_R 0x136b 7089#define mmCM4_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 7090#define mmCM4_CM_BLNDGAM_RAMB_REGION_0_1 0x136c 7091#define mmCM4_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 7092#define mmCM4_CM_BLNDGAM_RAMB_REGION_2_3 0x136d 7093#define mmCM4_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 7094#define mmCM4_CM_BLNDGAM_RAMB_REGION_4_5 0x136e 7095#define mmCM4_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 7096#define mmCM4_CM_BLNDGAM_RAMB_REGION_6_7 0x136f 7097#define mmCM4_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 7098#define mmCM4_CM_BLNDGAM_RAMB_REGION_8_9 0x1370 7099#define mmCM4_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 7100#define mmCM4_CM_BLNDGAM_RAMB_REGION_10_11 0x1371 7101#define mmCM4_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 7102#define mmCM4_CM_BLNDGAM_RAMB_REGION_12_13 0x1372 7103#define mmCM4_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 7104#define mmCM4_CM_BLNDGAM_RAMB_REGION_14_15 0x1373 7105#define mmCM4_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 7106#define mmCM4_CM_BLNDGAM_RAMB_REGION_16_17 0x1374 7107#define mmCM4_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 7108#define mmCM4_CM_BLNDGAM_RAMB_REGION_18_19 0x1375 7109#define mmCM4_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 7110#define mmCM4_CM_BLNDGAM_RAMB_REGION_20_21 0x1376 7111#define mmCM4_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 7112#define mmCM4_CM_BLNDGAM_RAMB_REGION_22_23 0x1377 7113#define mmCM4_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 7114#define mmCM4_CM_BLNDGAM_RAMB_REGION_24_25 0x1378 7115#define mmCM4_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 7116#define mmCM4_CM_BLNDGAM_RAMB_REGION_26_27 0x1379 7117#define mmCM4_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 7118#define mmCM4_CM_BLNDGAM_RAMB_REGION_28_29 0x137a 7119#define mmCM4_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 7120#define mmCM4_CM_BLNDGAM_RAMB_REGION_30_31 0x137b 7121#define mmCM4_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 7122#define mmCM4_CM_BLNDGAM_RAMB_REGION_32_33 0x137c 7123#define mmCM4_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 7124#define mmCM4_CM_HDR_MULT_COEF 0x137d 7125#define mmCM4_CM_HDR_MULT_COEF_BASE_IDX 2 7126#define mmCM4_CM_MEM_PWR_CTRL 0x137e 7127#define mmCM4_CM_MEM_PWR_CTRL_BASE_IDX 2 7128#define mmCM4_CM_MEM_PWR_STATUS 0x137f 7129#define mmCM4_CM_MEM_PWR_STATUS_BASE_IDX 2 7130#define mmCM4_CM_DEALPHA 0x1381 7131#define mmCM4_CM_DEALPHA_BASE_IDX 2 7132#define mmCM4_CM_COEF_FORMAT 0x1382 7133#define mmCM4_CM_COEF_FORMAT_BASE_IDX 2 7134#define mmCM4_CM_SHAPER_CONTROL 0x1383 7135#define mmCM4_CM_SHAPER_CONTROL_BASE_IDX 2 7136#define mmCM4_CM_SHAPER_OFFSET_R 0x1384 7137#define mmCM4_CM_SHAPER_OFFSET_R_BASE_IDX 2 7138#define mmCM4_CM_SHAPER_OFFSET_G 0x1385 7139#define mmCM4_CM_SHAPER_OFFSET_G_BASE_IDX 2 7140#define mmCM4_CM_SHAPER_OFFSET_B 0x1386 7141#define mmCM4_CM_SHAPER_OFFSET_B_BASE_IDX 2 7142#define mmCM4_CM_SHAPER_SCALE_R 0x1387 7143#define mmCM4_CM_SHAPER_SCALE_R_BASE_IDX 2 7144#define mmCM4_CM_SHAPER_SCALE_G_B 0x1388 7145#define mmCM4_CM_SHAPER_SCALE_G_B_BASE_IDX 2 7146#define mmCM4_CM_SHAPER_LUT_INDEX 0x1389 7147#define mmCM4_CM_SHAPER_LUT_INDEX_BASE_IDX 2 7148#define mmCM4_CM_SHAPER_LUT_DATA 0x138a 7149#define mmCM4_CM_SHAPER_LUT_DATA_BASE_IDX 2 7150#define mmCM4_CM_SHAPER_LUT_WRITE_EN_MASK 0x138b 7151#define mmCM4_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 7152#define mmCM4_CM_SHAPER_RAMA_START_CNTL_B 0x138c 7153#define mmCM4_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 7154#define mmCM4_CM_SHAPER_RAMA_START_CNTL_G 0x138d 7155#define mmCM4_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 7156#define mmCM4_CM_SHAPER_RAMA_START_CNTL_R 0x138e 7157#define mmCM4_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 7158#define mmCM4_CM_SHAPER_RAMA_END_CNTL_B 0x138f 7159#define mmCM4_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 7160#define mmCM4_CM_SHAPER_RAMA_END_CNTL_G 0x1390 7161#define mmCM4_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 7162#define mmCM4_CM_SHAPER_RAMA_END_CNTL_R 0x1391 7163#define mmCM4_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 7164#define mmCM4_CM_SHAPER_RAMA_REGION_0_1 0x1392 7165#define mmCM4_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 7166#define mmCM4_CM_SHAPER_RAMA_REGION_2_3 0x1393 7167#define mmCM4_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 7168#define mmCM4_CM_SHAPER_RAMA_REGION_4_5 0x1394 7169#define mmCM4_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 7170#define mmCM4_CM_SHAPER_RAMA_REGION_6_7 0x1395 7171#define mmCM4_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 7172#define mmCM4_CM_SHAPER_RAMA_REGION_8_9 0x1396 7173#define mmCM4_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 7174#define mmCM4_CM_SHAPER_RAMA_REGION_10_11 0x1397 7175#define mmCM4_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 7176#define mmCM4_CM_SHAPER_RAMA_REGION_12_13 0x1398 7177#define mmCM4_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 7178#define mmCM4_CM_SHAPER_RAMA_REGION_14_15 0x1399 7179#define mmCM4_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 7180#define mmCM4_CM_SHAPER_RAMA_REGION_16_17 0x139a 7181#define mmCM4_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 7182#define mmCM4_CM_SHAPER_RAMA_REGION_18_19 0x139b 7183#define mmCM4_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 7184#define mmCM4_CM_SHAPER_RAMA_REGION_20_21 0x139c 7185#define mmCM4_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 7186#define mmCM4_CM_SHAPER_RAMA_REGION_22_23 0x139d 7187#define mmCM4_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 7188#define mmCM4_CM_SHAPER_RAMA_REGION_24_25 0x139e 7189#define mmCM4_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 7190#define mmCM4_CM_SHAPER_RAMA_REGION_26_27 0x139f 7191#define mmCM4_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 7192#define mmCM4_CM_SHAPER_RAMA_REGION_28_29 0x13a0 7193#define mmCM4_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 7194#define mmCM4_CM_SHAPER_RAMA_REGION_30_31 0x13a1 7195#define mmCM4_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 7196#define mmCM4_CM_SHAPER_RAMA_REGION_32_33 0x13a2 7197#define mmCM4_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 7198#define mmCM4_CM_SHAPER_RAMB_START_CNTL_B 0x13a3 7199#define mmCM4_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 7200#define mmCM4_CM_SHAPER_RAMB_START_CNTL_G 0x13a4 7201#define mmCM4_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 7202#define mmCM4_CM_SHAPER_RAMB_START_CNTL_R 0x13a5 7203#define mmCM4_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 7204#define mmCM4_CM_SHAPER_RAMB_END_CNTL_B 0x13a6 7205#define mmCM4_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 7206#define mmCM4_CM_SHAPER_RAMB_END_CNTL_G 0x13a7 7207#define mmCM4_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 7208#define mmCM4_CM_SHAPER_RAMB_END_CNTL_R 0x13a8 7209#define mmCM4_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 7210#define mmCM4_CM_SHAPER_RAMB_REGION_0_1 0x13a9 7211#define mmCM4_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 7212#define mmCM4_CM_SHAPER_RAMB_REGION_2_3 0x13aa 7213#define mmCM4_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 7214#define mmCM4_CM_SHAPER_RAMB_REGION_4_5 0x13ab 7215#define mmCM4_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 7216#define mmCM4_CM_SHAPER_RAMB_REGION_6_7 0x13ac 7217#define mmCM4_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 7218#define mmCM4_CM_SHAPER_RAMB_REGION_8_9 0x13ad 7219#define mmCM4_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 7220#define mmCM4_CM_SHAPER_RAMB_REGION_10_11 0x13ae 7221#define mmCM4_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 7222#define mmCM4_CM_SHAPER_RAMB_REGION_12_13 0x13af 7223#define mmCM4_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 7224#define mmCM4_CM_SHAPER_RAMB_REGION_14_15 0x13b0 7225#define mmCM4_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 7226#define mmCM4_CM_SHAPER_RAMB_REGION_16_17 0x13b1 7227#define mmCM4_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 7228#define mmCM4_CM_SHAPER_RAMB_REGION_18_19 0x13b2 7229#define mmCM4_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 7230#define mmCM4_CM_SHAPER_RAMB_REGION_20_21 0x13b3 7231#define mmCM4_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 7232#define mmCM4_CM_SHAPER_RAMB_REGION_22_23 0x13b4 7233#define mmCM4_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 7234#define mmCM4_CM_SHAPER_RAMB_REGION_24_25 0x13b5 7235#define mmCM4_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 7236#define mmCM4_CM_SHAPER_RAMB_REGION_26_27 0x13b6 7237#define mmCM4_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 7238#define mmCM4_CM_SHAPER_RAMB_REGION_28_29 0x13b7 7239#define mmCM4_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 7240#define mmCM4_CM_SHAPER_RAMB_REGION_30_31 0x13b8 7241#define mmCM4_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 7242#define mmCM4_CM_SHAPER_RAMB_REGION_32_33 0x13b9 7243#define mmCM4_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 7244#define mmCM4_CM_MEM_PWR_CTRL2 0x13ba 7245#define mmCM4_CM_MEM_PWR_CTRL2_BASE_IDX 2 7246#define mmCM4_CM_MEM_PWR_STATUS2 0x13bb 7247#define mmCM4_CM_MEM_PWR_STATUS2_BASE_IDX 2 7248#define mmCM4_CM_3DLUT_MODE 0x13bc 7249#define mmCM4_CM_3DLUT_MODE_BASE_IDX 2 7250#define mmCM4_CM_3DLUT_INDEX 0x13bd 7251#define mmCM4_CM_3DLUT_INDEX_BASE_IDX 2 7252#define mmCM4_CM_3DLUT_DATA 0x13be 7253#define mmCM4_CM_3DLUT_DATA_BASE_IDX 2 7254#define mmCM4_CM_3DLUT_DATA_30BIT 0x13bf 7255#define mmCM4_CM_3DLUT_DATA_30BIT_BASE_IDX 2 7256#define mmCM4_CM_3DLUT_READ_WRITE_CONTROL 0x13c0 7257#define mmCM4_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 7258#define mmCM4_CM_3DLUT_OUT_NORM_FACTOR 0x13c1 7259#define mmCM4_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 7260#define mmCM4_CM_3DLUT_OUT_OFFSET_R 0x13c2 7261#define mmCM4_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 7262#define mmCM4_CM_3DLUT_OUT_OFFSET_G 0x13c3 7263#define mmCM4_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 7264#define mmCM4_CM_3DLUT_OUT_OFFSET_B 0x13c4 7265#define mmCM4_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 7266 7267 7268// addressBlock: dce_dc_dpp4_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 7269// base address: 0x4f40 7270#define mmDC_PERFMON16_PERFCOUNTER_CNTL 0x13d0 7271#define mmDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX 2 7272#define mmDC_PERFMON16_PERFCOUNTER_CNTL2 0x13d1 7273#define mmDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX 2 7274#define mmDC_PERFMON16_PERFCOUNTER_STATE 0x13d2 7275#define mmDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX 2 7276#define mmDC_PERFMON16_PERFMON_CNTL 0x13d3 7277#define mmDC_PERFMON16_PERFMON_CNTL_BASE_IDX 2 7278#define mmDC_PERFMON16_PERFMON_CNTL2 0x13d4 7279#define mmDC_PERFMON16_PERFMON_CNTL2_BASE_IDX 2 7280#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC 0x13d5 7281#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 7282#define mmDC_PERFMON16_PERFMON_CVALUE_LOW 0x13d6 7283#define mmDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX 2 7284#define mmDC_PERFMON16_PERFMON_HI 0x13d7 7285#define mmDC_PERFMON16_PERFMON_HI_BASE_IDX 2 7286#define mmDC_PERFMON16_PERFMON_LOW 0x13d8 7287#define mmDC_PERFMON16_PERFMON_LOW_BASE_IDX 2 7288 7289 7290// addressBlock: dce_dc_dpp5_dispdec_dpp_top_dispdec 7291// base address: 0x1c5c 7292#define mmDPP_TOP5_DPP_CONTROL 0x13dc 7293#define mmDPP_TOP5_DPP_CONTROL_BASE_IDX 2 7294#define mmDPP_TOP5_DPP_SOFT_RESET 0x13dd 7295#define mmDPP_TOP5_DPP_SOFT_RESET_BASE_IDX 2 7296#define mmDPP_TOP5_DPP_CRC_VAL_R_G 0x13de 7297#define mmDPP_TOP5_DPP_CRC_VAL_R_G_BASE_IDX 2 7298#define mmDPP_TOP5_DPP_CRC_VAL_B_A 0x13df 7299#define mmDPP_TOP5_DPP_CRC_VAL_B_A_BASE_IDX 2 7300#define mmDPP_TOP5_DPP_CRC_CTRL 0x13e0 7301#define mmDPP_TOP5_DPP_CRC_CTRL_BASE_IDX 2 7302#define mmDPP_TOP5_HOST_READ_CONTROL 0x13e1 7303#define mmDPP_TOP5_HOST_READ_CONTROL_BASE_IDX 2 7304 7305 7306// addressBlock: dce_dc_dpp5_dispdec_cnvc_cfg_dispdec 7307// base address: 0x1c5c 7308#define mmCNVC_CFG5_CNVC_SURFACE_PIXEL_FORMAT 0x13e6 7309#define mmCNVC_CFG5_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 7310#define mmCNVC_CFG5_FORMAT_CONTROL 0x13e7 7311#define mmCNVC_CFG5_FORMAT_CONTROL_BASE_IDX 2 7312#define mmCNVC_CFG5_FCNV_FP_BIAS_R 0x13e8 7313#define mmCNVC_CFG5_FCNV_FP_BIAS_R_BASE_IDX 2 7314#define mmCNVC_CFG5_FCNV_FP_BIAS_G 0x13e9 7315#define mmCNVC_CFG5_FCNV_FP_BIAS_G_BASE_IDX 2 7316#define mmCNVC_CFG5_FCNV_FP_BIAS_B 0x13ea 7317#define mmCNVC_CFG5_FCNV_FP_BIAS_B_BASE_IDX 2 7318#define mmCNVC_CFG5_FCNV_FP_SCALE_R 0x13eb 7319#define mmCNVC_CFG5_FCNV_FP_SCALE_R_BASE_IDX 2 7320#define mmCNVC_CFG5_FCNV_FP_SCALE_G 0x13ec 7321#define mmCNVC_CFG5_FCNV_FP_SCALE_G_BASE_IDX 2 7322#define mmCNVC_CFG5_FCNV_FP_SCALE_B 0x13ed 7323#define mmCNVC_CFG5_FCNV_FP_SCALE_B_BASE_IDX 2 7324#define mmCNVC_CFG5_COLOR_KEYER_CONTROL 0x13ee 7325#define mmCNVC_CFG5_COLOR_KEYER_CONTROL_BASE_IDX 2 7326#define mmCNVC_CFG5_COLOR_KEYER_ALPHA 0x13ef 7327#define mmCNVC_CFG5_COLOR_KEYER_ALPHA_BASE_IDX 2 7328#define mmCNVC_CFG5_COLOR_KEYER_RED 0x13f0 7329#define mmCNVC_CFG5_COLOR_KEYER_RED_BASE_IDX 2 7330#define mmCNVC_CFG5_COLOR_KEYER_GREEN 0x13f1 7331#define mmCNVC_CFG5_COLOR_KEYER_GREEN_BASE_IDX 2 7332#define mmCNVC_CFG5_COLOR_KEYER_BLUE 0x13f2 7333#define mmCNVC_CFG5_COLOR_KEYER_BLUE_BASE_IDX 2 7334#define mmCNVC_CFG5_ALPHA_2BIT_LUT 0x13f4 7335#define mmCNVC_CFG5_ALPHA_2BIT_LUT_BASE_IDX 2 7336#define mmCNVC_CFG5_PRE_DEALPHA 0x13f5 7337#define mmCNVC_CFG5_PRE_DEALPHA_BASE_IDX 2 7338#define mmCNVC_CFG5_PRE_CSC_MODE 0x13f6 7339#define mmCNVC_CFG5_PRE_CSC_MODE_BASE_IDX 2 7340#define mmCNVC_CFG5_PRE_CSC_C11_C12 0x13f7 7341#define mmCNVC_CFG5_PRE_CSC_C11_C12_BASE_IDX 2 7342#define mmCNVC_CFG5_PRE_CSC_C13_C14 0x13f8 7343#define mmCNVC_CFG5_PRE_CSC_C13_C14_BASE_IDX 2 7344#define mmCNVC_CFG5_PRE_CSC_C21_C22 0x13f9 7345#define mmCNVC_CFG5_PRE_CSC_C21_C22_BASE_IDX 2 7346#define mmCNVC_CFG5_PRE_CSC_C23_C24 0x13fa 7347#define mmCNVC_CFG5_PRE_CSC_C23_C24_BASE_IDX 2 7348#define mmCNVC_CFG5_PRE_CSC_C31_C32 0x13fb 7349#define mmCNVC_CFG5_PRE_CSC_C31_C32_BASE_IDX 2 7350#define mmCNVC_CFG5_PRE_CSC_C33_C34 0x13fc 7351#define mmCNVC_CFG5_PRE_CSC_C33_C34_BASE_IDX 2 7352#define mmCNVC_CFG5_PRE_CSC_B_C11_C12 0x13fd 7353#define mmCNVC_CFG5_PRE_CSC_B_C11_C12_BASE_IDX 2 7354#define mmCNVC_CFG5_PRE_CSC_B_C13_C14 0x13fe 7355#define mmCNVC_CFG5_PRE_CSC_B_C13_C14_BASE_IDX 2 7356#define mmCNVC_CFG5_PRE_CSC_B_C21_C22 0x13ff 7357#define mmCNVC_CFG5_PRE_CSC_B_C21_C22_BASE_IDX 2 7358#define mmCNVC_CFG5_PRE_CSC_B_C23_C24 0x1400 7359#define mmCNVC_CFG5_PRE_CSC_B_C23_C24_BASE_IDX 2 7360#define mmCNVC_CFG5_PRE_CSC_B_C31_C32 0x1401 7361#define mmCNVC_CFG5_PRE_CSC_B_C31_C32_BASE_IDX 2 7362#define mmCNVC_CFG5_PRE_CSC_B_C33_C34 0x1402 7363#define mmCNVC_CFG5_PRE_CSC_B_C33_C34_BASE_IDX 2 7364#define mmCNVC_CFG5_CNVC_COEF_FORMAT 0x1403 7365#define mmCNVC_CFG5_CNVC_COEF_FORMAT_BASE_IDX 2 7366#define mmCNVC_CFG5_PRE_DEGAM 0x1404 7367#define mmCNVC_CFG5_PRE_DEGAM_BASE_IDX 2 7368#define mmCNVC_CFG5_PRE_REALPHA 0x1405 7369#define mmCNVC_CFG5_PRE_REALPHA_BASE_IDX 2 7370 7371 7372// addressBlock: dce_dc_dpp5_dispdec_cnvc_cur_dispdec 7373// base address: 0x1c5c 7374#define mmCNVC_CUR5_CURSOR0_CONTROL 0x1408 7375#define mmCNVC_CUR5_CURSOR0_CONTROL_BASE_IDX 2 7376#define mmCNVC_CUR5_CURSOR0_COLOR0 0x1409 7377#define mmCNVC_CUR5_CURSOR0_COLOR0_BASE_IDX 2 7378#define mmCNVC_CUR5_CURSOR0_COLOR1 0x140a 7379#define mmCNVC_CUR5_CURSOR0_COLOR1_BASE_IDX 2 7380#define mmCNVC_CUR5_CURSOR0_FP_SCALE_BIAS 0x140b 7381#define mmCNVC_CUR5_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 7382 7383 7384// addressBlock: dce_dc_dpp5_dispdec_dscl_dispdec 7385// base address: 0x1c5c 7386#define mmDSCL5_SCL_COEF_RAM_TAP_SELECT 0x1410 7387#define mmDSCL5_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 7388#define mmDSCL5_SCL_COEF_RAM_TAP_DATA 0x1411 7389#define mmDSCL5_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 7390#define mmDSCL5_SCL_MODE 0x1412 7391#define mmDSCL5_SCL_MODE_BASE_IDX 2 7392#define mmDSCL5_SCL_TAP_CONTROL 0x1413 7393#define mmDSCL5_SCL_TAP_CONTROL_BASE_IDX 2 7394#define mmDSCL5_DSCL_CONTROL 0x1414 7395#define mmDSCL5_DSCL_CONTROL_BASE_IDX 2 7396#define mmDSCL5_DSCL_2TAP_CONTROL 0x1415 7397#define mmDSCL5_DSCL_2TAP_CONTROL_BASE_IDX 2 7398#define mmDSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x1416 7399#define mmDSCL5_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 7400#define mmDSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x1417 7401#define mmDSCL5_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 7402#define mmDSCL5_SCL_HORZ_FILTER_INIT 0x1418 7403#define mmDSCL5_SCL_HORZ_FILTER_INIT_BASE_IDX 2 7404#define mmDSCL5_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1419 7405#define mmDSCL5_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 7406#define mmDSCL5_SCL_HORZ_FILTER_INIT_C 0x141a 7407#define mmDSCL5_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 7408#define mmDSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x141b 7409#define mmDSCL5_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 7410#define mmDSCL5_SCL_VERT_FILTER_INIT 0x141c 7411#define mmDSCL5_SCL_VERT_FILTER_INIT_BASE_IDX 2 7412#define mmDSCL5_SCL_VERT_FILTER_INIT_BOT 0x141d 7413#define mmDSCL5_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 7414#define mmDSCL5_SCL_VERT_FILTER_SCALE_RATIO_C 0x141e 7415#define mmDSCL5_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 7416#define mmDSCL5_SCL_VERT_FILTER_INIT_C 0x141f 7417#define mmDSCL5_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 7418#define mmDSCL5_SCL_VERT_FILTER_INIT_BOT_C 0x1420 7419#define mmDSCL5_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 7420#define mmDSCL5_SCL_BLACK_COLOR 0x1421 7421#define mmDSCL5_SCL_BLACK_COLOR_BASE_IDX 2 7422#define mmDSCL5_DSCL_UPDATE 0x1422 7423#define mmDSCL5_DSCL_UPDATE_BASE_IDX 2 7424#define mmDSCL5_DSCL_AUTOCAL 0x1423 7425#define mmDSCL5_DSCL_AUTOCAL_BASE_IDX 2 7426#define mmDSCL5_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x1424 7427#define mmDSCL5_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 7428#define mmDSCL5_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x1425 7429#define mmDSCL5_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 7430#define mmDSCL5_OTG_H_BLANK 0x1426 7431#define mmDSCL5_OTG_H_BLANK_BASE_IDX 2 7432#define mmDSCL5_OTG_V_BLANK 0x1427 7433#define mmDSCL5_OTG_V_BLANK_BASE_IDX 2 7434#define mmDSCL5_RECOUT_START 0x1428 7435#define mmDSCL5_RECOUT_START_BASE_IDX 2 7436#define mmDSCL5_RECOUT_SIZE 0x1429 7437#define mmDSCL5_RECOUT_SIZE_BASE_IDX 2 7438#define mmDSCL5_MPC_SIZE 0x142a 7439#define mmDSCL5_MPC_SIZE_BASE_IDX 2 7440#define mmDSCL5_LB_DATA_FORMAT 0x142b 7441#define mmDSCL5_LB_DATA_FORMAT_BASE_IDX 2 7442#define mmDSCL5_LB_MEMORY_CTRL 0x142c 7443#define mmDSCL5_LB_MEMORY_CTRL_BASE_IDX 2 7444#define mmDSCL5_LB_V_COUNTER 0x142d 7445#define mmDSCL5_LB_V_COUNTER_BASE_IDX 2 7446#define mmDSCL5_DSCL_MEM_PWR_CTRL 0x142e 7447#define mmDSCL5_DSCL_MEM_PWR_CTRL_BASE_IDX 2 7448#define mmDSCL5_DSCL_MEM_PWR_STATUS 0x142f 7449#define mmDSCL5_DSCL_MEM_PWR_STATUS_BASE_IDX 2 7450#define mmDSCL5_OBUF_CONTROL 0x1430 7451#define mmDSCL5_OBUF_CONTROL_BASE_IDX 2 7452#define mmDSCL5_OBUF_MEM_PWR_CTRL 0x1431 7453#define mmDSCL5_OBUF_MEM_PWR_CTRL_BASE_IDX 2 7454 7455 7456// addressBlock: dce_dc_dpp5_dispdec_cm_dispdec 7457// base address: 0x1c5c 7458#define mmCM5_CM_CONTROL 0x1437 7459#define mmCM5_CM_CONTROL_BASE_IDX 2 7460#define mmCM5_CM_POST_CSC_CONTROL 0x1438 7461#define mmCM5_CM_POST_CSC_CONTROL_BASE_IDX 2 7462#define mmCM5_CM_POST_CSC_C11_C12 0x1439 7463#define mmCM5_CM_POST_CSC_C11_C12_BASE_IDX 2 7464#define mmCM5_CM_POST_CSC_C13_C14 0x143a 7465#define mmCM5_CM_POST_CSC_C13_C14_BASE_IDX 2 7466#define mmCM5_CM_POST_CSC_C21_C22 0x143b 7467#define mmCM5_CM_POST_CSC_C21_C22_BASE_IDX 2 7468#define mmCM5_CM_POST_CSC_C23_C24 0x143c 7469#define mmCM5_CM_POST_CSC_C23_C24_BASE_IDX 2 7470#define mmCM5_CM_POST_CSC_C31_C32 0x143d 7471#define mmCM5_CM_POST_CSC_C31_C32_BASE_IDX 2 7472#define mmCM5_CM_POST_CSC_C33_C34 0x143e 7473#define mmCM5_CM_POST_CSC_C33_C34_BASE_IDX 2 7474#define mmCM5_CM_POST_CSC_B_C11_C12 0x143f 7475#define mmCM5_CM_POST_CSC_B_C11_C12_BASE_IDX 2 7476#define mmCM5_CM_POST_CSC_B_C13_C14 0x1440 7477#define mmCM5_CM_POST_CSC_B_C13_C14_BASE_IDX 2 7478#define mmCM5_CM_POST_CSC_B_C21_C22 0x1441 7479#define mmCM5_CM_POST_CSC_B_C21_C22_BASE_IDX 2 7480#define mmCM5_CM_POST_CSC_B_C23_C24 0x1442 7481#define mmCM5_CM_POST_CSC_B_C23_C24_BASE_IDX 2 7482#define mmCM5_CM_POST_CSC_B_C31_C32 0x1443 7483#define mmCM5_CM_POST_CSC_B_C31_C32_BASE_IDX 2 7484#define mmCM5_CM_POST_CSC_B_C33_C34 0x1444 7485#define mmCM5_CM_POST_CSC_B_C33_C34_BASE_IDX 2 7486#define mmCM5_CM_GAMUT_REMAP_CONTROL 0x1445 7487#define mmCM5_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 7488#define mmCM5_CM_GAMUT_REMAP_C11_C12 0x1446 7489#define mmCM5_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 7490#define mmCM5_CM_GAMUT_REMAP_C13_C14 0x1447 7491#define mmCM5_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 7492#define mmCM5_CM_GAMUT_REMAP_C21_C22 0x1448 7493#define mmCM5_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 7494#define mmCM5_CM_GAMUT_REMAP_C23_C24 0x1449 7495#define mmCM5_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 7496#define mmCM5_CM_GAMUT_REMAP_C31_C32 0x144a 7497#define mmCM5_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 7498#define mmCM5_CM_GAMUT_REMAP_C33_C34 0x144b 7499#define mmCM5_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 7500#define mmCM5_CM_GAMUT_REMAP_B_C11_C12 0x144c 7501#define mmCM5_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 7502#define mmCM5_CM_GAMUT_REMAP_B_C13_C14 0x144d 7503#define mmCM5_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 7504#define mmCM5_CM_GAMUT_REMAP_B_C21_C22 0x144e 7505#define mmCM5_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 7506#define mmCM5_CM_GAMUT_REMAP_B_C23_C24 0x144f 7507#define mmCM5_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 7508#define mmCM5_CM_GAMUT_REMAP_B_C31_C32 0x1450 7509#define mmCM5_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 7510#define mmCM5_CM_GAMUT_REMAP_B_C33_C34 0x1451 7511#define mmCM5_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 7512#define mmCM5_CM_BIAS_CR_R 0x1452 7513#define mmCM5_CM_BIAS_CR_R_BASE_IDX 2 7514#define mmCM5_CM_BIAS_Y_G_CB_B 0x1453 7515#define mmCM5_CM_BIAS_Y_G_CB_B_BASE_IDX 2 7516#define mmCM5_CM_GAMCOR_CONTROL 0x1454 7517#define mmCM5_CM_GAMCOR_CONTROL_BASE_IDX 2 7518#define mmCM5_CM_GAMCOR_LUT_INDEX 0x1455 7519#define mmCM5_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 7520#define mmCM5_CM_GAMCOR_LUT_DATA 0x1456 7521#define mmCM5_CM_GAMCOR_LUT_DATA_BASE_IDX 2 7522#define mmCM5_CM_GAMCOR_LUT_CONTROL 0x1457 7523#define mmCM5_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 7524#define mmCM5_CM_GAMCOR_RAMA_START_CNTL_B 0x1458 7525#define mmCM5_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 7526#define mmCM5_CM_GAMCOR_RAMA_START_CNTL_G 0x1459 7527#define mmCM5_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 7528#define mmCM5_CM_GAMCOR_RAMA_START_CNTL_R 0x145a 7529#define mmCM5_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 7530#define mmCM5_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x145b 7531#define mmCM5_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 7532#define mmCM5_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x145c 7533#define mmCM5_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 7534#define mmCM5_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x145d 7535#define mmCM5_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 7536#define mmCM5_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x145e 7537#define mmCM5_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 7538#define mmCM5_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x145f 7539#define mmCM5_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 7540#define mmCM5_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x1460 7541#define mmCM5_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 7542#define mmCM5_CM_GAMCOR_RAMA_END_CNTL1_B 0x1461 7543#define mmCM5_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 7544#define mmCM5_CM_GAMCOR_RAMA_END_CNTL2_B 0x1462 7545#define mmCM5_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 7546#define mmCM5_CM_GAMCOR_RAMA_END_CNTL1_G 0x1463 7547#define mmCM5_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 7548#define mmCM5_CM_GAMCOR_RAMA_END_CNTL2_G 0x1464 7549#define mmCM5_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 7550#define mmCM5_CM_GAMCOR_RAMA_END_CNTL1_R 0x1465 7551#define mmCM5_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 7552#define mmCM5_CM_GAMCOR_RAMA_END_CNTL2_R 0x1466 7553#define mmCM5_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 7554#define mmCM5_CM_GAMCOR_RAMA_OFFSET_B 0x1467 7555#define mmCM5_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 7556#define mmCM5_CM_GAMCOR_RAMA_OFFSET_G 0x1468 7557#define mmCM5_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 7558#define mmCM5_CM_GAMCOR_RAMA_OFFSET_R 0x1469 7559#define mmCM5_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 7560#define mmCM5_CM_GAMCOR_RAMA_REGION_0_1 0x146a 7561#define mmCM5_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 7562#define mmCM5_CM_GAMCOR_RAMA_REGION_2_3 0x146b 7563#define mmCM5_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 7564#define mmCM5_CM_GAMCOR_RAMA_REGION_4_5 0x146c 7565#define mmCM5_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 7566#define mmCM5_CM_GAMCOR_RAMA_REGION_6_7 0x146d 7567#define mmCM5_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 7568#define mmCM5_CM_GAMCOR_RAMA_REGION_8_9 0x146e 7569#define mmCM5_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 7570#define mmCM5_CM_GAMCOR_RAMA_REGION_10_11 0x146f 7571#define mmCM5_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 7572#define mmCM5_CM_GAMCOR_RAMA_REGION_12_13 0x1470 7573#define mmCM5_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 7574#define mmCM5_CM_GAMCOR_RAMA_REGION_14_15 0x1471 7575#define mmCM5_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 7576#define mmCM5_CM_GAMCOR_RAMA_REGION_16_17 0x1472 7577#define mmCM5_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 7578#define mmCM5_CM_GAMCOR_RAMA_REGION_18_19 0x1473 7579#define mmCM5_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 7580#define mmCM5_CM_GAMCOR_RAMA_REGION_20_21 0x1474 7581#define mmCM5_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 7582#define mmCM5_CM_GAMCOR_RAMA_REGION_22_23 0x1475 7583#define mmCM5_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 7584#define mmCM5_CM_GAMCOR_RAMA_REGION_24_25 0x1476 7585#define mmCM5_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 7586#define mmCM5_CM_GAMCOR_RAMA_REGION_26_27 0x1477 7587#define mmCM5_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 7588#define mmCM5_CM_GAMCOR_RAMA_REGION_28_29 0x1478 7589#define mmCM5_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 7590#define mmCM5_CM_GAMCOR_RAMA_REGION_30_31 0x1479 7591#define mmCM5_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 7592#define mmCM5_CM_GAMCOR_RAMA_REGION_32_33 0x147a 7593#define mmCM5_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 7594#define mmCM5_CM_GAMCOR_RAMB_START_CNTL_B 0x147b 7595#define mmCM5_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 7596#define mmCM5_CM_GAMCOR_RAMB_START_CNTL_G 0x147c 7597#define mmCM5_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 7598#define mmCM5_CM_GAMCOR_RAMB_START_CNTL_R 0x147d 7599#define mmCM5_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 7600#define mmCM5_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x147e 7601#define mmCM5_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 7602#define mmCM5_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x147f 7603#define mmCM5_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 7604#define mmCM5_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x1480 7605#define mmCM5_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 7606#define mmCM5_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x1481 7607#define mmCM5_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 7608#define mmCM5_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x1482 7609#define mmCM5_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 7610#define mmCM5_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x1483 7611#define mmCM5_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 7612#define mmCM5_CM_GAMCOR_RAMB_END_CNTL1_B 0x1484 7613#define mmCM5_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 7614#define mmCM5_CM_GAMCOR_RAMB_END_CNTL2_B 0x1485 7615#define mmCM5_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 7616#define mmCM5_CM_GAMCOR_RAMB_END_CNTL1_G 0x1486 7617#define mmCM5_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 7618#define mmCM5_CM_GAMCOR_RAMB_END_CNTL2_G 0x1487 7619#define mmCM5_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 7620#define mmCM5_CM_GAMCOR_RAMB_END_CNTL1_R 0x1488 7621#define mmCM5_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 7622#define mmCM5_CM_GAMCOR_RAMB_END_CNTL2_R 0x1489 7623#define mmCM5_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 7624#define mmCM5_CM_GAMCOR_RAMB_OFFSET_B 0x148a 7625#define mmCM5_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 7626#define mmCM5_CM_GAMCOR_RAMB_OFFSET_G 0x148b 7627#define mmCM5_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 7628#define mmCM5_CM_GAMCOR_RAMB_OFFSET_R 0x148c 7629#define mmCM5_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 7630#define mmCM5_CM_GAMCOR_RAMB_REGION_0_1 0x148d 7631#define mmCM5_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 7632#define mmCM5_CM_GAMCOR_RAMB_REGION_2_3 0x148e 7633#define mmCM5_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 7634#define mmCM5_CM_GAMCOR_RAMB_REGION_4_5 0x148f 7635#define mmCM5_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 7636#define mmCM5_CM_GAMCOR_RAMB_REGION_6_7 0x1490 7637#define mmCM5_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 7638#define mmCM5_CM_GAMCOR_RAMB_REGION_8_9 0x1491 7639#define mmCM5_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 7640#define mmCM5_CM_GAMCOR_RAMB_REGION_10_11 0x1492 7641#define mmCM5_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 7642#define mmCM5_CM_GAMCOR_RAMB_REGION_12_13 0x1493 7643#define mmCM5_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 7644#define mmCM5_CM_GAMCOR_RAMB_REGION_14_15 0x1494 7645#define mmCM5_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 7646#define mmCM5_CM_GAMCOR_RAMB_REGION_16_17 0x1495 7647#define mmCM5_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 7648#define mmCM5_CM_GAMCOR_RAMB_REGION_18_19 0x1496 7649#define mmCM5_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 7650#define mmCM5_CM_GAMCOR_RAMB_REGION_20_21 0x1497 7651#define mmCM5_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 7652#define mmCM5_CM_GAMCOR_RAMB_REGION_22_23 0x1498 7653#define mmCM5_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 7654#define mmCM5_CM_GAMCOR_RAMB_REGION_24_25 0x1499 7655#define mmCM5_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 7656#define mmCM5_CM_GAMCOR_RAMB_REGION_26_27 0x149a 7657#define mmCM5_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 7658#define mmCM5_CM_GAMCOR_RAMB_REGION_28_29 0x149b 7659#define mmCM5_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 7660#define mmCM5_CM_GAMCOR_RAMB_REGION_30_31 0x149c 7661#define mmCM5_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 7662#define mmCM5_CM_GAMCOR_RAMB_REGION_32_33 0x149d 7663#define mmCM5_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 7664#define mmCM5_CM_BLNDGAM_CONTROL 0x149e 7665#define mmCM5_CM_BLNDGAM_CONTROL_BASE_IDX 2 7666#define mmCM5_CM_BLNDGAM_LUT_INDEX 0x149f 7667#define mmCM5_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 7668#define mmCM5_CM_BLNDGAM_LUT_DATA 0x14a0 7669#define mmCM5_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 7670#define mmCM5_CM_BLNDGAM_LUT_CONTROL 0x14a1 7671#define mmCM5_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 7672#define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_B 0x14a2 7673#define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 7674#define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_G 0x14a3 7675#define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 7676#define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_R 0x14a4 7677#define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 7678#define mmCM5_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x14a5 7679#define mmCM5_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 7680#define mmCM5_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x14a6 7681#define mmCM5_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 7682#define mmCM5_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x14a7 7683#define mmCM5_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 7684#define mmCM5_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x14a8 7685#define mmCM5_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 7686#define mmCM5_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x14a9 7687#define mmCM5_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 7688#define mmCM5_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x14aa 7689#define mmCM5_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 7690#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_B 0x14ab 7691#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 7692#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_B 0x14ac 7693#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 7694#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_G 0x14ad 7695#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 7696#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_G 0x14ae 7697#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 7698#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_R 0x14af 7699#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 7700#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_R 0x14b0 7701#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 7702#define mmCM5_CM_BLNDGAM_RAMA_OFFSET_B 0x14b1 7703#define mmCM5_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 7704#define mmCM5_CM_BLNDGAM_RAMA_OFFSET_G 0x14b2 7705#define mmCM5_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 7706#define mmCM5_CM_BLNDGAM_RAMA_OFFSET_R 0x14b3 7707#define mmCM5_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 7708#define mmCM5_CM_BLNDGAM_RAMA_REGION_0_1 0x14b4 7709#define mmCM5_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 7710#define mmCM5_CM_BLNDGAM_RAMA_REGION_2_3 0x14b5 7711#define mmCM5_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 7712#define mmCM5_CM_BLNDGAM_RAMA_REGION_4_5 0x14b6 7713#define mmCM5_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 7714#define mmCM5_CM_BLNDGAM_RAMA_REGION_6_7 0x14b7 7715#define mmCM5_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 7716#define mmCM5_CM_BLNDGAM_RAMA_REGION_8_9 0x14b8 7717#define mmCM5_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 7718#define mmCM5_CM_BLNDGAM_RAMA_REGION_10_11 0x14b9 7719#define mmCM5_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 7720#define mmCM5_CM_BLNDGAM_RAMA_REGION_12_13 0x14ba 7721#define mmCM5_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 7722#define mmCM5_CM_BLNDGAM_RAMA_REGION_14_15 0x14bb 7723#define mmCM5_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 7724#define mmCM5_CM_BLNDGAM_RAMA_REGION_16_17 0x14bc 7725#define mmCM5_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 7726#define mmCM5_CM_BLNDGAM_RAMA_REGION_18_19 0x14bd 7727#define mmCM5_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 7728#define mmCM5_CM_BLNDGAM_RAMA_REGION_20_21 0x14be 7729#define mmCM5_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 7730#define mmCM5_CM_BLNDGAM_RAMA_REGION_22_23 0x14bf 7731#define mmCM5_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 7732#define mmCM5_CM_BLNDGAM_RAMA_REGION_24_25 0x14c0 7733#define mmCM5_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 7734#define mmCM5_CM_BLNDGAM_RAMA_REGION_26_27 0x14c1 7735#define mmCM5_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 7736#define mmCM5_CM_BLNDGAM_RAMA_REGION_28_29 0x14c2 7737#define mmCM5_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 7738#define mmCM5_CM_BLNDGAM_RAMA_REGION_30_31 0x14c3 7739#define mmCM5_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 7740#define mmCM5_CM_BLNDGAM_RAMA_REGION_32_33 0x14c4 7741#define mmCM5_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 7742#define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_B 0x14c5 7743#define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 7744#define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_G 0x14c6 7745#define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 7746#define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_R 0x14c7 7747#define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 7748#define mmCM5_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x14c8 7749#define mmCM5_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 7750#define mmCM5_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x14c9 7751#define mmCM5_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 7752#define mmCM5_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x14ca 7753#define mmCM5_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 7754#define mmCM5_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x14cb 7755#define mmCM5_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 7756#define mmCM5_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x14cc 7757#define mmCM5_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 7758#define mmCM5_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x14cd 7759#define mmCM5_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 7760#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_B 0x14ce 7761#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 7762#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_B 0x14cf 7763#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 7764#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_G 0x14d0 7765#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 7766#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_G 0x14d1 7767#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 7768#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_R 0x14d2 7769#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 7770#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_R 0x14d3 7771#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 7772#define mmCM5_CM_BLNDGAM_RAMB_OFFSET_B 0x14d4 7773#define mmCM5_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 7774#define mmCM5_CM_BLNDGAM_RAMB_OFFSET_G 0x14d5 7775#define mmCM5_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 7776#define mmCM5_CM_BLNDGAM_RAMB_OFFSET_R 0x14d6 7777#define mmCM5_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 7778#define mmCM5_CM_BLNDGAM_RAMB_REGION_0_1 0x14d7 7779#define mmCM5_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 7780#define mmCM5_CM_BLNDGAM_RAMB_REGION_2_3 0x14d8 7781#define mmCM5_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 7782#define mmCM5_CM_BLNDGAM_RAMB_REGION_4_5 0x14d9 7783#define mmCM5_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 7784#define mmCM5_CM_BLNDGAM_RAMB_REGION_6_7 0x14da 7785#define mmCM5_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 7786#define mmCM5_CM_BLNDGAM_RAMB_REGION_8_9 0x14db 7787#define mmCM5_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 7788#define mmCM5_CM_BLNDGAM_RAMB_REGION_10_11 0x14dc 7789#define mmCM5_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 7790#define mmCM5_CM_BLNDGAM_RAMB_REGION_12_13 0x14dd 7791#define mmCM5_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 7792#define mmCM5_CM_BLNDGAM_RAMB_REGION_14_15 0x14de 7793#define mmCM5_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 7794#define mmCM5_CM_BLNDGAM_RAMB_REGION_16_17 0x14df 7795#define mmCM5_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 7796#define mmCM5_CM_BLNDGAM_RAMB_REGION_18_19 0x14e0 7797#define mmCM5_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 7798#define mmCM5_CM_BLNDGAM_RAMB_REGION_20_21 0x14e1 7799#define mmCM5_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 7800#define mmCM5_CM_BLNDGAM_RAMB_REGION_22_23 0x14e2 7801#define mmCM5_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 7802#define mmCM5_CM_BLNDGAM_RAMB_REGION_24_25 0x14e3 7803#define mmCM5_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 7804#define mmCM5_CM_BLNDGAM_RAMB_REGION_26_27 0x14e4 7805#define mmCM5_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 7806#define mmCM5_CM_BLNDGAM_RAMB_REGION_28_29 0x14e5 7807#define mmCM5_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 7808#define mmCM5_CM_BLNDGAM_RAMB_REGION_30_31 0x14e6 7809#define mmCM5_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 7810#define mmCM5_CM_BLNDGAM_RAMB_REGION_32_33 0x14e7 7811#define mmCM5_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 7812#define mmCM5_CM_HDR_MULT_COEF 0x14e8 7813#define mmCM5_CM_HDR_MULT_COEF_BASE_IDX 2 7814#define mmCM5_CM_MEM_PWR_CTRL 0x14e9 7815#define mmCM5_CM_MEM_PWR_CTRL_BASE_IDX 2 7816#define mmCM5_CM_MEM_PWR_STATUS 0x14ea 7817#define mmCM5_CM_MEM_PWR_STATUS_BASE_IDX 2 7818#define mmCM5_CM_DEALPHA 0x14ec 7819#define mmCM5_CM_DEALPHA_BASE_IDX 2 7820#define mmCM5_CM_COEF_FORMAT 0x14ed 7821#define mmCM5_CM_COEF_FORMAT_BASE_IDX 2 7822#define mmCM5_CM_SHAPER_CONTROL 0x14ee 7823#define mmCM5_CM_SHAPER_CONTROL_BASE_IDX 2 7824#define mmCM5_CM_SHAPER_OFFSET_R 0x14ef 7825#define mmCM5_CM_SHAPER_OFFSET_R_BASE_IDX 2 7826#define mmCM5_CM_SHAPER_OFFSET_G 0x14f0 7827#define mmCM5_CM_SHAPER_OFFSET_G_BASE_IDX 2 7828#define mmCM5_CM_SHAPER_OFFSET_B 0x14f1 7829#define mmCM5_CM_SHAPER_OFFSET_B_BASE_IDX 2 7830#define mmCM5_CM_SHAPER_SCALE_R 0x14f2 7831#define mmCM5_CM_SHAPER_SCALE_R_BASE_IDX 2 7832#define mmCM5_CM_SHAPER_SCALE_G_B 0x14f3 7833#define mmCM5_CM_SHAPER_SCALE_G_B_BASE_IDX 2 7834#define mmCM5_CM_SHAPER_LUT_INDEX 0x14f4 7835#define mmCM5_CM_SHAPER_LUT_INDEX_BASE_IDX 2 7836#define mmCM5_CM_SHAPER_LUT_DATA 0x14f5 7837#define mmCM5_CM_SHAPER_LUT_DATA_BASE_IDX 2 7838#define mmCM5_CM_SHAPER_LUT_WRITE_EN_MASK 0x14f6 7839#define mmCM5_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 7840#define mmCM5_CM_SHAPER_RAMA_START_CNTL_B 0x14f7 7841#define mmCM5_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 7842#define mmCM5_CM_SHAPER_RAMA_START_CNTL_G 0x14f8 7843#define mmCM5_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 7844#define mmCM5_CM_SHAPER_RAMA_START_CNTL_R 0x14f9 7845#define mmCM5_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 7846#define mmCM5_CM_SHAPER_RAMA_END_CNTL_B 0x14fa 7847#define mmCM5_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 7848#define mmCM5_CM_SHAPER_RAMA_END_CNTL_G 0x14fb 7849#define mmCM5_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 7850#define mmCM5_CM_SHAPER_RAMA_END_CNTL_R 0x14fc 7851#define mmCM5_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 7852#define mmCM5_CM_SHAPER_RAMA_REGION_0_1 0x14fd 7853#define mmCM5_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 7854#define mmCM5_CM_SHAPER_RAMA_REGION_2_3 0x14fe 7855#define mmCM5_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 7856#define mmCM5_CM_SHAPER_RAMA_REGION_4_5 0x14ff 7857#define mmCM5_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 7858#define mmCM5_CM_SHAPER_RAMA_REGION_6_7 0x1500 7859#define mmCM5_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 7860#define mmCM5_CM_SHAPER_RAMA_REGION_8_9 0x1501 7861#define mmCM5_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 7862#define mmCM5_CM_SHAPER_RAMA_REGION_10_11 0x1502 7863#define mmCM5_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 7864#define mmCM5_CM_SHAPER_RAMA_REGION_12_13 0x1503 7865#define mmCM5_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 7866#define mmCM5_CM_SHAPER_RAMA_REGION_14_15 0x1504 7867#define mmCM5_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 7868#define mmCM5_CM_SHAPER_RAMA_REGION_16_17 0x1505 7869#define mmCM5_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 7870#define mmCM5_CM_SHAPER_RAMA_REGION_18_19 0x1506 7871#define mmCM5_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 7872#define mmCM5_CM_SHAPER_RAMA_REGION_20_21 0x1507 7873#define mmCM5_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 7874#define mmCM5_CM_SHAPER_RAMA_REGION_22_23 0x1508 7875#define mmCM5_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 7876#define mmCM5_CM_SHAPER_RAMA_REGION_24_25 0x1509 7877#define mmCM5_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 7878#define mmCM5_CM_SHAPER_RAMA_REGION_26_27 0x150a 7879#define mmCM5_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 7880#define mmCM5_CM_SHAPER_RAMA_REGION_28_29 0x150b 7881#define mmCM5_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 7882#define mmCM5_CM_SHAPER_RAMA_REGION_30_31 0x150c 7883#define mmCM5_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 7884#define mmCM5_CM_SHAPER_RAMA_REGION_32_33 0x150d 7885#define mmCM5_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 7886#define mmCM5_CM_SHAPER_RAMB_START_CNTL_B 0x150e 7887#define mmCM5_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 7888#define mmCM5_CM_SHAPER_RAMB_START_CNTL_G 0x150f 7889#define mmCM5_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 7890#define mmCM5_CM_SHAPER_RAMB_START_CNTL_R 0x1510 7891#define mmCM5_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 7892#define mmCM5_CM_SHAPER_RAMB_END_CNTL_B 0x1511 7893#define mmCM5_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 7894#define mmCM5_CM_SHAPER_RAMB_END_CNTL_G 0x1512 7895#define mmCM5_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 7896#define mmCM5_CM_SHAPER_RAMB_END_CNTL_R 0x1513 7897#define mmCM5_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 7898#define mmCM5_CM_SHAPER_RAMB_REGION_0_1 0x1514 7899#define mmCM5_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 7900#define mmCM5_CM_SHAPER_RAMB_REGION_2_3 0x1515 7901#define mmCM5_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 7902#define mmCM5_CM_SHAPER_RAMB_REGION_4_5 0x1516 7903#define mmCM5_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 7904#define mmCM5_CM_SHAPER_RAMB_REGION_6_7 0x1517 7905#define mmCM5_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 7906#define mmCM5_CM_SHAPER_RAMB_REGION_8_9 0x1518 7907#define mmCM5_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 7908#define mmCM5_CM_SHAPER_RAMB_REGION_10_11 0x1519 7909#define mmCM5_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 7910#define mmCM5_CM_SHAPER_RAMB_REGION_12_13 0x151a 7911#define mmCM5_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 7912#define mmCM5_CM_SHAPER_RAMB_REGION_14_15 0x151b 7913#define mmCM5_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 7914#define mmCM5_CM_SHAPER_RAMB_REGION_16_17 0x151c 7915#define mmCM5_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 7916#define mmCM5_CM_SHAPER_RAMB_REGION_18_19 0x151d 7917#define mmCM5_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 7918#define mmCM5_CM_SHAPER_RAMB_REGION_20_21 0x151e 7919#define mmCM5_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 7920#define mmCM5_CM_SHAPER_RAMB_REGION_22_23 0x151f 7921#define mmCM5_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 7922#define mmCM5_CM_SHAPER_RAMB_REGION_24_25 0x1520 7923#define mmCM5_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 7924#define mmCM5_CM_SHAPER_RAMB_REGION_26_27 0x1521 7925#define mmCM5_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 7926#define mmCM5_CM_SHAPER_RAMB_REGION_28_29 0x1522 7927#define mmCM5_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 7928#define mmCM5_CM_SHAPER_RAMB_REGION_30_31 0x1523 7929#define mmCM5_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 7930#define mmCM5_CM_SHAPER_RAMB_REGION_32_33 0x1524 7931#define mmCM5_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 7932#define mmCM5_CM_MEM_PWR_CTRL2 0x1525 7933#define mmCM5_CM_MEM_PWR_CTRL2_BASE_IDX 2 7934#define mmCM5_CM_MEM_PWR_STATUS2 0x1526 7935#define mmCM5_CM_MEM_PWR_STATUS2_BASE_IDX 2 7936#define mmCM5_CM_3DLUT_MODE 0x1527 7937#define mmCM5_CM_3DLUT_MODE_BASE_IDX 2 7938#define mmCM5_CM_3DLUT_INDEX 0x1528 7939#define mmCM5_CM_3DLUT_INDEX_BASE_IDX 2 7940#define mmCM5_CM_3DLUT_DATA 0x1529 7941#define mmCM5_CM_3DLUT_DATA_BASE_IDX 2 7942#define mmCM5_CM_3DLUT_DATA_30BIT 0x152a 7943#define mmCM5_CM_3DLUT_DATA_30BIT_BASE_IDX 2 7944#define mmCM5_CM_3DLUT_READ_WRITE_CONTROL 0x152b 7945#define mmCM5_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 7946#define mmCM5_CM_3DLUT_OUT_NORM_FACTOR 0x152c 7947#define mmCM5_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 7948#define mmCM5_CM_3DLUT_OUT_OFFSET_R 0x152d 7949#define mmCM5_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 7950#define mmCM5_CM_3DLUT_OUT_OFFSET_G 0x152e 7951#define mmCM5_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 7952#define mmCM5_CM_3DLUT_OUT_OFFSET_B 0x152f 7953#define mmCM5_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 7954 7955 7956// addressBlock: dce_dc_dpp5_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 7957// base address: 0x54ec 7958#define mmDC_PERFMON17_PERFCOUNTER_CNTL 0x153b 7959#define mmDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX 2 7960#define mmDC_PERFMON17_PERFCOUNTER_CNTL2 0x153c 7961#define mmDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX 2 7962#define mmDC_PERFMON17_PERFCOUNTER_STATE 0x153d 7963#define mmDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX 2 7964#define mmDC_PERFMON17_PERFMON_CNTL 0x153e 7965#define mmDC_PERFMON17_PERFMON_CNTL_BASE_IDX 2 7966#define mmDC_PERFMON17_PERFMON_CNTL2 0x153f 7967#define mmDC_PERFMON17_PERFMON_CNTL2_BASE_IDX 2 7968#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC 0x1540 7969#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 7970#define mmDC_PERFMON17_PERFMON_CVALUE_LOW 0x1541 7971#define mmDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX 2 7972#define mmDC_PERFMON17_PERFMON_HI 0x1542 7973#define mmDC_PERFMON17_PERFMON_HI_BASE_IDX 2 7974#define mmDC_PERFMON17_PERFMON_LOW 0x1543 7975#define mmDC_PERFMON17_PERFMON_LOW_BASE_IDX 2 7976 7977 7978// addressBlock: dce_dc_opp_fmt0_dispdec 7979// base address: 0x0 7980#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x183c 7981#define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 7982#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x183d 7983#define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 7984#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x183e 7985#define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 7986#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f 7987#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 7988#define mmFMT0_FMT_CONTROL 0x1840 7989#define mmFMT0_FMT_CONTROL_BASE_IDX 2 7990#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1841 7991#define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 7992#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1842 7993#define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 7994#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1843 7995#define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 7996#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1844 7997#define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 7998#define mmFMT0_FMT_CLAMP_CNTL 0x1845 7999#define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX 2 8000#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1846
8001#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8002#define mmFMT0_FMT_MAP420_MEMORY_CONTROL 0x1847 8003#define mmFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8004#define mmFMT0_FMT_422_CONTROL 0x1849 8005#define mmFMT0_FMT_422_CONTROL_BASE_IDX 2 8006 8007 8008// addressBlock: dce_dc_opp_dpg0_dispdec 8009// base address: 0x0 8010#define mmDPG0_DPG_CONTROL 0x1854 8011#define mmDPG0_DPG_CONTROL_BASE_IDX 2 8012#define mmDPG0_DPG_RAMP_CONTROL 0x1855 8013#define mmDPG0_DPG_RAMP_CONTROL_BASE_IDX 2 8014#define mmDPG0_DPG_DIMENSIONS 0x1856 8015#define mmDPG0_DPG_DIMENSIONS_BASE_IDX 2 8016#define mmDPG0_DPG_COLOUR_R_CR 0x1857 8017#define mmDPG0_DPG_COLOUR_R_CR_BASE_IDX 2 8018#define mmDPG0_DPG_COLOUR_G_Y 0x1858 8019#define mmDPG0_DPG_COLOUR_G_Y_BASE_IDX 2 8020#define mmDPG0_DPG_COLOUR_B_CB 0x1859 8021#define mmDPG0_DPG_COLOUR_B_CB_BASE_IDX 2 8022#define mmDPG0_DPG_OFFSET_SEGMENT 0x185a 8023#define mmDPG0_DPG_OFFSET_SEGMENT_BASE_IDX 2 8024#define mmDPG0_DPG_STATUS 0x185b 8025#define mmDPG0_DPG_STATUS_BASE_IDX 2 8026 8027 8028// addressBlock: dce_dc_opp_oppbuf0_dispdec 8029// base address: 0x0 8030#define mmOPPBUF0_OPPBUF_CONTROL 0x1884 8031#define mmOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2 8032#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885 8033#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8034#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886 8035#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8036#define mmOPPBUF0_OPPBUF_CONTROL1 0x1889 8037#define mmOPPBUF0_OPPBUF_CONTROL1_BASE_IDX 2 8038 8039 8040// addressBlock: dce_dc_opp_opp_pipe0_dispdec 8041// base address: 0x0 8042#define mmOPP_PIPE0_OPP_PIPE_CONTROL 0x188c 8043#define mmOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2 8044 8045 8046// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec 8047// base address: 0x0 8048#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891 8049#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8050#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892 8051#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2 8052#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893 8053#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8054#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894 8055#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8056#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895 8057#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8058 8059 8060// addressBlock: dce_dc_opp_fmt1_dispdec 8061// base address: 0x168 8062#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1896 8063#define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8064#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1897 8065#define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8066#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1898 8067#define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8068#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899 8069#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8070#define mmFMT1_FMT_CONTROL 0x189a 8071#define mmFMT1_FMT_CONTROL_BASE_IDX 2 8072#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x189b 8073#define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8074#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x189c 8075#define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8076#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x189d 8077#define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8078#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x189e 8079#define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8080#define mmFMT1_FMT_CLAMP_CNTL 0x189f 8081#define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX 2 8082#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a0 8083#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8084#define mmFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a1 8085#define mmFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8086#define mmFMT1_FMT_422_CONTROL 0x18a3 8087#define mmFMT1_FMT_422_CONTROL_BASE_IDX 2 8088 8089 8090// addressBlock: dce_dc_opp_dpg1_dispdec 8091// base address: 0x168 8092#define mmDPG1_DPG_CONTROL 0x18ae 8093#define mmDPG1_DPG_CONTROL_BASE_IDX 2 8094#define mmDPG1_DPG_RAMP_CONTROL 0x18af 8095#define mmDPG1_DPG_RAMP_CONTROL_BASE_IDX 2 8096#define mmDPG1_DPG_DIMENSIONS 0x18b0 8097#define mmDPG1_DPG_DIMENSIONS_BASE_IDX 2 8098#define mmDPG1_DPG_COLOUR_R_CR 0x18b1 8099#define mmDPG1_DPG_COLOUR_R_CR_BASE_IDX 2 8100#define mmDPG1_DPG_COLOUR_G_Y 0x18b2 8101#define mmDPG1_DPG_COLOUR_G_Y_BASE_IDX 2 8102#define mmDPG1_DPG_COLOUR_B_CB 0x18b3 8103#define mmDPG1_DPG_COLOUR_B_CB_BASE_IDX 2 8104#define mmDPG1_DPG_OFFSET_SEGMENT 0x18b4 8105#define mmDPG1_DPG_OFFSET_SEGMENT_BASE_IDX 2 8106#define mmDPG1_DPG_STATUS 0x18b5 8107#define mmDPG1_DPG_STATUS_BASE_IDX 2 8108 8109 8110// addressBlock: dce_dc_opp_oppbuf1_dispdec 8111// base address: 0x168 8112#define mmOPPBUF1_OPPBUF_CONTROL 0x18de 8113#define mmOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2 8114#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df 8115#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8116#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0 8117#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8118#define mmOPPBUF1_OPPBUF_CONTROL1 0x18e3 8119#define mmOPPBUF1_OPPBUF_CONTROL1_BASE_IDX 2 8120 8121 8122// addressBlock: dce_dc_opp_opp_pipe1_dispdec 8123// base address: 0x168 8124#define mmOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6 8125#define mmOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2 8126 8127 8128// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec 8129// base address: 0x168 8130#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb 8131#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8132#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec 8133#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2 8134#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed 8135#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8136#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee 8137#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8138#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef 8139#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8140 8141 8142// addressBlock: dce_dc_opp_fmt2_dispdec 8143// base address: 0x2d0 8144#define mmFMT2_FMT_CLAMP_COMPONENT_R 0x18f0 8145#define mmFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8146#define mmFMT2_FMT_CLAMP_COMPONENT_G 0x18f1 8147#define mmFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8148#define mmFMT2_FMT_CLAMP_COMPONENT_B 0x18f2 8149#define mmFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8150#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3 8151#define mmFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8152#define mmFMT2_FMT_CONTROL 0x18f4 8153#define mmFMT2_FMT_CONTROL_BASE_IDX 2 8154#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5 8155#define mmFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8156#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x18f6 8157#define mmFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8158#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x18f7 8159#define mmFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8160#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x18f8 8161#define mmFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8162#define mmFMT2_FMT_CLAMP_CNTL 0x18f9 8163#define mmFMT2_FMT_CLAMP_CNTL_BASE_IDX 2 8164#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fa 8165#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8166#define mmFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fb 8167#define mmFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8168#define mmFMT2_FMT_422_CONTROL 0x18fd 8169#define mmFMT2_FMT_422_CONTROL_BASE_IDX 2 8170 8171 8172 8173// addressBlock: dce_dc_opp_dpg2_dispdec 8174// base address: 0x2d0 8175#define mmDPG2_DPG_CONTROL 0x1908 8176#define mmDPG2_DPG_CONTROL_BASE_IDX 2 8177#define mmDPG2_DPG_RAMP_CONTROL 0x1909 8178#define mmDPG2_DPG_RAMP_CONTROL_BASE_IDX 2 8179#define mmDPG2_DPG_DIMENSIONS 0x190a 8180#define mmDPG2_DPG_DIMENSIONS_BASE_IDX 2 8181#define mmDPG2_DPG_COLOUR_R_CR 0x190b 8182#define mmDPG2_DPG_COLOUR_R_CR_BASE_IDX 2 8183#define mmDPG2_DPG_COLOUR_G_Y 0x190c 8184#define mmDPG2_DPG_COLOUR_G_Y_BASE_IDX 2 8185#define mmDPG2_DPG_COLOUR_B_CB 0x190d 8186#define mmDPG2_DPG_COLOUR_B_CB_BASE_IDX 2 8187#define mmDPG2_DPG_OFFSET_SEGMENT 0x190e 8188#define mmDPG2_DPG_OFFSET_SEGMENT_BASE_IDX 2 8189#define mmDPG2_DPG_STATUS 0x190f 8190#define mmDPG2_DPG_STATUS_BASE_IDX 2 8191 8192 8193// addressBlock: dce_dc_opp_oppbuf2_dispdec 8194// base address: 0x2d0 8195#define mmOPPBUF2_OPPBUF_CONTROL 0x1938 8196#define mmOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2 8197#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939 8198#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8199#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a 8200#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8201#define mmOPPBUF2_OPPBUF_CONTROL1 0x193d 8202#define mmOPPBUF2_OPPBUF_CONTROL1_BASE_IDX 2 8203 8204 8205// addressBlock: dce_dc_opp_opp_pipe2_dispdec 8206// base address: 0x2d0 8207#define mmOPP_PIPE2_OPP_PIPE_CONTROL 0x1940 8208#define mmOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2 8209 8210 8211// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec 8212// base address: 0x2d0 8213#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1945 8214#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8215#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1946 8216#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2 8217#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 0x1947 8218#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8219#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 0x1948 8220#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8221#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 0x1949 8222#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8223 8224 8225// addressBlock: dce_dc_opp_fmt3_dispdec 8226// base address: 0x438 8227#define mmFMT3_FMT_CLAMP_COMPONENT_R 0x194a 8228#define mmFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8229#define mmFMT3_FMT_CLAMP_COMPONENT_G 0x194b 8230#define mmFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8231#define mmFMT3_FMT_CLAMP_COMPONENT_B 0x194c 8232#define mmFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8233#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d 8234#define mmFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8235#define mmFMT3_FMT_CONTROL 0x194e 8236#define mmFMT3_FMT_CONTROL_BASE_IDX 2 8237#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x194f 8238#define mmFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8239#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x1950 8240#define mmFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8241#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x1951 8242#define mmFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8243#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x1952 8244#define mmFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8245#define mmFMT3_FMT_CLAMP_CNTL 0x1953 8246#define mmFMT3_FMT_CLAMP_CNTL_BASE_IDX 2 8247#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1954 8248#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8249#define mmFMT3_FMT_MAP420_MEMORY_CONTROL 0x1955 8250#define mmFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8251#define mmFMT3_FMT_422_CONTROL 0x1957 8252#define mmFMT3_FMT_422_CONTROL_BASE_IDX 2 8253 8254 8255// addressBlock: dce_dc_opp_dpg3_dispdec 8256// base address: 0x438 8257#define mmDPG3_DPG_CONTROL 0x1962 8258#define mmDPG3_DPG_CONTROL_BASE_IDX 2 8259#define mmDPG3_DPG_RAMP_CONTROL 0x1963 8260#define mmDPG3_DPG_RAMP_CONTROL_BASE_IDX 2 8261#define mmDPG3_DPG_DIMENSIONS 0x1964 8262#define mmDPG3_DPG_DIMENSIONS_BASE_IDX 2 8263#define mmDPG3_DPG_COLOUR_R_CR 0x1965 8264#define mmDPG3_DPG_COLOUR_R_CR_BASE_IDX 2 8265#define mmDPG3_DPG_COLOUR_G_Y 0x1966 8266#define mmDPG3_DPG_COLOUR_G_Y_BASE_IDX 2 8267#define mmDPG3_DPG_COLOUR_B_CB 0x1967 8268#define mmDPG3_DPG_COLOUR_B_CB_BASE_IDX 2 8269#define mmDPG3_DPG_OFFSET_SEGMENT 0x1968 8270#define mmDPG3_DPG_OFFSET_SEGMENT_BASE_IDX 2 8271#define mmDPG3_DPG_STATUS 0x1969 8272#define mmDPG3_DPG_STATUS_BASE_IDX 2 8273 8274 8275// addressBlock: dce_dc_opp_oppbuf3_dispdec 8276// base address: 0x438 8277#define mmOPPBUF3_OPPBUF_CONTROL 0x1992 8278#define mmOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2 8279#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993 8280#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8281#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994 8282#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8283#define mmOPPBUF3_OPPBUF_CONTROL1 0x1997 8284#define mmOPPBUF3_OPPBUF_CONTROL1_BASE_IDX 2 8285 8286 8287// addressBlock: dce_dc_opp_opp_pipe3_dispdec 8288// base address: 0x438 8289#define mmOPP_PIPE3_OPP_PIPE_CONTROL 0x199a 8290#define mmOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2 8291 8292// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec 8293// base address: 0x438 8294#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199f 8295#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8296#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x19a0 8297#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2 8298#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 0x19a1 8299#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8300#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 0x19a2 8301#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8302#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 0x19a3 8303#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8304 8305 8306// addressBlock: dce_dc_opp_fmt4_dispdec 8307// base address: 0x5a0 8308#define mmFMT4_FMT_CLAMP_COMPONENT_R 0x19a4 8309#define mmFMT4_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8310#define mmFMT4_FMT_CLAMP_COMPONENT_G 0x19a5 8311#define mmFMT4_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8312#define mmFMT4_FMT_CLAMP_COMPONENT_B 0x19a6 8313#define mmFMT4_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8314#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x19a7 8315#define mmFMT4_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8316#define mmFMT4_FMT_CONTROL 0x19a8 8317#define mmFMT4_FMT_CONTROL_BASE_IDX 2 8318#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x19a9 8319#define mmFMT4_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8320#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x19aa 8321#define mmFMT4_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8322#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x19ab 8323#define mmFMT4_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8324#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x19ac 8325#define mmFMT4_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8326#define mmFMT4_FMT_CLAMP_CNTL 0x19ad 8327#define mmFMT4_FMT_CLAMP_CNTL_BASE_IDX 2 8328#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x19ae 8329#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8330#define mmFMT4_FMT_MAP420_MEMORY_CONTROL 0x19af 8331#define mmFMT4_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8332#define mmFMT4_FMT_422_CONTROL 0x19b1 8333#define mmFMT4_FMT_422_CONTROL_BASE_IDX 2 8334 8335 8336 8337// addressBlock: dce_dc_opp_dpg4_dispdec 8338// base address: 0x5a0 8339#define mmDPG4_DPG_CONTROL 0x19bc 8340#define mmDPG4_DPG_CONTROL_BASE_IDX 2 8341#define mmDPG4_DPG_RAMP_CONTROL 0x19bd 8342#define mmDPG4_DPG_RAMP_CONTROL_BASE_IDX 2 8343#define mmDPG4_DPG_DIMENSIONS 0x19be 8344#define mmDPG4_DPG_DIMENSIONS_BASE_IDX 2 8345#define mmDPG4_DPG_COLOUR_R_CR 0x19bf 8346#define mmDPG4_DPG_COLOUR_R_CR_BASE_IDX 2 8347#define mmDPG4_DPG_COLOUR_G_Y 0x19c0 8348#define mmDPG4_DPG_COLOUR_G_Y_BASE_IDX 2 8349#define mmDPG4_DPG_COLOUR_B_CB 0x19c1 8350#define mmDPG4_DPG_COLOUR_B_CB_BASE_IDX 2 8351#define mmDPG4_DPG_OFFSET_SEGMENT 0x19c2 8352#define mmDPG4_DPG_OFFSET_SEGMENT_BASE_IDX 2 8353#define mmDPG4_DPG_STATUS 0x19c3 8354#define mmDPG4_DPG_STATUS_BASE_IDX 2 8355 8356 8357// addressBlock: dce_dc_opp_oppbuf4_dispdec 8358// base address: 0x5a0 8359#define mmOPPBUF4_OPPBUF_CONTROL 0x19ec 8360#define mmOPPBUF4_OPPBUF_CONTROL_BASE_IDX 2 8361#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0 0x19ed 8362#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8363#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1 0x19ee 8364#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8365#define mmOPPBUF4_OPPBUF_CONTROL1 0x19f1 8366#define mmOPPBUF4_OPPBUF_CONTROL1_BASE_IDX 2 8367 8368 8369// addressBlock: dce_dc_opp_opp_pipe4_dispdec 8370// base address: 0x5a0 8371#define mmOPP_PIPE4_OPP_PIPE_CONTROL 0x19f4 8372#define mmOPP_PIPE4_OPP_PIPE_CONTROL_BASE_IDX 2 8373 8374// addressBlock: dce_dc_opp_opp_pipe_crc4_dispdec 8375// base address: 0x5a0 8376#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL 0x19f9 8377#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8378#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK 0x19fa 8379#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK_BASE_IDX 2 8380#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0 0x19fb 8381#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8382#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1 0x19fc 8383#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8384#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2 0x19fd 8385#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8386 8387 8388// addressBlock: dce_dc_opp_fmt5_dispdec 8389// base address: 0x708 8390#define mmFMT5_FMT_CLAMP_COMPONENT_R 0x19fe 8391#define mmFMT5_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8392#define mmFMT5_FMT_CLAMP_COMPONENT_G 0x19ff 8393#define mmFMT5_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8394#define mmFMT5_FMT_CLAMP_COMPONENT_B 0x1a00 8395#define mmFMT5_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8396#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x1a01 8397#define mmFMT5_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8398#define mmFMT5_FMT_CONTROL 0x1a02 8399#define mmFMT5_FMT_CONTROL_BASE_IDX 2 8400#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x1a03 8401#define mmFMT5_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8402#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x1a04 8403#define mmFMT5_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8404#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x1a05 8405#define mmFMT5_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8406#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x1a06 8407#define mmFMT5_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8408#define mmFMT5_FMT_CLAMP_CNTL 0x1a07 8409#define mmFMT5_FMT_CLAMP_CNTL_BASE_IDX 2 8410#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1a08 8411#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8412#define mmFMT5_FMT_MAP420_MEMORY_CONTROL 0x1a09 8413#define mmFMT5_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8414#define mmFMT5_FMT_422_CONTROL 0x1a0b 8415#define mmFMT5_FMT_422_CONTROL_BASE_IDX 2 8416 8417 8418// addressBlock: dce_dc_opp_dpg5_dispdec 8419// base address: 0x708 8420#define mmDPG5_DPG_CONTROL 0x1a16 8421#define mmDPG5_DPG_CONTROL_BASE_IDX 2 8422#define mmDPG5_DPG_RAMP_CONTROL 0x1a17 8423#define mmDPG5_DPG_RAMP_CONTROL_BASE_IDX 2 8424#define mmDPG5_DPG_DIMENSIONS 0x1a18 8425#define mmDPG5_DPG_DIMENSIONS_BASE_IDX 2 8426#define mmDPG5_DPG_COLOUR_R_CR 0x1a19 8427#define mmDPG5_DPG_COLOUR_R_CR_BASE_IDX 2 8428#define mmDPG5_DPG_COLOUR_G_Y 0x1a1a 8429#define mmDPG5_DPG_COLOUR_G_Y_BASE_IDX 2 8430#define mmDPG5_DPG_COLOUR_B_CB 0x1a1b 8431#define mmDPG5_DPG_COLOUR_B_CB_BASE_IDX 2 8432#define mmDPG5_DPG_OFFSET_SEGMENT 0x1a1c 8433#define mmDPG5_DPG_OFFSET_SEGMENT_BASE_IDX 2 8434#define mmDPG5_DPG_STATUS 0x1a1d 8435#define mmDPG5_DPG_STATUS_BASE_IDX 2 8436 8437 8438// addressBlock: dce_dc_opp_oppbuf5_dispdec 8439// base address: 0x708 8440#define mmOPPBUF5_OPPBUF_CONTROL 0x1a46 8441#define mmOPPBUF5_OPPBUF_CONTROL_BASE_IDX 2 8442#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0 0x1a47 8443#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8444#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1 0x1a48 8445#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8446#define mmOPPBUF5_OPPBUF_CONTROL1 0x1a4b 8447#define mmOPPBUF5_OPPBUF_CONTROL1_BASE_IDX 2 8448 8449 8450// addressBlock: dce_dc_opp_opp_pipe5_dispdec 8451// base address: 0x708 8452#define mmOPP_PIPE5_OPP_PIPE_CONTROL 0x1a4e 8453#define mmOPP_PIPE5_OPP_PIPE_CONTROL_BASE_IDX 2 8454 8455 8456// addressBlock: dce_dc_opp_opp_pipe_crc5_dispdec 8457// base address: 0x708 8458#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL 0x1a53 8459#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8460#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK 0x1a54 8461#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK_BASE_IDX 2 8462#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0 0x1a55 8463#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8464#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1 0x1a56 8465#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8466#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2 0x1a57 8467#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8468 8469 8470// addressBlock: dce_dc_opp_opp_top_dispdec 8471// base address: 0x0 8472#define mmOPP_TOP_CLK_CONTROL 0x1a5e 8473#define mmOPP_TOP_CLK_CONTROL_BASE_IDX 2 8474#define mmOPP_ABM_CONTROL 0x1a60 8475#define mmOPP_ABM_CONTROL_BASE_IDX 2 8476 8477 8478// addressBlock: dce_dc_opp_dscrm0_dispdec 8479// base address: 0x0 8480#define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG 0x1a64 8481#define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8482 8483 8484// addressBlock: dce_dc_opp_dscrm1_dispdec 8485// base address: 0x4 8486#define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG 0x1a65 8487#define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8488 8489 8490// addressBlock: dce_dc_opp_dscrm2_dispdec 8491// base address: 0x8 8492#define mmDSCRM2_DSCRM_DSC_FORWARD_CONFIG 0x1a66 8493#define mmDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8494 8495 8496// addressBlock: dce_dc_opp_dscrm3_dispdec 8497// base address: 0xc 8498#define mmDSCRM3_DSCRM_DSC_FORWARD_CONFIG 0x1a67 8499#define mmDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8500 8501 8502// addressBlock: dce_dc_opp_dscrm4_dispdec 8503// base address: 0x10 8504#define mmDSCRM4_DSCRM_DSC_FORWARD_CONFIG 0x1a68 8505#define mmDSCRM4_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8506 8507 8508// addressBlock: dce_dc_opp_dscrm5_dispdec 8509// base address: 0x14 8510#define mmDSCRM5_DSCRM_DSC_FORWARD_CONFIG 0x1a69 8511#define mmDSCRM5_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8512 8513 8514// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec 8515// base address: 0x6af8 8516#define mmDC_PERFMON18_PERFCOUNTER_CNTL 0x1abe 8517#define mmDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX 2 8518#define mmDC_PERFMON18_PERFCOUNTER_CNTL2 0x1abf 8519#define mmDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX 2 8520#define mmDC_PERFMON18_PERFCOUNTER_STATE 0x1ac0 8521#define mmDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX 2 8522#define mmDC_PERFMON18_PERFMON_CNTL 0x1ac1 8523#define mmDC_PERFMON18_PERFMON_CNTL_BASE_IDX 2 8524#define mmDC_PERFMON18_PERFMON_CNTL2 0x1ac2 8525#define mmDC_PERFMON18_PERFMON_CNTL2_BASE_IDX 2 8526#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC 0x1ac3 8527#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 8528#define mmDC_PERFMON18_PERFMON_CVALUE_LOW 0x1ac4 8529#define mmDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX 2 8530#define mmDC_PERFMON18_PERFMON_HI 0x1ac5 8531#define mmDC_PERFMON18_PERFMON_HI_BASE_IDX 2 8532#define mmDC_PERFMON18_PERFMON_LOW 0x1ac6 8533#define mmDC_PERFMON18_PERFMON_LOW_BASE_IDX 2 8534 8535 8536// addressBlock: dce_dc_optc_odm0_dispdec 8537// base address: 0x0 8538#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca 8539#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8540#define mmODM0_OPTC_DATA_SOURCE_SELECT 0x1acb 8541#define mmODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8542#define mmODM0_OPTC_DATA_FORMAT_CONTROL 0x1acc 8543#define mmODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8544#define mmODM0_OPTC_BYTES_PER_PIXEL 0x1acd 8545#define mmODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8546#define mmODM0_OPTC_WIDTH_CONTROL 0x1ace 8547#define mmODM0_OPTC_WIDTH_CONTROL_BASE_IDX 2 8548#define mmODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acf 8549#define mmODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8550#define mmODM0_OPTC_MEMORY_CONFIG 0x1ad0 8551#define mmODM0_OPTC_MEMORY_CONFIG_BASE_IDX 2 8552#define mmODM0_OPTC_INPUT_SPARE_REGISTER 0x1ad1 8553#define mmODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8554 8555 8556// addressBlock: dce_dc_optc_odm1_dispdec 8557// base address: 0x40 8558#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada 8559#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8560#define mmODM1_OPTC_DATA_SOURCE_SELECT 0x1adb 8561#define mmODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8562#define mmODM1_OPTC_DATA_FORMAT_CONTROL 0x1adc 8563#define mmODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8564#define mmODM1_OPTC_BYTES_PER_PIXEL 0x1add 8565#define mmODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8566#define mmODM1_OPTC_WIDTH_CONTROL 0x1ade 8567#define mmODM1_OPTC_WIDTH_CONTROL_BASE_IDX 2 8568#define mmODM1_OPTC_INPUT_CLOCK_CONTROL 0x1adf 8569#define mmODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8570#define mmODM1_OPTC_MEMORY_CONFIG 0x1ae0 8571#define mmODM1_OPTC_MEMORY_CONFIG_BASE_IDX 2 8572#define mmODM1_OPTC_INPUT_SPARE_REGISTER 0x1ae1 8573#define mmODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8574 8575 8576// addressBlock: dce_dc_optc_odm2_dispdec 8577// base address: 0x80 8578#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea 8579#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8580#define mmODM2_OPTC_DATA_SOURCE_SELECT 0x1aeb 8581#define mmODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8582#define mmODM2_OPTC_DATA_FORMAT_CONTROL 0x1aec 8583#define mmODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8584#define mmODM2_OPTC_BYTES_PER_PIXEL 0x1aed 8585#define mmODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8586#define mmODM2_OPTC_WIDTH_CONTROL 0x1aee 8587#define mmODM2_OPTC_WIDTH_CONTROL_BASE_IDX 2 8588#define mmODM2_OPTC_INPUT_CLOCK_CONTROL 0x1aef 8589#define mmODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8590#define mmODM2_OPTC_MEMORY_CONFIG 0x1af0 8591#define mmODM2_OPTC_MEMORY_CONFIG_BASE_IDX 2 8592#define mmODM2_OPTC_INPUT_SPARE_REGISTER 0x1af1 8593#define mmODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8594 8595 8596// addressBlock: dce_dc_optc_odm3_dispdec 8597// base address: 0xc0 8598#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa 8599#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8600#define mmODM3_OPTC_DATA_SOURCE_SELECT 0x1afb 8601#define mmODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8602#define mmODM3_OPTC_DATA_FORMAT_CONTROL 0x1afc 8603#define mmODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8604#define mmODM3_OPTC_BYTES_PER_PIXEL 0x1afd 8605#define mmODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8606#define mmODM3_OPTC_WIDTH_CONTROL 0x1afe 8607#define mmODM3_OPTC_WIDTH_CONTROL_BASE_IDX 2 8608#define mmODM3_OPTC_INPUT_CLOCK_CONTROL 0x1aff 8609#define mmODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8610#define mmODM3_OPTC_MEMORY_CONFIG 0x1b00 8611#define mmODM3_OPTC_MEMORY_CONFIG_BASE_IDX 2 8612#define mmODM3_OPTC_INPUT_SPARE_REGISTER 0x1b01 8613#define mmODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8614 8615 8616// addressBlock: dce_dc_optc_odm4_dispdec 8617// base address: 0x100 8618#define mmODM4_OPTC_INPUT_GLOBAL_CONTROL 0x1b0a 8619#define mmODM4_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8620#define mmODM4_OPTC_DATA_SOURCE_SELECT 0x1b0b 8621#define mmODM4_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8622#define mmODM4_OPTC_DATA_FORMAT_CONTROL 0x1b0c 8623#define mmODM4_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8624#define mmODM4_OPTC_BYTES_PER_PIXEL 0x1b0d 8625#define mmODM4_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8626#define mmODM4_OPTC_WIDTH_CONTROL 0x1b0e 8627#define mmODM4_OPTC_WIDTH_CONTROL_BASE_IDX 2 8628#define mmODM4_OPTC_INPUT_CLOCK_CONTROL 0x1b0f 8629#define mmODM4_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8630#define mmODM4_OPTC_MEMORY_CONFIG 0x1b10 8631#define mmODM4_OPTC_MEMORY_CONFIG_BASE_IDX 2 8632#define mmODM4_OPTC_INPUT_SPARE_REGISTER 0x1b11 8633#define mmODM4_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8634 8635 8636// addressBlock: dce_dc_optc_odm5_dispdec 8637// base address: 0x140 8638#define mmODM5_OPTC_INPUT_GLOBAL_CONTROL 0x1b1a 8639#define mmODM5_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8640#define mmODM5_OPTC_DATA_SOURCE_SELECT 0x1b1b 8641#define mmODM5_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8642#define mmODM5_OPTC_DATA_FORMAT_CONTROL 0x1b1c 8643#define mmODM5_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8644#define mmODM5_OPTC_BYTES_PER_PIXEL 0x1b1d 8645#define mmODM5_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8646#define mmODM5_OPTC_WIDTH_CONTROL 0x1b1e 8647#define mmODM5_OPTC_WIDTH_CONTROL_BASE_IDX 2 8648#define mmODM5_OPTC_INPUT_CLOCK_CONTROL 0x1b1f 8649#define mmODM5_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8650#define mmODM5_OPTC_MEMORY_CONFIG 0x1b20 8651#define mmODM5_OPTC_MEMORY_CONFIG_BASE_IDX 2 8652#define mmODM5_OPTC_INPUT_SPARE_REGISTER 0x1b21 8653#define mmODM5_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8654 8655 8656// addressBlock: dce_dc_optc_otg0_dispdec 8657// base address: 0x0 8658#define mmOTG0_OTG_H_TOTAL 0x1b2a 8659#define mmOTG0_OTG_H_TOTAL_BASE_IDX 2 8660#define mmOTG0_OTG_H_BLANK_START_END 0x1b2b 8661#define mmOTG0_OTG_H_BLANK_START_END_BASE_IDX 2 8662#define mmOTG0_OTG_H_SYNC_A 0x1b2c 8663#define mmOTG0_OTG_H_SYNC_A_BASE_IDX 2 8664#define mmOTG0_OTG_H_SYNC_A_CNTL 0x1b2d 8665#define mmOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2 8666#define mmOTG0_OTG_H_TIMING_CNTL 0x1b2e 8667#define mmOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2 8668#define mmOTG0_OTG_V_TOTAL 0x1b2f 8669#define mmOTG0_OTG_V_TOTAL_BASE_IDX 2 8670#define mmOTG0_OTG_V_TOTAL_MIN 0x1b30 8671#define mmOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2 8672#define mmOTG0_OTG_V_TOTAL_MAX 0x1b31 8673#define mmOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2 8674#define mmOTG0_OTG_V_TOTAL_MID 0x1b32 8675#define mmOTG0_OTG_V_TOTAL_MID_BASE_IDX 2 8676#define mmOTG0_OTG_V_TOTAL_CONTROL 0x1b33 8677#define mmOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2 8678#define mmOTG0_OTG_V_TOTAL_INT_STATUS 0x1b34 8679#define mmOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 8680#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b35 8681#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 8682#define mmOTG0_OTG_V_BLANK_START_END 0x1b36 8683#define mmOTG0_OTG_V_BLANK_START_END_BASE_IDX 2 8684#define mmOTG0_OTG_V_SYNC_A 0x1b37 8685#define mmOTG0_OTG_V_SYNC_A_BASE_IDX 2 8686#define mmOTG0_OTG_V_SYNC_A_CNTL 0x1b38 8687#define mmOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2 8688#define mmOTG0_OTG_TRIGA_CNTL 0x1b39 8689#define mmOTG0_OTG_TRIGA_CNTL_BASE_IDX 2 8690#define mmOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3a 8691#define mmOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 8692#define mmOTG0_OTG_TRIGB_CNTL 0x1b3b 8693#define mmOTG0_OTG_TRIGB_CNTL_BASE_IDX 2 8694#define mmOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3c 8695#define mmOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 8696#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3d 8697#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 8698#define mmOTG0_OTG_FLOW_CONTROL 0x1b3e 8699#define mmOTG0_OTG_FLOW_CONTROL_BASE_IDX 2 8700#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b3f 8701#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 8702#define mmOTG0_OTG_CONTROL 0x1b41 8703#define mmOTG0_OTG_CONTROL_BASE_IDX 2 8704#define mmOTG0_OTG_BLANK_CONTROL 0x1b42 8705#define mmOTG0_OTG_BLANK_CONTROL_BASE_IDX 2 8706#define mmOTG0_OTG_INTERLACE_CONTROL 0x1b44 8707#define mmOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2 8708#define mmOTG0_OTG_INTERLACE_STATUS 0x1b45 8709#define mmOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2 8710#define mmOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47 8711#define mmOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 8712#define mmOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48 8713#define mmOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 8714#define mmOTG0_OTG_STATUS 0x1b49 8715#define mmOTG0_OTG_STATUS_BASE_IDX 2 8716#define mmOTG0_OTG_STATUS_POSITION 0x1b4a 8717#define mmOTG0_OTG_STATUS_POSITION_BASE_IDX 2 8718#define mmOTG0_OTG_NOM_VERT_POSITION 0x1b4b 8719#define mmOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2 8720#define mmOTG0_OTG_STATUS_FRAME_COUNT 0x1b4c 8721#define mmOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 8722#define mmOTG0_OTG_STATUS_VF_COUNT 0x1b4d 8723#define mmOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2 8724#define mmOTG0_OTG_STATUS_HV_COUNT 0x1b4e 8725#define mmOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2 8726#define mmOTG0_OTG_COUNT_CONTROL 0x1b4f 8727#define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX 2 8728#define mmOTG0_OTG_COUNT_RESET 0x1b50 8729#define mmOTG0_OTG_COUNT_RESET_BASE_IDX 2 8730#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b51 8731#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 8732#define mmOTG0_OTG_VERT_SYNC_CONTROL 0x1b52 8733#define mmOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 8734#define mmOTG0_OTG_STEREO_STATUS 0x1b53 8735#define mmOTG0_OTG_STEREO_STATUS_BASE_IDX 2 8736#define mmOTG0_OTG_STEREO_CONTROL 0x1b54 8737#define mmOTG0_OTG_STEREO_CONTROL_BASE_IDX 2 8738#define mmOTG0_OTG_SNAPSHOT_STATUS 0x1b55 8739#define mmOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2 8740#define mmOTG0_OTG_SNAPSHOT_CONTROL 0x1b56 8741#define mmOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 8742#define mmOTG0_OTG_SNAPSHOT_POSITION 0x1b57 8743#define mmOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2 8744#define mmOTG0_OTG_SNAPSHOT_FRAME 0x1b58 8745#define mmOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2 8746#define mmOTG0_OTG_INTERRUPT_CONTROL 0x1b59 8747#define mmOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2 8748#define mmOTG0_OTG_UPDATE_LOCK 0x1b5a 8749#define mmOTG0_OTG_UPDATE_LOCK_BASE_IDX 2 8750#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5b 8751#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 8752#define mmOTG0_OTG_MASTER_EN 0x1b5c 8753#define mmOTG0_OTG_MASTER_EN_BASE_IDX 2 8754#define mmOTG0_OTG_BLANK_DATA_COLOR 0x1b5e 8755#define mmOTG0_OTG_BLANK_DATA_COLOR_BASE_IDX 2 8756#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT 0x1b5f 8757#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 8758#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b62 8759#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 8760#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b63 8761#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 8762#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b64 8763#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 8764#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b65 8765#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 8766#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b66 8767#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 8768#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b67 8769#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 8770#define mmOTG0_OTG_CRC_CNTL 0x1b68 8771#define mmOTG0_OTG_CRC_CNTL_BASE_IDX 2 8772#define mmOTG0_OTG_CRC_CNTL2 0x1b69 8773#define mmOTG0_OTG_CRC_CNTL2_BASE_IDX 2 8774#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b6a 8775#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 8776#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b6b 8777#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 8778#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b6c 8779#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 8780#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b6d 8781#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 8782#define mmOTG0_OTG_CRC0_DATA_RG 0x1b6e 8783#define mmOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2 8784#define mmOTG0_OTG_CRC0_DATA_B 0x1b6f 8785#define mmOTG0_OTG_CRC0_DATA_B_BASE_IDX 2 8786#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b70 8787#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 8788#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b71 8789#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 8790#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b72 8791#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 8792#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b73 8793#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 8794#define mmOTG0_OTG_CRC1_DATA_RG 0x1b74 8795#define mmOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2 8796#define mmOTG0_OTG_CRC1_DATA_B 0x1b75 8797#define mmOTG0_OTG_CRC1_DATA_B_BASE_IDX 2 8798#define mmOTG0_OTG_CRC2_DATA_RG 0x1b76 8799#define mmOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2 8800#define mmOTG0_OTG_CRC2_DATA_B 0x1b77 8801#define mmOTG0_OTG_CRC2_DATA_B_BASE_IDX 2 8802#define mmOTG0_OTG_CRC3_DATA_RG 0x1b78 8803#define mmOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2 8804#define mmOTG0_OTG_CRC3_DATA_B 0x1b79 8805#define mmOTG0_OTG_CRC3_DATA_B_BASE_IDX 2 8806#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b7a 8807#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 8808#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b7b 8809#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 8810#define mmOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b82 8811#define mmOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 8812#define mmOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b83 8813#define mmOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 8814#define mmOTG0_OTG_GSL_VSYNC_GAP 0x1b84 8815#define mmOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2 8816#define mmOTG0_OTG_MASTER_UPDATE_MODE 0x1b85 8817#define mmOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 8818#define mmOTG0_OTG_CLOCK_CONTROL 0x1b86 8819#define mmOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2 8820#define mmOTG0_OTG_VSTARTUP_PARAM 0x1b87 8821#define mmOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2 8822#define mmOTG0_OTG_VUPDATE_PARAM 0x1b88 8823#define mmOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2 8824#define mmOTG0_OTG_VREADY_PARAM 0x1b89 8825#define mmOTG0_OTG_VREADY_PARAM_BASE_IDX 2 8826#define mmOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b8a 8827#define mmOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 8828#define mmOTG0_OTG_MASTER_UPDATE_LOCK 0x1b8b 8829#define mmOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 8830#define mmOTG0_OTG_GSL_CONTROL 0x1b8c 8831#define mmOTG0_OTG_GSL_CONTROL_BASE_IDX 2 8832#define mmOTG0_OTG_GSL_WINDOW_X 0x1b8d 8833#define mmOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2 8834#define mmOTG0_OTG_GSL_WINDOW_Y 0x1b8e 8835#define mmOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2 8836#define mmOTG0_OTG_VUPDATE_KEEPOUT 0x1b8f 8837#define mmOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 8838#define mmOTG0_OTG_GLOBAL_CONTROL0 0x1b90 8839#define mmOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2 8840#define mmOTG0_OTG_GLOBAL_CONTROL1 0x1b91 8841#define mmOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2 8842#define mmOTG0_OTG_GLOBAL_CONTROL2 0x1b92 8843#define mmOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2 8844#define mmOTG0_OTG_GLOBAL_CONTROL3 0x1b93 8845#define mmOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2 8846#define mmOTG0_OTG_GLOBAL_CONTROL4 0x1b94 8847#define mmOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX 2 8848#define mmOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b95 8849#define mmOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 8850#define mmOTG0_OTG_MANUAL_FLOW_CONTROL 0x1b96 8851#define mmOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 8852#define mmOTG0_OTG_DRR_TIMING_INT_STATUS 0x1b97 8853#define mmOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 8854#define mmOTG0_OTG_DRR_V_TOTAL_REACH_RANGE 0x1b98 8855#define mmOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 8856#define mmOTG0_OTG_DRR_V_TOTAL_CHANGE 0x1b99 8857#define mmOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 8858#define mmOTG0_OTG_DRR_TRIGGER_WINDOW 0x1b9a 8859#define mmOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 8860#define mmOTG0_OTG_DRR_CONTROL 0x1b9b 8861#define mmOTG0_OTG_DRR_CONTROL_BASE_IDX 2 8862#define mmOTG0_OTG_M_CONST_DTO0 0x1b9c 8863#define mmOTG0_OTG_M_CONST_DTO0_BASE_IDX 2 8864#define mmOTG0_OTG_M_CONST_DTO1 0x1b9d 8865#define mmOTG0_OTG_M_CONST_DTO1_BASE_IDX 2 8866#define mmOTG0_OTG_REQUEST_CONTROL 0x1b9e 8867#define mmOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2 8868#define mmOTG0_OTG_DSC_START_POSITION 0x1b9f 8869#define mmOTG0_OTG_DSC_START_POSITION_BASE_IDX 2 8870#define mmOTG0_OTG_PIPE_UPDATE_STATUS 0x1ba0 8871#define mmOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 8872#define mmOTG0_OTG_SPARE_REGISTER 0x1ba2 8873#define mmOTG0_OTG_SPARE_REGISTER_BASE_IDX 2 8874 8875 8876// addressBlock: dce_dc_optc_otg1_dispdec 8877// base address: 0x200 8878#define mmOTG1_OTG_H_TOTAL 0x1baa 8879#define mmOTG1_OTG_H_TOTAL_BASE_IDX 2 8880#define mmOTG1_OTG_H_BLANK_START_END 0x1bab 8881#define mmOTG1_OTG_H_BLANK_START_END_BASE_IDX 2 8882#define mmOTG1_OTG_H_SYNC_A 0x1bac 8883#define mmOTG1_OTG_H_SYNC_A_BASE_IDX 2 8884#define mmOTG1_OTG_H_SYNC_A_CNTL 0x1bad 8885#define mmOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2 8886#define mmOTG1_OTG_H_TIMING_CNTL 0x1bae 8887#define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2 8888#define mmOTG1_OTG_V_TOTAL 0x1baf 8889#define mmOTG1_OTG_V_TOTAL_BASE_IDX 2 8890#define mmOTG1_OTG_V_TOTAL_MIN 0x1bb0 8891#define mmOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2 8892#define mmOTG1_OTG_V_TOTAL_MAX 0x1bb1 8893#define mmOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2 8894#define mmOTG1_OTG_V_TOTAL_MID 0x1bb2 8895#define mmOTG1_OTG_V_TOTAL_MID_BASE_IDX 2 8896#define mmOTG1_OTG_V_TOTAL_CONTROL 0x1bb3 8897#define mmOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2 8898#define mmOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb4 8899#define mmOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 8900#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb5 8901#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 8902#define mmOTG1_OTG_V_BLANK_START_END 0x1bb6 8903#define mmOTG1_OTG_V_BLANK_START_END_BASE_IDX 2 8904#define mmOTG1_OTG_V_SYNC_A 0x1bb7 8905#define mmOTG1_OTG_V_SYNC_A_BASE_IDX 2 8906#define mmOTG1_OTG_V_SYNC_A_CNTL 0x1bb8 8907#define mmOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2 8908#define mmOTG1_OTG_TRIGA_CNTL 0x1bb9 8909#define mmOTG1_OTG_TRIGA_CNTL_BASE_IDX 2 8910#define mmOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bba 8911#define mmOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 8912#define mmOTG1_OTG_TRIGB_CNTL 0x1bbb 8913#define mmOTG1_OTG_TRIGB_CNTL_BASE_IDX 2 8914#define mmOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbc 8915#define mmOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 8916#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbd 8917#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 8918#define mmOTG1_OTG_FLOW_CONTROL 0x1bbe 8919#define mmOTG1_OTG_FLOW_CONTROL_BASE_IDX 2 8920#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bbf 8921#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 8922#define mmOTG1_OTG_CONTROL 0x1bc1 8923#define mmOTG1_OTG_CONTROL_BASE_IDX 2 8924#define mmOTG1_OTG_BLANK_CONTROL 0x1bc2 8925#define mmOTG1_OTG_BLANK_CONTROL_BASE_IDX 2 8926#define mmOTG1_OTG_INTERLACE_CONTROL 0x1bc4 8927#define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2 8928#define mmOTG1_OTG_INTERLACE_STATUS 0x1bc5 8929#define mmOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2 8930#define mmOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7 8931#define mmOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 8932#define mmOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8 8933#define mmOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 8934#define mmOTG1_OTG_STATUS 0x1bc9 8935#define mmOTG1_OTG_STATUS_BASE_IDX 2 8936#define mmOTG1_OTG_STATUS_POSITION 0x1bca 8937#define mmOTG1_OTG_STATUS_POSITION_BASE_IDX 2 8938#define mmOTG1_OTG_NOM_VERT_POSITION 0x1bcb 8939#define mmOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2 8940#define mmOTG1_OTG_STATUS_FRAME_COUNT 0x1bcc 8941#define mmOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 8942#define mmOTG1_OTG_STATUS_VF_COUNT 0x1bcd 8943#define mmOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2 8944#define mmOTG1_OTG_STATUS_HV_COUNT 0x1bce 8945#define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2 8946#define mmOTG1_OTG_COUNT_CONTROL 0x1bcf 8947#define mmOTG1_OTG_COUNT_CONTROL_BASE_IDX 2 8948#define mmOTG1_OTG_COUNT_RESET 0x1bd0 8949#define mmOTG1_OTG_COUNT_RESET_BASE_IDX 2 8950#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd1 8951#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 8952#define mmOTG1_OTG_VERT_SYNC_CONTROL 0x1bd2 8953#define mmOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 8954#define mmOTG1_OTG_STEREO_STATUS 0x1bd3 8955#define mmOTG1_OTG_STEREO_STATUS_BASE_IDX 2 8956#define mmOTG1_OTG_STEREO_CONTROL 0x1bd4 8957#define mmOTG1_OTG_STEREO_CONTROL_BASE_IDX 2 8958#define mmOTG1_OTG_SNAPSHOT_STATUS 0x1bd5 8959#define mmOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2 8960#define mmOTG1_OTG_SNAPSHOT_CONTROL 0x1bd6 8961#define mmOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 8962#define mmOTG1_OTG_SNAPSHOT_POSITION 0x1bd7 8963#define mmOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2 8964#define mmOTG1_OTG_SNAPSHOT_FRAME 0x1bd8 8965#define mmOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2 8966#define mmOTG1_OTG_INTERRUPT_CONTROL 0x1bd9 8967#define mmOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2 8968#define mmOTG1_OTG_UPDATE_LOCK 0x1bda 8969#define mmOTG1_OTG_UPDATE_LOCK_BASE_IDX 2 8970#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdb 8971#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 8972#define mmOTG1_OTG_MASTER_EN 0x1bdc 8973#define mmOTG1_OTG_MASTER_EN_BASE_IDX 2 8974#define mmOTG1_OTG_BLANK_DATA_COLOR 0x1bde 8975#define mmOTG1_OTG_BLANK_DATA_COLOR_BASE_IDX 2 8976#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT 0x1bdf 8977#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 8978#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1be2 8979#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 8980#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be3 8981#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 8982#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be4 8983#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 8984#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be5 8985#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 8986#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be6 8987#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 8988#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1be7 8989#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 8990#define mmOTG1_OTG_CRC_CNTL 0x1be8 8991#define mmOTG1_OTG_CRC_CNTL_BASE_IDX 2 8992#define mmOTG1_OTG_CRC_CNTL2 0x1be9 8993#define mmOTG1_OTG_CRC_CNTL2_BASE_IDX 2 8994#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1bea 8995#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 8996#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1beb 8997#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 8998#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1bec 8999#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 9000#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1bed
9001#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 9002#define mmOTG1_OTG_CRC0_DATA_RG 0x1bee 9003#define mmOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2 9004#define mmOTG1_OTG_CRC0_DATA_B 0x1bef 9005#define mmOTG1_OTG_CRC0_DATA_B_BASE_IDX 2 9006#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bf0 9007#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 9008#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bf1 9009#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 9010#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bf2 9011#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 9012#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bf3 9013#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 9014#define mmOTG1_OTG_CRC1_DATA_RG 0x1bf4 9015#define mmOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2 9016#define mmOTG1_OTG_CRC1_DATA_B 0x1bf5 9017#define mmOTG1_OTG_CRC1_DATA_B_BASE_IDX 2 9018#define mmOTG1_OTG_CRC2_DATA_RG 0x1bf6 9019#define mmOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2 9020#define mmOTG1_OTG_CRC2_DATA_B 0x1bf7 9021#define mmOTG1_OTG_CRC2_DATA_B_BASE_IDX 2 9022#define mmOTG1_OTG_CRC3_DATA_RG 0x1bf8 9023#define mmOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2 9024#define mmOTG1_OTG_CRC3_DATA_B 0x1bf9 9025#define mmOTG1_OTG_CRC3_DATA_B_BASE_IDX 2 9026#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bfa 9027#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 9028#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bfb 9029#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 9030#define mmOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c02 9031#define mmOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 9032#define mmOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c03 9033#define mmOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 9034#define mmOTG1_OTG_GSL_VSYNC_GAP 0x1c04 9035#define mmOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2 9036#define mmOTG1_OTG_MASTER_UPDATE_MODE 0x1c05 9037#define mmOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 9038#define mmOTG1_OTG_CLOCK_CONTROL 0x1c06 9039#define mmOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2 9040#define mmOTG1_OTG_VSTARTUP_PARAM 0x1c07 9041#define mmOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2 9042#define mmOTG1_OTG_VUPDATE_PARAM 0x1c08 9043#define mmOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2 9044#define mmOTG1_OTG_VREADY_PARAM 0x1c09 9045#define mmOTG1_OTG_VREADY_PARAM_BASE_IDX 2 9046#define mmOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c0a 9047#define mmOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 9048#define mmOTG1_OTG_MASTER_UPDATE_LOCK 0x1c0b 9049#define mmOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 9050#define mmOTG1_OTG_GSL_CONTROL 0x1c0c 9051#define mmOTG1_OTG_GSL_CONTROL_BASE_IDX 2 9052#define mmOTG1_OTG_GSL_WINDOW_X 0x1c0d 9053#define mmOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2 9054#define mmOTG1_OTG_GSL_WINDOW_Y 0x1c0e 9055#define mmOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2 9056#define mmOTG1_OTG_VUPDATE_KEEPOUT 0x1c0f 9057#define mmOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 9058#define mmOTG1_OTG_GLOBAL_CONTROL0 0x1c10 9059#define mmOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2 9060#define mmOTG1_OTG_GLOBAL_CONTROL1 0x1c11 9061#define mmOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2 9062#define mmOTG1_OTG_GLOBAL_CONTROL2 0x1c12 9063#define mmOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2 9064#define mmOTG1_OTG_GLOBAL_CONTROL3 0x1c13 9065#define mmOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2 9066#define mmOTG1_OTG_GLOBAL_CONTROL4 0x1c14 9067#define mmOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX 2 9068#define mmOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c15 9069#define mmOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 9070#define mmOTG1_OTG_MANUAL_FLOW_CONTROL 0x1c16 9071#define mmOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 9072#define mmOTG1_OTG_DRR_TIMING_INT_STATUS 0x1c17 9073#define mmOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 9074#define mmOTG1_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c18 9075#define mmOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 9076#define mmOTG1_OTG_DRR_V_TOTAL_CHANGE 0x1c19 9077#define mmOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 9078#define mmOTG1_OTG_DRR_TRIGGER_WINDOW 0x1c1a 9079#define mmOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 9080#define mmOTG1_OTG_DRR_CONTROL 0x1c1b 9081#define mmOTG1_OTG_DRR_CONTROL_BASE_IDX 2 9082#define mmOTG1_OTG_M_CONST_DTO0 0x1c1c 9083#define mmOTG1_OTG_M_CONST_DTO0_BASE_IDX 2 9084#define mmOTG1_OTG_M_CONST_DTO1 0x1c1d 9085#define mmOTG1_OTG_M_CONST_DTO1_BASE_IDX 2 9086#define mmOTG1_OTG_REQUEST_CONTROL 0x1c1e 9087#define mmOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2 9088#define mmOTG1_OTG_DSC_START_POSITION 0x1c1f 9089#define mmOTG1_OTG_DSC_START_POSITION_BASE_IDX 2 9090#define mmOTG1_OTG_PIPE_UPDATE_STATUS 0x1c20 9091#define mmOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 9092#define mmOTG1_OTG_SPARE_REGISTER 0x1c22 9093#define mmOTG1_OTG_SPARE_REGISTER_BASE_IDX 2 9094 9095 9096// addressBlock: dce_dc_optc_otg2_dispdec 9097// base address: 0x400 9098#define mmOTG2_OTG_H_TOTAL 0x1c2a 9099#define mmOTG2_OTG_H_TOTAL_BASE_IDX 2 9100#define mmOTG2_OTG_H_BLANK_START_END 0x1c2b 9101#define mmOTG2_OTG_H_BLANK_START_END_BASE_IDX 2 9102#define mmOTG2_OTG_H_SYNC_A 0x1c2c 9103#define mmOTG2_OTG_H_SYNC_A_BASE_IDX 2 9104#define mmOTG2_OTG_H_SYNC_A_CNTL 0x1c2d 9105#define mmOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2 9106#define mmOTG2_OTG_H_TIMING_CNTL 0x1c2e 9107#define mmOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2 9108#define mmOTG2_OTG_V_TOTAL 0x1c2f 9109#define mmOTG2_OTG_V_TOTAL_BASE_IDX 2 9110#define mmOTG2_OTG_V_TOTAL_MIN 0x1c30 9111#define mmOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2 9112#define mmOTG2_OTG_V_TOTAL_MAX 0x1c31 9113#define mmOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2 9114#define mmOTG2_OTG_V_TOTAL_MID 0x1c32 9115#define mmOTG2_OTG_V_TOTAL_MID_BASE_IDX 2 9116#define mmOTG2_OTG_V_TOTAL_CONTROL 0x1c33 9117#define mmOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2 9118#define mmOTG2_OTG_V_TOTAL_INT_STATUS 0x1c34 9119#define mmOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 9120#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c35 9121#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 9122#define mmOTG2_OTG_V_BLANK_START_END 0x1c36 9123#define mmOTG2_OTG_V_BLANK_START_END_BASE_IDX 2 9124#define mmOTG2_OTG_V_SYNC_A 0x1c37 9125#define mmOTG2_OTG_V_SYNC_A_BASE_IDX 2 9126#define mmOTG2_OTG_V_SYNC_A_CNTL 0x1c38 9127#define mmOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2 9128#define mmOTG2_OTG_TRIGA_CNTL 0x1c39 9129#define mmOTG2_OTG_TRIGA_CNTL_BASE_IDX 2 9130#define mmOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c3a 9131#define mmOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 9132#define mmOTG2_OTG_TRIGB_CNTL 0x1c3b 9133#define mmOTG2_OTG_TRIGB_CNTL_BASE_IDX 2 9134#define mmOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c3c 9135#define mmOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 9136#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c3d 9137#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 9138#define mmOTG2_OTG_FLOW_CONTROL 0x1c3e 9139#define mmOTG2_OTG_FLOW_CONTROL_BASE_IDX 2 9140#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c3f 9141#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 9142#define mmOTG2_OTG_CONTROL 0x1c41 9143#define mmOTG2_OTG_CONTROL_BASE_IDX 2 9144#define mmOTG2_OTG_BLANK_CONTROL 0x1c42 9145#define mmOTG2_OTG_BLANK_CONTROL_BASE_IDX 2 9146#define mmOTG2_OTG_INTERLACE_CONTROL 0x1c44 9147#define mmOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2 9148#define mmOTG2_OTG_INTERLACE_STATUS 0x1c45 9149#define mmOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2 9150#define mmOTG2_OTG_PIXEL_DATA_READBACK0 0x1c47 9151#define mmOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 9152#define mmOTG2_OTG_PIXEL_DATA_READBACK1 0x1c48 9153#define mmOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 9154#define mmOTG2_OTG_STATUS 0x1c49 9155#define mmOTG2_OTG_STATUS_BASE_IDX 2 9156#define mmOTG2_OTG_STATUS_POSITION 0x1c4a 9157#define mmOTG2_OTG_STATUS_POSITION_BASE_IDX 2 9158#define mmOTG2_OTG_NOM_VERT_POSITION 0x1c4b 9159#define mmOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2 9160#define mmOTG2_OTG_STATUS_FRAME_COUNT 0x1c4c 9161#define mmOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 9162#define mmOTG2_OTG_STATUS_VF_COUNT 0x1c4d 9163#define mmOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2 9164#define mmOTG2_OTG_STATUS_HV_COUNT 0x1c4e 9165#define mmOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2 9166#define mmOTG2_OTG_COUNT_CONTROL 0x1c4f 9167#define mmOTG2_OTG_COUNT_CONTROL_BASE_IDX 2 9168#define mmOTG2_OTG_COUNT_RESET 0x1c50 9169#define mmOTG2_OTG_COUNT_RESET_BASE_IDX 2 9170#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c51 9171#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 9172#define mmOTG2_OTG_VERT_SYNC_CONTROL 0x1c52 9173#define mmOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 9174#define mmOTG2_OTG_STEREO_STATUS 0x1c53 9175#define mmOTG2_OTG_STEREO_STATUS_BASE_IDX 2 9176#define mmOTG2_OTG_STEREO_CONTROL 0x1c54 9177#define mmOTG2_OTG_STEREO_CONTROL_BASE_IDX 2 9178#define mmOTG2_OTG_SNAPSHOT_STATUS 0x1c55 9179#define mmOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2 9180#define mmOTG2_OTG_SNAPSHOT_CONTROL 0x1c56 9181#define mmOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 9182#define mmOTG2_OTG_SNAPSHOT_POSITION 0x1c57 9183#define mmOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2 9184#define mmOTG2_OTG_SNAPSHOT_FRAME 0x1c58 9185#define mmOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2 9186#define mmOTG2_OTG_INTERRUPT_CONTROL 0x1c59 9187#define mmOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX 2 9188#define mmOTG2_OTG_UPDATE_LOCK 0x1c5a 9189#define mmOTG2_OTG_UPDATE_LOCK_BASE_IDX 2 9190#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c5b 9191#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 9192#define mmOTG2_OTG_MASTER_EN 0x1c5c 9193#define mmOTG2_OTG_MASTER_EN_BASE_IDX 2 9194#define mmOTG2_OTG_BLANK_DATA_COLOR 0x1c5e 9195#define mmOTG2_OTG_BLANK_DATA_COLOR_BASE_IDX 2 9196#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT 0x1c5f 9197#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 9198#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c62 9199#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 9200#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c63 9201#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 9202#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c64 9203#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 9204#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c65 9205#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 9206#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c66 9207#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 9208#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c67 9209#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 9210#define mmOTG2_OTG_CRC_CNTL 0x1c68 9211#define mmOTG2_OTG_CRC_CNTL_BASE_IDX 2 9212#define mmOTG2_OTG_CRC_CNTL2 0x1c69 9213#define mmOTG2_OTG_CRC_CNTL2_BASE_IDX 2 9214#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c6a 9215#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 9216#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c6b 9217#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 9218#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c6c 9219#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 9220#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c6d 9221#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 9222#define mmOTG2_OTG_CRC0_DATA_RG 0x1c6e 9223#define mmOTG2_OTG_CRC0_DATA_RG_BASE_IDX 2 9224#define mmOTG2_OTG_CRC0_DATA_B 0x1c6f 9225#define mmOTG2_OTG_CRC0_DATA_B_BASE_IDX 2 9226#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c70 9227#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 9228#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c71 9229#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 9230#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c72 9231#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 9232#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c73 9233#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 9234#define mmOTG2_OTG_CRC1_DATA_RG 0x1c74 9235#define mmOTG2_OTG_CRC1_DATA_RG_BASE_IDX 2 9236#define mmOTG2_OTG_CRC1_DATA_B 0x1c75 9237#define mmOTG2_OTG_CRC1_DATA_B_BASE_IDX 2 9238#define mmOTG2_OTG_CRC2_DATA_RG 0x1c76 9239#define mmOTG2_OTG_CRC2_DATA_RG_BASE_IDX 2 9240#define mmOTG2_OTG_CRC2_DATA_B 0x1c77 9241#define mmOTG2_OTG_CRC2_DATA_B_BASE_IDX 2 9242#define mmOTG2_OTG_CRC3_DATA_RG 0x1c78 9243#define mmOTG2_OTG_CRC3_DATA_RG_BASE_IDX 2 9244#define mmOTG2_OTG_CRC3_DATA_B 0x1c79 9245#define mmOTG2_OTG_CRC3_DATA_B_BASE_IDX 2 9246#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c7a 9247#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 9248#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c7b 9249#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 9250#define mmOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c82 9251#define mmOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 9252#define mmOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c83 9253#define mmOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 9254#define mmOTG2_OTG_GSL_VSYNC_GAP 0x1c84 9255#define mmOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2 9256#define mmOTG2_OTG_MASTER_UPDATE_MODE 0x1c85 9257#define mmOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 9258#define mmOTG2_OTG_CLOCK_CONTROL 0x1c86 9259#define mmOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2 9260#define mmOTG2_OTG_VSTARTUP_PARAM 0x1c87 9261#define mmOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2 9262#define mmOTG2_OTG_VUPDATE_PARAM 0x1c88 9263#define mmOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2 9264#define mmOTG2_OTG_VREADY_PARAM 0x1c89 9265#define mmOTG2_OTG_VREADY_PARAM_BASE_IDX 2 9266#define mmOTG2_OTG_GLOBAL_SYNC_STATUS 0x1c8a 9267#define mmOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 9268#define mmOTG2_OTG_MASTER_UPDATE_LOCK 0x1c8b 9269#define mmOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 9270#define mmOTG2_OTG_GSL_CONTROL 0x1c8c 9271#define mmOTG2_OTG_GSL_CONTROL_BASE_IDX 2 9272#define mmOTG2_OTG_GSL_WINDOW_X 0x1c8d 9273#define mmOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2 9274#define mmOTG2_OTG_GSL_WINDOW_Y 0x1c8e 9275#define mmOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2 9276#define mmOTG2_OTG_VUPDATE_KEEPOUT 0x1c8f 9277#define mmOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 9278#define mmOTG2_OTG_GLOBAL_CONTROL0 0x1c90 9279#define mmOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2 9280#define mmOTG2_OTG_GLOBAL_CONTROL1 0x1c91 9281#define mmOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2 9282#define mmOTG2_OTG_GLOBAL_CONTROL2 0x1c92 9283#define mmOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2 9284#define mmOTG2_OTG_GLOBAL_CONTROL3 0x1c93 9285#define mmOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2 9286#define mmOTG2_OTG_GLOBAL_CONTROL4 0x1c94 9287#define mmOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX 2 9288#define mmOTG2_OTG_TRIG_MANUAL_CONTROL 0x1c95 9289#define mmOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 9290#define mmOTG2_OTG_MANUAL_FLOW_CONTROL 0x1c96 9291#define mmOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 9292#define mmOTG2_OTG_DRR_TIMING_INT_STATUS 0x1c97 9293#define mmOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 9294#define mmOTG2_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c98 9295#define mmOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 9296#define mmOTG2_OTG_DRR_V_TOTAL_CHANGE 0x1c99 9297#define mmOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 9298#define mmOTG2_OTG_DRR_TRIGGER_WINDOW 0x1c9a 9299#define mmOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 9300#define mmOTG2_OTG_DRR_CONTROL 0x1c9b 9301#define mmOTG2_OTG_DRR_CONTROL_BASE_IDX 2 9302#define mmOTG2_OTG_M_CONST_DTO0 0x1c9c 9303#define mmOTG2_OTG_M_CONST_DTO0_BASE_IDX 2 9304#define mmOTG2_OTG_M_CONST_DTO1 0x1c9d 9305#define mmOTG2_OTG_M_CONST_DTO1_BASE_IDX 2 9306#define mmOTG2_OTG_REQUEST_CONTROL 0x1c9e 9307#define mmOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2 9308#define mmOTG2_OTG_DSC_START_POSITION 0x1c9f 9309#define mmOTG2_OTG_DSC_START_POSITION_BASE_IDX 2 9310#define mmOTG2_OTG_PIPE_UPDATE_STATUS 0x1ca0 9311#define mmOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 9312#define mmOTG2_OTG_SPARE_REGISTER 0x1ca2 9313#define mmOTG2_OTG_SPARE_REGISTER_BASE_IDX 2 9314 9315 9316// addressBlock: dce_dc_optc_otg3_dispdec 9317// base address: 0x600 9318#define mmOTG3_OTG_H_TOTAL 0x1caa 9319#define mmOTG3_OTG_H_TOTAL_BASE_IDX 2 9320#define mmOTG3_OTG_H_BLANK_START_END 0x1cab 9321#define mmOTG3_OTG_H_BLANK_START_END_BASE_IDX 2 9322#define mmOTG3_OTG_H_SYNC_A 0x1cac 9323#define mmOTG3_OTG_H_SYNC_A_BASE_IDX 2 9324#define mmOTG3_OTG_H_SYNC_A_CNTL 0x1cad 9325#define mmOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2 9326#define mmOTG3_OTG_H_TIMING_CNTL 0x1cae 9327#define mmOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2 9328#define mmOTG3_OTG_V_TOTAL 0x1caf 9329#define mmOTG3_OTG_V_TOTAL_BASE_IDX 2 9330#define mmOTG3_OTG_V_TOTAL_MIN 0x1cb0 9331#define mmOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2 9332#define mmOTG3_OTG_V_TOTAL_MAX 0x1cb1 9333#define mmOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2 9334#define mmOTG3_OTG_V_TOTAL_MID 0x1cb2 9335#define mmOTG3_OTG_V_TOTAL_MID_BASE_IDX 2 9336#define mmOTG3_OTG_V_TOTAL_CONTROL 0x1cb3 9337#define mmOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2 9338#define mmOTG3_OTG_V_TOTAL_INT_STATUS 0x1cb4 9339#define mmOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 9340#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1cb5 9341#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 9342#define mmOTG3_OTG_V_BLANK_START_END 0x1cb6 9343#define mmOTG3_OTG_V_BLANK_START_END_BASE_IDX 2 9344#define mmOTG3_OTG_V_SYNC_A 0x1cb7 9345#define mmOTG3_OTG_V_SYNC_A_BASE_IDX 2 9346#define mmOTG3_OTG_V_SYNC_A_CNTL 0x1cb8 9347#define mmOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2 9348#define mmOTG3_OTG_TRIGA_CNTL 0x1cb9 9349#define mmOTG3_OTG_TRIGA_CNTL_BASE_IDX 2 9350#define mmOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cba 9351#define mmOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 9352#define mmOTG3_OTG_TRIGB_CNTL 0x1cbb 9353#define mmOTG3_OTG_TRIGB_CNTL_BASE_IDX 2 9354#define mmOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cbc 9355#define mmOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 9356#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cbd 9357#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 9358#define mmOTG3_OTG_FLOW_CONTROL 0x1cbe 9359#define mmOTG3_OTG_FLOW_CONTROL_BASE_IDX 2 9360#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cbf 9361#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 9362#define mmOTG3_OTG_CONTROL 0x1cc1 9363#define mmOTG3_OTG_CONTROL_BASE_IDX 2 9364#define mmOTG3_OTG_BLANK_CONTROL 0x1cc2 9365#define mmOTG3_OTG_BLANK_CONTROL_BASE_IDX 2 9366#define mmOTG3_OTG_INTERLACE_CONTROL 0x1cc4 9367#define mmOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2 9368#define mmOTG3_OTG_INTERLACE_STATUS 0x1cc5 9369#define mmOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2 9370#define mmOTG3_OTG_PIXEL_DATA_READBACK0 0x1cc7 9371#define mmOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 9372#define mmOTG3_OTG_PIXEL_DATA_READBACK1 0x1cc8 9373#define mmOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 9374#define mmOTG3_OTG_STATUS 0x1cc9 9375#define mmOTG3_OTG_STATUS_BASE_IDX 2 9376#define mmOTG3_OTG_STATUS_POSITION 0x1cca 9377#define mmOTG3_OTG_STATUS_POSITION_BASE_IDX 2 9378#define mmOTG3_OTG_NOM_VERT_POSITION 0x1ccb 9379#define mmOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2 9380#define mmOTG3_OTG_STATUS_FRAME_COUNT 0x1ccc 9381#define mmOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 9382#define mmOTG3_OTG_STATUS_VF_COUNT 0x1ccd 9383#define mmOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2 9384#define mmOTG3_OTG_STATUS_HV_COUNT 0x1cce 9385#define mmOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2 9386#define mmOTG3_OTG_COUNT_CONTROL 0x1ccf 9387#define mmOTG3_OTG_COUNT_CONTROL_BASE_IDX 2 9388#define mmOTG3_OTG_COUNT_RESET 0x1cd0 9389#define mmOTG3_OTG_COUNT_RESET_BASE_IDX 2 9390#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1cd1 9391#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 9392#define mmOTG3_OTG_VERT_SYNC_CONTROL 0x1cd2 9393#define mmOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 9394#define mmOTG3_OTG_STEREO_STATUS 0x1cd3 9395#define mmOTG3_OTG_STEREO_STATUS_BASE_IDX 2 9396#define mmOTG3_OTG_STEREO_CONTROL 0x1cd4 9397#define mmOTG3_OTG_STEREO_CONTROL_BASE_IDX 2 9398#define mmOTG3_OTG_SNAPSHOT_STATUS 0x1cd5 9399#define mmOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2 9400#define mmOTG3_OTG_SNAPSHOT_CONTROL 0x1cd6 9401#define mmOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 9402#define mmOTG3_OTG_SNAPSHOT_POSITION 0x1cd7 9403#define mmOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2 9404#define mmOTG3_OTG_SNAPSHOT_FRAME 0x1cd8 9405#define mmOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2 9406#define mmOTG3_OTG_INTERRUPT_CONTROL 0x1cd9 9407#define mmOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX 2 9408#define mmOTG3_OTG_UPDATE_LOCK 0x1cda 9409#define mmOTG3_OTG_UPDATE_LOCK_BASE_IDX 2 9410#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cdb 9411#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 9412#define mmOTG3_OTG_MASTER_EN 0x1cdc 9413#define mmOTG3_OTG_MASTER_EN_BASE_IDX 2 9414#define mmOTG3_OTG_BLANK_DATA_COLOR 0x1cde 9415#define mmOTG3_OTG_BLANK_DATA_COLOR_BASE_IDX 2 9416#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT 0x1cdf 9417#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 9418#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1ce2 9419#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 9420#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1ce3 9421#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 9422#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1ce4 9423#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 9424#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1ce5 9425#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 9426#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1ce6 9427#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 9428#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1ce7 9429#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 9430#define mmOTG3_OTG_CRC_CNTL 0x1ce8 9431#define mmOTG3_OTG_CRC_CNTL_BASE_IDX 2 9432#define mmOTG3_OTG_CRC_CNTL2 0x1ce9 9433#define mmOTG3_OTG_CRC_CNTL2_BASE_IDX 2 9434#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1cea 9435#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 9436#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1ceb 9437#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 9438#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1cec 9439#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 9440#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1ced 9441#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 9442#define mmOTG3_OTG_CRC0_DATA_RG 0x1cee 9443#define mmOTG3_OTG_CRC0_DATA_RG_BASE_IDX 2 9444#define mmOTG3_OTG_CRC0_DATA_B 0x1cef 9445#define mmOTG3_OTG_CRC0_DATA_B_BASE_IDX 2 9446#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1cf0 9447#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 9448#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1cf1 9449#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 9450#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1cf2 9451#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 9452#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1cf3 9453#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 9454#define mmOTG3_OTG_CRC1_DATA_RG 0x1cf4 9455#define mmOTG3_OTG_CRC1_DATA_RG_BASE_IDX 2 9456#define mmOTG3_OTG_CRC1_DATA_B 0x1cf5 9457#define mmOTG3_OTG_CRC1_DATA_B_BASE_IDX 2 9458#define mmOTG3_OTG_CRC2_DATA_RG 0x1cf6 9459#define mmOTG3_OTG_CRC2_DATA_RG_BASE_IDX 2 9460#define mmOTG3_OTG_CRC2_DATA_B 0x1cf7 9461#define mmOTG3_OTG_CRC2_DATA_B_BASE_IDX 2 9462#define mmOTG3_OTG_CRC3_DATA_RG 0x1cf8 9463#define mmOTG3_OTG_CRC3_DATA_RG_BASE_IDX 2 9464#define mmOTG3_OTG_CRC3_DATA_B 0x1cf9 9465#define mmOTG3_OTG_CRC3_DATA_B_BASE_IDX 2 9466#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1cfa 9467#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 9468#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1cfb 9469#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 9470#define mmOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d02 9471#define mmOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 9472#define mmOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d03 9473#define mmOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 9474#define mmOTG3_OTG_GSL_VSYNC_GAP 0x1d04 9475#define mmOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2 9476#define mmOTG3_OTG_MASTER_UPDATE_MODE 0x1d05 9477#define mmOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 9478#define mmOTG3_OTG_CLOCK_CONTROL 0x1d06 9479#define mmOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2 9480#define mmOTG3_OTG_VSTARTUP_PARAM 0x1d07 9481#define mmOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2 9482#define mmOTG3_OTG_VUPDATE_PARAM 0x1d08 9483#define mmOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2 9484#define mmOTG3_OTG_VREADY_PARAM 0x1d09 9485#define mmOTG3_OTG_VREADY_PARAM_BASE_IDX 2 9486#define mmOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d0a 9487#define mmOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 9488#define mmOTG3_OTG_MASTER_UPDATE_LOCK 0x1d0b 9489#define mmOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 9490#define mmOTG3_OTG_GSL_CONTROL 0x1d0c 9491#define mmOTG3_OTG_GSL_CONTROL_BASE_IDX 2 9492#define mmOTG3_OTG_GSL_WINDOW_X 0x1d0d 9493#define mmOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2 9494#define mmOTG3_OTG_GSL_WINDOW_Y 0x1d0e 9495#define mmOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2 9496#define mmOTG3_OTG_VUPDATE_KEEPOUT 0x1d0f 9497#define mmOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 9498#define mmOTG3_OTG_GLOBAL_CONTROL0 0x1d10 9499#define mmOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2 9500#define mmOTG3_OTG_GLOBAL_CONTROL1 0x1d11 9501#define mmOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2 9502#define mmOTG3_OTG_GLOBAL_CONTROL2 0x1d12 9503#define mmOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2 9504#define mmOTG3_OTG_GLOBAL_CONTROL3 0x1d13 9505#define mmOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2 9506#define mmOTG3_OTG_GLOBAL_CONTROL4 0x1d14 9507#define mmOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX 2 9508#define mmOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d15 9509#define mmOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 9510#define mmOTG3_OTG_MANUAL_FLOW_CONTROL 0x1d16 9511#define mmOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 9512#define mmOTG3_OTG_DRR_TIMING_INT_STATUS 0x1d17 9513#define mmOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 9514#define mmOTG3_OTG_DRR_V_TOTAL_REACH_RANGE 0x1d18 9515#define mmOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 9516#define mmOTG3_OTG_DRR_V_TOTAL_CHANGE 0x1d19 9517#define mmOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 9518#define mmOTG3_OTG_DRR_TRIGGER_WINDOW 0x1d1a 9519#define mmOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 9520#define mmOTG3_OTG_DRR_CONTROL 0x1d1b 9521#define mmOTG3_OTG_DRR_CONTROL_BASE_IDX 2 9522#define mmOTG3_OTG_M_CONST_DTO0 0x1d1c 9523#define mmOTG3_OTG_M_CONST_DTO0_BASE_IDX 2 9524#define mmOTG3_OTG_M_CONST_DTO1 0x1d1d 9525#define mmOTG3_OTG_M_CONST_DTO1_BASE_IDX 2 9526#define mmOTG3_OTG_REQUEST_CONTROL 0x1d1e 9527#define mmOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2 9528#define mmOTG3_OTG_DSC_START_POSITION 0x1d1f 9529#define mmOTG3_OTG_DSC_START_POSITION_BASE_IDX 2 9530#define mmOTG3_OTG_PIPE_UPDATE_STATUS 0x1d20 9531#define mmOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 9532#define mmOTG3_OTG_SPARE_REGISTER 0x1d22 9533#define mmOTG3_OTG_SPARE_REGISTER_BASE_IDX 2 9534 9535 9536// addressBlock: dce_dc_optc_otg4_dispdec 9537// base address: 0x800 9538#define mmOTG4_OTG_H_TOTAL 0x1d2a 9539#define mmOTG4_OTG_H_TOTAL_BASE_IDX 2 9540#define mmOTG4_OTG_H_BLANK_START_END 0x1d2b 9541#define mmOTG4_OTG_H_BLANK_START_END_BASE_IDX 2 9542#define mmOTG4_OTG_H_SYNC_A 0x1d2c 9543#define mmOTG4_OTG_H_SYNC_A_BASE_IDX 2 9544#define mmOTG4_OTG_H_SYNC_A_CNTL 0x1d2d 9545#define mmOTG4_OTG_H_SYNC_A_CNTL_BASE_IDX 2 9546#define mmOTG4_OTG_H_TIMING_CNTL 0x1d2e 9547#define mmOTG4_OTG_H_TIMING_CNTL_BASE_IDX 2 9548#define mmOTG4_OTG_V_TOTAL 0x1d2f 9549#define mmOTG4_OTG_V_TOTAL_BASE_IDX 2 9550#define mmOTG4_OTG_V_TOTAL_MIN 0x1d30 9551#define mmOTG4_OTG_V_TOTAL_MIN_BASE_IDX 2 9552#define mmOTG4_OTG_V_TOTAL_MAX 0x1d31 9553#define mmOTG4_OTG_V_TOTAL_MAX_BASE_IDX 2 9554#define mmOTG4_OTG_V_TOTAL_MID 0x1d32 9555#define mmOTG4_OTG_V_TOTAL_MID_BASE_IDX 2 9556#define mmOTG4_OTG_V_TOTAL_CONTROL 0x1d33 9557#define mmOTG4_OTG_V_TOTAL_CONTROL_BASE_IDX 2 9558#define mmOTG4_OTG_V_TOTAL_INT_STATUS 0x1d34 9559#define mmOTG4_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 9560#define mmOTG4_OTG_VSYNC_NOM_INT_STATUS 0x1d35 9561#define mmOTG4_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 9562#define mmOTG4_OTG_V_BLANK_START_END 0x1d36 9563#define mmOTG4_OTG_V_BLANK_START_END_BASE_IDX 2 9564#define mmOTG4_OTG_V_SYNC_A 0x1d37 9565#define mmOTG4_OTG_V_SYNC_A_BASE_IDX 2 9566#define mmOTG4_OTG_V_SYNC_A_CNTL 0x1d38 9567#define mmOTG4_OTG_V_SYNC_A_CNTL_BASE_IDX 2 9568#define mmOTG4_OTG_TRIGA_CNTL 0x1d39 9569#define mmOTG4_OTG_TRIGA_CNTL_BASE_IDX 2 9570#define mmOTG4_OTG_TRIGA_MANUAL_TRIG 0x1d3a 9571#define mmOTG4_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 9572#define mmOTG4_OTG_TRIGB_CNTL 0x1d3b 9573#define mmOTG4_OTG_TRIGB_CNTL_BASE_IDX 2 9574#define mmOTG4_OTG_TRIGB_MANUAL_TRIG 0x1d3c 9575#define mmOTG4_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 9576#define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL 0x1d3d 9577#define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 9578#define mmOTG4_OTG_FLOW_CONTROL 0x1d3e 9579#define mmOTG4_OTG_FLOW_CONTROL_BASE_IDX 2 9580#define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE 0x1d3f 9581#define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 9582#define mmOTG4_OTG_CONTROL 0x1d41 9583#define mmOTG4_OTG_CONTROL_BASE_IDX 2 9584#define mmOTG4_OTG_BLANK_CONTROL 0x1d42 9585#define mmOTG4_OTG_BLANK_CONTROL_BASE_IDX 2 9586#define mmOTG4_OTG_INTERLACE_CONTROL 0x1d44 9587#define mmOTG4_OTG_INTERLACE_CONTROL_BASE_IDX 2 9588#define mmOTG4_OTG_INTERLACE_STATUS 0x1d45 9589#define mmOTG4_OTG_INTERLACE_STATUS_BASE_IDX 2 9590#define mmOTG4_OTG_PIXEL_DATA_READBACK0 0x1d47 9591#define mmOTG4_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 9592#define mmOTG4_OTG_PIXEL_DATA_READBACK1 0x1d48 9593#define mmOTG4_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 9594#define mmOTG4_OTG_STATUS 0x1d49 9595#define mmOTG4_OTG_STATUS_BASE_IDX 2 9596#define mmOTG4_OTG_STATUS_POSITION 0x1d4a 9597#define mmOTG4_OTG_STATUS_POSITION_BASE_IDX 2 9598#define mmOTG4_OTG_NOM_VERT_POSITION 0x1d4b 9599#define mmOTG4_OTG_NOM_VERT_POSITION_BASE_IDX 2 9600#define mmOTG4_OTG_STATUS_FRAME_COUNT 0x1d4c 9601#define mmOTG4_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 9602#define mmOTG4_OTG_STATUS_VF_COUNT 0x1d4d 9603#define mmOTG4_OTG_STATUS_VF_COUNT_BASE_IDX 2 9604#define mmOTG4_OTG_STATUS_HV_COUNT 0x1d4e 9605#define mmOTG4_OTG_STATUS_HV_COUNT_BASE_IDX 2 9606#define mmOTG4_OTG_COUNT_CONTROL 0x1d4f 9607#define mmOTG4_OTG_COUNT_CONTROL_BASE_IDX 2 9608#define mmOTG4_OTG_COUNT_RESET 0x1d50 9609#define mmOTG4_OTG_COUNT_RESET_BASE_IDX 2 9610#define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1d51 9611#define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 9612#define mmOTG4_OTG_VERT_SYNC_CONTROL 0x1d52 9613#define mmOTG4_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 9614#define mmOTG4_OTG_STEREO_STATUS 0x1d53 9615#define mmOTG4_OTG_STEREO_STATUS_BASE_IDX 2 9616#define mmOTG4_OTG_STEREO_CONTROL 0x1d54 9617#define mmOTG4_OTG_STEREO_CONTROL_BASE_IDX 2 9618#define mmOTG4_OTG_SNAPSHOT_STATUS 0x1d55 9619#define mmOTG4_OTG_SNAPSHOT_STATUS_BASE_IDX 2 9620#define mmOTG4_OTG_SNAPSHOT_CONTROL 0x1d56 9621#define mmOTG4_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 9622#define mmOTG4_OTG_SNAPSHOT_POSITION 0x1d57 9623#define mmOTG4_OTG_SNAPSHOT_POSITION_BASE_IDX 2 9624#define mmOTG4_OTG_SNAPSHOT_FRAME 0x1d58 9625#define mmOTG4_OTG_SNAPSHOT_FRAME_BASE_IDX 2 9626#define mmOTG4_OTG_INTERRUPT_CONTROL 0x1d59 9627#define mmOTG4_OTG_INTERRUPT_CONTROL_BASE_IDX 2 9628#define mmOTG4_OTG_UPDATE_LOCK 0x1d5a 9629#define mmOTG4_OTG_UPDATE_LOCK_BASE_IDX 2 9630#define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL 0x1d5b 9631#define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 9632#define mmOTG4_OTG_MASTER_EN 0x1d5c 9633#define mmOTG4_OTG_MASTER_EN_BASE_IDX 2 9634#define mmOTG4_OTG_BLANK_DATA_COLOR 0x1d5e 9635#define mmOTG4_OTG_BLANK_DATA_COLOR_BASE_IDX 2 9636#define mmOTG4_OTG_BLANK_DATA_COLOR_EXT 0x1d5f 9637#define mmOTG4_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 9638#define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION 0x1d62 9639#define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 9640#define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1d63 9641#define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 9642#define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION 0x1d64 9643#define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 9644#define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1d65 9645#define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 9646#define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION 0x1d66 9647#define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 9648#define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1d67 9649#define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 9650#define mmOTG4_OTG_CRC_CNTL 0x1d68 9651#define mmOTG4_OTG_CRC_CNTL_BASE_IDX 2 9652#define mmOTG4_OTG_CRC_CNTL2 0x1d69 9653#define mmOTG4_OTG_CRC_CNTL2_BASE_IDX 2 9654#define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL 0x1d6a 9655#define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 9656#define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL 0x1d6b 9657#define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 9658#define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL 0x1d6c 9659#define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 9660#define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL 0x1d6d 9661#define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 9662#define mmOTG4_OTG_CRC0_DATA_RG 0x1d6e 9663#define mmOTG4_OTG_CRC0_DATA_RG_BASE_IDX 2 9664#define mmOTG4_OTG_CRC0_DATA_B 0x1d6f 9665#define mmOTG4_OTG_CRC0_DATA_B_BASE_IDX 2 9666#define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL 0x1d70 9667#define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 9668#define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL 0x1d71 9669#define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 9670#define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL 0x1d72 9671#define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 9672#define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL 0x1d73 9673#define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 9674#define mmOTG4_OTG_CRC1_DATA_RG 0x1d74 9675#define mmOTG4_OTG_CRC1_DATA_RG_BASE_IDX 2 9676#define mmOTG4_OTG_CRC1_DATA_B 0x1d75 9677#define mmOTG4_OTG_CRC1_DATA_B_BASE_IDX 2 9678#define mmOTG4_OTG_CRC2_DATA_RG 0x1d76 9679#define mmOTG4_OTG_CRC2_DATA_RG_BASE_IDX 2 9680#define mmOTG4_OTG_CRC2_DATA_B 0x1d77 9681#define mmOTG4_OTG_CRC2_DATA_B_BASE_IDX 2 9682#define mmOTG4_OTG_CRC3_DATA_RG 0x1d78 9683#define mmOTG4_OTG_CRC3_DATA_RG_BASE_IDX 2 9684#define mmOTG4_OTG_CRC3_DATA_B 0x1d79 9685#define mmOTG4_OTG_CRC3_DATA_B_BASE_IDX 2 9686#define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK 0x1d7a 9687#define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 9688#define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1d7b 9689#define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 9690#define mmOTG4_OTG_STATIC_SCREEN_CONTROL 0x1d82 9691#define mmOTG4_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 9692#define mmOTG4_OTG_3D_STRUCTURE_CONTROL 0x1d83 9693#define mmOTG4_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 9694#define mmOTG4_OTG_GSL_VSYNC_GAP 0x1d84 9695#define mmOTG4_OTG_GSL_VSYNC_GAP_BASE_IDX 2 9696#define mmOTG4_OTG_MASTER_UPDATE_MODE 0x1d85 9697#define mmOTG4_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 9698#define mmOTG4_OTG_CLOCK_CONTROL 0x1d86 9699#define mmOTG4_OTG_CLOCK_CONTROL_BASE_IDX 2 9700#define mmOTG4_OTG_VSTARTUP_PARAM 0x1d87 9701#define mmOTG4_OTG_VSTARTUP_PARAM_BASE_IDX 2 9702#define mmOTG4_OTG_VUPDATE_PARAM 0x1d88 9703#define mmOTG4_OTG_VUPDATE_PARAM_BASE_IDX 2 9704#define mmOTG4_OTG_VREADY_PARAM 0x1d89 9705#define mmOTG4_OTG_VREADY_PARAM_BASE_IDX 2 9706#define mmOTG4_OTG_GLOBAL_SYNC_STATUS 0x1d8a 9707#define mmOTG4_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 9708#define mmOTG4_OTG_MASTER_UPDATE_LOCK 0x1d8b 9709#define mmOTG4_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 9710#define mmOTG4_OTG_GSL_CONTROL 0x1d8c 9711#define mmOTG4_OTG_GSL_CONTROL_BASE_IDX 2 9712#define mmOTG4_OTG_GSL_WINDOW_X 0x1d8d 9713#define mmOTG4_OTG_GSL_WINDOW_X_BASE_IDX 2 9714#define mmOTG4_OTG_GSL_WINDOW_Y 0x1d8e 9715#define mmOTG4_OTG_GSL_WINDOW_Y_BASE_IDX 2 9716#define mmOTG4_OTG_VUPDATE_KEEPOUT 0x1d8f 9717#define mmOTG4_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 9718#define mmOTG4_OTG_GLOBAL_CONTROL0 0x1d90 9719#define mmOTG4_OTG_GLOBAL_CONTROL0_BASE_IDX 2 9720#define mmOTG4_OTG_GLOBAL_CONTROL1 0x1d91 9721#define mmOTG4_OTG_GLOBAL_CONTROL1_BASE_IDX 2 9722#define mmOTG4_OTG_GLOBAL_CONTROL2 0x1d92 9723#define mmOTG4_OTG_GLOBAL_CONTROL2_BASE_IDX 2 9724#define mmOTG4_OTG_GLOBAL_CONTROL3 0x1d93 9725#define mmOTG4_OTG_GLOBAL_CONTROL3_BASE_IDX 2 9726#define mmOTG4_OTG_GLOBAL_CONTROL4 0x1d94 9727#define mmOTG4_OTG_GLOBAL_CONTROL4_BASE_IDX 2 9728#define mmOTG4_OTG_TRIG_MANUAL_CONTROL 0x1d95 9729#define mmOTG4_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 9730#define mmOTG4_OTG_MANUAL_FLOW_CONTROL 0x1d96 9731#define mmOTG4_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 9732#define mmOTG4_OTG_DRR_TIMING_INT_STATUS 0x1d97 9733#define mmOTG4_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 9734#define mmOTG4_OTG_DRR_V_TOTAL_REACH_RANGE 0x1d98 9735#define mmOTG4_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 9736#define mmOTG4_OTG_DRR_V_TOTAL_CHANGE 0x1d99 9737#define mmOTG4_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 9738#define mmOTG4_OTG_DRR_TRIGGER_WINDOW 0x1d9a 9739#define mmOTG4_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 9740#define mmOTG4_OTG_DRR_CONTROL 0x1d9b 9741#define mmOTG4_OTG_DRR_CONTROL_BASE_IDX 2 9742#define mmOTG4_OTG_M_CONST_DTO0 0x1d9c 9743#define mmOTG4_OTG_M_CONST_DTO0_BASE_IDX 2 9744#define mmOTG4_OTG_M_CONST_DTO1 0x1d9d 9745#define mmOTG4_OTG_M_CONST_DTO1_BASE_IDX 2 9746#define mmOTG4_OTG_REQUEST_CONTROL 0x1d9e 9747#define mmOTG4_OTG_REQUEST_CONTROL_BASE_IDX 2 9748#define mmOTG4_OTG_DSC_START_POSITION 0x1d9f 9749#define mmOTG4_OTG_DSC_START_POSITION_BASE_IDX 2 9750#define mmOTG4_OTG_PIPE_UPDATE_STATUS 0x1da0 9751#define mmOTG4_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 9752#define mmOTG4_OTG_SPARE_REGISTER 0x1da2 9753#define mmOTG4_OTG_SPARE_REGISTER_BASE_IDX 2 9754 9755 9756// addressBlock: dce_dc_optc_otg5_dispdec 9757// base address: 0xa00 9758#define mmOTG5_OTG_H_TOTAL 0x1daa 9759#define mmOTG5_OTG_H_TOTAL_BASE_IDX 2 9760#define mmOTG5_OTG_H_BLANK_START_END 0x1dab 9761#define mmOTG5_OTG_H_BLANK_START_END_BASE_IDX 2 9762#define mmOTG5_OTG_H_SYNC_A 0x1dac 9763#define mmOTG5_OTG_H_SYNC_A_BASE_IDX 2 9764#define mmOTG5_OTG_H_SYNC_A_CNTL 0x1dad 9765#define mmOTG5_OTG_H_SYNC_A_CNTL_BASE_IDX 2 9766#define mmOTG5_OTG_H_TIMING_CNTL 0x1dae 9767#define mmOTG5_OTG_H_TIMING_CNTL_BASE_IDX 2 9768#define mmOTG5_OTG_V_TOTAL 0x1daf 9769#define mmOTG5_OTG_V_TOTAL_BASE_IDX 2 9770#define mmOTG5_OTG_V_TOTAL_MIN 0x1db0 9771#define mmOTG5_OTG_V_TOTAL_MIN_BASE_IDX 2 9772#define mmOTG5_OTG_V_TOTAL_MAX 0x1db1 9773#define mmOTG5_OTG_V_TOTAL_MAX_BASE_IDX 2 9774#define mmOTG5_OTG_V_TOTAL_MID 0x1db2 9775#define mmOTG5_OTG_V_TOTAL_MID_BASE_IDX 2 9776#define mmOTG5_OTG_V_TOTAL_CONTROL 0x1db3 9777#define mmOTG5_OTG_V_TOTAL_CONTROL_BASE_IDX 2 9778#define mmOTG5_OTG_V_TOTAL_INT_STATUS 0x1db4 9779#define mmOTG5_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 9780#define mmOTG5_OTG_VSYNC_NOM_INT_STATUS 0x1db5 9781#define mmOTG5_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 9782#define mmOTG5_OTG_V_BLANK_START_END 0x1db6 9783#define mmOTG5_OTG_V_BLANK_START_END_BASE_IDX 2 9784#define mmOTG5_OTG_V_SYNC_A 0x1db7 9785#define mmOTG5_OTG_V_SYNC_A_BASE_IDX 2 9786#define mmOTG5_OTG_V_SYNC_A_CNTL 0x1db8 9787#define mmOTG5_OTG_V_SYNC_A_CNTL_BASE_IDX 2 9788#define mmOTG5_OTG_TRIGA_CNTL 0x1db9 9789#define mmOTG5_OTG_TRIGA_CNTL_BASE_IDX 2 9790#define mmOTG5_OTG_TRIGA_MANUAL_TRIG 0x1dba 9791#define mmOTG5_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 9792#define mmOTG5_OTG_TRIGB_CNTL 0x1dbb 9793#define mmOTG5_OTG_TRIGB_CNTL_BASE_IDX 2 9794#define mmOTG5_OTG_TRIGB_MANUAL_TRIG 0x1dbc 9795#define mmOTG5_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 9796#define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL 0x1dbd 9797#define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 9798#define mmOTG5_OTG_FLOW_CONTROL 0x1dbe 9799#define mmOTG5_OTG_FLOW_CONTROL_BASE_IDX 2 9800#define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE 0x1dbf 9801#define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 9802#define mmOTG5_OTG_CONTROL 0x1dc1 9803#define mmOTG5_OTG_CONTROL_BASE_IDX 2 9804#define mmOTG5_OTG_BLANK_CONTROL 0x1dc2 9805#define mmOTG5_OTG_BLANK_CONTROL_BASE_IDX 2 9806#define mmOTG5_OTG_INTERLACE_CONTROL 0x1dc4 9807#define mmOTG5_OTG_INTERLACE_CONTROL_BASE_IDX 2 9808#define mmOTG5_OTG_INTERLACE_STATUS 0x1dc5 9809#define mmOTG5_OTG_INTERLACE_STATUS_BASE_IDX 2 9810#define mmOTG5_OTG_PIXEL_DATA_READBACK0 0x1dc7 9811#define mmOTG5_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 9812#define mmOTG5_OTG_PIXEL_DATA_READBACK1 0x1dc8 9813#define mmOTG5_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 9814#define mmOTG5_OTG_STATUS 0x1dc9 9815#define mmOTG5_OTG_STATUS_BASE_IDX 2 9816#define mmOTG5_OTG_STATUS_POSITION 0x1dca 9817#define mmOTG5_OTG_STATUS_POSITION_BASE_IDX 2 9818#define mmOTG5_OTG_NOM_VERT_POSITION 0x1dcb 9819#define mmOTG5_OTG_NOM_VERT_POSITION_BASE_IDX 2 9820#define mmOTG5_OTG_STATUS_FRAME_COUNT 0x1dcc 9821#define mmOTG5_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 9822#define mmOTG5_OTG_STATUS_VF_COUNT 0x1dcd 9823#define mmOTG5_OTG_STATUS_VF_COUNT_BASE_IDX 2 9824#define mmOTG5_OTG_STATUS_HV_COUNT 0x1dce 9825#define mmOTG5_OTG_STATUS_HV_COUNT_BASE_IDX 2 9826#define mmOTG5_OTG_COUNT_CONTROL 0x1dcf 9827#define mmOTG5_OTG_COUNT_CONTROL_BASE_IDX 2 9828#define mmOTG5_OTG_COUNT_RESET 0x1dd0 9829#define mmOTG5_OTG_COUNT_RESET_BASE_IDX 2 9830#define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1dd1 9831#define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 9832#define mmOTG5_OTG_VERT_SYNC_CONTROL 0x1dd2 9833#define mmOTG5_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 9834#define mmOTG5_OTG_STEREO_STATUS 0x1dd3 9835#define mmOTG5_OTG_STEREO_STATUS_BASE_IDX 2 9836#define mmOTG5_OTG_STEREO_CONTROL 0x1dd4 9837#define mmOTG5_OTG_STEREO_CONTROL_BASE_IDX 2 9838#define mmOTG5_OTG_SNAPSHOT_STATUS 0x1dd5 9839#define mmOTG5_OTG_SNAPSHOT_STATUS_BASE_IDX 2 9840#define mmOTG5_OTG_SNAPSHOT_CONTROL 0x1dd6 9841#define mmOTG5_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 9842#define mmOTG5_OTG_SNAPSHOT_POSITION 0x1dd7 9843#define mmOTG5_OTG_SNAPSHOT_POSITION_BASE_IDX 2 9844#define mmOTG5_OTG_SNAPSHOT_FRAME 0x1dd8 9845#define mmOTG5_OTG_SNAPSHOT_FRAME_BASE_IDX 2 9846#define mmOTG5_OTG_INTERRUPT_CONTROL 0x1dd9 9847#define mmOTG5_OTG_INTERRUPT_CONTROL_BASE_IDX 2 9848#define mmOTG5_OTG_UPDATE_LOCK 0x1dda 9849#define mmOTG5_OTG_UPDATE_LOCK_BASE_IDX 2 9850#define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL 0x1ddb 9851#define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 9852#define mmOTG5_OTG_MASTER_EN 0x1ddc 9853#define mmOTG5_OTG_MASTER_EN_BASE_IDX 2 9854#define mmOTG5_OTG_BLANK_DATA_COLOR 0x1dde 9855#define mmOTG5_OTG_BLANK_DATA_COLOR_BASE_IDX 2 9856#define mmOTG5_OTG_BLANK_DATA_COLOR_EXT 0x1ddf 9857#define mmOTG5_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 9858#define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION 0x1de2 9859#define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 9860#define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1de3 9861#define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 9862#define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION 0x1de4 9863#define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 9864#define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1de5 9865#define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 9866#define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION 0x1de6 9867#define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 9868#define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1de7 9869#define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 9870#define mmOTG5_OTG_CRC_CNTL 0x1de8 9871#define mmOTG5_OTG_CRC_CNTL_BASE_IDX 2 9872#define mmOTG5_OTG_CRC_CNTL2 0x1de9 9873#define mmOTG5_OTG_CRC_CNTL2_BASE_IDX 2 9874#define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL 0x1dea 9875#define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 9876#define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL 0x1deb 9877#define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 9878#define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL 0x1dec 9879#define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 9880#define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL 0x1ded 9881#define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 9882#define mmOTG5_OTG_CRC0_DATA_RG 0x1dee 9883#define mmOTG5_OTG_CRC0_DATA_RG_BASE_IDX 2 9884#define mmOTG5_OTG_CRC0_DATA_B 0x1def 9885#define mmOTG5_OTG_CRC0_DATA_B_BASE_IDX 2 9886#define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL 0x1df0 9887#define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 9888#define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL 0x1df1 9889#define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 9890#define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL 0x1df2 9891#define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 9892#define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL 0x1df3 9893#define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 9894#define mmOTG5_OTG_CRC1_DATA_RG 0x1df4 9895#define mmOTG5_OTG_CRC1_DATA_RG_BASE_IDX 2 9896#define mmOTG5_OTG_CRC1_DATA_B 0x1df5 9897#define mmOTG5_OTG_CRC1_DATA_B_BASE_IDX 2 9898#define mmOTG5_OTG_CRC2_DATA_RG 0x1df6 9899#define mmOTG5_OTG_CRC2_DATA_RG_BASE_IDX 2 9900#define mmOTG5_OTG_CRC2_DATA_B 0x1df7 9901#define mmOTG5_OTG_CRC2_DATA_B_BASE_IDX 2 9902#define mmOTG5_OTG_CRC3_DATA_RG 0x1df8 9903#define mmOTG5_OTG_CRC3_DATA_RG_BASE_IDX 2 9904#define mmOTG5_OTG_CRC3_DATA_B 0x1df9 9905#define mmOTG5_OTG_CRC3_DATA_B_BASE_IDX 2 9906#define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK 0x1dfa 9907#define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 9908#define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1dfb 9909#define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 9910#define mmOTG5_OTG_STATIC_SCREEN_CONTROL 0x1e02 9911#define mmOTG5_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 9912#define mmOTG5_OTG_3D_STRUCTURE_CONTROL 0x1e03 9913#define mmOTG5_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 9914#define mmOTG5_OTG_GSL_VSYNC_GAP 0x1e04 9915#define mmOTG5_OTG_GSL_VSYNC_GAP_BASE_IDX 2 9916#define mmOTG5_OTG_MASTER_UPDATE_MODE 0x1e05 9917#define mmOTG5_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 9918#define mmOTG5_OTG_CLOCK_CONTROL 0x1e06 9919#define mmOTG5_OTG_CLOCK_CONTROL_BASE_IDX 2 9920#define mmOTG5_OTG_VSTARTUP_PARAM 0x1e07 9921#define mmOTG5_OTG_VSTARTUP_PARAM_BASE_IDX 2 9922#define mmOTG5_OTG_VUPDATE_PARAM 0x1e08 9923#define mmOTG5_OTG_VUPDATE_PARAM_BASE_IDX 2 9924#define mmOTG5_OTG_VREADY_PARAM 0x1e09 9925#define mmOTG5_OTG_VREADY_PARAM_BASE_IDX 2 9926#define mmOTG5_OTG_GLOBAL_SYNC_STATUS 0x1e0a 9927#define mmOTG5_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 9928#define mmOTG5_OTG_MASTER_UPDATE_LOCK 0x1e0b 9929#define mmOTG5_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 9930#define mmOTG5_OTG_GSL_CONTROL 0x1e0c 9931#define mmOTG5_OTG_GSL_CONTROL_BASE_IDX 2 9932#define mmOTG5_OTG_GSL_WINDOW_X 0x1e0d 9933#define mmOTG5_OTG_GSL_WINDOW_X_BASE_IDX 2 9934#define mmOTG5_OTG_GSL_WINDOW_Y 0x1e0e 9935#define mmOTG5_OTG_GSL_WINDOW_Y_BASE_IDX 2 9936#define mmOTG5_OTG_VUPDATE_KEEPOUT 0x1e0f 9937#define mmOTG5_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 9938#define mmOTG5_OTG_GLOBAL_CONTROL0 0x1e10 9939#define mmOTG5_OTG_GLOBAL_CONTROL0_BASE_IDX 2 9940#define mmOTG5_OTG_GLOBAL_CONTROL1 0x1e11 9941#define mmOTG5_OTG_GLOBAL_CONTROL1_BASE_IDX 2 9942#define mmOTG5_OTG_GLOBAL_CONTROL2 0x1e12 9943#define mmOTG5_OTG_GLOBAL_CONTROL2_BASE_IDX 2 9944#define mmOTG5_OTG_GLOBAL_CONTROL3 0x1e13 9945#define mmOTG5_OTG_GLOBAL_CONTROL3_BASE_IDX 2 9946#define mmOTG5_OTG_GLOBAL_CONTROL4 0x1e14 9947#define mmOTG5_OTG_GLOBAL_CONTROL4_BASE_IDX 2 9948#define mmOTG5_OTG_TRIG_MANUAL_CONTROL 0x1e15 9949#define mmOTG5_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 9950#define mmOTG5_OTG_MANUAL_FLOW_CONTROL 0x1e16 9951#define mmOTG5_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 9952#define mmOTG5_OTG_DRR_TIMING_INT_STATUS 0x1e17 9953#define mmOTG5_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 9954#define mmOTG5_OTG_DRR_V_TOTAL_REACH_RANGE 0x1e18 9955#define mmOTG5_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 9956#define mmOTG5_OTG_DRR_V_TOTAL_CHANGE 0x1e19 9957#define mmOTG5_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 9958#define mmOTG5_OTG_DRR_TRIGGER_WINDOW 0x1e1a 9959#define mmOTG5_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 9960#define mmOTG5_OTG_DRR_CONTROL 0x1e1b 9961#define mmOTG5_OTG_DRR_CONTROL_BASE_IDX 2 9962#define mmOTG5_OTG_M_CONST_DTO0 0x1e1c 9963#define mmOTG5_OTG_M_CONST_DTO0_BASE_IDX 2 9964#define mmOTG5_OTG_M_CONST_DTO1 0x1e1d 9965#define mmOTG5_OTG_M_CONST_DTO1_BASE_IDX 2 9966#define mmOTG5_OTG_REQUEST_CONTROL 0x1e1e 9967#define mmOTG5_OTG_REQUEST_CONTROL_BASE_IDX 2 9968#define mmOTG5_OTG_DSC_START_POSITION 0x1e1f 9969#define mmOTG5_OTG_DSC_START_POSITION_BASE_IDX 2 9970#define mmOTG5_OTG_PIPE_UPDATE_STATUS 0x1e20 9971#define mmOTG5_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 9972#define mmOTG5_OTG_SPARE_REGISTER 0x1e22 9973#define mmOTG5_OTG_SPARE_REGISTER_BASE_IDX 2 9974 9975 9976// addressBlock: dce_dc_optc_optc_misc_dispdec 9977// base address: 0x0 9978#define mmDWB_SOURCE_SELECT 0x1e2a 9979#define mmDWB_SOURCE_SELECT_BASE_IDX 2 9980#define mmGSL_SOURCE_SELECT 0x1e2b 9981#define mmGSL_SOURCE_SELECT_BASE_IDX 2 9982#define mmOPTC_CLOCK_CONTROL 0x1e2c 9983#define mmOPTC_CLOCK_CONTROL_BASE_IDX 2 9984#define mmODM_MEM_PWR_CTRL 0x1e2d 9985#define mmODM_MEM_PWR_CTRL_BASE_IDX 2 9986#define mmODM_MEM_PWR_CTRL2 0x1e2e 9987#define mmODM_MEM_PWR_CTRL2_BASE_IDX 2 9988#define mmODM_MEM_PWR_CTRL3 0x1e2f 9989#define mmODM_MEM_PWR_CTRL3_BASE_IDX 2 9990#define mmODM_MEM_PWR_STATUS 0x1e30 9991#define mmODM_MEM_PWR_STATUS_BASE_IDX 2 9992#define mmOPTC_MISC_SPARE_REGISTER 0x1e31 9993#define mmOPTC_MISC_SPARE_REGISTER_BASE_IDX 2 9994 9995 9996// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec 9997// base address: 0x79a8 9998#define mmDC_PERFMON19_PERFCOUNTER_CNTL 0x1e6a 9999#define mmDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX 2 10000#define mmDC_PERFMON19_PERFCOUNTER_CNTL2 0x1e6b
10001#define mmDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX 2 10002#define mmDC_PERFMON19_PERFCOUNTER_STATE 0x1e6c 10003#define mmDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX 2 10004#define mmDC_PERFMON19_PERFMON_CNTL 0x1e6d 10005#define mmDC_PERFMON19_PERFMON_CNTL_BASE_IDX 2 10006#define mmDC_PERFMON19_PERFMON_CNTL2 0x1e6e 10007#define mmDC_PERFMON19_PERFMON_CNTL2_BASE_IDX 2 10008#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC 0x1e6f 10009#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 10010#define mmDC_PERFMON19_PERFMON_CVALUE_LOW 0x1e70 10011#define mmDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX 2 10012#define mmDC_PERFMON19_PERFMON_HI 0x1e71 10013#define mmDC_PERFMON19_PERFMON_HI_BASE_IDX 2 10014#define mmDC_PERFMON19_PERFMON_LOW 0x1e72 10015#define mmDC_PERFMON19_PERFMON_LOW_BASE_IDX 2 10016 10017 10018// addressBlock: dce_dc_dio_dout_i2c_dispdec 10019// base address: 0x0 10020#define mmDC_I2C_CONTROL 0x1e98 10021#define mmDC_I2C_CONTROL_BASE_IDX 2 10022#define mmDC_I2C_ARBITRATION 0x1e99 10023#define mmDC_I2C_ARBITRATION_BASE_IDX 2 10024#define mmDC_I2C_INTERRUPT_CONTROL 0x1e9a 10025#define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2 10026#define mmDC_I2C_SW_STATUS 0x1e9b 10027#define mmDC_I2C_SW_STATUS_BASE_IDX 2 10028#define mmDC_I2C_DDC1_HW_STATUS 0x1e9c 10029#define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX 2 10030#define mmDC_I2C_DDC2_HW_STATUS 0x1e9d 10031#define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX 2 10032#define mmDC_I2C_DDC3_HW_STATUS 0x1e9e 10033#define mmDC_I2C_DDC3_HW_STATUS_BASE_IDX 2 10034#define mmDC_I2C_DDC4_HW_STATUS 0x1e9f 10035#define mmDC_I2C_DDC4_HW_STATUS_BASE_IDX 2 10036#define mmDC_I2C_DDC5_HW_STATUS 0x1ea0 10037#define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX 2 10038#define mmDC_I2C_DDC6_HW_STATUS 0x1ea1 10039#define mmDC_I2C_DDC6_HW_STATUS_BASE_IDX 2 10040#define mmDC_I2C_DDC1_SPEED 0x1ea2 10041#define mmDC_I2C_DDC1_SPEED_BASE_IDX 2 10042#define mmDC_I2C_DDC1_SETUP 0x1ea3 10043#define mmDC_I2C_DDC1_SETUP_BASE_IDX 2 10044#define mmDC_I2C_DDC2_SPEED 0x1ea4 10045#define mmDC_I2C_DDC2_SPEED_BASE_IDX 2 10046#define mmDC_I2C_DDC2_SETUP 0x1ea5 10047#define mmDC_I2C_DDC2_SETUP_BASE_IDX 2 10048#define mmDC_I2C_DDC3_SPEED 0x1ea6 10049#define mmDC_I2C_DDC3_SPEED_BASE_IDX 2 10050#define mmDC_I2C_DDC3_SETUP 0x1ea7 10051#define mmDC_I2C_DDC3_SETUP_BASE_IDX 2 10052#define mmDC_I2C_DDC4_SPEED 0x1ea8 10053#define mmDC_I2C_DDC4_SPEED_BASE_IDX 2 10054#define mmDC_I2C_DDC4_SETUP 0x1ea9 10055#define mmDC_I2C_DDC4_SETUP_BASE_IDX 2 10056#define mmDC_I2C_DDC5_SPEED 0x1eaa 10057#define mmDC_I2C_DDC5_SPEED_BASE_IDX 2 10058#define mmDC_I2C_DDC5_SETUP 0x1eab 10059#define mmDC_I2C_DDC5_SETUP_BASE_IDX 2 10060#define mmDC_I2C_DDC6_SPEED 0x1eac 10061#define mmDC_I2C_DDC6_SPEED_BASE_IDX 2 10062#define mmDC_I2C_DDC6_SETUP 0x1ead 10063#define mmDC_I2C_DDC6_SETUP_BASE_IDX 2 10064#define mmDC_I2C_TRANSACTION0 0x1eae 10065#define mmDC_I2C_TRANSACTION0_BASE_IDX 2 10066#define mmDC_I2C_TRANSACTION1 0x1eaf 10067#define mmDC_I2C_TRANSACTION1_BASE_IDX 2 10068#define mmDC_I2C_TRANSACTION2 0x1eb0 10069#define mmDC_I2C_TRANSACTION2_BASE_IDX 2 10070#define mmDC_I2C_TRANSACTION3 0x1eb1 10071#define mmDC_I2C_TRANSACTION3_BASE_IDX 2 10072#define mmDC_I2C_DATA 0x1eb2 10073#define mmDC_I2C_DATA_BASE_IDX 2 10074#define mmDC_I2C_EDID_DETECT_CTRL 0x1eb6 10075#define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2 10076#define mmDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7 10077#define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2 10078 10079 10080// addressBlock: dce_dc_dio_dio_misc_dispdec 10081// base address: 0x0 10082#define mmDIO_SCRATCH0 0x1eca 10083#define mmDIO_SCRATCH0_BASE_IDX 2 10084#define mmDIO_SCRATCH1 0x1ecb 10085#define mmDIO_SCRATCH1_BASE_IDX 2 10086#define mmDIO_SCRATCH2 0x1ecc 10087#define mmDIO_SCRATCH2_BASE_IDX 2 10088#define mmDIO_SCRATCH3 0x1ecd 10089#define mmDIO_SCRATCH3_BASE_IDX 2 10090#define mmDIO_SCRATCH4 0x1ece 10091#define mmDIO_SCRATCH4_BASE_IDX 2 10092#define mmDIO_SCRATCH5 0x1ecf 10093#define mmDIO_SCRATCH5_BASE_IDX 2 10094#define mmDIO_SCRATCH6 0x1ed0 10095#define mmDIO_SCRATCH6_BASE_IDX 2 10096#define mmDIO_SCRATCH7 0x1ed1 10097#define mmDIO_SCRATCH7_BASE_IDX 2 10098#define mmDIO_MEM_PWR_STATUS 0x1edd 10099#define mmDIO_MEM_PWR_STATUS_BASE_IDX 2 10100#define mmDIO_MEM_PWR_CTRL 0x1ede 10101#define mmDIO_MEM_PWR_CTRL_BASE_IDX 2 10102#define mmDIO_MEM_PWR_CTRL2 0x1edf 10103#define mmDIO_MEM_PWR_CTRL2_BASE_IDX 2 10104#define mmDIO_CLK_CNTL 0x1ee0 10105#define mmDIO_CLK_CNTL_BASE_IDX 2 10106#define mmDIO_POWER_MANAGEMENT_CNTL 0x1ee4 10107#define mmDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2 10108#define mmDIG_SOFT_RESET 0x1eee 10109#define mmDIG_SOFT_RESET_BASE_IDX 2 10110#define mmDIO_CLK_CNTL2 0x1ef2 10111#define mmDIO_CLK_CNTL2_BASE_IDX 2 10112#define mmDIO_CLK_CNTL3 0x1ef3 10113#define mmDIO_CLK_CNTL3_BASE_IDX 2 10114#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff 10115#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2 10116#define mmDIO_GENERIC_INTERRUPT_MESSAGE 0x1f02 10117#define mmDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2 10118#define mmDIO_GENERIC_INTERRUPT_CLEAR 0x1f03 10119#define mmDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2 10120 10121 10122// addressBlock: dce_dc_dio_hpd0_dispdec 10123// base address: 0x0 10124#define mmHPD0_DC_HPD_INT_STATUS 0x1f14 10125#define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX 2 10126#define mmHPD0_DC_HPD_INT_CONTROL 0x1f15 10127#define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2 10128#define mmHPD0_DC_HPD_CONTROL 0x1f16 10129#define mmHPD0_DC_HPD_CONTROL_BASE_IDX 2 10130#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17 10131#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 10132#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18 10133#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 10134 10135 10136// addressBlock: dce_dc_dio_hpd1_dispdec 10137// base address: 0x20 10138#define mmHPD1_DC_HPD_INT_STATUS 0x1f1c 10139#define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX 2 10140#define mmHPD1_DC_HPD_INT_CONTROL 0x1f1d 10141#define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2 10142#define mmHPD1_DC_HPD_CONTROL 0x1f1e 10143#define mmHPD1_DC_HPD_CONTROL_BASE_IDX 2 10144#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f 10145#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 10146#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20 10147#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 10148 10149 10150// addressBlock: dce_dc_dio_hpd2_dispdec 10151// base address: 0x40 10152#define mmHPD2_DC_HPD_INT_STATUS 0x1f24 10153#define mmHPD2_DC_HPD_INT_STATUS_BASE_IDX 2 10154#define mmHPD2_DC_HPD_INT_CONTROL 0x1f25 10155#define mmHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2 10156#define mmHPD2_DC_HPD_CONTROL 0x1f26 10157#define mmHPD2_DC_HPD_CONTROL_BASE_IDX 2 10158#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1f27 10159#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 10160#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1f28 10161#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 10162 10163 10164// addressBlock: dce_dc_dio_hpd3_dispdec 10165// base address: 0x60 10166#define mmHPD3_DC_HPD_INT_STATUS 0x1f2c 10167#define mmHPD3_DC_HPD_INT_STATUS_BASE_IDX 2 10168#define mmHPD3_DC_HPD_INT_CONTROL 0x1f2d 10169#define mmHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2 10170#define mmHPD3_DC_HPD_CONTROL 0x1f2e 10171#define mmHPD3_DC_HPD_CONTROL_BASE_IDX 2 10172#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1f2f 10173#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 10174#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1f30 10175#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 10176 10177 10178// addressBlock: dce_dc_dio_hpd4_dispdec 10179// base address: 0x80 10180#define mmHPD4_DC_HPD_INT_STATUS 0x1f34 10181#define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX 2 10182#define mmHPD4_DC_HPD_INT_CONTROL 0x1f35 10183#define mmHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2 10184#define mmHPD4_DC_HPD_CONTROL 0x1f36 10185#define mmHPD4_DC_HPD_CONTROL_BASE_IDX 2 10186#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1f37 10187#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 10188#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1f38 10189#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 10190 10191 10192// addressBlock: dce_dc_dio_hpd5_dispdec 10193// base address: 0xa0 10194#define mmHPD5_DC_HPD_INT_STATUS 0x1f3c 10195#define mmHPD5_DC_HPD_INT_STATUS_BASE_IDX 2 10196#define mmHPD5_DC_HPD_INT_CONTROL 0x1f3d 10197#define mmHPD5_DC_HPD_INT_CONTROL_BASE_IDX 2 10198#define mmHPD5_DC_HPD_CONTROL 0x1f3e 10199#define mmHPD5_DC_HPD_CONTROL_BASE_IDX 2 10200#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x1f3f 10201#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 10202#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x1f40 10203#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 10204 10205 10206// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec 10207// base address: 0x7d10 10208#define mmDC_PERFMON20_PERFCOUNTER_CNTL 0x1f44 10209#define mmDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX 2 10210#define mmDC_PERFMON20_PERFCOUNTER_CNTL2 0x1f45 10211#define mmDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX 2 10212#define mmDC_PERFMON20_PERFCOUNTER_STATE 0x1f46 10213#define mmDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX 2 10214#define mmDC_PERFMON20_PERFMON_CNTL 0x1f47 10215#define mmDC_PERFMON20_PERFMON_CNTL_BASE_IDX 2 10216#define mmDC_PERFMON20_PERFMON_CNTL2 0x1f48 10217#define mmDC_PERFMON20_PERFMON_CNTL2_BASE_IDX 2 10218#define mmDC_PERFMON20_PERFMON_CVALUE_INT_MISC 0x1f49 10219#define mmDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 10220#define mmDC_PERFMON20_PERFMON_CVALUE_LOW 0x1f4a 10221#define mmDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX 2 10222#define mmDC_PERFMON20_PERFMON_HI 0x1f4b 10223#define mmDC_PERFMON20_PERFMON_HI_BASE_IDX 2 10224#define mmDC_PERFMON20_PERFMON_LOW 0x1f4c 10225#define mmDC_PERFMON20_PERFMON_LOW_BASE_IDX 2 10226 10227 10228// addressBlock: dce_dc_dio_dp_aux0_dispdec 10229// base address: 0x0 10230#define mmDP_AUX0_AUX_CONTROL 0x1f50 10231#define mmDP_AUX0_AUX_CONTROL_BASE_IDX 2 10232#define mmDP_AUX0_AUX_SW_CONTROL 0x1f51 10233#define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2 10234#define mmDP_AUX0_AUX_ARB_CONTROL 0x1f52 10235#define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2 10236#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53 10237#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2 10238#define mmDP_AUX0_AUX_SW_STATUS 0x1f54 10239#define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX 2 10240#define mmDP_AUX0_AUX_LS_STATUS 0x1f55 10241#define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX 2 10242#define mmDP_AUX0_AUX_SW_DATA 0x1f56 10243#define mmDP_AUX0_AUX_SW_DATA_BASE_IDX 2 10244#define mmDP_AUX0_AUX_LS_DATA 0x1f57 10245#define mmDP_AUX0_AUX_LS_DATA_BASE_IDX 2 10246#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58 10247#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 10248#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59 10249#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2 10250#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a 10251#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 10252#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b 10253#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 10254#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c 10255#define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2 10256#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d 10257#define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2 10258#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x1f5e 10259#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 10260#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1f5f 10261#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 10262#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f60 10263#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 10264#define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1f61 10265#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2 10266#define mmDP_AUX0_AUX_PHY_WAKE_CNTL 0x1f66 10267#define mmDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX 2 10268 10269 10270// addressBlock: dce_dc_dio_dp_aux1_dispdec 10271// base address: 0x70 10272#define mmDP_AUX1_AUX_CONTROL 0x1f6c 10273#define mmDP_AUX1_AUX_CONTROL_BASE_IDX 2 10274#define mmDP_AUX1_AUX_SW_CONTROL 0x1f6d 10275#define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2 10276#define mmDP_AUX1_AUX_ARB_CONTROL 0x1f6e 10277#define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2 10278#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f 10279#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2 10280#define mmDP_AUX1_AUX_SW_STATUS 0x1f70 10281#define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX 2 10282#define mmDP_AUX1_AUX_LS_STATUS 0x1f71 10283#define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX 2 10284#define mmDP_AUX1_AUX_SW_DATA 0x1f72 10285#define mmDP_AUX1_AUX_SW_DATA_BASE_IDX 2 10286#define mmDP_AUX1_AUX_LS_DATA 0x1f73 10287#define mmDP_AUX1_AUX_LS_DATA_BASE_IDX 2 10288#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74 10289#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 10290#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75 10291#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2 10292#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76 10293#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 10294#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77 10295#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 10296#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78 10297#define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2 10298#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79 10299#define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2 10300#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x1f7a 10301#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 10302#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1f7b 10303#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 10304#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f7c 10305#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 10306#define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x1f7d 10307#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2 10308#define mmDP_AUX1_AUX_PHY_WAKE_CNTL 0x1f82 10309#define mmDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX 2 10310 10311 10312// addressBlock: dce_dc_dio_dp_aux2_dispdec 10313// base address: 0xe0 10314#define mmDP_AUX2_AUX_CONTROL 0x1f88 10315#define mmDP_AUX2_AUX_CONTROL_BASE_IDX 2 10316#define mmDP_AUX2_AUX_SW_CONTROL 0x1f89 10317#define mmDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2 10318#define mmDP_AUX2_AUX_ARB_CONTROL 0x1f8a 10319#define mmDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2 10320#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x1f8b 10321#define mmDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2 10322#define mmDP_AUX2_AUX_SW_STATUS 0x1f8c 10323#define mmDP_AUX2_AUX_SW_STATUS_BASE_IDX 2 10324#define mmDP_AUX2_AUX_LS_STATUS 0x1f8d 10325#define mmDP_AUX2_AUX_LS_STATUS_BASE_IDX 2 10326#define mmDP_AUX2_AUX_SW_DATA 0x1f8e 10327#define mmDP_AUX2_AUX_SW_DATA_BASE_IDX 2 10328#define mmDP_AUX2_AUX_LS_DATA 0x1f8f 10329#define mmDP_AUX2_AUX_LS_DATA_BASE_IDX 2 10330#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x1f90 10331#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 10332#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x1f91 10333#define mmDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2 10334#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x1f92 10335#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 10336#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x1f93 10337#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 10338#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x1f94 10339#define mmDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2 10340#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x1f95 10341#define mmDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2 10342#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x1f96 10343#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 10344#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x1f97 10345#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 10346#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f98 10347#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 10348#define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x1f99 10349#define mmDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2 10350#define mmDP_AUX2_AUX_PHY_WAKE_CNTL 0x1f9e 10351#define mmDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX 2 10352 10353 10354// addressBlock: dce_dc_dio_dp_aux3_dispdec 10355// base address: 0x150 10356#define mmDP_AUX3_AUX_CONTROL 0x1fa4 10357#define mmDP_AUX3_AUX_CONTROL_BASE_IDX 2 10358#define mmDP_AUX3_AUX_SW_CONTROL 0x1fa5 10359#define mmDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2 10360#define mmDP_AUX3_AUX_ARB_CONTROL 0x1fa6 10361#define mmDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2 10362#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x1fa7 10363#define mmDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2 10364#define mmDP_AUX3_AUX_SW_STATUS 0x1fa8 10365#define mmDP_AUX3_AUX_SW_STATUS_BASE_IDX 2 10366#define mmDP_AUX3_AUX_LS_STATUS 0x1fa9 10367#define mmDP_AUX3_AUX_LS_STATUS_BASE_IDX 2 10368#define mmDP_AUX3_AUX_SW_DATA 0x1faa 10369#define mmDP_AUX3_AUX_SW_DATA_BASE_IDX 2 10370#define mmDP_AUX3_AUX_LS_DATA 0x1fab 10371#define mmDP_AUX3_AUX_LS_DATA_BASE_IDX 2 10372#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x1fac 10373#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 10374#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x1fad 10375#define mmDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2 10376#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1fae 10377#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 10378#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1faf 10379#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 10380#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x1fb0 10381#define mmDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2 10382#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x1fb1 10383#define mmDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2 10384#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x1fb2 10385#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 10386#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x1fb3 10387#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 10388#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fb4 10389#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 10390#define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x1fb5 10391#define mmDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2 10392#define mmDP_AUX3_AUX_PHY_WAKE_CNTL 0x1fba 10393#define mmDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX 2 10394 10395 10396// addressBlock: dce_dc_dio_dp_aux4_dispdec 10397// base address: 0x1c0 10398#define mmDP_AUX4_AUX_CONTROL 0x1fc0 10399#define mmDP_AUX4_AUX_CONTROL_BASE_IDX 2 10400#define mmDP_AUX4_AUX_SW_CONTROL 0x1fc1 10401#define mmDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2 10402#define mmDP_AUX4_AUX_ARB_CONTROL 0x1fc2 10403#define mmDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2 10404#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x1fc3 10405#define mmDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2 10406#define mmDP_AUX4_AUX_SW_STATUS 0x1fc4 10407#define mmDP_AUX4_AUX_SW_STATUS_BASE_IDX 2 10408#define mmDP_AUX4_AUX_LS_STATUS 0x1fc5 10409#define mmDP_AUX4_AUX_LS_STATUS_BASE_IDX 2 10410#define mmDP_AUX4_AUX_SW_DATA 0x1fc6 10411#define mmDP_AUX4_AUX_SW_DATA_BASE_IDX 2 10412#define mmDP_AUX4_AUX_LS_DATA 0x1fc7 10413#define mmDP_AUX4_AUX_LS_DATA_BASE_IDX 2 10414#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x1fc8 10415#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 10416#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x1fc9 10417#define mmDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2 10418#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x1fca 10419#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 10420#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x1fcb 10421#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 10422#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x1fcc 10423#define mmDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2 10424#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x1fcd 10425#define mmDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2 10426#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x1fce 10427#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 10428#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x1fcf 10429#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 10430#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fd0 10431#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 10432#define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x1fd1 10433#define mmDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2 10434#define mmDP_AUX4_AUX_PHY_WAKE_CNTL 0x1fd6 10435#define mmDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX 2 10436 10437 10438// addressBlock: dce_dc_dio_dp_aux5_dispdec 10439// base address: 0x230 10440#define mmDP_AUX5_AUX_CONTROL 0x1fdc 10441#define mmDP_AUX5_AUX_CONTROL_BASE_IDX 2 10442#define mmDP_AUX5_AUX_SW_CONTROL 0x1fdd 10443#define mmDP_AUX5_AUX_SW_CONTROL_BASE_IDX 2 10444#define mmDP_AUX5_AUX_ARB_CONTROL 0x1fde 10445#define mmDP_AUX5_AUX_ARB_CONTROL_BASE_IDX 2 10446#define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x1fdf 10447#define mmDP_AUX5_AUX_INTERRUPT_CONTROL_BASE_IDX 2 10448#define mmDP_AUX5_AUX_SW_STATUS 0x1fe0 10449#define mmDP_AUX5_AUX_SW_STATUS_BASE_IDX 2 10450#define mmDP_AUX5_AUX_LS_STATUS 0x1fe1 10451#define mmDP_AUX5_AUX_LS_STATUS_BASE_IDX 2 10452#define mmDP_AUX5_AUX_SW_DATA 0x1fe2 10453#define mmDP_AUX5_AUX_SW_DATA_BASE_IDX 2 10454#define mmDP_AUX5_AUX_LS_DATA 0x1fe3 10455#define mmDP_AUX5_AUX_LS_DATA_BASE_IDX 2 10456#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x1fe4 10457#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 10458#define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x1fe5 10459#define mmDP_AUX5_AUX_DPHY_TX_CONTROL_BASE_IDX 2 10460#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x1fe6 10461#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 10462#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x1fe7 10463#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 10464#define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x1fe8 10465#define mmDP_AUX5_AUX_DPHY_TX_STATUS_BASE_IDX 2 10466#define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x1fe9 10467#define mmDP_AUX5_AUX_DPHY_RX_STATUS_BASE_IDX 2 10468#define mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x1fea 10469#define mmDP_AUX5_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 10470#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x1feb 10471#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 10472#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fec 10473#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 10474#define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x1fed 10475#define mmDP_AUX5_AUX_GTC_SYNC_STATUS_BASE_IDX 2 10476#define mmDP_AUX5_AUX_PHY_WAKE_CNTL 0x1ff2 10477#define mmDP_AUX5_AUX_PHY_WAKE_CNTL_BASE_IDX 2 10478 10479 10480// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec 10481// base address: 0x154a0 10482#define mmVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2068 10483#define mmVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 10484#define mmVPG0_VPG_GENERIC_PACKET_DATA 0x2069 10485#define mmVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 10486#define mmVPG0_VPG_GSP_FRAME_UPDATE_CTRL 0x206a 10487#define mmVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 10488#define mmVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x206b 10489#define mmVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 10490#define mmVPG0_VPG_GENERIC_STATUS 0x206c 10491#define mmVPG0_VPG_GENERIC_STATUS_BASE_IDX 2 10492#define mmVPG0_VPG_MEM_PWR 0x206d 10493#define mmVPG0_VPG_MEM_PWR_BASE_IDX 2 10494#define mmVPG0_VPG_ISRC1_2_ACCESS_CTRL 0x206e 10495#define mmVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 10496#define mmVPG0_VPG_ISRC1_2_DATA 0x206f 10497#define mmVPG0_VPG_ISRC1_2_DATA_BASE_IDX 2 10498#define mmVPG0_VPG_MPEG_INFO0 0x2070 10499#define mmVPG0_VPG_MPEG_INFO0_BASE_IDX 2 10500#define mmVPG0_VPG_MPEG_INFO1 0x2071 10501#define mmVPG0_VPG_MPEG_INFO1_BASE_IDX 2 10502 10503 10504// addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec 10505// base address: 0x154cc 10506#define mmAFMT0_AFMT_VBI_PACKET_CONTROL 0x2074 10507#define mmAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 10508#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL2 0x2075 10509#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 10510#define mmAFMT0_AFMT_AUDIO_INFO0 0x2076 10511#define mmAFMT0_AFMT_AUDIO_INFO0_BASE_IDX 2 10512#define mmAFMT0_AFMT_AUDIO_INFO1 0x2077 10513#define mmAFMT0_AFMT_AUDIO_INFO1_BASE_IDX 2 10514#define mmAFMT0_AFMT_60958_0 0x2078 10515#define mmAFMT0_AFMT_60958_0_BASE_IDX 2 10516#define mmAFMT0_AFMT_60958_1 0x2079 10517#define mmAFMT0_AFMT_60958_1_BASE_IDX 2 10518#define mmAFMT0_AFMT_AUDIO_CRC_CONTROL 0x207a 10519#define mmAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 10520#define mmAFMT0_AFMT_RAMP_CONTROL0 0x207b 10521#define mmAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX 2 10522#define mmAFMT0_AFMT_RAMP_CONTROL1 0x207c 10523#define mmAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX 2 10524#define mmAFMT0_AFMT_RAMP_CONTROL2 0x207d 10525#define mmAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX 2 10526#define mmAFMT0_AFMT_RAMP_CONTROL3 0x207e 10527#define mmAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX 2 10528#define mmAFMT0_AFMT_60958_2 0x207f 10529#define mmAFMT0_AFMT_60958_2_BASE_IDX 2 10530#define mmAFMT0_AFMT_AUDIO_CRC_RESULT 0x2080 10531#define mmAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 10532#define mmAFMT0_AFMT_STATUS 0x2081 10533#define mmAFMT0_AFMT_STATUS_BASE_IDX 2 10534#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL 0x2082 10535#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 10536#define mmAFMT0_AFMT_INFOFRAME_CONTROL0 0x2083 10537#define mmAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 10538#define mmAFMT0_AFMT_INTERRUPT_STATUS 0x2084 10539#define mmAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX 2 10540#define mmAFMT0_AFMT_AUDIO_SRC_CONTROL 0x2085 10541#define mmAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 10542#define mmAFMT0_AFMT_MEM_PWR 0x2087 10543#define mmAFMT0_AFMT_MEM_PWR_BASE_IDX 2 10544 10545 10546// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec 10547// base address: 0x15524 10548#define mmDME0_DME_CONTROL 0x2089 10549#define mmDME0_DME_CONTROL_BASE_IDX 2 10550#define mmDME0_DME_MEMORY_CONTROL 0x208a 10551#define mmDME0_DME_MEMORY_CONTROL_BASE_IDX 2 10552 10553 10554// addressBlock: dce_dc_dio_dig0_dispdec 10555// base address: 0x0 10556#define mmDIG0_DIG_FE_CNTL 0x208b 10557#define mmDIG0_DIG_FE_CNTL_BASE_IDX 2 10558#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x208c 10559#define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 10560#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x208d 10561#define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 10562#define mmDIG0_DIG_CLOCK_PATTERN 0x208e 10563#define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2 10564#define mmDIG0_DIG_TEST_PATTERN 0x208f 10565#define mmDIG0_DIG_TEST_PATTERN_BASE_IDX 2 10566#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x2090 10567#define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 10568#define mmDIG0_DIG_FIFO_STATUS 0x2091 10569#define mmDIG0_DIG_FIFO_STATUS_BASE_IDX 2 10570#define mmDIG0_HDMI_METADATA_PACKET_CONTROL 0x2092 10571#define mmDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 10572#define mmDIG0_HDMI_CONTROL 0x2093 10573#define mmDIG0_HDMI_CONTROL_BASE_IDX 2 10574#define mmDIG0_HDMI_STATUS 0x2094 10575#define mmDIG0_HDMI_STATUS_BASE_IDX 2 10576#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x2095 10577#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 10578#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x2096 10579#define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 10580#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x2097 10581#define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 10582#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x2098 10583#define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 10584#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x2099 10585#define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 10586#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x209a 10587#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 10588#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL6 0x209b 10589#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 10590#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5 0x209c 10591#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 10592#define mmDIG0_HDMI_GC 0x209d 10593#define mmDIG0_HDMI_GC_BASE_IDX 2 10594#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x209e 10595#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 10596#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x209f 10597#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 10598#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x20a0 10599#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 10600#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4 0x20a1 10601#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 10602#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL7 0x20a2 10603#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 10604#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL8 0x20a3 10605#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 10606#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL9 0x20a4 10607#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 10608#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL10 0x20a5 10609#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 10610#define mmDIG0_HDMI_DB_CONTROL 0x20a6 10611#define mmDIG0_HDMI_DB_CONTROL_BASE_IDX 2 10612#define mmDIG0_HDMI_ACR_32_0 0x20a7 10613#define mmDIG0_HDMI_ACR_32_0_BASE_IDX 2 10614#define mmDIG0_HDMI_ACR_32_1 0x20a8 10615#define mmDIG0_HDMI_ACR_32_1_BASE_IDX 2 10616#define mmDIG0_HDMI_ACR_44_0 0x20a9 10617#define mmDIG0_HDMI_ACR_44_0_BASE_IDX 2 10618#define mmDIG0_HDMI_ACR_44_1 0x20aa 10619#define mmDIG0_HDMI_ACR_44_1_BASE_IDX 2 10620#define mmDIG0_HDMI_ACR_48_0 0x20ab 10621#define mmDIG0_HDMI_ACR_48_0_BASE_IDX 2 10622#define mmDIG0_HDMI_ACR_48_1 0x20ac 10623#define mmDIG0_HDMI_ACR_48_1_BASE_IDX 2 10624#define mmDIG0_HDMI_ACR_STATUS_0 0x20ad 10625#define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2 10626#define mmDIG0_HDMI_ACR_STATUS_1 0x20ae 10627#define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2 10628#define mmDIG0_AFMT_CNTL 0x20af 10629#define mmDIG0_AFMT_CNTL_BASE_IDX 2 10630#define mmDIG0_DIG_BE_CNTL 0x20b0 10631#define mmDIG0_DIG_BE_CNTL_BASE_IDX 2 10632#define mmDIG0_DIG_BE_EN_CNTL 0x20b1 10633#define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX 2 10634#define mmDIG0_TMDS_CNTL 0x20d7 10635#define mmDIG0_TMDS_CNTL_BASE_IDX 2 10636#define mmDIG0_TMDS_CONTROL_CHAR 0x20d8 10637#define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2 10638#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x20d9 10639#define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 10640#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20da 10641#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 10642#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20db 10643#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 10644#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20dc 10645#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 10646#define mmDIG0_TMDS_CTL_BITS 0x20de 10647#define mmDIG0_TMDS_CTL_BITS_BASE_IDX 2 10648#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x20df 10649#define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 10650#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR 0x20e0 10651#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 10652#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x20e1 10653#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 10654#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x20e2 10655#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 10656#define mmDIG0_DIG_VERSION 0x20e4 10657#define mmDIG0_DIG_VERSION_BASE_IDX 2 10658#define mmDIG0_DIG_LANE_ENABLE 0x20e5 10659#define mmDIG0_DIG_LANE_ENABLE_BASE_IDX 2 10660#define mmDIG0_FORCE_DIG_DISABLE 0x20e6 10661#define mmDIG0_FORCE_DIG_DISABLE_BASE_IDX 2 10662 10663// addressBlock: dce_dc_dio_dp0_dispdec 10664// base address: 0x0 10665#define mmDP0_DP_LINK_CNTL 0x2108 10666#define mmDP0_DP_LINK_CNTL_BASE_IDX 2 10667#define mmDP0_DP_PIXEL_FORMAT 0x2109 10668#define mmDP0_DP_PIXEL_FORMAT_BASE_IDX 2 10669#define mmDP0_DP_MSA_COLORIMETRY 0x210a 10670#define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX 2 10671#define mmDP0_DP_CONFIG 0x210b 10672#define mmDP0_DP_CONFIG_BASE_IDX 2 10673#define mmDP0_DP_VID_STREAM_CNTL 0x210c 10674#define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX 2 10675#define mmDP0_DP_STEER_FIFO 0x210d 10676#define mmDP0_DP_STEER_FIFO_BASE_IDX 2 10677#define mmDP0_DP_MSA_MISC 0x210e 10678#define mmDP0_DP_MSA_MISC_BASE_IDX 2 10679#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 10680#define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 10681#define mmDP0_DP_VID_TIMING 0x2110 10682#define mmDP0_DP_VID_TIMING_BASE_IDX 2 10683#define mmDP0_DP_VID_N 0x2111 10684#define mmDP0_DP_VID_N_BASE_IDX 2 10685#define mmDP0_DP_VID_M 0x2112 10686#define mmDP0_DP_VID_M_BASE_IDX 2 10687#define mmDP0_DP_LINK_FRAMING_CNTL 0x2113 10688#define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2 10689#define mmDP0_DP_HBR2_EYE_PATTERN 0x2114 10690#define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2 10691#define mmDP0_DP_VID_MSA_VBID 0x2115 10692#define mmDP0_DP_VID_MSA_VBID_BASE_IDX 2 10693#define mmDP0_DP_VID_INTERRUPT_CNTL 0x2116 10694#define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 10695#define mmDP0_DP_DPHY_CNTL 0x2117 10696#define mmDP0_DP_DPHY_CNTL_BASE_IDX 2 10697#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x2118 10698#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 10699#define mmDP0_DP_DPHY_SYM0 0x2119 10700#define mmDP0_DP_DPHY_SYM0_BASE_IDX 2 10701#define mmDP0_DP_DPHY_SYM1 0x211a 10702#define mmDP0_DP_DPHY_SYM1_BASE_IDX 2 10703#define mmDP0_DP_DPHY_SYM2 0x211b 10704#define mmDP0_DP_DPHY_SYM2_BASE_IDX 2 10705#define mmDP0_DP_DPHY_8B10B_CNTL 0x211c 10706#define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2 10707#define mmDP0_DP_DPHY_PRBS_CNTL 0x211d 10708#define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2 10709#define mmDP0_DP_DPHY_SCRAM_CNTL 0x211e 10710#define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 10711#define mmDP0_DP_DPHY_CRC_EN 0x211f 10712#define mmDP0_DP_DPHY_CRC_EN_BASE_IDX 2 10713#define mmDP0_DP_DPHY_CRC_CNTL 0x2120 10714#define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2 10715#define mmDP0_DP_DPHY_CRC_RESULT 0x2121 10716#define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2 10717#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x2122 10718#define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 10719#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x2123 10720#define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 10721#define mmDP0_DP_DPHY_FAST_TRAINING 0x2124 10722#define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2 10723#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x2125 10724#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 10725#define mmDP0_DP_SEC_CNTL 0x212b 10726#define mmDP0_DP_SEC_CNTL_BASE_IDX 2 10727#define mmDP0_DP_SEC_CNTL1 0x212c 10728#define mmDP0_DP_SEC_CNTL1_BASE_IDX 2 10729#define mmDP0_DP_SEC_FRAMING1 0x212d 10730#define mmDP0_DP_SEC_FRAMING1_BASE_IDX 2 10731#define mmDP0_DP_SEC_FRAMING2 0x212e 10732#define mmDP0_DP_SEC_FRAMING2_BASE_IDX 2 10733#define mmDP0_DP_SEC_FRAMING3 0x212f 10734#define mmDP0_DP_SEC_FRAMING3_BASE_IDX 2 10735#define mmDP0_DP_SEC_FRAMING4 0x2130 10736#define mmDP0_DP_SEC_FRAMING4_BASE_IDX 2 10737#define mmDP0_DP_SEC_AUD_N 0x2131 10738#define mmDP0_DP_SEC_AUD_N_BASE_IDX 2 10739#define mmDP0_DP_SEC_AUD_N_READBACK 0x2132 10740#define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2 10741#define mmDP0_DP_SEC_AUD_M 0x2133 10742#define mmDP0_DP_SEC_AUD_M_BASE_IDX 2 10743#define mmDP0_DP_SEC_AUD_M_READBACK 0x2134 10744#define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2 10745#define mmDP0_DP_SEC_TIMESTAMP 0x2135 10746#define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX 2 10747#define mmDP0_DP_SEC_PACKET_CNTL 0x2136 10748#define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2 10749#define mmDP0_DP_MSE_RATE_CNTL 0x2137 10750#define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX 2 10751#define mmDP0_DP_MSE_RATE_UPDATE 0x2139 10752#define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2 10753#define mmDP0_DP_MSE_SAT0 0x213a 10754#define mmDP0_DP_MSE_SAT0_BASE_IDX 2 10755#define mmDP0_DP_MSE_SAT1 0x213b 10756#define mmDP0_DP_MSE_SAT1_BASE_IDX 2 10757#define mmDP0_DP_MSE_SAT2 0x213c 10758#define mmDP0_DP_MSE_SAT2_BASE_IDX 2 10759#define mmDP0_DP_MSE_SAT_UPDATE 0x213d 10760#define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2 10761#define mmDP0_DP_MSE_LINK_TIMING 0x213e 10762#define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX 2 10763#define mmDP0_DP_MSE_MISC_CNTL 0x213f 10764#define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX 2 10765#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x2144 10766#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 10767#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x2145 10768#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 10769#define mmDP0_DP_MSE_SAT0_STATUS 0x2147 10770#define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2 10771#define mmDP0_DP_MSE_SAT1_STATUS 0x2148 10772#define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2 10773#define mmDP0_DP_MSE_SAT2_STATUS 0x2149 10774#define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2 10775#define mmDP0_DP_MSA_TIMING_PARAM1 0x214c 10776#define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2 10777#define mmDP0_DP_MSA_TIMING_PARAM2 0x214d 10778#define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2 10779#define mmDP0_DP_MSA_TIMING_PARAM3 0x214e 10780#define mmDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2 10781#define mmDP0_DP_MSA_TIMING_PARAM4 0x214f 10782#define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2 10783#define mmDP0_DP_MSO_CNTL 0x2150 10784#define mmDP0_DP_MSO_CNTL_BASE_IDX 2 10785#define mmDP0_DP_MSO_CNTL1 0x2151 10786#define mmDP0_DP_MSO_CNTL1_BASE_IDX 2 10787#define mmDP0_DP_DSC_CNTL 0x2152 10788#define mmDP0_DP_DSC_CNTL_BASE_IDX 2 10789#define mmDP0_DP_SEC_CNTL2 0x2153 10790#define mmDP0_DP_SEC_CNTL2_BASE_IDX 2 10791#define mmDP0_DP_SEC_CNTL3 0x2154 10792#define mmDP0_DP_SEC_CNTL3_BASE_IDX 2 10793#define mmDP0_DP_SEC_CNTL4 0x2155 10794#define mmDP0_DP_SEC_CNTL4_BASE_IDX 2 10795#define mmDP0_DP_SEC_CNTL5 0x2156 10796#define mmDP0_DP_SEC_CNTL5_BASE_IDX 2 10797#define mmDP0_DP_SEC_CNTL6 0x2157 10798#define mmDP0_DP_SEC_CNTL6_BASE_IDX 2 10799#define mmDP0_DP_SEC_CNTL7 0x2158 10800#define mmDP0_DP_SEC_CNTL7_BASE_IDX 2 10801#define mmDP0_DP_DB_CNTL 0x2159 10802#define mmDP0_DP_DB_CNTL_BASE_IDX 2 10803#define mmDP0_DP_MSA_VBID_MISC 0x215a 10804#define mmDP0_DP_MSA_VBID_MISC_BASE_IDX 2 10805#define mmDP0_DP_SEC_METADATA_TRANSMISSION 0x215b 10806#define mmDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 10807#define mmDP0_DP_DSC_BYTES_PER_PIXEL 0x215c 10808#define mmDP0_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 10809#define mmDP0_DP_ALPM_CNTL 0x215d 10810#define mmDP0_DP_ALPM_CNTL_BASE_IDX 2 10811#define mmDP0_DP_GSP8_CNTL 0x215e 10812#define mmDP0_DP_GSP8_CNTL_BASE_IDX 2 10813#define mmDP0_DP_GSP9_CNTL 0x215f 10814#define mmDP0_DP_GSP9_CNTL_BASE_IDX 2 10815#define mmDP0_DP_GSP10_CNTL 0x2160 10816#define mmDP0_DP_GSP10_CNTL_BASE_IDX 2 10817#define mmDP0_DP_GSP11_CNTL 0x2161 10818#define mmDP0_DP_GSP11_CNTL_BASE_IDX 2 10819#define mmDP0_DP_GSP_EN_DB_STATUS 0x2162 10820#define mmDP0_DP_GSP_EN_DB_STATUS_BASE_IDX 2 10821 10822 10823// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec 10824// base address: 0x158a0 10825#define mmVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2168 10826#define mmVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 10827#define mmVPG1_VPG_GENERIC_PACKET_DATA 0x2169 10828#define mmVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 10829#define mmVPG1_VPG_GSP_FRAME_UPDATE_CTRL 0x216a 10830#define mmVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 10831#define mmVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x216b 10832#define mmVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 10833#define mmVPG1_VPG_GENERIC_STATUS 0x216c 10834#define mmVPG1_VPG_GENERIC_STATUS_BASE_IDX 2 10835#define mmVPG1_VPG_MEM_PWR 0x216d 10836#define mmVPG1_VPG_MEM_PWR_BASE_IDX 2 10837#define mmVPG1_VPG_ISRC1_2_ACCESS_CTRL 0x216e 10838#define mmVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 10839#define mmVPG1_VPG_ISRC1_2_DATA 0x216f 10840#define mmVPG1_VPG_ISRC1_2_DATA_BASE_IDX 2 10841#define mmVPG1_VPG_MPEG_INFO0 0x2170 10842#define mmVPG1_VPG_MPEG_INFO0_BASE_IDX 2 10843#define mmVPG1_VPG_MPEG_INFO1 0x2171 10844#define mmVPG1_VPG_MPEG_INFO1_BASE_IDX 2 10845 10846 10847// addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec 10848// base address: 0x158cc 10849#define mmAFMT1_AFMT_VBI_PACKET_CONTROL 0x2174 10850#define mmAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 10851#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL2 0x2175 10852#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 10853#define mmAFMT1_AFMT_AUDIO_INFO0 0x2176 10854#define mmAFMT1_AFMT_AUDIO_INFO0_BASE_IDX 2 10855#define mmAFMT1_AFMT_AUDIO_INFO1 0x2177 10856#define mmAFMT1_AFMT_AUDIO_INFO1_BASE_IDX 2 10857#define mmAFMT1_AFMT_60958_0 0x2178 10858#define mmAFMT1_AFMT_60958_0_BASE_IDX 2 10859#define mmAFMT1_AFMT_60958_1 0x2179 10860#define mmAFMT1_AFMT_60958_1_BASE_IDX 2 10861#define mmAFMT1_AFMT_AUDIO_CRC_CONTROL 0x217a 10862#define mmAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 10863#define mmAFMT1_AFMT_RAMP_CONTROL0 0x217b 10864#define mmAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX 2 10865#define mmAFMT1_AFMT_RAMP_CONTROL1 0x217c 10866#define mmAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX 2 10867#define mmAFMT1_AFMT_RAMP_CONTROL2 0x217d 10868#define mmAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX 2 10869#define mmAFMT1_AFMT_RAMP_CONTROL3 0x217e 10870#define mmAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX 2 10871#define mmAFMT1_AFMT_60958_2 0x217f 10872#define mmAFMT1_AFMT_60958_2_BASE_IDX 2 10873#define mmAFMT1_AFMT_AUDIO_CRC_RESULT 0x2180 10874#define mmAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 10875#define mmAFMT1_AFMT_STATUS 0x2181 10876#define mmAFMT1_AFMT_STATUS_BASE_IDX 2 10877#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL 0x2182 10878#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 10879#define mmAFMT1_AFMT_INFOFRAME_CONTROL0 0x2183 10880#define mmAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 10881#define mmAFMT1_AFMT_INTERRUPT_STATUS 0x2184 10882#define mmAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX 2 10883#define mmAFMT1_AFMT_AUDIO_SRC_CONTROL 0x2185 10884#define mmAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 10885#define mmAFMT1_AFMT_MEM_PWR 0x2187 10886#define mmAFMT1_AFMT_MEM_PWR_BASE_IDX 2 10887 10888 10889// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec 10890// base address: 0x15924 10891#define mmDME1_DME_CONTROL 0x2189 10892#define mmDME1_DME_CONTROL_BASE_IDX 2 10893#define mmDME1_DME_MEMORY_CONTROL 0x218a 10894#define mmDME1_DME_MEMORY_CONTROL_BASE_IDX 2 10895 10896 10897// addressBlock: dce_dc_dio_dig1_dispdec 10898// base address: 0x400 10899#define mmDIG1_DIG_FE_CNTL 0x218b 10900#define mmDIG1_DIG_FE_CNTL_BASE_IDX 2 10901#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x218c 10902#define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 10903#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x218d 10904#define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 10905#define mmDIG1_DIG_CLOCK_PATTERN 0x218e 10906#define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2 10907#define mmDIG1_DIG_TEST_PATTERN 0x218f 10908#define mmDIG1_DIG_TEST_PATTERN_BASE_IDX 2 10909#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x2190 10910#define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 10911#define mmDIG1_DIG_FIFO_STATUS 0x2191 10912#define mmDIG1_DIG_FIFO_STATUS_BASE_IDX 2 10913#define mmDIG1_HDMI_METADATA_PACKET_CONTROL 0x2192 10914#define mmDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 10915#define mmDIG1_HDMI_CONTROL 0x2193 10916#define mmDIG1_HDMI_CONTROL_BASE_IDX 2 10917#define mmDIG1_HDMI_STATUS 0x2194 10918#define mmDIG1_HDMI_STATUS_BASE_IDX 2 10919#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x2195 10920#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 10921#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x2196 10922#define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 10923#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x2197 10924#define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 10925#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x2198 10926#define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 10927#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x2199 10928#define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 10929#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x219a 10930#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 10931#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL6 0x219b 10932#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 10933#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5 0x219c 10934#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 10935#define mmDIG1_HDMI_GC 0x219d 10936#define mmDIG1_HDMI_GC_BASE_IDX 2 10937#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x219e 10938#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 10939#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x219f 10940#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 10941#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x21a0 10942#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 10943#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4 0x21a1 10944#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 10945#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL7 0x21a2 10946#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 10947#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL8 0x21a3 10948#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 10949#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL9 0x21a4 10950#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 10951#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL10 0x21a5 10952#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 10953#define mmDIG1_HDMI_DB_CONTROL 0x21a6 10954#define mmDIG1_HDMI_DB_CONTROL_BASE_IDX 2 10955#define mmDIG1_HDMI_ACR_32_0 0x21a7 10956#define mmDIG1_HDMI_ACR_32_0_BASE_IDX 2 10957#define mmDIG1_HDMI_ACR_32_1 0x21a8 10958#define mmDIG1_HDMI_ACR_32_1_BASE_IDX 2 10959#define mmDIG1_HDMI_ACR_44_0 0x21a9 10960#define mmDIG1_HDMI_ACR_44_0_BASE_IDX 2 10961#define mmDIG1_HDMI_ACR_44_1 0x21aa 10962#define mmDIG1_HDMI_ACR_44_1_BASE_IDX 2 10963#define mmDIG1_HDMI_ACR_48_0 0x21ab 10964#define mmDIG1_HDMI_ACR_48_0_BASE_IDX 2 10965#define mmDIG1_HDMI_ACR_48_1 0x21ac 10966#define mmDIG1_HDMI_ACR_48_1_BASE_IDX 2 10967#define mmDIG1_HDMI_ACR_STATUS_0 0x21ad 10968#define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2 10969#define mmDIG1_HDMI_ACR_STATUS_1 0x21ae 10970#define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2 10971#define mmDIG1_AFMT_CNTL 0x21af 10972#define mmDIG1_AFMT_CNTL_BASE_IDX 2 10973#define mmDIG1_DIG_BE_CNTL 0x21b0 10974#define mmDIG1_DIG_BE_CNTL_BASE_IDX 2 10975#define mmDIG1_DIG_BE_EN_CNTL 0x21b1 10976#define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX 2 10977#define mmDIG1_TMDS_CNTL 0x21d7 10978#define mmDIG1_TMDS_CNTL_BASE_IDX 2 10979#define mmDIG1_TMDS_CONTROL_CHAR 0x21d8 10980#define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2 10981#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x21d9 10982#define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 10983#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x21da 10984#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 10985#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x21db 10986#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 10987#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x21dc 10988#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 10989#define mmDIG1_TMDS_CTL_BITS 0x21de 10990#define mmDIG1_TMDS_CTL_BITS_BASE_IDX 2 10991#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x21df 10992#define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 10993#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR 0x21e0 10994#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 10995#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x21e1 10996#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 10997#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x21e2 10998#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 10999#define mmDIG1_DIG_VERSION 0x21e4 11000#define mmDIG1_DIG_VERSION_BASE_IDX 2
11001#define mmDIG1_DIG_LANE_ENABLE 0x21e5 11002#define mmDIG1_DIG_LANE_ENABLE_BASE_IDX 2 11003#define mmDIG1_FORCE_DIG_DISABLE 0x21e6 11004#define mmDIG1_FORCE_DIG_DISABLE_BASE_IDX 2 11005 11006// addressBlock: dce_dc_dio_dp1_dispdec 11007// base address: 0x400 11008#define mmDP1_DP_LINK_CNTL 0x2208 11009#define mmDP1_DP_LINK_CNTL_BASE_IDX 2 11010#define mmDP1_DP_PIXEL_FORMAT 0x2209 11011#define mmDP1_DP_PIXEL_FORMAT_BASE_IDX 2 11012#define mmDP1_DP_MSA_COLORIMETRY 0x220a 11013#define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX 2 11014#define mmDP1_DP_CONFIG 0x220b 11015#define mmDP1_DP_CONFIG_BASE_IDX 2 11016#define mmDP1_DP_VID_STREAM_CNTL 0x220c 11017#define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX 2 11018#define mmDP1_DP_STEER_FIFO 0x220d 11019#define mmDP1_DP_STEER_FIFO_BASE_IDX 2 11020#define mmDP1_DP_MSA_MISC 0x220e 11021#define mmDP1_DP_MSA_MISC_BASE_IDX 2 11022#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 11023#define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 11024#define mmDP1_DP_VID_TIMING 0x2210 11025#define mmDP1_DP_VID_TIMING_BASE_IDX 2 11026#define mmDP1_DP_VID_N 0x2211 11027#define mmDP1_DP_VID_N_BASE_IDX 2 11028#define mmDP1_DP_VID_M 0x2212 11029#define mmDP1_DP_VID_M_BASE_IDX 2 11030#define mmDP1_DP_LINK_FRAMING_CNTL 0x2213 11031#define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2 11032#define mmDP1_DP_HBR2_EYE_PATTERN 0x2214 11033#define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2 11034#define mmDP1_DP_VID_MSA_VBID 0x2215 11035#define mmDP1_DP_VID_MSA_VBID_BASE_IDX 2 11036#define mmDP1_DP_VID_INTERRUPT_CNTL 0x2216 11037#define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 11038#define mmDP1_DP_DPHY_CNTL 0x2217 11039#define mmDP1_DP_DPHY_CNTL_BASE_IDX 2 11040#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2218 11041#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 11042#define mmDP1_DP_DPHY_SYM0 0x2219 11043#define mmDP1_DP_DPHY_SYM0_BASE_IDX 2 11044#define mmDP1_DP_DPHY_SYM1 0x221a 11045#define mmDP1_DP_DPHY_SYM1_BASE_IDX 2 11046#define mmDP1_DP_DPHY_SYM2 0x221b 11047#define mmDP1_DP_DPHY_SYM2_BASE_IDX 2 11048#define mmDP1_DP_DPHY_8B10B_CNTL 0x221c 11049#define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2 11050#define mmDP1_DP_DPHY_PRBS_CNTL 0x221d 11051#define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2 11052#define mmDP1_DP_DPHY_SCRAM_CNTL 0x221e 11053#define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 11054#define mmDP1_DP_DPHY_CRC_EN 0x221f 11055#define mmDP1_DP_DPHY_CRC_EN_BASE_IDX 2 11056#define mmDP1_DP_DPHY_CRC_CNTL 0x2220 11057#define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2 11058#define mmDP1_DP_DPHY_CRC_RESULT 0x2221 11059#define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2 11060#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x2222 11061#define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 11062#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x2223 11063#define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 11064#define mmDP1_DP_DPHY_FAST_TRAINING 0x2224 11065#define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2 11066#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x2225 11067#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 11068#define mmDP1_DP_SEC_CNTL 0x222b 11069#define mmDP1_DP_SEC_CNTL_BASE_IDX 2 11070#define mmDP1_DP_SEC_CNTL1 0x222c 11071#define mmDP1_DP_SEC_CNTL1_BASE_IDX 2 11072#define mmDP1_DP_SEC_FRAMING1 0x222d 11073#define mmDP1_DP_SEC_FRAMING1_BASE_IDX 2 11074#define mmDP1_DP_SEC_FRAMING2 0x222e 11075#define mmDP1_DP_SEC_FRAMING2_BASE_IDX 2 11076#define mmDP1_DP_SEC_FRAMING3 0x222f 11077#define mmDP1_DP_SEC_FRAMING3_BASE_IDX 2 11078#define mmDP1_DP_SEC_FRAMING4 0x2230 11079#define mmDP1_DP_SEC_FRAMING4_BASE_IDX 2 11080#define mmDP1_DP_SEC_AUD_N 0x2231 11081#define mmDP1_DP_SEC_AUD_N_BASE_IDX 2 11082#define mmDP1_DP_SEC_AUD_N_READBACK 0x2232 11083#define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2 11084#define mmDP1_DP_SEC_AUD_M 0x2233 11085#define mmDP1_DP_SEC_AUD_M_BASE_IDX 2 11086#define mmDP1_DP_SEC_AUD_M_READBACK 0x2234 11087#define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2 11088#define mmDP1_DP_SEC_TIMESTAMP 0x2235 11089#define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX 2 11090#define mmDP1_DP_SEC_PACKET_CNTL 0x2236 11091#define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2 11092#define mmDP1_DP_MSE_RATE_CNTL 0x2237 11093#define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX 2 11094#define mmDP1_DP_MSE_RATE_UPDATE 0x2239 11095#define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2 11096#define mmDP1_DP_MSE_SAT0 0x223a 11097#define mmDP1_DP_MSE_SAT0_BASE_IDX 2 11098#define mmDP1_DP_MSE_SAT1 0x223b 11099#define mmDP1_DP_MSE_SAT1_BASE_IDX 2 11100#define mmDP1_DP_MSE_SAT2 0x223c 11101#define mmDP1_DP_MSE_SAT2_BASE_IDX 2 11102#define mmDP1_DP_MSE_SAT_UPDATE 0x223d 11103#define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2 11104#define mmDP1_DP_MSE_LINK_TIMING 0x223e 11105#define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX 2 11106#define mmDP1_DP_MSE_MISC_CNTL 0x223f 11107#define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX 2 11108#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x2244 11109#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 11110#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x2245 11111#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 11112#define mmDP1_DP_MSE_SAT0_STATUS 0x2247 11113#define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2 11114#define mmDP1_DP_MSE_SAT1_STATUS 0x2248 11115#define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2 11116#define mmDP1_DP_MSE_SAT2_STATUS 0x2249 11117#define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2 11118#define mmDP1_DP_MSA_TIMING_PARAM1 0x224c 11119#define mmDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2 11120#define mmDP1_DP_MSA_TIMING_PARAM2 0x224d 11121#define mmDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2 11122#define mmDP1_DP_MSA_TIMING_PARAM3 0x224e 11123#define mmDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2 11124#define mmDP1_DP_MSA_TIMING_PARAM4 0x224f 11125#define mmDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2 11126#define mmDP1_DP_MSO_CNTL 0x2250 11127#define mmDP1_DP_MSO_CNTL_BASE_IDX 2 11128#define mmDP1_DP_MSO_CNTL1 0x2251 11129#define mmDP1_DP_MSO_CNTL1_BASE_IDX 2 11130#define mmDP1_DP_DSC_CNTL 0x2252 11131#define mmDP1_DP_DSC_CNTL_BASE_IDX 2 11132#define mmDP1_DP_SEC_CNTL2 0x2253 11133#define mmDP1_DP_SEC_CNTL2_BASE_IDX 2 11134#define mmDP1_DP_SEC_CNTL3 0x2254 11135#define mmDP1_DP_SEC_CNTL3_BASE_IDX 2 11136#define mmDP1_DP_SEC_CNTL4 0x2255 11137#define mmDP1_DP_SEC_CNTL4_BASE_IDX 2 11138#define mmDP1_DP_SEC_CNTL5 0x2256 11139#define mmDP1_DP_SEC_CNTL5_BASE_IDX 2 11140#define mmDP1_DP_SEC_CNTL6 0x2257 11141#define mmDP1_DP_SEC_CNTL6_BASE_IDX 2 11142#define mmDP1_DP_SEC_CNTL7 0x2258 11143#define mmDP1_DP_SEC_CNTL7_BASE_IDX 2 11144#define mmDP1_DP_DB_CNTL 0x2259 11145#define mmDP1_DP_DB_CNTL_BASE_IDX 2 11146#define mmDP1_DP_MSA_VBID_MISC 0x225a 11147#define mmDP1_DP_MSA_VBID_MISC_BASE_IDX 2 11148#define mmDP1_DP_SEC_METADATA_TRANSMISSION 0x225b 11149#define mmDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 11150#define mmDP1_DP_DSC_BYTES_PER_PIXEL 0x225c 11151#define mmDP1_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 11152#define mmDP1_DP_ALPM_CNTL 0x225d 11153#define mmDP1_DP_ALPM_CNTL_BASE_IDX 2 11154#define mmDP1_DP_GSP8_CNTL 0x225e 11155#define mmDP1_DP_GSP8_CNTL_BASE_IDX 2 11156#define mmDP1_DP_GSP9_CNTL 0x225f 11157#define mmDP1_DP_GSP9_CNTL_BASE_IDX 2 11158#define mmDP1_DP_GSP10_CNTL 0x2260 11159#define mmDP1_DP_GSP10_CNTL_BASE_IDX 2 11160#define mmDP1_DP_GSP11_CNTL 0x2261 11161#define mmDP1_DP_GSP11_CNTL_BASE_IDX 2 11162#define mmDP1_DP_GSP_EN_DB_STATUS 0x2262 11163#define mmDP1_DP_GSP_EN_DB_STATUS_BASE_IDX 2 11164 11165 11166// addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec 11167// base address: 0x15ca0 11168#define mmVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2268 11169#define mmVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11170#define mmVPG2_VPG_GENERIC_PACKET_DATA 0x2269 11171#define mmVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11172#define mmVPG2_VPG_GSP_FRAME_UPDATE_CTRL 0x226a 11173#define mmVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11174#define mmVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x226b 11175#define mmVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11176#define mmVPG2_VPG_GENERIC_STATUS 0x226c 11177#define mmVPG2_VPG_GENERIC_STATUS_BASE_IDX 2 11178#define mmVPG2_VPG_MEM_PWR 0x226d 11179#define mmVPG2_VPG_MEM_PWR_BASE_IDX 2 11180#define mmVPG2_VPG_ISRC1_2_ACCESS_CTRL 0x226e 11181#define mmVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11182#define mmVPG2_VPG_ISRC1_2_DATA 0x226f 11183#define mmVPG2_VPG_ISRC1_2_DATA_BASE_IDX 2 11184#define mmVPG2_VPG_MPEG_INFO0 0x2270 11185#define mmVPG2_VPG_MPEG_INFO0_BASE_IDX 2 11186#define mmVPG2_VPG_MPEG_INFO1 0x2271 11187#define mmVPG2_VPG_MPEG_INFO1_BASE_IDX 2 11188 11189 11190// addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec 11191// base address: 0x15ccc 11192#define mmAFMT2_AFMT_VBI_PACKET_CONTROL 0x2274 11193#define mmAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 11194#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL2 0x2275 11195#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 11196#define mmAFMT2_AFMT_AUDIO_INFO0 0x2276 11197#define mmAFMT2_AFMT_AUDIO_INFO0_BASE_IDX 2 11198#define mmAFMT2_AFMT_AUDIO_INFO1 0x2277 11199#define mmAFMT2_AFMT_AUDIO_INFO1_BASE_IDX 2 11200#define mmAFMT2_AFMT_60958_0 0x2278 11201#define mmAFMT2_AFMT_60958_0_BASE_IDX 2 11202#define mmAFMT2_AFMT_60958_1 0x2279 11203#define mmAFMT2_AFMT_60958_1_BASE_IDX 2 11204#define mmAFMT2_AFMT_AUDIO_CRC_CONTROL 0x227a 11205#define mmAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 11206#define mmAFMT2_AFMT_RAMP_CONTROL0 0x227b 11207#define mmAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX 2 11208#define mmAFMT2_AFMT_RAMP_CONTROL1 0x227c 11209#define mmAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX 2 11210#define mmAFMT2_AFMT_RAMP_CONTROL2 0x227d 11211#define mmAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX 2 11212#define mmAFMT2_AFMT_RAMP_CONTROL3 0x227e 11213#define mmAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX 2 11214#define mmAFMT2_AFMT_60958_2 0x227f 11215#define mmAFMT2_AFMT_60958_2_BASE_IDX 2 11216#define mmAFMT2_AFMT_AUDIO_CRC_RESULT 0x2280 11217#define mmAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 11218#define mmAFMT2_AFMT_STATUS 0x2281 11219#define mmAFMT2_AFMT_STATUS_BASE_IDX 2 11220#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL 0x2282 11221#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 11222#define mmAFMT2_AFMT_INFOFRAME_CONTROL0 0x2283 11223#define mmAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 11224#define mmAFMT2_AFMT_INTERRUPT_STATUS 0x2284 11225#define mmAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX 2 11226#define mmAFMT2_AFMT_AUDIO_SRC_CONTROL 0x2285 11227#define mmAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 11228#define mmAFMT2_AFMT_MEM_PWR 0x2287 11229#define mmAFMT2_AFMT_MEM_PWR_BASE_IDX 2 11230 11231 11232// addressBlock: dce_dc_dio_dig2_dme_dme_dispdec 11233// base address: 0x15d24 11234#define mmDME2_DME_CONTROL 0x2289 11235#define mmDME2_DME_CONTROL_BASE_IDX 2 11236#define mmDME2_DME_MEMORY_CONTROL 0x228a 11237#define mmDME2_DME_MEMORY_CONTROL_BASE_IDX 2 11238 11239 11240// addressBlock: dce_dc_dio_dig2_dispdec 11241// base address: 0x800 11242#define mmDIG2_DIG_FE_CNTL 0x228b 11243#define mmDIG2_DIG_FE_CNTL_BASE_IDX 2 11244#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x228c 11245#define mmDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 11246#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x228d 11247#define mmDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 11248#define mmDIG2_DIG_CLOCK_PATTERN 0x228e 11249#define mmDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2 11250#define mmDIG2_DIG_TEST_PATTERN 0x228f 11251#define mmDIG2_DIG_TEST_PATTERN_BASE_IDX 2 11252#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x2290 11253#define mmDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 11254#define mmDIG2_DIG_FIFO_STATUS 0x2291 11255#define mmDIG2_DIG_FIFO_STATUS_BASE_IDX 2 11256#define mmDIG2_HDMI_METADATA_PACKET_CONTROL 0x2292 11257#define mmDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 11258#define mmDIG2_HDMI_CONTROL 0x2293 11259#define mmDIG2_HDMI_CONTROL_BASE_IDX 2 11260#define mmDIG2_HDMI_STATUS 0x2294 11261#define mmDIG2_HDMI_STATUS_BASE_IDX 2 11262#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x2295 11263#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 11264#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x2296 11265#define mmDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 11266#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x2297 11267#define mmDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 11268#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x2298 11269#define mmDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 11270#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x2299 11271#define mmDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 11272#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x229a 11273#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 11274#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL6 0x229b 11275#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 11276#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL5 0x229c 11277#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 11278#define mmDIG2_HDMI_GC 0x229d 11279#define mmDIG2_HDMI_GC_BASE_IDX 2 11280#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x229e 11281#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 11282#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x229f 11283#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 11284#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x22a0 11285#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 11286#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL4 0x22a1 11287#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 11288#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL7 0x22a2 11289#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 11290#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL8 0x22a3 11291#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 11292#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL9 0x22a4 11293#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 11294#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL10 0x22a5 11295#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 11296#define mmDIG2_HDMI_DB_CONTROL 0x22a6 11297#define mmDIG2_HDMI_DB_CONTROL_BASE_IDX 2 11298#define mmDIG2_HDMI_ACR_32_0 0x22a7 11299#define mmDIG2_HDMI_ACR_32_0_BASE_IDX 2 11300#define mmDIG2_HDMI_ACR_32_1 0x22a8 11301#define mmDIG2_HDMI_ACR_32_1_BASE_IDX 2 11302#define mmDIG2_HDMI_ACR_44_0 0x22a9 11303#define mmDIG2_HDMI_ACR_44_0_BASE_IDX 2 11304#define mmDIG2_HDMI_ACR_44_1 0x22aa 11305#define mmDIG2_HDMI_ACR_44_1_BASE_IDX 2 11306#define mmDIG2_HDMI_ACR_48_0 0x22ab 11307#define mmDIG2_HDMI_ACR_48_0_BASE_IDX 2 11308#define mmDIG2_HDMI_ACR_48_1 0x22ac 11309#define mmDIG2_HDMI_ACR_48_1_BASE_IDX 2 11310#define mmDIG2_HDMI_ACR_STATUS_0 0x22ad 11311#define mmDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2 11312#define mmDIG2_HDMI_ACR_STATUS_1 0x22ae 11313#define mmDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2 11314#define mmDIG2_AFMT_CNTL 0x22af 11315#define mmDIG2_AFMT_CNTL_BASE_IDX 2 11316#define mmDIG2_DIG_BE_CNTL 0x22b0 11317#define mmDIG2_DIG_BE_CNTL_BASE_IDX 2 11318#define mmDIG2_DIG_BE_EN_CNTL 0x22b1 11319#define mmDIG2_DIG_BE_EN_CNTL_BASE_IDX 2 11320#define mmDIG2_TMDS_CNTL 0x22d7 11321#define mmDIG2_TMDS_CNTL_BASE_IDX 2 11322#define mmDIG2_TMDS_CONTROL_CHAR 0x22d8 11323#define mmDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2 11324#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x22d9 11325#define mmDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 11326#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x22da 11327#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 11328#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x22db 11329#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 11330#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x22dc 11331#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 11332#define mmDIG2_TMDS_CTL_BITS 0x22de 11333#define mmDIG2_TMDS_CTL_BITS_BASE_IDX 2 11334#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x22df 11335#define mmDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 11336#define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR 0x22e0 11337#define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 11338#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x22e1 11339#define mmDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 11340#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x22e2 11341#define mmDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 11342#define mmDIG2_DIG_VERSION 0x22e4 11343#define mmDIG2_DIG_VERSION_BASE_IDX 2 11344#define mmDIG2_DIG_LANE_ENABLE 0x22e5 11345#define mmDIG2_DIG_LANE_ENABLE_BASE_IDX 2 11346#define mmDIG2_FORCE_DIG_DISABLE 0x22e6 11347#define mmDIG2_FORCE_DIG_DISABLE_BASE_IDX 2 11348 11349// addressBlock: dce_dc_dio_dp2_dispdec 11350// base address: 0x800 11351#define mmDP2_DP_LINK_CNTL 0x2308 11352#define mmDP2_DP_LINK_CNTL_BASE_IDX 2 11353#define mmDP2_DP_PIXEL_FORMAT 0x2309 11354#define mmDP2_DP_PIXEL_FORMAT_BASE_IDX 2 11355#define mmDP2_DP_MSA_COLORIMETRY 0x230a 11356#define mmDP2_DP_MSA_COLORIMETRY_BASE_IDX 2 11357#define mmDP2_DP_CONFIG 0x230b 11358#define mmDP2_DP_CONFIG_BASE_IDX 2 11359#define mmDP2_DP_VID_STREAM_CNTL 0x230c 11360#define mmDP2_DP_VID_STREAM_CNTL_BASE_IDX 2 11361#define mmDP2_DP_STEER_FIFO 0x230d 11362#define mmDP2_DP_STEER_FIFO_BASE_IDX 2 11363#define mmDP2_DP_MSA_MISC 0x230e 11364#define mmDP2_DP_MSA_MISC_BASE_IDX 2 11365#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 11366#define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 11367#define mmDP2_DP_VID_TIMING 0x2310 11368#define mmDP2_DP_VID_TIMING_BASE_IDX 2 11369#define mmDP2_DP_VID_N 0x2311 11370#define mmDP2_DP_VID_N_BASE_IDX 2 11371#define mmDP2_DP_VID_M 0x2312 11372#define mmDP2_DP_VID_M_BASE_IDX 2 11373#define mmDP2_DP_LINK_FRAMING_CNTL 0x2313 11374#define mmDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2 11375#define mmDP2_DP_HBR2_EYE_PATTERN 0x2314 11376#define mmDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2 11377#define mmDP2_DP_VID_MSA_VBID 0x2315 11378#define mmDP2_DP_VID_MSA_VBID_BASE_IDX 2 11379#define mmDP2_DP_VID_INTERRUPT_CNTL 0x2316 11380#define mmDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 11381#define mmDP2_DP_DPHY_CNTL 0x2317 11382#define mmDP2_DP_DPHY_CNTL_BASE_IDX 2 11383#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2318 11384#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 11385#define mmDP2_DP_DPHY_SYM0 0x2319 11386#define mmDP2_DP_DPHY_SYM0_BASE_IDX 2 11387#define mmDP2_DP_DPHY_SYM1 0x231a 11388#define mmDP2_DP_DPHY_SYM1_BASE_IDX 2 11389#define mmDP2_DP_DPHY_SYM2 0x231b 11390#define mmDP2_DP_DPHY_SYM2_BASE_IDX 2 11391#define mmDP2_DP_DPHY_8B10B_CNTL 0x231c 11392#define mmDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2 11393#define mmDP2_DP_DPHY_PRBS_CNTL 0x231d 11394#define mmDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2 11395#define mmDP2_DP_DPHY_SCRAM_CNTL 0x231e 11396#define mmDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 11397#define mmDP2_DP_DPHY_CRC_EN 0x231f 11398#define mmDP2_DP_DPHY_CRC_EN_BASE_IDX 2 11399#define mmDP2_DP_DPHY_CRC_CNTL 0x2320 11400#define mmDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2 11401#define mmDP2_DP_DPHY_CRC_RESULT 0x2321 11402#define mmDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2 11403#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x2322 11404#define mmDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 11405#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x2323 11406#define mmDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 11407#define mmDP2_DP_DPHY_FAST_TRAINING 0x2324 11408#define mmDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2 11409#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x2325 11410#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 11411#define mmDP2_DP_SEC_CNTL 0x232b 11412#define mmDP2_DP_SEC_CNTL_BASE_IDX 2 11413#define mmDP2_DP_SEC_CNTL1 0x232c 11414#define mmDP2_DP_SEC_CNTL1_BASE_IDX 2 11415#define mmDP2_DP_SEC_FRAMING1 0x232d 11416#define mmDP2_DP_SEC_FRAMING1_BASE_IDX 2 11417#define mmDP2_DP_SEC_FRAMING2 0x232e 11418#define mmDP2_DP_SEC_FRAMING2_BASE_IDX 2 11419#define mmDP2_DP_SEC_FRAMING3 0x232f 11420#define mmDP2_DP_SEC_FRAMING3_BASE_IDX 2 11421#define mmDP2_DP_SEC_FRAMING4 0x2330 11422#define mmDP2_DP_SEC_FRAMING4_BASE_IDX 2 11423#define mmDP2_DP_SEC_AUD_N 0x2331 11424#define mmDP2_DP_SEC_AUD_N_BASE_IDX 2 11425#define mmDP2_DP_SEC_AUD_N_READBACK 0x2332 11426#define mmDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2 11427#define mmDP2_DP_SEC_AUD_M 0x2333 11428#define mmDP2_DP_SEC_AUD_M_BASE_IDX 2 11429#define mmDP2_DP_SEC_AUD_M_READBACK 0x2334 11430#define mmDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2 11431#define mmDP2_DP_SEC_TIMESTAMP 0x2335 11432#define mmDP2_DP_SEC_TIMESTAMP_BASE_IDX 2 11433#define mmDP2_DP_SEC_PACKET_CNTL 0x2336 11434#define mmDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2 11435#define mmDP2_DP_MSE_RATE_CNTL 0x2337 11436#define mmDP2_DP_MSE_RATE_CNTL_BASE_IDX 2 11437#define mmDP2_DP_MSE_RATE_UPDATE 0x2339 11438#define mmDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2 11439#define mmDP2_DP_MSE_SAT0 0x233a 11440#define mmDP2_DP_MSE_SAT0_BASE_IDX 2 11441#define mmDP2_DP_MSE_SAT1 0x233b 11442#define mmDP2_DP_MSE_SAT1_BASE_IDX 2 11443#define mmDP2_DP_MSE_SAT2 0x233c 11444#define mmDP2_DP_MSE_SAT2_BASE_IDX 2 11445#define mmDP2_DP_MSE_SAT_UPDATE 0x233d 11446#define mmDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2 11447#define mmDP2_DP_MSE_LINK_TIMING 0x233e 11448#define mmDP2_DP_MSE_LINK_TIMING_BASE_IDX 2 11449#define mmDP2_DP_MSE_MISC_CNTL 0x233f 11450#define mmDP2_DP_MSE_MISC_CNTL_BASE_IDX 2 11451#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x2344 11452#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 11453#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x2345 11454#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 11455#define mmDP2_DP_MSE_SAT0_STATUS 0x2347 11456#define mmDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2 11457#define mmDP2_DP_MSE_SAT1_STATUS 0x2348 11458#define mmDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2 11459#define mmDP2_DP_MSE_SAT2_STATUS 0x2349 11460#define mmDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2 11461#define mmDP2_DP_MSA_TIMING_PARAM1 0x234c 11462#define mmDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2 11463#define mmDP2_DP_MSA_TIMING_PARAM2 0x234d 11464#define mmDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2 11465#define mmDP2_DP_MSA_TIMING_PARAM3 0x234e 11466#define mmDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2 11467#define mmDP2_DP_MSA_TIMING_PARAM4 0x234f 11468#define mmDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2 11469#define mmDP2_DP_MSO_CNTL 0x2350 11470#define mmDP2_DP_MSO_CNTL_BASE_IDX 2 11471#define mmDP2_DP_MSO_CNTL1 0x2351 11472#define mmDP2_DP_MSO_CNTL1_BASE_IDX 2 11473#define mmDP2_DP_DSC_CNTL 0x2352 11474#define mmDP2_DP_DSC_CNTL_BASE_IDX 2 11475#define mmDP2_DP_SEC_CNTL2 0x2353 11476#define mmDP2_DP_SEC_CNTL2_BASE_IDX 2 11477#define mmDP2_DP_SEC_CNTL3 0x2354 11478#define mmDP2_DP_SEC_CNTL3_BASE_IDX 2 11479#define mmDP2_DP_SEC_CNTL4 0x2355 11480#define mmDP2_DP_SEC_CNTL4_BASE_IDX 2 11481#define mmDP2_DP_SEC_CNTL5 0x2356 11482#define mmDP2_DP_SEC_CNTL5_BASE_IDX 2 11483#define mmDP2_DP_SEC_CNTL6 0x2357 11484#define mmDP2_DP_SEC_CNTL6_BASE_IDX 2 11485#define mmDP2_DP_SEC_CNTL7 0x2358 11486#define mmDP2_DP_SEC_CNTL7_BASE_IDX 2 11487#define mmDP2_DP_DB_CNTL 0x2359 11488#define mmDP2_DP_DB_CNTL_BASE_IDX 2 11489#define mmDP2_DP_MSA_VBID_MISC 0x235a 11490#define mmDP2_DP_MSA_VBID_MISC_BASE_IDX 2 11491#define mmDP2_DP_SEC_METADATA_TRANSMISSION 0x235b 11492#define mmDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 11493#define mmDP2_DP_DSC_BYTES_PER_PIXEL 0x235c 11494#define mmDP2_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 11495#define mmDP2_DP_ALPM_CNTL 0x235d 11496#define mmDP2_DP_ALPM_CNTL_BASE_IDX 2 11497#define mmDP2_DP_GSP8_CNTL 0x235e 11498#define mmDP2_DP_GSP8_CNTL_BASE_IDX 2 11499#define mmDP2_DP_GSP9_CNTL 0x235f 11500#define mmDP2_DP_GSP9_CNTL_BASE_IDX 2 11501#define mmDP2_DP_GSP10_CNTL 0x2360 11502#define mmDP2_DP_GSP10_CNTL_BASE_IDX 2 11503#define mmDP2_DP_GSP11_CNTL 0x2361 11504#define mmDP2_DP_GSP11_CNTL_BASE_IDX 2 11505#define mmDP2_DP_GSP_EN_DB_STATUS 0x2362 11506#define mmDP2_DP_GSP_EN_DB_STATUS_BASE_IDX 2 11507 11508 11509// addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec 11510// base address: 0x160a0 11511#define mmVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2368 11512#define mmVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11513#define mmVPG3_VPG_GENERIC_PACKET_DATA 0x2369 11514#define mmVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11515#define mmVPG3_VPG_GSP_FRAME_UPDATE_CTRL 0x236a 11516#define mmVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11517#define mmVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x236b 11518#define mmVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11519#define mmVPG3_VPG_GENERIC_STATUS 0x236c 11520#define mmVPG3_VPG_GENERIC_STATUS_BASE_IDX 2 11521#define mmVPG3_VPG_MEM_PWR 0x236d 11522#define mmVPG3_VPG_MEM_PWR_BASE_IDX 2 11523#define mmVPG3_VPG_ISRC1_2_ACCESS_CTRL 0x236e 11524#define mmVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11525#define mmVPG3_VPG_ISRC1_2_DATA 0x236f 11526#define mmVPG3_VPG_ISRC1_2_DATA_BASE_IDX 2 11527#define mmVPG3_VPG_MPEG_INFO0 0x2370 11528#define mmVPG3_VPG_MPEG_INFO0_BASE_IDX 2 11529#define mmVPG3_VPG_MPEG_INFO1 0x2371 11530#define mmVPG3_VPG_MPEG_INFO1_BASE_IDX 2 11531 11532 11533// addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec 11534// base address: 0x160cc 11535#define mmAFMT3_AFMT_VBI_PACKET_CONTROL 0x2374 11536#define mmAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 11537#define mmAFMT3_AFMT_AUDIO_PACKET_CONTROL2 0x2375 11538#define mmAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 11539#define mmAFMT3_AFMT_AUDIO_INFO0 0x2376 11540#define mmAFMT3_AFMT_AUDIO_INFO0_BASE_IDX 2 11541#define mmAFMT3_AFMT_AUDIO_INFO1 0x2377 11542#define mmAFMT3_AFMT_AUDIO_INFO1_BASE_IDX 2 11543#define mmAFMT3_AFMT_60958_0 0x2378 11544#define mmAFMT3_AFMT_60958_0_BASE_IDX 2 11545#define mmAFMT3_AFMT_60958_1 0x2379 11546#define mmAFMT3_AFMT_60958_1_BASE_IDX 2 11547#define mmAFMT3_AFMT_AUDIO_CRC_CONTROL 0x237a 11548#define mmAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 11549#define mmAFMT3_AFMT_RAMP_CONTROL0 0x237b 11550#define mmAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX 2 11551#define mmAFMT3_AFMT_RAMP_CONTROL1 0x237c 11552#define mmAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX 2 11553#define mmAFMT3_AFMT_RAMP_CONTROL2 0x237d 11554#define mmAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX 2 11555#define mmAFMT3_AFMT_RAMP_CONTROL3 0x237e 11556#define mmAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX 2 11557#define mmAFMT3_AFMT_60958_2 0x237f 11558#define mmAFMT3_AFMT_60958_2_BASE_IDX 2 11559#define mmAFMT3_AFMT_AUDIO_CRC_RESULT 0x2380 11560#define mmAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 11561#define mmAFMT3_AFMT_STATUS 0x2381 11562#define mmAFMT3_AFMT_STATUS_BASE_IDX 2 11563#define mmAFMT3_AFMT_AUDIO_PACKET_CONTROL 0x2382 11564#define mmAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 11565#define mmAFMT3_AFMT_INFOFRAME_CONTROL0 0x2383 11566#define mmAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 11567#define mmAFMT3_AFMT_INTERRUPT_STATUS 0x2384 11568#define mmAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX 2 11569#define mmAFMT3_AFMT_AUDIO_SRC_CONTROL 0x2385 11570#define mmAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 11571#define mmAFMT3_AFMT_MEM_PWR 0x2387 11572#define mmAFMT3_AFMT_MEM_PWR_BASE_IDX 2 11573 11574 11575// addressBlock: dce_dc_dio_dig3_dme_dme_dispdec 11576// base address: 0x16124 11577#define mmDME3_DME_CONTROL 0x2389 11578#define mmDME3_DME_CONTROL_BASE_IDX 2 11579#define mmDME3_DME_MEMORY_CONTROL 0x238a 11580#define mmDME3_DME_MEMORY_CONTROL_BASE_IDX 2 11581 11582 11583// addressBlock: dce_dc_dio_dig3_dispdec 11584// base address: 0xc00 11585#define mmDIG3_DIG_FE_CNTL 0x238b 11586#define mmDIG3_DIG_FE_CNTL_BASE_IDX 2 11587#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x238c 11588#define mmDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 11589#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x238d 11590#define mmDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 11591#define mmDIG3_DIG_CLOCK_PATTERN 0x238e 11592#define mmDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2 11593#define mmDIG3_DIG_TEST_PATTERN 0x238f 11594#define mmDIG3_DIG_TEST_PATTERN_BASE_IDX 2 11595#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x2390 11596#define mmDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 11597#define mmDIG3_DIG_FIFO_STATUS 0x2391 11598#define mmDIG3_DIG_FIFO_STATUS_BASE_IDX 2 11599#define mmDIG3_HDMI_METADATA_PACKET_CONTROL 0x2392 11600#define mmDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 11601#define mmDIG3_HDMI_CONTROL 0x2393 11602#define mmDIG3_HDMI_CONTROL_BASE_IDX 2 11603#define mmDIG3_HDMI_STATUS 0x2394 11604#define mmDIG3_HDMI_STATUS_BASE_IDX 2 11605#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x2395 11606#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 11607#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x2396 11608#define mmDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 11609#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x2397 11610#define mmDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 11611#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x2398 11612#define mmDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 11613#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x2399 11614#define mmDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 11615#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x239a 11616#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 11617#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL6 0x239b 11618#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 11619#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL5 0x239c 11620#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 11621#define mmDIG3_HDMI_GC 0x239d 11622#define mmDIG3_HDMI_GC_BASE_IDX 2 11623#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x239e 11624#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 11625#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x239f 11626#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 11627#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x23a0 11628#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 11629#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL4 0x23a1 11630#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 11631#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL7 0x23a2 11632#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 11633#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL8 0x23a3 11634#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 11635#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL9 0x23a4 11636#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 11637#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL10 0x23a5 11638#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 11639#define mmDIG3_HDMI_DB_CONTROL 0x23a6 11640#define mmDIG3_HDMI_DB_CONTROL_BASE_IDX 2 11641#define mmDIG3_HDMI_ACR_32_0 0x23a7 11642#define mmDIG3_HDMI_ACR_32_0_BASE_IDX 2 11643#define mmDIG3_HDMI_ACR_32_1 0x23a8 11644#define mmDIG3_HDMI_ACR_32_1_BASE_IDX 2 11645#define mmDIG3_HDMI_ACR_44_0 0x23a9 11646#define mmDIG3_HDMI_ACR_44_0_BASE_IDX 2 11647#define mmDIG3_HDMI_ACR_44_1 0x23aa 11648#define mmDIG3_HDMI_ACR_44_1_BASE_IDX 2 11649#define mmDIG3_HDMI_ACR_48_0 0x23ab 11650#define mmDIG3_HDMI_ACR_48_0_BASE_IDX 2 11651#define mmDIG3_HDMI_ACR_48_1 0x23ac 11652#define mmDIG3_HDMI_ACR_48_1_BASE_IDX 2 11653#define mmDIG3_HDMI_ACR_STATUS_0 0x23ad 11654#define mmDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2 11655#define mmDIG3_HDMI_ACR_STATUS_1 0x23ae 11656#define mmDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2 11657#define mmDIG3_AFMT_CNTL 0x23af 11658#define mmDIG3_AFMT_CNTL_BASE_IDX 2 11659#define mmDIG3_DIG_BE_CNTL 0x23b0 11660#define mmDIG3_DIG_BE_CNTL_BASE_IDX 2 11661#define mmDIG3_DIG_BE_EN_CNTL 0x23b1 11662#define mmDIG3_DIG_BE_EN_CNTL_BASE_IDX 2 11663#define mmDIG3_TMDS_CNTL 0x23d7 11664#define mmDIG3_TMDS_CNTL_BASE_IDX 2 11665#define mmDIG3_TMDS_CONTROL_CHAR 0x23d8 11666#define mmDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2 11667#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x23d9 11668#define mmDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 11669#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x23da 11670#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 11671#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x23db 11672#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 11673#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x23dc 11674#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 11675#define mmDIG3_TMDS_CTL_BITS 0x23de 11676#define mmDIG3_TMDS_CTL_BITS_BASE_IDX 2 11677#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x23df 11678#define mmDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 11679#define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR 0x23e0 11680#define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 11681#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x23e1 11682#define mmDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 11683#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x23e2 11684#define mmDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 11685#define mmDIG3_DIG_VERSION 0x23e4 11686#define mmDIG3_DIG_VERSION_BASE_IDX 2 11687#define mmDIG3_DIG_LANE_ENABLE 0x23e5 11688#define mmDIG3_DIG_LANE_ENABLE_BASE_IDX 2 11689#define mmDIG3_FORCE_DIG_DISABLE 0x23e6 11690#define mmDIG3_FORCE_DIG_DISABLE_BASE_IDX 2 11691 11692 11693// addressBlock: dce_dc_dio_dp3_dispdec 11694// base address: 0xc00 11695#define mmDP3_DP_LINK_CNTL 0x2408 11696#define mmDP3_DP_LINK_CNTL_BASE_IDX 2 11697#define mmDP3_DP_PIXEL_FORMAT 0x2409 11698#define mmDP3_DP_PIXEL_FORMAT_BASE_IDX 2 11699#define mmDP3_DP_MSA_COLORIMETRY 0x240a 11700#define mmDP3_DP_MSA_COLORIMETRY_BASE_IDX 2 11701#define mmDP3_DP_CONFIG 0x240b 11702#define mmDP3_DP_CONFIG_BASE_IDX 2 11703#define mmDP3_DP_VID_STREAM_CNTL 0x240c 11704#define mmDP3_DP_VID_STREAM_CNTL_BASE_IDX 2 11705#define mmDP3_DP_STEER_FIFO 0x240d 11706#define mmDP3_DP_STEER_FIFO_BASE_IDX 2 11707#define mmDP3_DP_MSA_MISC 0x240e 11708#define mmDP3_DP_MSA_MISC_BASE_IDX 2 11709#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 11710#define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 11711#define mmDP3_DP_VID_TIMING 0x2410 11712#define mmDP3_DP_VID_TIMING_BASE_IDX 2 11713#define mmDP3_DP_VID_N 0x2411 11714#define mmDP3_DP_VID_N_BASE_IDX 2 11715#define mmDP3_DP_VID_M 0x2412 11716#define mmDP3_DP_VID_M_BASE_IDX 2 11717#define mmDP3_DP_LINK_FRAMING_CNTL 0x2413 11718#define mmDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2 11719#define mmDP3_DP_HBR2_EYE_PATTERN 0x2414 11720#define mmDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2 11721#define mmDP3_DP_VID_MSA_VBID 0x2415 11722#define mmDP3_DP_VID_MSA_VBID_BASE_IDX 2 11723#define mmDP3_DP_VID_INTERRUPT_CNTL 0x2416 11724#define mmDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 11725#define mmDP3_DP_DPHY_CNTL 0x2417 11726#define mmDP3_DP_DPHY_CNTL_BASE_IDX 2 11727#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x2418 11728#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 11729#define mmDP3_DP_DPHY_SYM0 0x2419 11730#define mmDP3_DP_DPHY_SYM0_BASE_IDX 2 11731#define mmDP3_DP_DPHY_SYM1 0x241a 11732#define mmDP3_DP_DPHY_SYM1_BASE_IDX 2 11733#define mmDP3_DP_DPHY_SYM2 0x241b 11734#define mmDP3_DP_DPHY_SYM2_BASE_IDX 2 11735#define mmDP3_DP_DPHY_8B10B_CNTL 0x241c 11736#define mmDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2 11737#define mmDP3_DP_DPHY_PRBS_CNTL 0x241d 11738#define mmDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2 11739#define mmDP3_DP_DPHY_SCRAM_CNTL 0x241e 11740#define mmDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 11741#define mmDP3_DP_DPHY_CRC_EN 0x241f 11742#define mmDP3_DP_DPHY_CRC_EN_BASE_IDX 2 11743#define mmDP3_DP_DPHY_CRC_CNTL 0x2420 11744#define mmDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2 11745#define mmDP3_DP_DPHY_CRC_RESULT 0x2421 11746#define mmDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2 11747#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x2422 11748#define mmDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 11749#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x2423 11750#define mmDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 11751#define mmDP3_DP_DPHY_FAST_TRAINING 0x2424 11752#define mmDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2 11753#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x2425 11754#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 11755#define mmDP3_DP_SEC_CNTL 0x242b 11756#define mmDP3_DP_SEC_CNTL_BASE_IDX 2 11757#define mmDP3_DP_SEC_CNTL1 0x242c 11758#define mmDP3_DP_SEC_CNTL1_BASE_IDX 2 11759#define mmDP3_DP_SEC_FRAMING1 0x242d 11760#define mmDP3_DP_SEC_FRAMING1_BASE_IDX 2 11761#define mmDP3_DP_SEC_FRAMING2 0x242e 11762#define mmDP3_DP_SEC_FRAMING2_BASE_IDX 2 11763#define mmDP3_DP_SEC_FRAMING3 0x242f 11764#define mmDP3_DP_SEC_FRAMING3_BASE_IDX 2 11765#define mmDP3_DP_SEC_FRAMING4 0x2430 11766#define mmDP3_DP_SEC_FRAMING4_BASE_IDX 2 11767#define mmDP3_DP_SEC_AUD_N 0x2431 11768#define mmDP3_DP_SEC_AUD_N_BASE_IDX 2 11769#define mmDP3_DP_SEC_AUD_N_READBACK 0x2432 11770#define mmDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2 11771#define mmDP3_DP_SEC_AUD_M 0x2433 11772#define mmDP3_DP_SEC_AUD_M_BASE_IDX 2 11773#define mmDP3_DP_SEC_AUD_M_READBACK 0x2434 11774#define mmDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2 11775#define mmDP3_DP_SEC_TIMESTAMP 0x2435 11776#define mmDP3_DP_SEC_TIMESTAMP_BASE_IDX 2 11777#define mmDP3_DP_SEC_PACKET_CNTL 0x2436 11778#define mmDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2 11779#define mmDP3_DP_MSE_RATE_CNTL 0x2437 11780#define mmDP3_DP_MSE_RATE_CNTL_BASE_IDX 2 11781#define mmDP3_DP_MSE_RATE_UPDATE 0x2439 11782#define mmDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2 11783#define mmDP3_DP_MSE_SAT0 0x243a 11784#define mmDP3_DP_MSE_SAT0_BASE_IDX 2 11785#define mmDP3_DP_MSE_SAT1 0x243b 11786#define mmDP3_DP_MSE_SAT1_BASE_IDX 2 11787#define mmDP3_DP_MSE_SAT2 0x243c 11788#define mmDP3_DP_MSE_SAT2_BASE_IDX 2 11789#define mmDP3_DP_MSE_SAT_UPDATE 0x243d 11790#define mmDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2 11791#define mmDP3_DP_MSE_LINK_TIMING 0x243e 11792#define mmDP3_DP_MSE_LINK_TIMING_BASE_IDX 2 11793#define mmDP3_DP_MSE_MISC_CNTL 0x243f 11794#define mmDP3_DP_MSE_MISC_CNTL_BASE_IDX 2 11795#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x2444 11796#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 11797#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x2445 11798#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 11799#define mmDP3_DP_MSE_SAT0_STATUS 0x2447 11800#define mmDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2 11801#define mmDP3_DP_MSE_SAT1_STATUS 0x2448 11802#define mmDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2 11803#define mmDP3_DP_MSE_SAT2_STATUS 0x2449 11804#define mmDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2 11805#define mmDP3_DP_MSA_TIMING_PARAM1 0x244c 11806#define mmDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2 11807#define mmDP3_DP_MSA_TIMING_PARAM2 0x244d 11808#define mmDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2 11809#define mmDP3_DP_MSA_TIMING_PARAM3 0x244e 11810#define mmDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2 11811#define mmDP3_DP_MSA_TIMING_PARAM4 0x244f 11812#define mmDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2 11813#define mmDP3_DP_MSO_CNTL 0x2450 11814#define mmDP3_DP_MSO_CNTL_BASE_IDX 2 11815#define mmDP3_DP_MSO_CNTL1 0x2451 11816#define mmDP3_DP_MSO_CNTL1_BASE_IDX 2 11817#define mmDP3_DP_DSC_CNTL 0x2452 11818#define mmDP3_DP_DSC_CNTL_BASE_IDX 2 11819#define mmDP3_DP_SEC_CNTL2 0x2453 11820#define mmDP3_DP_SEC_CNTL2_BASE_IDX 2 11821#define mmDP3_DP_SEC_CNTL3 0x2454 11822#define mmDP3_DP_SEC_CNTL3_BASE_IDX 2 11823#define mmDP3_DP_SEC_CNTL4 0x2455 11824#define mmDP3_DP_SEC_CNTL4_BASE_IDX 2 11825#define mmDP3_DP_SEC_CNTL5 0x2456 11826#define mmDP3_DP_SEC_CNTL5_BASE_IDX 2 11827#define mmDP3_DP_SEC_CNTL6 0x2457 11828#define mmDP3_DP_SEC_CNTL6_BASE_IDX 2 11829#define mmDP3_DP_SEC_CNTL7 0x2458 11830#define mmDP3_DP_SEC_CNTL7_BASE_IDX 2 11831#define mmDP3_DP_DB_CNTL 0x2459 11832#define mmDP3_DP_DB_CNTL_BASE_IDX 2 11833#define mmDP3_DP_MSA_VBID_MISC 0x245a 11834#define mmDP3_DP_MSA_VBID_MISC_BASE_IDX 2 11835#define mmDP3_DP_SEC_METADATA_TRANSMISSION 0x245b 11836#define mmDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 11837#define mmDP3_DP_DSC_BYTES_PER_PIXEL 0x245c 11838#define mmDP3_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 11839#define mmDP3_DP_ALPM_CNTL 0x245d 11840#define mmDP3_DP_ALPM_CNTL_BASE_IDX 2 11841#define mmDP3_DP_GSP8_CNTL 0x245e 11842#define mmDP3_DP_GSP8_CNTL_BASE_IDX 2 11843#define mmDP3_DP_GSP9_CNTL 0x245f 11844#define mmDP3_DP_GSP9_CNTL_BASE_IDX 2 11845#define mmDP3_DP_GSP10_CNTL 0x2460 11846#define mmDP3_DP_GSP10_CNTL_BASE_IDX 2 11847#define mmDP3_DP_GSP11_CNTL 0x2461 11848#define mmDP3_DP_GSP11_CNTL_BASE_IDX 2 11849#define mmDP3_DP_GSP_EN_DB_STATUS 0x2462 11850#define mmDP3_DP_GSP_EN_DB_STATUS_BASE_IDX 2 11851 11852 11853// addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec 11854// base address: 0x164a0 11855#define mmVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2468 11856#define mmVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11857#define mmVPG4_VPG_GENERIC_PACKET_DATA 0x2469 11858#define mmVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11859#define mmVPG4_VPG_GSP_FRAME_UPDATE_CTRL 0x246a 11860#define mmVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11861#define mmVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x246b 11862#define mmVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11863#define mmVPG4_VPG_GENERIC_STATUS 0x246c 11864#define mmVPG4_VPG_GENERIC_STATUS_BASE_IDX 2 11865#define mmVPG4_VPG_MEM_PWR 0x246d 11866#define mmVPG4_VPG_MEM_PWR_BASE_IDX 2 11867#define mmVPG4_VPG_ISRC1_2_ACCESS_CTRL 0x246e 11868#define mmVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11869#define mmVPG4_VPG_ISRC1_2_DATA 0x246f 11870#define mmVPG4_VPG_ISRC1_2_DATA_BASE_IDX 2 11871#define mmVPG4_VPG_MPEG_INFO0 0x2470 11872#define mmVPG4_VPG_MPEG_INFO0_BASE_IDX 2 11873#define mmVPG4_VPG_MPEG_INFO1 0x2471 11874#define mmVPG4_VPG_MPEG_INFO1_BASE_IDX 2 11875 11876 11877// addressBlock: dce_dc_dio_dig4_afmt_afmt_dispdec 11878#define mmAFMT4_AFMT_VBI_PACKET_CONTROL 0x2474 11879#define mmAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 11880#define mmAFMT4_AFMT_AUDIO_PACKET_CONTROL2 0x2475 11881#define mmAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 11882#define mmAFMT4_AFMT_AUDIO_INFO0 0x2476 11883#define mmAFMT4_AFMT_AUDIO_INFO0_BASE_IDX 2 11884#define mmAFMT4_AFMT_AUDIO_INFO1 0x2477 11885#define mmAFMT4_AFMT_AUDIO_INFO1_BASE_IDX 2 11886#define mmAFMT4_AFMT_60958_0 0x2478 11887#define mmAFMT4_AFMT_60958_0_BASE_IDX 2 11888#define mmAFMT4_AFMT_60958_1 0x2479 11889#define mmAFMT4_AFMT_60958_1_BASE_IDX 2 11890#define mmAFMT4_AFMT_AUDIO_CRC_CONTROL 0x247a 11891#define mmAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 11892#define mmAFMT4_AFMT_RAMP_CONTROL0 0x247b 11893#define mmAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX 2 11894#define mmAFMT4_AFMT_RAMP_CONTROL1 0x247c 11895#define mmAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX 2 11896#define mmAFMT4_AFMT_RAMP_CONTROL2 0x247d 11897#define mmAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX 2 11898#define mmAFMT4_AFMT_RAMP_CONTROL3 0x247e 11899#define mmAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX 2 11900#define mmAFMT4_AFMT_60958_2 0x247f 11901#define mmAFMT4_AFMT_60958_2_BASE_IDX 2 11902#define mmAFMT4_AFMT_AUDIO_CRC_RESULT 0x2480 11903#define mmAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 11904#define mmAFMT4_AFMT_STATUS 0x2481 11905#define mmAFMT4_AFMT_STATUS_BASE_IDX 2 11906#define mmAFMT4_AFMT_AUDIO_PACKET_CONTROL 0x2482 11907#define mmAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 11908#define mmAFMT4_AFMT_INFOFRAME_CONTROL0 0x2483 11909#define mmAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 11910#define mmAFMT4_AFMT_INTERRUPT_STATUS 0x2484 11911#define mmAFMT4_AFMT_INTERRUPT_STATUS_BASE_IDX 2 11912#define mmAFMT4_AFMT_AUDIO_SRC_CONTROL 0x2485 11913#define mmAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 11914#define mmAFMT4_AFMT_MEM_PWR 0x2487 11915#define mmAFMT4_AFMT_MEM_PWR_BASE_IDX 2 11916 11917 11918// addressBlock: dce_dc_dio_dig4_dme_dme_dispdec 11919// base address: 0x16524 11920#define mmDME4_DME_CONTROL 0x2489 11921#define mmDME4_DME_CONTROL_BASE_IDX 2 11922#define mmDME4_DME_MEMORY_CONTROL 0x248a 11923#define mmDME4_DME_MEMORY_CONTROL_BASE_IDX 2 11924 11925 11926// addressBlock: dce_dc_dio_dig4_dispdec 11927// base address: 0x1000 11928#define mmDIG4_DIG_FE_CNTL 0x248b 11929#define mmDIG4_DIG_FE_CNTL_BASE_IDX 2 11930#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x248c 11931#define mmDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 11932#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x248d 11933#define mmDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 11934#define mmDIG4_DIG_CLOCK_PATTERN 0x248e 11935#define mmDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2 11936#define mmDIG4_DIG_TEST_PATTERN 0x248f 11937#define mmDIG4_DIG_TEST_PATTERN_BASE_IDX 2 11938#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x2490 11939#define mmDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 11940#define mmDIG4_DIG_FIFO_STATUS 0x2491 11941#define mmDIG4_DIG_FIFO_STATUS_BASE_IDX 2 11942#define mmDIG4_HDMI_METADATA_PACKET_CONTROL 0x2492 11943#define mmDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 11944#define mmDIG4_HDMI_CONTROL 0x2493 11945#define mmDIG4_HDMI_CONTROL_BASE_IDX 2 11946#define mmDIG4_HDMI_STATUS 0x2494 11947#define mmDIG4_HDMI_STATUS_BASE_IDX 2 11948#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x2495 11949#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 11950#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x2496 11951#define mmDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 11952#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x2497 11953#define mmDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 11954#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x2498 11955#define mmDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 11956#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x2499 11957#define mmDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 11958#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x249a 11959#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 11960#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL6 0x249b 11961#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 11962#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL5 0x249c 11963#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 11964#define mmDIG4_HDMI_GC 0x249d 11965#define mmDIG4_HDMI_GC_BASE_IDX 2 11966#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x249e 11967#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 11968#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2 0x249f 11969#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 11970#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3 0x24a0 11971#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 11972#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL4 0x24a1 11973#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 11974#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL7 0x24a2 11975#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 11976#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL8 0x24a3 11977#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 11978#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL9 0x24a4 11979#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 11980#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL10 0x24a5 11981#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 11982#define mmDIG4_HDMI_DB_CONTROL 0x24a6 11983#define mmDIG4_HDMI_DB_CONTROL_BASE_IDX 2 11984#define mmDIG4_HDMI_ACR_32_0 0x24a7 11985#define mmDIG4_HDMI_ACR_32_0_BASE_IDX 2 11986#define mmDIG4_HDMI_ACR_32_1 0x24a8 11987#define mmDIG4_HDMI_ACR_32_1_BASE_IDX 2 11988#define mmDIG4_HDMI_ACR_44_0 0x24a9 11989#define mmDIG4_HDMI_ACR_44_0_BASE_IDX 2 11990#define mmDIG4_HDMI_ACR_44_1 0x24aa 11991#define mmDIG4_HDMI_ACR_44_1_BASE_IDX 2 11992#define mmDIG4_HDMI_ACR_48_0 0x24ab 11993#define mmDIG4_HDMI_ACR_48_0_BASE_IDX 2 11994#define mmDIG4_HDMI_ACR_48_1 0x24ac 11995#define mmDIG4_HDMI_ACR_48_1_BASE_IDX 2 11996#define mmDIG4_HDMI_ACR_STATUS_0 0x24ad 11997#define mmDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2 11998#define mmDIG4_HDMI_ACR_STATUS_1 0x24ae 11999#define mmDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2 12000#define mmDIG4_AFMT_CNTL 0x24af
12001#define mmDIG4_AFMT_CNTL_BASE_IDX 2 12002#define mmDIG4_DIG_BE_CNTL 0x24b0 12003#define mmDIG4_DIG_BE_CNTL_BASE_IDX 2 12004#define mmDIG4_DIG_BE_EN_CNTL 0x24b1 12005#define mmDIG4_DIG_BE_EN_CNTL_BASE_IDX 2 12006#define mmDIG4_TMDS_CNTL 0x24d7 12007#define mmDIG4_TMDS_CNTL_BASE_IDX 2 12008#define mmDIG4_TMDS_CONTROL_CHAR 0x24d8 12009#define mmDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2 12010#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x24d9 12011#define mmDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 12012#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x24da 12013#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 12014#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x24db 12015#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 12016#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x24dc 12017#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 12018#define mmDIG4_TMDS_CTL_BITS 0x24de 12019#define mmDIG4_TMDS_CTL_BITS_BASE_IDX 2 12020#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x24df 12021#define mmDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 12022#define mmDIG4_TMDS_SYNC_DCBALANCE_CHAR 0x24e0 12023#define mmDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 12024#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x24e1 12025#define mmDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 12026#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x24e2 12027#define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 12028#define mmDIG4_DIG_VERSION 0x24e4 12029#define mmDIG4_DIG_VERSION_BASE_IDX 2 12030#define mmDIG4_DIG_LANE_ENABLE 0x24e5 12031#define mmDIG4_DIG_LANE_ENABLE_BASE_IDX 2 12032#define mmDIG4_FORCE_DIG_DISABLE 0x24e6 12033#define mmDIG4_FORCE_DIG_DISABLE_BASE_IDX 2 12034 12035 12036// addressBlock: dce_dc_dio_dp4_dispdec 12037// base address: 0x1000 12038#define mmDP4_DP_LINK_CNTL 0x2508 12039#define mmDP4_DP_LINK_CNTL_BASE_IDX 2 12040#define mmDP4_DP_PIXEL_FORMAT 0x2509 12041#define mmDP4_DP_PIXEL_FORMAT_BASE_IDX 2 12042#define mmDP4_DP_MSA_COLORIMETRY 0x250a 12043#define mmDP4_DP_MSA_COLORIMETRY_BASE_IDX 2 12044#define mmDP4_DP_CONFIG 0x250b 12045#define mmDP4_DP_CONFIG_BASE_IDX 2 12046#define mmDP4_DP_VID_STREAM_CNTL 0x250c 12047#define mmDP4_DP_VID_STREAM_CNTL_BASE_IDX 2 12048#define mmDP4_DP_STEER_FIFO 0x250d 12049#define mmDP4_DP_STEER_FIFO_BASE_IDX 2 12050#define mmDP4_DP_MSA_MISC 0x250e 12051#define mmDP4_DP_MSA_MISC_BASE_IDX 2 12052#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 12053#define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 12054#define mmDP4_DP_VID_TIMING 0x2510 12055#define mmDP4_DP_VID_TIMING_BASE_IDX 2 12056#define mmDP4_DP_VID_N 0x2511 12057#define mmDP4_DP_VID_N_BASE_IDX 2 12058#define mmDP4_DP_VID_M 0x2512 12059#define mmDP4_DP_VID_M_BASE_IDX 2 12060#define mmDP4_DP_LINK_FRAMING_CNTL 0x2513 12061#define mmDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2 12062#define mmDP4_DP_HBR2_EYE_PATTERN 0x2514 12063#define mmDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2 12064#define mmDP4_DP_VID_MSA_VBID 0x2515 12065#define mmDP4_DP_VID_MSA_VBID_BASE_IDX 2 12066#define mmDP4_DP_VID_INTERRUPT_CNTL 0x2516 12067#define mmDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 12068#define mmDP4_DP_DPHY_CNTL 0x2517 12069#define mmDP4_DP_DPHY_CNTL_BASE_IDX 2 12070#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x2518 12071#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 12072#define mmDP4_DP_DPHY_SYM0 0x2519 12073#define mmDP4_DP_DPHY_SYM0_BASE_IDX 2 12074#define mmDP4_DP_DPHY_SYM1 0x251a 12075#define mmDP4_DP_DPHY_SYM1_BASE_IDX 2 12076#define mmDP4_DP_DPHY_SYM2 0x251b 12077#define mmDP4_DP_DPHY_SYM2_BASE_IDX 2 12078#define mmDP4_DP_DPHY_8B10B_CNTL 0x251c 12079#define mmDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2 12080#define mmDP4_DP_DPHY_PRBS_CNTL 0x251d 12081#define mmDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2 12082#define mmDP4_DP_DPHY_SCRAM_CNTL 0x251e 12083#define mmDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 12084#define mmDP4_DP_DPHY_CRC_EN 0x251f 12085#define mmDP4_DP_DPHY_CRC_EN_BASE_IDX 2 12086#define mmDP4_DP_DPHY_CRC_CNTL 0x2520 12087#define mmDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2 12088#define mmDP4_DP_DPHY_CRC_RESULT 0x2521 12089#define mmDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2 12090#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x2522 12091#define mmDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 12092#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x2523 12093#define mmDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 12094#define mmDP4_DP_DPHY_FAST_TRAINING 0x2524 12095#define mmDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2 12096#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x2525 12097#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 12098#define mmDP4_DP_SEC_CNTL 0x252b 12099#define mmDP4_DP_SEC_CNTL_BASE_IDX 2 12100#define mmDP4_DP_SEC_CNTL1 0x252c 12101#define mmDP4_DP_SEC_CNTL1_BASE_IDX 2 12102#define mmDP4_DP_SEC_FRAMING1 0x252d 12103#define mmDP4_DP_SEC_FRAMING1_BASE_IDX 2 12104#define mmDP4_DP_SEC_FRAMING2 0x252e 12105#define mmDP4_DP_SEC_FRAMING2_BASE_IDX 2 12106#define mmDP4_DP_SEC_FRAMING3 0x252f 12107#define mmDP4_DP_SEC_FRAMING3_BASE_IDX 2 12108#define mmDP4_DP_SEC_FRAMING4 0x2530 12109#define mmDP4_DP_SEC_FRAMING4_BASE_IDX 2 12110#define mmDP4_DP_SEC_AUD_N 0x2531 12111#define mmDP4_DP_SEC_AUD_N_BASE_IDX 2 12112#define mmDP4_DP_SEC_AUD_N_READBACK 0x2532 12113#define mmDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2 12114#define mmDP4_DP_SEC_AUD_M 0x2533 12115#define mmDP4_DP_SEC_AUD_M_BASE_IDX 2 12116#define mmDP4_DP_SEC_AUD_M_READBACK 0x2534 12117#define mmDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2 12118#define mmDP4_DP_SEC_TIMESTAMP 0x2535 12119#define mmDP4_DP_SEC_TIMESTAMP_BASE_IDX 2 12120#define mmDP4_DP_SEC_PACKET_CNTL 0x2536 12121#define mmDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2 12122#define mmDP4_DP_MSE_RATE_CNTL 0x2537 12123#define mmDP4_DP_MSE_RATE_CNTL_BASE_IDX 2 12124#define mmDP4_DP_MSE_RATE_UPDATE 0x2539 12125#define mmDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2 12126#define mmDP4_DP_MSE_SAT0 0x253a 12127#define mmDP4_DP_MSE_SAT0_BASE_IDX 2 12128#define mmDP4_DP_MSE_SAT1 0x253b 12129#define mmDP4_DP_MSE_SAT1_BASE_IDX 2 12130#define mmDP4_DP_MSE_SAT2 0x253c 12131#define mmDP4_DP_MSE_SAT2_BASE_IDX 2 12132#define mmDP4_DP_MSE_SAT_UPDATE 0x253d 12133#define mmDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2 12134#define mmDP4_DP_MSE_LINK_TIMING 0x253e 12135#define mmDP4_DP_MSE_LINK_TIMING_BASE_IDX 2 12136#define mmDP4_DP_MSE_MISC_CNTL 0x253f 12137#define mmDP4_DP_MSE_MISC_CNTL_BASE_IDX 2 12138#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x2544 12139#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 12140#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x2545 12141#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 12142#define mmDP4_DP_MSE_SAT0_STATUS 0x2547 12143#define mmDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2 12144#define mmDP4_DP_MSE_SAT1_STATUS 0x2548 12145#define mmDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2 12146#define mmDP4_DP_MSE_SAT2_STATUS 0x2549 12147#define mmDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2 12148#define mmDP4_DP_MSA_TIMING_PARAM1 0x254c 12149#define mmDP4_DP_MSA_TIMING_PARAM1_BASE_IDX 2 12150#define mmDP4_DP_MSA_TIMING_PARAM2 0x254d 12151#define mmDP4_DP_MSA_TIMING_PARAM2_BASE_IDX 2 12152#define mmDP4_DP_MSA_TIMING_PARAM3 0x254e 12153#define mmDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 2 12154#define mmDP4_DP_MSA_TIMING_PARAM4 0x254f 12155#define mmDP4_DP_MSA_TIMING_PARAM4_BASE_IDX 2 12156#define mmDP4_DP_MSO_CNTL 0x2550 12157#define mmDP4_DP_MSO_CNTL_BASE_IDX 2 12158#define mmDP4_DP_MSO_CNTL1 0x2551 12159#define mmDP4_DP_MSO_CNTL1_BASE_IDX 2 12160#define mmDP4_DP_DSC_CNTL 0x2552 12161#define mmDP4_DP_DSC_CNTL_BASE_IDX 2 12162#define mmDP4_DP_SEC_CNTL2 0x2553 12163#define mmDP4_DP_SEC_CNTL2_BASE_IDX 2 12164#define mmDP4_DP_SEC_CNTL3 0x2554 12165#define mmDP4_DP_SEC_CNTL3_BASE_IDX 2 12166#define mmDP4_DP_SEC_CNTL4 0x2555 12167#define mmDP4_DP_SEC_CNTL4_BASE_IDX 2 12168#define mmDP4_DP_SEC_CNTL5 0x2556 12169#define mmDP4_DP_SEC_CNTL5_BASE_IDX 2 12170#define mmDP4_DP_SEC_CNTL6 0x2557 12171#define mmDP4_DP_SEC_CNTL6_BASE_IDX 2 12172#define mmDP4_DP_SEC_CNTL7 0x2558 12173#define mmDP4_DP_SEC_CNTL7_BASE_IDX 2 12174#define mmDP4_DP_DB_CNTL 0x2559 12175#define mmDP4_DP_DB_CNTL_BASE_IDX 2 12176#define mmDP4_DP_MSA_VBID_MISC 0x255a 12177#define mmDP4_DP_MSA_VBID_MISC_BASE_IDX 2 12178#define mmDP4_DP_SEC_METADATA_TRANSMISSION 0x255b 12179#define mmDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 12180#define mmDP4_DP_DSC_BYTES_PER_PIXEL 0x255c 12181#define mmDP4_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 12182#define mmDP4_DP_ALPM_CNTL 0x255d 12183#define mmDP4_DP_ALPM_CNTL_BASE_IDX 2 12184#define mmDP4_DP_GSP8_CNTL 0x255e 12185#define mmDP4_DP_GSP8_CNTL_BASE_IDX 2 12186#define mmDP4_DP_GSP9_CNTL 0x255f 12187#define mmDP4_DP_GSP9_CNTL_BASE_IDX 2 12188#define mmDP4_DP_GSP10_CNTL 0x2560 12189#define mmDP4_DP_GSP10_CNTL_BASE_IDX 2 12190#define mmDP4_DP_GSP11_CNTL 0x2561 12191#define mmDP4_DP_GSP11_CNTL_BASE_IDX 2 12192#define mmDP4_DP_GSP_EN_DB_STATUS 0x2562 12193#define mmDP4_DP_GSP_EN_DB_STATUS_BASE_IDX 2 12194 12195 12196// addressBlock: dce_dc_dio_dig5_vpg_vpg_dispdec 12197// base address: 0x168a0 12198#define mmVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2568 12199#define mmVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 12200#define mmVPG5_VPG_GENERIC_PACKET_DATA 0x2569 12201#define mmVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 12202#define mmVPG5_VPG_GSP_FRAME_UPDATE_CTRL 0x256a 12203#define mmVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 12204#define mmVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x256b 12205#define mmVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 12206#define mmVPG5_VPG_GENERIC_STATUS 0x256c 12207#define mmVPG5_VPG_GENERIC_STATUS_BASE_IDX 2 12208#define mmVPG5_VPG_MEM_PWR 0x256d 12209#define mmVPG5_VPG_MEM_PWR_BASE_IDX 2 12210#define mmVPG5_VPG_ISRC1_2_ACCESS_CTRL 0x256e 12211#define mmVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 12212#define mmVPG5_VPG_ISRC1_2_DATA 0x256f 12213#define mmVPG5_VPG_ISRC1_2_DATA_BASE_IDX 2 12214#define mmVPG5_VPG_MPEG_INFO0 0x2570 12215#define mmVPG5_VPG_MPEG_INFO0_BASE_IDX 2 12216#define mmVPG5_VPG_MPEG_INFO1 0x2571 12217#define mmVPG5_VPG_MPEG_INFO1_BASE_IDX 2 12218 12219 12220// addressBlock: dce_dc_dio_dig5_afmt_afmt_dispdec 12221// base address: 0x168cc 12222#define mmAFMT5_AFMT_VBI_PACKET_CONTROL 0x2574 12223#define mmAFMT5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 12224#define mmAFMT5_AFMT_AUDIO_PACKET_CONTROL2 0x2575 12225#define mmAFMT5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 12226#define mmAFMT5_AFMT_AUDIO_INFO0 0x2576 12227#define mmAFMT5_AFMT_AUDIO_INFO0_BASE_IDX 2 12228#define mmAFMT5_AFMT_AUDIO_INFO1 0x2577 12229#define mmAFMT5_AFMT_AUDIO_INFO1_BASE_IDX 2 12230#define mmAFMT5_AFMT_60958_0 0x2578 12231#define mmAFMT5_AFMT_60958_0_BASE_IDX 2 12232#define mmAFMT5_AFMT_60958_1 0x2579 12233#define mmAFMT5_AFMT_60958_1_BASE_IDX 2 12234#define mmAFMT5_AFMT_AUDIO_CRC_CONTROL 0x257a 12235#define mmAFMT5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 12236#define mmAFMT5_AFMT_RAMP_CONTROL0 0x257b 12237#define mmAFMT5_AFMT_RAMP_CONTROL0_BASE_IDX 2 12238#define mmAFMT5_AFMT_RAMP_CONTROL1 0x257c 12239#define mmAFMT5_AFMT_RAMP_CONTROL1_BASE_IDX 2 12240#define mmAFMT5_AFMT_RAMP_CONTROL2 0x257d 12241#define mmAFMT5_AFMT_RAMP_CONTROL2_BASE_IDX 2 12242#define mmAFMT5_AFMT_RAMP_CONTROL3 0x257e 12243#define mmAFMT5_AFMT_RAMP_CONTROL3_BASE_IDX 2 12244#define mmAFMT5_AFMT_60958_2 0x257f 12245#define mmAFMT5_AFMT_60958_2_BASE_IDX 2 12246#define mmAFMT5_AFMT_AUDIO_CRC_RESULT 0x2580 12247#define mmAFMT5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 12248#define mmAFMT5_AFMT_STATUS 0x2581 12249#define mmAFMT5_AFMT_STATUS_BASE_IDX 2 12250#define mmAFMT5_AFMT_AUDIO_PACKET_CONTROL 0x2582 12251#define mmAFMT5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 12252#define mmAFMT5_AFMT_INFOFRAME_CONTROL0 0x2583 12253#define mmAFMT5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 12254#define mmAFMT5_AFMT_INTERRUPT_STATUS 0x2584 12255#define mmAFMT5_AFMT_INTERRUPT_STATUS_BASE_IDX 2 12256#define mmAFMT5_AFMT_AUDIO_SRC_CONTROL 0x2585 12257#define mmAFMT5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 12258#define mmAFMT5_AFMT_MEM_PWR 0x2587 12259#define mmAFMT5_AFMT_MEM_PWR_BASE_IDX 2 12260 12261 12262// addressBlock: dce_dc_dio_dig5_dme_dme_dispdec 12263// base address: 0x16924 12264#define mmDME5_DME_CONTROL 0x2589 12265#define mmDME5_DME_CONTROL_BASE_IDX 2 12266#define mmDME5_DME_MEMORY_CONTROL 0x258a 12267#define mmDME5_DME_MEMORY_CONTROL_BASE_IDX 2 12268 12269 12270// addressBlock: dce_dc_dio_dig5_dispdec 12271// base address: 0x1400 12272#define mmDIG5_DIG_FE_CNTL 0x258b 12273#define mmDIG5_DIG_FE_CNTL_BASE_IDX 2 12274#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x258c 12275#define mmDIG5_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 12276#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x258d 12277#define mmDIG5_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 12278#define mmDIG5_DIG_CLOCK_PATTERN 0x258e 12279#define mmDIG5_DIG_CLOCK_PATTERN_BASE_IDX 2 12280#define mmDIG5_DIG_TEST_PATTERN 0x258f 12281#define mmDIG5_DIG_TEST_PATTERN_BASE_IDX 2 12282#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x2590 12283#define mmDIG5_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 12284#define mmDIG5_DIG_FIFO_STATUS 0x2591 12285#define mmDIG5_DIG_FIFO_STATUS_BASE_IDX 2 12286#define mmDIG5_HDMI_METADATA_PACKET_CONTROL 0x2592 12287#define mmDIG5_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 12288#define mmDIG5_HDMI_CONTROL 0x2593 12289#define mmDIG5_HDMI_CONTROL_BASE_IDX 2 12290#define mmDIG5_HDMI_STATUS 0x2594 12291#define mmDIG5_HDMI_STATUS_BASE_IDX 2 12292#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x2595 12293#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 12294#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x2596 12295#define mmDIG5_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 12296#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x2597 12297#define mmDIG5_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 12298#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x2598 12299#define mmDIG5_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 12300#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x2599 12301#define mmDIG5_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 12302#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x259a 12303#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 12304#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL6 0x259b 12305#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 12306#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL5 0x259c 12307#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 12308#define mmDIG5_HDMI_GC 0x259d 12309#define mmDIG5_HDMI_GC_BASE_IDX 2 12310#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x259e 12311#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 12312#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2 0x259f 12313#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 12314#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3 0x25a0 12315#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 12316#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL4 0x25a1 12317#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 12318#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL7 0x25a2 12319#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 12320#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL8 0x25a3 12321#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 12322#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL9 0x25a4 12323#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 12324#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL10 0x25a5 12325#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 12326#define mmDIG5_HDMI_DB_CONTROL 0x25a6 12327#define mmDIG5_HDMI_DB_CONTROL_BASE_IDX 2 12328#define mmDIG5_HDMI_ACR_32_0 0x25a7 12329#define mmDIG5_HDMI_ACR_32_0_BASE_IDX 2 12330#define mmDIG5_HDMI_ACR_32_1 0x25a8 12331#define mmDIG5_HDMI_ACR_32_1_BASE_IDX 2 12332#define mmDIG5_HDMI_ACR_44_0 0x25a9 12333#define mmDIG5_HDMI_ACR_44_0_BASE_IDX 2 12334#define mmDIG5_HDMI_ACR_44_1 0x25aa 12335#define mmDIG5_HDMI_ACR_44_1_BASE_IDX 2 12336#define mmDIG5_HDMI_ACR_48_0 0x25ab 12337#define mmDIG5_HDMI_ACR_48_0_BASE_IDX 2 12338#define mmDIG5_HDMI_ACR_48_1 0x25ac 12339#define mmDIG5_HDMI_ACR_48_1_BASE_IDX 2 12340#define mmDIG5_HDMI_ACR_STATUS_0 0x25ad 12341#define mmDIG5_HDMI_ACR_STATUS_0_BASE_IDX 2 12342#define mmDIG5_HDMI_ACR_STATUS_1 0x25ae 12343#define mmDIG5_HDMI_ACR_STATUS_1_BASE_IDX 2 12344#define mmDIG5_AFMT_CNTL 0x25af 12345#define mmDIG5_AFMT_CNTL_BASE_IDX 2 12346#define mmDIG5_DIG_BE_CNTL 0x25b0 12347#define mmDIG5_DIG_BE_CNTL_BASE_IDX 2 12348#define mmDIG5_DIG_BE_EN_CNTL 0x25b1 12349#define mmDIG5_DIG_BE_EN_CNTL_BASE_IDX 2 12350 12351#define mmDIG5_TMDS_CNTL 0x25d7 12352#define mmDIG5_TMDS_CNTL_BASE_IDX 2 12353#define mmDIG5_TMDS_CONTROL_CHAR 0x25d8 12354#define mmDIG5_TMDS_CONTROL_CHAR_BASE_IDX 2 12355#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x25d9 12356#define mmDIG5_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 12357#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x25da 12358#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 12359#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x25db 12360#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 12361#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x25dc 12362#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 12363#define mmDIG5_TMDS_CTL_BITS 0x25de 12364#define mmDIG5_TMDS_CTL_BITS_BASE_IDX 2 12365#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x25df 12366#define mmDIG5_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 12367#define mmDIG5_TMDS_SYNC_DCBALANCE_CHAR 0x25e0 12368#define mmDIG5_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 12369#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x25e1 12370#define mmDIG5_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 12371#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x25e2 12372#define mmDIG5_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 12373#define mmDIG5_DIG_VERSION 0x25e4 12374#define mmDIG5_DIG_VERSION_BASE_IDX 2 12375#define mmDIG5_DIG_LANE_ENABLE 0x25e5 12376#define mmDIG5_DIG_LANE_ENABLE_BASE_IDX 2 12377#define mmDIG5_FORCE_DIG_DISABLE 0x25e6 12378#define mmDIG5_FORCE_DIG_DISABLE_BASE_IDX 2 12379 12380// addressBlock: dce_dc_dio_dp5_dispdec 12381// base address: 0x1400 12382#define mmDP5_DP_LINK_CNTL 0x2608 12383#define mmDP5_DP_LINK_CNTL_BASE_IDX 2 12384#define mmDP5_DP_PIXEL_FORMAT 0x2609 12385#define mmDP5_DP_PIXEL_FORMAT_BASE_IDX 2 12386#define mmDP5_DP_MSA_COLORIMETRY 0x260a 12387#define mmDP5_DP_MSA_COLORIMETRY_BASE_IDX 2 12388#define mmDP5_DP_CONFIG 0x260b 12389#define mmDP5_DP_CONFIG_BASE_IDX 2 12390#define mmDP5_DP_VID_STREAM_CNTL 0x260c 12391#define mmDP5_DP_VID_STREAM_CNTL_BASE_IDX 2 12392#define mmDP5_DP_STEER_FIFO 0x260d 12393#define mmDP5_DP_STEER_FIFO_BASE_IDX 2 12394#define mmDP5_DP_MSA_MISC 0x260e 12395#define mmDP5_DP_MSA_MISC_BASE_IDX 2 12396#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 12397#define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 12398#define mmDP5_DP_VID_TIMING 0x2610 12399#define mmDP5_DP_VID_TIMING_BASE_IDX 2 12400#define mmDP5_DP_VID_N 0x2611 12401#define mmDP5_DP_VID_N_BASE_IDX 2 12402#define mmDP5_DP_VID_M 0x2612 12403#define mmDP5_DP_VID_M_BASE_IDX 2 12404#define mmDP5_DP_LINK_FRAMING_CNTL 0x2613 12405#define mmDP5_DP_LINK_FRAMING_CNTL_BASE_IDX 2 12406#define mmDP5_DP_HBR2_EYE_PATTERN 0x2614 12407#define mmDP5_DP_HBR2_EYE_PATTERN_BASE_IDX 2 12408#define mmDP5_DP_VID_MSA_VBID 0x2615 12409#define mmDP5_DP_VID_MSA_VBID_BASE_IDX 2 12410#define mmDP5_DP_VID_INTERRUPT_CNTL 0x2616 12411#define mmDP5_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 12412#define mmDP5_DP_DPHY_CNTL 0x2617 12413#define mmDP5_DP_DPHY_CNTL_BASE_IDX 2 12414#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x2618 12415#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 12416#define mmDP5_DP_DPHY_SYM0 0x2619 12417#define mmDP5_DP_DPHY_SYM0_BASE_IDX 2 12418#define mmDP5_DP_DPHY_SYM1 0x261a 12419#define mmDP5_DP_DPHY_SYM1_BASE_IDX 2 12420#define mmDP5_DP_DPHY_SYM2 0x261b 12421#define mmDP5_DP_DPHY_SYM2_BASE_IDX 2 12422#define mmDP5_DP_DPHY_8B10B_CNTL 0x261c 12423#define mmDP5_DP_DPHY_8B10B_CNTL_BASE_IDX 2 12424#define mmDP5_DP_DPHY_PRBS_CNTL 0x261d 12425#define mmDP5_DP_DPHY_PRBS_CNTL_BASE_IDX 2 12426#define mmDP5_DP_DPHY_SCRAM_CNTL 0x261e 12427#define mmDP5_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 12428#define mmDP5_DP_DPHY_CRC_EN 0x261f 12429#define mmDP5_DP_DPHY_CRC_EN_BASE_IDX 2 12430#define mmDP5_DP_DPHY_CRC_CNTL 0x2620 12431#define mmDP5_DP_DPHY_CRC_CNTL_BASE_IDX 2 12432#define mmDP5_DP_DPHY_CRC_RESULT 0x2621 12433#define mmDP5_DP_DPHY_CRC_RESULT_BASE_IDX 2 12434#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x2622 12435#define mmDP5_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 12436#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x2623 12437#define mmDP5_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 12438#define mmDP5_DP_DPHY_FAST_TRAINING 0x2624 12439#define mmDP5_DP_DPHY_FAST_TRAINING_BASE_IDX 2 12440#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x2625 12441#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 12442#define mmDP5_DP_SEC_CNTL 0x262b 12443#define mmDP5_DP_SEC_CNTL_BASE_IDX 2 12444#define mmDP5_DP_SEC_CNTL1 0x262c 12445#define mmDP5_DP_SEC_CNTL1_BASE_IDX 2 12446#define mmDP5_DP_SEC_FRAMING1 0x262d 12447#define mmDP5_DP_SEC_FRAMING1_BASE_IDX 2 12448#define mmDP5_DP_SEC_FRAMING2 0x262e 12449#define mmDP5_DP_SEC_FRAMING2_BASE_IDX 2 12450#define mmDP5_DP_SEC_FRAMING3 0x262f 12451#define mmDP5_DP_SEC_FRAMING3_BASE_IDX 2 12452#define mmDP5_DP_SEC_FRAMING4 0x2630 12453#define mmDP5_DP_SEC_FRAMING4_BASE_IDX 2 12454#define mmDP5_DP_SEC_AUD_N 0x2631 12455#define mmDP5_DP_SEC_AUD_N_BASE_IDX 2 12456#define mmDP5_DP_SEC_AUD_N_READBACK 0x2632 12457#define mmDP5_DP_SEC_AUD_N_READBACK_BASE_IDX 2 12458#define mmDP5_DP_SEC_AUD_M 0x2633 12459#define mmDP5_DP_SEC_AUD_M_BASE_IDX 2 12460#define mmDP5_DP_SEC_AUD_M_READBACK 0x2634 12461#define mmDP5_DP_SEC_AUD_M_READBACK_BASE_IDX 2 12462#define mmDP5_DP_SEC_TIMESTAMP 0x2635 12463#define mmDP5_DP_SEC_TIMESTAMP_BASE_IDX 2 12464#define mmDP5_DP_SEC_PACKET_CNTL 0x2636 12465#define mmDP5_DP_SEC_PACKET_CNTL_BASE_IDX 2 12466#define mmDP5_DP_MSE_RATE_CNTL 0x2637 12467#define mmDP5_DP_MSE_RATE_CNTL_BASE_IDX 2 12468#define mmDP5_DP_MSE_RATE_UPDATE 0x2639 12469#define mmDP5_DP_MSE_RATE_UPDATE_BASE_IDX 2 12470#define mmDP5_DP_MSE_SAT0 0x263a 12471#define mmDP5_DP_MSE_SAT0_BASE_IDX 2 12472#define mmDP5_DP_MSE_SAT1 0x263b 12473#define mmDP5_DP_MSE_SAT1_BASE_IDX 2 12474#define mmDP5_DP_MSE_SAT2 0x263c 12475#define mmDP5_DP_MSE_SAT2_BASE_IDX 2 12476#define mmDP5_DP_MSE_SAT_UPDATE 0x263d 12477#define mmDP5_DP_MSE_SAT_UPDATE_BASE_IDX 2 12478#define mmDP5_DP_MSE_LINK_TIMING 0x263e 12479#define mmDP5_DP_MSE_LINK_TIMING_BASE_IDX 2 12480#define mmDP5_DP_MSE_MISC_CNTL 0x263f 12481#define mmDP5_DP_MSE_MISC_CNTL_BASE_IDX 2 12482#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x2644 12483#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 12484#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 0x2645 12485#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 12486#define mmDP5_DP_MSE_SAT0_STATUS 0x2647 12487#define mmDP5_DP_MSE_SAT0_STATUS_BASE_IDX 2 12488#define mmDP5_DP_MSE_SAT1_STATUS 0x2648 12489#define mmDP5_DP_MSE_SAT1_STATUS_BASE_IDX 2 12490#define mmDP5_DP_MSE_SAT2_STATUS 0x2649 12491#define mmDP5_DP_MSE_SAT2_STATUS_BASE_IDX 2 12492#define mmDP5_DP_MSA_TIMING_PARAM1 0x264c 12493#define mmDP5_DP_MSA_TIMING_PARAM1_BASE_IDX 2 12494#define mmDP5_DP_MSA_TIMING_PARAM2 0x264d 12495#define mmDP5_DP_MSA_TIMING_PARAM2_BASE_IDX 2 12496#define mmDP5_DP_MSA_TIMING_PARAM3 0x264e 12497#define mmDP5_DP_MSA_TIMING_PARAM3_BASE_IDX 2 12498#define mmDP5_DP_MSA_TIMING_PARAM4 0x264f 12499#define mmDP5_DP_MSA_TIMING_PARAM4_BASE_IDX 2 12500#define mmDP5_DP_MSO_CNTL 0x2650 12501#define mmDP5_DP_MSO_CNTL_BASE_IDX 2 12502#define mmDP5_DP_MSO_CNTL1 0x2651 12503#define mmDP5_DP_MSO_CNTL1_BASE_IDX 2 12504#define mmDP5_DP_DSC_CNTL 0x2652 12505#define mmDP5_DP_DSC_CNTL_BASE_IDX 2 12506#define mmDP5_DP_SEC_CNTL2 0x2653 12507#define mmDP5_DP_SEC_CNTL2_BASE_IDX 2 12508#define mmDP5_DP_SEC_CNTL3 0x2654 12509#define mmDP5_DP_SEC_CNTL3_BASE_IDX 2 12510#define mmDP5_DP_SEC_CNTL4 0x2655 12511#define mmDP5_DP_SEC_CNTL4_BASE_IDX 2 12512#define mmDP5_DP_SEC_CNTL5 0x2656 12513#define mmDP5_DP_SEC_CNTL5_BASE_IDX 2 12514#define mmDP5_DP_SEC_CNTL6 0x2657 12515#define mmDP5_DP_SEC_CNTL6_BASE_IDX 2 12516#define mmDP5_DP_SEC_CNTL7 0x2658 12517#define mmDP5_DP_SEC_CNTL7_BASE_IDX 2 12518#define mmDP5_DP_DB_CNTL 0x2659 12519#define mmDP5_DP_DB_CNTL_BASE_IDX 2 12520#define mmDP5_DP_MSA_VBID_MISC 0x265a 12521#define mmDP5_DP_MSA_VBID_MISC_BASE_IDX 2 12522#define mmDP5_DP_SEC_METADATA_TRANSMISSION 0x265b 12523#define mmDP5_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 12524#define mmDP5_DP_DSC_BYTES_PER_PIXEL 0x265c 12525#define mmDP5_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 12526#define mmDP5_DP_ALPM_CNTL 0x265d 12527#define mmDP5_DP_ALPM_CNTL_BASE_IDX 2 12528#define mmDP5_DP_GSP8_CNTL 0x265e 12529#define mmDP5_DP_GSP8_CNTL_BASE_IDX 2 12530#define mmDP5_DP_GSP9_CNTL 0x265f 12531#define mmDP5_DP_GSP9_CNTL_BASE_IDX 2 12532#define mmDP5_DP_GSP10_CNTL 0x2660 12533#define mmDP5_DP_GSP10_CNTL_BASE_IDX 2 12534#define mmDP5_DP_GSP11_CNTL 0x2661 12535#define mmDP5_DP_GSP11_CNTL_BASE_IDX 2 12536#define mmDP5_DP_GSP_EN_DB_STATUS 0x2662 12537#define mmDP5_DP_GSP_EN_DB_STATUS_BASE_IDX 2 12538 12539 12540// addressBlock: dce_dc_dcio_dcio_dispdec 12541// base address: 0x0 12542#define mmDC_GENERICA 0x2868 12543#define mmDC_GENERICA_BASE_IDX 2 12544#define mmDC_GENERICB 0x2869 12545#define mmDC_GENERICB_BASE_IDX 2 12546#define mmDCIO_CLOCK_CNTL 0x286a 12547#define mmDCIO_CLOCK_CNTL_BASE_IDX 2 12548#define mmDC_REF_CLK_CNTL 0x286b 12549#define mmDC_REF_CLK_CNTL_BASE_IDX 2 12550#define mmUNIPHYA_LINK_CNTL 0x286d 12551#define mmUNIPHYA_LINK_CNTL_BASE_IDX 2 12552#define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x286e 12553#define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2 12554#define mmUNIPHYB_LINK_CNTL 0x286f 12555#define mmUNIPHYB_LINK_CNTL_BASE_IDX 2 12556#define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x2870 12557#define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2 12558#define mmUNIPHYC_LINK_CNTL 0x2871 12559#define mmUNIPHYC_LINK_CNTL_BASE_IDX 2 12560#define mmUNIPHYC_CHANNEL_XBAR_CNTL 0x2872 12561#define mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2 12562#define mmUNIPHYD_LINK_CNTL 0x2873 12563#define mmUNIPHYD_LINK_CNTL_BASE_IDX 2 12564#define mmUNIPHYD_CHANNEL_XBAR_CNTL 0x2874 12565#define mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2 12566#define mmUNIPHYE_LINK_CNTL 0x2875 12567#define mmUNIPHYE_LINK_CNTL_BASE_IDX 2 12568#define mmUNIPHYE_CHANNEL_XBAR_CNTL 0x2876 12569#define mmUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2 12570#define mmUNIPHYF_LINK_CNTL 0x2877 12571#define mmUNIPHYF_LINK_CNTL_BASE_IDX 2 12572#define mmUNIPHYF_CHANNEL_XBAR_CNTL 0x2878 12573#define mmUNIPHYF_CHANNEL_XBAR_CNTL_BASE_IDX 2 12574#define mmDCIO_WRCMD_DELAY 0x287e 12575#define mmDCIO_WRCMD_DELAY_BASE_IDX 2 12576#define mmDC_PINSTRAPS 0x2880 12577#define mmDC_PINSTRAPS_BASE_IDX 2 12578#define mmLVTMA_PWRSEQ_CNTL 0x2883 12579#define mmLVTMA_PWRSEQ_CNTL_BASE_IDX 2 12580#define mmLVTMA_PWRSEQ_STATE 0x2884 12581#define mmLVTMA_PWRSEQ_STATE_BASE_IDX 2 12582#define mmLVTMA_PWRSEQ_REF_DIV 0x2885 12583#define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX 2 12584#define mmLVTMA_PWRSEQ_DELAY1 0x2886 12585#define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX 2 12586#define mmLVTMA_PWRSEQ_DELAY2 0x2887 12587#define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX 2 12588#define mmBL_PWM_CNTL 0x2888 12589#define mmBL_PWM_CNTL_BASE_IDX 2 12590#define mmBL_PWM_CNTL2 0x2889 12591#define mmBL_PWM_CNTL2_BASE_IDX 2 12592#define mmBL_PWM_PERIOD_CNTL 0x288a 12593#define mmBL_PWM_PERIOD_CNTL_BASE_IDX 2 12594#define mmBL_PWM_GRP1_REG_LOCK 0x288b 12595#define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX 2 12596#define mmDCIO_GSL_GENLK_PAD_CNTL 0x288c 12597#define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2 12598#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d 12599#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2 12600#define mmDCIO_SOFT_RESET 0x289e 12601#define mmDCIO_SOFT_RESET_BASE_IDX 2 12602 12603 12604// addressBlock: dce_dc_dcio_dcio_chip_dispdec 12605// base address: 0x0 12606#define mmDC_GPIO_GENERIC_MASK 0x28c8 12607#define mmDC_GPIO_GENERIC_MASK_BASE_IDX 2 12608#define mmDC_GPIO_GENERIC_A 0x28c9 12609#define mmDC_GPIO_GENERIC_A_BASE_IDX 2 12610#define mmDC_GPIO_GENERIC_EN 0x28ca 12611#define mmDC_GPIO_GENERIC_EN_BASE_IDX 2 12612#define mmDC_GPIO_GENERIC_Y 0x28cb 12613#define mmDC_GPIO_GENERIC_Y_BASE_IDX 2 12614#define mmDC_GPIO_DDC1_MASK 0x28d0 12615#define mmDC_GPIO_DDC1_MASK_BASE_IDX 2 12616#define mmDC_GPIO_DDC1_A 0x28d1 12617#define mmDC_GPIO_DDC1_A_BASE_IDX 2 12618#define mmDC_GPIO_DDC1_EN 0x28d2 12619#define mmDC_GPIO_DDC1_EN_BASE_IDX 2 12620#define mmDC_GPIO_DDC1_Y 0x28d3 12621#define mmDC_GPIO_DDC1_Y_BASE_IDX 2 12622#define mmDC_GPIO_DDC2_MASK 0x28d4 12623#define mmDC_GPIO_DDC2_MASK_BASE_IDX 2 12624#define mmDC_GPIO_DDC2_A 0x28d5 12625#define mmDC_GPIO_DDC2_A_BASE_IDX 2 12626#define mmDC_GPIO_DDC2_EN 0x28d6 12627#define mmDC_GPIO_DDC2_EN_BASE_IDX 2 12628#define mmDC_GPIO_DDC2_Y 0x28d7 12629#define mmDC_GPIO_DDC2_Y_BASE_IDX 2 12630#define mmDC_GPIO_DDC3_MASK 0x28d8 12631#define mmDC_GPIO_DDC3_MASK_BASE_IDX 2 12632#define mmDC_GPIO_DDC3_A 0x28d9 12633#define mmDC_GPIO_DDC3_A_BASE_IDX 2 12634#define mmDC_GPIO_DDC3_EN 0x28da 12635#define mmDC_GPIO_DDC3_EN_BASE_IDX 2 12636#define mmDC_GPIO_DDC3_Y 0x28db 12637#define mmDC_GPIO_DDC3_Y_BASE_IDX 2 12638#define mmDC_GPIO_DDC4_MASK 0x28dc 12639#define mmDC_GPIO_DDC4_MASK_BASE_IDX 2 12640#define mmDC_GPIO_DDC4_A 0x28dd 12641#define mmDC_GPIO_DDC4_A_BASE_IDX 2 12642#define mmDC_GPIO_DDC4_EN 0x28de 12643#define mmDC_GPIO_DDC4_EN_BASE_IDX 2 12644#define mmDC_GPIO_DDC4_Y 0x28df 12645#define mmDC_GPIO_DDC4_Y_BASE_IDX 2 12646#define mmDC_GPIO_DDC5_MASK 0x28e0 12647#define mmDC_GPIO_DDC5_MASK_BASE_IDX 2 12648#define mmDC_GPIO_DDC5_A 0x28e1 12649#define mmDC_GPIO_DDC5_A_BASE_IDX 2 12650#define mmDC_GPIO_DDC5_EN 0x28e2 12651#define mmDC_GPIO_DDC5_EN_BASE_IDX 2 12652#define mmDC_GPIO_DDC5_Y 0x28e3 12653#define mmDC_GPIO_DDC5_Y_BASE_IDX 2 12654#define mmDC_GPIO_DDC6_MASK 0x28e4 12655#define mmDC_GPIO_DDC6_MASK_BASE_IDX 2 12656#define mmDC_GPIO_DDC6_A 0x28e5 12657#define mmDC_GPIO_DDC6_A_BASE_IDX 2 12658#define mmDC_GPIO_DDC6_EN 0x28e6 12659#define mmDC_GPIO_DDC6_EN_BASE_IDX 2 12660#define mmDC_GPIO_DDC6_Y 0x28e7 12661#define mmDC_GPIO_DDC6_Y_BASE_IDX 2 12662#define mmDC_GPIO_DDCVGA_MASK 0x28e8 12663#define mmDC_GPIO_DDCVGA_MASK_BASE_IDX 2 12664#define mmDC_GPIO_DDCVGA_A 0x28e9 12665#define mmDC_GPIO_DDCVGA_A_BASE_IDX 2 12666#define mmDC_GPIO_DDCVGA_EN 0x28ea 12667#define mmDC_GPIO_DDCVGA_EN_BASE_IDX 2 12668#define mmDC_GPIO_DDCVGA_Y 0x28eb 12669#define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2 12670#define mmDC_GPIO_GENLK_MASK 0x28f0 12671#define mmDC_GPIO_GENLK_MASK_BASE_IDX 2 12672#define mmDC_GPIO_GENLK_A 0x28f1 12673#define mmDC_GPIO_GENLK_A_BASE_IDX 2 12674#define mmDC_GPIO_GENLK_EN 0x28f2 12675#define mmDC_GPIO_GENLK_EN_BASE_IDX 2 12676#define mmDC_GPIO_GENLK_Y 0x28f3 12677#define mmDC_GPIO_GENLK_Y_BASE_IDX 2 12678#define mmDC_GPIO_HPD_MASK 0x28f4 12679#define mmDC_GPIO_HPD_MASK_BASE_IDX 2 12680#define mmDC_GPIO_HPD_A 0x28f5 12681#define mmDC_GPIO_HPD_A_BASE_IDX 2 12682#define mmDC_GPIO_HPD_EN 0x28f6 12683#define mmDC_GPIO_HPD_EN_BASE_IDX 2 12684#define mmDC_GPIO_HPD_Y 0x28f7 12685#define mmDC_GPIO_HPD_Y_BASE_IDX 2 12686#define mmDC_GPIO_PWRSEQ_MASK 0x28f8 12687#define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX 2 12688#define mmDC_GPIO_PWRSEQ_A 0x28f9 12689#define mmDC_GPIO_PWRSEQ_A_BASE_IDX 2 12690#define mmDC_GPIO_PWRSEQ_EN 0x28fa 12691#define mmDC_GPIO_PWRSEQ_EN_BASE_IDX 2 12692#define mmDC_GPIO_PWRSEQ_Y 0x28fb 12693#define mmDC_GPIO_PWRSEQ_Y_BASE_IDX 2 12694#define mmDC_GPIO_PAD_STRENGTH_1 0x28fc 12695#define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2 12696#define mmDC_GPIO_PAD_STRENGTH_2 0x28fd 12697#define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2 12698#define mmPHY_AUX_CNTL 0x28ff 12699#define mmPHY_AUX_CNTL_BASE_IDX 2 12700#define mmDC_GPIO_TX12_EN 0x2915 12701#define mmDC_GPIO_TX12_EN_BASE_IDX 2 12702#define mmDC_GPIO_AUX_CTRL_0 0x2916 12703#define mmDC_GPIO_AUX_CTRL_0_BASE_IDX 2 12704#define mmDC_GPIO_AUX_CTRL_1 0x2917 12705#define mmDC_GPIO_AUX_CTRL_1_BASE_IDX 2 12706#define mmDC_GPIO_AUX_CTRL_2 0x2918 12707#define mmDC_GPIO_AUX_CTRL_2_BASE_IDX 2 12708#define mmDC_GPIO_RXEN 0x2919 12709#define mmDC_GPIO_RXEN_BASE_IDX 2 12710#define mmDC_GPIO_PULLUPEN 0x291a 12711#define mmDC_GPIO_PULLUPEN_BASE_IDX 2 12712#define mmDC_GPIO_AUX_CTRL_3 0x291b 12713#define mmDC_GPIO_AUX_CTRL_3_BASE_IDX 2 12714#define mmDC_GPIO_AUX_CTRL_4 0x291c 12715#define mmDC_GPIO_AUX_CTRL_4_BASE_IDX 2 12716#define mmDC_GPIO_AUX_CTRL_5 0x291d 12717#define mmDC_GPIO_AUX_CTRL_5_BASE_IDX 2 12718#define mmAUXI2C_PAD_ALL_PWR_OK 0x291e 12719#define mmAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2 12720 12721 12722 12723// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec 12724// base address: 0x0 12725#define mmDSC_TOP0_DSC_TOP_CONTROL 0x3000 12726#define mmDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX 2 12727#define mmDSC_TOP0_DSC_DEBUG_CONTROL 0x3001 12728#define mmDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX 2 12729 12730 12731// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec 12732// base address: 0x0 12733#define mmDSCCIF0_DSCCIF_CONFIG0 0x3005 12734#define mmDSCCIF0_DSCCIF_CONFIG0_BASE_IDX 2 12735#define mmDSCCIF0_DSCCIF_CONFIG1 0x3006 12736#define mmDSCCIF0_DSCCIF_CONFIG1_BASE_IDX 2 12737 12738 12739// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec 12740// base address: 0x0 12741#define mmDSCC0_DSCC_CONFIG0 0x300a 12742#define mmDSCC0_DSCC_CONFIG0_BASE_IDX 2 12743#define mmDSCC0_DSCC_CONFIG1 0x300b 12744#define mmDSCC0_DSCC_CONFIG1_BASE_IDX 2 12745#define mmDSCC0_DSCC_STATUS 0x300c 12746#define mmDSCC0_DSCC_STATUS_BASE_IDX 2 12747#define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS 0x300d 12748#define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 12749#define mmDSCC0_DSCC_PPS_CONFIG0 0x300e 12750#define mmDSCC0_DSCC_PPS_CONFIG0_BASE_IDX 2 12751#define mmDSCC0_DSCC_PPS_CONFIG1 0x300f 12752#define mmDSCC0_DSCC_PPS_CONFIG1_BASE_IDX 2 12753#define mmDSCC0_DSCC_PPS_CONFIG2 0x3010 12754#define mmDSCC0_DSCC_PPS_CONFIG2_BASE_IDX 2 12755#define mmDSCC0_DSCC_PPS_CONFIG3 0x3011 12756#define mmDSCC0_DSCC_PPS_CONFIG3_BASE_IDX 2 12757#define mmDSCC0_DSCC_PPS_CONFIG4 0x3012 12758#define mmDSCC0_DSCC_PPS_CONFIG4_BASE_IDX 2 12759#define mmDSCC0_DSCC_PPS_CONFIG5 0x3013 12760#define mmDSCC0_DSCC_PPS_CONFIG5_BASE_IDX 2 12761#define mmDSCC0_DSCC_PPS_CONFIG6 0x3014 12762#define mmDSCC0_DSCC_PPS_CONFIG6_BASE_IDX 2 12763#define mmDSCC0_DSCC_PPS_CONFIG7 0x3015 12764#define mmDSCC0_DSCC_PPS_CONFIG7_BASE_IDX 2 12765#define mmDSCC0_DSCC_PPS_CONFIG8 0x3016 12766#define mmDSCC0_DSCC_PPS_CONFIG8_BASE_IDX 2 12767#define mmDSCC0_DSCC_PPS_CONFIG9 0x3017 12768#define mmDSCC0_DSCC_PPS_CONFIG9_BASE_IDX 2 12769#define mmDSCC0_DSCC_PPS_CONFIG10 0x3018 12770#define mmDSCC0_DSCC_PPS_CONFIG10_BASE_IDX 2 12771#define mmDSCC0_DSCC_PPS_CONFIG11 0x3019 12772#define mmDSCC0_DSCC_PPS_CONFIG11_BASE_IDX 2 12773#define mmDSCC0_DSCC_PPS_CONFIG12 0x301a 12774#define mmDSCC0_DSCC_PPS_CONFIG12_BASE_IDX 2 12775#define mmDSCC0_DSCC_PPS_CONFIG13 0x301b 12776#define mmDSCC0_DSCC_PPS_CONFIG13_BASE_IDX 2 12777#define mmDSCC0_DSCC_PPS_CONFIG14 0x301c 12778#define mmDSCC0_DSCC_PPS_CONFIG14_BASE_IDX 2 12779#define mmDSCC0_DSCC_PPS_CONFIG15 0x301d 12780#define mmDSCC0_DSCC_PPS_CONFIG15_BASE_IDX 2 12781#define mmDSCC0_DSCC_PPS_CONFIG16 0x301e 12782#define mmDSCC0_DSCC_PPS_CONFIG16_BASE_IDX 2 12783#define mmDSCC0_DSCC_PPS_CONFIG17 0x301f 12784#define mmDSCC0_DSCC_PPS_CONFIG17_BASE_IDX 2 12785#define mmDSCC0_DSCC_PPS_CONFIG18 0x3020 12786#define mmDSCC0_DSCC_PPS_CONFIG18_BASE_IDX 2 12787#define mmDSCC0_DSCC_PPS_CONFIG19 0x3021 12788#define mmDSCC0_DSCC_PPS_CONFIG19_BASE_IDX 2 12789#define mmDSCC0_DSCC_PPS_CONFIG20 0x3022 12790#define mmDSCC0_DSCC_PPS_CONFIG20_BASE_IDX 2 12791#define mmDSCC0_DSCC_PPS_CONFIG21 0x3023 12792#define mmDSCC0_DSCC_PPS_CONFIG21_BASE_IDX 2 12793#define mmDSCC0_DSCC_PPS_CONFIG22 0x3024 12794#define mmDSCC0_DSCC_PPS_CONFIG22_BASE_IDX 2 12795#define mmDSCC0_DSCC_MEM_POWER_CONTROL 0x3025 12796#define mmDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 12797#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3026 12798#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 12799#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3027 12800#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 12801#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3028 12802#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 12803#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3029 12804#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 12805#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER 0x302a 12806#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 12807#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER 0x302b 12808#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 12809#define mmDSCC0_DSCC_MAX_ABS_ERROR0 0x302c 12810#define mmDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 12811#define mmDSCC0_DSCC_MAX_ABS_ERROR1 0x302d 12812#define mmDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 12813#define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x302e 12814#define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12815#define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x302f 12816#define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12817#define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3030 12818#define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12819#define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3031 12820#define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12821#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3032 12822#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12823#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3033 12824#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12825#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3034 12826#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12827#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035 12828#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12829 12830 12831// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 12832// base address: 0xc140 12833#define mmDC_PERFMON21_PERFCOUNTER_CNTL 0x3050 12834#define mmDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX 2 12835#define mmDC_PERFMON21_PERFCOUNTER_CNTL2 0x3051 12836#define mmDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX 2 12837#define mmDC_PERFMON21_PERFCOUNTER_STATE 0x3052 12838#define mmDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX 2 12839#define mmDC_PERFMON21_PERFMON_CNTL 0x3053 12840#define mmDC_PERFMON21_PERFMON_CNTL_BASE_IDX 2 12841#define mmDC_PERFMON21_PERFMON_CNTL2 0x3054 12842#define mmDC_PERFMON21_PERFMON_CNTL2_BASE_IDX 2 12843#define mmDC_PERFMON21_PERFMON_CVALUE_INT_MISC 0x3055 12844#define mmDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 12845#define mmDC_PERFMON21_PERFMON_CVALUE_LOW 0x3056 12846#define mmDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX 2 12847#define mmDC_PERFMON21_PERFMON_HI 0x3057 12848#define mmDC_PERFMON21_PERFMON_HI_BASE_IDX 2 12849#define mmDC_PERFMON21_PERFMON_LOW 0x3058 12850#define mmDC_PERFMON21_PERFMON_LOW_BASE_IDX 2 12851 12852 12853// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec 12854// base address: 0x170 12855#define mmDSC_TOP1_DSC_TOP_CONTROL 0x305c 12856#define mmDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX 2 12857#define mmDSC_TOP1_DSC_DEBUG_CONTROL 0x305d 12858#define mmDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX 2 12859 12860 12861// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec 12862// base address: 0x170 12863#define mmDSCCIF1_DSCCIF_CONFIG0 0x3061 12864#define mmDSCCIF1_DSCCIF_CONFIG0_BASE_IDX 2 12865#define mmDSCCIF1_DSCCIF_CONFIG1 0x3062 12866#define mmDSCCIF1_DSCCIF_CONFIG1_BASE_IDX 2 12867 12868 12869// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec 12870// base address: 0x170 12871#define mmDSCC1_DSCC_CONFIG0 0x3066 12872#define mmDSCC1_DSCC_CONFIG0_BASE_IDX 2 12873#define mmDSCC1_DSCC_CONFIG1 0x3067 12874#define mmDSCC1_DSCC_CONFIG1_BASE_IDX 2 12875#define mmDSCC1_DSCC_STATUS 0x3068 12876#define mmDSCC1_DSCC_STATUS_BASE_IDX 2 12877#define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS 0x3069 12878#define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 12879#define mmDSCC1_DSCC_PPS_CONFIG0 0x306a 12880#define mmDSCC1_DSCC_PPS_CONFIG0_BASE_IDX 2 12881#define mmDSCC1_DSCC_PPS_CONFIG1 0x306b 12882#define mmDSCC1_DSCC_PPS_CONFIG1_BASE_IDX 2 12883#define mmDSCC1_DSCC_PPS_CONFIG2 0x306c 12884#define mmDSCC1_DSCC_PPS_CONFIG2_BASE_IDX 2 12885#define mmDSCC1_DSCC_PPS_CONFIG3 0x306d 12886#define mmDSCC1_DSCC_PPS_CONFIG3_BASE_IDX 2 12887#define mmDSCC1_DSCC_PPS_CONFIG4 0x306e 12888#define mmDSCC1_DSCC_PPS_CONFIG4_BASE_IDX 2 12889#define mmDSCC1_DSCC_PPS_CONFIG5 0x306f 12890#define mmDSCC1_DSCC_PPS_CONFIG5_BASE_IDX 2 12891#define mmDSCC1_DSCC_PPS_CONFIG6 0x3070 12892#define mmDSCC1_DSCC_PPS_CONFIG6_BASE_IDX 2 12893#define mmDSCC1_DSCC_PPS_CONFIG7 0x3071 12894#define mmDSCC1_DSCC_PPS_CONFIG7_BASE_IDX 2 12895#define mmDSCC1_DSCC_PPS_CONFIG8 0x3072 12896#define mmDSCC1_DSCC_PPS_CONFIG8_BASE_IDX 2 12897#define mmDSCC1_DSCC_PPS_CONFIG9 0x3073 12898#define mmDSCC1_DSCC_PPS_CONFIG9_BASE_IDX 2 12899#define mmDSCC1_DSCC_PPS_CONFIG10 0x3074 12900#define mmDSCC1_DSCC_PPS_CONFIG10_BASE_IDX 2 12901#define mmDSCC1_DSCC_PPS_CONFIG11 0x3075 12902#define mmDSCC1_DSCC_PPS_CONFIG11_BASE_IDX 2 12903#define mmDSCC1_DSCC_PPS_CONFIG12 0x3076 12904#define mmDSCC1_DSCC_PPS_CONFIG12_BASE_IDX 2 12905#define mmDSCC1_DSCC_PPS_CONFIG13 0x3077 12906#define mmDSCC1_DSCC_PPS_CONFIG13_BASE_IDX 2 12907#define mmDSCC1_DSCC_PPS_CONFIG14 0x3078 12908#define mmDSCC1_DSCC_PPS_CONFIG14_BASE_IDX 2 12909#define mmDSCC1_DSCC_PPS_CONFIG15 0x3079 12910#define mmDSCC1_DSCC_PPS_CONFIG15_BASE_IDX 2 12911#define mmDSCC1_DSCC_PPS_CONFIG16 0x307a 12912#define mmDSCC1_DSCC_PPS_CONFIG16_BASE_IDX 2 12913#define mmDSCC1_DSCC_PPS_CONFIG17 0x307b 12914#define mmDSCC1_DSCC_PPS_CONFIG17_BASE_IDX 2 12915#define mmDSCC1_DSCC_PPS_CONFIG18 0x307c 12916#define mmDSCC1_DSCC_PPS_CONFIG18_BASE_IDX 2 12917#define mmDSCC1_DSCC_PPS_CONFIG19 0x307d 12918#define mmDSCC1_DSCC_PPS_CONFIG19_BASE_IDX 2 12919#define mmDSCC1_DSCC_PPS_CONFIG20 0x307e 12920#define mmDSCC1_DSCC_PPS_CONFIG20_BASE_IDX 2 12921#define mmDSCC1_DSCC_PPS_CONFIG21 0x307f 12922#define mmDSCC1_DSCC_PPS_CONFIG21_BASE_IDX 2 12923#define mmDSCC1_DSCC_PPS_CONFIG22 0x3080 12924#define mmDSCC1_DSCC_PPS_CONFIG22_BASE_IDX 2 12925#define mmDSCC1_DSCC_MEM_POWER_CONTROL 0x3081 12926#define mmDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 12927#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3082 12928#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 12929#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3083 12930#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 12931#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3084 12932#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 12933#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3085 12934#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 12935#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER 0x3086 12936#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 12937#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3087 12938#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 12939#define mmDSCC1_DSCC_MAX_ABS_ERROR0 0x3088 12940#define mmDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 12941#define mmDSCC1_DSCC_MAX_ABS_ERROR1 0x3089 12942#define mmDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 12943#define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x308a 12944#define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12945#define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x308b 12946#define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12947#define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x308c 12948#define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12949#define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x308d 12950#define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12951#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x308e 12952#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12953#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x308f 12954#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12955#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3090 12956#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12957#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091 12958#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12959 12960 12961// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 12962// base address: 0xc2b0 12963#define mmDC_PERFMON22_PERFCOUNTER_CNTL 0x30ac 12964#define mmDC_PERFMON22_PERFCOUNTER_CNTL_BASE_IDX 2 12965#define mmDC_PERFMON22_PERFCOUNTER_CNTL2 0x30ad 12966#define mmDC_PERFMON22_PERFCOUNTER_CNTL2_BASE_IDX 2 12967#define mmDC_PERFMON22_PERFCOUNTER_STATE 0x30ae 12968#define mmDC_PERFMON22_PERFCOUNTER_STATE_BASE_IDX 2 12969#define mmDC_PERFMON22_PERFMON_CNTL 0x30af 12970#define mmDC_PERFMON22_PERFMON_CNTL_BASE_IDX 2 12971#define mmDC_PERFMON22_PERFMON_CNTL2 0x30b0 12972#define mmDC_PERFMON22_PERFMON_CNTL2_BASE_IDX 2 12973#define mmDC_PERFMON22_PERFMON_CVALUE_INT_MISC 0x30b1 12974#define mmDC_PERFMON22_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 12975#define mmDC_PERFMON22_PERFMON_CVALUE_LOW 0x30b2 12976#define mmDC_PERFMON22_PERFMON_CVALUE_LOW_BASE_IDX 2 12977#define mmDC_PERFMON22_PERFMON_HI 0x30b3 12978#define mmDC_PERFMON22_PERFMON_HI_BASE_IDX 2 12979#define mmDC_PERFMON22_PERFMON_LOW 0x30b4 12980#define mmDC_PERFMON22_PERFMON_LOW_BASE_IDX 2 12981 12982 12983// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec 12984// base address: 0x2e0 12985#define mmDSC_TOP2_DSC_TOP_CONTROL 0x30b8 12986#define mmDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX 2 12987#define mmDSC_TOP2_DSC_DEBUG_CONTROL 0x30b9 12988#define mmDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX 2 12989 12990 12991// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec 12992// base address: 0x2e0 12993#define mmDSCCIF2_DSCCIF_CONFIG0 0x30bd 12994#define mmDSCCIF2_DSCCIF_CONFIG0_BASE_IDX 2 12995#define mmDSCCIF2_DSCCIF_CONFIG1 0x30be 12996#define mmDSCCIF2_DSCCIF_CONFIG1_BASE_IDX 2 12997 12998 12999// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec 13000// base address: 0x2e0
13001#define mmDSCC2_DSCC_CONFIG0 0x30c2 13002#define mmDSCC2_DSCC_CONFIG0_BASE_IDX 2 13003#define mmDSCC2_DSCC_CONFIG1 0x30c3 13004#define mmDSCC2_DSCC_CONFIG1_BASE_IDX 2 13005#define mmDSCC2_DSCC_STATUS 0x30c4 13006#define mmDSCC2_DSCC_STATUS_BASE_IDX 2 13007#define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS 0x30c5 13008#define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 13009#define mmDSCC2_DSCC_PPS_CONFIG0 0x30c6 13010#define mmDSCC2_DSCC_PPS_CONFIG0_BASE_IDX 2 13011#define mmDSCC2_DSCC_PPS_CONFIG1 0x30c7 13012#define mmDSCC2_DSCC_PPS_CONFIG1_BASE_IDX 2 13013#define mmDSCC2_DSCC_PPS_CONFIG2 0x30c8 13014#define mmDSCC2_DSCC_PPS_CONFIG2_BASE_IDX 2 13015#define mmDSCC2_DSCC_PPS_CONFIG3 0x30c9 13016#define mmDSCC2_DSCC_PPS_CONFIG3_BASE_IDX 2 13017#define mmDSCC2_DSCC_PPS_CONFIG4 0x30ca 13018#define mmDSCC2_DSCC_PPS_CONFIG4_BASE_IDX 2 13019#define mmDSCC2_DSCC_PPS_CONFIG5 0x30cb 13020#define mmDSCC2_DSCC_PPS_CONFIG5_BASE_IDX 2 13021#define mmDSCC2_DSCC_PPS_CONFIG6 0x30cc 13022#define mmDSCC2_DSCC_PPS_CONFIG6_BASE_IDX 2 13023#define mmDSCC2_DSCC_PPS_CONFIG7 0x30cd 13024#define mmDSCC2_DSCC_PPS_CONFIG7_BASE_IDX 2 13025#define mmDSCC2_DSCC_PPS_CONFIG8 0x30ce 13026#define mmDSCC2_DSCC_PPS_CONFIG8_BASE_IDX 2 13027#define mmDSCC2_DSCC_PPS_CONFIG9 0x30cf 13028#define mmDSCC2_DSCC_PPS_CONFIG9_BASE_IDX 2 13029#define mmDSCC2_DSCC_PPS_CONFIG10 0x30d0 13030#define mmDSCC2_DSCC_PPS_CONFIG10_BASE_IDX 2 13031#define mmDSCC2_DSCC_PPS_CONFIG11 0x30d1 13032#define mmDSCC2_DSCC_PPS_CONFIG11_BASE_IDX 2 13033#define mmDSCC2_DSCC_PPS_CONFIG12 0x30d2 13034#define mmDSCC2_DSCC_PPS_CONFIG12_BASE_IDX 2 13035#define mmDSCC2_DSCC_PPS_CONFIG13 0x30d3 13036#define mmDSCC2_DSCC_PPS_CONFIG13_BASE_IDX 2 13037#define mmDSCC2_DSCC_PPS_CONFIG14 0x30d4 13038#define mmDSCC2_DSCC_PPS_CONFIG14_BASE_IDX 2 13039#define mmDSCC2_DSCC_PPS_CONFIG15 0x30d5 13040#define mmDSCC2_DSCC_PPS_CONFIG15_BASE_IDX 2 13041#define mmDSCC2_DSCC_PPS_CONFIG16 0x30d6 13042#define mmDSCC2_DSCC_PPS_CONFIG16_BASE_IDX 2 13043#define mmDSCC2_DSCC_PPS_CONFIG17 0x30d7 13044#define mmDSCC2_DSCC_PPS_CONFIG17_BASE_IDX 2 13045#define mmDSCC2_DSCC_PPS_CONFIG18 0x30d8 13046#define mmDSCC2_DSCC_PPS_CONFIG18_BASE_IDX 2 13047#define mmDSCC2_DSCC_PPS_CONFIG19 0x30d9 13048#define mmDSCC2_DSCC_PPS_CONFIG19_BASE_IDX 2 13049#define mmDSCC2_DSCC_PPS_CONFIG20 0x30da 13050#define mmDSCC2_DSCC_PPS_CONFIG20_BASE_IDX 2 13051#define mmDSCC2_DSCC_PPS_CONFIG21 0x30db 13052#define mmDSCC2_DSCC_PPS_CONFIG21_BASE_IDX 2 13053#define mmDSCC2_DSCC_PPS_CONFIG22 0x30dc 13054#define mmDSCC2_DSCC_PPS_CONFIG22_BASE_IDX 2 13055#define mmDSCC2_DSCC_MEM_POWER_CONTROL 0x30dd 13056#define mmDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 13057#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER 0x30de 13058#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 13059#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER 0x30df 13060#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 13061#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER 0x30e0 13062#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 13063#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER 0x30e1 13064#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 13065#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER 0x30e2 13066#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 13067#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER 0x30e3 13068#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 13069#define mmDSCC2_DSCC_MAX_ABS_ERROR0 0x30e4 13070#define mmDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 13071#define mmDSCC2_DSCC_MAX_ABS_ERROR1 0x30e5 13072#define mmDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 13073#define mmDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x30e6 13074#define mmDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 13075#define mmDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x30e7 13076#define mmDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 13077#define mmDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x30e8 13078#define mmDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 13079#define mmDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x30e9 13080#define mmDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 13081#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x30ea 13082#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 13083#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x30eb 13084#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 13085#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x30ec 13086#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 13087#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x30ed 13088#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 13089 13090 13091// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 13092// base address: 0xc420 13093#define mmDC_PERFMON23_PERFCOUNTER_CNTL 0x3108 13094#define mmDC_PERFMON23_PERFCOUNTER_CNTL_BASE_IDX 2 13095#define mmDC_PERFMON23_PERFCOUNTER_CNTL2 0x3109 13096#define mmDC_PERFMON23_PERFCOUNTER_CNTL2_BASE_IDX 2 13097#define mmDC_PERFMON23_PERFCOUNTER_STATE 0x310a 13098#define mmDC_PERFMON23_PERFCOUNTER_STATE_BASE_IDX 2 13099#define mmDC_PERFMON23_PERFMON_CNTL 0x310b 13100#define mmDC_PERFMON23_PERFMON_CNTL_BASE_IDX 2 13101#define mmDC_PERFMON23_PERFMON_CNTL2 0x310c 13102#define mmDC_PERFMON23_PERFMON_CNTL2_BASE_IDX 2 13103#define mmDC_PERFMON23_PERFMON_CVALUE_INT_MISC 0x310d 13104#define mmDC_PERFMON23_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 13105#define mmDC_PERFMON23_PERFMON_CVALUE_LOW 0x310e 13106#define mmDC_PERFMON23_PERFMON_CVALUE_LOW_BASE_IDX 2 13107#define mmDC_PERFMON23_PERFMON_HI 0x310f 13108#define mmDC_PERFMON23_PERFMON_HI_BASE_IDX 2 13109#define mmDC_PERFMON23_PERFMON_LOW 0x3110 13110#define mmDC_PERFMON23_PERFMON_LOW_BASE_IDX 2 13111 13112 13113// addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec 13114// base address: 0x450 13115#define mmDSC_TOP3_DSC_TOP_CONTROL 0x3114 13116#define mmDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX 2 13117#define mmDSC_TOP3_DSC_DEBUG_CONTROL 0x3115 13118#define mmDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX 2 13119 13120 13121// addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec 13122// base address: 0x450 13123#define mmDSCCIF3_DSCCIF_CONFIG0 0x3119 13124#define mmDSCCIF3_DSCCIF_CONFIG0_BASE_IDX 2 13125#define mmDSCCIF3_DSCCIF_CONFIG1 0x311a 13126#define mmDSCCIF3_DSCCIF_CONFIG1_BASE_IDX 2 13127 13128 13129// addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec 13130// base address: 0x450 13131#define mmDSCC3_DSCC_CONFIG0 0x311e 13132#define mmDSCC3_DSCC_CONFIG0_BASE_IDX 2 13133#define mmDSCC3_DSCC_CONFIG1 0x311f 13134#define mmDSCC3_DSCC_CONFIG1_BASE_IDX 2 13135#define mmDSCC3_DSCC_STATUS 0x3120 13136#define mmDSCC3_DSCC_STATUS_BASE_IDX 2 13137#define mmDSCC3_DSCC_INTERRUPT_CONTROL_STATUS 0x3121 13138#define mmDSCC3_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 13139#define mmDSCC3_DSCC_PPS_CONFIG0 0x3122 13140#define mmDSCC3_DSCC_PPS_CONFIG0_BASE_IDX 2 13141#define mmDSCC3_DSCC_PPS_CONFIG1 0x3123 13142#define mmDSCC3_DSCC_PPS_CONFIG1_BASE_IDX 2 13143#define mmDSCC3_DSCC_PPS_CONFIG2 0x3124 13144#define mmDSCC3_DSCC_PPS_CONFIG2_BASE_IDX 2 13145#define mmDSCC3_DSCC_PPS_CONFIG3 0x3125 13146#define mmDSCC3_DSCC_PPS_CONFIG3_BASE_IDX 2 13147#define mmDSCC3_DSCC_PPS_CONFIG4 0x3126 13148#define mmDSCC3_DSCC_PPS_CONFIG4_BASE_IDX 2 13149#define mmDSCC3_DSCC_PPS_CONFIG5 0x3127 13150#define mmDSCC3_DSCC_PPS_CONFIG5_BASE_IDX 2 13151#define mmDSCC3_DSCC_PPS_CONFIG6 0x3128 13152#define mmDSCC3_DSCC_PPS_CONFIG6_BASE_IDX 2 13153#define mmDSCC3_DSCC_PPS_CONFIG7 0x3129 13154#define mmDSCC3_DSCC_PPS_CONFIG7_BASE_IDX 2 13155#define mmDSCC3_DSCC_PPS_CONFIG8 0x312a 13156#define mmDSCC3_DSCC_PPS_CONFIG8_BASE_IDX 2 13157#define mmDSCC3_DSCC_PPS_CONFIG9 0x312b 13158#define mmDSCC3_DSCC_PPS_CONFIG9_BASE_IDX 2 13159#define mmDSCC3_DSCC_PPS_CONFIG10 0x312c 13160#define mmDSCC3_DSCC_PPS_CONFIG10_BASE_IDX 2 13161#define mmDSCC3_DSCC_PPS_CONFIG11 0x312d 13162#define mmDSCC3_DSCC_PPS_CONFIG11_BASE_IDX 2 13163#define mmDSCC3_DSCC_PPS_CONFIG12 0x312e 13164#define mmDSCC3_DSCC_PPS_CONFIG12_BASE_IDX 2 13165#define mmDSCC3_DSCC_PPS_CONFIG13 0x312f 13166#define mmDSCC3_DSCC_PPS_CONFIG13_BASE_IDX 2 13167#define mmDSCC3_DSCC_PPS_CONFIG14 0x3130 13168#define mmDSCC3_DSCC_PPS_CONFIG14_BASE_IDX 2 13169#define mmDSCC3_DSCC_PPS_CONFIG15 0x3131 13170#define mmDSCC3_DSCC_PPS_CONFIG15_BASE_IDX 2 13171#define mmDSCC3_DSCC_PPS_CONFIG16 0x3132 13172#define mmDSCC3_DSCC_PPS_CONFIG16_BASE_IDX 2 13173#define mmDSCC3_DSCC_PPS_CONFIG17 0x3133 13174#define mmDSCC3_DSCC_PPS_CONFIG17_BASE_IDX 2 13175#define mmDSCC3_DSCC_PPS_CONFIG18 0x3134 13176#define mmDSCC3_DSCC_PPS_CONFIG18_BASE_IDX 2 13177#define mmDSCC3_DSCC_PPS_CONFIG19 0x3135 13178#define mmDSCC3_DSCC_PPS_CONFIG19_BASE_IDX 2 13179#define mmDSCC3_DSCC_PPS_CONFIG20 0x3136 13180#define mmDSCC3_DSCC_PPS_CONFIG20_BASE_IDX 2 13181#define mmDSCC3_DSCC_PPS_CONFIG21 0x3137 13182#define mmDSCC3_DSCC_PPS_CONFIG21_BASE_IDX 2 13183#define mmDSCC3_DSCC_PPS_CONFIG22 0x3138 13184#define mmDSCC3_DSCC_PPS_CONFIG22_BASE_IDX 2 13185#define mmDSCC3_DSCC_MEM_POWER_CONTROL 0x3139 13186#define mmDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 13187#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER 0x313a 13188#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 13189#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER 0x313b 13190#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 13191#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER 0x313c 13192#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 13193#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER 0x313d 13194#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 13195#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER 0x313e 13196#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 13197#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER 0x313f 13198#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 13199#define mmDSCC3_DSCC_MAX_ABS_ERROR0 0x3140 13200#define mmDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 13201#define mmDSCC3_DSCC_MAX_ABS_ERROR1 0x3141 13202#define mmDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 13203#define mmDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x3142 13204#define mmDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 13205#define mmDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x3143 13206#define mmDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 13207#define mmDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3144 13208#define mmDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 13209#define mmDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3145 13210#define mmDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 13211#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3146 13212#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 13213#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3147 13214#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 13215#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3148 13216#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 13217#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3149 13218#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 13219 13220 13221// addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 13222// base address: 0xc590 13223#define mmDC_PERFMON24_PERFCOUNTER_CNTL 0x3164 13224#define mmDC_PERFMON24_PERFCOUNTER_CNTL_BASE_IDX 2 13225#define mmDC_PERFMON24_PERFCOUNTER_CNTL2 0x3165 13226#define mmDC_PERFMON24_PERFCOUNTER_CNTL2_BASE_IDX 2 13227#define mmDC_PERFMON24_PERFCOUNTER_STATE 0x3166 13228#define mmDC_PERFMON24_PERFCOUNTER_STATE_BASE_IDX 2 13229#define mmDC_PERFMON24_PERFMON_CNTL 0x3167 13230#define mmDC_PERFMON24_PERFMON_CNTL_BASE_IDX 2 13231#define mmDC_PERFMON24_PERFMON_CNTL2 0x3168 13232#define mmDC_PERFMON24_PERFMON_CNTL2_BASE_IDX 2 13233#define mmDC_PERFMON24_PERFMON_CVALUE_INT_MISC 0x3169 13234#define mmDC_PERFMON24_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 13235#define mmDC_PERFMON24_PERFMON_CVALUE_LOW 0x316a 13236#define mmDC_PERFMON24_PERFMON_CVALUE_LOW_BASE_IDX 2 13237#define mmDC_PERFMON24_PERFMON_HI 0x316b 13238#define mmDC_PERFMON24_PERFMON_HI_BASE_IDX 2 13239#define mmDC_PERFMON24_PERFMON_LOW 0x316c 13240#define mmDC_PERFMON24_PERFMON_LOW_BASE_IDX 2 13241 13242 13243// addressBlock: dce_dc_dsc4_dispdec_dsc_top_dispdec 13244// base address: 0x5c0 13245#define mmDSC_TOP4_DSC_TOP_CONTROL 0x3170 13246#define mmDSC_TOP4_DSC_TOP_CONTROL_BASE_IDX 2 13247#define mmDSC_TOP4_DSC_DEBUG_CONTROL 0x3171 13248#define mmDSC_TOP4_DSC_DEBUG_CONTROL_BASE_IDX 2 13249 13250 13251// addressBlock: dce_dc_dsc4_dispdec_dsccif_dispdec 13252// base address: 0x5c0 13253#define mmDSCCIF4_DSCCIF_CONFIG0 0x3175 13254#define mmDSCCIF4_DSCCIF_CONFIG0_BASE_IDX 2 13255#define mmDSCCIF4_DSCCIF_CONFIG1 0x3176 13256#define mmDSCCIF4_DSCCIF_CONFIG1_BASE_IDX 2 13257 13258 13259// addressBlock: dce_dc_dsc4_dispdec_dscc_dispdec 13260// base address: 0x5c0 13261#define mmDSCC4_DSCC_CONFIG0 0x317a 13262#define mmDSCC4_DSCC_CONFIG0_BASE_IDX 2 13263#define mmDSCC4_DSCC_CONFIG1 0x317b 13264#define mmDSCC4_DSCC_CONFIG1_BASE_IDX 2 13265#define mmDSCC4_DSCC_STATUS 0x317c 13266#define mmDSCC4_DSCC_STATUS_BASE_IDX 2 13267#define mmDSCC4_DSCC_INTERRUPT_CONTROL_STATUS 0x317d 13268#define mmDSCC4_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 13269#define mmDSCC4_DSCC_PPS_CONFIG0 0x317e 13270#define mmDSCC4_DSCC_PPS_CONFIG0_BASE_IDX 2 13271#define mmDSCC4_DSCC_PPS_CONFIG1 0x317f 13272#define mmDSCC4_DSCC_PPS_CONFIG1_BASE_IDX 2 13273#define mmDSCC4_DSCC_PPS_CONFIG2 0x3180 13274#define mmDSCC4_DSCC_PPS_CONFIG2_BASE_IDX 2 13275#define mmDSCC4_DSCC_PPS_CONFIG3 0x3181 13276#define mmDSCC4_DSCC_PPS_CONFIG3_BASE_IDX 2 13277#define mmDSCC4_DSCC_PPS_CONFIG4 0x3182 13278#define mmDSCC4_DSCC_PPS_CONFIG4_BASE_IDX 2 13279#define mmDSCC4_DSCC_PPS_CONFIG5 0x3183 13280#define mmDSCC4_DSCC_PPS_CONFIG5_BASE_IDX 2 13281#define mmDSCC4_DSCC_PPS_CONFIG6 0x3184 13282#define mmDSCC4_DSCC_PPS_CONFIG6_BASE_IDX 2 13283#define mmDSCC4_DSCC_PPS_CONFIG7 0x3185 13284#define mmDSCC4_DSCC_PPS_CONFIG7_BASE_IDX 2 13285#define mmDSCC4_DSCC_PPS_CONFIG8 0x3186 13286#define mmDSCC4_DSCC_PPS_CONFIG8_BASE_IDX 2 13287#define mmDSCC4_DSCC_PPS_CONFIG9 0x3187 13288#define mmDSCC4_DSCC_PPS_CONFIG9_BASE_IDX 2 13289#define mmDSCC4_DSCC_PPS_CONFIG10 0x3188 13290#define mmDSCC4_DSCC_PPS_CONFIG10_BASE_IDX 2 13291#define mmDSCC4_DSCC_PPS_CONFIG11 0x3189 13292#define mmDSCC4_DSCC_PPS_CONFIG11_BASE_IDX 2 13293#define mmDSCC4_DSCC_PPS_CONFIG12 0x318a 13294#define mmDSCC4_DSCC_PPS_CONFIG12_BASE_IDX 2 13295#define mmDSCC4_DSCC_PPS_CONFIG13 0x318b 13296#define mmDSCC4_DSCC_PPS_CONFIG13_BASE_IDX 2 13297#define mmDSCC4_DSCC_PPS_CONFIG14 0x318c 13298#define mmDSCC4_DSCC_PPS_CONFIG14_BASE_IDX 2 13299#define mmDSCC4_DSCC_PPS_CONFIG15 0x318d 13300#define mmDSCC4_DSCC_PPS_CONFIG15_BASE_IDX 2 13301#define mmDSCC4_DSCC_PPS_CONFIG16 0x318e 13302#define mmDSCC4_DSCC_PPS_CONFIG16_BASE_IDX 2 13303#define mmDSCC4_DSCC_PPS_CONFIG17 0x318f 13304#define mmDSCC4_DSCC_PPS_CONFIG17_BASE_IDX 2 13305#define mmDSCC4_DSCC_PPS_CONFIG18 0x3190 13306#define mmDSCC4_DSCC_PPS_CONFIG18_BASE_IDX 2 13307#define mmDSCC4_DSCC_PPS_CONFIG19 0x3191 13308#define mmDSCC4_DSCC_PPS_CONFIG19_BASE_IDX 2 13309#define mmDSCC4_DSCC_PPS_CONFIG20 0x3192 13310#define mmDSCC4_DSCC_PPS_CONFIG20_BASE_IDX 2 13311#define mmDSCC4_DSCC_PPS_CONFIG21 0x3193 13312#define mmDSCC4_DSCC_PPS_CONFIG21_BASE_IDX 2 13313#define mmDSCC4_DSCC_PPS_CONFIG22 0x3194 13314#define mmDSCC4_DSCC_PPS_CONFIG22_BASE_IDX 2 13315#define mmDSCC4_DSCC_MEM_POWER_CONTROL 0x3195 13316#define mmDSCC4_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 13317#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3196 13318#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 13319#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3197 13320#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 13321#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3198 13322#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 13323#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3199 13324#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 13325#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER 0x319a 13326#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 13327#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER 0x319b 13328#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 13329#define mmDSCC4_DSCC_MAX_ABS_ERROR0 0x319c 13330#define mmDSCC4_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 13331#define mmDSCC4_DSCC_MAX_ABS_ERROR1 0x319d 13332#define mmDSCC4_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 13333#define mmDSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x319e 13334#define mmDSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 13335#define mmDSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x319f 13336#define mmDSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 13337#define mmDSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x31a0 13338#define mmDSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 13339#define mmDSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x31a1 13340#define mmDSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 13341#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x31a2 13342#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 13343#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x31a3 13344#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 13345#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x31a4 13346#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 13347#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x31a5 13348#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 13349 13350 13351// addressBlock: dce_dc_dsc4_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 13352// base address: 0xc700 13353#define mmDC_PERFMON25_PERFCOUNTER_CNTL 0x31c0 13354#define mmDC_PERFMON25_PERFCOUNTER_CNTL_BASE_IDX 2 13355#define mmDC_PERFMON25_PERFCOUNTER_CNTL2 0x31c1 13356#define mmDC_PERFMON25_PERFCOUNTER_CNTL2_BASE_IDX 2 13357#define mmDC_PERFMON25_PERFCOUNTER_STATE 0x31c2 13358#define mmDC_PERFMON25_PERFCOUNTER_STATE_BASE_IDX 2 13359#define mmDC_PERFMON25_PERFMON_CNTL 0x31c3 13360#define mmDC_PERFMON25_PERFMON_CNTL_BASE_IDX 2 13361#define mmDC_PERFMON25_PERFMON_CNTL2 0x31c4 13362#define mmDC_PERFMON25_PERFMON_CNTL2_BASE_IDX 2 13363#define mmDC_PERFMON25_PERFMON_CVALUE_INT_MISC 0x31c5 13364#define mmDC_PERFMON25_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 13365#define mmDC_PERFMON25_PERFMON_CVALUE_LOW 0x31c6 13366#define mmDC_PERFMON25_PERFMON_CVALUE_LOW_BASE_IDX 2 13367#define mmDC_PERFMON25_PERFMON_HI 0x31c7 13368#define mmDC_PERFMON25_PERFMON_HI_BASE_IDX 2 13369#define mmDC_PERFMON25_PERFMON_LOW 0x31c8 13370#define mmDC_PERFMON25_PERFMON_LOW_BASE_IDX 2 13371 13372 13373// addressBlock: dce_dc_dsc5_dispdec_dsc_top_dispdec 13374// base address: 0x730 13375#define mmDSC_TOP5_DSC_TOP_CONTROL 0x31cc 13376#define mmDSC_TOP5_DSC_TOP_CONTROL_BASE_IDX 2 13377#define mmDSC_TOP5_DSC_DEBUG_CONTROL 0x31cd 13378#define mmDSC_TOP5_DSC_DEBUG_CONTROL_BASE_IDX 2 13379 13380// addressBlock: dce_dc_dsc5_dispdec_dsccif_dispdec 13381// base address: 0x730 13382#define mmDSCCIF5_DSCCIF_CONFIG0 0x31d1 13383#define mmDSCCIF5_DSCCIF_CONFIG0_BASE_IDX 2 13384#define mmDSCCIF5_DSCCIF_CONFIG1 0x31d2 13385#define mmDSCCIF5_DSCCIF_CONFIG1_BASE_IDX 2 13386 13387 13388// addressBlock: dce_dc_dsc5_dispdec_dscc_dispdec 13389// base address: 0x730 13390#define mmDSCC5_DSCC_CONFIG0 0x31d6 13391#define mmDSCC5_DSCC_CONFIG0_BASE_IDX 2 13392#define mmDSCC5_DSCC_CONFIG1 0x31d7 13393#define mmDSCC5_DSCC_CONFIG1_BASE_IDX 2 13394#define mmDSCC5_DSCC_STATUS 0x31d8 13395#define mmDSCC5_DSCC_STATUS_BASE_IDX 2 13396#define mmDSCC5_DSCC_INTERRUPT_CONTROL_STATUS 0x31d9 13397#define mmDSCC5_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 13398#define mmDSCC5_DSCC_PPS_CONFIG0 0x31da 13399#define mmDSCC5_DSCC_PPS_CONFIG0_BASE_IDX 2 13400#define mmDSCC5_DSCC_PPS_CONFIG1 0x31db 13401#define mmDSCC5_DSCC_PPS_CONFIG1_BASE_IDX 2 13402#define mmDSCC5_DSCC_PPS_CONFIG2 0x31dc 13403#define mmDSCC5_DSCC_PPS_CONFIG2_BASE_IDX 2 13404#define mmDSCC5_DSCC_PPS_CONFIG3 0x31dd 13405#define mmDSCC5_DSCC_PPS_CONFIG3_BASE_IDX 2 13406#define mmDSCC5_DSCC_PPS_CONFIG4 0x31de 13407#define mmDSCC5_DSCC_PPS_CONFIG4_BASE_IDX 2 13408#define mmDSCC5_DSCC_PPS_CONFIG5 0x31df 13409#define mmDSCC5_DSCC_PPS_CONFIG5_BASE_IDX 2 13410#define mmDSCC5_DSCC_PPS_CONFIG6 0x31e0 13411#define mmDSCC5_DSCC_PPS_CONFIG6_BASE_IDX 2 13412#define mmDSCC5_DSCC_PPS_CONFIG7 0x31e1 13413#define mmDSCC5_DSCC_PPS_CONFIG7_BASE_IDX 2 13414#define mmDSCC5_DSCC_PPS_CONFIG8 0x31e2 13415#define mmDSCC5_DSCC_PPS_CONFIG8_BASE_IDX 2 13416#define mmDSCC5_DSCC_PPS_CONFIG9 0x31e3 13417#define mmDSCC5_DSCC_PPS_CONFIG9_BASE_IDX 2 13418#define mmDSCC5_DSCC_PPS_CONFIG10 0x31e4 13419#define mmDSCC5_DSCC_PPS_CONFIG10_BASE_IDX 2 13420#define mmDSCC5_DSCC_PPS_CONFIG11 0x31e5 13421#define mmDSCC5_DSCC_PPS_CONFIG11_BASE_IDX 2 13422#define mmDSCC5_DSCC_PPS_CONFIG12 0x31e6 13423#define mmDSCC5_DSCC_PPS_CONFIG12_BASE_IDX 2 13424#define mmDSCC5_DSCC_PPS_CONFIG13 0x31e7 13425#define mmDSCC5_DSCC_PPS_CONFIG13_BASE_IDX 2 13426#define mmDSCC5_DSCC_PPS_CONFIG14 0x31e8 13427#define mmDSCC5_DSCC_PPS_CONFIG14_BASE_IDX 2 13428#define mmDSCC5_DSCC_PPS_CONFIG15 0x31e9 13429#define mmDSCC5_DSCC_PPS_CONFIG15_BASE_IDX 2 13430#define mmDSCC5_DSCC_PPS_CONFIG16 0x31ea 13431#define mmDSCC5_DSCC_PPS_CONFIG16_BASE_IDX 2 13432#define mmDSCC5_DSCC_PPS_CONFIG17 0x31eb 13433#define mmDSCC5_DSCC_PPS_CONFIG17_BASE_IDX 2 13434#define mmDSCC5_DSCC_PPS_CONFIG18 0x31ec 13435#define mmDSCC5_DSCC_PPS_CONFIG18_BASE_IDX 2 13436#define mmDSCC5_DSCC_PPS_CONFIG19 0x31ed 13437#define mmDSCC5_DSCC_PPS_CONFIG19_BASE_IDX 2 13438#define mmDSCC5_DSCC_PPS_CONFIG20 0x31ee 13439#define mmDSCC5_DSCC_PPS_CONFIG20_BASE_IDX 2 13440#define mmDSCC5_DSCC_PPS_CONFIG21 0x31ef 13441#define mmDSCC5_DSCC_PPS_CONFIG21_BASE_IDX 2 13442#define mmDSCC5_DSCC_PPS_CONFIG22 0x31f0 13443#define mmDSCC5_DSCC_PPS_CONFIG22_BASE_IDX 2 13444#define mmDSCC5_DSCC_MEM_POWER_CONTROL 0x31f1 13445#define mmDSCC5_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 13446#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER 0x31f2 13447#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 13448#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER 0x31f3 13449#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 13450#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER 0x31f4 13451#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 13452#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER 0x31f5 13453#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 13454#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER 0x31f6 13455#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 13456#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER 0x31f7 13457#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 13458#define mmDSCC5_DSCC_MAX_ABS_ERROR0 0x31f8 13459#define mmDSCC5_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 13460#define mmDSCC5_DSCC_MAX_ABS_ERROR1 0x31f9 13461#define mmDSCC5_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 13462#define mmDSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x31fa 13463#define mmDSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 13464#define mmDSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x31fb 13465#define mmDSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 13466#define mmDSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x31fc 13467#define mmDSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 13468#define mmDSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x31fd 13469#define mmDSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 13470#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x31fe 13471#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 13472#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x31ff 13473#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 13474#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3200 13475#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 13476#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3201 13477#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 13478 13479 13480// addressBlock: dce_dc_dsc5_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 13481// base address: 0xc870 13482#define mmDC_PERFMON26_PERFCOUNTER_CNTL 0x321c 13483#define mmDC_PERFMON26_PERFCOUNTER_CNTL_BASE_IDX 2 13484#define mmDC_PERFMON26_PERFCOUNTER_CNTL2 0x321d 13485#define mmDC_PERFMON26_PERFCOUNTER_CNTL2_BASE_IDX 2 13486#define mmDC_PERFMON26_PERFCOUNTER_STATE 0x321e 13487#define mmDC_PERFMON26_PERFCOUNTER_STATE_BASE_IDX 2 13488#define mmDC_PERFMON26_PERFMON_CNTL 0x321f 13489#define mmDC_PERFMON26_PERFMON_CNTL_BASE_IDX 2 13490#define mmDC_PERFMON26_PERFMON_CNTL2 0x3220 13491#define mmDC_PERFMON26_PERFMON_CNTL2_BASE_IDX 2 13492#define mmDC_PERFMON26_PERFMON_CVALUE_INT_MISC 0x3221 13493#define mmDC_PERFMON26_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 13494#define mmDC_PERFMON26_PERFMON_CVALUE_LOW 0x3222 13495#define mmDC_PERFMON26_PERFMON_CVALUE_LOW_BASE_IDX 2 13496#define mmDC_PERFMON26_PERFMON_HI 0x3223 13497#define mmDC_PERFMON26_PERFMON_HI_BASE_IDX 2 13498#define mmDC_PERFMON26_PERFMON_LOW 0x3224 13499#define mmDC_PERFMON26_PERFMON_LOW_BASE_IDX 2 13500 13501 13502// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec 13503// base address: 0x0 13504#define mmDWB_ENABLE_CLK_CTRL 0x3228 13505#define mmDWB_ENABLE_CLK_CTRL_BASE_IDX 2 13506#define mmDWB_MEM_PWR_CTRL 0x3229 13507#define mmDWB_MEM_PWR_CTRL_BASE_IDX 2 13508#define mmFC_MODE_CTRL 0x322a 13509#define mmFC_MODE_CTRL_BASE_IDX 2 13510#define mmFC_FLOW_CTRL 0x322b 13511#define mmFC_FLOW_CTRL_BASE_IDX 2 13512#define mmFC_WINDOW_START 0x322c 13513#define mmFC_WINDOW_START_BASE_IDX 2 13514#define mmFC_WINDOW_SIZE 0x322d 13515#define mmFC_WINDOW_SIZE_BASE_IDX 2 13516#define mmFC_SOURCE_SIZE 0x322e 13517#define mmFC_SOURCE_SIZE_BASE_IDX 2 13518#define mmDWB_UPDATE_CTRL 0x322f 13519#define mmDWB_UPDATE_CTRL_BASE_IDX 2 13520#define mmDWB_CRC_CTRL 0x3230 13521#define mmDWB_CRC_CTRL_BASE_IDX 2 13522#define mmDWB_CRC_MASK_R_G 0x3231 13523#define mmDWB_CRC_MASK_R_G_BASE_IDX 2 13524#define mmDWB_CRC_MASK_B_A 0x3232 13525#define mmDWB_CRC_MASK_B_A_BASE_IDX 2 13526#define mmDWB_CRC_VAL_R_G 0x3233 13527#define mmDWB_CRC_VAL_R_G_BASE_IDX 2 13528#define mmDWB_CRC_VAL_B_A 0x3234 13529#define mmDWB_CRC_VAL_B_A_BASE_IDX 2 13530#define mmDWB_OUT_CTRL 0x3235 13531#define mmDWB_OUT_CTRL_BASE_IDX 2 13532#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_EN 0x3236 13533#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX 2 13534#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT 0x3237 13535#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX 2 13536#define mmDWB_HOST_READ_CONTROL 0x3238 13537#define mmDWB_HOST_READ_CONTROL_BASE_IDX 2 13538#define mmDWB_OVERFLOW_STATUS 0x3239 13539#define mmDWB_OVERFLOW_STATUS_BASE_IDX 2 13540#define mmDWB_OVERFLOW_COUNTER 0x323a 13541#define mmDWB_OVERFLOW_COUNTER_BASE_IDX 2 13542#define mmDWB_SOFT_RESET 0x323b 13543#define mmDWB_SOFT_RESET_BASE_IDX 2 13544 13545 13546// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec 13547// base address: 0xca20 13548#define mmDC_PERFMON27_PERFCOUNTER_CNTL 0x3288 13549#define mmDC_PERFMON27_PERFCOUNTER_CNTL_BASE_IDX 2 13550#define mmDC_PERFMON27_PERFCOUNTER_CNTL2 0x3289 13551#define mmDC_PERFMON27_PERFCOUNTER_CNTL2_BASE_IDX 2 13552#define mmDC_PERFMON27_PERFCOUNTER_STATE 0x328a 13553#define mmDC_PERFMON27_PERFCOUNTER_STATE_BASE_IDX 2 13554#define mmDC_PERFMON27_PERFMON_CNTL 0x328b 13555#define mmDC_PERFMON27_PERFMON_CNTL_BASE_IDX 2 13556#define mmDC_PERFMON27_PERFMON_CNTL2 0x328c 13557#define mmDC_PERFMON27_PERFMON_CNTL2_BASE_IDX 2 13558#define mmDC_PERFMON27_PERFMON_CVALUE_INT_MISC 0x328d 13559#define mmDC_PERFMON27_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 13560#define mmDC_PERFMON27_PERFMON_CVALUE_LOW 0x328e 13561#define mmDC_PERFMON27_PERFMON_CVALUE_LOW_BASE_IDX 2 13562#define mmDC_PERFMON27_PERFMON_HI 0x328f 13563#define mmDC_PERFMON27_PERFMON_HI_BASE_IDX 2 13564#define mmDC_PERFMON27_PERFMON_LOW 0x3290 13565#define mmDC_PERFMON27_PERFMON_LOW_BASE_IDX 2 13566 13567 13568// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec 13569// base address: 0x0 13570#define mmDWB_HDR_MULT_COEF 0x3294 13571#define mmDWB_HDR_MULT_COEF_BASE_IDX 2 13572#define mmDWB_GAMUT_REMAP_MODE 0x3295 13573#define mmDWB_GAMUT_REMAP_MODE_BASE_IDX 2 13574#define mmDWB_GAMUT_REMAP_COEF_FORMAT 0x3296 13575#define mmDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 2 13576#define mmDWB_GAMUT_REMAPA_C11_C12 0x3297 13577#define mmDWB_GAMUT_REMAPA_C11_C12_BASE_IDX 2 13578#define mmDWB_GAMUT_REMAPA_C13_C14 0x3298 13579#define mmDWB_GAMUT_REMAPA_C13_C14_BASE_IDX 2 13580#define mmDWB_GAMUT_REMAPA_C21_C22 0x3299 13581#define mmDWB_GAMUT_REMAPA_C21_C22_BASE_IDX 2 13582#define mmDWB_GAMUT_REMAPA_C23_C24 0x329a 13583#define mmDWB_GAMUT_REMAPA_C23_C24_BASE_IDX 2 13584#define mmDWB_GAMUT_REMAPA_C31_C32 0x329b 13585#define mmDWB_GAMUT_REMAPA_C31_C32_BASE_IDX 2 13586#define mmDWB_GAMUT_REMAPA_C33_C34 0x329c 13587#define mmDWB_GAMUT_REMAPA_C33_C34_BASE_IDX 2 13588#define mmDWB_GAMUT_REMAPB_C11_C12 0x329d 13589#define mmDWB_GAMUT_REMAPB_C11_C12_BASE_IDX 2 13590#define mmDWB_GAMUT_REMAPB_C13_C14 0x329e 13591#define mmDWB_GAMUT_REMAPB_C13_C14_BASE_IDX 2 13592#define mmDWB_GAMUT_REMAPB_C21_C22 0x329f 13593#define mmDWB_GAMUT_REMAPB_C21_C22_BASE_IDX 2 13594#define mmDWB_GAMUT_REMAPB_C23_C24 0x32a0 13595#define mmDWB_GAMUT_REMAPB_C23_C24_BASE_IDX 2 13596#define mmDWB_GAMUT_REMAPB_C31_C32 0x32a1 13597#define mmDWB_GAMUT_REMAPB_C31_C32_BASE_IDX 2 13598#define mmDWB_GAMUT_REMAPB_C33_C34 0x32a2 13599#define mmDWB_GAMUT_REMAPB_C33_C34_BASE_IDX 2 13600#define mmDWB_OGAM_CONTROL 0x32a3 13601#define mmDWB_OGAM_CONTROL_BASE_IDX 2 13602#define mmDWB_OGAM_LUT_INDEX 0x32a4 13603#define mmDWB_OGAM_LUT_INDEX_BASE_IDX 2 13604#define mmDWB_OGAM_LUT_DATA 0x32a5 13605#define mmDWB_OGAM_LUT_DATA_BASE_IDX 2 13606#define mmDWB_OGAM_LUT_CONTROL 0x32a6 13607#define mmDWB_OGAM_LUT_CONTROL_BASE_IDX 2 13608#define mmDWB_OGAM_RAMA_START_CNTL_B 0x32a7 13609#define mmDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 13610#define mmDWB_OGAM_RAMA_START_CNTL_G 0x32a8 13611#define mmDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 13612#define mmDWB_OGAM_RAMA_START_CNTL_R 0x32a9 13613#define mmDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 13614#define mmDWB_OGAM_RAMA_START_BASE_CNTL_B 0x32aa 13615#define mmDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 13616#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_B 0x32ab 13617#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 13618#define mmDWB_OGAM_RAMA_START_BASE_CNTL_G 0x32ac 13619#define mmDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 13620#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_G 0x32ad 13621#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 13622#define mmDWB_OGAM_RAMA_START_BASE_CNTL_R 0x32ae 13623#define mmDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 13624#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_R 0x32af 13625#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 13626#define mmDWB_OGAM_RAMA_END_CNTL1_B 0x32b0 13627#define mmDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 13628#define mmDWB_OGAM_RAMA_END_CNTL2_B 0x32b1 13629#define mmDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 13630#define mmDWB_OGAM_RAMA_END_CNTL1_G 0x32b2 13631#define mmDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 13632#define mmDWB_OGAM_RAMA_END_CNTL2_G 0x32b3 13633#define mmDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 13634#define mmDWB_OGAM_RAMA_END_CNTL1_R 0x32b4 13635#define mmDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 13636#define mmDWB_OGAM_RAMA_END_CNTL2_R 0x32b5 13637#define mmDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 13638#define mmDWB_OGAM_RAMA_OFFSET_B 0x32b6 13639#define mmDWB_OGAM_RAMA_OFFSET_B_BASE_IDX 2 13640#define mmDWB_OGAM_RAMA_OFFSET_G 0x32b7 13641#define mmDWB_OGAM_RAMA_OFFSET_G_BASE_IDX 2 13642#define mmDWB_OGAM_RAMA_OFFSET_R 0x32b8 13643#define mmDWB_OGAM_RAMA_OFFSET_R_BASE_IDX 2 13644#define mmDWB_OGAM_RAMA_REGION_0_1 0x32b9 13645#define mmDWB_OGAM_RAMA_REGION_0_1_BASE_IDX 2 13646#define mmDWB_OGAM_RAMA_REGION_2_3 0x32ba 13647#define mmDWB_OGAM_RAMA_REGION_2_3_BASE_IDX 2 13648#define mmDWB_OGAM_RAMA_REGION_4_5 0x32bb 13649#define mmDWB_OGAM_RAMA_REGION_4_5_BASE_IDX 2 13650#define mmDWB_OGAM_RAMA_REGION_6_7 0x32bc 13651#define mmDWB_OGAM_RAMA_REGION_6_7_BASE_IDX 2 13652#define mmDWB_OGAM_RAMA_REGION_8_9 0x32bd 13653#define mmDWB_OGAM_RAMA_REGION_8_9_BASE_IDX 2 13654#define mmDWB_OGAM_RAMA_REGION_10_11 0x32be 13655#define mmDWB_OGAM_RAMA_REGION_10_11_BASE_IDX 2 13656#define mmDWB_OGAM_RAMA_REGION_12_13 0x32bf 13657#define mmDWB_OGAM_RAMA_REGION_12_13_BASE_IDX 2 13658#define mmDWB_OGAM_RAMA_REGION_14_15 0x32c0 13659#define mmDWB_OGAM_RAMA_REGION_14_15_BASE_IDX 2 13660#define mmDWB_OGAM_RAMA_REGION_16_17 0x32c1 13661#define mmDWB_OGAM_RAMA_REGION_16_17_BASE_IDX 2 13662#define mmDWB_OGAM_RAMA_REGION_18_19 0x32c2 13663#define mmDWB_OGAM_RAMA_REGION_18_19_BASE_IDX 2 13664#define mmDWB_OGAM_RAMA_REGION_20_21 0x32c3 13665#define mmDWB_OGAM_RAMA_REGION_20_21_BASE_IDX 2 13666#define mmDWB_OGAM_RAMA_REGION_22_23 0x32c4 13667#define mmDWB_OGAM_RAMA_REGION_22_23_BASE_IDX 2 13668#define mmDWB_OGAM_RAMA_REGION_24_25 0x32c5 13669#define mmDWB_OGAM_RAMA_REGION_24_25_BASE_IDX 2 13670#define mmDWB_OGAM_RAMA_REGION_26_27 0x32c6 13671#define mmDWB_OGAM_RAMA_REGION_26_27_BASE_IDX 2 13672#define mmDWB_OGAM_RAMA_REGION_28_29 0x32c7 13673#define mmDWB_OGAM_RAMA_REGION_28_29_BASE_IDX 2 13674#define mmDWB_OGAM_RAMA_REGION_30_31 0x32c8 13675#define mmDWB_OGAM_RAMA_REGION_30_31_BASE_IDX 2 13676#define mmDWB_OGAM_RAMA_REGION_32_33 0x32c9 13677#define mmDWB_OGAM_RAMA_REGION_32_33_BASE_IDX 2 13678#define mmDWB_OGAM_RAMB_START_CNTL_B 0x32ca 13679#define mmDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 13680#define mmDWB_OGAM_RAMB_START_CNTL_G 0x32cb 13681#define mmDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 13682#define mmDWB_OGAM_RAMB_START_CNTL_R 0x32cc 13683#define mmDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 13684#define mmDWB_OGAM_RAMB_START_BASE_CNTL_B 0x32cd 13685#define mmDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 13686#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_B 0x32ce 13687#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 13688#define mmDWB_OGAM_RAMB_START_BASE_CNTL_G 0x32cf 13689#define mmDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 13690#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_G 0x32d0 13691#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 13692#define mmDWB_OGAM_RAMB_START_BASE_CNTL_R 0x32d1 13693#define mmDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 13694#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_R 0x32d2 13695#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 13696#define mmDWB_OGAM_RAMB_END_CNTL1_B 0x32d3 13697#define mmDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 13698#define mmDWB_OGAM_RAMB_END_CNTL2_B 0x32d4 13699#define mmDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 13700#define mmDWB_OGAM_RAMB_END_CNTL1_G 0x32d5 13701#define mmDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 13702#define mmDWB_OGAM_RAMB_END_CNTL2_G 0x32d6 13703#define mmDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 13704#define mmDWB_OGAM_RAMB_END_CNTL1_R 0x32d7 13705#define mmDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 13706#define mmDWB_OGAM_RAMB_END_CNTL2_R 0x32d8 13707#define mmDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 13708#define mmDWB_OGAM_RAMB_OFFSET_B 0x32d9 13709#define mmDWB_OGAM_RAMB_OFFSET_B_BASE_IDX 2 13710#define mmDWB_OGAM_RAMB_OFFSET_G 0x32da 13711#define mmDWB_OGAM_RAMB_OFFSET_G_BASE_IDX 2 13712#define mmDWB_OGAM_RAMB_OFFSET_R 0x32db 13713#define mmDWB_OGAM_RAMB_OFFSET_R_BASE_IDX 2 13714#define mmDWB_OGAM_RAMB_REGION_0_1 0x32dc 13715#define mmDWB_OGAM_RAMB_REGION_0_1_BASE_IDX 2 13716#define mmDWB_OGAM_RAMB_REGION_2_3 0x32dd 13717#define mmDWB_OGAM_RAMB_REGION_2_3_BASE_IDX 2 13718#define mmDWB_OGAM_RAMB_REGION_4_5 0x32de 13719#define mmDWB_OGAM_RAMB_REGION_4_5_BASE_IDX 2 13720#define mmDWB_OGAM_RAMB_REGION_6_7 0x32df 13721#define mmDWB_OGAM_RAMB_REGION_6_7_BASE_IDX 2 13722#define mmDWB_OGAM_RAMB_REGION_8_9 0x32e0 13723#define mmDWB_OGAM_RAMB_REGION_8_9_BASE_IDX 2 13724#define mmDWB_OGAM_RAMB_REGION_10_11 0x32e1 13725#define mmDWB_OGAM_RAMB_REGION_10_11_BASE_IDX 2 13726#define mmDWB_OGAM_RAMB_REGION_12_13 0x32e2 13727#define mmDWB_OGAM_RAMB_REGION_12_13_BASE_IDX 2 13728#define mmDWB_OGAM_RAMB_REGION_14_15 0x32e3 13729#define mmDWB_OGAM_RAMB_REGION_14_15_BASE_IDX 2 13730#define mmDWB_OGAM_RAMB_REGION_16_17 0x32e4 13731#define mmDWB_OGAM_RAMB_REGION_16_17_BASE_IDX 2 13732#define mmDWB_OGAM_RAMB_REGION_18_19 0x32e5 13733#define mmDWB_OGAM_RAMB_REGION_18_19_BASE_IDX 2 13734#define mmDWB_OGAM_RAMB_REGION_20_21 0x32e6 13735#define mmDWB_OGAM_RAMB_REGION_20_21_BASE_IDX 2 13736#define mmDWB_OGAM_RAMB_REGION_22_23 0x32e7 13737#define mmDWB_OGAM_RAMB_REGION_22_23_BASE_IDX 2 13738#define mmDWB_OGAM_RAMB_REGION_24_25 0x32e8 13739#define mmDWB_OGAM_RAMB_REGION_24_25_BASE_IDX 2 13740#define mmDWB_OGAM_RAMB_REGION_26_27 0x32e9 13741#define mmDWB_OGAM_RAMB_REGION_26_27_BASE_IDX 2 13742#define mmDWB_OGAM_RAMB_REGION_28_29 0x32ea 13743#define mmDWB_OGAM_RAMB_REGION_28_29_BASE_IDX 2 13744#define mmDWB_OGAM_RAMB_REGION_30_31 0x32eb 13745#define mmDWB_OGAM_RAMB_REGION_30_31_BASE_IDX 2 13746#define mmDWB_OGAM_RAMB_REGION_32_33 0x32ec 13747#define mmDWB_OGAM_RAMB_REGION_32_33_BASE_IDX 2 13748 13749 13750// addressBlock: dce_dc_mpc_mpcc0_dispdec 13751// base address: 0x0 13752#define mmMPCC0_MPCC_TOP_SEL 0x0000 13753#define mmMPCC0_MPCC_TOP_SEL_BASE_IDX 3 13754#define mmMPCC0_MPCC_BOT_SEL 0x0001 13755#define mmMPCC0_MPCC_BOT_SEL_BASE_IDX 3 13756#define mmMPCC0_MPCC_OPP_ID 0x0002 13757#define mmMPCC0_MPCC_OPP_ID_BASE_IDX 3 13758#define mmMPCC0_MPCC_CONTROL 0x0003 13759#define mmMPCC0_MPCC_CONTROL_BASE_IDX 3 13760#define mmMPCC0_MPCC_SM_CONTROL 0x0004 13761#define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX 3 13762#define mmMPCC0_MPCC_UPDATE_LOCK_SEL 0x0005 13763#define mmMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 13764#define mmMPCC0_MPCC_TOP_GAIN 0x0006 13765#define mmMPCC0_MPCC_TOP_GAIN_BASE_IDX 3 13766#define mmMPCC0_MPCC_BOT_GAIN_INSIDE 0x0007 13767#define mmMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 13768#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE 0x0008 13769#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 13770#define mmMPCC0_MPCC_BG_R_CR 0x0009 13771#define mmMPCC0_MPCC_BG_R_CR_BASE_IDX 3 13772#define mmMPCC0_MPCC_BG_G_Y 0x000a 13773#define mmMPCC0_MPCC_BG_G_Y_BASE_IDX 3 13774#define mmMPCC0_MPCC_BG_B_CB 0x000b 13775#define mmMPCC0_MPCC_BG_B_CB_BASE_IDX 3 13776#define mmMPCC0_MPCC_MEM_PWR_CTRL 0x000c 13777#define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 3 13778#define mmMPCC0_MPCC_STATUS 0x000d 13779#define mmMPCC0_MPCC_STATUS_BASE_IDX 3 13780 13781 13782// addressBlock: dce_dc_mpc_mpcc1_dispdec 13783// base address: 0x80 13784#define mmMPCC1_MPCC_TOP_SEL 0x0020 13785#define mmMPCC1_MPCC_TOP_SEL_BASE_IDX 3 13786#define mmMPCC1_MPCC_BOT_SEL 0x0021 13787#define mmMPCC1_MPCC_BOT_SEL_BASE_IDX 3 13788#define mmMPCC1_MPCC_OPP_ID 0x0022 13789#define mmMPCC1_MPCC_OPP_ID_BASE_IDX 3 13790#define mmMPCC1_MPCC_CONTROL 0x0023 13791#define mmMPCC1_MPCC_CONTROL_BASE_IDX 3 13792#define mmMPCC1_MPCC_SM_CONTROL 0x0024 13793#define mmMPCC1_MPCC_SM_CONTROL_BASE_IDX 3 13794#define mmMPCC1_MPCC_UPDATE_LOCK_SEL 0x0025 13795#define mmMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 13796#define mmMPCC1_MPCC_TOP_GAIN 0x0026 13797#define mmMPCC1_MPCC_TOP_GAIN_BASE_IDX 3 13798#define mmMPCC1_MPCC_BOT_GAIN_INSIDE 0x0027 13799#define mmMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 13800#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE 0x0028 13801#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 13802#define mmMPCC1_MPCC_BG_R_CR 0x0029 13803#define mmMPCC1_MPCC_BG_R_CR_BASE_IDX 3 13804#define mmMPCC1_MPCC_BG_G_Y 0x002a 13805#define mmMPCC1_MPCC_BG_G_Y_BASE_IDX 3 13806#define mmMPCC1_MPCC_BG_B_CB 0x002b 13807#define mmMPCC1_MPCC_BG_B_CB_BASE_IDX 3 13808#define mmMPCC1_MPCC_MEM_PWR_CTRL 0x002c 13809#define mmMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 3 13810#define mmMPCC1_MPCC_STATUS 0x002d 13811#define mmMPCC1_MPCC_STATUS_BASE_IDX 3 13812 13813 13814// addressBlock: dce_dc_mpc_mpcc2_dispdec 13815// base address: 0x100 13816#define mmMPCC2_MPCC_TOP_SEL 0x0040 13817#define mmMPCC2_MPCC_TOP_SEL_BASE_IDX 3 13818#define mmMPCC2_MPCC_BOT_SEL 0x0041 13819#define mmMPCC2_MPCC_BOT_SEL_BASE_IDX 3 13820#define mmMPCC2_MPCC_OPP_ID 0x0042 13821#define mmMPCC2_MPCC_OPP_ID_BASE_IDX 3 13822#define mmMPCC2_MPCC_CONTROL 0x0043 13823#define mmMPCC2_MPCC_CONTROL_BASE_IDX 3 13824#define mmMPCC2_MPCC_SM_CONTROL 0x0044 13825#define mmMPCC2_MPCC_SM_CONTROL_BASE_IDX 3 13826#define mmMPCC2_MPCC_UPDATE_LOCK_SEL 0x0045 13827#define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 13828#define mmMPCC2_MPCC_TOP_GAIN 0x0046 13829#define mmMPCC2_MPCC_TOP_GAIN_BASE_IDX 3 13830#define mmMPCC2_MPCC_BOT_GAIN_INSIDE 0x0047 13831#define mmMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 13832#define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE 0x0048 13833#define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 13834#define mmMPCC2_MPCC_BG_R_CR 0x0049 13835#define mmMPCC2_MPCC_BG_R_CR_BASE_IDX 3 13836#define mmMPCC2_MPCC_BG_G_Y 0x004a 13837#define mmMPCC2_MPCC_BG_G_Y_BASE_IDX 3 13838#define mmMPCC2_MPCC_BG_B_CB 0x004b 13839#define mmMPCC2_MPCC_BG_B_CB_BASE_IDX 3 13840#define mmMPCC2_MPCC_MEM_PWR_CTRL 0x004c 13841#define mmMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX 3 13842#define mmMPCC2_MPCC_STATUS 0x004d 13843#define mmMPCC2_MPCC_STATUS_BASE_IDX 3 13844 13845 13846// addressBlock: dce_dc_mpc_mpcc3_dispdec 13847// base address: 0x180 13848#define mmMPCC3_MPCC_TOP_SEL 0x0060 13849#define mmMPCC3_MPCC_TOP_SEL_BASE_IDX 3 13850#define mmMPCC3_MPCC_BOT_SEL 0x0061 13851#define mmMPCC3_MPCC_BOT_SEL_BASE_IDX 3 13852#define mmMPCC3_MPCC_OPP_ID 0x0062 13853#define mmMPCC3_MPCC_OPP_ID_BASE_IDX 3 13854#define mmMPCC3_MPCC_CONTROL 0x0063 13855#define mmMPCC3_MPCC_CONTROL_BASE_IDX 3 13856#define mmMPCC3_MPCC_SM_CONTROL 0x0064 13857#define mmMPCC3_MPCC_SM_CONTROL_BASE_IDX 3 13858#define mmMPCC3_MPCC_UPDATE_LOCK_SEL 0x0065 13859#define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 13860#define mmMPCC3_MPCC_TOP_GAIN 0x0066 13861#define mmMPCC3_MPCC_TOP_GAIN_BASE_IDX 3 13862#define mmMPCC3_MPCC_BOT_GAIN_INSIDE 0x0067 13863#define mmMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 13864#define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE 0x0068 13865#define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 13866#define mmMPCC3_MPCC_BG_R_CR 0x0069 13867#define mmMPCC3_MPCC_BG_R_CR_BASE_IDX 3 13868#define mmMPCC3_MPCC_BG_G_Y 0x006a 13869#define mmMPCC3_MPCC_BG_G_Y_BASE_IDX 3 13870#define mmMPCC3_MPCC_BG_B_CB 0x006b 13871#define mmMPCC3_MPCC_BG_B_CB_BASE_IDX 3 13872#define mmMPCC3_MPCC_MEM_PWR_CTRL 0x006c 13873#define mmMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX 3 13874#define mmMPCC3_MPCC_STATUS 0x006d 13875#define mmMPCC3_MPCC_STATUS_BASE_IDX 3 13876 13877 13878// addressBlock: dce_dc_mpc_mpcc4_dispdec 13879// base address: 0x200 13880#define mmMPCC4_MPCC_TOP_SEL 0x0080 13881#define mmMPCC4_MPCC_TOP_SEL_BASE_IDX 3 13882#define mmMPCC4_MPCC_BOT_SEL 0x0081 13883#define mmMPCC4_MPCC_BOT_SEL_BASE_IDX 3 13884#define mmMPCC4_MPCC_OPP_ID 0x0082 13885#define mmMPCC4_MPCC_OPP_ID_BASE_IDX 3 13886#define mmMPCC4_MPCC_CONTROL 0x0083 13887#define mmMPCC4_MPCC_CONTROL_BASE_IDX 3 13888#define mmMPCC4_MPCC_SM_CONTROL 0x0084 13889#define mmMPCC4_MPCC_SM_CONTROL_BASE_IDX 3 13890#define mmMPCC4_MPCC_UPDATE_LOCK_SEL 0x0085 13891#define mmMPCC4_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 13892#define mmMPCC4_MPCC_TOP_GAIN 0x0086 13893#define mmMPCC4_MPCC_TOP_GAIN_BASE_IDX 3 13894#define mmMPCC4_MPCC_BOT_GAIN_INSIDE 0x0087 13895#define mmMPCC4_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 13896#define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE 0x0088 13897#define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 13898#define mmMPCC4_MPCC_BG_R_CR 0x0089 13899#define mmMPCC4_MPCC_BG_R_CR_BASE_IDX 3 13900#define mmMPCC4_MPCC_BG_G_Y 0x008a 13901#define mmMPCC4_MPCC_BG_G_Y_BASE_IDX 3 13902#define mmMPCC4_MPCC_BG_B_CB 0x008b 13903#define mmMPCC4_MPCC_BG_B_CB_BASE_IDX 3 13904#define mmMPCC4_MPCC_MEM_PWR_CTRL 0x008c 13905#define mmMPCC4_MPCC_MEM_PWR_CTRL_BASE_IDX 3 13906#define mmMPCC4_MPCC_STATUS 0x008d 13907#define mmMPCC4_MPCC_STATUS_BASE_IDX 3 13908 13909 13910// addressBlock: dce_dc_mpc_mpcc5_dispdec 13911// base address: 0x280 13912#define mmMPCC5_MPCC_TOP_SEL 0x00a0 13913#define mmMPCC5_MPCC_TOP_SEL_BASE_IDX 3 13914#define mmMPCC5_MPCC_BOT_SEL 0x00a1 13915#define mmMPCC5_MPCC_BOT_SEL_BASE_IDX 3 13916#define mmMPCC5_MPCC_OPP_ID 0x00a2 13917#define mmMPCC5_MPCC_OPP_ID_BASE_IDX 3 13918#define mmMPCC5_MPCC_CONTROL 0x00a3 13919#define mmMPCC5_MPCC_CONTROL_BASE_IDX 3 13920#define mmMPCC5_MPCC_SM_CONTROL 0x00a4 13921#define mmMPCC5_MPCC_SM_CONTROL_BASE_IDX 3 13922#define mmMPCC5_MPCC_UPDATE_LOCK_SEL 0x00a5 13923#define mmMPCC5_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 13924#define mmMPCC5_MPCC_TOP_GAIN 0x00a6 13925#define mmMPCC5_MPCC_TOP_GAIN_BASE_IDX 3 13926#define mmMPCC5_MPCC_BOT_GAIN_INSIDE 0x00a7 13927#define mmMPCC5_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 13928#define mmMPCC5_MPCC_BOT_GAIN_OUTSIDE 0x00a8 13929#define mmMPCC5_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 13930#define mmMPCC5_MPCC_BG_R_CR 0x00a9 13931#define mmMPCC5_MPCC_BG_R_CR_BASE_IDX 3 13932#define mmMPCC5_MPCC_BG_G_Y 0x00aa 13933#define mmMPCC5_MPCC_BG_G_Y_BASE_IDX 3 13934#define mmMPCC5_MPCC_BG_B_CB 0x00ab 13935#define mmMPCC5_MPCC_BG_B_CB_BASE_IDX 3 13936#define mmMPCC5_MPCC_MEM_PWR_CTRL 0x00ac 13937#define mmMPCC5_MPCC_MEM_PWR_CTRL_BASE_IDX 3 13938#define mmMPCC5_MPCC_STATUS 0x00ad 13939#define mmMPCC5_MPCC_STATUS_BASE_IDX 3 13940 13941 13942// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec 13943// base address: 0x0 13944#define mmMPCC_OGAM0_MPCC_OGAM_CONTROL 0x0100 13945#define mmMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX 3 13946#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0x0101 13947#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 13948#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0x0102 13949#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX 3 13950#define mmMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL 0x0103 13951#define mmMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 13952#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0x0104 13953#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 13954#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0x0105 13955#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 13956#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0x0106 13957#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 13958#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0107 13959#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 13960#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0108 13961#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 13962#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0109 13963#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 13964#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x010a 13965#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 13966#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x010b 13967#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 13968#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x010c 13969#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 13970#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0x010d 13971#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 13972#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0x010e 13973#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 13974#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0x010f 13975#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 13976#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0x0110 13977#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 13978#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0x0111 13979#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 13980#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0x0112 13981#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 13982#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B 0x0113 13983#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 13984#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G 0x0114 13985#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 13986#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R 0x0115 13987#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 13988#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0x0116 13989#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 13990#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0x0117 13991#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 13992#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0x0118 13993#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 13994#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0x0119 13995#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 13996#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0x011a 13997#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 13998#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0x011b 13999#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 14000#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0x011c
14001#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 14002#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0x011d 14003#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 14004#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0x011e 14005#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 14006#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0x011f 14007#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 14008#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0x0120 14009#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 14010#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0x0121 14011#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 14012#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0x0122 14013#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 14014#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0x0123 14015#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 14016#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0x0124 14017#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 14018#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0x0125 14019#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 14020#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0x0126 14021#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 14022#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0x0127 14023#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 14024#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0x0128 14025#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 14026#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0x0129 14027#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 14028#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x012a 14029#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 14030#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x012b 14031#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 14032#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x012c 14033#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 14034#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x012d 14035#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 14036#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x012e 14037#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 14038#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x012f 14039#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 14040#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0x0130 14041#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 14042#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0x0131 14043#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 14044#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0x0132 14045#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 14046#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0x0133 14047#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 14048#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0x0134 14049#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 14050#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0x0135 14051#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 14052#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B 0x0136 14053#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 14054#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G 0x0137 14055#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 14056#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R 0x0138 14057#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 14058#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0x0139 14059#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 14060#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0x013a 14061#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 14062#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0x013b 14063#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 14064#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0x013c 14065#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 14066#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0x013d 14067#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 14068#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0x013e 14069#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 14070#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0x013f 14071#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 14072#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0x0140 14073#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 14074#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0x0141 14075#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 14076#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0x0142 14077#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 14078#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0x0143 14079#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 14080#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0x0144 14081#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 14082#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0x0145 14083#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 14084#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0x0146 14085#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 14086#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0x0147 14087#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 14088#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0x0148 14089#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 14090#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0x0149 14091#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 14092#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT 0x014a 14093#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 14094#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE 0x014b 14095#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 14096#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A 0x014c 14097#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 14098#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A 0x014d 14099#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 14100#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A 0x014e 14101#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 14102#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A 0x014f 14103#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 14104#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A 0x0150 14105#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 14106#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A 0x0151 14107#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 14108#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B 0x0152 14109#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 14110#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B 0x0153 14111#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 14112#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B 0x0154 14113#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 14114#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B 0x0155 14115#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 14116#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B 0x0156 14117#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 14118#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B 0x0157 14119#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 14120 14121 14122// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec 14123// base address: 0x200 14124#define mmMPCC_OGAM1_MPCC_OGAM_CONTROL 0x0180 14125#define mmMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX 3 14126#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0x0181 14127#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 14128#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0x0182 14129#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX 3 14130#define mmMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL 0x0183 14131#define mmMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 14132#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0x0184 14133#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 14134#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0x0185 14135#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 14136#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0x0186 14137#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 14138#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0187 14139#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 14140#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0188 14141#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 14142#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0189 14143#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 14144#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x018a 14145#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 14146#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x018b 14147#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 14148#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x018c 14149#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 14150#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0x018d 14151#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 14152#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0x018e 14153#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 14154#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0x018f 14155#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 14156#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0x0190 14157#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 14158#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0x0191 14159#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 14160#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0x0192 14161#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 14162#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B 0x0193 14163#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 14164#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G 0x0194 14165#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 14166#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R 0x0195 14167#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 14168#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0x0196 14169#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 14170#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0x0197 14171#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 14172#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0x0198 14173#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 14174#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0x0199 14175#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 14176#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0x019a 14177#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 14178#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0x019b 14179#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 14180#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0x019c 14181#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 14182#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0x019d 14183#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 14184#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0x019e 14185#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 14186#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0x019f 14187#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 14188#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0x01a0 14189#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 14190#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0x01a1 14191#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 14192#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0x01a2 14193#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 14194#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0x01a3 14195#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 14196#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0x01a4 14197#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 14198#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0x01a5 14199#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 14200#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0x01a6 14201#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 14202#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0x01a7 14203#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 14204#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0x01a8 14205#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 14206#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0x01a9 14207#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 14208#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x01aa 14209#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 14210#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x01ab 14211#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 14212#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x01ac 14213#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 14214#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x01ad 14215#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 14216#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x01ae 14217#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 14218#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x01af 14219#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 14220#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0x01b0 14221#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 14222#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0x01b1 14223#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 14224#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0x01b2 14225#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 14226#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0x01b3 14227#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 14228#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0x01b4 14229#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 14230#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0x01b5 14231#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 14232#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B 0x01b6 14233#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 14234#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G 0x01b7 14235#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 14236#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R 0x01b8 14237#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 14238#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0x01b9 14239#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 14240#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0x01ba 14241#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 14242#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0x01bb 14243#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 14244#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0x01bc 14245#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 14246#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0x01bd 14247#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 14248#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0x01be 14249#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 14250#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0x01bf 14251#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 14252#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0x01c0 14253#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 14254#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0x01c1 14255#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 14256#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0x01c2 14257#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 14258#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0x01c3 14259#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 14260#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0x01c4 14261#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 14262#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0x01c5 14263#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 14264#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0x01c6 14265#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 14266#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0x01c7 14267#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 14268#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0x01c8 14269#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 14270#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0x01c9 14271#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 14272#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT 0x01ca 14273#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 14274#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE 0x01cb 14275#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 14276#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A 0x01cc 14277#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 14278#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A 0x01cd 14279#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 14280#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A 0x01ce 14281#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 14282#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A 0x01cf 14283#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 14284#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A 0x01d0 14285#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 14286#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A 0x01d1 14287#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 14288#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B 0x01d2 14289#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 14290#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B 0x01d3 14291#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 14292#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B 0x01d4 14293#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 14294#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B 0x01d5 14295#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 14296#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B 0x01d6 14297#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 14298#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B 0x01d7 14299#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 14300 14301 14302// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec 14303// base address: 0x400 14304#define mmMPCC_OGAM2_MPCC_OGAM_CONTROL 0x0200 14305#define mmMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX 3 14306#define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX 0x0201 14307#define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 14308#define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA 0x0202 14309#define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX 3 14310#define mmMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL 0x0203 14311#define mmMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 14312#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B 0x0204 14313#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 14314#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G 0x0205 14315#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 14316#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R 0x0206 14317#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 14318#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0207 14319#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 14320#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0208 14321#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 14322#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0209 14323#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 14324#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x020a 14325#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 14326#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x020b 14327#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 14328#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x020c 14329#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 14330#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B 0x020d 14331#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 14332#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B 0x020e 14333#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 14334#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G 0x020f 14335#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 14336#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G 0x0210 14337#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 14338#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R 0x0211 14339#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 14340#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R 0x0212 14341#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 14342#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B 0x0213 14343#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 14344#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G 0x0214 14345#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 14346#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R 0x0215 14347#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 14348#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 0x0216 14349#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 14350#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 0x0217 14351#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 14352#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 0x0218 14353#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 14354#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 0x0219 14355#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 14356#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 0x021a 14357#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 14358#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 0x021b 14359#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 14360#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 0x021c 14361#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 14362#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 0x021d 14363#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 14364#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 0x021e 14365#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 14366#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 0x021f 14367#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 14368#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 0x0220 14369#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 14370#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 0x0221 14371#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 14372#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 0x0222 14373#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 14374#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 0x0223 14375#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 14376#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 0x0224 14377#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 14378#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 0x0225 14379#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 14380#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 0x0226 14381#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 14382#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B 0x0227 14383#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 14384#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G 0x0228 14385#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 14386#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R 0x0229 14387#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 14388#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x022a 14389#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 14390#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x022b 14391#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 14392#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x022c 14393#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 14394#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x022d 14395#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 14396#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x022e 14397#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 14398#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x022f 14399#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 14400#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B 0x0230 14401#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 14402#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B 0x0231 14403#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 14404#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G 0x0232 14405#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 14406#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G 0x0233 14407#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 14408#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R 0x0234 14409#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 14410#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R 0x0235 14411#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 14412#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B 0x0236 14413#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 14414#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G 0x0237 14415#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 14416#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R 0x0238 14417#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 14418#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 0x0239 14419#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 14420#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 0x023a 14421#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 14422#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 0x023b 14423#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 14424#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 0x023c 14425#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 14426#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 0x023d 14427#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 14428#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 0x023e 14429#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 14430#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 0x023f 14431#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 14432#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 0x0240 14433#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 14434#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 0x0241 14435#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 14436#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 0x0242 14437#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 14438#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 0x0243 14439#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 14440#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 0x0244 14441#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 14442#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 0x0245 14443#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 14444#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 0x0246 14445#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 14446#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 0x0247 14447#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 14448#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 0x0248 14449#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 14450#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 0x0249 14451#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 14452#define mmMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT 0x024a 14453#define mmMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 14454#define mmMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE 0x024b 14455#define mmMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 14456#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A 0x024c 14457#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 14458#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A 0x024d 14459#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 14460#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A 0x024e 14461#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 14462#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A 0x024f 14463#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 14464#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A 0x0250 14465#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 14466#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A 0x0251 14467#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 14468#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B 0x0252 14469#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 14470#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B 0x0253 14471#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 14472#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B 0x0254 14473#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 14474#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B 0x0255 14475#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 14476#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B 0x0256 14477#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 14478#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B 0x0257 14479#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 14480 14481 14482// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec 14483// base address: 0x600 14484#define mmMPCC_OGAM3_MPCC_OGAM_CONTROL 0x0280 14485#define mmMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX 3 14486#define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX 0x0281 14487#define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 14488#define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA 0x0282 14489#define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX 3 14490#define mmMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL 0x0283 14491#define mmMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 14492#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B 0x0284 14493#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 14494#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G 0x0285 14495#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 14496#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R 0x0286 14497#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 14498#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0287 14499#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 14500#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0288 14501#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 14502#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0289 14503#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 14504#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x028a 14505#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 14506#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x028b 14507#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 14508#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x028c 14509#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 14510#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B 0x028d 14511#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 14512#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B 0x028e 14513#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 14514#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 0x028f 14515#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 14516#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G 0x0290 14517#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 14518#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 0x0291 14519#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 14520#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R 0x0292 14521#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 14522#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B 0x0293 14523#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 14524#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G 0x0294 14525#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 14526#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R 0x0295 14527#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 14528#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 0x0296 14529#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 14530#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 0x0297 14531#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 14532#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 0x0298 14533#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 14534#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 0x0299 14535#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 14536#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 0x029a 14537#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 14538#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 0x029b 14539#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 14540#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 0x029c 14541#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 14542#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 0x029d 14543#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 14544#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 0x029e 14545#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 14546#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 0x029f 14547#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 14548#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 0x02a0 14549#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 14550#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 0x02a1 14551#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 14552#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 0x02a2 14553#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 14554#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 0x02a3 14555#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 14556#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 0x02a4 14557#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 14558#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 0x02a5 14559#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 14560#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 0x02a6 14561#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 14562#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B 0x02a7 14563#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 14564#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G 0x02a8 14565#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 14566#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R 0x02a9 14567#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 14568#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x02aa 14569#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 14570#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x02ab 14571#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 14572#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x02ac 14573#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 14574#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x02ad 14575#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 14576#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x02ae 14577#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 14578#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x02af 14579#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 14580#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B 0x02b0 14581#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 14582#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B 0x02b1 14583#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 14584#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G 0x02b2 14585#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 14586#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G 0x02b3 14587#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 14588#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R 0x02b4 14589#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 14590#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R 0x02b5 14591#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 14592#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B 0x02b6 14593#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 14594#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G 0x02b7 14595#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 14596#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R 0x02b8 14597#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 14598#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 0x02b9 14599#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 14600#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 0x02ba 14601#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 14602#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 0x02bb 14603#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 14604#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 0x02bc 14605#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 14606#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 0x02bd 14607#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 14608#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 0x02be 14609#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 14610#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 0x02bf 14611#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 14612#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 0x02c0 14613#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 14614#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 0x02c1 14615#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 14616#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 0x02c2 14617#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 14618#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 0x02c3 14619#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 14620#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 0x02c4 14621#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 14622#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 0x02c5 14623#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 14624#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 0x02c6 14625#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 14626#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 0x02c7 14627#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 14628#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 0x02c8 14629#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 14630#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 0x02c9 14631#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 14632#define mmMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT 0x02ca 14633#define mmMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 14634#define mmMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE 0x02cb 14635#define mmMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 14636#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A 0x02cc 14637#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 14638#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A 0x02cd 14639#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 14640#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A 0x02ce 14641#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 14642#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A 0x02cf 14643#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 14644#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A 0x02d0 14645#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 14646#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A 0x02d1 14647#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 14648#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B 0x02d2 14649#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 14650#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B 0x02d3 14651#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 14652#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B 0x02d4 14653#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 14654#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B 0x02d5 14655#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 14656#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B 0x02d6 14657#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 14658#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B 0x02d7 14659#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 14660 14661 14662// addressBlock: dce_dc_mpc_mpcc_ogam4_dispdec 14663// base address: 0x800 14664#define mmMPCC_OGAM4_MPCC_OGAM_CONTROL 0x0300 14665#define mmMPCC_OGAM4_MPCC_OGAM_CONTROL_BASE_IDX 3 14666#define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX 0x0301 14667#define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 14668#define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA 0x0302 14669#define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA_BASE_IDX 3 14670#define mmMPCC_OGAM4_MPCC_OGAM_LUT_CONTROL 0x0303 14671#define mmMPCC_OGAM4_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 14672#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B 0x0304 14673#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 14674#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G 0x0305 14675#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 14676#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R 0x0306 14677#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 14678#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0307 14679#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 14680#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0308 14681#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 14682#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0309 14683#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 14684#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x030a 14685#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 14686#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x030b 14687#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 14688#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x030c 14689#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 14690#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B 0x030d 14691#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 14692#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B 0x030e 14693#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 14694#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G 0x030f 14695#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 14696#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G 0x0310 14697#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 14698#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R 0x0311 14699#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 14700#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R 0x0312 14701#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 14702#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_OFFSET_B 0x0313 14703#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 14704#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_OFFSET_G 0x0314 14705#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 14706#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_OFFSET_R 0x0315 14707#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 14708#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1 0x0316 14709#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 14710#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3 0x0317 14711#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 14712#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5 0x0318 14713#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 14714#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7 0x0319 14715#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 14716#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9 0x031a 14717#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 14718#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11 0x031b 14719#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 14720#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13 0x031c 14721#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 14722#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15 0x031d 14723#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 14724#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17 0x031e 14725#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 14726#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19 0x031f 14727#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 14728#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21 0x0320 14729#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 14730#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23 0x0321 14731#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 14732#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25 0x0322 14733#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 14734#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27 0x0323 14735#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 14736#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29 0x0324 14737#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 14738#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31 0x0325 14739#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 14740#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33 0x0326 14741#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 14742#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B 0x0327 14743#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 14744#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G 0x0328 14745#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 14746#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R 0x0329 14747#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 14748#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x032a 14749#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 14750#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x032b 14751#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 14752#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x032c 14753#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 14754#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x032d 14755#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 14756#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x032e 14757#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 14758#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x032f 14759#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 14760#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B 0x0330 14761#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 14762#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B 0x0331 14763#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 14764#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G 0x0332 14765#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 14766#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G 0x0333 14767#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 14768#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R 0x0334 14769#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 14770#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R 0x0335 14771#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 14772#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_OFFSET_B 0x0336 14773#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 14774#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_OFFSET_G 0x0337 14775#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 14776#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_OFFSET_R 0x0338 14777#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 14778#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1 0x0339 14779#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 14780#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3 0x033a 14781#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 14782#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5 0x033b 14783#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 14784#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7 0x033c 14785#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 14786#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9 0x033d 14787#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 14788#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11 0x033e 14789#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 14790#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13 0x033f 14791#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 14792#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15 0x0340 14793#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 14794#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17 0x0341 14795#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 14796#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19 0x0342 14797#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 14798#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21 0x0343 14799#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 14800#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23 0x0344 14801#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 14802#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25 0x0345 14803#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 14804#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27 0x0346 14805#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 14806#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29 0x0347 14807#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 14808#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31 0x0348 14809#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 14810#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33 0x0349 14811#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 14812#define mmMPCC_OGAM4_MPCC_GAMUT_REMAP_COEF_FORMAT 0x034a 14813#define mmMPCC_OGAM4_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 14814#define mmMPCC_OGAM4_MPCC_GAMUT_REMAP_MODE 0x034b 14815#define mmMPCC_OGAM4_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 14816#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C11_C12_A 0x034c 14817#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 14818#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C13_C14_A 0x034d 14819#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 14820#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C21_C22_A 0x034e 14821#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 14822#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C23_C24_A 0x034f 14823#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 14824#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C31_C32_A 0x0350 14825#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 14826#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C33_C34_A 0x0351 14827#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 14828#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C11_C12_B 0x0352 14829#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 14830#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C13_C14_B 0x0353 14831#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 14832#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C21_C22_B 0x0354 14833#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 14834#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C23_C24_B 0x0355 14835#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 14836#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C31_C32_B 0x0356 14837#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 14838#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C33_C34_B 0x0357 14839#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 14840 14841 14842// addressBlock: dce_dc_mpc_mpcc_ogam5_dispdec 14843// base address: 0xa00 14844#define mmMPCC_OGAM5_MPCC_OGAM_CONTROL 0x0380 14845#define mmMPCC_OGAM5_MPCC_OGAM_CONTROL_BASE_IDX 3 14846#define mmMPCC_OGAM5_MPCC_OGAM_LUT_INDEX 0x0381 14847#define mmMPCC_OGAM5_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 14848#define mmMPCC_OGAM5_MPCC_OGAM_LUT_DATA 0x0382 14849#define mmMPCC_OGAM5_MPCC_OGAM_LUT_DATA_BASE_IDX 3 14850#define mmMPCC_OGAM5_MPCC_OGAM_LUT_CONTROL 0x0383 14851#define mmMPCC_OGAM5_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 14852#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B 0x0384 14853#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 14854#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G 0x0385 14855#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 14856#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R 0x0386 14857#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 14858#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0387 14859#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 14860#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0388 14861#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 14862#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0389 14863#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 14864#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x038a 14865#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 14866#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x038b 14867#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 14868#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x038c 14869#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 14870#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B 0x038d 14871#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 14872#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B 0x038e 14873#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 14874#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G 0x038f 14875#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 14876#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G 0x0390 14877#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 14878#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R 0x0391 14879#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 14880#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R 0x0392 14881#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 14882#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_OFFSET_B 0x0393 14883#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 14884#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_OFFSET_G 0x0394 14885#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 14886#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_OFFSET_R 0x0395 14887#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 14888#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1 0x0396 14889#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 14890#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3 0x0397 14891#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 14892#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5 0x0398 14893#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 14894#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7 0x0399 14895#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 14896#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9 0x039a 14897#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 14898#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11 0x039b 14899#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 14900#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13 0x039c 14901#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 14902#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15 0x039d 14903#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 14904#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17 0x039e 14905#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 14906#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19 0x039f 14907#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 14908#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21 0x03a0 14909#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 14910#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23 0x03a1 14911#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 14912#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25 0x03a2 14913#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 14914#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27 0x03a3 14915#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 14916#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29 0x03a4 14917#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 14918#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31 0x03a5 14919#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 14920#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33 0x03a6 14921#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 14922#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B 0x03a7 14923#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 14924#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G 0x03a8 14925#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 14926#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R 0x03a9 14927#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 14928#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x03aa 14929#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 14930#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x03ab 14931#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 14932#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x03ac 14933#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 14934#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x03ad 14935#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 14936#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x03ae 14937#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 14938#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x03af 14939#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 14940#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B 0x03b0 14941#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 14942#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B 0x03b1 14943#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 14944#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G 0x03b2 14945#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 14946#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G 0x03b3 14947#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 14948#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R 0x03b4 14949#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 14950#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R 0x03b5 14951#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 14952#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_OFFSET_B 0x03b6 14953#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 14954#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_OFFSET_G 0x03b7 14955#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 14956#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_OFFSET_R 0x03b8 14957#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 14958#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1 0x03b9 14959#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 14960#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3 0x03ba 14961#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 14962#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5 0x03bb 14963#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 14964#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7 0x03bc 14965#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 14966#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9 0x03bd 14967#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 14968#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11 0x03be 14969#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 14970#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13 0x03bf 14971#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 14972#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15 0x03c0 14973#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 14974#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17 0x03c1 14975#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 14976#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19 0x03c2 14977#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 14978#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21 0x03c3 14979#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 14980#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23 0x03c4 14981#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 14982#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25 0x03c5 14983#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 14984#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27 0x03c6 14985#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 14986#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29 0x03c7 14987#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 14988#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31 0x03c8 14989#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 14990#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33 0x03c9 14991#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 14992#define mmMPCC_OGAM5_MPCC_GAMUT_REMAP_COEF_FORMAT 0x03ca 14993#define mmMPCC_OGAM5_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 14994#define mmMPCC_OGAM5_MPCC_GAMUT_REMAP_MODE 0x03cb 14995#define mmMPCC_OGAM5_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 14996#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C11_C12_A 0x03cc 14997#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 14998#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C13_C14_A 0x03cd 14999#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 15000#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C21_C22_A 0x03ce
15001#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 15002#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C23_C24_A 0x03cf 15003#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 15004#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C31_C32_A 0x03d0 15005#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 15006#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C33_C34_A 0x03d1 15007#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 15008#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C11_C12_B 0x03d2 15009#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 15010#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C13_C14_B 0x03d3 15011#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 15012#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C21_C22_B 0x03d4 15013#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 15014#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C23_C24_B 0x03d5 15015#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 15016#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C31_C32_B 0x03d6 15017#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 15018#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C33_C34_B 0x03d7 15019#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 15020 15021 15022// addressBlock: dce_dc_mpc_mpc_cfg_dispdec 15023// base address: 0x0 15024#define mmMPC_CLOCK_CONTROL 0x0500 15025#define mmMPC_CLOCK_CONTROL_BASE_IDX 3 15026#define mmMPC_SOFT_RESET 0x0501 15027#define mmMPC_SOFT_RESET_BASE_IDX 3 15028#define mmMPC_CRC_CTRL 0x0502 15029#define mmMPC_CRC_CTRL_BASE_IDX 3 15030#define mmMPC_CRC_SEL_CONTROL 0x0503 15031#define mmMPC_CRC_SEL_CONTROL_BASE_IDX 3 15032#define mmMPC_CRC_RESULT_AR 0x0504 15033#define mmMPC_CRC_RESULT_AR_BASE_IDX 3 15034#define mmMPC_CRC_RESULT_GB 0x0505 15035#define mmMPC_CRC_RESULT_GB_BASE_IDX 3 15036#define mmMPC_CRC_RESULT_C 0x0506 15037#define mmMPC_CRC_RESULT_C_BASE_IDX 3 15038#define mmMPC_PERFMON_EVENT_CTRL 0x0509 15039#define mmMPC_PERFMON_EVENT_CTRL_BASE_IDX 3 15040#define mmMPC_BYPASS_BG_AR 0x050a 15041#define mmMPC_BYPASS_BG_AR_BASE_IDX 3 15042#define mmMPC_BYPASS_BG_GB 0x050b 15043#define mmMPC_BYPASS_BG_GB_BASE_IDX 3 15044#define mmMPC_HOST_READ_CONTROL 0x050c 15045#define mmMPC_HOST_READ_CONTROL_BASE_IDX 3 15046#define mmMPC_DPP_PENDING_STATUS 0x050d 15047#define mmMPC_DPP_PENDING_STATUS_BASE_IDX 3 15048#define mmMPC_PENDING_STATUS_MISC 0x050e 15049#define mmMPC_PENDING_STATUS_MISC_BASE_IDX 3 15050#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0 0x050f 15051#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX 3 15052#define mmADR_CFG_VUPDATE_LOCK_SET0 0x0510 15053#define mmADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 3 15054#define mmADR_VUPDATE_LOCK_SET0 0x0511 15055#define mmADR_VUPDATE_LOCK_SET0_BASE_IDX 3 15056#define mmCFG_VUPDATE_LOCK_SET0 0x0512 15057#define mmCFG_VUPDATE_LOCK_SET0_BASE_IDX 3 15058#define mmCUR_VUPDATE_LOCK_SET0 0x0513 15059#define mmCUR_VUPDATE_LOCK_SET0_BASE_IDX 3 15060#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1 0x0514 15061#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX 3 15062#define mmADR_CFG_VUPDATE_LOCK_SET1 0x0515 15063#define mmADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 3 15064#define mmADR_VUPDATE_LOCK_SET1 0x0516 15065#define mmADR_VUPDATE_LOCK_SET1_BASE_IDX 3 15066#define mmCFG_VUPDATE_LOCK_SET1 0x0517 15067#define mmCFG_VUPDATE_LOCK_SET1_BASE_IDX 3 15068#define mmCUR_VUPDATE_LOCK_SET1 0x0518 15069#define mmCUR_VUPDATE_LOCK_SET1_BASE_IDX 3 15070#define mmADR_CFG_CUR_VUPDATE_LOCK_SET2 0x0519 15071#define mmADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX 3 15072#define mmADR_CFG_VUPDATE_LOCK_SET2 0x051a 15073#define mmADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 3 15074#define mmADR_VUPDATE_LOCK_SET2 0x051b 15075#define mmADR_VUPDATE_LOCK_SET2_BASE_IDX 3 15076#define mmCFG_VUPDATE_LOCK_SET2 0x051c 15077#define mmCFG_VUPDATE_LOCK_SET2_BASE_IDX 3 15078#define mmCUR_VUPDATE_LOCK_SET2 0x051d 15079#define mmCUR_VUPDATE_LOCK_SET2_BASE_IDX 3 15080#define mmADR_CFG_CUR_VUPDATE_LOCK_SET3 0x051e 15081#define mmADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX 3 15082#define mmADR_CFG_VUPDATE_LOCK_SET3 0x051f 15083#define mmADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 3 15084#define mmADR_VUPDATE_LOCK_SET3 0x0520 15085#define mmADR_VUPDATE_LOCK_SET3_BASE_IDX 3 15086#define mmCFG_VUPDATE_LOCK_SET3 0x0521 15087#define mmCFG_VUPDATE_LOCK_SET3_BASE_IDX 3 15088#define mmCUR_VUPDATE_LOCK_SET3 0x0522 15089#define mmCUR_VUPDATE_LOCK_SET3_BASE_IDX 3 15090#define mmADR_CFG_CUR_VUPDATE_LOCK_SET4 0x0523 15091#define mmADR_CFG_CUR_VUPDATE_LOCK_SET4_BASE_IDX 3 15092#define mmADR_CFG_VUPDATE_LOCK_SET4 0x0524 15093#define mmADR_CFG_VUPDATE_LOCK_SET4_BASE_IDX 3 15094#define mmADR_VUPDATE_LOCK_SET4 0x0525 15095#define mmADR_VUPDATE_LOCK_SET4_BASE_IDX 3 15096#define mmCFG_VUPDATE_LOCK_SET4 0x0526 15097#define mmCFG_VUPDATE_LOCK_SET4_BASE_IDX 3 15098#define mmCUR_VUPDATE_LOCK_SET4 0x0527 15099#define mmCUR_VUPDATE_LOCK_SET4_BASE_IDX 3 15100#define mmADR_CFG_CUR_VUPDATE_LOCK_SET5 0x0528 15101#define mmADR_CFG_CUR_VUPDATE_LOCK_SET5_BASE_IDX 3 15102#define mmADR_CFG_VUPDATE_LOCK_SET5 0x0529 15103#define mmADR_CFG_VUPDATE_LOCK_SET5_BASE_IDX 3 15104#define mmADR_VUPDATE_LOCK_SET5 0x052a 15105#define mmADR_VUPDATE_LOCK_SET5_BASE_IDX 3 15106#define mmCFG_VUPDATE_LOCK_SET5 0x052b 15107#define mmCFG_VUPDATE_LOCK_SET5_BASE_IDX 3 15108#define mmCUR_VUPDATE_LOCK_SET5 0x052c 15109#define mmCUR_VUPDATE_LOCK_SET5_BASE_IDX 3 15110#define mmMPC_DWB0_MUX 0x055c 15111#define mmMPC_DWB0_MUX_BASE_IDX 3 15112 15113 15114// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec 15115// base address: 0x0 15116#define mmMPC_OUT0_MUX 0x0580 15117#define mmMPC_OUT0_MUX_BASE_IDX 3 15118#define mmMPC_OUT0_DENORM_CONTROL 0x0581 15119#define mmMPC_OUT0_DENORM_CONTROL_BASE_IDX 3 15120#define mmMPC_OUT0_DENORM_CLAMP_G_Y 0x0582 15121#define mmMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 3 15122#define mmMPC_OUT0_DENORM_CLAMP_B_CB 0x0583 15123#define mmMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 3 15124#define mmMPC_OUT1_MUX 0x0584 15125#define mmMPC_OUT1_MUX_BASE_IDX 3 15126#define mmMPC_OUT1_DENORM_CONTROL 0x0585 15127#define mmMPC_OUT1_DENORM_CONTROL_BASE_IDX 3 15128#define mmMPC_OUT1_DENORM_CLAMP_G_Y 0x0586 15129#define mmMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX 3 15130#define mmMPC_OUT1_DENORM_CLAMP_B_CB 0x0587 15131#define mmMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX 3 15132#define mmMPC_OUT2_MUX 0x0588 15133#define mmMPC_OUT2_MUX_BASE_IDX 3 15134#define mmMPC_OUT2_DENORM_CONTROL 0x0589 15135#define mmMPC_OUT2_DENORM_CONTROL_BASE_IDX 3 15136#define mmMPC_OUT2_DENORM_CLAMP_G_Y 0x058a 15137#define mmMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX 3 15138#define mmMPC_OUT2_DENORM_CLAMP_B_CB 0x058b 15139#define mmMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX 3 15140#define mmMPC_OUT3_MUX 0x058c 15141#define mmMPC_OUT3_MUX_BASE_IDX 3 15142#define mmMPC_OUT3_DENORM_CONTROL 0x058d 15143#define mmMPC_OUT3_DENORM_CONTROL_BASE_IDX 3 15144#define mmMPC_OUT3_DENORM_CLAMP_G_Y 0x058e 15145#define mmMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX 3 15146#define mmMPC_OUT3_DENORM_CLAMP_B_CB 0x058f 15147#define mmMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX 3 15148#define mmMPC_OUT4_MUX 0x0590 15149#define mmMPC_OUT4_MUX_BASE_IDX 3 15150#define mmMPC_OUT4_DENORM_CONTROL 0x0591 15151#define mmMPC_OUT4_DENORM_CONTROL_BASE_IDX 3 15152#define mmMPC_OUT4_DENORM_CLAMP_G_Y 0x0592 15153#define mmMPC_OUT4_DENORM_CLAMP_G_Y_BASE_IDX 3 15154#define mmMPC_OUT4_DENORM_CLAMP_B_CB 0x0593 15155#define mmMPC_OUT4_DENORM_CLAMP_B_CB_BASE_IDX 3 15156#define mmMPC_OUT5_MUX 0x0594 15157#define mmMPC_OUT5_MUX_BASE_IDX 3 15158#define mmMPC_OUT5_DENORM_CONTROL 0x0595 15159#define mmMPC_OUT5_DENORM_CONTROL_BASE_IDX 3 15160#define mmMPC_OUT5_DENORM_CLAMP_G_Y 0x0596 15161#define mmMPC_OUT5_DENORM_CLAMP_G_Y_BASE_IDX 3 15162#define mmMPC_OUT5_DENORM_CLAMP_B_CB 0x0597 15163#define mmMPC_OUT5_DENORM_CLAMP_B_CB_BASE_IDX 3 15164#define mmMPC_OUT_CSC_COEF_FORMAT 0x0598 15165#define mmMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 3 15166#define mmMPC_OUT0_CSC_MODE 0x0599 15167#define mmMPC_OUT0_CSC_MODE_BASE_IDX 3 15168#define mmMPC_OUT0_CSC_C11_C12_A 0x059a 15169#define mmMPC_OUT0_CSC_C11_C12_A_BASE_IDX 3 15170#define mmMPC_OUT0_CSC_C13_C14_A 0x059b 15171#define mmMPC_OUT0_CSC_C13_C14_A_BASE_IDX 3 15172#define mmMPC_OUT0_CSC_C21_C22_A 0x059c 15173#define mmMPC_OUT0_CSC_C21_C22_A_BASE_IDX 3 15174#define mmMPC_OUT0_CSC_C23_C24_A 0x059d 15175#define mmMPC_OUT0_CSC_C23_C24_A_BASE_IDX 3 15176#define mmMPC_OUT0_CSC_C31_C32_A 0x059e 15177#define mmMPC_OUT0_CSC_C31_C32_A_BASE_IDX 3 15178#define mmMPC_OUT0_CSC_C33_C34_A 0x059f 15179#define mmMPC_OUT0_CSC_C33_C34_A_BASE_IDX 3 15180#define mmMPC_OUT0_CSC_C11_C12_B 0x05a0 15181#define mmMPC_OUT0_CSC_C11_C12_B_BASE_IDX 3 15182#define mmMPC_OUT0_CSC_C13_C14_B 0x05a1 15183#define mmMPC_OUT0_CSC_C13_C14_B_BASE_IDX 3 15184#define mmMPC_OUT0_CSC_C21_C22_B 0x05a2 15185#define mmMPC_OUT0_CSC_C21_C22_B_BASE_IDX 3 15186#define mmMPC_OUT0_CSC_C23_C24_B 0x05a3 15187#define mmMPC_OUT0_CSC_C23_C24_B_BASE_IDX 3 15188#define mmMPC_OUT0_CSC_C31_C32_B 0x05a4 15189#define mmMPC_OUT0_CSC_C31_C32_B_BASE_IDX 3 15190#define mmMPC_OUT0_CSC_C33_C34_B 0x05a5 15191#define mmMPC_OUT0_CSC_C33_C34_B_BASE_IDX 3 15192#define mmMPC_OUT1_CSC_MODE 0x05a6 15193#define mmMPC_OUT1_CSC_MODE_BASE_IDX 3 15194#define mmMPC_OUT1_CSC_C11_C12_A 0x05a7 15195#define mmMPC_OUT1_CSC_C11_C12_A_BASE_IDX 3 15196#define mmMPC_OUT1_CSC_C13_C14_A 0x05a8 15197#define mmMPC_OUT1_CSC_C13_C14_A_BASE_IDX 3 15198#define mmMPC_OUT1_CSC_C21_C22_A 0x05a9 15199#define mmMPC_OUT1_CSC_C21_C22_A_BASE_IDX 3 15200#define mmMPC_OUT1_CSC_C23_C24_A 0x05aa 15201#define mmMPC_OUT1_CSC_C23_C24_A_BASE_IDX 3 15202#define mmMPC_OUT1_CSC_C31_C32_A 0x05ab 15203#define mmMPC_OUT1_CSC_C31_C32_A_BASE_IDX 3 15204#define mmMPC_OUT1_CSC_C33_C34_A 0x05ac 15205#define mmMPC_OUT1_CSC_C33_C34_A_BASE_IDX 3 15206#define mmMPC_OUT1_CSC_C11_C12_B 0x05ad 15207#define mmMPC_OUT1_CSC_C11_C12_B_BASE_IDX 3 15208#define mmMPC_OUT1_CSC_C13_C14_B 0x05ae 15209#define mmMPC_OUT1_CSC_C13_C14_B_BASE_IDX 3 15210#define mmMPC_OUT1_CSC_C21_C22_B 0x05af 15211#define mmMPC_OUT1_CSC_C21_C22_B_BASE_IDX 3 15212#define mmMPC_OUT1_CSC_C23_C24_B 0x05b0 15213#define mmMPC_OUT1_CSC_C23_C24_B_BASE_IDX 3 15214#define mmMPC_OUT1_CSC_C31_C32_B 0x05b1 15215#define mmMPC_OUT1_CSC_C31_C32_B_BASE_IDX 3 15216#define mmMPC_OUT1_CSC_C33_C34_B 0x05b2 15217#define mmMPC_OUT1_CSC_C33_C34_B_BASE_IDX 3 15218#define mmMPC_OUT2_CSC_MODE 0x05b3 15219#define mmMPC_OUT2_CSC_MODE_BASE_IDX 3 15220#define mmMPC_OUT2_CSC_C11_C12_A 0x05b4 15221#define mmMPC_OUT2_CSC_C11_C12_A_BASE_IDX 3 15222#define mmMPC_OUT2_CSC_C13_C14_A 0x05b5 15223#define mmMPC_OUT2_CSC_C13_C14_A_BASE_IDX 3 15224#define mmMPC_OUT2_CSC_C21_C22_A 0x05b6 15225#define mmMPC_OUT2_CSC_C21_C22_A_BASE_IDX 3 15226#define mmMPC_OUT2_CSC_C23_C24_A 0x05b7 15227#define mmMPC_OUT2_CSC_C23_C24_A_BASE_IDX 3 15228#define mmMPC_OUT2_CSC_C31_C32_A 0x05b8 15229#define mmMPC_OUT2_CSC_C31_C32_A_BASE_IDX 3 15230#define mmMPC_OUT2_CSC_C33_C34_A 0x05b9 15231#define mmMPC_OUT2_CSC_C33_C34_A_BASE_IDX 3 15232#define mmMPC_OUT2_CSC_C11_C12_B 0x05ba 15233#define mmMPC_OUT2_CSC_C11_C12_B_BASE_IDX 3 15234#define mmMPC_OUT2_CSC_C13_C14_B 0x05bb 15235#define mmMPC_OUT2_CSC_C13_C14_B_BASE_IDX 3 15236#define mmMPC_OUT2_CSC_C21_C22_B 0x05bc 15237#define mmMPC_OUT2_CSC_C21_C22_B_BASE_IDX 3 15238#define mmMPC_OUT2_CSC_C23_C24_B 0x05bd 15239#define mmMPC_OUT2_CSC_C23_C24_B_BASE_IDX 3 15240#define mmMPC_OUT2_CSC_C31_C32_B 0x05be 15241#define mmMPC_OUT2_CSC_C31_C32_B_BASE_IDX 3 15242#define mmMPC_OUT2_CSC_C33_C34_B 0x05bf 15243#define mmMPC_OUT2_CSC_C33_C34_B_BASE_IDX 3 15244#define mmMPC_OUT3_CSC_MODE 0x05c0 15245#define mmMPC_OUT3_CSC_MODE_BASE_IDX 3 15246#define mmMPC_OUT3_CSC_C11_C12_A 0x05c1 15247#define mmMPC_OUT3_CSC_C11_C12_A_BASE_IDX 3 15248#define mmMPC_OUT3_CSC_C13_C14_A 0x05c2 15249#define mmMPC_OUT3_CSC_C13_C14_A_BASE_IDX 3 15250#define mmMPC_OUT3_CSC_C21_C22_A 0x05c3 15251#define mmMPC_OUT3_CSC_C21_C22_A_BASE_IDX 3 15252#define mmMPC_OUT3_CSC_C23_C24_A 0x05c4 15253#define mmMPC_OUT3_CSC_C23_C24_A_BASE_IDX 3 15254#define mmMPC_OUT3_CSC_C31_C32_A 0x05c5 15255#define mmMPC_OUT3_CSC_C31_C32_A_BASE_IDX 3 15256#define mmMPC_OUT3_CSC_C33_C34_A 0x05c6 15257#define mmMPC_OUT3_CSC_C33_C34_A_BASE_IDX 3 15258#define mmMPC_OUT3_CSC_C11_C12_B 0x05c7 15259#define mmMPC_OUT3_CSC_C11_C12_B_BASE_IDX 3 15260#define mmMPC_OUT3_CSC_C13_C14_B 0x05c8 15261#define mmMPC_OUT3_CSC_C13_C14_B_BASE_IDX 3 15262#define mmMPC_OUT3_CSC_C21_C22_B 0x05c9 15263#define mmMPC_OUT3_CSC_C21_C22_B_BASE_IDX 3 15264#define mmMPC_OUT3_CSC_C23_C24_B 0x05ca 15265#define mmMPC_OUT3_CSC_C23_C24_B_BASE_IDX 3 15266#define mmMPC_OUT3_CSC_C31_C32_B 0x05cb 15267#define mmMPC_OUT3_CSC_C31_C32_B_BASE_IDX 3 15268#define mmMPC_OUT3_CSC_C33_C34_B 0x05cc 15269#define mmMPC_OUT3_CSC_C33_C34_B_BASE_IDX 3 15270#define mmMPC_OUT4_CSC_MODE 0x05cd 15271#define mmMPC_OUT4_CSC_MODE_BASE_IDX 3 15272#define mmMPC_OUT4_CSC_C11_C12_A 0x05ce 15273#define mmMPC_OUT4_CSC_C11_C12_A_BASE_IDX 3 15274#define mmMPC_OUT4_CSC_C13_C14_A 0x05cf 15275#define mmMPC_OUT4_CSC_C13_C14_A_BASE_IDX 3 15276#define mmMPC_OUT4_CSC_C21_C22_A 0x05d0 15277#define mmMPC_OUT4_CSC_C21_C22_A_BASE_IDX 3 15278#define mmMPC_OUT4_CSC_C23_C24_A 0x05d1 15279#define mmMPC_OUT4_CSC_C23_C24_A_BASE_IDX 3 15280#define mmMPC_OUT4_CSC_C31_C32_A 0x05d2 15281#define mmMPC_OUT4_CSC_C31_C32_A_BASE_IDX 3 15282#define mmMPC_OUT4_CSC_C33_C34_A 0x05d3 15283#define mmMPC_OUT4_CSC_C33_C34_A_BASE_IDX 3 15284#define mmMPC_OUT4_CSC_C11_C12_B 0x05d4 15285#define mmMPC_OUT4_CSC_C11_C12_B_BASE_IDX 3 15286#define mmMPC_OUT4_CSC_C13_C14_B 0x05d5 15287#define mmMPC_OUT4_CSC_C13_C14_B_BASE_IDX 3 15288#define mmMPC_OUT4_CSC_C21_C22_B 0x05d6 15289#define mmMPC_OUT4_CSC_C21_C22_B_BASE_IDX 3 15290#define mmMPC_OUT4_CSC_C23_C24_B 0x05d7 15291#define mmMPC_OUT4_CSC_C23_C24_B_BASE_IDX 3 15292#define mmMPC_OUT4_CSC_C31_C32_B 0x05d8 15293#define mmMPC_OUT4_CSC_C31_C32_B_BASE_IDX 3 15294#define mmMPC_OUT4_CSC_C33_C34_B 0x05d9 15295#define mmMPC_OUT4_CSC_C33_C34_B_BASE_IDX 3 15296#define mmMPC_OUT5_CSC_MODE 0x05da 15297#define mmMPC_OUT5_CSC_MODE_BASE_IDX 3 15298#define mmMPC_OUT5_CSC_C11_C12_A 0x05db 15299#define mmMPC_OUT5_CSC_C11_C12_A_BASE_IDX 3 15300#define mmMPC_OUT5_CSC_C13_C14_A 0x05dc 15301#define mmMPC_OUT5_CSC_C13_C14_A_BASE_IDX 3 15302#define mmMPC_OUT5_CSC_C21_C22_A 0x05dd 15303#define mmMPC_OUT5_CSC_C21_C22_A_BASE_IDX 3 15304#define mmMPC_OUT5_CSC_C23_C24_A 0x05de 15305#define mmMPC_OUT5_CSC_C23_C24_A_BASE_IDX 3 15306#define mmMPC_OUT5_CSC_C31_C32_A 0x05df 15307#define mmMPC_OUT5_CSC_C31_C32_A_BASE_IDX 3 15308#define mmMPC_OUT5_CSC_C33_C34_A 0x05e0 15309#define mmMPC_OUT5_CSC_C33_C34_A_BASE_IDX 3 15310#define mmMPC_OUT5_CSC_C11_C12_B 0x05e1 15311#define mmMPC_OUT5_CSC_C11_C12_B_BASE_IDX 3 15312#define mmMPC_OUT5_CSC_C13_C14_B 0x05e2 15313#define mmMPC_OUT5_CSC_C13_C14_B_BASE_IDX 3 15314#define mmMPC_OUT5_CSC_C21_C22_B 0x05e3 15315#define mmMPC_OUT5_CSC_C21_C22_B_BASE_IDX 3 15316#define mmMPC_OUT5_CSC_C23_C24_B 0x05e4 15317#define mmMPC_OUT5_CSC_C23_C24_B_BASE_IDX 3 15318#define mmMPC_OUT5_CSC_C31_C32_B 0x05e5 15319#define mmMPC_OUT5_CSC_C31_C32_B_BASE_IDX 3 15320#define mmMPC_OUT5_CSC_C33_C34_B 0x05e6 15321#define mmMPC_OUT5_CSC_C33_C34_B_BASE_IDX 3 15322 15323 15324// addressBlock: dce_dc_mpc_mpc_rmu_dispdec 15325// base address: 0x0 15326#define mmMPC_RMU_CONTROL 0x0680 15327#define mmMPC_RMU_CONTROL_BASE_IDX 3 15328#define mmMPC_RMU_MEM_PWR_CTRL 0x0681 15329#define mmMPC_RMU_MEM_PWR_CTRL_BASE_IDX 3 15330#define mmMPC_RMU0_SHAPER_CONTROL 0x0682 15331#define mmMPC_RMU0_SHAPER_CONTROL_BASE_IDX 3 15332#define mmMPC_RMU0_SHAPER_OFFSET_R 0x0683 15333#define mmMPC_RMU0_SHAPER_OFFSET_R_BASE_IDX 3 15334#define mmMPC_RMU0_SHAPER_OFFSET_G 0x0684 15335#define mmMPC_RMU0_SHAPER_OFFSET_G_BASE_IDX 3 15336#define mmMPC_RMU0_SHAPER_OFFSET_B 0x0685 15337#define mmMPC_RMU0_SHAPER_OFFSET_B_BASE_IDX 3 15338#define mmMPC_RMU0_SHAPER_SCALE_R 0x0686 15339#define mmMPC_RMU0_SHAPER_SCALE_R_BASE_IDX 3 15340#define mmMPC_RMU0_SHAPER_SCALE_G_B 0x0687 15341#define mmMPC_RMU0_SHAPER_SCALE_G_B_BASE_IDX 3 15342#define mmMPC_RMU0_SHAPER_LUT_INDEX 0x0688 15343#define mmMPC_RMU0_SHAPER_LUT_INDEX_BASE_IDX 3 15344#define mmMPC_RMU0_SHAPER_LUT_DATA 0x0689 15345#define mmMPC_RMU0_SHAPER_LUT_DATA_BASE_IDX 3 15346#define mmMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK 0x068a 15347#define mmMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 15348#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_B 0x068b 15349#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 15350#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_G 0x068c 15351#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 15352#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_R 0x068d 15353#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 15354#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_B 0x068e 15355#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 15356#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_G 0x068f 15357#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 15358#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_R 0x0690 15359#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 15360#define mmMPC_RMU0_SHAPER_RAMA_REGION_0_1 0x0691 15361#define mmMPC_RMU0_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 15362#define mmMPC_RMU0_SHAPER_RAMA_REGION_2_3 0x0692 15363#define mmMPC_RMU0_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 15364#define mmMPC_RMU0_SHAPER_RAMA_REGION_4_5 0x0693 15365#define mmMPC_RMU0_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 15366#define mmMPC_RMU0_SHAPER_RAMA_REGION_6_7 0x0694 15367#define mmMPC_RMU0_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 15368#define mmMPC_RMU0_SHAPER_RAMA_REGION_8_9 0x0695 15369#define mmMPC_RMU0_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 15370#define mmMPC_RMU0_SHAPER_RAMA_REGION_10_11 0x0696 15371#define mmMPC_RMU0_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 15372#define mmMPC_RMU0_SHAPER_RAMA_REGION_12_13 0x0697 15373#define mmMPC_RMU0_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 15374#define mmMPC_RMU0_SHAPER_RAMA_REGION_14_15 0x0698 15375#define mmMPC_RMU0_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 15376#define mmMPC_RMU0_SHAPER_RAMA_REGION_16_17 0x0699 15377#define mmMPC_RMU0_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 15378#define mmMPC_RMU0_SHAPER_RAMA_REGION_18_19 0x069a 15379#define mmMPC_RMU0_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 15380#define mmMPC_RMU0_SHAPER_RAMA_REGION_20_21 0x069b 15381#define mmMPC_RMU0_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 15382#define mmMPC_RMU0_SHAPER_RAMA_REGION_22_23 0x069c 15383#define mmMPC_RMU0_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 15384#define mmMPC_RMU0_SHAPER_RAMA_REGION_24_25 0x069d 15385#define mmMPC_RMU0_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 15386#define mmMPC_RMU0_SHAPER_RAMA_REGION_26_27 0x069e 15387#define mmMPC_RMU0_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 15388#define mmMPC_RMU0_SHAPER_RAMA_REGION_28_29 0x069f 15389#define mmMPC_RMU0_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 15390#define mmMPC_RMU0_SHAPER_RAMA_REGION_30_31 0x06a0 15391#define mmMPC_RMU0_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 15392#define mmMPC_RMU0_SHAPER_RAMA_REGION_32_33 0x06a1 15393#define mmMPC_RMU0_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 15394#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_B 0x06a2 15395#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 15396#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_G 0x06a3 15397#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 15398#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_R 0x06a4 15399#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 15400#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_B 0x06a5 15401#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 15402#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_G 0x06a6 15403#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 15404#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_R 0x06a7 15405#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 15406#define mmMPC_RMU0_SHAPER_RAMB_REGION_0_1 0x06a8 15407#define mmMPC_RMU0_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 15408#define mmMPC_RMU0_SHAPER_RAMB_REGION_2_3 0x06a9 15409#define mmMPC_RMU0_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 15410#define mmMPC_RMU0_SHAPER_RAMB_REGION_4_5 0x06aa 15411#define mmMPC_RMU0_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 15412#define mmMPC_RMU0_SHAPER_RAMB_REGION_6_7 0x06ab 15413#define mmMPC_RMU0_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 15414#define mmMPC_RMU0_SHAPER_RAMB_REGION_8_9 0x06ac 15415#define mmMPC_RMU0_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 15416#define mmMPC_RMU0_SHAPER_RAMB_REGION_10_11 0x06ad 15417#define mmMPC_RMU0_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 15418#define mmMPC_RMU0_SHAPER_RAMB_REGION_12_13 0x06ae 15419#define mmMPC_RMU0_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 15420#define mmMPC_RMU0_SHAPER_RAMB_REGION_14_15 0x06af 15421#define mmMPC_RMU0_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 15422#define mmMPC_RMU0_SHAPER_RAMB_REGION_16_17 0x06b0 15423#define mmMPC_RMU0_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 15424#define mmMPC_RMU0_SHAPER_RAMB_REGION_18_19 0x06b1 15425#define mmMPC_RMU0_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 15426#define mmMPC_RMU0_SHAPER_RAMB_REGION_20_21 0x06b2 15427#define mmMPC_RMU0_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 15428#define mmMPC_RMU0_SHAPER_RAMB_REGION_22_23 0x06b3 15429#define mmMPC_RMU0_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 15430#define mmMPC_RMU0_SHAPER_RAMB_REGION_24_25 0x06b4 15431#define mmMPC_RMU0_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 15432#define mmMPC_RMU0_SHAPER_RAMB_REGION_26_27 0x06b5 15433#define mmMPC_RMU0_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 15434#define mmMPC_RMU0_SHAPER_RAMB_REGION_28_29 0x06b6 15435#define mmMPC_RMU0_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 15436#define mmMPC_RMU0_SHAPER_RAMB_REGION_30_31 0x06b7 15437#define mmMPC_RMU0_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 15438#define mmMPC_RMU0_SHAPER_RAMB_REGION_32_33 0x06b8 15439#define mmMPC_RMU0_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 15440#define mmMPC_RMU0_3DLUT_MODE 0x06b9 15441#define mmMPC_RMU0_3DLUT_MODE_BASE_IDX 3 15442#define mmMPC_RMU0_3DLUT_INDEX 0x06ba 15443#define mmMPC_RMU0_3DLUT_INDEX_BASE_IDX 3 15444#define mmMPC_RMU0_3DLUT_DATA 0x06bb 15445#define mmMPC_RMU0_3DLUT_DATA_BASE_IDX 3 15446#define mmMPC_RMU0_3DLUT_DATA_30BIT 0x06bc 15447#define mmMPC_RMU0_3DLUT_DATA_30BIT_BASE_IDX 3 15448#define mmMPC_RMU0_3DLUT_READ_WRITE_CONTROL 0x06bd 15449#define mmMPC_RMU0_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 15450#define mmMPC_RMU0_3DLUT_OUT_NORM_FACTOR 0x06be 15451#define mmMPC_RMU0_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 15452#define mmMPC_RMU0_3DLUT_OUT_OFFSET_R 0x06bf 15453#define mmMPC_RMU0_3DLUT_OUT_OFFSET_R_BASE_IDX 3 15454#define mmMPC_RMU0_3DLUT_OUT_OFFSET_G 0x06c0 15455#define mmMPC_RMU0_3DLUT_OUT_OFFSET_G_BASE_IDX 3 15456#define mmMPC_RMU0_3DLUT_OUT_OFFSET_B 0x06c1 15457#define mmMPC_RMU0_3DLUT_OUT_OFFSET_B_BASE_IDX 3 15458#define mmMPC_RMU1_SHAPER_CONTROL 0x06c2 15459#define mmMPC_RMU1_SHAPER_CONTROL_BASE_IDX 3 15460#define mmMPC_RMU1_SHAPER_OFFSET_R 0x06c3 15461#define mmMPC_RMU1_SHAPER_OFFSET_R_BASE_IDX 3 15462#define mmMPC_RMU1_SHAPER_OFFSET_G 0x06c4 15463#define mmMPC_RMU1_SHAPER_OFFSET_G_BASE_IDX 3 15464#define mmMPC_RMU1_SHAPER_OFFSET_B 0x06c5 15465#define mmMPC_RMU1_SHAPER_OFFSET_B_BASE_IDX 3 15466#define mmMPC_RMU1_SHAPER_SCALE_R 0x06c6 15467#define mmMPC_RMU1_SHAPER_SCALE_R_BASE_IDX 3 15468#define mmMPC_RMU1_SHAPER_SCALE_G_B 0x06c7 15469#define mmMPC_RMU1_SHAPER_SCALE_G_B_BASE_IDX 3 15470#define mmMPC_RMU1_SHAPER_LUT_INDEX 0x06c8 15471#define mmMPC_RMU1_SHAPER_LUT_INDEX_BASE_IDX 3 15472#define mmMPC_RMU1_SHAPER_LUT_DATA 0x06c9 15473#define mmMPC_RMU1_SHAPER_LUT_DATA_BASE_IDX 3 15474#define mmMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK 0x06ca 15475#define mmMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 15476#define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_B 0x06cb 15477#define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 15478#define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_G 0x06cc 15479#define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 15480#define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_R 0x06cd 15481#define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 15482#define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_B 0x06ce 15483#define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 15484#define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_G 0x06cf 15485#define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 15486#define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_R 0x06d0 15487#define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 15488#define mmMPC_RMU1_SHAPER_RAMA_REGION_0_1 0x06d1 15489#define mmMPC_RMU1_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 15490#define mmMPC_RMU1_SHAPER_RAMA_REGION_2_3 0x06d2 15491#define mmMPC_RMU1_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 15492#define mmMPC_RMU1_SHAPER_RAMA_REGION_4_5 0x06d3 15493#define mmMPC_RMU1_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 15494#define mmMPC_RMU1_SHAPER_RAMA_REGION_6_7 0x06d4 15495#define mmMPC_RMU1_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 15496#define mmMPC_RMU1_SHAPER_RAMA_REGION_8_9 0x06d5 15497#define mmMPC_RMU1_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 15498#define mmMPC_RMU1_SHAPER_RAMA_REGION_10_11 0x06d6 15499#define mmMPC_RMU1_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 15500#define mmMPC_RMU1_SHAPER_RAMA_REGION_12_13 0x06d7 15501#define mmMPC_RMU1_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 15502#define mmMPC_RMU1_SHAPER_RAMA_REGION_14_15 0x06d8 15503#define mmMPC_RMU1_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 15504#define mmMPC_RMU1_SHAPER_RAMA_REGION_16_17 0x06d9 15505#define mmMPC_RMU1_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 15506#define mmMPC_RMU1_SHAPER_RAMA_REGION_18_19 0x06da 15507#define mmMPC_RMU1_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 15508#define mmMPC_RMU1_SHAPER_RAMA_REGION_20_21 0x06db 15509#define mmMPC_RMU1_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 15510#define mmMPC_RMU1_SHAPER_RAMA_REGION_22_23 0x06dc 15511#define mmMPC_RMU1_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 15512#define mmMPC_RMU1_SHAPER_RAMA_REGION_24_25 0x06dd 15513#define mmMPC_RMU1_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 15514#define mmMPC_RMU1_SHAPER_RAMA_REGION_26_27 0x06de 15515#define mmMPC_RMU1_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 15516#define mmMPC_RMU1_SHAPER_RAMA_REGION_28_29 0x06df 15517#define mmMPC_RMU1_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 15518#define mmMPC_RMU1_SHAPER_RAMA_REGION_30_31 0x06e0 15519#define mmMPC_RMU1_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 15520#define mmMPC_RMU1_SHAPER_RAMA_REGION_32_33 0x06e1 15521#define mmMPC_RMU1_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 15522#define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_B 0x06e2 15523#define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 15524#define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_G 0x06e3 15525#define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 15526#define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_R 0x06e4 15527#define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 15528#define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_B 0x06e5 15529#define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 15530#define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_G 0x06e6 15531#define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 15532#define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_R 0x06e7 15533#define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 15534#define mmMPC_RMU1_SHAPER_RAMB_REGION_0_1 0x06e8 15535#define mmMPC_RMU1_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 15536#define mmMPC_RMU1_SHAPER_RAMB_REGION_2_3 0x06e9 15537#define mmMPC_RMU1_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 15538#define mmMPC_RMU1_SHAPER_RAMB_REGION_4_5 0x06ea 15539#define mmMPC_RMU1_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 15540#define mmMPC_RMU1_SHAPER_RAMB_REGION_6_7 0x06eb 15541#define mmMPC_RMU1_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 15542#define mmMPC_RMU1_SHAPER_RAMB_REGION_8_9 0x06ec 15543#define mmMPC_RMU1_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 15544#define mmMPC_RMU1_SHAPER_RAMB_REGION_10_11 0x06ed 15545#define mmMPC_RMU1_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 15546#define mmMPC_RMU1_SHAPER_RAMB_REGION_12_13 0x06ee 15547#define mmMPC_RMU1_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 15548#define mmMPC_RMU1_SHAPER_RAMB_REGION_14_15 0x06ef 15549#define mmMPC_RMU1_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 15550#define mmMPC_RMU1_SHAPER_RAMB_REGION_16_17 0x06f0 15551#define mmMPC_RMU1_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 15552#define mmMPC_RMU1_SHAPER_RAMB_REGION_18_19 0x06f1 15553#define mmMPC_RMU1_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 15554#define mmMPC_RMU1_SHAPER_RAMB_REGION_20_21 0x06f2 15555#define mmMPC_RMU1_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 15556#define mmMPC_RMU1_SHAPER_RAMB_REGION_22_23 0x06f3 15557#define mmMPC_RMU1_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 15558#define mmMPC_RMU1_SHAPER_RAMB_REGION_24_25 0x06f4 15559#define mmMPC_RMU1_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 15560#define mmMPC_RMU1_SHAPER_RAMB_REGION_26_27 0x06f5 15561#define mmMPC_RMU1_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 15562#define mmMPC_RMU1_SHAPER_RAMB_REGION_28_29 0x06f6 15563#define mmMPC_RMU1_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 15564#define mmMPC_RMU1_SHAPER_RAMB_REGION_30_31 0x06f7 15565#define mmMPC_RMU1_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 15566#define mmMPC_RMU1_SHAPER_RAMB_REGION_32_33 0x06f8 15567#define mmMPC_RMU1_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 15568#define mmMPC_RMU1_3DLUT_MODE 0x06f9 15569#define mmMPC_RMU1_3DLUT_MODE_BASE_IDX 3 15570#define mmMPC_RMU1_3DLUT_INDEX 0x06fa 15571#define mmMPC_RMU1_3DLUT_INDEX_BASE_IDX 3 15572#define mmMPC_RMU1_3DLUT_DATA 0x06fb 15573#define mmMPC_RMU1_3DLUT_DATA_BASE_IDX 3 15574#define mmMPC_RMU1_3DLUT_DATA_30BIT 0x06fc 15575#define mmMPC_RMU1_3DLUT_DATA_30BIT_BASE_IDX 3 15576#define mmMPC_RMU1_3DLUT_READ_WRITE_CONTROL 0x06fd 15577#define mmMPC_RMU1_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 15578#define mmMPC_RMU1_3DLUT_OUT_NORM_FACTOR 0x06fe 15579#define mmMPC_RMU1_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 15580#define mmMPC_RMU1_3DLUT_OUT_OFFSET_R 0x06ff 15581#define mmMPC_RMU1_3DLUT_OUT_OFFSET_R_BASE_IDX 3 15582#define mmMPC_RMU1_3DLUT_OUT_OFFSET_G 0x0700 15583#define mmMPC_RMU1_3DLUT_OUT_OFFSET_G_BASE_IDX 3 15584#define mmMPC_RMU1_3DLUT_OUT_OFFSET_B 0x0701 15585#define mmMPC_RMU1_3DLUT_OUT_OFFSET_B_BASE_IDX 3 15586#define mmMPC_RMU2_SHAPER_CONTROL 0x0702 15587#define mmMPC_RMU2_SHAPER_CONTROL_BASE_IDX 3 15588#define mmMPC_RMU2_SHAPER_OFFSET_R 0x0703 15589#define mmMPC_RMU2_SHAPER_OFFSET_R_BASE_IDX 3 15590#define mmMPC_RMU2_SHAPER_OFFSET_G 0x0704 15591#define mmMPC_RMU2_SHAPER_OFFSET_G_BASE_IDX 3 15592#define mmMPC_RMU2_SHAPER_OFFSET_B 0x0705 15593#define mmMPC_RMU2_SHAPER_OFFSET_B_BASE_IDX 3 15594#define mmMPC_RMU2_SHAPER_SCALE_R 0x0706 15595#define mmMPC_RMU2_SHAPER_SCALE_R_BASE_IDX 3 15596#define mmMPC_RMU2_SHAPER_SCALE_G_B 0x0707 15597#define mmMPC_RMU2_SHAPER_SCALE_G_B_BASE_IDX 3 15598#define mmMPC_RMU2_SHAPER_LUT_INDEX 0x0708 15599#define mmMPC_RMU2_SHAPER_LUT_INDEX_BASE_IDX 3 15600#define mmMPC_RMU2_SHAPER_LUT_DATA 0x0709 15601#define mmMPC_RMU2_SHAPER_LUT_DATA_BASE_IDX 3 15602#define mmMPC_RMU2_SHAPER_LUT_WRITE_EN_MASK 0x070a 15603#define mmMPC_RMU2_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 15604#define mmMPC_RMU2_SHAPER_RAMA_START_CNTL_B 0x070b 15605#define mmMPC_RMU2_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 15606#define mmMPC_RMU2_SHAPER_RAMA_START_CNTL_G 0x070c 15607#define mmMPC_RMU2_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 15608#define mmMPC_RMU2_SHAPER_RAMA_START_CNTL_R 0x070d 15609#define mmMPC_RMU2_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 15610#define mmMPC_RMU2_SHAPER_RAMA_END_CNTL_B 0x070e 15611#define mmMPC_RMU2_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 15612#define mmMPC_RMU2_SHAPER_RAMA_END_CNTL_G 0x070f 15613#define mmMPC_RMU2_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 15614#define mmMPC_RMU2_SHAPER_RAMA_END_CNTL_R 0x0710 15615#define mmMPC_RMU2_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 15616#define mmMPC_RMU2_SHAPER_RAMA_REGION_0_1 0x0711 15617#define mmMPC_RMU2_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 15618#define mmMPC_RMU2_SHAPER_RAMA_REGION_2_3 0x0712 15619#define mmMPC_RMU2_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 15620#define mmMPC_RMU2_SHAPER_RAMA_REGION_4_5 0x0713 15621#define mmMPC_RMU2_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 15622#define mmMPC_RMU2_SHAPER_RAMA_REGION_6_7 0x0714 15623#define mmMPC_RMU2_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 15624#define mmMPC_RMU2_SHAPER_RAMA_REGION_8_9 0x0715 15625#define mmMPC_RMU2_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 15626#define mmMPC_RMU2_SHAPER_RAMA_REGION_10_11 0x0716 15627#define mmMPC_RMU2_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 15628#define mmMPC_RMU2_SHAPER_RAMA_REGION_12_13 0x0717 15629#define mmMPC_RMU2_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 15630#define mmMPC_RMU2_SHAPER_RAMA_REGION_14_15 0x0718 15631#define mmMPC_RMU2_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 15632#define mmMPC_RMU2_SHAPER_RAMA_REGION_16_17 0x0719 15633#define mmMPC_RMU2_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 15634#define mmMPC_RMU2_SHAPER_RAMA_REGION_18_19 0x071a 15635#define mmMPC_RMU2_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 15636#define mmMPC_RMU2_SHAPER_RAMA_REGION_20_21 0x071b 15637#define mmMPC_RMU2_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 15638#define mmMPC_RMU2_SHAPER_RAMA_REGION_22_23 0x071c 15639#define mmMPC_RMU2_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 15640#define mmMPC_RMU2_SHAPER_RAMA_REGION_24_25 0x071d 15641#define mmMPC_RMU2_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 15642#define mmMPC_RMU2_SHAPER_RAMA_REGION_26_27 0x071e 15643#define mmMPC_RMU2_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 15644#define mmMPC_RMU2_SHAPER_RAMA_REGION_28_29 0x071f 15645#define mmMPC_RMU2_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 15646#define mmMPC_RMU2_SHAPER_RAMA_REGION_30_31 0x0720 15647#define mmMPC_RMU2_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 15648#define mmMPC_RMU2_SHAPER_RAMA_REGION_32_33 0x0721 15649#define mmMPC_RMU2_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 15650#define mmMPC_RMU2_SHAPER_RAMB_START_CNTL_B 0x0722 15651#define mmMPC_RMU2_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 15652#define mmMPC_RMU2_SHAPER_RAMB_START_CNTL_G 0x0723 15653#define mmMPC_RMU2_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 15654#define mmMPC_RMU2_SHAPER_RAMB_START_CNTL_R 0x0724 15655#define mmMPC_RMU2_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 15656#define mmMPC_RMU2_SHAPER_RAMB_END_CNTL_B 0x0725 15657#define mmMPC_RMU2_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 15658#define mmMPC_RMU2_SHAPER_RAMB_END_CNTL_G 0x0726 15659#define mmMPC_RMU2_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 15660#define mmMPC_RMU2_SHAPER_RAMB_END_CNTL_R 0x0727 15661#define mmMPC_RMU2_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 15662#define mmMPC_RMU2_SHAPER_RAMB_REGION_0_1 0x0728 15663#define mmMPC_RMU2_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 15664#define mmMPC_RMU2_SHAPER_RAMB_REGION_2_3 0x0729 15665#define mmMPC_RMU2_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 15666#define mmMPC_RMU2_SHAPER_RAMB_REGION_4_5 0x072a 15667#define mmMPC_RMU2_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 15668#define mmMPC_RMU2_SHAPER_RAMB_REGION_6_7 0x072b 15669#define mmMPC_RMU2_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 15670#define mmMPC_RMU2_SHAPER_RAMB_REGION_8_9 0x072c 15671#define mmMPC_RMU2_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 15672#define mmMPC_RMU2_SHAPER_RAMB_REGION_10_11 0x072d 15673#define mmMPC_RMU2_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 15674#define mmMPC_RMU2_SHAPER_RAMB_REGION_12_13 0x072e 15675#define mmMPC_RMU2_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 15676#define mmMPC_RMU2_SHAPER_RAMB_REGION_14_15 0x072f 15677#define mmMPC_RMU2_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 15678#define mmMPC_RMU2_SHAPER_RAMB_REGION_16_17 0x0730 15679#define mmMPC_RMU2_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 15680#define mmMPC_RMU2_SHAPER_RAMB_REGION_18_19 0x0731 15681#define mmMPC_RMU2_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 15682#define mmMPC_RMU2_SHAPER_RAMB_REGION_20_21 0x0732 15683#define mmMPC_RMU2_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 15684#define mmMPC_RMU2_SHAPER_RAMB_REGION_22_23 0x0733 15685#define mmMPC_RMU2_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 15686#define mmMPC_RMU2_SHAPER_RAMB_REGION_24_25 0x0734 15687#define mmMPC_RMU2_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 15688#define mmMPC_RMU2_SHAPER_RAMB_REGION_26_27 0x0735 15689#define mmMPC_RMU2_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 15690#define mmMPC_RMU2_SHAPER_RAMB_REGION_28_29 0x0736 15691#define mmMPC_RMU2_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 15692#define mmMPC_RMU2_SHAPER_RAMB_REGION_30_31 0x0737 15693#define mmMPC_RMU2_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 15694#define mmMPC_RMU2_SHAPER_RAMB_REGION_32_33 0x0738 15695#define mmMPC_RMU2_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 15696#define mmMPC_RMU2_3DLUT_MODE 0x0739 15697#define mmMPC_RMU2_3DLUT_MODE_BASE_IDX 3 15698#define mmMPC_RMU2_3DLUT_INDEX 0x073a 15699#define mmMPC_RMU2_3DLUT_INDEX_BASE_IDX 3 15700#define mmMPC_RMU2_3DLUT_DATA 0x073b 15701#define mmMPC_RMU2_3DLUT_DATA_BASE_IDX 3 15702#define mmMPC_RMU2_3DLUT_DATA_30BIT 0x073c 15703#define mmMPC_RMU2_3DLUT_DATA_30BIT_BASE_IDX 3 15704#define mmMPC_RMU2_3DLUT_READ_WRITE_CONTROL 0x073d 15705#define mmMPC_RMU2_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 15706#define mmMPC_RMU2_3DLUT_OUT_NORM_FACTOR 0x073e 15707#define mmMPC_RMU2_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 15708#define mmMPC_RMU2_3DLUT_OUT_OFFSET_R 0x073f 15709#define mmMPC_RMU2_3DLUT_OUT_OFFSET_R_BASE_IDX 3 15710#define mmMPC_RMU2_3DLUT_OUT_OFFSET_G 0x0740 15711#define mmMPC_RMU2_3DLUT_OUT_OFFSET_G_BASE_IDX 3 15712#define mmMPC_RMU2_3DLUT_OUT_OFFSET_B 0x0741 15713#define mmMPC_RMU2_3DLUT_OUT_OFFSET_B_BASE_IDX 3 15714 15715 15716// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec 15717// base address: 0x1901c 15718#define mmDC_PERFMON28_PERFCOUNTER_CNTL 0x08c7 15719#define mmDC_PERFMON28_PERFCOUNTER_CNTL_BASE_IDX 3 15720#define mmDC_PERFMON28_PERFCOUNTER_CNTL2 0x08c8 15721#define mmDC_PERFMON28_PERFCOUNTER_CNTL2_BASE_IDX 3 15722#define mmDC_PERFMON28_PERFCOUNTER_STATE 0x08c9 15723#define mmDC_PERFMON28_PERFCOUNTER_STATE_BASE_IDX 3 15724#define mmDC_PERFMON28_PERFMON_CNTL 0x08ca 15725#define mmDC_PERFMON28_PERFMON_CNTL_BASE_IDX 3 15726#define mmDC_PERFMON28_PERFMON_CNTL2 0x08cb 15727#define mmDC_PERFMON28_PERFMON_CNTL2_BASE_IDX 3 15728#define mmDC_PERFMON28_PERFMON_CVALUE_INT_MISC 0x08cc 15729#define mmDC_PERFMON28_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 15730#define mmDC_PERFMON28_PERFMON_CVALUE_LOW 0x08cd 15731#define mmDC_PERFMON28_PERFMON_CVALUE_LOW_BASE_IDX 3 15732#define mmDC_PERFMON28_PERFMON_HI 0x08ce 15733#define mmDC_PERFMON28_PERFMON_HI_BASE_IDX 3 15734#define mmDC_PERFMON28_PERFMON_LOW 0x08cf 15735#define mmDC_PERFMON28_PERFMON_LOW_BASE_IDX 3 15736 15737// base address: 0x2646c 15738#define mmAFMT6_AFMT_VBI_PACKET_CONTROL 0x091c 15739#define mmAFMT6_AFMT_VBI_PACKET_CONTROL_BASE_IDX 3 15740#define mmAFMT6_AFMT_AUDIO_PACKET_CONTROL2 0x091d 15741#define mmAFMT6_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 3 15742#define mmAFMT6_AFMT_AUDIO_INFO0 0x091e 15743#define mmAFMT6_AFMT_AUDIO_INFO0_BASE_IDX 3 15744#define mmAFMT6_AFMT_AUDIO_INFO1 0x091f 15745#define mmAFMT6_AFMT_AUDIO_INFO1_BASE_IDX 3 15746#define mmAFMT6_AFMT_60958_0 0x0920 15747#define mmAFMT6_AFMT_60958_0_BASE_IDX 3 15748#define mmAFMT6_AFMT_60958_1 0x0921 15749#define mmAFMT6_AFMT_60958_1_BASE_IDX 3 15750#define mmAFMT6_AFMT_AUDIO_CRC_CONTROL 0x0922 15751#define mmAFMT6_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 3 15752#define mmAFMT6_AFMT_RAMP_CONTROL0 0x0923 15753#define mmAFMT6_AFMT_RAMP_CONTROL0_BASE_IDX 3 15754#define mmAFMT6_AFMT_RAMP_CONTROL1 0x0924 15755#define mmAFMT6_AFMT_RAMP_CONTROL1_BASE_IDX 3 15756#define mmAFMT6_AFMT_RAMP_CONTROL2 0x0925 15757#define mmAFMT6_AFMT_RAMP_CONTROL2_BASE_IDX 3 15758#define mmAFMT6_AFMT_RAMP_CONTROL3 0x0926 15759#define mmAFMT6_AFMT_RAMP_CONTROL3_BASE_IDX 3 15760#define mmAFMT6_AFMT_60958_2 0x0927 15761#define mmAFMT6_AFMT_60958_2_BASE_IDX 3 15762#define mmAFMT6_AFMT_AUDIO_CRC_RESULT 0x0928 15763#define mmAFMT6_AFMT_AUDIO_CRC_RESULT_BASE_IDX 3 15764#define mmAFMT6_AFMT_STATUS 0x0929 15765#define mmAFMT6_AFMT_STATUS_BASE_IDX 3 15766#define mmAFMT6_AFMT_AUDIO_PACKET_CONTROL 0x092a 15767#define mmAFMT6_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 3 15768#define mmAFMT6_AFMT_INFOFRAME_CONTROL0 0x092b 15769#define mmAFMT6_AFMT_INFOFRAME_CONTROL0_BASE_IDX 3 15770#define mmAFMT6_AFMT_INTERRUPT_STATUS 0x092c 15771#define mmAFMT6_AFMT_INTERRUPT_STATUS_BASE_IDX 3 15772#define mmAFMT6_AFMT_AUDIO_SRC_CONTROL 0x092d 15773#define mmAFMT6_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 3 15774#define mmAFMT6_AFMT_MEM_PWR 0x092f 15775#define mmAFMT6_AFMT_MEM_PWR_BASE_IDX 3 15776 15777 15778// base address: 0x264c4 15779#define mmVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL 0x0931 15780#define mmVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 3 15781#define mmVPG6_VPG_GENERIC_PACKET_DATA 0x0932 15782#define mmVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX 3 15783#define mmVPG6_VPG_GSP_FRAME_UPDATE_CTRL 0x0933 15784#define mmVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 3 15785#define mmVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x0934 15786#define mmVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 3 15787#define mmVPG6_VPG_GENERIC_STATUS 0x0935 15788#define mmVPG6_VPG_GENERIC_STATUS_BASE_IDX 3 15789#define mmVPG6_VPG_MEM_PWR 0x0936 15790#define mmVPG6_VPG_MEM_PWR_BASE_IDX 3 15791#define mmVPG6_VPG_ISRC1_2_ACCESS_CTRL 0x0937 15792#define mmVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 3 15793#define mmVPG6_VPG_ISRC1_2_DATA 0x0938 15794#define mmVPG6_VPG_ISRC1_2_DATA_BASE_IDX 3 15795#define mmVPG6_VPG_MPEG_INFO0 0x0939 15796#define mmVPG6_VPG_MPEG_INFO0_BASE_IDX 3 15797#define mmVPG6_VPG_MPEG_INFO1 0x093a 15798#define mmVPG6_VPG_MPEG_INFO1_BASE_IDX 3 15799 15800 15801// base address: 0x264f0 15802#define mmDME6_DME_CONTROL 0x093c 15803#define mmDME6_DME_CONTROL_BASE_IDX 3 15804#define mmDME6_DME_MEMORY_CONTROL 0x093d 15805#define mmDME6_DME_MEMORY_CONTROL_BASE_IDX 3 15806 15807// base address: 0x1a698 15808#define mmDC_PERFMON29_PERFCOUNTER_CNTL 0x0e66 15809#define mmDC_PERFMON29_PERFCOUNTER_CNTL_BASE_IDX 3 15810#define mmDC_PERFMON29_PERFCOUNTER_CNTL2 0x0e67 15811#define mmDC_PERFMON29_PERFCOUNTER_CNTL2_BASE_IDX 3 15812#define mmDC_PERFMON29_PERFCOUNTER_STATE 0x0e68 15813#define mmDC_PERFMON29_PERFCOUNTER_STATE_BASE_IDX 3 15814#define mmDC_PERFMON29_PERFMON_CNTL 0x0e69 15815#define mmDC_PERFMON29_PERFMON_CNTL_BASE_IDX 3 15816#define mmDC_PERFMON29_PERFMON_CNTL2 0x0e6a 15817#define mmDC_PERFMON29_PERFMON_CNTL2_BASE_IDX 3 15818#define mmDC_PERFMON29_PERFMON_CVALUE_INT_MISC 0x0e6b 15819#define mmDC_PERFMON29_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 15820#define mmDC_PERFMON29_PERFMON_CVALUE_LOW 0x0e6c 15821#define mmDC_PERFMON29_PERFMON_CVALUE_LOW_BASE_IDX 3 15822#define mmDC_PERFMON29_PERFMON_HI 0x0e6d 15823#define mmDC_PERFMON29_PERFMON_HI_BASE_IDX 3 15824#define mmDC_PERFMON29_PERFMON_LOW 0x0e6e 15825#define mmDC_PERFMON29_PERFMON_LOW_BASE_IDX 3 15826 15827 15828// addressBlock: dce_dc_opp_abm0_dispdec 15829// base address: 0x0 15830#define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0e7a 15831#define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 15832#define mmABM0_BL1_PWM_USER_LEVEL 0x0e7b 15833#define mmABM0_BL1_PWM_USER_LEVEL_BASE_IDX 3 15834#define mmABM0_BL1_PWM_TARGET_ABM_LEVEL 0x0e7c 15835#define mmABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 15836#define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL 0x0e7d 15837#define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 15838#define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE 0x0e7e 15839#define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 15840#define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0e7f 15841#define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 15842#define mmABM0_BL1_PWM_ABM_CNTL 0x0e80 15843#define mmABM0_BL1_PWM_ABM_CNTL_BASE_IDX 3 15844#define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0e81 15845#define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 15846#define mmABM0_BL1_PWM_GRP2_REG_LOCK 0x0e82 15847#define mmABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 15848#define mmABM0_DC_ABM1_CNTL 0x0e83 15849#define mmABM0_DC_ABM1_CNTL_BASE_IDX 3 15850#define mmABM0_DC_ABM1_IPCSC_COEFF_SEL 0x0e84 15851#define mmABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 15852#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0e85 15853#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 15854#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0e86 15855#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 15856#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0e87 15857#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 15858#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0e88 15859#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 15860#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0e89 15861#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 15862#define mmABM0_DC_ABM1_ACE_THRES_12 0x0e8a 15863#define mmABM0_DC_ABM1_ACE_THRES_12_BASE_IDX 3 15864#define mmABM0_DC_ABM1_ACE_THRES_34 0x0e8b 15865#define mmABM0_DC_ABM1_ACE_THRES_34_BASE_IDX 3 15866#define mmABM0_DC_ABM1_ACE_CNTL_MISC 0x0e8c 15867#define mmABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 15868#define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0e8e 15869#define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 15870#define mmABM0_DC_ABM1_HG_MISC_CTRL 0x0e8f 15871#define mmABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 15872#define mmABM0_DC_ABM1_LS_SUM_OF_LUMA 0x0e90 15873#define mmABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 15874#define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA 0x0e91 15875#define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 15876#define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0e92 15877#define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 15878#define mmABM0_DC_ABM1_LS_PIXEL_COUNT 0x0e93 15879#define mmABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 15880#define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0e94 15881#define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 15882#define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0e95 15883#define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 15884#define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0e96 15885#define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 15886#define mmABM0_DC_ABM1_HG_SAMPLE_RATE 0x0e97 15887#define mmABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 15888#define mmABM0_DC_ABM1_LS_SAMPLE_RATE 0x0e98 15889#define mmABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 15890#define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0e99 15891#define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 15892#define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0e9a 15893#define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 15894#define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0e9b 15895#define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 15896#define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0e9c 15897#define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 15898#define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0e9d 15899#define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 15900#define mmABM0_DC_ABM1_HG_RESULT_1 0x0e9e 15901#define mmABM0_DC_ABM1_HG_RESULT_1_BASE_IDX 3 15902#define mmABM0_DC_ABM1_HG_RESULT_2 0x0e9f 15903#define mmABM0_DC_ABM1_HG_RESULT_2_BASE_IDX 3 15904#define mmABM0_DC_ABM1_HG_RESULT_3 0x0ea0 15905#define mmABM0_DC_ABM1_HG_RESULT_3_BASE_IDX 3 15906#define mmABM0_DC_ABM1_HG_RESULT_4 0x0ea1 15907#define mmABM0_DC_ABM1_HG_RESULT_4_BASE_IDX 3 15908#define mmABM0_DC_ABM1_HG_RESULT_5 0x0ea2 15909#define mmABM0_DC_ABM1_HG_RESULT_5_BASE_IDX 3 15910#define mmABM0_DC_ABM1_HG_RESULT_6 0x0ea3 15911#define mmABM0_DC_ABM1_HG_RESULT_6_BASE_IDX 3 15912#define mmABM0_DC_ABM1_HG_RESULT_7 0x0ea4 15913#define mmABM0_DC_ABM1_HG_RESULT_7_BASE_IDX 3 15914#define mmABM0_DC_ABM1_HG_RESULT_8 0x0ea5 15915#define mmABM0_DC_ABM1_HG_RESULT_8_BASE_IDX 3 15916#define mmABM0_DC_ABM1_HG_RESULT_9 0x0ea6 15917#define mmABM0_DC_ABM1_HG_RESULT_9_BASE_IDX 3 15918#define mmABM0_DC_ABM1_HG_RESULT_10 0x0ea7 15919#define mmABM0_DC_ABM1_HG_RESULT_10_BASE_IDX 3 15920#define mmABM0_DC_ABM1_HG_RESULT_11 0x0ea8 15921#define mmABM0_DC_ABM1_HG_RESULT_11_BASE_IDX 3 15922#define mmABM0_DC_ABM1_HG_RESULT_12 0x0ea9 15923#define mmABM0_DC_ABM1_HG_RESULT_12_BASE_IDX 3 15924#define mmABM0_DC_ABM1_HG_RESULT_13 0x0eaa 15925#define mmABM0_DC_ABM1_HG_RESULT_13_BASE_IDX 3 15926#define mmABM0_DC_ABM1_HG_RESULT_14 0x0eab 15927#define mmABM0_DC_ABM1_HG_RESULT_14_BASE_IDX 3 15928#define mmABM0_DC_ABM1_HG_RESULT_15 0x0eac 15929#define mmABM0_DC_ABM1_HG_RESULT_15_BASE_IDX 3 15930#define mmABM0_DC_ABM1_HG_RESULT_16 0x0ead 15931#define mmABM0_DC_ABM1_HG_RESULT_16_BASE_IDX 3 15932#define mmABM0_DC_ABM1_HG_RESULT_17 0x0eae 15933#define mmABM0_DC_ABM1_HG_RESULT_17_BASE_IDX 3 15934#define mmABM0_DC_ABM1_HG_RESULT_18 0x0eaf 15935#define mmABM0_DC_ABM1_HG_RESULT_18_BASE_IDX 3 15936#define mmABM0_DC_ABM1_HG_RESULT_19 0x0eb0 15937#define mmABM0_DC_ABM1_HG_RESULT_19_BASE_IDX 3 15938#define mmABM0_DC_ABM1_HG_RESULT_20 0x0eb1 15939#define mmABM0_DC_ABM1_HG_RESULT_20_BASE_IDX 3 15940#define mmABM0_DC_ABM1_HG_RESULT_21 0x0eb2 15941#define mmABM0_DC_ABM1_HG_RESULT_21_BASE_IDX 3 15942#define mmABM0_DC_ABM1_HG_RESULT_22 0x0eb3 15943#define mmABM0_DC_ABM1_HG_RESULT_22_BASE_IDX 3 15944#define mmABM0_DC_ABM1_HG_RESULT_23 0x0eb4 15945#define mmABM0_DC_ABM1_HG_RESULT_23_BASE_IDX 3 15946#define mmABM0_DC_ABM1_HG_RESULT_24 0x0eb5 15947#define mmABM0_DC_ABM1_HG_RESULT_24_BASE_IDX 3 15948#define mmABM0_DC_ABM1_BL_MASTER_LOCK 0x0eb6 15949#define mmABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 15950 15951 15952// addressBlock: dce_dc_opp_abm1_dispdec 15953// base address: 0x104 15954#define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0ebb 15955#define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 15956#define mmABM1_BL1_PWM_USER_LEVEL 0x0ebc 15957#define mmABM1_BL1_PWM_USER_LEVEL_BASE_IDX 3 15958#define mmABM1_BL1_PWM_TARGET_ABM_LEVEL 0x0ebd 15959#define mmABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 15960#define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL 0x0ebe 15961#define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 15962#define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE 0x0ebf 15963#define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 15964#define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0ec0 15965#define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 15966#define mmABM1_BL1_PWM_ABM_CNTL 0x0ec1 15967#define mmABM1_BL1_PWM_ABM_CNTL_BASE_IDX 3 15968#define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0ec2 15969#define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 15970#define mmABM1_BL1_PWM_GRP2_REG_LOCK 0x0ec3 15971#define mmABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 15972#define mmABM1_DC_ABM1_CNTL 0x0ec4 15973#define mmABM1_DC_ABM1_CNTL_BASE_IDX 3 15974#define mmABM1_DC_ABM1_IPCSC_COEFF_SEL 0x0ec5 15975#define mmABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 15976#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0ec6 15977#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 15978#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0ec7 15979#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 15980#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0ec8 15981#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 15982#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0ec9 15983#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 15984#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0eca 15985#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 15986#define mmABM1_DC_ABM1_ACE_THRES_12 0x0ecb 15987#define mmABM1_DC_ABM1_ACE_THRES_12_BASE_IDX 3 15988#define mmABM1_DC_ABM1_ACE_THRES_34 0x0ecc 15989#define mmABM1_DC_ABM1_ACE_THRES_34_BASE_IDX 3 15990#define mmABM1_DC_ABM1_ACE_CNTL_MISC 0x0ecd 15991#define mmABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 15992#define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0ecf 15993#define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 15994#define mmABM1_DC_ABM1_HG_MISC_CTRL 0x0ed0 15995#define mmABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 15996#define mmABM1_DC_ABM1_LS_SUM_OF_LUMA 0x0ed1 15997#define mmABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 15998#define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA 0x0ed2 15999#define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 16000#define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0ed3
16001#define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 16002#define mmABM1_DC_ABM1_LS_PIXEL_COUNT 0x0ed4 16003#define mmABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 16004#define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0ed5 16005#define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 16006#define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0ed6 16007#define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 16008#define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0ed7 16009#define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 16010#define mmABM1_DC_ABM1_HG_SAMPLE_RATE 0x0ed8 16011#define mmABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 16012#define mmABM1_DC_ABM1_LS_SAMPLE_RATE 0x0ed9 16013#define mmABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 16014#define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0eda 16015#define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 16016#define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0edb 16017#define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 16018#define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0edc 16019#define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 16020#define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0edd 16021#define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 16022#define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0ede 16023#define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 16024#define mmABM1_DC_ABM1_HG_RESULT_1 0x0edf 16025#define mmABM1_DC_ABM1_HG_RESULT_1_BASE_IDX 3 16026#define mmABM1_DC_ABM1_HG_RESULT_2 0x0ee0 16027#define mmABM1_DC_ABM1_HG_RESULT_2_BASE_IDX 3 16028#define mmABM1_DC_ABM1_HG_RESULT_3 0x0ee1 16029#define mmABM1_DC_ABM1_HG_RESULT_3_BASE_IDX 3 16030#define mmABM1_DC_ABM1_HG_RESULT_4 0x0ee2 16031#define mmABM1_DC_ABM1_HG_RESULT_4_BASE_IDX 3 16032#define mmABM1_DC_ABM1_HG_RESULT_5 0x0ee3 16033#define mmABM1_DC_ABM1_HG_RESULT_5_BASE_IDX 3 16034#define mmABM1_DC_ABM1_HG_RESULT_6 0x0ee4 16035#define mmABM1_DC_ABM1_HG_RESULT_6_BASE_IDX 3 16036#define mmABM1_DC_ABM1_HG_RESULT_7 0x0ee5 16037#define mmABM1_DC_ABM1_HG_RESULT_7_BASE_IDX 3 16038#define mmABM1_DC_ABM1_HG_RESULT_8 0x0ee6 16039#define mmABM1_DC_ABM1_HG_RESULT_8_BASE_IDX 3 16040#define mmABM1_DC_ABM1_HG_RESULT_9 0x0ee7 16041#define mmABM1_DC_ABM1_HG_RESULT_9_BASE_IDX 3 16042#define mmABM1_DC_ABM1_HG_RESULT_10 0x0ee8 16043#define mmABM1_DC_ABM1_HG_RESULT_10_BASE_IDX 3 16044#define mmABM1_DC_ABM1_HG_RESULT_11 0x0ee9 16045#define mmABM1_DC_ABM1_HG_RESULT_11_BASE_IDX 3 16046#define mmABM1_DC_ABM1_HG_RESULT_12 0x0eea 16047#define mmABM1_DC_ABM1_HG_RESULT_12_BASE_IDX 3 16048#define mmABM1_DC_ABM1_HG_RESULT_13 0x0eeb 16049#define mmABM1_DC_ABM1_HG_RESULT_13_BASE_IDX 3 16050#define mmABM1_DC_ABM1_HG_RESULT_14 0x0eec 16051#define mmABM1_DC_ABM1_HG_RESULT_14_BASE_IDX 3 16052#define mmABM1_DC_ABM1_HG_RESULT_15 0x0eed 16053#define mmABM1_DC_ABM1_HG_RESULT_15_BASE_IDX 3 16054#define mmABM1_DC_ABM1_HG_RESULT_16 0x0eee 16055#define mmABM1_DC_ABM1_HG_RESULT_16_BASE_IDX 3 16056#define mmABM1_DC_ABM1_HG_RESULT_17 0x0eef 16057#define mmABM1_DC_ABM1_HG_RESULT_17_BASE_IDX 3 16058#define mmABM1_DC_ABM1_HG_RESULT_18 0x0ef0 16059#define mmABM1_DC_ABM1_HG_RESULT_18_BASE_IDX 3 16060#define mmABM1_DC_ABM1_HG_RESULT_19 0x0ef1 16061#define mmABM1_DC_ABM1_HG_RESULT_19_BASE_IDX 3 16062#define mmABM1_DC_ABM1_HG_RESULT_20 0x0ef2 16063#define mmABM1_DC_ABM1_HG_RESULT_20_BASE_IDX 3 16064#define mmABM1_DC_ABM1_HG_RESULT_21 0x0ef3 16065#define mmABM1_DC_ABM1_HG_RESULT_21_BASE_IDX 3 16066#define mmABM1_DC_ABM1_HG_RESULT_22 0x0ef4 16067#define mmABM1_DC_ABM1_HG_RESULT_22_BASE_IDX 3 16068#define mmABM1_DC_ABM1_HG_RESULT_23 0x0ef5 16069#define mmABM1_DC_ABM1_HG_RESULT_23_BASE_IDX 3 16070#define mmABM1_DC_ABM1_HG_RESULT_24 0x0ef6 16071#define mmABM1_DC_ABM1_HG_RESULT_24_BASE_IDX 3 16072#define mmABM1_DC_ABM1_BL_MASTER_LOCK 0x0ef7 16073#define mmABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 16074 16075 16076// addressBlock: dce_dc_opp_abm2_dispdec 16077// base address: 0x208 16078#define mmABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0efc 16079#define mmABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 16080#define mmABM2_BL1_PWM_USER_LEVEL 0x0efd 16081#define mmABM2_BL1_PWM_USER_LEVEL_BASE_IDX 3 16082#define mmABM2_BL1_PWM_TARGET_ABM_LEVEL 0x0efe 16083#define mmABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 16084#define mmABM2_BL1_PWM_CURRENT_ABM_LEVEL 0x0eff 16085#define mmABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 16086#define mmABM2_BL1_PWM_FINAL_DUTY_CYCLE 0x0f00 16087#define mmABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 16088#define mmABM2_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f01 16089#define mmABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 16090#define mmABM2_BL1_PWM_ABM_CNTL 0x0f02 16091#define mmABM2_BL1_PWM_ABM_CNTL_BASE_IDX 3 16092#define mmABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f03 16093#define mmABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 16094#define mmABM2_BL1_PWM_GRP2_REG_LOCK 0x0f04 16095#define mmABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 16096#define mmABM2_DC_ABM1_CNTL 0x0f05 16097#define mmABM2_DC_ABM1_CNTL_BASE_IDX 3 16098#define mmABM2_DC_ABM1_IPCSC_COEFF_SEL 0x0f06 16099#define mmABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 16100#define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f07 16101#define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 16102#define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f08 16103#define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 16104#define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f09 16105#define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 16106#define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f0a 16107#define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 16108#define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f0b 16109#define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 16110#define mmABM2_DC_ABM1_ACE_THRES_12 0x0f0c 16111#define mmABM2_DC_ABM1_ACE_THRES_12_BASE_IDX 3 16112#define mmABM2_DC_ABM1_ACE_THRES_34 0x0f0d 16113#define mmABM2_DC_ABM1_ACE_THRES_34_BASE_IDX 3 16114#define mmABM2_DC_ABM1_ACE_CNTL_MISC 0x0f0e 16115#define mmABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 16116#define mmABM2_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f10 16117#define mmABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 16118#define mmABM2_DC_ABM1_HG_MISC_CTRL 0x0f11 16119#define mmABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 16120#define mmABM2_DC_ABM1_LS_SUM_OF_LUMA 0x0f12 16121#define mmABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 16122#define mmABM2_DC_ABM1_LS_MIN_MAX_LUMA 0x0f13 16123#define mmABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 16124#define mmABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f14 16125#define mmABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 16126#define mmABM2_DC_ABM1_LS_PIXEL_COUNT 0x0f15 16127#define mmABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 16128#define mmABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f16 16129#define mmABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 16130#define mmABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f17 16131#define mmABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 16132#define mmABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f18 16133#define mmABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 16134#define mmABM2_DC_ABM1_HG_SAMPLE_RATE 0x0f19 16135#define mmABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 16136#define mmABM2_DC_ABM1_LS_SAMPLE_RATE 0x0f1a 16137#define mmABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 16138#define mmABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f1b 16139#define mmABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 16140#define mmABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f1c 16141#define mmABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 16142#define mmABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f1d 16143#define mmABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 16144#define mmABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f1e 16145#define mmABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 16146#define mmABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f1f 16147#define mmABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 16148#define mmABM2_DC_ABM1_HG_RESULT_1 0x0f20 16149#define mmABM2_DC_ABM1_HG_RESULT_1_BASE_IDX 3 16150#define mmABM2_DC_ABM1_HG_RESULT_2 0x0f21 16151#define mmABM2_DC_ABM1_HG_RESULT_2_BASE_IDX 3 16152#define mmABM2_DC_ABM1_HG_RESULT_3 0x0f22 16153#define mmABM2_DC_ABM1_HG_RESULT_3_BASE_IDX 3 16154#define mmABM2_DC_ABM1_HG_RESULT_4 0x0f23 16155#define mmABM2_DC_ABM1_HG_RESULT_4_BASE_IDX 3 16156#define mmABM2_DC_ABM1_HG_RESULT_5 0x0f24 16157#define mmABM2_DC_ABM1_HG_RESULT_5_BASE_IDX 3 16158#define mmABM2_DC_ABM1_HG_RESULT_6 0x0f25 16159#define mmABM2_DC_ABM1_HG_RESULT_6_BASE_IDX 3 16160#define mmABM2_DC_ABM1_HG_RESULT_7 0x0f26 16161#define mmABM2_DC_ABM1_HG_RESULT_7_BASE_IDX 3 16162#define mmABM2_DC_ABM1_HG_RESULT_8 0x0f27 16163#define mmABM2_DC_ABM1_HG_RESULT_8_BASE_IDX 3 16164#define mmABM2_DC_ABM1_HG_RESULT_9 0x0f28 16165#define mmABM2_DC_ABM1_HG_RESULT_9_BASE_IDX 3 16166#define mmABM2_DC_ABM1_HG_RESULT_10 0x0f29 16167#define mmABM2_DC_ABM1_HG_RESULT_10_BASE_IDX 3 16168#define mmABM2_DC_ABM1_HG_RESULT_11 0x0f2a 16169#define mmABM2_DC_ABM1_HG_RESULT_11_BASE_IDX 3 16170#define mmABM2_DC_ABM1_HG_RESULT_12 0x0f2b 16171#define mmABM2_DC_ABM1_HG_RESULT_12_BASE_IDX 3 16172#define mmABM2_DC_ABM1_HG_RESULT_13 0x0f2c 16173#define mmABM2_DC_ABM1_HG_RESULT_13_BASE_IDX 3 16174#define mmABM2_DC_ABM1_HG_RESULT_14 0x0f2d 16175#define mmABM2_DC_ABM1_HG_RESULT_14_BASE_IDX 3 16176#define mmABM2_DC_ABM1_HG_RESULT_15 0x0f2e 16177#define mmABM2_DC_ABM1_HG_RESULT_15_BASE_IDX 3 16178#define mmABM2_DC_ABM1_HG_RESULT_16 0x0f2f 16179#define mmABM2_DC_ABM1_HG_RESULT_16_BASE_IDX 3 16180#define mmABM2_DC_ABM1_HG_RESULT_17 0x0f30 16181#define mmABM2_DC_ABM1_HG_RESULT_17_BASE_IDX 3 16182#define mmABM2_DC_ABM1_HG_RESULT_18 0x0f31 16183#define mmABM2_DC_ABM1_HG_RESULT_18_BASE_IDX 3 16184#define mmABM2_DC_ABM1_HG_RESULT_19 0x0f32 16185#define mmABM2_DC_ABM1_HG_RESULT_19_BASE_IDX 3 16186#define mmABM2_DC_ABM1_HG_RESULT_20 0x0f33 16187#define mmABM2_DC_ABM1_HG_RESULT_20_BASE_IDX 3 16188#define mmABM2_DC_ABM1_HG_RESULT_21 0x0f34 16189#define mmABM2_DC_ABM1_HG_RESULT_21_BASE_IDX 3 16190#define mmABM2_DC_ABM1_HG_RESULT_22 0x0f35 16191#define mmABM2_DC_ABM1_HG_RESULT_22_BASE_IDX 3 16192#define mmABM2_DC_ABM1_HG_RESULT_23 0x0f36 16193#define mmABM2_DC_ABM1_HG_RESULT_23_BASE_IDX 3 16194#define mmABM2_DC_ABM1_HG_RESULT_24 0x0f37 16195#define mmABM2_DC_ABM1_HG_RESULT_24_BASE_IDX 3 16196#define mmABM2_DC_ABM1_BL_MASTER_LOCK 0x0f38 16197#define mmABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 16198 16199 16200// addressBlock: dce_dc_opp_abm3_dispdec 16201// base address: 0x30c 16202#define mmABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0f3d 16203#define mmABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 16204#define mmABM3_BL1_PWM_USER_LEVEL 0x0f3e 16205#define mmABM3_BL1_PWM_USER_LEVEL_BASE_IDX 3 16206#define mmABM3_BL1_PWM_TARGET_ABM_LEVEL 0x0f3f 16207#define mmABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 16208#define mmABM3_BL1_PWM_CURRENT_ABM_LEVEL 0x0f40 16209#define mmABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 16210#define mmABM3_BL1_PWM_FINAL_DUTY_CYCLE 0x0f41 16211#define mmABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 16212#define mmABM3_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f42 16213#define mmABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 16214#define mmABM3_BL1_PWM_ABM_CNTL 0x0f43 16215#define mmABM3_BL1_PWM_ABM_CNTL_BASE_IDX 3 16216#define mmABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f44 16217#define mmABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 16218#define mmABM3_BL1_PWM_GRP2_REG_LOCK 0x0f45 16219#define mmABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 16220#define mmABM3_DC_ABM1_CNTL 0x0f46 16221#define mmABM3_DC_ABM1_CNTL_BASE_IDX 3 16222#define mmABM3_DC_ABM1_IPCSC_COEFF_SEL 0x0f47 16223#define mmABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 16224#define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f48 16225#define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 16226#define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f49 16227#define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 16228#define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f4a 16229#define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 16230#define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f4b 16231#define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 16232#define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f4c 16233#define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 16234#define mmABM3_DC_ABM1_ACE_THRES_12 0x0f4d 16235#define mmABM3_DC_ABM1_ACE_THRES_12_BASE_IDX 3 16236#define mmABM3_DC_ABM1_ACE_THRES_34 0x0f4e 16237#define mmABM3_DC_ABM1_ACE_THRES_34_BASE_IDX 3 16238#define mmABM3_DC_ABM1_ACE_CNTL_MISC 0x0f4f 16239#define mmABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 16240#define mmABM3_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f51 16241#define mmABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 16242#define mmABM3_DC_ABM1_HG_MISC_CTRL 0x0f52 16243#define mmABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 16244#define mmABM3_DC_ABM1_LS_SUM_OF_LUMA 0x0f53 16245#define mmABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 16246#define mmABM3_DC_ABM1_LS_MIN_MAX_LUMA 0x0f54 16247#define mmABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 16248#define mmABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f55 16249#define mmABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 16250#define mmABM3_DC_ABM1_LS_PIXEL_COUNT 0x0f56 16251#define mmABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 16252#define mmABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f57 16253#define mmABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 16254#define mmABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f58 16255#define mmABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 16256#define mmABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f59 16257#define mmABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 16258#define mmABM3_DC_ABM1_HG_SAMPLE_RATE 0x0f5a 16259#define mmABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 16260#define mmABM3_DC_ABM1_LS_SAMPLE_RATE 0x0f5b 16261#define mmABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 16262#define mmABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f5c 16263#define mmABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 16264#define mmABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f5d 16265#define mmABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 16266#define mmABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f5e 16267#define mmABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 16268#define mmABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f5f 16269#define mmABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 16270#define mmABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f60 16271#define mmABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 16272#define mmABM3_DC_ABM1_HG_RESULT_1 0x0f61 16273#define mmABM3_DC_ABM1_HG_RESULT_1_BASE_IDX 3 16274#define mmABM3_DC_ABM1_HG_RESULT_2 0x0f62 16275#define mmABM3_DC_ABM1_HG_RESULT_2_BASE_IDX 3 16276#define mmABM3_DC_ABM1_HG_RESULT_3 0x0f63 16277#define mmABM3_DC_ABM1_HG_RESULT_3_BASE_IDX 3 16278#define mmABM3_DC_ABM1_HG_RESULT_4 0x0f64 16279#define mmABM3_DC_ABM1_HG_RESULT_4_BASE_IDX 3 16280#define mmABM3_DC_ABM1_HG_RESULT_5 0x0f65 16281#define mmABM3_DC_ABM1_HG_RESULT_5_BASE_IDX 3 16282#define mmABM3_DC_ABM1_HG_RESULT_6 0x0f66 16283#define mmABM3_DC_ABM1_HG_RESULT_6_BASE_IDX 3 16284#define mmABM3_DC_ABM1_HG_RESULT_7 0x0f67 16285#define mmABM3_DC_ABM1_HG_RESULT_7_BASE_IDX 3 16286#define mmABM3_DC_ABM1_HG_RESULT_8 0x0f68 16287#define mmABM3_DC_ABM1_HG_RESULT_8_BASE_IDX 3 16288#define mmABM3_DC_ABM1_HG_RESULT_9 0x0f69 16289#define mmABM3_DC_ABM1_HG_RESULT_9_BASE_IDX 3 16290#define mmABM3_DC_ABM1_HG_RESULT_10 0x0f6a 16291#define mmABM3_DC_ABM1_HG_RESULT_10_BASE_IDX 3 16292#define mmABM3_DC_ABM1_HG_RESULT_11 0x0f6b 16293#define mmABM3_DC_ABM1_HG_RESULT_11_BASE_IDX 3 16294#define mmABM3_DC_ABM1_HG_RESULT_12 0x0f6c 16295#define mmABM3_DC_ABM1_HG_RESULT_12_BASE_IDX 3 16296#define mmABM3_DC_ABM1_HG_RESULT_13 0x0f6d 16297#define mmABM3_DC_ABM1_HG_RESULT_13_BASE_IDX 3 16298#define mmABM3_DC_ABM1_HG_RESULT_14 0x0f6e 16299#define mmABM3_DC_ABM1_HG_RESULT_14_BASE_IDX 3 16300#define mmABM3_DC_ABM1_HG_RESULT_15 0x0f6f 16301#define mmABM3_DC_ABM1_HG_RESULT_15_BASE_IDX 3 16302#define mmABM3_DC_ABM1_HG_RESULT_16 0x0f70 16303#define mmABM3_DC_ABM1_HG_RESULT_16_BASE_IDX 3 16304#define mmABM3_DC_ABM1_HG_RESULT_17 0x0f71 16305#define mmABM3_DC_ABM1_HG_RESULT_17_BASE_IDX 3 16306#define mmABM3_DC_ABM1_HG_RESULT_18 0x0f72 16307#define mmABM3_DC_ABM1_HG_RESULT_18_BASE_IDX 3 16308#define mmABM3_DC_ABM1_HG_RESULT_19 0x0f73 16309#define mmABM3_DC_ABM1_HG_RESULT_19_BASE_IDX 3 16310#define mmABM3_DC_ABM1_HG_RESULT_20 0x0f74 16311#define mmABM3_DC_ABM1_HG_RESULT_20_BASE_IDX 3 16312#define mmABM3_DC_ABM1_HG_RESULT_21 0x0f75 16313#define mmABM3_DC_ABM1_HG_RESULT_21_BASE_IDX 3 16314#define mmABM3_DC_ABM1_HG_RESULT_22 0x0f76 16315#define mmABM3_DC_ABM1_HG_RESULT_22_BASE_IDX 3 16316#define mmABM3_DC_ABM1_HG_RESULT_23 0x0f77 16317#define mmABM3_DC_ABM1_HG_RESULT_23_BASE_IDX 3 16318#define mmABM3_DC_ABM1_HG_RESULT_24 0x0f78 16319#define mmABM3_DC_ABM1_HG_RESULT_24_BASE_IDX 3 16320#define mmABM3_DC_ABM1_BL_MASTER_LOCK 0x0f79 16321#define mmABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 16322 16323 16324// addressBlock: dce_dc_opp_abm4_dispdec 16325// base address: 0x410 16326#define mmABM4_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0f7e 16327#define mmABM4_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 16328#define mmABM4_BL1_PWM_USER_LEVEL 0x0f7f 16329#define mmABM4_BL1_PWM_USER_LEVEL_BASE_IDX 3 16330#define mmABM4_BL1_PWM_TARGET_ABM_LEVEL 0x0f80 16331#define mmABM4_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 16332#define mmABM4_BL1_PWM_CURRENT_ABM_LEVEL 0x0f81 16333#define mmABM4_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 16334#define mmABM4_BL1_PWM_FINAL_DUTY_CYCLE 0x0f82 16335#define mmABM4_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 16336#define mmABM4_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f83 16337#define mmABM4_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 16338#define mmABM4_BL1_PWM_ABM_CNTL 0x0f84 16339#define mmABM4_BL1_PWM_ABM_CNTL_BASE_IDX 3 16340#define mmABM4_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f85 16341#define mmABM4_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 16342#define mmABM4_BL1_PWM_GRP2_REG_LOCK 0x0f86 16343#define mmABM4_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 16344#define mmABM4_DC_ABM1_CNTL 0x0f87 16345#define mmABM4_DC_ABM1_CNTL_BASE_IDX 3 16346#define mmABM4_DC_ABM1_IPCSC_COEFF_SEL 0x0f88 16347#define mmABM4_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 16348#define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f89 16349#define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 16350#define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f8a 16351#define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 16352#define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f8b 16353#define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 16354#define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f8c 16355#define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 16356#define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f8d 16357#define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 16358#define mmABM4_DC_ABM1_ACE_THRES_12 0x0f8e 16359#define mmABM4_DC_ABM1_ACE_THRES_12_BASE_IDX 3 16360#define mmABM4_DC_ABM1_ACE_THRES_34 0x0f8f 16361#define mmABM4_DC_ABM1_ACE_THRES_34_BASE_IDX 3 16362#define mmABM4_DC_ABM1_ACE_CNTL_MISC 0x0f90 16363#define mmABM4_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 16364#define mmABM4_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f92 16365#define mmABM4_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 16366#define mmABM4_DC_ABM1_HG_MISC_CTRL 0x0f93 16367#define mmABM4_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 16368#define mmABM4_DC_ABM1_LS_SUM_OF_LUMA 0x0f94 16369#define mmABM4_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 16370#define mmABM4_DC_ABM1_LS_MIN_MAX_LUMA 0x0f95 16371#define mmABM4_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 16372#define mmABM4_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f96 16373#define mmABM4_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 16374#define mmABM4_DC_ABM1_LS_PIXEL_COUNT 0x0f97 16375#define mmABM4_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 16376#define mmABM4_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f98 16377#define mmABM4_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 16378#define mmABM4_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f99 16379#define mmABM4_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 16380#define mmABM4_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f9a 16381#define mmABM4_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 16382#define mmABM4_DC_ABM1_HG_SAMPLE_RATE 0x0f9b 16383#define mmABM4_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 16384#define mmABM4_DC_ABM1_LS_SAMPLE_RATE 0x0f9c 16385#define mmABM4_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 16386#define mmABM4_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f9d 16387#define mmABM4_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 16388#define mmABM4_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f9e 16389#define mmABM4_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 16390#define mmABM4_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f9f 16391#define mmABM4_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 16392#define mmABM4_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0fa0 16393#define mmABM4_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 16394#define mmABM4_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0fa1 16395#define mmABM4_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 16396#define mmABM4_DC_ABM1_HG_RESULT_1 0x0fa2 16397#define mmABM4_DC_ABM1_HG_RESULT_1_BASE_IDX 3 16398#define mmABM4_DC_ABM1_HG_RESULT_2 0x0fa3 16399#define mmABM4_DC_ABM1_HG_RESULT_2_BASE_IDX 3 16400#define mmABM4_DC_ABM1_HG_RESULT_3 0x0fa4 16401#define mmABM4_DC_ABM1_HG_RESULT_3_BASE_IDX 3 16402#define mmABM4_DC_ABM1_HG_RESULT_4 0x0fa5 16403#define mmABM4_DC_ABM1_HG_RESULT_4_BASE_IDX 3 16404#define mmABM4_DC_ABM1_HG_RESULT_5 0x0fa6 16405#define mmABM4_DC_ABM1_HG_RESULT_5_BASE_IDX 3 16406#define mmABM4_DC_ABM1_HG_RESULT_6 0x0fa7 16407#define mmABM4_DC_ABM1_HG_RESULT_6_BASE_IDX 3 16408#define mmABM4_DC_ABM1_HG_RESULT_7 0x0fa8 16409#define mmABM4_DC_ABM1_HG_RESULT_7_BASE_IDX 3 16410#define mmABM4_DC_ABM1_HG_RESULT_8 0x0fa9 16411#define mmABM4_DC_ABM1_HG_RESULT_8_BASE_IDX 3 16412#define mmABM4_DC_ABM1_HG_RESULT_9 0x0faa 16413#define mmABM4_DC_ABM1_HG_RESULT_9_BASE_IDX 3 16414#define mmABM4_DC_ABM1_HG_RESULT_10 0x0fab 16415#define mmABM4_DC_ABM1_HG_RESULT_10_BASE_IDX 3 16416#define mmABM4_DC_ABM1_HG_RESULT_11 0x0fac 16417#define mmABM4_DC_ABM1_HG_RESULT_11_BASE_IDX 3 16418#define mmABM4_DC_ABM1_HG_RESULT_12 0x0fad 16419#define mmABM4_DC_ABM1_HG_RESULT_12_BASE_IDX 3 16420#define mmABM4_DC_ABM1_HG_RESULT_13 0x0fae 16421#define mmABM4_DC_ABM1_HG_RESULT_13_BASE_IDX 3 16422#define mmABM4_DC_ABM1_HG_RESULT_14 0x0faf 16423#define mmABM4_DC_ABM1_HG_RESULT_14_BASE_IDX 3 16424#define mmABM4_DC_ABM1_HG_RESULT_15 0x0fb0 16425#define mmABM4_DC_ABM1_HG_RESULT_15_BASE_IDX 3 16426#define mmABM4_DC_ABM1_HG_RESULT_16 0x0fb1 16427#define mmABM4_DC_ABM1_HG_RESULT_16_BASE_IDX 3 16428#define mmABM4_DC_ABM1_HG_RESULT_17 0x0fb2 16429#define mmABM4_DC_ABM1_HG_RESULT_17_BASE_IDX 3 16430#define mmABM4_DC_ABM1_HG_RESULT_18 0x0fb3 16431#define mmABM4_DC_ABM1_HG_RESULT_18_BASE_IDX 3 16432#define mmABM4_DC_ABM1_HG_RESULT_19 0x0fb4 16433#define mmABM4_DC_ABM1_HG_RESULT_19_BASE_IDX 3 16434#define mmABM4_DC_ABM1_HG_RESULT_20 0x0fb5 16435#define mmABM4_DC_ABM1_HG_RESULT_20_BASE_IDX 3 16436#define mmABM4_DC_ABM1_HG_RESULT_21 0x0fb6 16437#define mmABM4_DC_ABM1_HG_RESULT_21_BASE_IDX 3 16438#define mmABM4_DC_ABM1_HG_RESULT_22 0x0fb7 16439#define mmABM4_DC_ABM1_HG_RESULT_22_BASE_IDX 3 16440#define mmABM4_DC_ABM1_HG_RESULT_23 0x0fb8 16441#define mmABM4_DC_ABM1_HG_RESULT_23_BASE_IDX 3 16442#define mmABM4_DC_ABM1_HG_RESULT_24 0x0fb9 16443#define mmABM4_DC_ABM1_HG_RESULT_24_BASE_IDX 3 16444#define mmABM4_DC_ABM1_BL_MASTER_LOCK 0x0fba 16445#define mmABM4_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 16446 16447 16448// addressBlock: dce_dc_opp_abm5_dispdec 16449// base address: 0x514 16450#define mmABM5_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0fbf 16451#define mmABM5_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 16452#define mmABM5_BL1_PWM_USER_LEVEL 0x0fc0 16453#define mmABM5_BL1_PWM_USER_LEVEL_BASE_IDX 3 16454#define mmABM5_BL1_PWM_TARGET_ABM_LEVEL 0x0fc1 16455#define mmABM5_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 16456#define mmABM5_BL1_PWM_CURRENT_ABM_LEVEL 0x0fc2 16457#define mmABM5_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 16458#define mmABM5_BL1_PWM_FINAL_DUTY_CYCLE 0x0fc3 16459#define mmABM5_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 16460#define mmABM5_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0fc4 16461#define mmABM5_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 16462#define mmABM5_BL1_PWM_ABM_CNTL 0x0fc5 16463#define mmABM5_BL1_PWM_ABM_CNTL_BASE_IDX 3 16464#define mmABM5_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0fc6 16465#define mmABM5_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 16466#define mmABM5_BL1_PWM_GRP2_REG_LOCK 0x0fc7 16467#define mmABM5_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 16468#define mmABM5_DC_ABM1_CNTL 0x0fc8 16469#define mmABM5_DC_ABM1_CNTL_BASE_IDX 3 16470#define mmABM5_DC_ABM1_IPCSC_COEFF_SEL 0x0fc9 16471#define mmABM5_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 16472#define mmABM5_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0fca 16473#define mmABM5_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 16474#define mmABM5_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0fcb 16475#define mmABM5_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 16476#define mmABM5_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0fcc 16477#define mmABM5_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 16478#define mmABM5_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0fcd 16479#define mmABM5_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 16480#define mmABM5_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0fce 16481#define mmABM5_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 16482#define mmABM5_DC_ABM1_ACE_THRES_12 0x0fcf 16483#define mmABM5_DC_ABM1_ACE_THRES_12_BASE_IDX 3 16484#define mmABM5_DC_ABM1_ACE_THRES_34 0x0fd0 16485#define mmABM5_DC_ABM1_ACE_THRES_34_BASE_IDX 3 16486#define mmABM5_DC_ABM1_ACE_CNTL_MISC 0x0fd1 16487#define mmABM5_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 16488#define mmABM5_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0fd3 16489#define mmABM5_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 16490#define mmABM5_DC_ABM1_HG_MISC_CTRL 0x0fd4 16491#define mmABM5_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 16492#define mmABM5_DC_ABM1_LS_SUM_OF_LUMA 0x0fd5 16493#define mmABM5_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 16494#define mmABM5_DC_ABM1_LS_MIN_MAX_LUMA 0x0fd6 16495#define mmABM5_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 16496#define mmABM5_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0fd7 16497#define mmABM5_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 16498#define mmABM5_DC_ABM1_LS_PIXEL_COUNT 0x0fd8 16499#define mmABM5_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 16500#define mmABM5_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0fd9 16501#define mmABM5_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 16502#define mmABM5_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0fda 16503#define mmABM5_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 16504#define mmABM5_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0fdb 16505#define mmABM5_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 16506#define mmABM5_DC_ABM1_HG_SAMPLE_RATE 0x0fdc 16507#define mmABM5_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 16508#define mmABM5_DC_ABM1_LS_SAMPLE_RATE 0x0fdd 16509#define mmABM5_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 16510#define mmABM5_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0fde 16511#define mmABM5_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 16512#define mmABM5_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0fdf 16513#define mmABM5_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 16514#define mmABM5_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0fe0 16515#define mmABM5_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 16516#define mmABM5_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0fe1 16517#define mmABM5_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 16518#define mmABM5_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0fe2 16519#define mmABM5_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 16520#define mmABM5_DC_ABM1_HG_RESULT_1 0x0fe3 16521#define mmABM5_DC_ABM1_HG_RESULT_1_BASE_IDX 3 16522#define mmABM5_DC_ABM1_HG_RESULT_2 0x0fe4 16523#define mmABM5_DC_ABM1_HG_RESULT_2_BASE_IDX 3 16524#define mmABM5_DC_ABM1_HG_RESULT_3 0x0fe5 16525#define mmABM5_DC_ABM1_HG_RESULT_3_BASE_IDX 3 16526#define mmABM5_DC_ABM1_HG_RESULT_4 0x0fe6 16527#define mmABM5_DC_ABM1_HG_RESULT_4_BASE_IDX 3 16528#define mmABM5_DC_ABM1_HG_RESULT_5 0x0fe7 16529#define mmABM5_DC_ABM1_HG_RESULT_5_BASE_IDX 3 16530#define mmABM5_DC_ABM1_HG_RESULT_6 0x0fe8 16531#define mmABM5_DC_ABM1_HG_RESULT_6_BASE_IDX 3 16532#define mmABM5_DC_ABM1_HG_RESULT_7 0x0fe9 16533#define mmABM5_DC_ABM1_HG_RESULT_7_BASE_IDX 3 16534#define mmABM5_DC_ABM1_HG_RESULT_8 0x0fea 16535#define mmABM5_DC_ABM1_HG_RESULT_8_BASE_IDX 3 16536#define mmABM5_DC_ABM1_HG_RESULT_9 0x0feb 16537#define mmABM5_DC_ABM1_HG_RESULT_9_BASE_IDX 3 16538#define mmABM5_DC_ABM1_HG_RESULT_10 0x0fec 16539#define mmABM5_DC_ABM1_HG_RESULT_10_BASE_IDX 3 16540#define mmABM5_DC_ABM1_HG_RESULT_11 0x0fed 16541#define mmABM5_DC_ABM1_HG_RESULT_11_BASE_IDX 3 16542#define mmABM5_DC_ABM1_HG_RESULT_12 0x0fee 16543#define mmABM5_DC_ABM1_HG_RESULT_12_BASE_IDX 3 16544#define mmABM5_DC_ABM1_HG_RESULT_13 0x0fef 16545#define mmABM5_DC_ABM1_HG_RESULT_13_BASE_IDX 3 16546#define mmABM5_DC_ABM1_HG_RESULT_14 0x0ff0 16547#define mmABM5_DC_ABM1_HG_RESULT_14_BASE_IDX 3 16548#define mmABM5_DC_ABM1_HG_RESULT_15 0x0ff1 16549#define mmABM5_DC_ABM1_HG_RESULT_15_BASE_IDX 3 16550#define mmABM5_DC_ABM1_HG_RESULT_16 0x0ff2 16551#define mmABM5_DC_ABM1_HG_RESULT_16_BASE_IDX 3 16552#define mmABM5_DC_ABM1_HG_RESULT_17 0x0ff3 16553#define mmABM5_DC_ABM1_HG_RESULT_17_BASE_IDX 3 16554#define mmABM5_DC_ABM1_HG_RESULT_18 0x0ff4 16555#define mmABM5_DC_ABM1_HG_RESULT_18_BASE_IDX 3 16556#define mmABM5_DC_ABM1_HG_RESULT_19 0x0ff5 16557#define mmABM5_DC_ABM1_HG_RESULT_19_BASE_IDX 3 16558#define mmABM5_DC_ABM1_HG_RESULT_20 0x0ff6 16559#define mmABM5_DC_ABM1_HG_RESULT_20_BASE_IDX 3 16560#define mmABM5_DC_ABM1_HG_RESULT_21 0x0ff7 16561#define mmABM5_DC_ABM1_HG_RESULT_21_BASE_IDX 3 16562#define mmABM5_DC_ABM1_HG_RESULT_22 0x0ff8 16563#define mmABM5_DC_ABM1_HG_RESULT_22_BASE_IDX 3 16564#define mmABM5_DC_ABM1_HG_RESULT_23 0x0ff9 16565#define mmABM5_DC_ABM1_HG_RESULT_23_BASE_IDX 3 16566#define mmABM5_DC_ABM1_HG_RESULT_24 0x0ffa 16567#define mmABM5_DC_ABM1_HG_RESULT_24_BASE_IDX 3 16568#define mmABM5_DC_ABM1_BL_MASTER_LOCK 0x0ffb 16569#define mmABM5_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 16570 16571 16572// addressBlock: dce_dc_hda_azcontroller_azdec 16573// base address: 0x0 16574#define mmCORB_WRITE_POINTER 0x0000 16575#define mmCORB_WRITE_POINTER_BASE_IDX 0 16576#define mmCORB_READ_POINTER 0x0000 16577#define mmCORB_READ_POINTER_BASE_IDX 0 16578#define mmCORB_CONTROL 0x0001 16579#define mmCORB_CONTROL_BASE_IDX 0 16580#define mmCORB_STATUS 0x0001 16581#define mmCORB_STATUS_BASE_IDX 0 16582#define mmCORB_SIZE 0x0001 16583#define mmCORB_SIZE_BASE_IDX 0 16584#define mmRIRB_LOWER_BASE_ADDRESS 0x0002 16585#define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX 0 16586#define mmRIRB_UPPER_BASE_ADDRESS 0x0003 16587#define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX 0 16588#define mmRIRB_WRITE_POINTER 0x0004 16589#define mmRIRB_WRITE_POINTER_BASE_IDX 0 16590#define mmRESPONSE_INTERRUPT_COUNT 0x0004 16591#define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX 0 16592#define mmRIRB_CONTROL 0x0005 16593#define mmRIRB_CONTROL_BASE_IDX 0 16594#define mmRIRB_STATUS 0x0005 16595#define mmRIRB_STATUS_BASE_IDX 0 16596#define mmRIRB_SIZE 0x0005 16597#define mmRIRB_SIZE_BASE_IDX 0 16598#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006 16599#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0 16600#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 16601#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 16602#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 16603#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 16604#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007 16605#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0 16606#define mmIMMEDIATE_COMMAND_STATUS 0x0008 16607#define mmIMMEDIATE_COMMAND_STATUS_BASE_IDX 0 16608#define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x000a 16609#define mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0 16610#define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x000b 16611#define mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0 16612#define mmWALL_CLOCK_COUNTER_ALIAS 0x074c 16613#define mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1 16614 16615 16616// addressBlock: dce_dc_hda_azendpoint_azdec 16617// base address: 0x0 16618#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 16619#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 16620#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 16621#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 16622 16623 16624// addressBlock: dce_dc_hda_azinputendpoint_azdec 16625// base address: 0x0 16626#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006 16627#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0 16628#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006 16629#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0 16630 16631 16632 16633// addressBlock: vga_vgaseqind 16634// base address: 0x0 16635#define ixSEQ00 0x0000 16636#define ixSEQ01 0x0001 16637#define ixSEQ02 0x0002 16638#define ixSEQ03 0x0003 16639#define ixSEQ04 0x0004 16640 16641 16642// addressBlock: vga_vgacrtind 16643// base address: 0x0 16644#define ixCRT00 0x0000 16645#define ixCRT01 0x0001 16646#define ixCRT02 0x0002 16647#define ixCRT03 0x0003 16648#define ixCRT04 0x0004 16649#define ixCRT05 0x0005 16650#define ixCRT06 0x0006 16651#define ixCRT07 0x0007 16652#define ixCRT08 0x0008 16653#define ixCRT09 0x0009 16654#define ixCRT0A 0x000a 16655#define ixCRT0B 0x000b 16656#define ixCRT0C 0x000c 16657#define ixCRT0D 0x000d 16658#define ixCRT0E 0x000e 16659#define ixCRT0F 0x000f 16660#define ixCRT10 0x0010 16661#define ixCRT11 0x0011 16662#define ixCRT12 0x0012 16663#define ixCRT13 0x0013 16664#define ixCRT14 0x0014 16665#define ixCRT15 0x0015 16666#define ixCRT16 0x0016 16667#define ixCRT17 0x0017 16668#define ixCRT18 0x0018 16669#define ixCRT1E 0x001e 16670#define ixCRT1F 0x001f 16671#define ixCRT22 0x0022 16672 16673 16674// addressBlock: vga_vgagrphind 16675// base address: 0x0 16676#define ixGRA00 0x0000 16677#define ixGRA01 0x0001 16678#define ixGRA02 0x0002 16679#define ixGRA03 0x0003 16680#define ixGRA04 0x0004 16681#define ixGRA05 0x0005 16682#define ixGRA06 0x0006 16683#define ixGRA07 0x0007 16684#define ixGRA08 0x0008 16685 16686 16687// addressBlock: vga_vgaattrind 16688// base address: 0x0 16689#define ixATTR00 0x0000 16690#define ixATTR01 0x0001 16691#define ixATTR02 0x0002 16692#define ixATTR03 0x0003 16693#define ixATTR04 0x0004 16694#define ixATTR05 0x0005 16695#define ixATTR06 0x0006 16696#define ixATTR07 0x0007 16697#define ixATTR08 0x0008 16698#define ixATTR09 0x0009 16699#define ixATTR0A 0x000a 16700#define ixATTR0B 0x000b 16701#define ixATTR0C 0x000c 16702#define ixATTR0D 0x000d 16703#define ixATTR0E 0x000e 16704#define ixATTR0F 0x000f 16705#define ixATTR10 0x0010 16706#define ixATTR11 0x0011 16707#define ixATTR12 0x0012 16708#define ixATTR13 0x0013 16709#define ixATTR14 0x0014 16710 16711 16712// addressBlock: azendpoint_f2codecind 16713// base address: 0x0 16714#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 16715#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 16716#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d 16717#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e 16718#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 16719#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e 16720#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 16721#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 16722#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 16723#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a 16724#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b 16725#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 16726#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 16727#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 16728#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 16729#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c 16730#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d 16731#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e 16732#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f 16733#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 16734#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 16735#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 16736#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 16737#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 16738#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 16739#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 16740#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 16741#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a 16742#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b 16743#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c 16744#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 16745#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 16746#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 16747#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 16748#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 16749#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 16750#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 16751#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a 16752#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b 16753#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c 16754#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d 16755#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e 16756#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f 16757#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 16758#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 16759#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 16760#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 16761#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 16762#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 16763#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 16764#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a 16765#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b 16766#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c 16767#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d 16768#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e 16769#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 16770#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c 16771#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e 16772 16773 16774// addressBlock: azendpoint_descriptorind 16775// base address: 0x0 16776#define ixAUDIO_DESCRIPTOR0 0x0001 16777#define ixAUDIO_DESCRIPTOR1 0x0002 16778#define ixAUDIO_DESCRIPTOR2 0x0003 16779#define ixAUDIO_DESCRIPTOR3 0x0004 16780#define ixAUDIO_DESCRIPTOR4 0x0005 16781#define ixAUDIO_DESCRIPTOR5 0x0006 16782#define ixAUDIO_DESCRIPTOR6 0x0007 16783#define ixAUDIO_DESCRIPTOR7 0x0008 16784#define ixAUDIO_DESCRIPTOR8 0x0009 16785#define ixAUDIO_DESCRIPTOR9 0x000a 16786#define ixAUDIO_DESCRIPTOR10 0x000b 16787#define ixAUDIO_DESCRIPTOR11 0x000c 16788#define ixAUDIO_DESCRIPTOR12 0x000d 16789#define ixAUDIO_DESCRIPTOR13 0x000e 16790 16791 16792// addressBlock: azendpoint_sinkinfoind 16793// base address: 0x0 16794#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 16795#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 16796#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 16797#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 16798#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 16799#define ixSINK_DESCRIPTION0 0x0005 16800#define ixSINK_DESCRIPTION1 0x0006 16801#define ixSINK_DESCRIPTION2 0x0007 16802#define ixSINK_DESCRIPTION3 0x0008 16803#define ixSINK_DESCRIPTION4 0x0009 16804#define ixSINK_DESCRIPTION5 0x000a 16805#define ixSINK_DESCRIPTION6 0x000b 16806#define ixSINK_DESCRIPTION7 0x000c 16807#define ixSINK_DESCRIPTION8 0x000d 16808#define ixSINK_DESCRIPTION9 0x000e 16809#define ixSINK_DESCRIPTION10 0x000f 16810#define ixSINK_DESCRIPTION11 0x0010 16811#define ixSINK_DESCRIPTION12 0x0011 16812#define ixSINK_DESCRIPTION13 0x0012 16813#define ixSINK_DESCRIPTION14 0x0013 16814#define ixSINK_DESCRIPTION15 0x0014 16815#define ixSINK_DESCRIPTION16 0x0015 16816#define ixSINK_DESCRIPTION17 0x0016 16817 16818 16819// addressBlock: azf0controller_azinputcrc0resultind 16820// base address: 0x0 16821#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000 16822#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001 16823#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002 16824#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003 16825#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004 16826#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005 16827#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006 16828#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007 16829 16830 16831// addressBlock: azf0controller_azinputcrc1resultind 16832// base address: 0x0 16833#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000 16834#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001 16835#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002 16836#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003 16837#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004 16838#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005 16839#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006 16840#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007 16841 16842 16843// addressBlock: azf0controller_azcrc0resultind 16844// base address: 0x0 16845#define ixAZALIA_CRC0_CHANNEL0 0x0000 16846#define ixAZALIA_CRC0_CHANNEL1 0x0001 16847#define ixAZALIA_CRC0_CHANNEL2 0x0002 16848#define ixAZALIA_CRC0_CHANNEL3 0x0003 16849#define ixAZALIA_CRC0_CHANNEL4 0x0004 16850#define ixAZALIA_CRC0_CHANNEL5 0x0005 16851#define ixAZALIA_CRC0_CHANNEL6 0x0006 16852#define ixAZALIA_CRC0_CHANNEL7 0x0007 16853 16854 16855// addressBlock: azf0controller_azcrc1resultind 16856// base address: 0x0 16857#define ixAZALIA_CRC1_CHANNEL0 0x0000 16858#define ixAZALIA_CRC1_CHANNEL1 0x0001 16859#define ixAZALIA_CRC1_CHANNEL2 0x0002 16860#define ixAZALIA_CRC1_CHANNEL3 0x0003 16861#define ixAZALIA_CRC1_CHANNEL4 0x0004 16862#define ixAZALIA_CRC1_CHANNEL5 0x0005 16863#define ixAZALIA_CRC1_CHANNEL6 0x0006 16864#define ixAZALIA_CRC1_CHANNEL7 0x0007 16865 16866 16867// addressBlock: azinputendpoint_f2codecind 16868// base address: 0x0 16869#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 16870#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 16871#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d 16872#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 16873#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a 16874#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b 16875#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 16876#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 16877#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 16878#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c 16879#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d 16880#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e 16881#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f 16882#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 16883#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 16884#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 16885#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 16886#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a 16887#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c 16888#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 16889#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 16890#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 16891#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 16892#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 16893#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 16894#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a 16895#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b 16896#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c 16897#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d 16898#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e 16899#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 16900#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c 16901 16902 16903// addressBlock: azroot_f2codecind 16904// base address: 0x0 16905#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00 16906#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02 16907#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04 16908#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 16909#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 16910#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 16911#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 16912#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 16913#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 16914#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff 16915#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 16916#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 16917#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a 16918#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b 16919#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f 16920 16921 16922// addressBlock: azf0stream0_streamind 16923// base address: 0x0 16924#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000 16925#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 16926#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 16927#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 16928#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 16929 16930 16931// addressBlock: azf0stream1_streamind 16932// base address: 0x0 16933#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000 16934#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 16935#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 16936#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 16937#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 16938 16939 16940// addressBlock: azf0stream2_streamind 16941// base address: 0x0 16942#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000 16943#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 16944#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 16945#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 16946#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 16947 16948 16949// addressBlock: azf0stream3_streamind 16950// base address: 0x0 16951#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000 16952#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 16953#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 16954#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 16955#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 16956 16957// addressBlock: azf0stream4_streamind 16958// base address: 0x0 16959#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000 16960#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 16961#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 16962#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 16963#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 16964 16965 16966// addressBlock: azf0stream5_streamind 16967// base address: 0x0 16968#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000 16969#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 16970#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 16971#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 16972#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 16973 16974 16975// addressBlock: azf0stream6_streamind 16976// base address: 0x0 16977#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000 16978#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 16979#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 16980#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 16981#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 16982 16983 16984// addressBlock: azf0stream7_streamind 16985// base address: 0x0 16986#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000 16987#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 16988#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 16989#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 16990#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 16991 16992 16993// addressBlock: azf0stream8_streamind 16994// base address: 0x0 16995#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000 16996#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 16997#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 16998#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 16999#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 17000
17001 17002// addressBlock: azf0stream9_streamind 17003// base address: 0x0 17004#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000 17005#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 17006#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 17007#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 17008#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 17009 17010 17011// addressBlock: azf0stream10_streamind 17012// base address: 0x0 17013#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000 17014#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 17015#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 17016#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 17017#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 17018 17019 17020// addressBlock: azf0stream11_streamind 17021// base address: 0x0 17022#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000 17023#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 17024#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 17025#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 17026#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 17027 17028 17029// addressBlock: azf0stream12_streamind 17030// base address: 0x0 17031#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000 17032#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 17033#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 17034#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 17035#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 17036 17037 17038// addressBlock: azf0stream13_streamind 17039// base address: 0x0 17040#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000 17041#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 17042#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 17043#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 17044#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 17045 17046 17047// addressBlock: azf0stream14_streamind 17048// base address: 0x0 17049#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000 17050#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 17051#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 17052#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 17053#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 17054 17055 17056// addressBlock: azf0stream15_streamind 17057// base address: 0x0 17058#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000 17059#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 17060#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 17061#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 17062#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 17063 17064 17065// addressBlock: azf0endpoint0_endpointind 17066// base address: 0x0 17067#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17068#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17069#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17070#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17071#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17072#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17073#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 17074#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 17075#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 17076#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 17077#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 17078#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 17079#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17080#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 17081#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17082#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 17083#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 17084#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 17085#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 17086#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 17087#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 17088#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 17089#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 17090#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 17091#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 17092#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 17093#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 17094#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 17095#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 17096#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 17097#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 17098#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 17099#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17100#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 17101#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 17102#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 17103#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 17104#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 17105#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 17106#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 17107#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 17108#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 17109#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 17110#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 17111#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17112#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17113#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17114#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 17115#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 17116#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 17117#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 17118#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 17119#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 17120#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 17121#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 17122#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 17123#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 17124#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 17125#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 17126#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 17127#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17128#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 17129#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17130#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 17131#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 17132#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 17133#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 17134#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 17135#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 17136#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 17137#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 17138 17139 17140// addressBlock: azf0endpoint1_endpointind 17141// base address: 0x0 17142#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17143#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17144#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17145#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17146#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17147#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17148#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 17149#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 17150#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 17151#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 17152#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 17153#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 17154#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17155#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 17156#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17157#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 17158#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 17159#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 17160#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 17161#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 17162#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 17163#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 17164#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 17165#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 17166#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 17167#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 17168#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 17169#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 17170#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 17171#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 17172#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 17173#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 17174#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17175#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 17176#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 17177#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 17178#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 17179#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 17180#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 17181#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 17182#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 17183#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 17184#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 17185#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 17186#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17187#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17188#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17189#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 17190#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 17191#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 17192#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 17193#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 17194#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 17195#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 17196#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 17197#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 17198#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 17199#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 17200#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 17201#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 17202#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17203#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 17204#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17205#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 17206#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 17207#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 17208#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 17209#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 17210#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 17211#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 17212#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 17213 17214 17215// addressBlock: azf0endpoint2_endpointind 17216// base address: 0x0 17217#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17218#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17219#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17220#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17221#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17222#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17223#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 17224#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 17225#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 17226#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 17227#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 17228#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 17229#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17230#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 17231#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17232#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 17233#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 17234#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 17235#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 17236#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 17237#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 17238#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 17239#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 17240#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 17241#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 17242#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 17243#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 17244#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 17245#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 17246#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 17247#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 17248#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 17249#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17250#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 17251#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 17252#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 17253#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 17254#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 17255#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 17256#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 17257#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 17258#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 17259#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 17260#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 17261#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17262#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17263#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17264#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 17265#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 17266#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 17267#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 17268#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 17269#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 17270#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 17271#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 17272#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 17273#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 17274#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 17275#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 17276#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 17277#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17278#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 17279#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17280#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 17281#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 17282#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 17283#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 17284#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 17285#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 17286#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 17287#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 17288 17289 17290// addressBlock: azf0endpoint3_endpointind 17291// base address: 0x0 17292#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17293#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17294#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17295#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17296#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17297#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17298#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 17299#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 17300#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 17301#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 17302#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 17303#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 17304#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17305#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 17306#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17307#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 17308#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 17309#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 17310#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 17311#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 17312#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 17313#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 17314#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 17315#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 17316#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 17317#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 17318#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 17319#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 17320#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 17321#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 17322#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 17323#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 17324#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17325#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 17326#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 17327#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 17328#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 17329#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 17330#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 17331#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 17332#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 17333#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 17334#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 17335#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 17336#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17337#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17338#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17339#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 17340#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 17341#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 17342#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 17343#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 17344#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 17345#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 17346#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 17347#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 17348#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 17349#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 17350#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 17351#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 17352#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17353#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 17354#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17355#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 17356#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 17357#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 17358#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 17359#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 17360#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 17361#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 17362#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 17363 17364 17365// addressBlock: azf0endpoint4_endpointind 17366// base address: 0x0 17367#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17368#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17369#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17370#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17371#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17372#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17373#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 17374#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 17375#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 17376#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 17377#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 17378#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 17379#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17380#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 17381#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17382#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 17383#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 17384#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 17385#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 17386#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 17387#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 17388#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 17389#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 17390#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 17391#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 17392#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 17393#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 17394#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 17395#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 17396#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 17397#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 17398#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 17399#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17400#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 17401#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 17402#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 17403#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 17404#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 17405#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 17406#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 17407#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 17408#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 17409#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 17410#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 17411#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17412#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17413#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17414#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 17415#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 17416#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 17417#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 17418#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 17419#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 17420#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 17421#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 17422#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 17423#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 17424#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 17425#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 17426#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 17427#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17428#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 17429#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17430#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 17431#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 17432#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 17433#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 17434#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 17435#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 17436#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 17437#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 17438 17439 17440// addressBlock: azf0endpoint5_endpointind 17441// base address: 0x0 17442#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17443#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17444#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17445#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17446#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17447#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17448#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 17449#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 17450#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 17451#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 17452#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 17453#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 17454#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17455#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 17456#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17457#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 17458#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 17459#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 17460#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 17461#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 17462#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 17463#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 17464#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 17465#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 17466#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 17467#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 17468#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 17469#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 17470#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 17471#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 17472#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 17473#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 17474#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17475#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 17476#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 17477#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 17478#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 17479#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 17480#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 17481#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 17482#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 17483#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 17484#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 17485#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 17486#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17487#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17488#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17489#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 17490#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 17491#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 17492#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 17493#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 17494#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 17495#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 17496#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 17497#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 17498#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 17499#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 17500#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 17501#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 17502#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17503#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 17504#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17505#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 17506#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 17507#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 17508#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 17509#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 17510#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 17511#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 17512#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 17513 17514 17515// addressBlock: azf0endpoint6_endpointind 17516// base address: 0x0 17517#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17518#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17519#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17520#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17521#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17522#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17523#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 17524#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 17525#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 17526#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 17527#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 17528#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 17529#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17530#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 17531#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17532#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 17533#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 17534#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 17535#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 17536#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 17537#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 17538#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 17539#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 17540#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 17541#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 17542#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 17543#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 17544#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 17545#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 17546#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 17547#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 17548#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 17549#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17550#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 17551#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 17552#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 17553#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 17554#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 17555#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 17556#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 17557#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 17558#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 17559#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 17560#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 17561#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17562#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17563#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17564#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 17565#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 17566#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 17567#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 17568#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 17569#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 17570#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 17571#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 17572#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 17573#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 17574#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 17575#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 17576#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 17577#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17578#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 17579#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17580#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 17581#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 17582#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 17583#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 17584#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 17585#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 17586#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 17587#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 17588 17589 17590// addressBlock: azf0endpoint7_endpointind 17591// base address: 0x0 17592#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17593#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17594#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17595#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17596#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17597#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17598#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 17599#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 17600#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 17601#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 17602#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 17603#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 17604#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17605#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 17606#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17607#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 17608#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 17609#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 17610#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 17611#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 17612#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 17613#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 17614#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 17615#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 17616#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 17617#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 17618#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 17619#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 17620#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 17621#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 17622#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 17623#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 17624#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17625#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 17626#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 17627#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 17628#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 17629#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 17630#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 17631#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 17632#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 17633#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 17634#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 17635#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 17636#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17637#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17638#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17639#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 17640#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 17641#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 17642#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 17643#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 17644#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 17645#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 17646#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 17647#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 17648#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 17649#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 17650#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 17651#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 17652#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17653#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 17654#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17655#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 17656#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 17657#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 17658#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 17659#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 17660#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 17661#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 17662#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 17663 17664 17665// addressBlock: azf0inputendpoint0_inputendpointind 17666// base address: 0x0 17667#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17668#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17669#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17670#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17671#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17672#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17673#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17674#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 17675#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17676#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 17677#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 17678#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17679#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 17680#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 17681#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 17682#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17683#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17684#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17685#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17686#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 17687#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17688#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 17689#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 17690 17691 17692// addressBlock: azf0inputendpoint1_inputendpointind 17693// base address: 0x0 17694#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17695#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17696#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17697#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17698#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17699#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17700#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17701#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 17702#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17703#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 17704#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 17705#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17706#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 17707#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 17708#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 17709#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17710#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17711#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17712#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17713#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 17714#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17715#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 17716#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 17717 17718 17719// addressBlock: azf0inputendpoint2_inputendpointind 17720// base address: 0x0 17721#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17722#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17723#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17724#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17725#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17726#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17727#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17728#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 17729#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17730#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 17731#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 17732#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17733#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 17734#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 17735#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 17736#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17737#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17738#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17739#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17740#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 17741#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17742#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 17743#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 17744 17745 17746// addressBlock: azf0inputendpoint3_inputendpointind 17747// base address: 0x0 17748#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17749#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17750#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17751#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17752#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17753#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17754#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17755#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 17756#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17757#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 17758#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 17759#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17760#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 17761#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 17762#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 17763#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17764#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17765#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17766#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17767#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 17768#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17769#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 17770#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 17771 17772 17773// addressBlock: azf0inputendpoint4_inputendpointind 17774// base address: 0x0 17775#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17776#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17777#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17778#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17779#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17780#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17781#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17782#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 17783#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17784#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 17785#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 17786#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17787#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 17788#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 17789#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 17790#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17791#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17792#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17793#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17794#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 17795#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17796#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 17797#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 17798 17799 17800// addressBlock: azf0inputendpoint5_inputendpointind 17801// base address: 0x0 17802#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17803#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17804#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17805#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17806#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17807#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17808#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17809#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 17810#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17811#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 17812#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 17813#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17814#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 17815#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 17816#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 17817#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17818#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17819#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17820#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17821#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 17822#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17823#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 17824#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 17825 17826 17827// addressBlock: azf0inputendpoint6_inputendpointind 17828// base address: 0x0 17829#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17830#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17831#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17832#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17833#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17834#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17835#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17836#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 17837#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17838#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 17839#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 17840#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17841#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 17842#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 17843#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 17844#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17845#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17846#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17847#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17848#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 17849#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17850#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 17851#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 17852 17853 17854// addressBlock: azf0inputendpoint7_inputendpointind 17855// base address: 0x0 17856#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17857#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17858#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17859#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17860#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17861#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17862#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17863#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 17864#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17865#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 17866#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 17867#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17868#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 17869#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 17870#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 17871#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17872#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17873#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17874#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17875#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 17876#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17877#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 17878#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 17879 17880#endif 17881