1/* 2 * SMU_7_1_2 Register documentation 3 * 4 * Copyright (C) 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24#ifndef SMU_7_1_2_SH_MASK_H 25#define SMU_7_1_2_SH_MASK_H 26 27#define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 28#define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 29#define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 30#define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 31#define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f 32#define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0 33#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100 34#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8 35#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200 36#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9 37#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 38#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa 39#define CG_DCLK_STATUS__DCLK_STATUS_MASK 0x1 40#define CG_DCLK_STATUS__DCLK_STATUS__SHIFT 0x0 41#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK 0x2 42#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT 0x1 43#define CG_VCLK_CNTL__VCLK_DIVIDER_MASK 0x7f 44#define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT 0x0 45#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100 46#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8 47#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK 0x200 48#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT 0x9 49#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 50#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa 51#define CG_VCLK_STATUS__VCLK_STATUS_MASK 0x1 52#define CG_VCLK_STATUS__VCLK_STATUS__SHIFT 0x0 53#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK 0x2 54#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT 0x1 55#define CG_ECLK_CNTL__ECLK_DIVIDER_MASK 0x7f 56#define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT 0x0 57#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100 58#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8 59#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK 0x200 60#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT 0x9 61#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 62#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa 63#define CG_ECLK_STATUS__ECLK_STATUS_MASK 0x1 64#define CG_ECLK_STATUS__ECLK_STATUS__SHIFT 0x0 65#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK 0x2 66#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT 0x1 67#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x7f 68#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x0 69#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100 70#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8 71#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK 0x200 72#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT 0x9 73#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 74#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa 75#define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK 0x1 76#define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT 0x0 77#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK 0x2 78#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT 0x1 79#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK 0x4 80#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT 0x2 81#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8 82#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT 0x3 83#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10 84#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT 0x4 85#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK 0x20 86#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT 0x5 87#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK 0x40 88#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT 0x6 89#define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80 90#define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT 0x7 91#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100 92#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8 93#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK 0x200 94#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT 0x9 95#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK 0x400 96#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa 97#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800 98#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT 0xb 99#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK 0x1000 100#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT 0xc 101#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1 102#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x0 103#define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK 0x2 104#define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT 0x1 105#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x4 106#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x2 107#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8 108#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x3 109#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10 110#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT 0x4 111#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x7e0 112#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5 113#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800 114#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT 0xb 115#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK 0x1000 116#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT 0xc 117#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x7f00000 118#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x14 119#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK_MASK 0x8000000 120#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK__SHIFT 0x1b 121#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK 0x10000000 122#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT 0x1c 123#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x1ff 124#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x0 125#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800 126#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT 0xb 127#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK 0x400000 128#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT 0x16 129#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x800000 130#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x17 131#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK 0x1000000 132#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT 0x18 133#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK 0x2000000 134#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT 0x19 135#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x4000000 136#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x1a 137#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK 0x8000000 138#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT 0x1b 139#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK 0x10000000 140#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT 0x1c 141#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK 0x40000000 142#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT 0x1e 143#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x3ffffff 144#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0 145#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000 146#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x1c 147#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK 0xf 148#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT 0x0 149#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK 0x60 150#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT 0x5 151#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK 0x180 152#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT 0x7 153#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK 0x7fe00 154#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT 0x9 155#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x200000 156#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x15 157#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK 0x800000 158#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT 0x17 159#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK 0x1000000 160#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT 0x18 161#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK 0x2000000 162#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT 0x19 163#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK 0xc000000 164#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT 0x1a 165#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK 0x70000000 166#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT 0x1c 167#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK 0x80000000 168#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT 0x1f 169#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x1 170#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x0 171#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2 172#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x1 173#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0xc 174#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x2 175#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x30 176#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x4 177#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0xc0 178#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x6 179#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100 180#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8 181#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x200 182#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x9 183#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK 0xff 184#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT 0x0 185#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK 0xff00 186#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8 187#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK 0x10000 188#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10 189#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK 0x1e0000 190#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT 0x11 191#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK 0x1e00000 192#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT 0x15 193#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK 0xfe000000 194#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19 195#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff 196#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0 197#define CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK 0x2 198#define CG_SPLL_STATUS__SPLL_CHG_STATUS__SHIFT 0x1 199#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1 200#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0 201#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2 202#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x1 203#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x4 204#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x2 205#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8 206#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x3 207#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10 208#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x4 209#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0xc00 210#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0xa 211#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0xff000 212#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0xc 213#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000 214#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x1c 215#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000 216#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x1d 217#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x1 218#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x0 219#define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK 0xfff0 220#define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x4 221#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x3ffffff 222#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x0 223#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00 224#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x8 225#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x2 226#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x1 227#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4 228#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x2 229#define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK 0x1 230#define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT 0x0 231#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x8 232#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x3 233#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100 234#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x8 235#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK 0x4000 236#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT 0xe 237#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK 0x8000 238#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT 0xf 239#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK 0x10000 240#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10 241#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK 0x20000 242#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT 0x11 243#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK 0x40000 244#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT 0x12 245#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK 0x80000 246#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT 0x13 247#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK 0x100000 248#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT 0x14 249#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK 0x200000 250#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT 0x15 251#define CG_CLKPIN_CNTL_2__CML_CTRL_MASK 0xc00000 252#define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT 0x16 253#define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK 0xff000000 254#define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT 0x18 255#define CG_CLKPIN_CNTL_DC__OSC_EN_MASK 0x1 256#define CG_CLKPIN_CNTL_DC__OSC_EN__SHIFT 0x0 257#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN_MASK 0x6 258#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN__SHIFT 0x1 259#define CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK 0x1c00 260#define CG_CLKPIN_CNTL_DC__XTALIN_SEL__SHIFT 0xa 261#define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff 262#define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0 263#define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00 264#define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8 265#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK 0x10000 266#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10 267#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK 0xff 268#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT 0x0 269#define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00 270#define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8 271#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000 272#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10 273#define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK 0x1f 274#define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0 275#define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK 0x3e0 276#define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x5 277#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00 278#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa 279#define GCK_PLL_TEST_CNTL__TST_RESET_MASK 0x20000 280#define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT 0x11 281#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK 0x40000 282#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12 283#define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK 0xfffe0000 284#define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11 285#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK 0x7 286#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT 0x0 287#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK 0x38 288#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT 0x3 289#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK 0x1c0 290#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT 0x6 291#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK 0xe00 292#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT 0x9 293#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK 0x7000 294#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT 0xc 295#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK 0x38000 296#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT 0xf 297#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK 0x1c0000 298#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT 0x12 299#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK 0xe00000 300#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT 0x15 301#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK 0x7000000 302#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT 0x18 303#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK 0x38000000 304#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT 0x1b 305#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 306#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 307#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 308#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 309#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff 310#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0 311#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff 312#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0 313#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff 314#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0 315#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff 316#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0 317#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff 318#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0 319#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff 320#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0 321#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff 322#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0 323#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff 324#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0 325#define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff 326#define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0 327#define SMC_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff 328#define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0 329#define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff 330#define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0 331#define SMC_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff 332#define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0 333#define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff 334#define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0 335#define SMC_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff 336#define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0 337#define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff 338#define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0 339#define SMC_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff 340#define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0 341#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1 342#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0 343#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2 344#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1 345#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4 346#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2 347#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8 348#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3 349#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10 350#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4 351#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20 352#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5 353#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40 354#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6 355#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80 356#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7 357#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8_MASK 0x100 358#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8__SHIFT 0x8 359#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9_MASK 0x200 360#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9__SHIFT 0x9 361#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10_MASK 0x400 362#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10__SHIFT 0xa 363#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11_MASK 0x800 364#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11__SHIFT 0xb 365#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12_MASK 0x1000 366#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12__SHIFT 0xc 367#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13_MASK 0x2000 368#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13__SHIFT 0xd 369#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14_MASK 0x4000 370#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14__SHIFT 0xe 371#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15_MASK 0x8000 372#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15__SHIFT 0xf 373#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffff 374#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x0 375#define SMC_RESP_0__SMC_RESP_MASK 0xffff 376#define SMC_RESP_0__SMC_RESP__SHIFT 0x0 377#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffff 378#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x0 379#define SMC_RESP_1__SMC_RESP_MASK 0xffff 380#define SMC_RESP_1__SMC_RESP__SHIFT 0x0 381#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffff 382#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x0 383#define SMC_RESP_2__SMC_RESP_MASK 0xffff 384#define SMC_RESP_2__SMC_RESP__SHIFT 0x0 385#define SMC_MESSAGE_3__SMC_MSG_MASK 0xffff 386#define SMC_MESSAGE_3__SMC_MSG__SHIFT 0x0 387#define SMC_RESP_3__SMC_RESP_MASK 0xffff 388#define SMC_RESP_3__SMC_RESP__SHIFT 0x0 389#define SMC_MESSAGE_4__SMC_MSG_MASK 0xffff 390#define SMC_MESSAGE_4__SMC_MSG__SHIFT 0x0 391#define SMC_RESP_4__SMC_RESP_MASK 0xffff 392#define SMC_RESP_4__SMC_RESP__SHIFT 0x0 393#define SMC_MESSAGE_5__SMC_MSG_MASK 0xffff 394#define SMC_MESSAGE_5__SMC_MSG__SHIFT 0x0 395#define SMC_RESP_5__SMC_RESP_MASK 0xffff 396#define SMC_RESP_5__SMC_RESP__SHIFT 0x0 397#define SMC_MESSAGE_6__SMC_MSG_MASK 0xffff 398#define SMC_MESSAGE_6__SMC_MSG__SHIFT 0x0 399#define SMC_RESP_6__SMC_RESP_MASK 0xffff 400#define SMC_RESP_6__SMC_RESP__SHIFT 0x0 401#define SMC_MESSAGE_7__SMC_MSG_MASK 0xffff 402#define SMC_MESSAGE_7__SMC_MSG__SHIFT 0x0 403#define SMC_RESP_7__SMC_RESP_MASK 0xffff 404#define SMC_RESP_7__SMC_RESP__SHIFT 0x0 405#define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK 0xffffffff 406#define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT 0x0 407#define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK 0xffffffff 408#define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT 0x0 409#define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK 0xffffffff 410#define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT 0x0 411#define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK 0xffffffff 412#define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT 0x0 413#define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK 0xffffffff 414#define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT 0x0 415#define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK 0xffffffff 416#define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT 0x0 417#define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK 0xffffffff 418#define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT 0x0 419#define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK 0xffffffff 420#define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT 0x0 421#define SMC_MESSAGE_8__SMC_MSG_MASK 0xffff 422#define SMC_MESSAGE_8__SMC_MSG__SHIFT 0x0 423#define SMC_RESP_8__SMC_RESP_MASK 0xffff 424#define SMC_RESP_8__SMC_RESP__SHIFT 0x0 425#define SMC_MESSAGE_9__SMC_MSG_MASK 0xffff 426#define SMC_MESSAGE_9__SMC_MSG__SHIFT 0x0 427#define SMC_RESP_9__SMC_RESP_MASK 0xffff 428#define SMC_RESP_9__SMC_RESP__SHIFT 0x0 429#define SMC_MESSAGE_10__SMC_MSG_MASK 0xffff 430#define SMC_MESSAGE_10__SMC_MSG__SHIFT 0x0 431#define SMC_RESP_10__SMC_RESP_MASK 0xffff 432#define SMC_RESP_10__SMC_RESP__SHIFT 0x0 433#define SMC_MESSAGE_11__SMC_MSG_MASK 0xffff 434#define SMC_MESSAGE_11__SMC_MSG__SHIFT 0x0 435#define SMC_RESP_11__SMC_RESP_MASK 0xffff 436#define SMC_RESP_11__SMC_RESP__SHIFT 0x0 437#define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK 0xffffffff 438#define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT 0x0 439#define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK 0xffffffff 440#define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT 0x0 441#define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK 0xffffffff 442#define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT 0x0 443#define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK 0xffffffff 444#define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT 0x0 445#define SMC_SYSCON_RESET_CNTL__rst_reg_MASK 0x1 446#define SMC_SYSCON_RESET_CNTL__rst_reg__SHIFT 0x0 447#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override_MASK 0x2 448#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override__SHIFT 0x1 449#define SMC_SYSCON_RESET_CNTL__RegReset_MASK 0x40000000 450#define SMC_SYSCON_RESET_CNTL__RegReset__SHIFT 0x1e 451#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK 0x1 452#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable__SHIFT 0x0 453#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en_MASK 0x2 454#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en__SHIFT 0x1 455#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout_MASK 0xffff00 456#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout__SHIFT 0x8 457#define SMC_SYSCON_CLOCK_CNTL_0__cken_MASK 0x1000000 458#define SMC_SYSCON_CLOCK_CNTL_0__cken__SHIFT 0x18 459#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable_MASK 0x1 460#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable__SHIFT 0x0 461#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq_MASK 0xffffffff 462#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq__SHIFT 0x0 463#define SMC_SYSCON_MISC_CNTL__dma_no_outstanding_MASK 0x2 464#define SMC_SYSCON_MISC_CNTL__dma_no_outstanding__SHIFT 0x1 465#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK 0xffffffff 466#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT 0x0 467#define SMC_PC_C__smc_pc_c_MASK 0xffffffff 468#define SMC_PC_C__smc_pc_c__SHIFT 0x0 469#define SMC_SCRATCH9__SCRATCH_VALUE_MASK 0xffffffff 470#define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT 0x0 471#define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x1 472#define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0 473#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0xf 474#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x0 475#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0xf0 476#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x4 477#define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffff 478#define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0 479#define GPIOPAD_A__GPIO_A_MASK 0x7fffffff 480#define GPIOPAD_A__GPIO_A__SHIFT 0x0 481#define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffff 482#define GPIOPAD_EN__GPIO_EN__SHIFT 0x0 483#define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffff 484#define GPIOPAD_Y__GPIO_Y__SHIFT 0x0 485#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x1 486#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0 487#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x2 488#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1 489#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x4 490#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2 491#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x8 492#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3 493#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x10 494#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4 495#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x20 496#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5 497#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x40 498#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6 499#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x80 500#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7 501#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x100 502#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8 503#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x200 504#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9 505#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x400 506#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa 507#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x800 508#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb 509#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x1000 510#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc 511#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x2000 512#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd 513#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x4000 514#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe 515#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x8000 516#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf 517#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x10000 518#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10 519#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x20000 520#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11 521#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x40000 522#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12 523#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x80000 524#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13 525#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x100000 526#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14 527#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x200000 528#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15 529#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x400000 530#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16 531#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x800000 532#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17 533#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x1000000 534#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18 535#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x2000000 536#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19 537#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x4000000 538#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a 539#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x8000000 540#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b 541#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000 542#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c 543#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000 544#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d 545#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000 546#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e 547#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffff 548#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0 549#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000 550#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f 551#define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffff 552#define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0 553#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000 554#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f 555#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x1 556#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0 557#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x2 558#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1 559#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x4 560#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2 561#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x8 562#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3 563#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x10 564#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4 565#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x20 566#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5 567#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x40 568#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6 569#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x80 570#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7 571#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x100 572#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8 573#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x200 574#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9 575#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x400 576#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa 577#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x800 578#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb 579#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x1000 580#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc 581#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x2000 582#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd 583#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x4000 584#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe 585#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x8000 586#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf 587#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x10000 588#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10 589#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x20000 590#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11 591#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x40000 592#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12 593#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x80000 594#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13 595#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x100000 596#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14 597#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x200000 598#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15 599#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x400000 600#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16 601#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x800000 602#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17 603#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x1000000 604#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18 605#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x2000000 606#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19 607#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x4000000 608#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a 609#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x8000000 610#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b 611#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000 612#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c 613#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000 614#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f 615#define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffff 616#define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0 617#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000 618#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f 619#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffff 620#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0 621#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000 622#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f 623#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffff 624#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0 625#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000 626#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f 627#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x1f 628#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x0 629#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x20 630#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x5 631#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x40 632#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x6 633#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffff 634#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x0 635#define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffff 636#define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0 637#define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffff 638#define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0 639#define CG_FPS_CNT__FPS_CNT_MASK 0xffffffff 640#define CG_FPS_CNT__FPS_CNT__SHIFT 0x0 641#define SMU_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff 642#define SMU_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0 643#define SMU_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff 644#define SMU_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0 645#define SMU_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff 646#define SMU_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0 647#define SMU_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff 648#define SMU_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0 649#define SMU_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff 650#define SMU_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0 651#define SMU_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff 652#define SMU_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0 653#define SMU_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff 654#define SMU_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0 655#define SMU_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff 656#define SMU_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0 657#define SMU_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff 658#define SMU_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0 659#define SMU_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff 660#define SMU_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0 661#define SMU_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff 662#define SMU_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0 663#define SMU_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff 664#define SMU_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0 665#define SMU_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff 666#define SMU_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0 667#define SMU_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff 668#define SMU_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0 669#define SMU_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff 670#define SMU_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0 671#define SMU_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff 672#define SMU_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0 673#define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 674#define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 675#define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 676#define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 677#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK 0x1 678#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT 0x0 679#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK 0x2 680#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT 0x1 681#define RCU_UC_EVENTS__drv_rst_mode_MASK 0x4 682#define RCU_UC_EVENTS__drv_rst_mode__SHIFT 0x2 683#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid_MASK 0x8 684#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid__SHIFT 0x3 685#define RCU_UC_EVENTS__TP_Tester_MASK 0x40 686#define RCU_UC_EVENTS__TP_Tester__SHIFT 0x6 687#define RCU_UC_EVENTS__boot_seq_done_MASK 0x80 688#define RCU_UC_EVENTS__boot_seq_done__SHIFT 0x7 689#define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100 690#define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT 0x8 691#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK 0x200 692#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT 0x9 693#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK 0x400 694#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT 0xa 695#define RCU_UC_EVENTS__FCH_HALT_MASK 0x800 696#define RCU_UC_EVENTS__FCH_HALT__SHIFT 0xb 697#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK 0x2000 698#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT 0xd 699#define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK 0x10000 700#define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT 0x10 701#define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK 0x20000 702#define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT 0x11 703#define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK 0x40000 704#define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT 0x12 705#define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK 0x80000 706#define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT 0x13 707#define RCU_UC_EVENTS__irq31_sel_MASK 0x3000000 708#define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18 709#define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK 0x2 710#define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT 0x1 711#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK 0x8 712#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT 0x3 713#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK 0x10 714#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT 0x4 715#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK 0x20 716#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT 0x5 717#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK 0x100 718#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT 0x8 719#define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK 0x10000 720#define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT 0x10 721#define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK 0x20000 722#define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT 0x11 723#define RCU_MISC_CTRL__SAMU_START_MASK 0x400000 724#define RCU_MISC_CTRL__SAMU_START__SHIFT 0x16 725#define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK 0xff800000 726#define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT 0x17 727#define RCU_VIRT_RESET_REQ__VF_MASK 0xffff 728#define RCU_VIRT_RESET_REQ__VF__SHIFT 0x0 729#define RCU_VIRT_RESET_REQ__PF_MASK 0x80000000 730#define RCU_VIRT_RESET_REQ__PF__SHIFT 0x1f 731#define CC_RCU_FUSES__GPU_DIS_MASK 0x2 732#define CC_RCU_FUSES__GPU_DIS__SHIFT 0x1 733#define CC_RCU_FUSES__DEBUG_DISABLE_MASK 0x4 734#define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT 0x2 735#define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK 0x10 736#define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT 0x4 737#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK 0x20 738#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT 0x5 739#define CC_RCU_FUSES__DRV_RST_MODE_MASK 0x40 740#define CC_RCU_FUSES__DRV_RST_MODE__SHIFT 0x6 741#define CC_RCU_FUSES__ROM_DIS_MASK 0x80 742#define CC_RCU_FUSES__ROM_DIS__SHIFT 0x7 743#define CC_RCU_FUSES__JPC_REP_DISABLE_MASK 0x100 744#define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT 0x8 745#define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK 0x200 746#define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT 0x9 747#define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK 0x400 748#define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT 0xa 749#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK 0x4000 750#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT 0xe 751#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK 0x8000 752#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT 0xf 753#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK 0x10000 754#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT 0x10 755#define CC_RCU_FUSES__XFIRE_DISABLE_MASK 0x20000 756#define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT 0x11 757#define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK 0x40000 758#define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT 0x12 759#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK 0x80000 760#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT 0x13 761#define CC_RCU_FUSES__MEM_HARDREP_EN_MASK 0x200000 762#define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT 0x15 763#define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK 0x400000 764#define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT 0x16 765#define CC_RCU_FUSES__DSMU_DISABLE_MASK 0x800000 766#define CC_RCU_FUSES__DSMU_DISABLE__SHIFT 0x17 767#define CC_RCU_FUSES__WRP_FUSE_VALID_MASK 0x1000000 768#define CC_RCU_FUSES__WRP_FUSE_VALID__SHIFT 0x18 769#define CC_RCU_FUSES__PHY_FUSE_VALID_MASK 0x2000000 770#define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT 0x19 771#define CC_RCU_FUSES__RCU_SPARE_MASK 0xfc000000 772#define CC_RCU_FUSES__RCU_SPARE__SHIFT 0x1a 773#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK 0x2 774#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT 0x1 775#define CC_SMU_MISC_FUSES__MinSClkDid_MASK 0x1fc 776#define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT 0x2 777#define CC_SMU_MISC_FUSES__MISC_SPARE_MASK 0x600 778#define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT 0x9 779#define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK 0x3f800 780#define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT 0xb 781#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK 0x40000 782#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT 0x12 783#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK 0x80000 784#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT 0x13 785#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK 0x100000 786#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT 0x14 787#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK 0x200000 788#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT 0x15 789#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK 0x400000 790#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT 0x16 791#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK 0x800000 792#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT 0x17 793#define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK 0x8000000 794#define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT 0x1b 795#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK 0x10000000 796#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT 0x1c 797#define CC_SMU_MISC_FUSES__GNB_SPARE_MASK 0x60000000 798#define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT 0x1d 799#define CC_SCLK_VID_FUSES__SClkVid0_MASK 0xff 800#define CC_SCLK_VID_FUSES__SClkVid0__SHIFT 0x0 801#define CC_SCLK_VID_FUSES__SClkVid1_MASK 0xff00 802#define CC_SCLK_VID_FUSES__SClkVid1__SHIFT 0x8 803#define CC_SCLK_VID_FUSES__SClkVid2_MASK 0xff0000 804#define CC_SCLK_VID_FUSES__SClkVid2__SHIFT 0x10 805#define CC_SCLK_VID_FUSES__SClkVid3_MASK 0xff000000 806#define CC_SCLK_VID_FUSES__SClkVid3__SHIFT 0x18 807#define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK 0x7fe 808#define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT 0x1 809#define CC_GIO_IOC_FUSES__IOC_FUSES_MASK 0x3e 810#define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT 0x1 811#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK 0x3e 812#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT 0x1 813#define CC_SMU_TST_EFUSE1_MISC__RME_MASK 0x40 814#define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT 0x6 815#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK 0x80 816#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT 0x7 817#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK 0x100 818#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT 0x8 819#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK 0x200 820#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT 0x9 821#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK 0x400 822#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT 0xa 823#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800 824#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT 0xb 825#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK 0x1000 826#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT 0xc 827#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK 0x2000 828#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT 0xd 829#define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK 0x4000 830#define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT 0xe 831#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK 0x400000 832#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT 0x16 833#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK 0x800000 834#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT 0x17 835#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK 0x1000000 836#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT 0x18 837#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK 0x2000000 838#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT 0x19 839#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK 0x4000000 840#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT 0x1a 841#define CC_TST_ID_STRAPS__DEVICE_ID_MASK 0xffff0 842#define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT 0x4 843#define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000 844#define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14 845#define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000 846#define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18 847#define CC_TST_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000 848#define CC_TST_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c 849#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK 0x2 850#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT 0x1 851#define CC_HARVEST_FUSES__VCE_DISABLE_MASK 0x6 852#define CC_HARVEST_FUSES__VCE_DISABLE__SHIFT 0x1 853#define CC_HARVEST_FUSES__UVD_DISABLE_MASK 0x10 854#define CC_HARVEST_FUSES__UVD_DISABLE__SHIFT 0x4 855#define CC_HARVEST_FUSES__ACP_DISABLE_MASK 0x40 856#define CC_HARVEST_FUSES__ACP_DISABLE__SHIFT 0x6 857#define CC_HARVEST_FUSES__DC_DISABLE_MASK 0x3f00 858#define CC_HARVEST_FUSES__DC_DISABLE__SHIFT 0x8 859#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK 0xffffffff 860#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT 0x0 861#define SMU_STATUS__SMU_DONE_MASK 0x1 862#define SMU_STATUS__SMU_DONE__SHIFT 0x0 863#define SMU_STATUS__SMU_PASS_MASK 0x2 864#define SMU_STATUS__SMU_PASS__SHIFT 0x1 865#define SMU_FIRMWARE__SMU_IN_PROG_MASK 0x1 866#define SMU_FIRMWARE__SMU_IN_PROG__SHIFT 0x0 867#define SMU_FIRMWARE__SMU_RD_DONE_MASK 0x6 868#define SMU_FIRMWARE__SMU_RD_DONE__SHIFT 0x1 869#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN_MASK 0x8 870#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN__SHIFT 0x3 871#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN_MASK 0x10 872#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN__SHIFT 0x4 873#define SMU_FIRMWARE__SMU_counter_MASK 0xf00 874#define SMU_FIRMWARE__SMU_counter__SHIFT 0x8 875#define SMU_FIRMWARE__SMU_MODE_MASK 0x10000 876#define SMU_FIRMWARE__SMU_MODE__SHIFT 0x10 877#define SMU_FIRMWARE__SMU_SEL_MASK 0x20000 878#define SMU_FIRMWARE__SMU_SEL__SHIFT 0x11 879#define SMU_INPUT_DATA__START_ADDR_MASK 0x7fffffff 880#define SMU_INPUT_DATA__START_ADDR__SHIFT 0x0 881#define SMU_INPUT_DATA__AUTO_START_MASK 0x80000000 882#define SMU_INPUT_DATA__AUTO_START__SHIFT 0x1f 883#define SMU_EFUSE_0__EFUSE_DATA_MASK 0xffffffff 884#define SMU_EFUSE_0__EFUSE_DATA__SHIFT 0x0 885#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x1 886#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 887#define FIRMWARE_FLAGS__RESERVED_MASK 0xfffffe 888#define FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 889#define FIRMWARE_FLAGS__TEST_COUNT_MASK 0xff000000 890#define FIRMWARE_FLAGS__TEST_COUNT__SHIFT 0x18 891#define TDC_STATUS__VDD_Boost_MASK 0xff 892#define TDC_STATUS__VDD_Boost__SHIFT 0x0 893#define TDC_STATUS__VDD_Throttle_MASK 0xff00 894#define TDC_STATUS__VDD_Throttle__SHIFT 0x8 895#define TDC_STATUS__VDDC_Boost_MASK 0xff0000 896#define TDC_STATUS__VDDC_Boost__SHIFT 0x10 897#define TDC_STATUS__VDDC_Throttle_MASK 0xff000000 898#define TDC_STATUS__VDDC_Throttle__SHIFT 0x18 899#define TDC_MV_AVERAGE__IDD_MASK 0xffff 900#define TDC_MV_AVERAGE__IDD__SHIFT 0x0 901#define TDC_MV_AVERAGE__IDDC_MASK 0xffff0000 902#define TDC_MV_AVERAGE__IDDC__SHIFT 0x10 903#define TDC_VRM_LIMIT__IDD_MASK 0xffff 904#define TDC_VRM_LIMIT__IDD__SHIFT 0x0 905#define TDC_VRM_LIMIT__IDDC_MASK 0xffff0000 906#define TDC_VRM_LIMIT__IDDC__SHIFT 0x10 907#define FEATURE_STATUS__SCLK_DPM_ON_MASK 0x1 908#define FEATURE_STATUS__SCLK_DPM_ON__SHIFT 0x0 909#define FEATURE_STATUS__MCLK_DPM_ON_MASK 0x2 910#define FEATURE_STATUS__MCLK_DPM_ON__SHIFT 0x1 911#define FEATURE_STATUS__LCLK_DPM_ON_MASK 0x4 912#define FEATURE_STATUS__LCLK_DPM_ON__SHIFT 0x2 913#define FEATURE_STATUS__UVD_DPM_ON_MASK 0x8 914#define FEATURE_STATUS__UVD_DPM_ON__SHIFT 0x3 915#define FEATURE_STATUS__VCE_DPM_ON_MASK 0x10 916#define FEATURE_STATUS__VCE_DPM_ON__SHIFT 0x4 917#define FEATURE_STATUS__ACP_DPM_ON_MASK 0x20 918#define FEATURE_STATUS__ACP_DPM_ON__SHIFT 0x5 919#define FEATURE_STATUS__SAMU_DPM_ON_MASK 0x40 920#define FEATURE_STATUS__SAMU_DPM_ON__SHIFT 0x6 921#define FEATURE_STATUS__PCIE_DPM_ON_MASK 0x80 922#define FEATURE_STATUS__PCIE_DPM_ON__SHIFT 0x7 923#define FEATURE_STATUS__BAPM_ON_MASK 0x100 924#define FEATURE_STATUS__BAPM_ON__SHIFT 0x8 925#define FEATURE_STATUS__LPMX_ON_MASK 0x200 926#define FEATURE_STATUS__LPMX_ON__SHIFT 0x9 927#define FEATURE_STATUS__NBDPM_ON_MASK 0x400 928#define FEATURE_STATUS__NBDPM_ON__SHIFT 0xa 929#define FEATURE_STATUS__LHTC_ON_MASK 0x800 930#define FEATURE_STATUS__LHTC_ON__SHIFT 0xb 931#define FEATURE_STATUS__VPC_ON_MASK 0x1000 932#define FEATURE_STATUS__VPC_ON__SHIFT 0xc 933#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON_MASK 0x2000 934#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON__SHIFT 0xd 935#define FEATURE_STATUS__TDC_LIMIT_ON_MASK 0x4000 936#define FEATURE_STATUS__TDC_LIMIT_ON__SHIFT 0xe 937#define FEATURE_STATUS__GPU_CAC_ON_MASK 0x8000 938#define FEATURE_STATUS__GPU_CAC_ON__SHIFT 0xf 939#define FEATURE_STATUS__AVS_ON_MASK 0x10000 940#define FEATURE_STATUS__AVS_ON__SHIFT 0x10 941#define FEATURE_STATUS__SPMI_ON_MASK 0x20000 942#define FEATURE_STATUS__SPMI_ON__SHIFT 0x11 943#define FEATURE_STATUS__SCLK_DPM_FORCED_MASK 0x40000 944#define FEATURE_STATUS__SCLK_DPM_FORCED__SHIFT 0x12 945#define FEATURE_STATUS__MCLK_DPM_FORCED_MASK 0x80000 946#define FEATURE_STATUS__MCLK_DPM_FORCED__SHIFT 0x13 947#define FEATURE_STATUS__LCLK_DPM_FORCED_MASK 0x100000 948#define FEATURE_STATUS__LCLK_DPM_FORCED__SHIFT 0x14 949#define FEATURE_STATUS__PCIE_DPM_FORCED_MASK 0x200000 950#define FEATURE_STATUS__PCIE_DPM_FORCED__SHIFT 0x15 951#define FEATURE_STATUS__RESERVED_MASK 0xffc00000 952#define FEATURE_STATUS__RESERVED__SHIFT 0x16 953#define ENTITY_TEMPERATURES_1__GPU_MASK 0xffffffff 954#define ENTITY_TEMPERATURES_1__GPU__SHIFT 0x0 955#define DPM_TABLE_1__GraphicsPIDController_Ki_MASK 0xffffffff 956#define DPM_TABLE_1__GraphicsPIDController_Ki__SHIFT 0x0 957#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim_MASK 0xffffffff 958#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim__SHIFT 0x0 959#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim_MASK 0xffffffff 960#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim__SHIFT 0x0 961#define DPM_TABLE_4__GraphicsPIDController_StatePrecision_MASK 0xffffffff 962#define DPM_TABLE_4__GraphicsPIDController_StatePrecision__SHIFT 0x0 963#define DPM_TABLE_5__GraphicsPIDController_LfPrecision_MASK 0xffffffff 964#define DPM_TABLE_5__GraphicsPIDController_LfPrecision__SHIFT 0x0 965#define DPM_TABLE_6__GraphicsPIDController_LfOffset_MASK 0xffffffff 966#define DPM_TABLE_6__GraphicsPIDController_LfOffset__SHIFT 0x0 967#define DPM_TABLE_7__GraphicsPIDController_MaxState_MASK 0xffffffff 968#define DPM_TABLE_7__GraphicsPIDController_MaxState__SHIFT 0x0 969#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction_MASK 0xffffffff 970#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction__SHIFT 0x0 971#define DPM_TABLE_9__GraphicsPIDController_StateShift_MASK 0xffffffff 972#define DPM_TABLE_9__GraphicsPIDController_StateShift__SHIFT 0x0 973#define DPM_TABLE_10__MemoryPIDController_Ki_MASK 0xffffffff 974#define DPM_TABLE_10__MemoryPIDController_Ki__SHIFT 0x0 975#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim_MASK 0xffffffff 976#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim__SHIFT 0x0 977#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim_MASK 0xffffffff 978#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim__SHIFT 0x0 979#define DPM_TABLE_13__MemoryPIDController_StatePrecision_MASK 0xffffffff 980#define DPM_TABLE_13__MemoryPIDController_StatePrecision__SHIFT 0x0 981#define DPM_TABLE_14__MemoryPIDController_LfPrecision_MASK 0xffffffff 982#define DPM_TABLE_14__MemoryPIDController_LfPrecision__SHIFT 0x0 983#define DPM_TABLE_15__MemoryPIDController_LfOffset_MASK 0xffffffff 984#define DPM_TABLE_15__MemoryPIDController_LfOffset__SHIFT 0x0 985#define DPM_TABLE_16__MemoryPIDController_MaxState_MASK 0xffffffff 986#define DPM_TABLE_16__MemoryPIDController_MaxState__SHIFT 0x0 987#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction_MASK 0xffffffff 988#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction__SHIFT 0x0 989#define DPM_TABLE_18__MemoryPIDController_StateShift_MASK 0xffffffff 990#define DPM_TABLE_18__MemoryPIDController_StateShift__SHIFT 0x0 991#define DPM_TABLE_19__LinkPIDController_Ki_MASK 0xffffffff 992#define DPM_TABLE_19__LinkPIDController_Ki__SHIFT 0x0 993#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim_MASK 0xffffffff 994#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim__SHIFT 0x0 995#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim_MASK 0xffffffff 996#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim__SHIFT 0x0 997#define DPM_TABLE_22__LinkPIDController_StatePrecision_MASK 0xffffffff 998#define DPM_TABLE_22__LinkPIDController_StatePrecision__SHIFT 0x0 999#define DPM_TABLE_23__LinkPIDController_LfPrecision_MASK 0xffffffff 1000#define DPM_TABLE_23__LinkPIDController_LfPrecision__SHIFT 0x0
1001#define DPM_TABLE_24__LinkPIDController_LfOffset_MASK 0xffffffff 1002#define DPM_TABLE_24__LinkPIDController_LfOffset__SHIFT 0x0 1003#define DPM_TABLE_25__LinkPIDController_MaxState_MASK 0xffffffff 1004#define DPM_TABLE_25__LinkPIDController_MaxState__SHIFT 0x0 1005#define DPM_TABLE_26__LinkPIDController_MaxLfFraction_MASK 0xffffffff 1006#define DPM_TABLE_26__LinkPIDController_MaxLfFraction__SHIFT 0x0 1007#define DPM_TABLE_27__LinkPIDController_StateShift_MASK 0xffffffff 1008#define DPM_TABLE_27__LinkPIDController_StateShift__SHIFT 0x0 1009#define DPM_TABLE_28__SystemFlags_MASK 0xffffffff 1010#define DPM_TABLE_28__SystemFlags__SHIFT 0x0 1011#define DPM_TABLE_29__VRConfig_MASK 0xffffffff 1012#define DPM_TABLE_29__VRConfig__SHIFT 0x0 1013#define DPM_TABLE_30__SmioMask1_MASK 0xffffffff 1014#define DPM_TABLE_30__SmioMask1__SHIFT 0x0 1015#define DPM_TABLE_31__SmioMask2_MASK 0xffffffff 1016#define DPM_TABLE_31__SmioMask2__SHIFT 0x0 1017#define DPM_TABLE_32__SmioTable1_Pattern_0_padding_MASK 0xff 1018#define DPM_TABLE_32__SmioTable1_Pattern_0_padding__SHIFT 0x0 1019#define DPM_TABLE_32__SmioTable1_Pattern_0_Smio_MASK 0xff00 1020#define DPM_TABLE_32__SmioTable1_Pattern_0_Smio__SHIFT 0x8 1021#define DPM_TABLE_32__SmioTable1_Pattern_0_Voltage_MASK 0xffff0000 1022#define DPM_TABLE_32__SmioTable1_Pattern_0_Voltage__SHIFT 0x10 1023#define DPM_TABLE_33__SmioTable1_Pattern_1_padding_MASK 0xff 1024#define DPM_TABLE_33__SmioTable1_Pattern_1_padding__SHIFT 0x0 1025#define DPM_TABLE_33__SmioTable1_Pattern_1_Smio_MASK 0xff00 1026#define DPM_TABLE_33__SmioTable1_Pattern_1_Smio__SHIFT 0x8 1027#define DPM_TABLE_33__SmioTable1_Pattern_1_Voltage_MASK 0xffff0000 1028#define DPM_TABLE_33__SmioTable1_Pattern_1_Voltage__SHIFT 0x10 1029#define DPM_TABLE_34__SmioTable1_Pattern_2_padding_MASK 0xff 1030#define DPM_TABLE_34__SmioTable1_Pattern_2_padding__SHIFT 0x0 1031#define DPM_TABLE_34__SmioTable1_Pattern_2_Smio_MASK 0xff00 1032#define DPM_TABLE_34__SmioTable1_Pattern_2_Smio__SHIFT 0x8 1033#define DPM_TABLE_34__SmioTable1_Pattern_2_Voltage_MASK 0xffff0000 1034#define DPM_TABLE_34__SmioTable1_Pattern_2_Voltage__SHIFT 0x10 1035#define DPM_TABLE_35__SmioTable1_Pattern_3_padding_MASK 0xff 1036#define DPM_TABLE_35__SmioTable1_Pattern_3_padding__SHIFT 0x0 1037#define DPM_TABLE_35__SmioTable1_Pattern_3_Smio_MASK 0xff00 1038#define DPM_TABLE_35__SmioTable1_Pattern_3_Smio__SHIFT 0x8 1039#define DPM_TABLE_35__SmioTable1_Pattern_3_Voltage_MASK 0xffff0000 1040#define DPM_TABLE_35__SmioTable1_Pattern_3_Voltage__SHIFT 0x10 1041#define DPM_TABLE_36__SmioTable2_Pattern_0_padding_MASK 0xff 1042#define DPM_TABLE_36__SmioTable2_Pattern_0_padding__SHIFT 0x0 1043#define DPM_TABLE_36__SmioTable2_Pattern_0_Smio_MASK 0xff00 1044#define DPM_TABLE_36__SmioTable2_Pattern_0_Smio__SHIFT 0x8 1045#define DPM_TABLE_36__SmioTable2_Pattern_0_Voltage_MASK 0xffff0000 1046#define DPM_TABLE_36__SmioTable2_Pattern_0_Voltage__SHIFT 0x10 1047#define DPM_TABLE_37__SmioTable2_Pattern_1_padding_MASK 0xff 1048#define DPM_TABLE_37__SmioTable2_Pattern_1_padding__SHIFT 0x0 1049#define DPM_TABLE_37__SmioTable2_Pattern_1_Smio_MASK 0xff00 1050#define DPM_TABLE_37__SmioTable2_Pattern_1_Smio__SHIFT 0x8 1051#define DPM_TABLE_37__SmioTable2_Pattern_1_Voltage_MASK 0xffff0000 1052#define DPM_TABLE_37__SmioTable2_Pattern_1_Voltage__SHIFT 0x10 1053#define DPM_TABLE_38__SmioTable2_Pattern_2_padding_MASK 0xff 1054#define DPM_TABLE_38__SmioTable2_Pattern_2_padding__SHIFT 0x0 1055#define DPM_TABLE_38__SmioTable2_Pattern_2_Smio_MASK 0xff00 1056#define DPM_TABLE_38__SmioTable2_Pattern_2_Smio__SHIFT 0x8 1057#define DPM_TABLE_38__SmioTable2_Pattern_2_Voltage_MASK 0xffff0000 1058#define DPM_TABLE_38__SmioTable2_Pattern_2_Voltage__SHIFT 0x10 1059#define DPM_TABLE_39__SmioTable2_Pattern_3_padding_MASK 0xff 1060#define DPM_TABLE_39__SmioTable2_Pattern_3_padding__SHIFT 0x0 1061#define DPM_TABLE_39__SmioTable2_Pattern_3_Smio_MASK 0xff00 1062#define DPM_TABLE_39__SmioTable2_Pattern_3_Smio__SHIFT 0x8 1063#define DPM_TABLE_39__SmioTable2_Pattern_3_Voltage_MASK 0xffff0000 1064#define DPM_TABLE_39__SmioTable2_Pattern_3_Voltage__SHIFT 0x10 1065#define DPM_TABLE_40__VddcLevelCount_MASK 0xffffffff 1066#define DPM_TABLE_40__VddcLevelCount__SHIFT 0x0 1067#define DPM_TABLE_41__VddciLevelCount_MASK 0xffffffff 1068#define DPM_TABLE_41__VddciLevelCount__SHIFT 0x0 1069#define DPM_TABLE_42__VddGfxLevelCount_MASK 0xffffffff 1070#define DPM_TABLE_42__VddGfxLevelCount__SHIFT 0x0 1071#define DPM_TABLE_43__MvddLevelCount_MASK 0xffffffff 1072#define DPM_TABLE_43__MvddLevelCount__SHIFT 0x0 1073#define DPM_TABLE_44__VddcTable_1_MASK 0xffff 1074#define DPM_TABLE_44__VddcTable_1__SHIFT 0x0 1075#define DPM_TABLE_44__VddcTable_0_MASK 0xffff0000 1076#define DPM_TABLE_44__VddcTable_0__SHIFT 0x10 1077#define DPM_TABLE_45__VddcTable_3_MASK 0xffff 1078#define DPM_TABLE_45__VddcTable_3__SHIFT 0x0 1079#define DPM_TABLE_45__VddcTable_2_MASK 0xffff0000 1080#define DPM_TABLE_45__VddcTable_2__SHIFT 0x10 1081#define DPM_TABLE_46__VddcTable_5_MASK 0xffff 1082#define DPM_TABLE_46__VddcTable_5__SHIFT 0x0 1083#define DPM_TABLE_46__VddcTable_4_MASK 0xffff0000 1084#define DPM_TABLE_46__VddcTable_4__SHIFT 0x10 1085#define DPM_TABLE_47__VddcTable_7_MASK 0xffff 1086#define DPM_TABLE_47__VddcTable_7__SHIFT 0x0 1087#define DPM_TABLE_47__VddcTable_6_MASK 0xffff0000 1088#define DPM_TABLE_47__VddcTable_6__SHIFT 0x10 1089#define DPM_TABLE_48__VddcTable_9_MASK 0xffff 1090#define DPM_TABLE_48__VddcTable_9__SHIFT 0x0 1091#define DPM_TABLE_48__VddcTable_8_MASK 0xffff0000 1092#define DPM_TABLE_48__VddcTable_8__SHIFT 0x10 1093#define DPM_TABLE_49__VddcTable_11_MASK 0xffff 1094#define DPM_TABLE_49__VddcTable_11__SHIFT 0x0 1095#define DPM_TABLE_49__VddcTable_10_MASK 0xffff0000 1096#define DPM_TABLE_49__VddcTable_10__SHIFT 0x10 1097#define DPM_TABLE_50__VddcTable_13_MASK 0xffff 1098#define DPM_TABLE_50__VddcTable_13__SHIFT 0x0 1099#define DPM_TABLE_50__VddcTable_12_MASK 0xffff0000 1100#define DPM_TABLE_50__VddcTable_12__SHIFT 0x10 1101#define DPM_TABLE_51__VddcTable_15_MASK 0xffff 1102#define DPM_TABLE_51__VddcTable_15__SHIFT 0x0 1103#define DPM_TABLE_51__VddcTable_14_MASK 0xffff0000 1104#define DPM_TABLE_51__VddcTable_14__SHIFT 0x10 1105#define DPM_TABLE_52__VddGfxTable_1_MASK 0xffff 1106#define DPM_TABLE_52__VddGfxTable_1__SHIFT 0x0 1107#define DPM_TABLE_52__VddGfxTable_0_MASK 0xffff0000 1108#define DPM_TABLE_52__VddGfxTable_0__SHIFT 0x10 1109#define DPM_TABLE_53__VddGfxTable_3_MASK 0xffff 1110#define DPM_TABLE_53__VddGfxTable_3__SHIFT 0x0 1111#define DPM_TABLE_53__VddGfxTable_2_MASK 0xffff0000 1112#define DPM_TABLE_53__VddGfxTable_2__SHIFT 0x10 1113#define DPM_TABLE_54__VddGfxTable_5_MASK 0xffff 1114#define DPM_TABLE_54__VddGfxTable_5__SHIFT 0x0 1115#define DPM_TABLE_54__VddGfxTable_4_MASK 0xffff0000 1116#define DPM_TABLE_54__VddGfxTable_4__SHIFT 0x10 1117#define DPM_TABLE_55__VddGfxTable_7_MASK 0xffff 1118#define DPM_TABLE_55__VddGfxTable_7__SHIFT 0x0 1119#define DPM_TABLE_55__VddGfxTable_6_MASK 0xffff0000 1120#define DPM_TABLE_55__VddGfxTable_6__SHIFT 0x10 1121#define DPM_TABLE_56__VddGfxTable_9_MASK 0xffff 1122#define DPM_TABLE_56__VddGfxTable_9__SHIFT 0x0 1123#define DPM_TABLE_56__VddGfxTable_8_MASK 0xffff0000 1124#define DPM_TABLE_56__VddGfxTable_8__SHIFT 0x10 1125#define DPM_TABLE_57__VddGfxTable_11_MASK 0xffff 1126#define DPM_TABLE_57__VddGfxTable_11__SHIFT 0x0 1127#define DPM_TABLE_57__VddGfxTable_10_MASK 0xffff0000 1128#define DPM_TABLE_57__VddGfxTable_10__SHIFT 0x10 1129#define DPM_TABLE_58__VddGfxTable_13_MASK 0xffff 1130#define DPM_TABLE_58__VddGfxTable_13__SHIFT 0x0 1131#define DPM_TABLE_58__VddGfxTable_12_MASK 0xffff0000 1132#define DPM_TABLE_58__VddGfxTable_12__SHIFT 0x10 1133#define DPM_TABLE_59__VddGfxTable_15_MASK 0xffff 1134#define DPM_TABLE_59__VddGfxTable_15__SHIFT 0x0 1135#define DPM_TABLE_59__VddGfxTable_14_MASK 0xffff0000 1136#define DPM_TABLE_59__VddGfxTable_14__SHIFT 0x10 1137#define DPM_TABLE_60__VddciTable_1_MASK 0xffff 1138#define DPM_TABLE_60__VddciTable_1__SHIFT 0x0 1139#define DPM_TABLE_60__VddciTable_0_MASK 0xffff0000 1140#define DPM_TABLE_60__VddciTable_0__SHIFT 0x10 1141#define DPM_TABLE_61__VddciTable_3_MASK 0xffff 1142#define DPM_TABLE_61__VddciTable_3__SHIFT 0x0 1143#define DPM_TABLE_61__VddciTable_2_MASK 0xffff0000 1144#define DPM_TABLE_61__VddciTable_2__SHIFT 0x10 1145#define DPM_TABLE_62__VddciTable_5_MASK 0xffff 1146#define DPM_TABLE_62__VddciTable_5__SHIFT 0x0 1147#define DPM_TABLE_62__VddciTable_4_MASK 0xffff0000 1148#define DPM_TABLE_62__VddciTable_4__SHIFT 0x10 1149#define DPM_TABLE_63__VddciTable_7_MASK 0xffff 1150#define DPM_TABLE_63__VddciTable_7__SHIFT 0x0 1151#define DPM_TABLE_63__VddciTable_6_MASK 0xffff0000 1152#define DPM_TABLE_63__VddciTable_6__SHIFT 0x10 1153#define DPM_TABLE_64__BapmVddGfxVidHiSidd_3_MASK 0xff 1154#define DPM_TABLE_64__BapmVddGfxVidHiSidd_3__SHIFT 0x0 1155#define DPM_TABLE_64__BapmVddGfxVidHiSidd_2_MASK 0xff00 1156#define DPM_TABLE_64__BapmVddGfxVidHiSidd_2__SHIFT 0x8 1157#define DPM_TABLE_64__BapmVddGfxVidHiSidd_1_MASK 0xff0000 1158#define DPM_TABLE_64__BapmVddGfxVidHiSidd_1__SHIFT 0x10 1159#define DPM_TABLE_64__BapmVddGfxVidHiSidd_0_MASK 0xff000000 1160#define DPM_TABLE_64__BapmVddGfxVidHiSidd_0__SHIFT 0x18 1161#define DPM_TABLE_65__BapmVddGfxVidHiSidd_7_MASK 0xff 1162#define DPM_TABLE_65__BapmVddGfxVidHiSidd_7__SHIFT 0x0 1163#define DPM_TABLE_65__BapmVddGfxVidHiSidd_6_MASK 0xff00 1164#define DPM_TABLE_65__BapmVddGfxVidHiSidd_6__SHIFT 0x8 1165#define DPM_TABLE_65__BapmVddGfxVidHiSidd_5_MASK 0xff0000 1166#define DPM_TABLE_65__BapmVddGfxVidHiSidd_5__SHIFT 0x10 1167#define DPM_TABLE_65__BapmVddGfxVidHiSidd_4_MASK 0xff000000 1168#define DPM_TABLE_65__BapmVddGfxVidHiSidd_4__SHIFT 0x18 1169#define DPM_TABLE_66__BapmVddGfxVidHiSidd_11_MASK 0xff 1170#define DPM_TABLE_66__BapmVddGfxVidHiSidd_11__SHIFT 0x0 1171#define DPM_TABLE_66__BapmVddGfxVidHiSidd_10_MASK 0xff00 1172#define DPM_TABLE_66__BapmVddGfxVidHiSidd_10__SHIFT 0x8 1173#define DPM_TABLE_66__BapmVddGfxVidHiSidd_9_MASK 0xff0000 1174#define DPM_TABLE_66__BapmVddGfxVidHiSidd_9__SHIFT 0x10 1175#define DPM_TABLE_66__BapmVddGfxVidHiSidd_8_MASK 0xff000000 1176#define DPM_TABLE_66__BapmVddGfxVidHiSidd_8__SHIFT 0x18 1177#define DPM_TABLE_67__BapmVddGfxVidHiSidd_15_MASK 0xff 1178#define DPM_TABLE_67__BapmVddGfxVidHiSidd_15__SHIFT 0x0 1179#define DPM_TABLE_67__BapmVddGfxVidHiSidd_14_MASK 0xff00 1180#define DPM_TABLE_67__BapmVddGfxVidHiSidd_14__SHIFT 0x8 1181#define DPM_TABLE_67__BapmVddGfxVidHiSidd_13_MASK 0xff0000 1182#define DPM_TABLE_67__BapmVddGfxVidHiSidd_13__SHIFT 0x10 1183#define DPM_TABLE_67__BapmVddGfxVidHiSidd_12_MASK 0xff000000 1184#define DPM_TABLE_67__BapmVddGfxVidHiSidd_12__SHIFT 0x18 1185#define DPM_TABLE_68__BapmVddGfxVidLoSidd_3_MASK 0xff 1186#define DPM_TABLE_68__BapmVddGfxVidLoSidd_3__SHIFT 0x0 1187#define DPM_TABLE_68__BapmVddGfxVidLoSidd_2_MASK 0xff00 1188#define DPM_TABLE_68__BapmVddGfxVidLoSidd_2__SHIFT 0x8 1189#define DPM_TABLE_68__BapmVddGfxVidLoSidd_1_MASK 0xff0000 1190#define DPM_TABLE_68__BapmVddGfxVidLoSidd_1__SHIFT 0x10 1191#define DPM_TABLE_68__BapmVddGfxVidLoSidd_0_MASK 0xff000000 1192#define DPM_TABLE_68__BapmVddGfxVidLoSidd_0__SHIFT 0x18 1193#define DPM_TABLE_69__BapmVddGfxVidLoSidd_7_MASK 0xff 1194#define DPM_TABLE_69__BapmVddGfxVidLoSidd_7__SHIFT 0x0 1195#define DPM_TABLE_69__BapmVddGfxVidLoSidd_6_MASK 0xff00 1196#define DPM_TABLE_69__BapmVddGfxVidLoSidd_6__SHIFT 0x8 1197#define DPM_TABLE_69__BapmVddGfxVidLoSidd_5_MASK 0xff0000 1198#define DPM_TABLE_69__BapmVddGfxVidLoSidd_5__SHIFT 0x10 1199#define DPM_TABLE_69__BapmVddGfxVidLoSidd_4_MASK 0xff000000 1200#define DPM_TABLE_69__BapmVddGfxVidLoSidd_4__SHIFT 0x18 1201#define DPM_TABLE_70__BapmVddGfxVidLoSidd_11_MASK 0xff 1202#define DPM_TABLE_70__BapmVddGfxVidLoSidd_11__SHIFT 0x0 1203#define DPM_TABLE_70__BapmVddGfxVidLoSidd_10_MASK 0xff00 1204#define DPM_TABLE_70__BapmVddGfxVidLoSidd_10__SHIFT 0x8 1205#define DPM_TABLE_70__BapmVddGfxVidLoSidd_9_MASK 0xff0000 1206#define DPM_TABLE_70__BapmVddGfxVidLoSidd_9__SHIFT 0x10 1207#define DPM_TABLE_70__BapmVddGfxVidLoSidd_8_MASK 0xff000000 1208#define DPM_TABLE_70__BapmVddGfxVidLoSidd_8__SHIFT 0x18 1209#define DPM_TABLE_71__BapmVddGfxVidLoSidd_15_MASK 0xff 1210#define DPM_TABLE_71__BapmVddGfxVidLoSidd_15__SHIFT 0x0 1211#define DPM_TABLE_71__BapmVddGfxVidLoSidd_14_MASK 0xff00 1212#define DPM_TABLE_71__BapmVddGfxVidLoSidd_14__SHIFT 0x8 1213#define DPM_TABLE_71__BapmVddGfxVidLoSidd_13_MASK 0xff0000 1214#define DPM_TABLE_71__BapmVddGfxVidLoSidd_13__SHIFT 0x10 1215#define DPM_TABLE_71__BapmVddGfxVidLoSidd_12_MASK 0xff000000 1216#define DPM_TABLE_71__BapmVddGfxVidLoSidd_12__SHIFT 0x18 1217#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_3_MASK 0xff 1218#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_3__SHIFT 0x0 1219#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_2_MASK 0xff00 1220#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_2__SHIFT 0x8 1221#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_1_MASK 0xff0000 1222#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_1__SHIFT 0x10 1223#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_0_MASK 0xff000000 1224#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_0__SHIFT 0x18 1225#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_7_MASK 0xff 1226#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_7__SHIFT 0x0 1227#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_6_MASK 0xff00 1228#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_6__SHIFT 0x8 1229#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_5_MASK 0xff0000 1230#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_5__SHIFT 0x10 1231#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_4_MASK 0xff000000 1232#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_4__SHIFT 0x18 1233#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_11_MASK 0xff 1234#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_11__SHIFT 0x0 1235#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_10_MASK 0xff00 1236#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_10__SHIFT 0x8 1237#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_9_MASK 0xff0000 1238#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_9__SHIFT 0x10 1239#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_8_MASK 0xff000000 1240#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_8__SHIFT 0x18 1241#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_15_MASK 0xff 1242#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_15__SHIFT 0x0 1243#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_14_MASK 0xff00 1244#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_14__SHIFT 0x8 1245#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_13_MASK 0xff0000 1246#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_13__SHIFT 0x10 1247#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_12_MASK 0xff000000 1248#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_12__SHIFT 0x18 1249#define DPM_TABLE_76__BapmVddcVidHiSidd_3_MASK 0xff 1250#define DPM_TABLE_76__BapmVddcVidHiSidd_3__SHIFT 0x0 1251#define DPM_TABLE_76__BapmVddcVidHiSidd_2_MASK 0xff00 1252#define DPM_TABLE_76__BapmVddcVidHiSidd_2__SHIFT 0x8 1253#define DPM_TABLE_76__BapmVddcVidHiSidd_1_MASK 0xff0000 1254#define DPM_TABLE_76__BapmVddcVidHiSidd_1__SHIFT 0x10 1255#define DPM_TABLE_76__BapmVddcVidHiSidd_0_MASK 0xff000000 1256#define DPM_TABLE_76__BapmVddcVidHiSidd_0__SHIFT 0x18 1257#define DPM_TABLE_77__BapmVddcVidHiSidd_7_MASK 0xff 1258#define DPM_TABLE_77__BapmVddcVidHiSidd_7__SHIFT 0x0 1259#define DPM_TABLE_77__BapmVddcVidHiSidd_6_MASK 0xff00 1260#define DPM_TABLE_77__BapmVddcVidHiSidd_6__SHIFT 0x8 1261#define DPM_TABLE_77__BapmVddcVidHiSidd_5_MASK 0xff0000 1262#define DPM_TABLE_77__BapmVddcVidHiSidd_5__SHIFT 0x10 1263#define DPM_TABLE_77__BapmVddcVidHiSidd_4_MASK 0xff000000 1264#define DPM_TABLE_77__BapmVddcVidHiSidd_4__SHIFT 0x18 1265#define DPM_TABLE_78__BapmVddcVidHiSidd_11_MASK 0xff 1266#define DPM_TABLE_78__BapmVddcVidHiSidd_11__SHIFT 0x0 1267#define DPM_TABLE_78__BapmVddcVidHiSidd_10_MASK 0xff00 1268#define DPM_TABLE_78__BapmVddcVidHiSidd_10__SHIFT 0x8 1269#define DPM_TABLE_78__BapmVddcVidHiSidd_9_MASK 0xff0000 1270#define DPM_TABLE_78__BapmVddcVidHiSidd_9__SHIFT 0x10 1271#define DPM_TABLE_78__BapmVddcVidHiSidd_8_MASK 0xff000000 1272#define DPM_TABLE_78__BapmVddcVidHiSidd_8__SHIFT 0x18 1273#define DPM_TABLE_79__BapmVddcVidHiSidd_15_MASK 0xff 1274#define DPM_TABLE_79__BapmVddcVidHiSidd_15__SHIFT 0x0 1275#define DPM_TABLE_79__BapmVddcVidHiSidd_14_MASK 0xff00 1276#define DPM_TABLE_79__BapmVddcVidHiSidd_14__SHIFT 0x8 1277#define DPM_TABLE_79__BapmVddcVidHiSidd_13_MASK 0xff0000 1278#define DPM_TABLE_79__BapmVddcVidHiSidd_13__SHIFT 0x10 1279#define DPM_TABLE_79__BapmVddcVidHiSidd_12_MASK 0xff000000 1280#define DPM_TABLE_79__BapmVddcVidHiSidd_12__SHIFT 0x18 1281#define DPM_TABLE_80__BapmVddcVidLoSidd_3_MASK 0xff 1282#define DPM_TABLE_80__BapmVddcVidLoSidd_3__SHIFT 0x0 1283#define DPM_TABLE_80__BapmVddcVidLoSidd_2_MASK 0xff00 1284#define DPM_TABLE_80__BapmVddcVidLoSidd_2__SHIFT 0x8 1285#define DPM_TABLE_80__BapmVddcVidLoSidd_1_MASK 0xff0000 1286#define DPM_TABLE_80__BapmVddcVidLoSidd_1__SHIFT 0x10 1287#define DPM_TABLE_80__BapmVddcVidLoSidd_0_MASK 0xff000000 1288#define DPM_TABLE_80__BapmVddcVidLoSidd_0__SHIFT 0x18 1289#define DPM_TABLE_81__BapmVddcVidLoSidd_7_MASK 0xff 1290#define DPM_TABLE_81__BapmVddcVidLoSidd_7__SHIFT 0x0 1291#define DPM_TABLE_81__BapmVddcVidLoSidd_6_MASK 0xff00 1292#define DPM_TABLE_81__BapmVddcVidLoSidd_6__SHIFT 0x8 1293#define DPM_TABLE_81__BapmVddcVidLoSidd_5_MASK 0xff0000 1294#define DPM_TABLE_81__BapmVddcVidLoSidd_5__SHIFT 0x10 1295#define DPM_TABLE_81__BapmVddcVidLoSidd_4_MASK 0xff000000 1296#define DPM_TABLE_81__BapmVddcVidLoSidd_4__SHIFT 0x18 1297#define DPM_TABLE_82__BapmVddcVidLoSidd_11_MASK 0xff 1298#define DPM_TABLE_82__BapmVddcVidLoSidd_11__SHIFT 0x0 1299#define DPM_TABLE_82__BapmVddcVidLoSidd_10_MASK 0xff00 1300#define DPM_TABLE_82__BapmVddcVidLoSidd_10__SHIFT 0x8 1301#define DPM_TABLE_82__BapmVddcVidLoSidd_9_MASK 0xff0000 1302#define DPM_TABLE_82__BapmVddcVidLoSidd_9__SHIFT 0x10 1303#define DPM_TABLE_82__BapmVddcVidLoSidd_8_MASK 0xff000000 1304#define DPM_TABLE_82__BapmVddcVidLoSidd_8__SHIFT 0x18 1305#define DPM_TABLE_83__BapmVddcVidLoSidd_15_MASK 0xff 1306#define DPM_TABLE_83__BapmVddcVidLoSidd_15__SHIFT 0x0 1307#define DPM_TABLE_83__BapmVddcVidLoSidd_14_MASK 0xff00 1308#define DPM_TABLE_83__BapmVddcVidLoSidd_14__SHIFT 0x8 1309#define DPM_TABLE_83__BapmVddcVidLoSidd_13_MASK 0xff0000 1310#define DPM_TABLE_83__BapmVddcVidLoSidd_13__SHIFT 0x10 1311#define DPM_TABLE_83__BapmVddcVidLoSidd_12_MASK 0xff000000 1312#define DPM_TABLE_83__BapmVddcVidLoSidd_12__SHIFT 0x18 1313#define DPM_TABLE_84__BapmVddcVidHiSidd2_3_MASK 0xff 1314#define DPM_TABLE_84__BapmVddcVidHiSidd2_3__SHIFT 0x0 1315#define DPM_TABLE_84__BapmVddcVidHiSidd2_2_MASK 0xff00 1316#define DPM_TABLE_84__BapmVddcVidHiSidd2_2__SHIFT 0x8 1317#define DPM_TABLE_84__BapmVddcVidHiSidd2_1_MASK 0xff0000 1318#define DPM_TABLE_84__BapmVddcVidHiSidd2_1__SHIFT 0x10 1319#define DPM_TABLE_84__BapmVddcVidHiSidd2_0_MASK 0xff000000 1320#define DPM_TABLE_84__BapmVddcVidHiSidd2_0__SHIFT 0x18 1321#define DPM_TABLE_85__BapmVddcVidHiSidd2_7_MASK 0xff 1322#define DPM_TABLE_85__BapmVddcVidHiSidd2_7__SHIFT 0x0 1323#define DPM_TABLE_85__BapmVddcVidHiSidd2_6_MASK 0xff00 1324#define DPM_TABLE_85__BapmVddcVidHiSidd2_6__SHIFT 0x8 1325#define DPM_TABLE_85__BapmVddcVidHiSidd2_5_MASK 0xff0000 1326#define DPM_TABLE_85__BapmVddcVidHiSidd2_5__SHIFT 0x10 1327#define DPM_TABLE_85__BapmVddcVidHiSidd2_4_MASK 0xff000000 1328#define DPM_TABLE_85__BapmVddcVidHiSidd2_4__SHIFT 0x18 1329#define DPM_TABLE_86__BapmVddcVidHiSidd2_11_MASK 0xff 1330#define DPM_TABLE_86__BapmVddcVidHiSidd2_11__SHIFT 0x0 1331#define DPM_TABLE_86__BapmVddcVidHiSidd2_10_MASK 0xff00 1332#define DPM_TABLE_86__BapmVddcVidHiSidd2_10__SHIFT 0x8 1333#define DPM_TABLE_86__BapmVddcVidHiSidd2_9_MASK 0xff0000 1334#define DPM_TABLE_86__BapmVddcVidHiSidd2_9__SHIFT 0x10 1335#define DPM_TABLE_86__BapmVddcVidHiSidd2_8_MASK 0xff000000 1336#define DPM_TABLE_86__BapmVddcVidHiSidd2_8__SHIFT 0x18 1337#define DPM_TABLE_87__BapmVddcVidHiSidd2_15_MASK 0xff 1338#define DPM_TABLE_87__BapmVddcVidHiSidd2_15__SHIFT 0x0 1339#define DPM_TABLE_87__BapmVddcVidHiSidd2_14_MASK 0xff00 1340#define DPM_TABLE_87__BapmVddcVidHiSidd2_14__SHIFT 0x8 1341#define DPM_TABLE_87__BapmVddcVidHiSidd2_13_MASK 0xff0000 1342#define DPM_TABLE_87__BapmVddcVidHiSidd2_13__SHIFT 0x10 1343#define DPM_TABLE_87__BapmVddcVidHiSidd2_12_MASK 0xff000000 1344#define DPM_TABLE_87__BapmVddcVidHiSidd2_12__SHIFT 0x18 1345#define DPM_TABLE_88__MasterDeepSleepControl_MASK 0xff 1346#define DPM_TABLE_88__MasterDeepSleepControl__SHIFT 0x0 1347#define DPM_TABLE_88__LinkLevelCount_MASK 0xff00 1348#define DPM_TABLE_88__LinkLevelCount__SHIFT 0x8 1349#define DPM_TABLE_88__MemoryDpmLevelCount_MASK 0xff0000 1350#define DPM_TABLE_88__MemoryDpmLevelCount__SHIFT 0x10 1351#define DPM_TABLE_88__GraphicsDpmLevelCount_MASK 0xff000000 1352#define DPM_TABLE_88__GraphicsDpmLevelCount__SHIFT 0x18 1353#define DPM_TABLE_89__SamuLevelCount_MASK 0xff 1354#define DPM_TABLE_89__SamuLevelCount__SHIFT 0x0 1355#define DPM_TABLE_89__AcpLevelCount_MASK 0xff00 1356#define DPM_TABLE_89__AcpLevelCount__SHIFT 0x8 1357#define DPM_TABLE_89__VceLevelCount_MASK 0xff0000 1358#define DPM_TABLE_89__VceLevelCount__SHIFT 0x10 1359#define DPM_TABLE_89__UvdLevelCount_MASK 0xff000000 1360#define DPM_TABLE_89__UvdLevelCount__SHIFT 0x18 1361#define DPM_TABLE_90__Reserved_0_MASK 0xffffffff 1362#define DPM_TABLE_90__Reserved_0__SHIFT 0x0 1363#define DPM_TABLE_91__Reserved_1_MASK 0xffffffff 1364#define DPM_TABLE_91__Reserved_1__SHIFT 0x0 1365#define DPM_TABLE_92__Reserved_2_MASK 0xffffffff 1366#define DPM_TABLE_92__Reserved_2__SHIFT 0x0 1367#define DPM_TABLE_93__Reserved_3_MASK 0xffffffff 1368#define DPM_TABLE_93__Reserved_3__SHIFT 0x0 1369#define DPM_TABLE_94__Reserved_4_MASK 0xffffffff 1370#define DPM_TABLE_94__Reserved_4__SHIFT 0x0 1371#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Phases_MASK 0xff 1372#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Phases__SHIFT 0x0 1373#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_VddGfx_MASK 0xff00 1374#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_VddGfx__SHIFT 0x8 1375#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddci_MASK 0xff0000 1376#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddci__SHIFT 0x10 1377#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddc_MASK 0xff000000 1378#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddc__SHIFT 0x18 1379#define DPM_TABLE_96__GraphicsLevel_0_SclkFrequency_MASK 0xffffffff 1380#define DPM_TABLE_96__GraphicsLevel_0_SclkFrequency__SHIFT 0x0 1381#define DPM_TABLE_97__GraphicsLevel_0_ActivityLevel_MASK 0xffff 1382#define DPM_TABLE_97__GraphicsLevel_0_ActivityLevel__SHIFT 0x0 1383#define DPM_TABLE_97__GraphicsLevel_0_DeepSleepDivId_MASK 0xff0000 1384#define DPM_TABLE_97__GraphicsLevel_0_DeepSleepDivId__SHIFT 0x10 1385#define DPM_TABLE_97__GraphicsLevel_0_pcieDpmLevel_MASK 0xff000000 1386#define DPM_TABLE_97__GraphicsLevel_0_pcieDpmLevel__SHIFT 0x18 1387#define DPM_TABLE_98__GraphicsLevel_0_CgSpllFuncCntl3_MASK 0xffffffff 1388#define DPM_TABLE_98__GraphicsLevel_0_CgSpllFuncCntl3__SHIFT 0x0 1389#define DPM_TABLE_99__GraphicsLevel_0_CgSpllFuncCntl4_MASK 0xffffffff 1390#define DPM_TABLE_99__GraphicsLevel_0_CgSpllFuncCntl4__SHIFT 0x0 1391#define DPM_TABLE_100__GraphicsLevel_0_SpllSpreadSpectrum_MASK 0xffffffff 1392#define DPM_TABLE_100__GraphicsLevel_0_SpllSpreadSpectrum__SHIFT 0x0 1393#define DPM_TABLE_101__GraphicsLevel_0_SpllSpreadSpectrum2_MASK 0xffffffff 1394#define DPM_TABLE_101__GraphicsLevel_0_SpllSpreadSpectrum2__SHIFT 0x0 1395#define DPM_TABLE_102__GraphicsLevel_0_CcPwrDynRm_MASK 0xffffffff 1396#define DPM_TABLE_102__GraphicsLevel_0_CcPwrDynRm__SHIFT 0x0 1397#define DPM_TABLE_103__GraphicsLevel_0_CcPwrDynRm1_MASK 0xffffffff 1398#define DPM_TABLE_103__GraphicsLevel_0_CcPwrDynRm1__SHIFT 0x0 1399#define DPM_TABLE_104__GraphicsLevel_0_EnabledForThrottle_MASK 0xff 1400#define DPM_TABLE_104__GraphicsLevel_0_EnabledForThrottle__SHIFT 0x0 1401#define DPM_TABLE_104__GraphicsLevel_0_EnabledForActivity_MASK 0xff00 1402#define DPM_TABLE_104__GraphicsLevel_0_EnabledForActivity__SHIFT 0x8 1403#define DPM_TABLE_104__GraphicsLevel_0_DisplayWatermark_MASK 0xff0000 1404#define DPM_TABLE_104__GraphicsLevel_0_DisplayWatermark__SHIFT 0x10 1405#define DPM_TABLE_104__GraphicsLevel_0_SclkDid_MASK 0xff000000 1406#define DPM_TABLE_104__GraphicsLevel_0_SclkDid__SHIFT 0x18 1407#define DPM_TABLE_105__GraphicsLevel_0_PowerThrottle_MASK 0xff 1408#define DPM_TABLE_105__GraphicsLevel_0_PowerThrottle__SHIFT 0x0 1409#define DPM_TABLE_105__GraphicsLevel_0_VoltageDownHyst_MASK 0xff00 1410#define DPM_TABLE_105__GraphicsLevel_0_VoltageDownHyst__SHIFT 0x8 1411#define DPM_TABLE_105__GraphicsLevel_0_DownHyst_MASK 0xff0000 1412#define DPM_TABLE_105__GraphicsLevel_0_DownHyst__SHIFT 0x10 1413#define DPM_TABLE_105__GraphicsLevel_0_UpHyst_MASK 0xff000000 1414#define DPM_TABLE_105__GraphicsLevel_0_UpHyst__SHIFT 0x18 1415#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Phases_MASK 0xff 1416#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Phases__SHIFT 0x0 1417#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_VddGfx_MASK 0xff00 1418#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_VddGfx__SHIFT 0x8 1419#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddci_MASK 0xff0000 1420#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddci__SHIFT 0x10 1421#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddc_MASK 0xff000000 1422#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddc__SHIFT 0x18 1423#define DPM_TABLE_107__GraphicsLevel_1_SclkFrequency_MASK 0xffffffff 1424#define DPM_TABLE_107__GraphicsLevel_1_SclkFrequency__SHIFT 0x0 1425#define DPM_TABLE_108__GraphicsLevel_1_ActivityLevel_MASK 0xffff 1426#define DPM_TABLE_108__GraphicsLevel_1_ActivityLevel__SHIFT 0x0 1427#define DPM_TABLE_108__GraphicsLevel_1_DeepSleepDivId_MASK 0xff0000 1428#define DPM_TABLE_108__GraphicsLevel_1_DeepSleepDivId__SHIFT 0x10 1429#define DPM_TABLE_108__GraphicsLevel_1_pcieDpmLevel_MASK 0xff000000 1430#define DPM_TABLE_108__GraphicsLevel_1_pcieDpmLevel__SHIFT 0x18 1431#define DPM_TABLE_109__GraphicsLevel_1_CgSpllFuncCntl3_MASK 0xffffffff 1432#define DPM_TABLE_109__GraphicsLevel_1_CgSpllFuncCntl3__SHIFT 0x0 1433#define DPM_TABLE_110__GraphicsLevel_1_CgSpllFuncCntl4_MASK 0xffffffff 1434#define DPM_TABLE_110__GraphicsLevel_1_CgSpllFuncCntl4__SHIFT 0x0 1435#define DPM_TABLE_111__GraphicsLevel_1_SpllSpreadSpectrum_MASK 0xffffffff 1436#define DPM_TABLE_111__GraphicsLevel_1_SpllSpreadSpectrum__SHIFT 0x0 1437#define DPM_TABLE_112__GraphicsLevel_1_SpllSpreadSpectrum2_MASK 0xffffffff 1438#define DPM_TABLE_112__GraphicsLevel_1_SpllSpreadSpectrum2__SHIFT 0x0 1439#define DPM_TABLE_113__GraphicsLevel_1_CcPwrDynRm_MASK 0xffffffff 1440#define DPM_TABLE_113__GraphicsLevel_1_CcPwrDynRm__SHIFT 0x0 1441#define DPM_TABLE_114__GraphicsLevel_1_CcPwrDynRm1_MASK 0xffffffff 1442#define DPM_TABLE_114__GraphicsLevel_1_CcPwrDynRm1__SHIFT 0x0 1443#define DPM_TABLE_115__GraphicsLevel_1_EnabledForThrottle_MASK 0xff 1444#define DPM_TABLE_115__GraphicsLevel_1_EnabledForThrottle__SHIFT 0x0 1445#define DPM_TABLE_115__GraphicsLevel_1_EnabledForActivity_MASK 0xff00 1446#define DPM_TABLE_115__GraphicsLevel_1_EnabledForActivity__SHIFT 0x8 1447#define DPM_TABLE_115__GraphicsLevel_1_DisplayWatermark_MASK 0xff0000 1448#define DPM_TABLE_115__GraphicsLevel_1_DisplayWatermark__SHIFT 0x10 1449#define DPM_TABLE_115__GraphicsLevel_1_SclkDid_MASK 0xff000000 1450#define DPM_TABLE_115__GraphicsLevel_1_SclkDid__SHIFT 0x18 1451#define DPM_TABLE_116__GraphicsLevel_1_PowerThrottle_MASK 0xff 1452#define DPM_TABLE_116__GraphicsLevel_1_PowerThrottle__SHIFT 0x0 1453#define DPM_TABLE_116__GraphicsLevel_1_VoltageDownHyst_MASK 0xff00 1454#define DPM_TABLE_116__GraphicsLevel_1_VoltageDownHyst__SHIFT 0x8 1455#define DPM_TABLE_116__GraphicsLevel_1_DownHyst_MASK 0xff0000 1456#define DPM_TABLE_116__GraphicsLevel_1_DownHyst__SHIFT 0x10 1457#define DPM_TABLE_116__GraphicsLevel_1_UpHyst_MASK 0xff000000 1458#define DPM_TABLE_116__GraphicsLevel_1_UpHyst__SHIFT 0x18 1459#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Phases_MASK 0xff 1460#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Phases__SHIFT 0x0 1461#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_VddGfx_MASK 0xff00 1462#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_VddGfx__SHIFT 0x8 1463#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddci_MASK 0xff0000 1464#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddci__SHIFT 0x10 1465#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddc_MASK 0xff000000 1466#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddc__SHIFT 0x18 1467#define DPM_TABLE_118__GraphicsLevel_2_SclkFrequency_MASK 0xffffffff 1468#define DPM_TABLE_118__GraphicsLevel_2_SclkFrequency__SHIFT 0x0 1469#define DPM_TABLE_119__GraphicsLevel_2_ActivityLevel_MASK 0xffff 1470#define DPM_TABLE_119__GraphicsLevel_2_ActivityLevel__SHIFT 0x0 1471#define DPM_TABLE_119__GraphicsLevel_2_DeepSleepDivId_MASK 0xff0000 1472#define DPM_TABLE_119__GraphicsLevel_2_DeepSleepDivId__SHIFT 0x10 1473#define DPM_TABLE_119__GraphicsLevel_2_pcieDpmLevel_MASK 0xff000000 1474#define DPM_TABLE_119__GraphicsLevel_2_pcieDpmLevel__SHIFT 0x18 1475#define DPM_TABLE_120__GraphicsLevel_2_CgSpllFuncCntl3_MASK 0xffffffff 1476#define DPM_TABLE_120__GraphicsLevel_2_CgSpllFuncCntl3__SHIFT 0x0 1477#define DPM_TABLE_121__GraphicsLevel_2_CgSpllFuncCntl4_MASK 0xffffffff 1478#define DPM_TABLE_121__GraphicsLevel_2_CgSpllFuncCntl4__SHIFT 0x0 1479#define DPM_TABLE_122__GraphicsLevel_2_SpllSpreadSpectrum_MASK 0xffffffff 1480#define DPM_TABLE_122__GraphicsLevel_2_SpllSpreadSpectrum__SHIFT 0x0 1481#define DPM_TABLE_123__GraphicsLevel_2_SpllSpreadSpectrum2_MASK 0xffffffff 1482#define DPM_TABLE_123__GraphicsLevel_2_SpllSpreadSpectrum2__SHIFT 0x0 1483#define DPM_TABLE_124__GraphicsLevel_2_CcPwrDynRm_MASK 0xffffffff 1484#define DPM_TABLE_124__GraphicsLevel_2_CcPwrDynRm__SHIFT 0x0 1485#define DPM_TABLE_125__GraphicsLevel_2_CcPwrDynRm1_MASK 0xffffffff 1486#define DPM_TABLE_125__GraphicsLevel_2_CcPwrDynRm1__SHIFT 0x0 1487#define DPM_TABLE_126__GraphicsLevel_2_EnabledForThrottle_MASK 0xff 1488#define DPM_TABLE_126__GraphicsLevel_2_EnabledForThrottle__SHIFT 0x0 1489#define DPM_TABLE_126__GraphicsLevel_2_EnabledForActivity_MASK 0xff00 1490#define DPM_TABLE_126__GraphicsLevel_2_EnabledForActivity__SHIFT 0x8 1491#define DPM_TABLE_126__GraphicsLevel_2_DisplayWatermark_MASK 0xff0000 1492#define DPM_TABLE_126__GraphicsLevel_2_DisplayWatermark__SHIFT 0x10 1493#define DPM_TABLE_126__GraphicsLevel_2_SclkDid_MASK 0xff000000 1494#define DPM_TABLE_126__GraphicsLevel_2_SclkDid__SHIFT 0x18 1495#define DPM_TABLE_127__GraphicsLevel_2_PowerThrottle_MASK 0xff 1496#define DPM_TABLE_127__GraphicsLevel_2_PowerThrottle__SHIFT 0x0 1497#define DPM_TABLE_127__GraphicsLevel_2_VoltageDownHyst_MASK 0xff00 1498#define DPM_TABLE_127__GraphicsLevel_2_VoltageDownHyst__SHIFT 0x8 1499#define DPM_TABLE_127__GraphicsLevel_2_DownHyst_MASK 0xff0000 1500#define DPM_TABLE_127__GraphicsLevel_2_DownHyst__SHIFT 0x10 1501#define DPM_TABLE_127__GraphicsLevel_2_UpHyst_MASK 0xff000000 1502#define DPM_TABLE_127__GraphicsLevel_2_UpHyst__SHIFT 0x18 1503#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Phases_MASK 0xff 1504#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Phases__SHIFT 0x0 1505#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_VddGfx_MASK 0xff00 1506#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_VddGfx__SHIFT 0x8 1507#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddci_MASK 0xff0000 1508#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddci__SHIFT 0x10 1509#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddc_MASK 0xff000000 1510#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddc__SHIFT 0x18 1511#define DPM_TABLE_129__GraphicsLevel_3_SclkFrequency_MASK 0xffffffff 1512#define DPM_TABLE_129__GraphicsLevel_3_SclkFrequency__SHIFT 0x0 1513#define DPM_TABLE_130__GraphicsLevel_3_ActivityLevel_MASK 0xffff 1514#define DPM_TABLE_130__GraphicsLevel_3_ActivityLevel__SHIFT 0x0 1515#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId_MASK 0xff0000 1516#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId__SHIFT 0x10 1517#define DPM_TABLE_130__GraphicsLevel_3_pcieDpmLevel_MASK 0xff000000 1518#define DPM_TABLE_130__GraphicsLevel_3_pcieDpmLevel__SHIFT 0x18 1519#define DPM_TABLE_131__GraphicsLevel_3_CgSpllFuncCntl3_MASK 0xffffffff 1520#define DPM_TABLE_131__GraphicsLevel_3_CgSpllFuncCntl3__SHIFT 0x0 1521#define DPM_TABLE_132__GraphicsLevel_3_CgSpllFuncCntl4_MASK 0xffffffff 1522#define DPM_TABLE_132__GraphicsLevel_3_CgSpllFuncCntl4__SHIFT 0x0 1523#define DPM_TABLE_133__GraphicsLevel_3_SpllSpreadSpectrum_MASK 0xffffffff 1524#define DPM_TABLE_133__GraphicsLevel_3_SpllSpreadSpectrum__SHIFT 0x0 1525#define DPM_TABLE_134__GraphicsLevel_3_SpllSpreadSpectrum2_MASK 0xffffffff 1526#define DPM_TABLE_134__GraphicsLevel_3_SpllSpreadSpectrum2__SHIFT 0x0 1527#define DPM_TABLE_135__GraphicsLevel_3_CcPwrDynRm_MASK 0xffffffff 1528#define DPM_TABLE_135__GraphicsLevel_3_CcPwrDynRm__SHIFT 0x0 1529#define DPM_TABLE_136__GraphicsLevel_3_CcPwrDynRm1_MASK 0xffffffff 1530#define DPM_TABLE_136__GraphicsLevel_3_CcPwrDynRm1__SHIFT 0x0 1531#define DPM_TABLE_137__GraphicsLevel_3_EnabledForThrottle_MASK 0xff 1532#define DPM_TABLE_137__GraphicsLevel_3_EnabledForThrottle__SHIFT 0x0 1533#define DPM_TABLE_137__GraphicsLevel_3_EnabledForActivity_MASK 0xff00 1534#define DPM_TABLE_137__GraphicsLevel_3_EnabledForActivity__SHIFT 0x8 1535#define DPM_TABLE_137__GraphicsLevel_3_DisplayWatermark_MASK 0xff0000 1536#define DPM_TABLE_137__GraphicsLevel_3_DisplayWatermark__SHIFT 0x10 1537#define DPM_TABLE_137__GraphicsLevel_3_SclkDid_MASK 0xff000000 1538#define DPM_TABLE_137__GraphicsLevel_3_SclkDid__SHIFT 0x18 1539#define DPM_TABLE_138__GraphicsLevel_3_PowerThrottle_MASK 0xff 1540#define DPM_TABLE_138__GraphicsLevel_3_PowerThrottle__SHIFT 0x0 1541#define DPM_TABLE_138__GraphicsLevel_3_VoltageDownHyst_MASK 0xff00 1542#define DPM_TABLE_138__GraphicsLevel_3_VoltageDownHyst__SHIFT 0x8 1543#define DPM_TABLE_138__GraphicsLevel_3_DownHyst_MASK 0xff0000 1544#define DPM_TABLE_138__GraphicsLevel_3_DownHyst__SHIFT 0x10 1545#define DPM_TABLE_138__GraphicsLevel_3_UpHyst_MASK 0xff000000 1546#define DPM_TABLE_138__GraphicsLevel_3_UpHyst__SHIFT 0x18 1547#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Phases_MASK 0xff 1548#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Phases__SHIFT 0x0 1549#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_VddGfx_MASK 0xff00 1550#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_VddGfx__SHIFT 0x8 1551#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddci_MASK 0xff0000 1552#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddci__SHIFT 0x10 1553#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddc_MASK 0xff000000 1554#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddc__SHIFT 0x18 1555#define DPM_TABLE_140__GraphicsLevel_4_SclkFrequency_MASK 0xffffffff 1556#define DPM_TABLE_140__GraphicsLevel_4_SclkFrequency__SHIFT 0x0 1557#define DPM_TABLE_141__GraphicsLevel_4_ActivityLevel_MASK 0xffff 1558#define DPM_TABLE_141__GraphicsLevel_4_ActivityLevel__SHIFT 0x0 1559#define DPM_TABLE_141__GraphicsLevel_4_DeepSleepDivId_MASK 0xff0000 1560#define DPM_TABLE_141__GraphicsLevel_4_DeepSleepDivId__SHIFT 0x10 1561#define DPM_TABLE_141__GraphicsLevel_4_pcieDpmLevel_MASK 0xff000000 1562#define DPM_TABLE_141__GraphicsLevel_4_pcieDpmLevel__SHIFT 0x18 1563#define DPM_TABLE_142__GraphicsLevel_4_CgSpllFuncCntl3_MASK 0xffffffff 1564#define DPM_TABLE_142__GraphicsLevel_4_CgSpllFuncCntl3__SHIFT 0x0 1565#define DPM_TABLE_143__GraphicsLevel_4_CgSpllFuncCntl4_MASK 0xffffffff 1566#define DPM_TABLE_143__GraphicsLevel_4_CgSpllFuncCntl4__SHIFT 0x0 1567#define DPM_TABLE_144__GraphicsLevel_4_SpllSpreadSpectrum_MASK 0xffffffff 1568#define DPM_TABLE_144__GraphicsLevel_4_SpllSpreadSpectrum__SHIFT 0x0 1569#define DPM_TABLE_145__GraphicsLevel_4_SpllSpreadSpectrum2_MASK 0xffffffff 1570#define DPM_TABLE_145__GraphicsLevel_4_SpllSpreadSpectrum2__SHIFT 0x0 1571#define DPM_TABLE_146__GraphicsLevel_4_CcPwrDynRm_MASK 0xffffffff 1572#define DPM_TABLE_146__GraphicsLevel_4_CcPwrDynRm__SHIFT 0x0 1573#define DPM_TABLE_147__GraphicsLevel_4_CcPwrDynRm1_MASK 0xffffffff 1574#define DPM_TABLE_147__GraphicsLevel_4_CcPwrDynRm1__SHIFT 0x0 1575#define DPM_TABLE_148__GraphicsLevel_4_EnabledForThrottle_MASK 0xff 1576#define DPM_TABLE_148__GraphicsLevel_4_EnabledForThrottle__SHIFT 0x0 1577#define DPM_TABLE_148__GraphicsLevel_4_EnabledForActivity_MASK 0xff00 1578#define DPM_TABLE_148__GraphicsLevel_4_EnabledForActivity__SHIFT 0x8 1579#define DPM_TABLE_148__GraphicsLevel_4_DisplayWatermark_MASK 0xff0000 1580#define DPM_TABLE_148__GraphicsLevel_4_DisplayWatermark__SHIFT 0x10 1581#define DPM_TABLE_148__GraphicsLevel_4_SclkDid_MASK 0xff000000 1582#define DPM_TABLE_148__GraphicsLevel_4_SclkDid__SHIFT 0x18 1583#define DPM_TABLE_149__GraphicsLevel_4_PowerThrottle_MASK 0xff 1584#define DPM_TABLE_149__GraphicsLevel_4_PowerThrottle__SHIFT 0x0 1585#define DPM_TABLE_149__GraphicsLevel_4_VoltageDownHyst_MASK 0xff00 1586#define DPM_TABLE_149__GraphicsLevel_4_VoltageDownHyst__SHIFT 0x8 1587#define DPM_TABLE_149__GraphicsLevel_4_DownHyst_MASK 0xff0000 1588#define DPM_TABLE_149__GraphicsLevel_4_DownHyst__SHIFT 0x10 1589#define DPM_TABLE_149__GraphicsLevel_4_UpHyst_MASK 0xff000000 1590#define DPM_TABLE_149__GraphicsLevel_4_UpHyst__SHIFT 0x18 1591#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Phases_MASK 0xff 1592#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Phases__SHIFT 0x0 1593#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_VddGfx_MASK 0xff00 1594#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_VddGfx__SHIFT 0x8 1595#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddci_MASK 0xff0000 1596#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddci__SHIFT 0x10 1597#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddc_MASK 0xff000000 1598#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddc__SHIFT 0x18 1599#define DPM_TABLE_151__GraphicsLevel_5_SclkFrequency_MASK 0xffffffff 1600#define DPM_TABLE_151__GraphicsLevel_5_SclkFrequency__SHIFT 0x0 1601#define DPM_TABLE_152__GraphicsLevel_5_ActivityLevel_MASK 0xffff 1602#define DPM_TABLE_152__GraphicsLevel_5_ActivityLevel__SHIFT 0x0 1603#define DPM_TABLE_152__GraphicsLevel_5_DeepSleepDivId_MASK 0xff0000 1604#define DPM_TABLE_152__GraphicsLevel_5_DeepSleepDivId__SHIFT 0x10 1605#define DPM_TABLE_152__GraphicsLevel_5_pcieDpmLevel_MASK 0xff000000 1606#define DPM_TABLE_152__GraphicsLevel_5_pcieDpmLevel__SHIFT 0x18 1607#define DPM_TABLE_153__GraphicsLevel_5_CgSpllFuncCntl3_MASK 0xffffffff 1608#define DPM_TABLE_153__GraphicsLevel_5_CgSpllFuncCntl3__SHIFT 0x0 1609#define DPM_TABLE_154__GraphicsLevel_5_CgSpllFuncCntl4_MASK 0xffffffff 1610#define DPM_TABLE_154__GraphicsLevel_5_CgSpllFuncCntl4__SHIFT 0x0 1611#define DPM_TABLE_155__GraphicsLevel_5_SpllSpreadSpectrum_MASK 0xffffffff 1612#define DPM_TABLE_155__GraphicsLevel_5_SpllSpreadSpectrum__SHIFT 0x0 1613#define DPM_TABLE_156__GraphicsLevel_5_SpllSpreadSpectrum2_MASK 0xffffffff 1614#define DPM_TABLE_156__GraphicsLevel_5_SpllSpreadSpectrum2__SHIFT 0x0 1615#define DPM_TABLE_157__GraphicsLevel_5_CcPwrDynRm_MASK 0xffffffff 1616#define DPM_TABLE_157__GraphicsLevel_5_CcPwrDynRm__SHIFT 0x0 1617#define DPM_TABLE_158__GraphicsLevel_5_CcPwrDynRm1_MASK 0xffffffff 1618#define DPM_TABLE_158__GraphicsLevel_5_CcPwrDynRm1__SHIFT 0x0 1619#define DPM_TABLE_159__GraphicsLevel_5_EnabledForThrottle_MASK 0xff 1620#define DPM_TABLE_159__GraphicsLevel_5_EnabledForThrottle__SHIFT 0x0 1621#define DPM_TABLE_159__GraphicsLevel_5_EnabledForActivity_MASK 0xff00 1622#define DPM_TABLE_159__GraphicsLevel_5_EnabledForActivity__SHIFT 0x8 1623#define DPM_TABLE_159__GraphicsLevel_5_DisplayWatermark_MASK 0xff0000 1624#define DPM_TABLE_159__GraphicsLevel_5_DisplayWatermark__SHIFT 0x10 1625#define DPM_TABLE_159__GraphicsLevel_5_SclkDid_MASK 0xff000000 1626#define DPM_TABLE_159__GraphicsLevel_5_SclkDid__SHIFT 0x18 1627#define DPM_TABLE_160__GraphicsLevel_5_PowerThrottle_MASK 0xff 1628#define DPM_TABLE_160__GraphicsLevel_5_PowerThrottle__SHIFT 0x0 1629#define DPM_TABLE_160__GraphicsLevel_5_VoltageDownHyst_MASK 0xff00 1630#define DPM_TABLE_160__GraphicsLevel_5_VoltageDownHyst__SHIFT 0x8 1631#define DPM_TABLE_160__GraphicsLevel_5_DownHyst_MASK 0xff0000 1632#define DPM_TABLE_160__GraphicsLevel_5_DownHyst__SHIFT 0x10 1633#define DPM_TABLE_160__GraphicsLevel_5_UpHyst_MASK 0xff000000 1634#define DPM_TABLE_160__GraphicsLevel_5_UpHyst__SHIFT 0x18 1635#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Phases_MASK 0xff 1636#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Phases__SHIFT 0x0 1637#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_VddGfx_MASK 0xff00 1638#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_VddGfx__SHIFT 0x8 1639#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddci_MASK 0xff0000 1640#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddci__SHIFT 0x10 1641#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddc_MASK 0xff000000 1642#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddc__SHIFT 0x18 1643#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency_MASK 0xffffffff 1644#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency__SHIFT 0x0 1645#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel_MASK 0xffff 1646#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel__SHIFT 0x0 1647#define DPM_TABLE_163__GraphicsLevel_6_DeepSleepDivId_MASK 0xff0000 1648#define DPM_TABLE_163__GraphicsLevel_6_DeepSleepDivId__SHIFT 0x10 1649#define DPM_TABLE_163__GraphicsLevel_6_pcieDpmLevel_MASK 0xff000000 1650#define DPM_TABLE_163__GraphicsLevel_6_pcieDpmLevel__SHIFT 0x18 1651#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3_MASK 0xffffffff 1652#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3__SHIFT 0x0 1653#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4_MASK 0xffffffff 1654#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4__SHIFT 0x0 1655#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum_MASK 0xffffffff 1656#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum__SHIFT 0x0 1657#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2_MASK 0xffffffff 1658#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2__SHIFT 0x0 1659#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm_MASK 0xffffffff 1660#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm__SHIFT 0x0 1661#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1_MASK 0xffffffff 1662#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1__SHIFT 0x0 1663#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle_MASK 0xff 1664#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle__SHIFT 0x0 1665#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity_MASK 0xff00 1666#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity__SHIFT 0x8 1667#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark_MASK 0xff0000 1668#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark__SHIFT 0x10 1669#define DPM_TABLE_170__GraphicsLevel_6_SclkDid_MASK 0xff000000 1670#define DPM_TABLE_170__GraphicsLevel_6_SclkDid__SHIFT 0x18 1671#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle_MASK 0xff 1672#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle__SHIFT 0x0 1673#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst_MASK 0xff00 1674#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst__SHIFT 0x8 1675#define DPM_TABLE_171__GraphicsLevel_6_DownHyst_MASK 0xff0000 1676#define DPM_TABLE_171__GraphicsLevel_6_DownHyst__SHIFT 0x10 1677#define DPM_TABLE_171__GraphicsLevel_6_UpHyst_MASK 0xff000000 1678#define DPM_TABLE_171__GraphicsLevel_6_UpHyst__SHIFT 0x18 1679#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Phases_MASK 0xff 1680#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Phases__SHIFT 0x0 1681#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_VddGfx_MASK 0xff00 1682#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_VddGfx__SHIFT 0x8 1683#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddci_MASK 0xff0000 1684#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddci__SHIFT 0x10 1685#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddc_MASK 0xff000000 1686#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddc__SHIFT 0x18 1687#define DPM_TABLE_173__GraphicsLevel_7_SclkFrequency_MASK 0xffffffff 1688#define DPM_TABLE_173__GraphicsLevel_7_SclkFrequency__SHIFT 0x0 1689#define DPM_TABLE_174__GraphicsLevel_7_ActivityLevel_MASK 0xffff 1690#define DPM_TABLE_174__GraphicsLevel_7_ActivityLevel__SHIFT 0x0 1691#define DPM_TABLE_174__GraphicsLevel_7_DeepSleepDivId_MASK 0xff0000 1692#define DPM_TABLE_174__GraphicsLevel_7_DeepSleepDivId__SHIFT 0x10 1693#define DPM_TABLE_174__GraphicsLevel_7_pcieDpmLevel_MASK 0xff000000 1694#define DPM_TABLE_174__GraphicsLevel_7_pcieDpmLevel__SHIFT 0x18 1695#define DPM_TABLE_175__GraphicsLevel_7_CgSpllFuncCntl3_MASK 0xffffffff 1696#define DPM_TABLE_175__GraphicsLevel_7_CgSpllFuncCntl3__SHIFT 0x0 1697#define DPM_TABLE_176__GraphicsLevel_7_CgSpllFuncCntl4_MASK 0xffffffff 1698#define DPM_TABLE_176__GraphicsLevel_7_CgSpllFuncCntl4__SHIFT 0x0 1699#define DPM_TABLE_177__GraphicsLevel_7_SpllSpreadSpectrum_MASK 0xffffffff 1700#define DPM_TABLE_177__GraphicsLevel_7_SpllSpreadSpectrum__SHIFT 0x0 1701#define DPM_TABLE_178__GraphicsLevel_7_SpllSpreadSpectrum2_MASK 0xffffffff 1702#define DPM_TABLE_178__GraphicsLevel_7_SpllSpreadSpectrum2__SHIFT 0x0 1703#define DPM_TABLE_179__GraphicsLevel_7_CcPwrDynRm_MASK 0xffffffff 1704#define DPM_TABLE_179__GraphicsLevel_7_CcPwrDynRm__SHIFT 0x0 1705#define DPM_TABLE_180__GraphicsLevel_7_CcPwrDynRm1_MASK 0xffffffff 1706#define DPM_TABLE_180__GraphicsLevel_7_CcPwrDynRm1__SHIFT 0x0 1707#define DPM_TABLE_181__GraphicsLevel_7_EnabledForThrottle_MASK 0xff 1708#define DPM_TABLE_181__GraphicsLevel_7_EnabledForThrottle__SHIFT 0x0 1709#define DPM_TABLE_181__GraphicsLevel_7_EnabledForActivity_MASK 0xff00 1710#define DPM_TABLE_181__GraphicsLevel_7_EnabledForActivity__SHIFT 0x8 1711#define DPM_TABLE_181__GraphicsLevel_7_DisplayWatermark_MASK 0xff0000 1712#define DPM_TABLE_181__GraphicsLevel_7_DisplayWatermark__SHIFT 0x10 1713#define DPM_TABLE_181__GraphicsLevel_7_SclkDid_MASK 0xff000000 1714#define DPM_TABLE_181__GraphicsLevel_7_SclkDid__SHIFT 0x18 1715#define DPM_TABLE_182__GraphicsLevel_7_PowerThrottle_MASK 0xff 1716#define DPM_TABLE_182__GraphicsLevel_7_PowerThrottle__SHIFT 0x0 1717#define DPM_TABLE_182__GraphicsLevel_7_VoltageDownHyst_MASK 0xff00 1718#define DPM_TABLE_182__GraphicsLevel_7_VoltageDownHyst__SHIFT 0x8 1719#define DPM_TABLE_182__GraphicsLevel_7_DownHyst_MASK 0xff0000 1720#define DPM_TABLE_182__GraphicsLevel_7_DownHyst__SHIFT 0x10 1721#define DPM_TABLE_182__GraphicsLevel_7_UpHyst_MASK 0xff000000 1722#define DPM_TABLE_182__GraphicsLevel_7_UpHyst__SHIFT 0x18 1723#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Phases_MASK 0xff 1724#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Phases__SHIFT 0x0 1725#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_VddGfx_MASK 0xff00 1726#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_VddGfx__SHIFT 0x8 1727#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddci_MASK 0xff0000 1728#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddci__SHIFT 0x10 1729#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddc_MASK 0xff000000 1730#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddc__SHIFT 0x18 1731#define DPM_TABLE_184__MemoryACPILevel_MinMvdd_MASK 0xffffffff 1732#define DPM_TABLE_184__MemoryACPILevel_MinMvdd__SHIFT 0x0 1733#define DPM_TABLE_185__MemoryACPILevel_MclkFrequency_MASK 0xffffffff 1734#define DPM_TABLE_185__MemoryACPILevel_MclkFrequency__SHIFT 0x0 1735#define DPM_TABLE_186__MemoryACPILevel_StutterEnable_MASK 0xff 1736#define DPM_TABLE_186__MemoryACPILevel_StutterEnable__SHIFT 0x0 1737#define DPM_TABLE_186__MemoryACPILevel_RttEnable_MASK 0xff00 1738#define DPM_TABLE_186__MemoryACPILevel_RttEnable__SHIFT 0x8 1739#define DPM_TABLE_186__MemoryACPILevel_EdcWriteEnable_MASK 0xff0000 1740#define DPM_TABLE_186__MemoryACPILevel_EdcWriteEnable__SHIFT 0x10 1741#define DPM_TABLE_186__MemoryACPILevel_EdcReadEnable_MASK 0xff000000 1742#define DPM_TABLE_186__MemoryACPILevel_EdcReadEnable__SHIFT 0x18 1743#define DPM_TABLE_187__MemoryACPILevel_EnabledForActivity_MASK 0xff 1744#define DPM_TABLE_187__MemoryACPILevel_EnabledForActivity__SHIFT 0x0 1745#define DPM_TABLE_187__MemoryACPILevel_EnabledForThrottle_MASK 0xff00 1746#define DPM_TABLE_187__MemoryACPILevel_EnabledForThrottle__SHIFT 0x8 1747#define DPM_TABLE_187__MemoryACPILevel_StrobeRatio_MASK 0xff0000 1748#define DPM_TABLE_187__MemoryACPILevel_StrobeRatio__SHIFT 0x10 1749#define DPM_TABLE_187__MemoryACPILevel_StrobeEnable_MASK 0xff000000 1750#define DPM_TABLE_187__MemoryACPILevel_StrobeEnable__SHIFT 0x18 1751#define DPM_TABLE_188__MemoryACPILevel_padding_MASK 0xff 1752#define DPM_TABLE_188__MemoryACPILevel_padding__SHIFT 0x0 1753#define DPM_TABLE_188__MemoryACPILevel_VoltageDownHyst_MASK 0xff00 1754#define DPM_TABLE_188__MemoryACPILevel_VoltageDownHyst__SHIFT 0x8 1755#define DPM_TABLE_188__MemoryACPILevel_DownHyst_MASK 0xff0000 1756#define DPM_TABLE_188__MemoryACPILevel_DownHyst__SHIFT 0x10 1757#define DPM_TABLE_188__MemoryACPILevel_UpHyst_MASK 0xff000000 1758#define DPM_TABLE_188__MemoryACPILevel_UpHyst__SHIFT 0x18 1759#define DPM_TABLE_189__MemoryACPILevel_padding1_MASK 0xff 1760#define DPM_TABLE_189__MemoryACPILevel_padding1__SHIFT 0x0 1761#define DPM_TABLE_189__MemoryACPILevel_DisplayWatermark_MASK 0xff00 1762#define DPM_TABLE_189__MemoryACPILevel_DisplayWatermark__SHIFT 0x8 1763#define DPM_TABLE_189__MemoryACPILevel_ActivityLevel_MASK 0xffff0000 1764#define DPM_TABLE_189__MemoryACPILevel_ActivityLevel__SHIFT 0x10 1765#define DPM_TABLE_190__MemoryACPILevel_MpllFuncCntl_MASK 0xffffffff 1766#define DPM_TABLE_190__MemoryACPILevel_MpllFuncCntl__SHIFT 0x0 1767#define DPM_TABLE_191__MemoryACPILevel_MpllFuncCntl_1_MASK 0xffffffff 1768#define DPM_TABLE_191__MemoryACPILevel_MpllFuncCntl_1__SHIFT 0x0 1769#define DPM_TABLE_192__MemoryACPILevel_MpllFuncCntl_2_MASK 0xffffffff 1770#define DPM_TABLE_192__MemoryACPILevel_MpllFuncCntl_2__SHIFT 0x0 1771#define DPM_TABLE_193__MemoryACPILevel_MpllAdFuncCntl_MASK 0xffffffff 1772#define DPM_TABLE_193__MemoryACPILevel_MpllAdFuncCntl__SHIFT 0x0 1773#define DPM_TABLE_194__MemoryACPILevel_MpllDqFuncCntl_MASK 0xffffffff 1774#define DPM_TABLE_194__MemoryACPILevel_MpllDqFuncCntl__SHIFT 0x0 1775#define DPM_TABLE_195__MemoryACPILevel_MclkPwrmgtCntl_MASK 0xffffffff 1776#define DPM_TABLE_195__MemoryACPILevel_MclkPwrmgtCntl__SHIFT 0x0 1777#define DPM_TABLE_196__MemoryACPILevel_DllCntl_MASK 0xffffffff 1778#define DPM_TABLE_196__MemoryACPILevel_DllCntl__SHIFT 0x0 1779#define DPM_TABLE_197__MemoryACPILevel_MpllSs1_MASK 0xffffffff 1780#define DPM_TABLE_197__MemoryACPILevel_MpllSs1__SHIFT 0x0 1781#define DPM_TABLE_198__MemoryACPILevel_MpllSs2_MASK 0xffffffff 1782#define DPM_TABLE_198__MemoryACPILevel_MpllSs2__SHIFT 0x0 1783#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_Phases_MASK 0xff 1784#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_Phases__SHIFT 0x0 1785#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_VddGfx_MASK 0xff00 1786#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_VddGfx__SHIFT 0x8 1787#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_Vddci_MASK 0xff0000 1788#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_Vddci__SHIFT 0x10 1789#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_Vddc_MASK 0xff000000 1790#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_Vddc__SHIFT 0x18 1791#define DPM_TABLE_200__MemoryLevel_0_MinMvdd_MASK 0xffffffff 1792#define DPM_TABLE_200__MemoryLevel_0_MinMvdd__SHIFT 0x0 1793#define DPM_TABLE_201__MemoryLevel_0_MclkFrequency_MASK 0xffffffff 1794#define DPM_TABLE_201__MemoryLevel_0_MclkFrequency__SHIFT 0x0 1795#define DPM_TABLE_202__MemoryLevel_0_StutterEnable_MASK 0xff 1796#define DPM_TABLE_202__MemoryLevel_0_StutterEnable__SHIFT 0x0 1797#define DPM_TABLE_202__MemoryLevel_0_RttEnable_MASK 0xff00 1798#define DPM_TABLE_202__MemoryLevel_0_RttEnable__SHIFT 0x8 1799#define DPM_TABLE_202__MemoryLevel_0_EdcWriteEnable_MASK 0xff0000 1800#define DPM_TABLE_202__MemoryLevel_0_EdcWriteEnable__SHIFT 0x10 1801#define DPM_TABLE_202__MemoryLevel_0_EdcReadEnable_MASK 0xff000000 1802#define DPM_TABLE_202__MemoryLevel_0_EdcReadEnable__SHIFT 0x18 1803#define DPM_TABLE_203__MemoryLevel_0_EnabledForActivity_MASK 0xff 1804#define DPM_TABLE_203__MemoryLevel_0_EnabledForActivity__SHIFT 0x0 1805#define DPM_TABLE_203__MemoryLevel_0_EnabledForThrottle_MASK 0xff00 1806#define DPM_TABLE_203__MemoryLevel_0_EnabledForThrottle__SHIFT 0x8 1807#define DPM_TABLE_203__MemoryLevel_0_StrobeRatio_MASK 0xff0000 1808#define DPM_TABLE_203__MemoryLevel_0_StrobeRatio__SHIFT 0x10 1809#define DPM_TABLE_203__MemoryLevel_0_StrobeEnable_MASK 0xff000000 1810#define DPM_TABLE_203__MemoryLevel_0_StrobeEnable__SHIFT 0x18 1811#define DPM_TABLE_204__MemoryLevel_0_padding_MASK 0xff 1812#define DPM_TABLE_204__MemoryLevel_0_padding__SHIFT 0x0 1813#define DPM_TABLE_204__MemoryLevel_0_VoltageDownHyst_MASK 0xff00 1814#define DPM_TABLE_204__MemoryLevel_0_VoltageDownHyst__SHIFT 0x8 1815#define DPM_TABLE_204__MemoryLevel_0_DownHyst_MASK 0xff0000 1816#define DPM_TABLE_204__MemoryLevel_0_DownHyst__SHIFT 0x10 1817#define DPM_TABLE_204__MemoryLevel_0_UpHyst_MASK 0xff000000 1818#define DPM_TABLE_204__MemoryLevel_0_UpHyst__SHIFT 0x18 1819#define DPM_TABLE_205__MemoryLevel_0_padding1_MASK 0xff 1820#define DPM_TABLE_205__MemoryLevel_0_padding1__SHIFT 0x0 1821#define DPM_TABLE_205__MemoryLevel_0_DisplayWatermark_MASK 0xff00 1822#define DPM_TABLE_205__MemoryLevel_0_DisplayWatermark__SHIFT 0x8 1823#define DPM_TABLE_205__MemoryLevel_0_ActivityLevel_MASK 0xffff0000 1824#define DPM_TABLE_205__MemoryLevel_0_ActivityLevel__SHIFT 0x10 1825#define DPM_TABLE_206__MemoryLevel_0_MpllFuncCntl_MASK 0xffffffff 1826#define DPM_TABLE_206__MemoryLevel_0_MpllFuncCntl__SHIFT 0x0 1827#define DPM_TABLE_207__MemoryLevel_0_MpllFuncCntl_1_MASK 0xffffffff 1828#define DPM_TABLE_207__MemoryLevel_0_MpllFuncCntl_1__SHIFT 0x0 1829#define DPM_TABLE_208__MemoryLevel_0_MpllFuncCntl_2_MASK 0xffffffff 1830#define DPM_TABLE_208__MemoryLevel_0_MpllFuncCntl_2__SHIFT 0x0 1831#define DPM_TABLE_209__MemoryLevel_0_MpllAdFuncCntl_MASK 0xffffffff 1832#define DPM_TABLE_209__MemoryLevel_0_MpllAdFuncCntl__SHIFT 0x0 1833#define DPM_TABLE_210__MemoryLevel_0_MpllDqFuncCntl_MASK 0xffffffff 1834#define DPM_TABLE_210__MemoryLevel_0_MpllDqFuncCntl__SHIFT 0x0 1835#define DPM_TABLE_211__MemoryLevel_0_MclkPwrmgtCntl_MASK 0xffffffff 1836#define DPM_TABLE_211__MemoryLevel_0_MclkPwrmgtCntl__SHIFT 0x0 1837#define DPM_TABLE_212__MemoryLevel_0_DllCntl_MASK 0xffffffff 1838#define DPM_TABLE_212__MemoryLevel_0_DllCntl__SHIFT 0x0 1839#define DPM_TABLE_213__MemoryLevel_0_MpllSs1_MASK 0xffffffff 1840#define DPM_TABLE_213__MemoryLevel_0_MpllSs1__SHIFT 0x0 1841#define DPM_TABLE_214__MemoryLevel_0_MpllSs2_MASK 0xffffffff 1842#define DPM_TABLE_214__MemoryLevel_0_MpllSs2__SHIFT 0x0 1843#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_Phases_MASK 0xff 1844#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_Phases__SHIFT 0x0 1845#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_VddGfx_MASK 0xff00 1846#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_VddGfx__SHIFT 0x8 1847#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_Vddci_MASK 0xff0000 1848#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_Vddci__SHIFT 0x10 1849#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_Vddc_MASK 0xff000000 1850#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_Vddc__SHIFT 0x18 1851#define DPM_TABLE_216__MemoryLevel_1_MinMvdd_MASK 0xffffffff 1852#define DPM_TABLE_216__MemoryLevel_1_MinMvdd__SHIFT 0x0 1853#define DPM_TABLE_217__MemoryLevel_1_MclkFrequency_MASK 0xffffffff 1854#define DPM_TABLE_217__MemoryLevel_1_MclkFrequency__SHIFT 0x0 1855#define DPM_TABLE_218__MemoryLevel_1_StutterEnable_MASK 0xff 1856#define DPM_TABLE_218__MemoryLevel_1_StutterEnable__SHIFT 0x0 1857#define DPM_TABLE_218__MemoryLevel_1_RttEnable_MASK 0xff00 1858#define DPM_TABLE_218__MemoryLevel_1_RttEnable__SHIFT 0x8 1859#define DPM_TABLE_218__MemoryLevel_1_EdcWriteEnable_MASK 0xff0000 1860#define DPM_TABLE_218__MemoryLevel_1_EdcWriteEnable__SHIFT 0x10 1861#define DPM_TABLE_218__MemoryLevel_1_EdcReadEnable_MASK 0xff000000 1862#define DPM_TABLE_218__MemoryLevel_1_EdcReadEnable__SHIFT 0x18 1863#define DPM_TABLE_219__MemoryLevel_1_EnabledForActivity_MASK 0xff 1864#define DPM_TABLE_219__MemoryLevel_1_EnabledForActivity__SHIFT 0x0 1865#define DPM_TABLE_219__MemoryLevel_1_EnabledForThrottle_MASK 0xff00 1866#define DPM_TABLE_219__MemoryLevel_1_EnabledForThrottle__SHIFT 0x8 1867#define DPM_TABLE_219__MemoryLevel_1_StrobeRatio_MASK 0xff0000 1868#define DPM_TABLE_219__MemoryLevel_1_StrobeRatio__SHIFT 0x10 1869#define DPM_TABLE_219__MemoryLevel_1_StrobeEnable_MASK 0xff000000 1870#define DPM_TABLE_219__MemoryLevel_1_StrobeEnable__SHIFT 0x18 1871#define DPM_TABLE_220__MemoryLevel_1_padding_MASK 0xff 1872#define DPM_TABLE_220__MemoryLevel_1_padding__SHIFT 0x0 1873#define DPM_TABLE_220__MemoryLevel_1_VoltageDownHyst_MASK 0xff00 1874#define DPM_TABLE_220__MemoryLevel_1_VoltageDownHyst__SHIFT 0x8 1875#define DPM_TABLE_220__MemoryLevel_1_DownHyst_MASK 0xff0000 1876#define DPM_TABLE_220__MemoryLevel_1_DownHyst__SHIFT 0x10 1877#define DPM_TABLE_220__MemoryLevel_1_UpHyst_MASK 0xff000000 1878#define DPM_TABLE_220__MemoryLevel_1_UpHyst__SHIFT 0x18 1879#define DPM_TABLE_221__MemoryLevel_1_padding1_MASK 0xff 1880#define DPM_TABLE_221__MemoryLevel_1_padding1__SHIFT 0x0 1881#define DPM_TABLE_221__MemoryLevel_1_DisplayWatermark_MASK 0xff00 1882#define DPM_TABLE_221__MemoryLevel_1_DisplayWatermark__SHIFT 0x8 1883#define DPM_TABLE_221__MemoryLevel_1_ActivityLevel_MASK 0xffff0000 1884#define DPM_TABLE_221__MemoryLevel_1_ActivityLevel__SHIFT 0x10 1885#define DPM_TABLE_222__MemoryLevel_1_MpllFuncCntl_MASK 0xffffffff 1886#define DPM_TABLE_222__MemoryLevel_1_MpllFuncCntl__SHIFT 0x0 1887#define DPM_TABLE_223__MemoryLevel_1_MpllFuncCntl_1_MASK 0xffffffff 1888#define DPM_TABLE_223__MemoryLevel_1_MpllFuncCntl_1__SHIFT 0x0 1889#define DPM_TABLE_224__MemoryLevel_1_MpllFuncCntl_2_MASK 0xffffffff 1890#define DPM_TABLE_224__MemoryLevel_1_MpllFuncCntl_2__SHIFT 0x0 1891#define DPM_TABLE_225__MemoryLevel_1_MpllAdFuncCntl_MASK 0xffffffff 1892#define DPM_TABLE_225__MemoryLevel_1_MpllAdFuncCntl__SHIFT 0x0 1893#define DPM_TABLE_226__MemoryLevel_1_MpllDqFuncCntl_MASK 0xffffffff 1894#define DPM_TABLE_226__MemoryLevel_1_MpllDqFuncCntl__SHIFT 0x0 1895#define DPM_TABLE_227__MemoryLevel_1_MclkPwrmgtCntl_MASK 0xffffffff 1896#define DPM_TABLE_227__MemoryLevel_1_MclkPwrmgtCntl__SHIFT 0x0 1897#define DPM_TABLE_228__MemoryLevel_1_DllCntl_MASK 0xffffffff 1898#define DPM_TABLE_228__MemoryLevel_1_DllCntl__SHIFT 0x0 1899#define DPM_TABLE_229__MemoryLevel_1_MpllSs1_MASK 0xffffffff 1900#define DPM_TABLE_229__MemoryLevel_1_MpllSs1__SHIFT 0x0 1901#define DPM_TABLE_230__MemoryLevel_1_MpllSs2_MASK 0xffffffff 1902#define DPM_TABLE_230__MemoryLevel_1_MpllSs2__SHIFT 0x0 1903#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_Phases_MASK 0xff 1904#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_Phases__SHIFT 0x0 1905#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_VddGfx_MASK 0xff00 1906#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_VddGfx__SHIFT 0x8 1907#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_Vddci_MASK 0xff0000 1908#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_Vddci__SHIFT 0x10 1909#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_Vddc_MASK 0xff000000 1910#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_Vddc__SHIFT 0x18 1911#define DPM_TABLE_232__MemoryLevel_2_MinMvdd_MASK 0xffffffff 1912#define DPM_TABLE_232__MemoryLevel_2_MinMvdd__SHIFT 0x0 1913#define DPM_TABLE_233__MemoryLevel_2_MclkFrequency_MASK 0xffffffff 1914#define DPM_TABLE_233__MemoryLevel_2_MclkFrequency__SHIFT 0x0 1915#define DPM_TABLE_234__MemoryLevel_2_StutterEnable_MASK 0xff 1916#define DPM_TABLE_234__MemoryLevel_2_StutterEnable__SHIFT 0x0 1917#define DPM_TABLE_234__MemoryLevel_2_RttEnable_MASK 0xff00 1918#define DPM_TABLE_234__MemoryLevel_2_RttEnable__SHIFT 0x8 1919#define DPM_TABLE_234__MemoryLevel_2_EdcWriteEnable_MASK 0xff0000 1920#define DPM_TABLE_234__MemoryLevel_2_EdcWriteEnable__SHIFT 0x10 1921#define DPM_TABLE_234__MemoryLevel_2_EdcReadEnable_MASK 0xff000000 1922#define DPM_TABLE_234__MemoryLevel_2_EdcReadEnable__SHIFT 0x18 1923#define DPM_TABLE_235__MemoryLevel_2_EnabledForActivity_MASK 0xff 1924#define DPM_TABLE_235__MemoryLevel_2_EnabledForActivity__SHIFT 0x0 1925#define DPM_TABLE_235__MemoryLevel_2_EnabledForThrottle_MASK 0xff00 1926#define DPM_TABLE_235__MemoryLevel_2_EnabledForThrottle__SHIFT 0x8 1927#define DPM_TABLE_235__MemoryLevel_2_StrobeRatio_MASK 0xff0000 1928#define DPM_TABLE_235__MemoryLevel_2_StrobeRatio__SHIFT 0x10 1929#define DPM_TABLE_235__MemoryLevel_2_StrobeEnable_MASK 0xff000000 1930#define DPM_TABLE_235__MemoryLevel_2_StrobeEnable__SHIFT 0x18 1931#define DPM_TABLE_236__MemoryLevel_2_padding_MASK 0xff 1932#define DPM_TABLE_236__MemoryLevel_2_padding__SHIFT 0x0 1933#define DPM_TABLE_236__MemoryLevel_2_VoltageDownHyst_MASK 0xff00 1934#define DPM_TABLE_236__MemoryLevel_2_VoltageDownHyst__SHIFT 0x8 1935#define DPM_TABLE_236__MemoryLevel_2_DownHyst_MASK 0xff0000 1936#define DPM_TABLE_236__MemoryLevel_2_DownHyst__SHIFT 0x10 1937#define DPM_TABLE_236__MemoryLevel_2_UpHyst_MASK 0xff000000 1938#define DPM_TABLE_236__MemoryLevel_2_UpHyst__SHIFT 0x18 1939#define DPM_TABLE_237__MemoryLevel_2_padding1_MASK 0xff 1940#define DPM_TABLE_237__MemoryLevel_2_padding1__SHIFT 0x0 1941#define DPM_TABLE_237__MemoryLevel_2_DisplayWatermark_MASK 0xff00 1942#define DPM_TABLE_237__MemoryLevel_2_DisplayWatermark__SHIFT 0x8 1943#define DPM_TABLE_237__MemoryLevel_2_ActivityLevel_MASK 0xffff0000 1944#define DPM_TABLE_237__MemoryLevel_2_ActivityLevel__SHIFT 0x10 1945#define DPM_TABLE_238__MemoryLevel_2_MpllFuncCntl_MASK 0xffffffff 1946#define DPM_TABLE_238__MemoryLevel_2_MpllFuncCntl__SHIFT 0x0 1947#define DPM_TABLE_239__MemoryLevel_2_MpllFuncCntl_1_MASK 0xffffffff 1948#define DPM_TABLE_239__MemoryLevel_2_MpllFuncCntl_1__SHIFT 0x0 1949#define DPM_TABLE_240__MemoryLevel_2_MpllFuncCntl_2_MASK 0xffffffff 1950#define DPM_TABLE_240__MemoryLevel_2_MpllFuncCntl_2__SHIFT 0x0 1951#define DPM_TABLE_241__MemoryLevel_2_MpllAdFuncCntl_MASK 0xffffffff 1952#define DPM_TABLE_241__MemoryLevel_2_MpllAdFuncCntl__SHIFT 0x0 1953#define DPM_TABLE_242__MemoryLevel_2_MpllDqFuncCntl_MASK 0xffffffff 1954#define DPM_TABLE_242__MemoryLevel_2_MpllDqFuncCntl__SHIFT 0x0 1955#define DPM_TABLE_243__MemoryLevel_2_MclkPwrmgtCntl_MASK 0xffffffff 1956#define DPM_TABLE_243__MemoryLevel_2_MclkPwrmgtCntl__SHIFT 0x0 1957#define DPM_TABLE_244__MemoryLevel_2_DllCntl_MASK 0xffffffff 1958#define DPM_TABLE_244__MemoryLevel_2_DllCntl__SHIFT 0x0 1959#define DPM_TABLE_245__MemoryLevel_2_MpllSs1_MASK 0xffffffff 1960#define DPM_TABLE_245__MemoryLevel_2_MpllSs1__SHIFT 0x0 1961#define DPM_TABLE_246__MemoryLevel_2_MpllSs2_MASK 0xffffffff 1962#define DPM_TABLE_246__MemoryLevel_2_MpllSs2__SHIFT 0x0 1963#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_Phases_MASK 0xff 1964#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_Phases__SHIFT 0x0 1965#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_VddGfx_MASK 0xff00 1966#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_VddGfx__SHIFT 0x8 1967#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_Vddci_MASK 0xff0000 1968#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_Vddci__SHIFT 0x10 1969#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_Vddc_MASK 0xff000000 1970#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_Vddc__SHIFT 0x18 1971#define DPM_TABLE_248__MemoryLevel_3_MinMvdd_MASK 0xffffffff 1972#define DPM_TABLE_248__MemoryLevel_3_MinMvdd__SHIFT 0x0 1973#define DPM_TABLE_249__MemoryLevel_3_MclkFrequency_MASK 0xffffffff 1974#define DPM_TABLE_249__MemoryLevel_3_MclkFrequency__SHIFT 0x0 1975#define DPM_TABLE_250__MemoryLevel_3_StutterEnable_MASK 0xff 1976#define DPM_TABLE_250__MemoryLevel_3_StutterEnable__SHIFT 0x0 1977#define DPM_TABLE_250__MemoryLevel_3_RttEnable_MASK 0xff00 1978#define DPM_TABLE_250__MemoryLevel_3_RttEnable__SHIFT 0x8 1979#define DPM_TABLE_250__MemoryLevel_3_EdcWriteEnable_MASK 0xff0000 1980#define DPM_TABLE_250__MemoryLevel_3_EdcWriteEnable__SHIFT 0x10 1981#define DPM_TABLE_250__MemoryLevel_3_EdcReadEnable_MASK 0xff000000 1982#define DPM_TABLE_250__MemoryLevel_3_EdcReadEnable__SHIFT 0x18 1983#define DPM_TABLE_251__MemoryLevel_3_EnabledForActivity_MASK 0xff 1984#define DPM_TABLE_251__MemoryLevel_3_EnabledForActivity__SHIFT 0x0 1985#define DPM_TABLE_251__MemoryLevel_3_EnabledForThrottle_MASK 0xff00 1986#define DPM_TABLE_251__MemoryLevel_3_EnabledForThrottle__SHIFT 0x8 1987#define DPM_TABLE_251__MemoryLevel_3_StrobeRatio_MASK 0xff0000 1988#define DPM_TABLE_251__MemoryLevel_3_StrobeRatio__SHIFT 0x10 1989#define DPM_TABLE_251__MemoryLevel_3_StrobeEnable_MASK 0xff000000 1990#define DPM_TABLE_251__MemoryLevel_3_StrobeEnable__SHIFT 0x18 1991#define DPM_TABLE_252__MemoryLevel_3_padding_MASK 0xff 1992#define DPM_TABLE_252__MemoryLevel_3_padding__SHIFT 0x0 1993#define DPM_TABLE_252__MemoryLevel_3_VoltageDownHyst_MASK 0xff00 1994#define DPM_TABLE_252__MemoryLevel_3_VoltageDownHyst__SHIFT 0x8 1995#define DPM_TABLE_252__MemoryLevel_3_DownHyst_MASK 0xff0000 1996#define DPM_TABLE_252__MemoryLevel_3_DownHyst__SHIFT 0x10 1997#define DPM_TABLE_252__MemoryLevel_3_UpHyst_MASK 0xff000000 1998#define DPM_TABLE_252__MemoryLevel_3_UpHyst__SHIFT 0x18 1999#define DPM_TABLE_253__MemoryLevel_3_padding1_MASK 0xff 2000#define DPM_TABLE_253__MemoryLevel_3_padding1__SHIFT 0x0
2001#define DPM_TABLE_253__MemoryLevel_3_DisplayWatermark_MASK 0xff00 2002#define DPM_TABLE_253__MemoryLevel_3_DisplayWatermark__SHIFT 0x8 2003#define DPM_TABLE_253__MemoryLevel_3_ActivityLevel_MASK 0xffff0000 2004#define DPM_TABLE_253__MemoryLevel_3_ActivityLevel__SHIFT 0x10 2005#define DPM_TABLE_254__MemoryLevel_3_MpllFuncCntl_MASK 0xffffffff 2006#define DPM_TABLE_254__MemoryLevel_3_MpllFuncCntl__SHIFT 0x0 2007#define DPM_TABLE_255__MemoryLevel_3_MpllFuncCntl_1_MASK 0xffffffff 2008#define DPM_TABLE_255__MemoryLevel_3_MpllFuncCntl_1__SHIFT 0x0 2009#define DPM_TABLE_256__MemoryLevel_3_MpllFuncCntl_2_MASK 0xffffffff 2010#define DPM_TABLE_256__MemoryLevel_3_MpllFuncCntl_2__SHIFT 0x0 2011#define DPM_TABLE_257__MemoryLevel_3_MpllAdFuncCntl_MASK 0xffffffff 2012#define DPM_TABLE_257__MemoryLevel_3_MpllAdFuncCntl__SHIFT 0x0 2013#define DPM_TABLE_258__MemoryLevel_3_MpllDqFuncCntl_MASK 0xffffffff 2014#define DPM_TABLE_258__MemoryLevel_3_MpllDqFuncCntl__SHIFT 0x0 2015#define DPM_TABLE_259__MemoryLevel_3_MclkPwrmgtCntl_MASK 0xffffffff 2016#define DPM_TABLE_259__MemoryLevel_3_MclkPwrmgtCntl__SHIFT 0x0 2017#define DPM_TABLE_260__MemoryLevel_3_DllCntl_MASK 0xffffffff 2018#define DPM_TABLE_260__MemoryLevel_3_DllCntl__SHIFT 0x0 2019#define DPM_TABLE_261__MemoryLevel_3_MpllSs1_MASK 0xffffffff 2020#define DPM_TABLE_261__MemoryLevel_3_MpllSs1__SHIFT 0x0 2021#define DPM_TABLE_262__MemoryLevel_3_MpllSs2_MASK 0xffffffff 2022#define DPM_TABLE_262__MemoryLevel_3_MpllSs2__SHIFT 0x0 2023#define DPM_TABLE_263__LinkLevel_0_SPC_MASK 0xff 2024#define DPM_TABLE_263__LinkLevel_0_SPC__SHIFT 0x0 2025#define DPM_TABLE_263__LinkLevel_0_EnabledForActivity_MASK 0xff00 2026#define DPM_TABLE_263__LinkLevel_0_EnabledForActivity__SHIFT 0x8 2027#define DPM_TABLE_263__LinkLevel_0_PcieLaneCount_MASK 0xff0000 2028#define DPM_TABLE_263__LinkLevel_0_PcieLaneCount__SHIFT 0x10 2029#define DPM_TABLE_263__LinkLevel_0_PcieGenSpeed_MASK 0xff000000 2030#define DPM_TABLE_263__LinkLevel_0_PcieGenSpeed__SHIFT 0x18 2031#define DPM_TABLE_264__LinkLevel_0_DownThreshold_MASK 0xffffffff 2032#define DPM_TABLE_264__LinkLevel_0_DownThreshold__SHIFT 0x0 2033#define DPM_TABLE_265__LinkLevel_0_UpThreshold_MASK 0xffffffff 2034#define DPM_TABLE_265__LinkLevel_0_UpThreshold__SHIFT 0x0 2035#define DPM_TABLE_266__LinkLevel_0_Reserved_MASK 0xffffffff 2036#define DPM_TABLE_266__LinkLevel_0_Reserved__SHIFT 0x0 2037#define DPM_TABLE_267__LinkLevel_1_SPC_MASK 0xff 2038#define DPM_TABLE_267__LinkLevel_1_SPC__SHIFT 0x0 2039#define DPM_TABLE_267__LinkLevel_1_EnabledForActivity_MASK 0xff00 2040#define DPM_TABLE_267__LinkLevel_1_EnabledForActivity__SHIFT 0x8 2041#define DPM_TABLE_267__LinkLevel_1_PcieLaneCount_MASK 0xff0000 2042#define DPM_TABLE_267__LinkLevel_1_PcieLaneCount__SHIFT 0x10 2043#define DPM_TABLE_267__LinkLevel_1_PcieGenSpeed_MASK 0xff000000 2044#define DPM_TABLE_267__LinkLevel_1_PcieGenSpeed__SHIFT 0x18 2045#define DPM_TABLE_268__LinkLevel_1_DownThreshold_MASK 0xffffffff 2046#define DPM_TABLE_268__LinkLevel_1_DownThreshold__SHIFT 0x0 2047#define DPM_TABLE_269__LinkLevel_1_UpThreshold_MASK 0xffffffff 2048#define DPM_TABLE_269__LinkLevel_1_UpThreshold__SHIFT 0x0 2049#define DPM_TABLE_270__LinkLevel_1_Reserved_MASK 0xffffffff 2050#define DPM_TABLE_270__LinkLevel_1_Reserved__SHIFT 0x0 2051#define DPM_TABLE_271__LinkLevel_2_SPC_MASK 0xff 2052#define DPM_TABLE_271__LinkLevel_2_SPC__SHIFT 0x0 2053#define DPM_TABLE_271__LinkLevel_2_EnabledForActivity_MASK 0xff00 2054#define DPM_TABLE_271__LinkLevel_2_EnabledForActivity__SHIFT 0x8 2055#define DPM_TABLE_271__LinkLevel_2_PcieLaneCount_MASK 0xff0000 2056#define DPM_TABLE_271__LinkLevel_2_PcieLaneCount__SHIFT 0x10 2057#define DPM_TABLE_271__LinkLevel_2_PcieGenSpeed_MASK 0xff000000 2058#define DPM_TABLE_271__LinkLevel_2_PcieGenSpeed__SHIFT 0x18 2059#define DPM_TABLE_272__LinkLevel_2_DownThreshold_MASK 0xffffffff 2060#define DPM_TABLE_272__LinkLevel_2_DownThreshold__SHIFT 0x0 2061#define DPM_TABLE_273__LinkLevel_2_UpThreshold_MASK 0xffffffff 2062#define DPM_TABLE_273__LinkLevel_2_UpThreshold__SHIFT 0x0 2063#define DPM_TABLE_274__LinkLevel_2_Reserved_MASK 0xffffffff 2064#define DPM_TABLE_274__LinkLevel_2_Reserved__SHIFT 0x0 2065#define DPM_TABLE_275__LinkLevel_3_SPC_MASK 0xff 2066#define DPM_TABLE_275__LinkLevel_3_SPC__SHIFT 0x0 2067#define DPM_TABLE_275__LinkLevel_3_EnabledForActivity_MASK 0xff00 2068#define DPM_TABLE_275__LinkLevel_3_EnabledForActivity__SHIFT 0x8 2069#define DPM_TABLE_275__LinkLevel_3_PcieLaneCount_MASK 0xff0000 2070#define DPM_TABLE_275__LinkLevel_3_PcieLaneCount__SHIFT 0x10 2071#define DPM_TABLE_275__LinkLevel_3_PcieGenSpeed_MASK 0xff000000 2072#define DPM_TABLE_275__LinkLevel_3_PcieGenSpeed__SHIFT 0x18 2073#define DPM_TABLE_276__LinkLevel_3_DownThreshold_MASK 0xffffffff 2074#define DPM_TABLE_276__LinkLevel_3_DownThreshold__SHIFT 0x0 2075#define DPM_TABLE_277__LinkLevel_3_UpThreshold_MASK 0xffffffff 2076#define DPM_TABLE_277__LinkLevel_3_UpThreshold__SHIFT 0x0 2077#define DPM_TABLE_278__LinkLevel_3_Reserved_MASK 0xffffffff 2078#define DPM_TABLE_278__LinkLevel_3_Reserved__SHIFT 0x0 2079#define DPM_TABLE_279__LinkLevel_4_SPC_MASK 0xff 2080#define DPM_TABLE_279__LinkLevel_4_SPC__SHIFT 0x0 2081#define DPM_TABLE_279__LinkLevel_4_EnabledForActivity_MASK 0xff00 2082#define DPM_TABLE_279__LinkLevel_4_EnabledForActivity__SHIFT 0x8 2083#define DPM_TABLE_279__LinkLevel_4_PcieLaneCount_MASK 0xff0000 2084#define DPM_TABLE_279__LinkLevel_4_PcieLaneCount__SHIFT 0x10 2085#define DPM_TABLE_279__LinkLevel_4_PcieGenSpeed_MASK 0xff000000 2086#define DPM_TABLE_279__LinkLevel_4_PcieGenSpeed__SHIFT 0x18 2087#define DPM_TABLE_280__LinkLevel_4_DownThreshold_MASK 0xffffffff 2088#define DPM_TABLE_280__LinkLevel_4_DownThreshold__SHIFT 0x0 2089#define DPM_TABLE_281__LinkLevel_4_UpThreshold_MASK 0xffffffff 2090#define DPM_TABLE_281__LinkLevel_4_UpThreshold__SHIFT 0x0 2091#define DPM_TABLE_282__LinkLevel_4_Reserved_MASK 0xffffffff 2092#define DPM_TABLE_282__LinkLevel_4_Reserved__SHIFT 0x0 2093#define DPM_TABLE_283__LinkLevel_5_SPC_MASK 0xff 2094#define DPM_TABLE_283__LinkLevel_5_SPC__SHIFT 0x0 2095#define DPM_TABLE_283__LinkLevel_5_EnabledForActivity_MASK 0xff00 2096#define DPM_TABLE_283__LinkLevel_5_EnabledForActivity__SHIFT 0x8 2097#define DPM_TABLE_283__LinkLevel_5_PcieLaneCount_MASK 0xff0000 2098#define DPM_TABLE_283__LinkLevel_5_PcieLaneCount__SHIFT 0x10 2099#define DPM_TABLE_283__LinkLevel_5_PcieGenSpeed_MASK 0xff000000 2100#define DPM_TABLE_283__LinkLevel_5_PcieGenSpeed__SHIFT 0x18 2101#define DPM_TABLE_284__LinkLevel_5_DownThreshold_MASK 0xffffffff 2102#define DPM_TABLE_284__LinkLevel_5_DownThreshold__SHIFT 0x0 2103#define DPM_TABLE_285__LinkLevel_5_UpThreshold_MASK 0xffffffff 2104#define DPM_TABLE_285__LinkLevel_5_UpThreshold__SHIFT 0x0 2105#define DPM_TABLE_286__LinkLevel_5_Reserved_MASK 0xffffffff 2106#define DPM_TABLE_286__LinkLevel_5_Reserved__SHIFT 0x0 2107#define DPM_TABLE_287__LinkLevel_6_SPC_MASK 0xff 2108#define DPM_TABLE_287__LinkLevel_6_SPC__SHIFT 0x0 2109#define DPM_TABLE_287__LinkLevel_6_EnabledForActivity_MASK 0xff00 2110#define DPM_TABLE_287__LinkLevel_6_EnabledForActivity__SHIFT 0x8 2111#define DPM_TABLE_287__LinkLevel_6_PcieLaneCount_MASK 0xff0000 2112#define DPM_TABLE_287__LinkLevel_6_PcieLaneCount__SHIFT 0x10 2113#define DPM_TABLE_287__LinkLevel_6_PcieGenSpeed_MASK 0xff000000 2114#define DPM_TABLE_287__LinkLevel_6_PcieGenSpeed__SHIFT 0x18 2115#define DPM_TABLE_288__LinkLevel_6_DownThreshold_MASK 0xffffffff 2116#define DPM_TABLE_288__LinkLevel_6_DownThreshold__SHIFT 0x0 2117#define DPM_TABLE_289__LinkLevel_6_UpThreshold_MASK 0xffffffff 2118#define DPM_TABLE_289__LinkLevel_6_UpThreshold__SHIFT 0x0 2119#define DPM_TABLE_290__LinkLevel_6_Reserved_MASK 0xffffffff 2120#define DPM_TABLE_290__LinkLevel_6_Reserved__SHIFT 0x0 2121#define DPM_TABLE_291__LinkLevel_7_SPC_MASK 0xff 2122#define DPM_TABLE_291__LinkLevel_7_SPC__SHIFT 0x0 2123#define DPM_TABLE_291__LinkLevel_7_EnabledForActivity_MASK 0xff00 2124#define DPM_TABLE_291__LinkLevel_7_EnabledForActivity__SHIFT 0x8 2125#define DPM_TABLE_291__LinkLevel_7_PcieLaneCount_MASK 0xff0000 2126#define DPM_TABLE_291__LinkLevel_7_PcieLaneCount__SHIFT 0x10 2127#define DPM_TABLE_291__LinkLevel_7_PcieGenSpeed_MASK 0xff000000 2128#define DPM_TABLE_291__LinkLevel_7_PcieGenSpeed__SHIFT 0x18 2129#define DPM_TABLE_292__LinkLevel_7_DownThreshold_MASK 0xffffffff 2130#define DPM_TABLE_292__LinkLevel_7_DownThreshold__SHIFT 0x0 2131#define DPM_TABLE_293__LinkLevel_7_UpThreshold_MASK 0xffffffff 2132#define DPM_TABLE_293__LinkLevel_7_UpThreshold__SHIFT 0x0 2133#define DPM_TABLE_294__LinkLevel_7_Reserved_MASK 0xffffffff 2134#define DPM_TABLE_294__LinkLevel_7_Reserved__SHIFT 0x0 2135#define DPM_TABLE_295__ACPILevel_Flags_MASK 0xffffffff 2136#define DPM_TABLE_295__ACPILevel_Flags__SHIFT 0x0 2137#define DPM_TABLE_296__ACPILevel_MinVoltage_Phases_MASK 0xff 2138#define DPM_TABLE_296__ACPILevel_MinVoltage_Phases__SHIFT 0x0 2139#define DPM_TABLE_296__ACPILevel_MinVoltage_VddGfx_MASK 0xff00 2140#define DPM_TABLE_296__ACPILevel_MinVoltage_VddGfx__SHIFT 0x8 2141#define DPM_TABLE_296__ACPILevel_MinVoltage_Vddci_MASK 0xff0000 2142#define DPM_TABLE_296__ACPILevel_MinVoltage_Vddci__SHIFT 0x10 2143#define DPM_TABLE_296__ACPILevel_MinVoltage_Vddc_MASK 0xff000000 2144#define DPM_TABLE_296__ACPILevel_MinVoltage_Vddc__SHIFT 0x18 2145#define DPM_TABLE_297__ACPILevel_SclkFrequency_MASK 0xffffffff 2146#define DPM_TABLE_297__ACPILevel_SclkFrequency__SHIFT 0x0 2147#define DPM_TABLE_298__ACPILevel_padding_MASK 0xff 2148#define DPM_TABLE_298__ACPILevel_padding__SHIFT 0x0 2149#define DPM_TABLE_298__ACPILevel_DeepSleepDivId_MASK 0xff00 2150#define DPM_TABLE_298__ACPILevel_DeepSleepDivId__SHIFT 0x8 2151#define DPM_TABLE_298__ACPILevel_DisplayWatermark_MASK 0xff0000 2152#define DPM_TABLE_298__ACPILevel_DisplayWatermark__SHIFT 0x10 2153#define DPM_TABLE_298__ACPILevel_SclkDid_MASK 0xff000000 2154#define DPM_TABLE_298__ACPILevel_SclkDid__SHIFT 0x18 2155#define DPM_TABLE_299__ACPILevel_CgSpllFuncCntl_MASK 0xffffffff 2156#define DPM_TABLE_299__ACPILevel_CgSpllFuncCntl__SHIFT 0x0 2157#define DPM_TABLE_300__ACPILevel_CgSpllFuncCntl2_MASK 0xffffffff 2158#define DPM_TABLE_300__ACPILevel_CgSpllFuncCntl2__SHIFT 0x0 2159#define DPM_TABLE_301__ACPILevel_CgSpllFuncCntl3_MASK 0xffffffff 2160#define DPM_TABLE_301__ACPILevel_CgSpllFuncCntl3__SHIFT 0x0 2161#define DPM_TABLE_302__ACPILevel_CgSpllFuncCntl4_MASK 0xffffffff 2162#define DPM_TABLE_302__ACPILevel_CgSpllFuncCntl4__SHIFT 0x0 2163#define DPM_TABLE_303__ACPILevel_SpllSpreadSpectrum_MASK 0xffffffff 2164#define DPM_TABLE_303__ACPILevel_SpllSpreadSpectrum__SHIFT 0x0 2165#define DPM_TABLE_304__ACPILevel_SpllSpreadSpectrum2_MASK 0xffffffff 2166#define DPM_TABLE_304__ACPILevel_SpllSpreadSpectrum2__SHIFT 0x0 2167#define DPM_TABLE_305__ACPILevel_CcPwrDynRm_MASK 0xffffffff 2168#define DPM_TABLE_305__ACPILevel_CcPwrDynRm__SHIFT 0x0 2169#define DPM_TABLE_306__ACPILevel_CcPwrDynRm1_MASK 0xffffffff 2170#define DPM_TABLE_306__ACPILevel_CcPwrDynRm1__SHIFT 0x0 2171#define DPM_TABLE_307__UvdLevel_0_VclkFrequency_MASK 0xffffffff 2172#define DPM_TABLE_307__UvdLevel_0_VclkFrequency__SHIFT 0x0 2173#define DPM_TABLE_308__UvdLevel_0_DclkFrequency_MASK 0xffffffff 2174#define DPM_TABLE_308__UvdLevel_0_DclkFrequency__SHIFT 0x0 2175#define DPM_TABLE_309__UvdLevel_0_MinVoltage_Phases_MASK 0xff 2176#define DPM_TABLE_309__UvdLevel_0_MinVoltage_Phases__SHIFT 0x0 2177#define DPM_TABLE_309__UvdLevel_0_MinVoltage_VddGfx_MASK 0xff00 2178#define DPM_TABLE_309__UvdLevel_0_MinVoltage_VddGfx__SHIFT 0x8 2179#define DPM_TABLE_309__UvdLevel_0_MinVoltage_Vddci_MASK 0xff0000 2180#define DPM_TABLE_309__UvdLevel_0_MinVoltage_Vddci__SHIFT 0x10 2181#define DPM_TABLE_309__UvdLevel_0_MinVoltage_Vddc_MASK 0xff000000 2182#define DPM_TABLE_309__UvdLevel_0_MinVoltage_Vddc__SHIFT 0x18 2183#define DPM_TABLE_310__UvdLevel_0_padding_1_MASK 0xff 2184#define DPM_TABLE_310__UvdLevel_0_padding_1__SHIFT 0x0 2185#define DPM_TABLE_310__UvdLevel_0_padding_0_MASK 0xff00 2186#define DPM_TABLE_310__UvdLevel_0_padding_0__SHIFT 0x8 2187#define DPM_TABLE_310__UvdLevel_0_DclkDivider_MASK 0xff0000 2188#define DPM_TABLE_310__UvdLevel_0_DclkDivider__SHIFT 0x10 2189#define DPM_TABLE_310__UvdLevel_0_VclkDivider_MASK 0xff000000 2190#define DPM_TABLE_310__UvdLevel_0_VclkDivider__SHIFT 0x18 2191#define DPM_TABLE_311__UvdLevel_1_VclkFrequency_MASK 0xffffffff 2192#define DPM_TABLE_311__UvdLevel_1_VclkFrequency__SHIFT 0x0 2193#define DPM_TABLE_312__UvdLevel_1_DclkFrequency_MASK 0xffffffff 2194#define DPM_TABLE_312__UvdLevel_1_DclkFrequency__SHIFT 0x0 2195#define DPM_TABLE_313__UvdLevel_1_MinVoltage_Phases_MASK 0xff 2196#define DPM_TABLE_313__UvdLevel_1_MinVoltage_Phases__SHIFT 0x0 2197#define DPM_TABLE_313__UvdLevel_1_MinVoltage_VddGfx_MASK 0xff00 2198#define DPM_TABLE_313__UvdLevel_1_MinVoltage_VddGfx__SHIFT 0x8 2199#define DPM_TABLE_313__UvdLevel_1_MinVoltage_Vddci_MASK 0xff0000 2200#define DPM_TABLE_313__UvdLevel_1_MinVoltage_Vddci__SHIFT 0x10 2201#define DPM_TABLE_313__UvdLevel_1_MinVoltage_Vddc_MASK 0xff000000 2202#define DPM_TABLE_313__UvdLevel_1_MinVoltage_Vddc__SHIFT 0x18 2203#define DPM_TABLE_314__UvdLevel_1_padding_1_MASK 0xff 2204#define DPM_TABLE_314__UvdLevel_1_padding_1__SHIFT 0x0 2205#define DPM_TABLE_314__UvdLevel_1_padding_0_MASK 0xff00 2206#define DPM_TABLE_314__UvdLevel_1_padding_0__SHIFT 0x8 2207#define DPM_TABLE_314__UvdLevel_1_DclkDivider_MASK 0xff0000 2208#define DPM_TABLE_314__UvdLevel_1_DclkDivider__SHIFT 0x10 2209#define DPM_TABLE_314__UvdLevel_1_VclkDivider_MASK 0xff000000 2210#define DPM_TABLE_314__UvdLevel_1_VclkDivider__SHIFT 0x18 2211#define DPM_TABLE_315__UvdLevel_2_VclkFrequency_MASK 0xffffffff 2212#define DPM_TABLE_315__UvdLevel_2_VclkFrequency__SHIFT 0x0 2213#define DPM_TABLE_316__UvdLevel_2_DclkFrequency_MASK 0xffffffff 2214#define DPM_TABLE_316__UvdLevel_2_DclkFrequency__SHIFT 0x0 2215#define DPM_TABLE_317__UvdLevel_2_MinVoltage_Phases_MASK 0xff 2216#define DPM_TABLE_317__UvdLevel_2_MinVoltage_Phases__SHIFT 0x0 2217#define DPM_TABLE_317__UvdLevel_2_MinVoltage_VddGfx_MASK 0xff00 2218#define DPM_TABLE_317__UvdLevel_2_MinVoltage_VddGfx__SHIFT 0x8 2219#define DPM_TABLE_317__UvdLevel_2_MinVoltage_Vddci_MASK 0xff0000 2220#define DPM_TABLE_317__UvdLevel_2_MinVoltage_Vddci__SHIFT 0x10 2221#define DPM_TABLE_317__UvdLevel_2_MinVoltage_Vddc_MASK 0xff000000 2222#define DPM_TABLE_317__UvdLevel_2_MinVoltage_Vddc__SHIFT 0x18 2223#define DPM_TABLE_318__UvdLevel_2_padding_1_MASK 0xff 2224#define DPM_TABLE_318__UvdLevel_2_padding_1__SHIFT 0x0 2225#define DPM_TABLE_318__UvdLevel_2_padding_0_MASK 0xff00 2226#define DPM_TABLE_318__UvdLevel_2_padding_0__SHIFT 0x8 2227#define DPM_TABLE_318__UvdLevel_2_DclkDivider_MASK 0xff0000 2228#define DPM_TABLE_318__UvdLevel_2_DclkDivider__SHIFT 0x10 2229#define DPM_TABLE_318__UvdLevel_2_VclkDivider_MASK 0xff000000 2230#define DPM_TABLE_318__UvdLevel_2_VclkDivider__SHIFT 0x18 2231#define DPM_TABLE_319__UvdLevel_3_VclkFrequency_MASK 0xffffffff 2232#define DPM_TABLE_319__UvdLevel_3_VclkFrequency__SHIFT 0x0 2233#define DPM_TABLE_320__UvdLevel_3_DclkFrequency_MASK 0xffffffff 2234#define DPM_TABLE_320__UvdLevel_3_DclkFrequency__SHIFT 0x0 2235#define DPM_TABLE_321__UvdLevel_3_MinVoltage_Phases_MASK 0xff 2236#define DPM_TABLE_321__UvdLevel_3_MinVoltage_Phases__SHIFT 0x0 2237#define DPM_TABLE_321__UvdLevel_3_MinVoltage_VddGfx_MASK 0xff00 2238#define DPM_TABLE_321__UvdLevel_3_MinVoltage_VddGfx__SHIFT 0x8 2239#define DPM_TABLE_321__UvdLevel_3_MinVoltage_Vddci_MASK 0xff0000 2240#define DPM_TABLE_321__UvdLevel_3_MinVoltage_Vddci__SHIFT 0x10 2241#define DPM_TABLE_321__UvdLevel_3_MinVoltage_Vddc_MASK 0xff000000 2242#define DPM_TABLE_321__UvdLevel_3_MinVoltage_Vddc__SHIFT 0x18 2243#define DPM_TABLE_322__UvdLevel_3_padding_1_MASK 0xff 2244#define DPM_TABLE_322__UvdLevel_3_padding_1__SHIFT 0x0 2245#define DPM_TABLE_322__UvdLevel_3_padding_0_MASK 0xff00 2246#define DPM_TABLE_322__UvdLevel_3_padding_0__SHIFT 0x8 2247#define DPM_TABLE_322__UvdLevel_3_DclkDivider_MASK 0xff0000 2248#define DPM_TABLE_322__UvdLevel_3_DclkDivider__SHIFT 0x10 2249#define DPM_TABLE_322__UvdLevel_3_VclkDivider_MASK 0xff000000 2250#define DPM_TABLE_322__UvdLevel_3_VclkDivider__SHIFT 0x18 2251#define DPM_TABLE_323__UvdLevel_4_VclkFrequency_MASK 0xffffffff 2252#define DPM_TABLE_323__UvdLevel_4_VclkFrequency__SHIFT 0x0 2253#define DPM_TABLE_324__UvdLevel_4_DclkFrequency_MASK 0xffffffff 2254#define DPM_TABLE_324__UvdLevel_4_DclkFrequency__SHIFT 0x0 2255#define DPM_TABLE_325__UvdLevel_4_MinVoltage_Phases_MASK 0xff 2256#define DPM_TABLE_325__UvdLevel_4_MinVoltage_Phases__SHIFT 0x0 2257#define DPM_TABLE_325__UvdLevel_4_MinVoltage_VddGfx_MASK 0xff00 2258#define DPM_TABLE_325__UvdLevel_4_MinVoltage_VddGfx__SHIFT 0x8 2259#define DPM_TABLE_325__UvdLevel_4_MinVoltage_Vddci_MASK 0xff0000 2260#define DPM_TABLE_325__UvdLevel_4_MinVoltage_Vddci__SHIFT 0x10 2261#define DPM_TABLE_325__UvdLevel_4_MinVoltage_Vddc_MASK 0xff000000 2262#define DPM_TABLE_325__UvdLevel_4_MinVoltage_Vddc__SHIFT 0x18 2263#define DPM_TABLE_326__UvdLevel_4_padding_1_MASK 0xff 2264#define DPM_TABLE_326__UvdLevel_4_padding_1__SHIFT 0x0 2265#define DPM_TABLE_326__UvdLevel_4_padding_0_MASK 0xff00 2266#define DPM_TABLE_326__UvdLevel_4_padding_0__SHIFT 0x8 2267#define DPM_TABLE_326__UvdLevel_4_DclkDivider_MASK 0xff0000 2268#define DPM_TABLE_326__UvdLevel_4_DclkDivider__SHIFT 0x10 2269#define DPM_TABLE_326__UvdLevel_4_VclkDivider_MASK 0xff000000 2270#define DPM_TABLE_326__UvdLevel_4_VclkDivider__SHIFT 0x18 2271#define DPM_TABLE_327__UvdLevel_5_VclkFrequency_MASK 0xffffffff 2272#define DPM_TABLE_327__UvdLevel_5_VclkFrequency__SHIFT 0x0 2273#define DPM_TABLE_328__UvdLevel_5_DclkFrequency_MASK 0xffffffff 2274#define DPM_TABLE_328__UvdLevel_5_DclkFrequency__SHIFT 0x0 2275#define DPM_TABLE_329__UvdLevel_5_MinVoltage_Phases_MASK 0xff 2276#define DPM_TABLE_329__UvdLevel_5_MinVoltage_Phases__SHIFT 0x0 2277#define DPM_TABLE_329__UvdLevel_5_MinVoltage_VddGfx_MASK 0xff00 2278#define DPM_TABLE_329__UvdLevel_5_MinVoltage_VddGfx__SHIFT 0x8 2279#define DPM_TABLE_329__UvdLevel_5_MinVoltage_Vddci_MASK 0xff0000 2280#define DPM_TABLE_329__UvdLevel_5_MinVoltage_Vddci__SHIFT 0x10 2281#define DPM_TABLE_329__UvdLevel_5_MinVoltage_Vddc_MASK 0xff000000 2282#define DPM_TABLE_329__UvdLevel_5_MinVoltage_Vddc__SHIFT 0x18 2283#define DPM_TABLE_330__UvdLevel_5_padding_1_MASK 0xff 2284#define DPM_TABLE_330__UvdLevel_5_padding_1__SHIFT 0x0 2285#define DPM_TABLE_330__UvdLevel_5_padding_0_MASK 0xff00 2286#define DPM_TABLE_330__UvdLevel_5_padding_0__SHIFT 0x8 2287#define DPM_TABLE_330__UvdLevel_5_DclkDivider_MASK 0xff0000 2288#define DPM_TABLE_330__UvdLevel_5_DclkDivider__SHIFT 0x10 2289#define DPM_TABLE_330__UvdLevel_5_VclkDivider_MASK 0xff000000 2290#define DPM_TABLE_330__UvdLevel_5_VclkDivider__SHIFT 0x18 2291#define DPM_TABLE_331__UvdLevel_6_VclkFrequency_MASK 0xffffffff 2292#define DPM_TABLE_331__UvdLevel_6_VclkFrequency__SHIFT 0x0 2293#define DPM_TABLE_332__UvdLevel_6_DclkFrequency_MASK 0xffffffff 2294#define DPM_TABLE_332__UvdLevel_6_DclkFrequency__SHIFT 0x0 2295#define DPM_TABLE_333__UvdLevel_6_MinVoltage_Phases_MASK 0xff 2296#define DPM_TABLE_333__UvdLevel_6_MinVoltage_Phases__SHIFT 0x0 2297#define DPM_TABLE_333__UvdLevel_6_MinVoltage_VddGfx_MASK 0xff00 2298#define DPM_TABLE_333__UvdLevel_6_MinVoltage_VddGfx__SHIFT 0x8 2299#define DPM_TABLE_333__UvdLevel_6_MinVoltage_Vddci_MASK 0xff0000 2300#define DPM_TABLE_333__UvdLevel_6_MinVoltage_Vddci__SHIFT 0x10 2301#define DPM_TABLE_333__UvdLevel_6_MinVoltage_Vddc_MASK 0xff000000 2302#define DPM_TABLE_333__UvdLevel_6_MinVoltage_Vddc__SHIFT 0x18 2303#define DPM_TABLE_334__UvdLevel_6_padding_1_MASK 0xff 2304#define DPM_TABLE_334__UvdLevel_6_padding_1__SHIFT 0x0 2305#define DPM_TABLE_334__UvdLevel_6_padding_0_MASK 0xff00 2306#define DPM_TABLE_334__UvdLevel_6_padding_0__SHIFT 0x8 2307#define DPM_TABLE_334__UvdLevel_6_DclkDivider_MASK 0xff0000 2308#define DPM_TABLE_334__UvdLevel_6_DclkDivider__SHIFT 0x10 2309#define DPM_TABLE_334__UvdLevel_6_VclkDivider_MASK 0xff000000 2310#define DPM_TABLE_334__UvdLevel_6_VclkDivider__SHIFT 0x18 2311#define DPM_TABLE_335__UvdLevel_7_VclkFrequency_MASK 0xffffffff 2312#define DPM_TABLE_335__UvdLevel_7_VclkFrequency__SHIFT 0x0 2313#define DPM_TABLE_336__UvdLevel_7_DclkFrequency_MASK 0xffffffff 2314#define DPM_TABLE_336__UvdLevel_7_DclkFrequency__SHIFT 0x0 2315#define DPM_TABLE_337__UvdLevel_7_MinVoltage_Phases_MASK 0xff 2316#define DPM_TABLE_337__UvdLevel_7_MinVoltage_Phases__SHIFT 0x0 2317#define DPM_TABLE_337__UvdLevel_7_MinVoltage_VddGfx_MASK 0xff00 2318#define DPM_TABLE_337__UvdLevel_7_MinVoltage_VddGfx__SHIFT 0x8 2319#define DPM_TABLE_337__UvdLevel_7_MinVoltage_Vddci_MASK 0xff0000 2320#define DPM_TABLE_337__UvdLevel_7_MinVoltage_Vddci__SHIFT 0x10 2321#define DPM_TABLE_337__UvdLevel_7_MinVoltage_Vddc_MASK 0xff000000 2322#define DPM_TABLE_337__UvdLevel_7_MinVoltage_Vddc__SHIFT 0x18 2323#define DPM_TABLE_338__UvdLevel_7_padding_1_MASK 0xff 2324#define DPM_TABLE_338__UvdLevel_7_padding_1__SHIFT 0x0 2325#define DPM_TABLE_338__UvdLevel_7_padding_0_MASK 0xff00 2326#define DPM_TABLE_338__UvdLevel_7_padding_0__SHIFT 0x8 2327#define DPM_TABLE_338__UvdLevel_7_DclkDivider_MASK 0xff0000 2328#define DPM_TABLE_338__UvdLevel_7_DclkDivider__SHIFT 0x10 2329#define DPM_TABLE_338__UvdLevel_7_VclkDivider_MASK 0xff000000 2330#define DPM_TABLE_338__UvdLevel_7_VclkDivider__SHIFT 0x18 2331#define DPM_TABLE_339__VceLevel_0_Frequency_MASK 0xffffffff 2332#define DPM_TABLE_339__VceLevel_0_Frequency__SHIFT 0x0 2333#define DPM_TABLE_340__VceLevel_0_MinVoltage_Phases_MASK 0xff 2334#define DPM_TABLE_340__VceLevel_0_MinVoltage_Phases__SHIFT 0x0 2335#define DPM_TABLE_340__VceLevel_0_MinVoltage_VddGfx_MASK 0xff00 2336#define DPM_TABLE_340__VceLevel_0_MinVoltage_VddGfx__SHIFT 0x8 2337#define DPM_TABLE_340__VceLevel_0_MinVoltage_Vddci_MASK 0xff0000 2338#define DPM_TABLE_340__VceLevel_0_MinVoltage_Vddci__SHIFT 0x10 2339#define DPM_TABLE_340__VceLevel_0_MinVoltage_Vddc_MASK 0xff000000 2340#define DPM_TABLE_340__VceLevel_0_MinVoltage_Vddc__SHIFT 0x18 2341#define DPM_TABLE_341__VceLevel_0_padding_2_MASK 0xff 2342#define DPM_TABLE_341__VceLevel_0_padding_2__SHIFT 0x0 2343#define DPM_TABLE_341__VceLevel_0_padding_1_MASK 0xff00 2344#define DPM_TABLE_341__VceLevel_0_padding_1__SHIFT 0x8 2345#define DPM_TABLE_341__VceLevel_0_padding_0_MASK 0xff0000 2346#define DPM_TABLE_341__VceLevel_0_padding_0__SHIFT 0x10 2347#define DPM_TABLE_341__VceLevel_0_Divider_MASK 0xff000000 2348#define DPM_TABLE_341__VceLevel_0_Divider__SHIFT 0x18 2349#define DPM_TABLE_342__VceLevel_1_Frequency_MASK 0xffffffff 2350#define DPM_TABLE_342__VceLevel_1_Frequency__SHIFT 0x0 2351#define DPM_TABLE_343__VceLevel_1_MinVoltage_Phases_MASK 0xff 2352#define DPM_TABLE_343__VceLevel_1_MinVoltage_Phases__SHIFT 0x0 2353#define DPM_TABLE_343__VceLevel_1_MinVoltage_VddGfx_MASK 0xff00 2354#define DPM_TABLE_343__VceLevel_1_MinVoltage_VddGfx__SHIFT 0x8 2355#define DPM_TABLE_343__VceLevel_1_MinVoltage_Vddci_MASK 0xff0000 2356#define DPM_TABLE_343__VceLevel_1_MinVoltage_Vddci__SHIFT 0x10 2357#define DPM_TABLE_343__VceLevel_1_MinVoltage_Vddc_MASK 0xff000000 2358#define DPM_TABLE_343__VceLevel_1_MinVoltage_Vddc__SHIFT 0x18 2359#define DPM_TABLE_344__VceLevel_1_padding_2_MASK 0xff 2360#define DPM_TABLE_344__VceLevel_1_padding_2__SHIFT 0x0 2361#define DPM_TABLE_344__VceLevel_1_padding_1_MASK 0xff00 2362#define DPM_TABLE_344__VceLevel_1_padding_1__SHIFT 0x8 2363#define DPM_TABLE_344__VceLevel_1_padding_0_MASK 0xff0000 2364#define DPM_TABLE_344__VceLevel_1_padding_0__SHIFT 0x10 2365#define DPM_TABLE_344__VceLevel_1_Divider_MASK 0xff000000 2366#define DPM_TABLE_344__VceLevel_1_Divider__SHIFT 0x18 2367#define DPM_TABLE_345__VceLevel_2_Frequency_MASK 0xffffffff 2368#define DPM_TABLE_345__VceLevel_2_Frequency__SHIFT 0x0 2369#define DPM_TABLE_346__VceLevel_2_MinVoltage_Phases_MASK 0xff 2370#define DPM_TABLE_346__VceLevel_2_MinVoltage_Phases__SHIFT 0x0 2371#define DPM_TABLE_346__VceLevel_2_MinVoltage_VddGfx_MASK 0xff00 2372#define DPM_TABLE_346__VceLevel_2_MinVoltage_VddGfx__SHIFT 0x8 2373#define DPM_TABLE_346__VceLevel_2_MinVoltage_Vddci_MASK 0xff0000 2374#define DPM_TABLE_346__VceLevel_2_MinVoltage_Vddci__SHIFT 0x10 2375#define DPM_TABLE_346__VceLevel_2_MinVoltage_Vddc_MASK 0xff000000 2376#define DPM_TABLE_346__VceLevel_2_MinVoltage_Vddc__SHIFT 0x18 2377#define DPM_TABLE_347__VceLevel_2_padding_2_MASK 0xff 2378#define DPM_TABLE_347__VceLevel_2_padding_2__SHIFT 0x0 2379#define DPM_TABLE_347__VceLevel_2_padding_1_MASK 0xff00 2380#define DPM_TABLE_347__VceLevel_2_padding_1__SHIFT 0x8 2381#define DPM_TABLE_347__VceLevel_2_padding_0_MASK 0xff0000 2382#define DPM_TABLE_347__VceLevel_2_padding_0__SHIFT 0x10 2383#define DPM_TABLE_347__VceLevel_2_Divider_MASK 0xff000000 2384#define DPM_TABLE_347__VceLevel_2_Divider__SHIFT 0x18 2385#define DPM_TABLE_348__VceLevel_3_Frequency_MASK 0xffffffff 2386#define DPM_TABLE_348__VceLevel_3_Frequency__SHIFT 0x0 2387#define DPM_TABLE_349__VceLevel_3_MinVoltage_Phases_MASK 0xff 2388#define DPM_TABLE_349__VceLevel_3_MinVoltage_Phases__SHIFT 0x0 2389#define DPM_TABLE_349__VceLevel_3_MinVoltage_VddGfx_MASK 0xff00 2390#define DPM_TABLE_349__VceLevel_3_MinVoltage_VddGfx__SHIFT 0x8 2391#define DPM_TABLE_349__VceLevel_3_MinVoltage_Vddci_MASK 0xff0000 2392#define DPM_TABLE_349__VceLevel_3_MinVoltage_Vddci__SHIFT 0x10 2393#define DPM_TABLE_349__VceLevel_3_MinVoltage_Vddc_MASK 0xff000000 2394#define DPM_TABLE_349__VceLevel_3_MinVoltage_Vddc__SHIFT 0x18 2395#define DPM_TABLE_350__VceLevel_3_padding_2_MASK 0xff 2396#define DPM_TABLE_350__VceLevel_3_padding_2__SHIFT 0x0 2397#define DPM_TABLE_350__VceLevel_3_padding_1_MASK 0xff00 2398#define DPM_TABLE_350__VceLevel_3_padding_1__SHIFT 0x8 2399#define DPM_TABLE_350__VceLevel_3_padding_0_MASK 0xff0000 2400#define DPM_TABLE_350__VceLevel_3_padding_0__SHIFT 0x10 2401#define DPM_TABLE_350__VceLevel_3_Divider_MASK 0xff000000 2402#define DPM_TABLE_350__VceLevel_3_Divider__SHIFT 0x18 2403#define DPM_TABLE_351__VceLevel_4_Frequency_MASK 0xffffffff 2404#define DPM_TABLE_351__VceLevel_4_Frequency__SHIFT 0x0 2405#define DPM_TABLE_352__VceLevel_4_MinVoltage_Phases_MASK 0xff 2406#define DPM_TABLE_352__VceLevel_4_MinVoltage_Phases__SHIFT 0x0 2407#define DPM_TABLE_352__VceLevel_4_MinVoltage_VddGfx_MASK 0xff00 2408#define DPM_TABLE_352__VceLevel_4_MinVoltage_VddGfx__SHIFT 0x8 2409#define DPM_TABLE_352__VceLevel_4_MinVoltage_Vddci_MASK 0xff0000 2410#define DPM_TABLE_352__VceLevel_4_MinVoltage_Vddci__SHIFT 0x10 2411#define DPM_TABLE_352__VceLevel_4_MinVoltage_Vddc_MASK 0xff000000 2412#define DPM_TABLE_352__VceLevel_4_MinVoltage_Vddc__SHIFT 0x18 2413#define DPM_TABLE_353__VceLevel_4_padding_2_MASK 0xff 2414#define DPM_TABLE_353__VceLevel_4_padding_2__SHIFT 0x0 2415#define DPM_TABLE_353__VceLevel_4_padding_1_MASK 0xff00 2416#define DPM_TABLE_353__VceLevel_4_padding_1__SHIFT 0x8 2417#define DPM_TABLE_353__VceLevel_4_padding_0_MASK 0xff0000 2418#define DPM_TABLE_353__VceLevel_4_padding_0__SHIFT 0x10 2419#define DPM_TABLE_353__VceLevel_4_Divider_MASK 0xff000000 2420#define DPM_TABLE_353__VceLevel_4_Divider__SHIFT 0x18 2421#define DPM_TABLE_354__VceLevel_5_Frequency_MASK 0xffffffff 2422#define DPM_TABLE_354__VceLevel_5_Frequency__SHIFT 0x0 2423#define DPM_TABLE_355__VceLevel_5_MinVoltage_Phases_MASK 0xff 2424#define DPM_TABLE_355__VceLevel_5_MinVoltage_Phases__SHIFT 0x0 2425#define DPM_TABLE_355__VceLevel_5_MinVoltage_VddGfx_MASK 0xff00 2426#define DPM_TABLE_355__VceLevel_5_MinVoltage_VddGfx__SHIFT 0x8 2427#define DPM_TABLE_355__VceLevel_5_MinVoltage_Vddci_MASK 0xff0000 2428#define DPM_TABLE_355__VceLevel_5_MinVoltage_Vddci__SHIFT 0x10 2429#define DPM_TABLE_355__VceLevel_5_MinVoltage_Vddc_MASK 0xff000000 2430#define DPM_TABLE_355__VceLevel_5_MinVoltage_Vddc__SHIFT 0x18 2431#define DPM_TABLE_356__VceLevel_5_padding_2_MASK 0xff 2432#define DPM_TABLE_356__VceLevel_5_padding_2__SHIFT 0x0 2433#define DPM_TABLE_356__VceLevel_5_padding_1_MASK 0xff00 2434#define DPM_TABLE_356__VceLevel_5_padding_1__SHIFT 0x8 2435#define DPM_TABLE_356__VceLevel_5_padding_0_MASK 0xff0000 2436#define DPM_TABLE_356__VceLevel_5_padding_0__SHIFT 0x10 2437#define DPM_TABLE_356__VceLevel_5_Divider_MASK 0xff000000 2438#define DPM_TABLE_356__VceLevel_5_Divider__SHIFT 0x18 2439#define DPM_TABLE_357__VceLevel_6_Frequency_MASK 0xffffffff 2440#define DPM_TABLE_357__VceLevel_6_Frequency__SHIFT 0x0 2441#define DPM_TABLE_358__VceLevel_6_MinVoltage_Phases_MASK 0xff 2442#define DPM_TABLE_358__VceLevel_6_MinVoltage_Phases__SHIFT 0x0 2443#define DPM_TABLE_358__VceLevel_6_MinVoltage_VddGfx_MASK 0xff00 2444#define DPM_TABLE_358__VceLevel_6_MinVoltage_VddGfx__SHIFT 0x8 2445#define DPM_TABLE_358__VceLevel_6_MinVoltage_Vddci_MASK 0xff0000 2446#define DPM_TABLE_358__VceLevel_6_MinVoltage_Vddci__SHIFT 0x10 2447#define DPM_TABLE_358__VceLevel_6_MinVoltage_Vddc_MASK 0xff000000 2448#define DPM_TABLE_358__VceLevel_6_MinVoltage_Vddc__SHIFT 0x18 2449#define DPM_TABLE_359__VceLevel_6_padding_2_MASK 0xff 2450#define DPM_TABLE_359__VceLevel_6_padding_2__SHIFT 0x0 2451#define DPM_TABLE_359__VceLevel_6_padding_1_MASK 0xff00 2452#define DPM_TABLE_359__VceLevel_6_padding_1__SHIFT 0x8 2453#define DPM_TABLE_359__VceLevel_6_padding_0_MASK 0xff0000 2454#define DPM_TABLE_359__VceLevel_6_padding_0__SHIFT 0x10 2455#define DPM_TABLE_359__VceLevel_6_Divider_MASK 0xff000000 2456#define DPM_TABLE_359__VceLevel_6_Divider__SHIFT 0x18 2457#define DPM_TABLE_360__VceLevel_7_Frequency_MASK 0xffffffff 2458#define DPM_TABLE_360__VceLevel_7_Frequency__SHIFT 0x0 2459#define DPM_TABLE_361__VceLevel_7_MinVoltage_Phases_MASK 0xff 2460#define DPM_TABLE_361__VceLevel_7_MinVoltage_Phases__SHIFT 0x0 2461#define DPM_TABLE_361__VceLevel_7_MinVoltage_VddGfx_MASK 0xff00 2462#define DPM_TABLE_361__VceLevel_7_MinVoltage_VddGfx__SHIFT 0x8 2463#define DPM_TABLE_361__VceLevel_7_MinVoltage_Vddci_MASK 0xff0000 2464#define DPM_TABLE_361__VceLevel_7_MinVoltage_Vddci__SHIFT 0x10 2465#define DPM_TABLE_361__VceLevel_7_MinVoltage_Vddc_MASK 0xff000000 2466#define DPM_TABLE_361__VceLevel_7_MinVoltage_Vddc__SHIFT 0x18 2467#define DPM_TABLE_362__VceLevel_7_padding_2_MASK 0xff 2468#define DPM_TABLE_362__VceLevel_7_padding_2__SHIFT 0x0 2469#define DPM_TABLE_362__VceLevel_7_padding_1_MASK 0xff00 2470#define DPM_TABLE_362__VceLevel_7_padding_1__SHIFT 0x8 2471#define DPM_TABLE_362__VceLevel_7_padding_0_MASK 0xff0000 2472#define DPM_TABLE_362__VceLevel_7_padding_0__SHIFT 0x10 2473#define DPM_TABLE_362__VceLevel_7_Divider_MASK 0xff000000 2474#define DPM_TABLE_362__VceLevel_7_Divider__SHIFT 0x18 2475#define DPM_TABLE_363__AcpLevel_0_Frequency_MASK 0xffffffff 2476#define DPM_TABLE_363__AcpLevel_0_Frequency__SHIFT 0x0 2477#define DPM_TABLE_364__AcpLevel_0_MinVoltage_Phases_MASK 0xff 2478#define DPM_TABLE_364__AcpLevel_0_MinVoltage_Phases__SHIFT 0x0 2479#define DPM_TABLE_364__AcpLevel_0_MinVoltage_VddGfx_MASK 0xff00 2480#define DPM_TABLE_364__AcpLevel_0_MinVoltage_VddGfx__SHIFT 0x8 2481#define DPM_TABLE_364__AcpLevel_0_MinVoltage_Vddci_MASK 0xff0000 2482#define DPM_TABLE_364__AcpLevel_0_MinVoltage_Vddci__SHIFT 0x10 2483#define DPM_TABLE_364__AcpLevel_0_MinVoltage_Vddc_MASK 0xff000000 2484#define DPM_TABLE_364__AcpLevel_0_MinVoltage_Vddc__SHIFT 0x18 2485#define DPM_TABLE_365__AcpLevel_0_padding_2_MASK 0xff 2486#define DPM_TABLE_365__AcpLevel_0_padding_2__SHIFT 0x0 2487#define DPM_TABLE_365__AcpLevel_0_padding_1_MASK 0xff00 2488#define DPM_TABLE_365__AcpLevel_0_padding_1__SHIFT 0x8 2489#define DPM_TABLE_365__AcpLevel_0_padding_0_MASK 0xff0000 2490#define DPM_TABLE_365__AcpLevel_0_padding_0__SHIFT 0x10 2491#define DPM_TABLE_365__AcpLevel_0_Divider_MASK 0xff000000 2492#define DPM_TABLE_365__AcpLevel_0_Divider__SHIFT 0x18 2493#define DPM_TABLE_366__AcpLevel_1_Frequency_MASK 0xffffffff 2494#define DPM_TABLE_366__AcpLevel_1_Frequency__SHIFT 0x0 2495#define DPM_TABLE_367__AcpLevel_1_MinVoltage_Phases_MASK 0xff 2496#define DPM_TABLE_367__AcpLevel_1_MinVoltage_Phases__SHIFT 0x0 2497#define DPM_TABLE_367__AcpLevel_1_MinVoltage_VddGfx_MASK 0xff00 2498#define DPM_TABLE_367__AcpLevel_1_MinVoltage_VddGfx__SHIFT 0x8 2499#define DPM_TABLE_367__AcpLevel_1_MinVoltage_Vddci_MASK 0xff0000 2500#define DPM_TABLE_367__AcpLevel_1_MinVoltage_Vddci__SHIFT 0x10 2501#define DPM_TABLE_367__AcpLevel_1_MinVoltage_Vddc_MASK 0xff000000 2502#define DPM_TABLE_367__AcpLevel_1_MinVoltage_Vddc__SHIFT 0x18 2503#define DPM_TABLE_368__AcpLevel_1_padding_2_MASK 0xff 2504#define DPM_TABLE_368__AcpLevel_1_padding_2__SHIFT 0x0 2505#define DPM_TABLE_368__AcpLevel_1_padding_1_MASK 0xff00 2506#define DPM_TABLE_368__AcpLevel_1_padding_1__SHIFT 0x8 2507#define DPM_TABLE_368__AcpLevel_1_padding_0_MASK 0xff0000 2508#define DPM_TABLE_368__AcpLevel_1_padding_0__SHIFT 0x10 2509#define DPM_TABLE_368__AcpLevel_1_Divider_MASK 0xff000000 2510#define DPM_TABLE_368__AcpLevel_1_Divider__SHIFT 0x18 2511#define DPM_TABLE_369__AcpLevel_2_Frequency_MASK 0xffffffff 2512#define DPM_TABLE_369__AcpLevel_2_Frequency__SHIFT 0x0 2513#define DPM_TABLE_370__AcpLevel_2_MinVoltage_Phases_MASK 0xff 2514#define DPM_TABLE_370__AcpLevel_2_MinVoltage_Phases__SHIFT 0x0 2515#define DPM_TABLE_370__AcpLevel_2_MinVoltage_VddGfx_MASK 0xff00 2516#define DPM_TABLE_370__AcpLevel_2_MinVoltage_VddGfx__SHIFT 0x8 2517#define DPM_TABLE_370__AcpLevel_2_MinVoltage_Vddci_MASK 0xff0000 2518#define DPM_TABLE_370__AcpLevel_2_MinVoltage_Vddci__SHIFT 0x10 2519#define DPM_TABLE_370__AcpLevel_2_MinVoltage_Vddc_MASK 0xff000000 2520#define DPM_TABLE_370__AcpLevel_2_MinVoltage_Vddc__SHIFT 0x18 2521#define DPM_TABLE_371__AcpLevel_2_padding_2_MASK 0xff 2522#define DPM_TABLE_371__AcpLevel_2_padding_2__SHIFT 0x0 2523#define DPM_TABLE_371__AcpLevel_2_padding_1_MASK 0xff00 2524#define DPM_TABLE_371__AcpLevel_2_padding_1__SHIFT 0x8 2525#define DPM_TABLE_371__AcpLevel_2_padding_0_MASK 0xff0000 2526#define DPM_TABLE_371__AcpLevel_2_padding_0__SHIFT 0x10 2527#define DPM_TABLE_371__AcpLevel_2_Divider_MASK 0xff000000 2528#define DPM_TABLE_371__AcpLevel_2_Divider__SHIFT 0x18 2529#define DPM_TABLE_372__AcpLevel_3_Frequency_MASK 0xffffffff 2530#define DPM_TABLE_372__AcpLevel_3_Frequency__SHIFT 0x0 2531#define DPM_TABLE_373__AcpLevel_3_MinVoltage_Phases_MASK 0xff 2532#define DPM_TABLE_373__AcpLevel_3_MinVoltage_Phases__SHIFT 0x0 2533#define DPM_TABLE_373__AcpLevel_3_MinVoltage_VddGfx_MASK 0xff00 2534#define DPM_TABLE_373__AcpLevel_3_MinVoltage_VddGfx__SHIFT 0x8 2535#define DPM_TABLE_373__AcpLevel_3_MinVoltage_Vddci_MASK 0xff0000 2536#define DPM_TABLE_373__AcpLevel_3_MinVoltage_Vddci__SHIFT 0x10 2537#define DPM_TABLE_373__AcpLevel_3_MinVoltage_Vddc_MASK 0xff000000 2538#define DPM_TABLE_373__AcpLevel_3_MinVoltage_Vddc__SHIFT 0x18 2539#define DPM_TABLE_374__AcpLevel_3_padding_2_MASK 0xff 2540#define DPM_TABLE_374__AcpLevel_3_padding_2__SHIFT 0x0 2541#define DPM_TABLE_374__AcpLevel_3_padding_1_MASK 0xff00 2542#define DPM_TABLE_374__AcpLevel_3_padding_1__SHIFT 0x8 2543#define DPM_TABLE_374__AcpLevel_3_padding_0_MASK 0xff0000 2544#define DPM_TABLE_374__AcpLevel_3_padding_0__SHIFT 0x10 2545#define DPM_TABLE_374__AcpLevel_3_Divider_MASK 0xff000000 2546#define DPM_TABLE_374__AcpLevel_3_Divider__SHIFT 0x18 2547#define DPM_TABLE_375__AcpLevel_4_Frequency_MASK 0xffffffff 2548#define DPM_TABLE_375__AcpLevel_4_Frequency__SHIFT 0x0 2549#define DPM_TABLE_376__AcpLevel_4_MinVoltage_Phases_MASK 0xff 2550#define DPM_TABLE_376__AcpLevel_4_MinVoltage_Phases__SHIFT 0x0 2551#define DPM_TABLE_376__AcpLevel_4_MinVoltage_VddGfx_MASK 0xff00 2552#define DPM_TABLE_376__AcpLevel_4_MinVoltage_VddGfx__SHIFT 0x8 2553#define DPM_TABLE_376__AcpLevel_4_MinVoltage_Vddci_MASK 0xff0000 2554#define DPM_TABLE_376__AcpLevel_4_MinVoltage_Vddci__SHIFT 0x10 2555#define DPM_TABLE_376__AcpLevel_4_MinVoltage_Vddc_MASK 0xff000000 2556#define DPM_TABLE_376__AcpLevel_4_MinVoltage_Vddc__SHIFT 0x18 2557#define DPM_TABLE_377__AcpLevel_4_padding_2_MASK 0xff 2558#define DPM_TABLE_377__AcpLevel_4_padding_2__SHIFT 0x0 2559#define DPM_TABLE_377__AcpLevel_4_padding_1_MASK 0xff00 2560#define DPM_TABLE_377__AcpLevel_4_padding_1__SHIFT 0x8 2561#define DPM_TABLE_377__AcpLevel_4_padding_0_MASK 0xff0000 2562#define DPM_TABLE_377__AcpLevel_4_padding_0__SHIFT 0x10 2563#define DPM_TABLE_377__AcpLevel_4_Divider_MASK 0xff000000 2564#define DPM_TABLE_377__AcpLevel_4_Divider__SHIFT 0x18 2565#define DPM_TABLE_378__AcpLevel_5_Frequency_MASK 0xffffffff 2566#define DPM_TABLE_378__AcpLevel_5_Frequency__SHIFT 0x0 2567#define DPM_TABLE_379__AcpLevel_5_MinVoltage_Phases_MASK 0xff 2568#define DPM_TABLE_379__AcpLevel_5_MinVoltage_Phases__SHIFT 0x0 2569#define DPM_TABLE_379__AcpLevel_5_MinVoltage_VddGfx_MASK 0xff00 2570#define DPM_TABLE_379__AcpLevel_5_MinVoltage_VddGfx__SHIFT 0x8 2571#define DPM_TABLE_379__AcpLevel_5_MinVoltage_Vddci_MASK 0xff0000 2572#define DPM_TABLE_379__AcpLevel_5_MinVoltage_Vddci__SHIFT 0x10 2573#define DPM_TABLE_379__AcpLevel_5_MinVoltage_Vddc_MASK 0xff000000 2574#define DPM_TABLE_379__AcpLevel_5_MinVoltage_Vddc__SHIFT 0x18 2575#define DPM_TABLE_380__AcpLevel_5_padding_2_MASK 0xff 2576#define DPM_TABLE_380__AcpLevel_5_padding_2__SHIFT 0x0 2577#define DPM_TABLE_380__AcpLevel_5_padding_1_MASK 0xff00 2578#define DPM_TABLE_380__AcpLevel_5_padding_1__SHIFT 0x8 2579#define DPM_TABLE_380__AcpLevel_5_padding_0_MASK 0xff0000 2580#define DPM_TABLE_380__AcpLevel_5_padding_0__SHIFT 0x10 2581#define DPM_TABLE_380__AcpLevel_5_Divider_MASK 0xff000000 2582#define DPM_TABLE_380__AcpLevel_5_Divider__SHIFT 0x18 2583#define DPM_TABLE_381__AcpLevel_6_Frequency_MASK 0xffffffff 2584#define DPM_TABLE_381__AcpLevel_6_Frequency__SHIFT 0x0 2585#define DPM_TABLE_382__AcpLevel_6_MinVoltage_Phases_MASK 0xff 2586#define DPM_TABLE_382__AcpLevel_6_MinVoltage_Phases__SHIFT 0x0 2587#define DPM_TABLE_382__AcpLevel_6_MinVoltage_VddGfx_MASK 0xff00 2588#define DPM_TABLE_382__AcpLevel_6_MinVoltage_VddGfx__SHIFT 0x8 2589#define DPM_TABLE_382__AcpLevel_6_MinVoltage_Vddci_MASK 0xff0000 2590#define DPM_TABLE_382__AcpLevel_6_MinVoltage_Vddci__SHIFT 0x10 2591#define DPM_TABLE_382__AcpLevel_6_MinVoltage_Vddc_MASK 0xff000000 2592#define DPM_TABLE_382__AcpLevel_6_MinVoltage_Vddc__SHIFT 0x18 2593#define DPM_TABLE_383__AcpLevel_6_padding_2_MASK 0xff 2594#define DPM_TABLE_383__AcpLevel_6_padding_2__SHIFT 0x0 2595#define DPM_TABLE_383__AcpLevel_6_padding_1_MASK 0xff00 2596#define DPM_TABLE_383__AcpLevel_6_padding_1__SHIFT 0x8 2597#define DPM_TABLE_383__AcpLevel_6_padding_0_MASK 0xff0000 2598#define DPM_TABLE_383__AcpLevel_6_padding_0__SHIFT 0x10 2599#define DPM_TABLE_383__AcpLevel_6_Divider_MASK 0xff000000 2600#define DPM_TABLE_383__AcpLevel_6_Divider__SHIFT 0x18 2601#define DPM_TABLE_384__AcpLevel_7_Frequency_MASK 0xffffffff 2602#define DPM_TABLE_384__AcpLevel_7_Frequency__SHIFT 0x0 2603#define DPM_TABLE_385__AcpLevel_7_MinVoltage_Phases_MASK 0xff 2604#define DPM_TABLE_385__AcpLevel_7_MinVoltage_Phases__SHIFT 0x0 2605#define DPM_TABLE_385__AcpLevel_7_MinVoltage_VddGfx_MASK 0xff00 2606#define DPM_TABLE_385__AcpLevel_7_MinVoltage_VddGfx__SHIFT 0x8 2607#define DPM_TABLE_385__AcpLevel_7_MinVoltage_Vddci_MASK 0xff0000 2608#define DPM_TABLE_385__AcpLevel_7_MinVoltage_Vddci__SHIFT 0x10 2609#define DPM_TABLE_385__AcpLevel_7_MinVoltage_Vddc_MASK 0xff000000 2610#define DPM_TABLE_385__AcpLevel_7_MinVoltage_Vddc__SHIFT 0x18 2611#define DPM_TABLE_386__AcpLevel_7_padding_2_MASK 0xff 2612#define DPM_TABLE_386__AcpLevel_7_padding_2__SHIFT 0x0 2613#define DPM_TABLE_386__AcpLevel_7_padding_1_MASK 0xff00 2614#define DPM_TABLE_386__AcpLevel_7_padding_1__SHIFT 0x8 2615#define DPM_TABLE_386__AcpLevel_7_padding_0_MASK 0xff0000 2616#define DPM_TABLE_386__AcpLevel_7_padding_0__SHIFT 0x10 2617#define DPM_TABLE_386__AcpLevel_7_Divider_MASK 0xff000000 2618#define DPM_TABLE_386__AcpLevel_7_Divider__SHIFT 0x18 2619#define DPM_TABLE_387__SamuLevel_0_Frequency_MASK 0xffffffff 2620#define DPM_TABLE_387__SamuLevel_0_Frequency__SHIFT 0x0 2621#define DPM_TABLE_388__SamuLevel_0_MinVoltage_Phases_MASK 0xff 2622#define DPM_TABLE_388__SamuLevel_0_MinVoltage_Phases__SHIFT 0x0 2623#define DPM_TABLE_388__SamuLevel_0_MinVoltage_VddGfx_MASK 0xff00 2624#define DPM_TABLE_388__SamuLevel_0_MinVoltage_VddGfx__SHIFT 0x8 2625#define DPM_TABLE_388__SamuLevel_0_MinVoltage_Vddci_MASK 0xff0000 2626#define DPM_TABLE_388__SamuLevel_0_MinVoltage_Vddci__SHIFT 0x10 2627#define DPM_TABLE_388__SamuLevel_0_MinVoltage_Vddc_MASK 0xff000000 2628#define DPM_TABLE_388__SamuLevel_0_MinVoltage_Vddc__SHIFT 0x18 2629#define DPM_TABLE_389__SamuLevel_0_padding_2_MASK 0xff 2630#define DPM_TABLE_389__SamuLevel_0_padding_2__SHIFT 0x0 2631#define DPM_TABLE_389__SamuLevel_0_padding_1_MASK 0xff00 2632#define DPM_TABLE_389__SamuLevel_0_padding_1__SHIFT 0x8 2633#define DPM_TABLE_389__SamuLevel_0_padding_0_MASK 0xff0000 2634#define DPM_TABLE_389__SamuLevel_0_padding_0__SHIFT 0x10 2635#define DPM_TABLE_389__SamuLevel_0_Divider_MASK 0xff000000 2636#define DPM_TABLE_389__SamuLevel_0_Divider__SHIFT 0x18 2637#define DPM_TABLE_390__SamuLevel_1_Frequency_MASK 0xffffffff 2638#define DPM_TABLE_390__SamuLevel_1_Frequency__SHIFT 0x0 2639#define DPM_TABLE_391__SamuLevel_1_MinVoltage_Phases_MASK 0xff 2640#define DPM_TABLE_391__SamuLevel_1_MinVoltage_Phases__SHIFT 0x0 2641#define DPM_TABLE_391__SamuLevel_1_MinVoltage_VddGfx_MASK 0xff00 2642#define DPM_TABLE_391__SamuLevel_1_MinVoltage_VddGfx__SHIFT 0x8 2643#define DPM_TABLE_391__SamuLevel_1_MinVoltage_Vddci_MASK 0xff0000 2644#define DPM_TABLE_391__SamuLevel_1_MinVoltage_Vddci__SHIFT 0x10 2645#define DPM_TABLE_391__SamuLevel_1_MinVoltage_Vddc_MASK 0xff000000 2646#define DPM_TABLE_391__SamuLevel_1_MinVoltage_Vddc__SHIFT 0x18 2647#define DPM_TABLE_392__SamuLevel_1_padding_2_MASK 0xff 2648#define DPM_TABLE_392__SamuLevel_1_padding_2__SHIFT 0x0 2649#define DPM_TABLE_392__SamuLevel_1_padding_1_MASK 0xff00 2650#define DPM_TABLE_392__SamuLevel_1_padding_1__SHIFT 0x8 2651#define DPM_TABLE_392__SamuLevel_1_padding_0_MASK 0xff0000 2652#define DPM_TABLE_392__SamuLevel_1_padding_0__SHIFT 0x10 2653#define DPM_TABLE_392__SamuLevel_1_Divider_MASK 0xff000000 2654#define DPM_TABLE_392__SamuLevel_1_Divider__SHIFT 0x18 2655#define DPM_TABLE_393__SamuLevel_2_Frequency_MASK 0xffffffff 2656#define DPM_TABLE_393__SamuLevel_2_Frequency__SHIFT 0x0 2657#define DPM_TABLE_394__SamuLevel_2_MinVoltage_Phases_MASK 0xff 2658#define DPM_TABLE_394__SamuLevel_2_MinVoltage_Phases__SHIFT 0x0 2659#define DPM_TABLE_394__SamuLevel_2_MinVoltage_VddGfx_MASK 0xff00 2660#define DPM_TABLE_394__SamuLevel_2_MinVoltage_VddGfx__SHIFT 0x8 2661#define DPM_TABLE_394__SamuLevel_2_MinVoltage_Vddci_MASK 0xff0000 2662#define DPM_TABLE_394__SamuLevel_2_MinVoltage_Vddci__SHIFT 0x10 2663#define DPM_TABLE_394__SamuLevel_2_MinVoltage_Vddc_MASK 0xff000000 2664#define DPM_TABLE_394__SamuLevel_2_MinVoltage_Vddc__SHIFT 0x18 2665#define DPM_TABLE_395__SamuLevel_2_padding_2_MASK 0xff 2666#define DPM_TABLE_395__SamuLevel_2_padding_2__SHIFT 0x0 2667#define DPM_TABLE_395__SamuLevel_2_padding_1_MASK 0xff00 2668#define DPM_TABLE_395__SamuLevel_2_padding_1__SHIFT 0x8 2669#define DPM_TABLE_395__SamuLevel_2_padding_0_MASK 0xff0000 2670#define DPM_TABLE_395__SamuLevel_2_padding_0__SHIFT 0x10 2671#define DPM_TABLE_395__SamuLevel_2_Divider_MASK 0xff000000 2672#define DPM_TABLE_395__SamuLevel_2_Divider__SHIFT 0x18 2673#define DPM_TABLE_396__SamuLevel_3_Frequency_MASK 0xffffffff 2674#define DPM_TABLE_396__SamuLevel_3_Frequency__SHIFT 0x0 2675#define DPM_TABLE_397__SamuLevel_3_MinVoltage_Phases_MASK 0xff 2676#define DPM_TABLE_397__SamuLevel_3_MinVoltage_Phases__SHIFT 0x0 2677#define DPM_TABLE_397__SamuLevel_3_MinVoltage_VddGfx_MASK 0xff00 2678#define DPM_TABLE_397__SamuLevel_3_MinVoltage_VddGfx__SHIFT 0x8 2679#define DPM_TABLE_397__SamuLevel_3_MinVoltage_Vddci_MASK 0xff0000 2680#define DPM_TABLE_397__SamuLevel_3_MinVoltage_Vddci__SHIFT 0x10 2681#define DPM_TABLE_397__SamuLevel_3_MinVoltage_Vddc_MASK 0xff000000 2682#define DPM_TABLE_397__SamuLevel_3_MinVoltage_Vddc__SHIFT 0x18 2683#define DPM_TABLE_398__SamuLevel_3_padding_2_MASK 0xff 2684#define DPM_TABLE_398__SamuLevel_3_padding_2__SHIFT 0x0 2685#define DPM_TABLE_398__SamuLevel_3_padding_1_MASK 0xff00 2686#define DPM_TABLE_398__SamuLevel_3_padding_1__SHIFT 0x8 2687#define DPM_TABLE_398__SamuLevel_3_padding_0_MASK 0xff0000 2688#define DPM_TABLE_398__SamuLevel_3_padding_0__SHIFT 0x10 2689#define DPM_TABLE_398__SamuLevel_3_Divider_MASK 0xff000000 2690#define DPM_TABLE_398__SamuLevel_3_Divider__SHIFT 0x18 2691#define DPM_TABLE_399__SamuLevel_4_Frequency_MASK 0xffffffff 2692#define DPM_TABLE_399__SamuLevel_4_Frequency__SHIFT 0x0 2693#define DPM_TABLE_400__SamuLevel_4_MinVoltage_Phases_MASK 0xff 2694#define DPM_TABLE_400__SamuLevel_4_MinVoltage_Phases__SHIFT 0x0 2695#define DPM_TABLE_400__SamuLevel_4_MinVoltage_VddGfx_MASK 0xff00 2696#define DPM_TABLE_400__SamuLevel_4_MinVoltage_VddGfx__SHIFT 0x8 2697#define DPM_TABLE_400__SamuLevel_4_MinVoltage_Vddci_MASK 0xff0000 2698#define DPM_TABLE_400__SamuLevel_4_MinVoltage_Vddci__SHIFT 0x10 2699#define DPM_TABLE_400__SamuLevel_4_MinVoltage_Vddc_MASK 0xff000000 2700#define DPM_TABLE_400__SamuLevel_4_MinVoltage_Vddc__SHIFT 0x18 2701#define DPM_TABLE_401__SamuLevel_4_padding_2_MASK 0xff 2702#define DPM_TABLE_401__SamuLevel_4_padding_2__SHIFT 0x0 2703#define DPM_TABLE_401__SamuLevel_4_padding_1_MASK 0xff00 2704#define DPM_TABLE_401__SamuLevel_4_padding_1__SHIFT 0x8 2705#define DPM_TABLE_401__SamuLevel_4_padding_0_MASK 0xff0000 2706#define DPM_TABLE_401__SamuLevel_4_padding_0__SHIFT 0x10 2707#define DPM_TABLE_401__SamuLevel_4_Divider_MASK 0xff000000 2708#define DPM_TABLE_401__SamuLevel_4_Divider__SHIFT 0x18 2709#define DPM_TABLE_402__SamuLevel_5_Frequency_MASK 0xffffffff 2710#define DPM_TABLE_402__SamuLevel_5_Frequency__SHIFT 0x0 2711#define DPM_TABLE_403__SamuLevel_5_MinVoltage_Phases_MASK 0xff 2712#define DPM_TABLE_403__SamuLevel_5_MinVoltage_Phases__SHIFT 0x0 2713#define DPM_TABLE_403__SamuLevel_5_MinVoltage_VddGfx_MASK 0xff00 2714#define DPM_TABLE_403__SamuLevel_5_MinVoltage_VddGfx__SHIFT 0x8 2715#define DPM_TABLE_403__SamuLevel_5_MinVoltage_Vddci_MASK 0xff0000 2716#define DPM_TABLE_403__SamuLevel_5_MinVoltage_Vddci__SHIFT 0x10 2717#define DPM_TABLE_403__SamuLevel_5_MinVoltage_Vddc_MASK 0xff000000 2718#define DPM_TABLE_403__SamuLevel_5_MinVoltage_Vddc__SHIFT 0x18 2719#define DPM_TABLE_404__SamuLevel_5_padding_2_MASK 0xff 2720#define DPM_TABLE_404__SamuLevel_5_padding_2__SHIFT 0x0 2721#define DPM_TABLE_404__SamuLevel_5_padding_1_MASK 0xff00 2722#define DPM_TABLE_404__SamuLevel_5_padding_1__SHIFT 0x8 2723#define DPM_TABLE_404__SamuLevel_5_padding_0_MASK 0xff0000 2724#define DPM_TABLE_404__SamuLevel_5_padding_0__SHIFT 0x10 2725#define DPM_TABLE_404__SamuLevel_5_Divider_MASK 0xff000000 2726#define DPM_TABLE_404__SamuLevel_5_Divider__SHIFT 0x18 2727#define DPM_TABLE_405__SamuLevel_6_Frequency_MASK 0xffffffff 2728#define DPM_TABLE_405__SamuLevel_6_Frequency__SHIFT 0x0 2729#define DPM_TABLE_406__SamuLevel_6_MinVoltage_Phases_MASK 0xff 2730#define DPM_TABLE_406__SamuLevel_6_MinVoltage_Phases__SHIFT 0x0 2731#define DPM_TABLE_406__SamuLevel_6_MinVoltage_VddGfx_MASK 0xff00 2732#define DPM_TABLE_406__SamuLevel_6_MinVoltage_VddGfx__SHIFT 0x8 2733#define DPM_TABLE_406__SamuLevel_6_MinVoltage_Vddci_MASK 0xff0000 2734#define DPM_TABLE_406__SamuLevel_6_MinVoltage_Vddci__SHIFT 0x10 2735#define DPM_TABLE_406__SamuLevel_6_MinVoltage_Vddc_MASK 0xff000000 2736#define DPM_TABLE_406__SamuLevel_6_MinVoltage_Vddc__SHIFT 0x18 2737#define DPM_TABLE_407__SamuLevel_6_padding_2_MASK 0xff 2738#define DPM_TABLE_407__SamuLevel_6_padding_2__SHIFT 0x0 2739#define DPM_TABLE_407__SamuLevel_6_padding_1_MASK 0xff00 2740#define DPM_TABLE_407__SamuLevel_6_padding_1__SHIFT 0x8 2741#define DPM_TABLE_407__SamuLevel_6_padding_0_MASK 0xff0000 2742#define DPM_TABLE_407__SamuLevel_6_padding_0__SHIFT 0x10 2743#define DPM_TABLE_407__SamuLevel_6_Divider_MASK 0xff000000 2744#define DPM_TABLE_407__SamuLevel_6_Divider__SHIFT 0x18 2745#define DPM_TABLE_408__SamuLevel_7_Frequency_MASK 0xffffffff 2746#define DPM_TABLE_408__SamuLevel_7_Frequency__SHIFT 0x0 2747#define DPM_TABLE_409__SamuLevel_7_MinVoltage_Phases_MASK 0xff 2748#define DPM_TABLE_409__SamuLevel_7_MinVoltage_Phases__SHIFT 0x0 2749#define DPM_TABLE_409__SamuLevel_7_MinVoltage_VddGfx_MASK 0xff00 2750#define DPM_TABLE_409__SamuLevel_7_MinVoltage_VddGfx__SHIFT 0x8 2751#define DPM_TABLE_409__SamuLevel_7_MinVoltage_Vddci_MASK 0xff0000 2752#define DPM_TABLE_409__SamuLevel_7_MinVoltage_Vddci__SHIFT 0x10 2753#define DPM_TABLE_409__SamuLevel_7_MinVoltage_Vddc_MASK 0xff000000 2754#define DPM_TABLE_409__SamuLevel_7_MinVoltage_Vddc__SHIFT 0x18 2755#define DPM_TABLE_410__SamuLevel_7_padding_2_MASK 0xff 2756#define DPM_TABLE_410__SamuLevel_7_padding_2__SHIFT 0x0 2757#define DPM_TABLE_410__SamuLevel_7_padding_1_MASK 0xff00 2758#define DPM_TABLE_410__SamuLevel_7_padding_1__SHIFT 0x8 2759#define DPM_TABLE_410__SamuLevel_7_padding_0_MASK 0xff0000 2760#define DPM_TABLE_410__SamuLevel_7_padding_0__SHIFT 0x10 2761#define DPM_TABLE_410__SamuLevel_7_Divider_MASK 0xff000000 2762#define DPM_TABLE_410__SamuLevel_7_Divider__SHIFT 0x18 2763#define DPM_TABLE_411__Ulv_CcPwrDynRm_MASK 0xffffffff 2764#define DPM_TABLE_411__Ulv_CcPwrDynRm__SHIFT 0x0 2765#define DPM_TABLE_412__Ulv_CcPwrDynRm1_MASK 0xffffffff 2766#define DPM_TABLE_412__Ulv_CcPwrDynRm1__SHIFT 0x0 2767#define DPM_TABLE_413__Ulv_VddcPhase_MASK 0xff 2768#define DPM_TABLE_413__Ulv_VddcPhase__SHIFT 0x0 2769#define DPM_TABLE_413__Ulv_VddcOffsetVid_MASK 0xff00 2770#define DPM_TABLE_413__Ulv_VddcOffsetVid__SHIFT 0x8 2771#define DPM_TABLE_413__Ulv_VddcOffset_MASK 0xffff0000 2772#define DPM_TABLE_413__Ulv_VddcOffset__SHIFT 0x10 2773#define DPM_TABLE_414__Ulv_Reserved_MASK 0xffffffff 2774#define DPM_TABLE_414__Ulv_Reserved__SHIFT 0x0 2775#define DPM_TABLE_415__SclkStepSize_MASK 0xffffffff 2776#define DPM_TABLE_415__SclkStepSize__SHIFT 0x0 2777#define DPM_TABLE_416__Smio_0_MASK 0xffffffff 2778#define DPM_TABLE_416__Smio_0__SHIFT 0x0 2779#define DPM_TABLE_417__Smio_1_MASK 0xffffffff 2780#define DPM_TABLE_417__Smio_1__SHIFT 0x0 2781#define DPM_TABLE_418__Smio_2_MASK 0xffffffff 2782#define DPM_TABLE_418__Smio_2__SHIFT 0x0 2783#define DPM_TABLE_419__Smio_3_MASK 0xffffffff 2784#define DPM_TABLE_419__Smio_3__SHIFT 0x0 2785#define DPM_TABLE_420__Smio_4_MASK 0xffffffff 2786#define DPM_TABLE_420__Smio_4__SHIFT 0x0 2787#define DPM_TABLE_421__Smio_5_MASK 0xffffffff 2788#define DPM_TABLE_421__Smio_5__SHIFT 0x0 2789#define DPM_TABLE_422__Smio_6_MASK 0xffffffff 2790#define DPM_TABLE_422__Smio_6__SHIFT 0x0 2791#define DPM_TABLE_423__Smio_7_MASK 0xffffffff 2792#define DPM_TABLE_423__Smio_7__SHIFT 0x0 2793#define DPM_TABLE_424__Smio_8_MASK 0xffffffff 2794#define DPM_TABLE_424__Smio_8__SHIFT 0x0 2795#define DPM_TABLE_425__Smio_9_MASK 0xffffffff 2796#define DPM_TABLE_425__Smio_9__SHIFT 0x0 2797#define DPM_TABLE_426__Smio_10_MASK 0xffffffff 2798#define DPM_TABLE_426__Smio_10__SHIFT 0x0 2799#define DPM_TABLE_427__Smio_11_MASK 0xffffffff 2800#define DPM_TABLE_427__Smio_11__SHIFT 0x0 2801#define DPM_TABLE_428__Smio_12_MASK 0xffffffff 2802#define DPM_TABLE_428__Smio_12__SHIFT 0x0 2803#define DPM_TABLE_429__Smio_13_MASK 0xffffffff 2804#define DPM_TABLE_429__Smio_13__SHIFT 0x0 2805#define DPM_TABLE_430__Smio_14_MASK 0xffffffff 2806#define DPM_TABLE_430__Smio_14__SHIFT 0x0 2807#define DPM_TABLE_431__Smio_15_MASK 0xffffffff 2808#define DPM_TABLE_431__Smio_15__SHIFT 0x0 2809#define DPM_TABLE_432__Smio_16_MASK 0xffffffff 2810#define DPM_TABLE_432__Smio_16__SHIFT 0x0 2811#define DPM_TABLE_433__Smio_17_MASK 0xffffffff 2812#define DPM_TABLE_433__Smio_17__SHIFT 0x0 2813#define DPM_TABLE_434__Smio_18_MASK 0xffffffff 2814#define DPM_TABLE_434__Smio_18__SHIFT 0x0 2815#define DPM_TABLE_435__Smio_19_MASK 0xffffffff 2816#define DPM_TABLE_435__Smio_19__SHIFT 0x0 2817#define DPM_TABLE_436__Smio_20_MASK 0xffffffff 2818#define DPM_TABLE_436__Smio_20__SHIFT 0x0 2819#define DPM_TABLE_437__Smio_21_MASK 0xffffffff 2820#define DPM_TABLE_437__Smio_21__SHIFT 0x0 2821#define DPM_TABLE_438__Smio_22_MASK 0xffffffff 2822#define DPM_TABLE_438__Smio_22__SHIFT 0x0 2823#define DPM_TABLE_439__Smio_23_MASK 0xffffffff 2824#define DPM_TABLE_439__Smio_23__SHIFT 0x0 2825#define DPM_TABLE_440__Smio_24_MASK 0xffffffff 2826#define DPM_TABLE_440__Smio_24__SHIFT 0x0 2827#define DPM_TABLE_441__Smio_25_MASK 0xffffffff 2828#define DPM_TABLE_441__Smio_25__SHIFT 0x0 2829#define DPM_TABLE_442__Smio_26_MASK 0xffffffff 2830#define DPM_TABLE_442__Smio_26__SHIFT 0x0 2831#define DPM_TABLE_443__Smio_27_MASK 0xffffffff 2832#define DPM_TABLE_443__Smio_27__SHIFT 0x0 2833#define DPM_TABLE_444__Smio_28_MASK 0xffffffff 2834#define DPM_TABLE_444__Smio_28__SHIFT 0x0 2835#define DPM_TABLE_445__Smio_29_MASK 0xffffffff 2836#define DPM_TABLE_445__Smio_29__SHIFT 0x0 2837#define DPM_TABLE_446__Smio_30_MASK 0xffffffff 2838#define DPM_TABLE_446__Smio_30__SHIFT 0x0 2839#define DPM_TABLE_447__Smio_31_MASK 0xffffffff 2840#define DPM_TABLE_447__Smio_31__SHIFT 0x0 2841#define DPM_TABLE_448__SamuBootLevel_MASK 0xff 2842#define DPM_TABLE_448__SamuBootLevel__SHIFT 0x0 2843#define DPM_TABLE_448__AcpBootLevel_MASK 0xff00 2844#define DPM_TABLE_448__AcpBootLevel__SHIFT 0x8 2845#define DPM_TABLE_448__VceBootLevel_MASK 0xff0000 2846#define DPM_TABLE_448__VceBootLevel__SHIFT 0x10 2847#define DPM_TABLE_448__UvdBootLevel_MASK 0xff000000 2848#define DPM_TABLE_448__UvdBootLevel__SHIFT 0x18 2849#define DPM_TABLE_449__GraphicsInterval_MASK 0xff 2850#define DPM_TABLE_449__GraphicsInterval__SHIFT 0x0 2851#define DPM_TABLE_449__GraphicsThermThrottleEnable_MASK 0xff00 2852#define DPM_TABLE_449__GraphicsThermThrottleEnable__SHIFT 0x8 2853#define DPM_TABLE_449__GraphicsVoltageChangeEnable_MASK 0xff0000 2854#define DPM_TABLE_449__GraphicsVoltageChangeEnable__SHIFT 0x10 2855#define DPM_TABLE_449__GraphicsBootLevel_MASK 0xff000000 2856#define DPM_TABLE_449__GraphicsBootLevel__SHIFT 0x18 2857#define DPM_TABLE_450__TemperatureLimitHigh_MASK 0xffff 2858#define DPM_TABLE_450__TemperatureLimitHigh__SHIFT 0x0 2859#define DPM_TABLE_450__ThermalInterval_MASK 0xff0000 2860#define DPM_TABLE_450__ThermalInterval__SHIFT 0x10 2861#define DPM_TABLE_450__VoltageInterval_MASK 0xff000000 2862#define DPM_TABLE_450__VoltageInterval__SHIFT 0x18 2863#define DPM_TABLE_451__MemoryVoltageChangeEnable_MASK 0xff 2864#define DPM_TABLE_451__MemoryVoltageChangeEnable__SHIFT 0x0 2865#define DPM_TABLE_451__MemoryBootLevel_MASK 0xff00 2866#define DPM_TABLE_451__MemoryBootLevel__SHIFT 0x8 2867#define DPM_TABLE_451__TemperatureLimitLow_MASK 0xffff0000 2868#define DPM_TABLE_451__TemperatureLimitLow__SHIFT 0x10 2869#define DPM_TABLE_452__MemoryThermThrottleEnable_MASK 0xff 2870#define DPM_TABLE_452__MemoryThermThrottleEnable__SHIFT 0x0 2871#define DPM_TABLE_452__MemoryInterval_MASK 0xff00 2872#define DPM_TABLE_452__MemoryInterval__SHIFT 0x8 2873#define DPM_TABLE_452__BootMVdd_MASK 0xffff0000 2874#define DPM_TABLE_452__BootMVdd__SHIFT 0x10 2875#define DPM_TABLE_453__PhaseResponseTime_MASK 0xffff 2876#define DPM_TABLE_453__PhaseResponseTime__SHIFT 0x0 2877#define DPM_TABLE_453__VoltageResponseTime_MASK 0xffff0000 2878#define DPM_TABLE_453__VoltageResponseTime__SHIFT 0x10 2879#define DPM_TABLE_454__DTEMode_MASK 0xff 2880#define DPM_TABLE_454__DTEMode__SHIFT 0x0 2881#define DPM_TABLE_454__DTEInterval_MASK 0xff00 2882#define DPM_TABLE_454__DTEInterval__SHIFT 0x8 2883#define DPM_TABLE_454__PCIeGenInterval_MASK 0xff0000 2884#define DPM_TABLE_454__PCIeGenInterval__SHIFT 0x10 2885#define DPM_TABLE_454__PCIeBootLinkLevel_MASK 0xff000000 2886#define DPM_TABLE_454__PCIeBootLinkLevel__SHIFT 0x18 2887#define DPM_TABLE_455__ThermGpio_MASK 0xff 2888#define DPM_TABLE_455__ThermGpio__SHIFT 0x0 2889#define DPM_TABLE_455__AcDcGpio_MASK 0xff00 2890#define DPM_TABLE_455__AcDcGpio__SHIFT 0x8 2891#define DPM_TABLE_455__VRHotGpio_MASK 0xff0000 2892#define DPM_TABLE_455__VRHotGpio__SHIFT 0x10 2893#define DPM_TABLE_455__SVI2Enable_MASK 0xff000000 2894#define DPM_TABLE_455__SVI2Enable__SHIFT 0x18 2895#define DPM_TABLE_456__PPM_TemperatureLimit_MASK 0xffff 2896#define DPM_TABLE_456__PPM_TemperatureLimit__SHIFT 0x0 2897#define DPM_TABLE_456__PPM_PkgPwrLimit_MASK 0xffff0000 2898#define DPM_TABLE_456__PPM_PkgPwrLimit__SHIFT 0x10 2899#define DPM_TABLE_457__TargetTdp_MASK 0xffff 2900#define DPM_TABLE_457__TargetTdp__SHIFT 0x0 2901#define DPM_TABLE_457__DefaultTdp_MASK 0xffff0000 2902#define DPM_TABLE_457__DefaultTdp__SHIFT 0x10 2903#define DPM_TABLE_458__FpsLowThreshold_MASK 0xffff 2904#define DPM_TABLE_458__FpsLowThreshold__SHIFT 0x0 2905#define DPM_TABLE_458__FpsHighThreshold_MASK 0xffff0000 2906#define DPM_TABLE_458__FpsHighThreshold__SHIFT 0x10 2907#define DPM_TABLE_459__BAPMTI_R_0_1_0_MASK 0xffff 2908#define DPM_TABLE_459__BAPMTI_R_0_1_0__SHIFT 0x0 2909#define DPM_TABLE_459__BAPMTI_R_0_0_0_MASK 0xffff0000 2910#define DPM_TABLE_459__BAPMTI_R_0_0_0__SHIFT 0x10 2911#define DPM_TABLE_460__BAPMTI_R_1_0_0_MASK 0xffff 2912#define DPM_TABLE_460__BAPMTI_R_1_0_0__SHIFT 0x0 2913#define DPM_TABLE_460__BAPMTI_R_0_2_0_MASK 0xffff0000 2914#define DPM_TABLE_460__BAPMTI_R_0_2_0__SHIFT 0x10 2915#define DPM_TABLE_461__BAPMTI_R_1_2_0_MASK 0xffff 2916#define DPM_TABLE_461__BAPMTI_R_1_2_0__SHIFT 0x0 2917#define DPM_TABLE_461__BAPMTI_R_1_1_0_MASK 0xffff0000 2918#define DPM_TABLE_461__BAPMTI_R_1_1_0__SHIFT 0x10 2919#define DPM_TABLE_462__BAPMTI_R_2_1_0_MASK 0xffff 2920#define DPM_TABLE_462__BAPMTI_R_2_1_0__SHIFT 0x0 2921#define DPM_TABLE_462__BAPMTI_R_2_0_0_MASK 0xffff0000 2922#define DPM_TABLE_462__BAPMTI_R_2_0_0__SHIFT 0x10 2923#define DPM_TABLE_463__BAPMTI_R_3_0_0_MASK 0xffff 2924#define DPM_TABLE_463__BAPMTI_R_3_0_0__SHIFT 0x0 2925#define DPM_TABLE_463__BAPMTI_R_2_2_0_MASK 0xffff0000 2926#define DPM_TABLE_463__BAPMTI_R_2_2_0__SHIFT 0x10 2927#define DPM_TABLE_464__BAPMTI_R_3_2_0_MASK 0xffff 2928#define DPM_TABLE_464__BAPMTI_R_3_2_0__SHIFT 0x0 2929#define DPM_TABLE_464__BAPMTI_R_3_1_0_MASK 0xffff0000 2930#define DPM_TABLE_464__BAPMTI_R_3_1_0__SHIFT 0x10 2931#define DPM_TABLE_465__BAPMTI_R_4_1_0_MASK 0xffff 2932#define DPM_TABLE_465__BAPMTI_R_4_1_0__SHIFT 0x0 2933#define DPM_TABLE_465__BAPMTI_R_4_0_0_MASK 0xffff0000 2934#define DPM_TABLE_465__BAPMTI_R_4_0_0__SHIFT 0x10 2935#define DPM_TABLE_466__BAPMTI_RC_0_0_0_MASK 0xffff 2936#define DPM_TABLE_466__BAPMTI_RC_0_0_0__SHIFT 0x0 2937#define DPM_TABLE_466__BAPMTI_R_4_2_0_MASK 0xffff0000 2938#define DPM_TABLE_466__BAPMTI_R_4_2_0__SHIFT 0x10 2939#define DPM_TABLE_467__BAPMTI_RC_0_2_0_MASK 0xffff 2940#define DPM_TABLE_467__BAPMTI_RC_0_2_0__SHIFT 0x0 2941#define DPM_TABLE_467__BAPMTI_RC_0_1_0_MASK 0xffff0000 2942#define DPM_TABLE_467__BAPMTI_RC_0_1_0__SHIFT 0x10 2943#define DPM_TABLE_468__BAPMTI_RC_1_1_0_MASK 0xffff 2944#define DPM_TABLE_468__BAPMTI_RC_1_1_0__SHIFT 0x0 2945#define DPM_TABLE_468__BAPMTI_RC_1_0_0_MASK 0xffff0000 2946#define DPM_TABLE_468__BAPMTI_RC_1_0_0__SHIFT 0x10 2947#define DPM_TABLE_469__BAPMTI_RC_2_0_0_MASK 0xffff 2948#define DPM_TABLE_469__BAPMTI_RC_2_0_0__SHIFT 0x0 2949#define DPM_TABLE_469__BAPMTI_RC_1_2_0_MASK 0xffff0000 2950#define DPM_TABLE_469__BAPMTI_RC_1_2_0__SHIFT 0x10 2951#define DPM_TABLE_470__BAPMTI_RC_2_2_0_MASK 0xffff 2952#define DPM_TABLE_470__BAPMTI_RC_2_2_0__SHIFT 0x0 2953#define DPM_TABLE_470__BAPMTI_RC_2_1_0_MASK 0xffff0000 2954#define DPM_TABLE_470__BAPMTI_RC_2_1_0__SHIFT 0x10 2955#define DPM_TABLE_471__BAPMTI_RC_3_1_0_MASK 0xffff 2956#define DPM_TABLE_471__BAPMTI_RC_3_1_0__SHIFT 0x0 2957#define DPM_TABLE_471__BAPMTI_RC_3_0_0_MASK 0xffff0000 2958#define DPM_TABLE_471__BAPMTI_RC_3_0_0__SHIFT 0x10 2959#define DPM_TABLE_472__BAPMTI_RC_4_0_0_MASK 0xffff 2960#define DPM_TABLE_472__BAPMTI_RC_4_0_0__SHIFT 0x0 2961#define DPM_TABLE_472__BAPMTI_RC_3_2_0_MASK 0xffff0000 2962#define DPM_TABLE_472__BAPMTI_RC_3_2_0__SHIFT 0x10 2963#define DPM_TABLE_473__BAPMTI_RC_4_2_0_MASK 0xffff 2964#define DPM_TABLE_473__BAPMTI_RC_4_2_0__SHIFT 0x0 2965#define DPM_TABLE_473__BAPMTI_RC_4_1_0_MASK 0xffff0000 2966#define DPM_TABLE_473__BAPMTI_RC_4_1_0__SHIFT 0x10 2967#define DPM_TABLE_474__GpuTjHyst_MASK 0xff 2968#define DPM_TABLE_474__GpuTjHyst__SHIFT 0x0 2969#define DPM_TABLE_474__GpuTjMax_MASK 0xff00 2970#define DPM_TABLE_474__GpuTjMax__SHIFT 0x8 2971#define DPM_TABLE_474__DTETjOffset_MASK 0xff0000 2972#define DPM_TABLE_474__DTETjOffset__SHIFT 0x10 2973#define DPM_TABLE_474__DTEAmbientTempBase_MASK 0xff000000 2974#define DPM_TABLE_474__DTEAmbientTempBase__SHIFT 0x18 2975#define DPM_TABLE_475__BootVoltage_Phases_MASK 0xff 2976#define DPM_TABLE_475__BootVoltage_Phases__SHIFT 0x0 2977#define DPM_TABLE_475__BootVoltage_VddGfx_MASK 0xff00 2978#define DPM_TABLE_475__BootVoltage_VddGfx__SHIFT 0x8 2979#define DPM_TABLE_475__BootVoltage_Vddci_MASK 0xff0000 2980#define DPM_TABLE_475__BootVoltage_Vddci__SHIFT 0x10 2981#define DPM_TABLE_475__BootVoltage_Vddc_MASK 0xff000000 2982#define DPM_TABLE_475__BootVoltage_Vddc__SHIFT 0x18 2983#define DPM_TABLE_476__BAPM_TEMP_GRADIENT_MASK 0xffffffff 2984#define DPM_TABLE_476__BAPM_TEMP_GRADIENT__SHIFT 0x0 2985#define DPM_TABLE_477__LowSclkInterruptThreshold_MASK 0xffffffff 2986#define DPM_TABLE_477__LowSclkInterruptThreshold__SHIFT 0x0 2987#define DPM_TABLE_478__VddGfxReChkWait_MASK 0xffffffff 2988#define DPM_TABLE_478__VddGfxReChkWait__SHIFT 0x0 2989#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_1_MASK 0xff 2990#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_1__SHIFT 0x0 2991#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_0_MASK 0xff00 2992#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_0__SHIFT 0x8 2993#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_maxVID_MASK 0xff0000 2994#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_maxVID__SHIFT 0x10 2995#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_minVID_MASK 0xff000000 2996#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_minVID__SHIFT 0x18 2997#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_3_MASK 0xff 2998#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_3__SHIFT 0x0 2999#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_2_MASK 0xff00 3000#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_2__SHIFT 0x8
3001#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_1_MASK 0xff0000 3002#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_1__SHIFT 0x10 3003#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_0_MASK 0xff000000 3004#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_0__SHIFT 0x18 3005#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_7_MASK 0xff 3006#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_7__SHIFT 0x0 3007#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_6_MASK 0xff00 3008#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_6__SHIFT 0x8 3009#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_5_MASK 0xff0000 3010#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_5__SHIFT 0x10 3011#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_4_MASK 0xff000000 3012#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_4__SHIFT 0x18 3013#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_1_MASK 0xff 3014#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_1__SHIFT 0x0 3015#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_0_MASK 0xff00 3016#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_0__SHIFT 0x8 3017#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_maxVID_MASK 0xff0000 3018#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_maxVID__SHIFT 0x10 3019#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_minVID_MASK 0xff000000 3020#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_minVID__SHIFT 0x18 3021#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_3_MASK 0xff 3022#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_3__SHIFT 0x0 3023#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_2_MASK 0xff00 3024#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_2__SHIFT 0x8 3025#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_1_MASK 0xff0000 3026#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_1__SHIFT 0x10 3027#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_0_MASK 0xff000000 3028#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_0__SHIFT 0x18 3029#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_7_MASK 0xff 3030#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_7__SHIFT 0x0 3031#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_6_MASK 0xff00 3032#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_6__SHIFT 0x8 3033#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_5_MASK 0xff0000 3034#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_5__SHIFT 0x10 3035#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_4_MASK 0xff000000 3036#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_4__SHIFT 0x18 3037#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_1_MASK 0xff 3038#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_1__SHIFT 0x0 3039#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_0_MASK 0xff00 3040#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_0__SHIFT 0x8 3041#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_maxVID_MASK 0xff0000 3042#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_maxVID__SHIFT 0x10 3043#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_minVID_MASK 0xff000000 3044#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_minVID__SHIFT 0x18 3045#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_3_MASK 0xff 3046#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_3__SHIFT 0x0 3047#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_2_MASK 0xff00 3048#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_2__SHIFT 0x8 3049#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_1_MASK 0xff0000 3050#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_1__SHIFT 0x10 3051#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_0_MASK 0xff000000 3052#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_0__SHIFT 0x18 3053#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_7_MASK 0xff 3054#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_7__SHIFT 0x0 3055#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_6_MASK 0xff00 3056#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_6__SHIFT 0x8 3057#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_5_MASK 0xff0000 3058#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_5__SHIFT 0x10 3059#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_4_MASK 0xff000000 3060#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_4__SHIFT 0x18 3061#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_1_MASK 0xff 3062#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_1__SHIFT 0x0 3063#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_0_MASK 0xff00 3064#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_0__SHIFT 0x8 3065#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_maxVID_MASK 0xff0000 3066#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_maxVID__SHIFT 0x10 3067#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_minVID_MASK 0xff000000 3068#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_minVID__SHIFT 0x18 3069#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_3_MASK 0xff 3070#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_3__SHIFT 0x0 3071#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_2_MASK 0xff00 3072#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_2__SHIFT 0x8 3073#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_1_MASK 0xff0000 3074#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_1__SHIFT 0x10 3075#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_0_MASK 0xff000000 3076#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_0__SHIFT 0x18 3077#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_7_MASK 0xff 3078#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_7__SHIFT 0x0 3079#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_6_MASK 0xff00 3080#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_6__SHIFT 0x8 3081#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_5_MASK 0xff0000 3082#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_5__SHIFT 0x10 3083#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_4_MASK 0xff000000 3084#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_4__SHIFT 0x18 3085#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming_MASK 0xffffffff 3086#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming__SHIFT 0x0 3087#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2_MASK 0xffffffff 3088#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2__SHIFT 0x0 3089#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2_MASK 0xff 3090#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2__SHIFT 0x0 3091#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1_MASK 0xff00 3092#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1__SHIFT 0x8 3093#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0_MASK 0xff0000 3094#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0__SHIFT 0x10 3095#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime_MASK 0xff000000 3096#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime__SHIFT 0x18 3097#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming_MASK 0xffffffff 3098#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming__SHIFT 0x0 3099#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2_MASK 0xffffffff 3100#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2__SHIFT 0x0 3101#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2_MASK 0xff 3102#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2__SHIFT 0x0 3103#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1_MASK 0xff00 3104#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1__SHIFT 0x8 3105#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0_MASK 0xff0000 3106#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0__SHIFT 0x10 3107#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime_MASK 0xff000000 3108#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime__SHIFT 0x18 3109#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming_MASK 0xffffffff 3110#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming__SHIFT 0x0 3111#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2_MASK 0xffffffff 3112#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2__SHIFT 0x0 3113#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2_MASK 0xff 3114#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2__SHIFT 0x0 3115#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1_MASK 0xff00 3116#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1__SHIFT 0x8 3117#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0_MASK 0xff0000 3118#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0__SHIFT 0x10 3119#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime_MASK 0xff000000 3120#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime__SHIFT 0x18 3121#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming_MASK 0xffffffff 3122#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming__SHIFT 0x0 3123#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2_MASK 0xffffffff 3124#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2__SHIFT 0x0 3125#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2_MASK 0xff 3126#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2__SHIFT 0x0 3127#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1_MASK 0xff00 3128#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1__SHIFT 0x8 3129#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0_MASK 0xff0000 3130#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0__SHIFT 0x10 3131#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime_MASK 0xff000000 3132#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime__SHIFT 0x18 3133#define MCARB_DRAM_TIMING_TABLE_13__entries_1_0_McArbDramTiming_MASK 0xffffffff 3134#define MCARB_DRAM_TIMING_TABLE_13__entries_1_0_McArbDramTiming__SHIFT 0x0 3135#define MCARB_DRAM_TIMING_TABLE_14__entries_1_0_McArbDramTiming2_MASK 0xffffffff 3136#define MCARB_DRAM_TIMING_TABLE_14__entries_1_0_McArbDramTiming2__SHIFT 0x0 3137#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_2_MASK 0xff 3138#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_2__SHIFT 0x0 3139#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_1_MASK 0xff00 3140#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_1__SHIFT 0x8 3141#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_0_MASK 0xff0000 3142#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_0__SHIFT 0x10 3143#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_McArbBurstTime_MASK 0xff000000 3144#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_McArbBurstTime__SHIFT 0x18 3145#define MCARB_DRAM_TIMING_TABLE_16__entries_1_1_McArbDramTiming_MASK 0xffffffff 3146#define MCARB_DRAM_TIMING_TABLE_16__entries_1_1_McArbDramTiming__SHIFT 0x0 3147#define MCARB_DRAM_TIMING_TABLE_17__entries_1_1_McArbDramTiming2_MASK 0xffffffff 3148#define MCARB_DRAM_TIMING_TABLE_17__entries_1_1_McArbDramTiming2__SHIFT 0x0 3149#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_2_MASK 0xff 3150#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_2__SHIFT 0x0 3151#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_1_MASK 0xff00 3152#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_1__SHIFT 0x8 3153#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_0_MASK 0xff0000 3154#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_0__SHIFT 0x10 3155#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_McArbBurstTime_MASK 0xff000000 3156#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_McArbBurstTime__SHIFT 0x18 3157#define MCARB_DRAM_TIMING_TABLE_19__entries_1_2_McArbDramTiming_MASK 0xffffffff 3158#define MCARB_DRAM_TIMING_TABLE_19__entries_1_2_McArbDramTiming__SHIFT 0x0 3159#define MCARB_DRAM_TIMING_TABLE_20__entries_1_2_McArbDramTiming2_MASK 0xffffffff 3160#define MCARB_DRAM_TIMING_TABLE_20__entries_1_2_McArbDramTiming2__SHIFT 0x0 3161#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_2_MASK 0xff 3162#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_2__SHIFT 0x0 3163#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_1_MASK 0xff00 3164#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_1__SHIFT 0x8 3165#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_0_MASK 0xff0000 3166#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_0__SHIFT 0x10 3167#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_McArbBurstTime_MASK 0xff000000 3168#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_McArbBurstTime__SHIFT 0x18 3169#define MCARB_DRAM_TIMING_TABLE_22__entries_1_3_McArbDramTiming_MASK 0xffffffff 3170#define MCARB_DRAM_TIMING_TABLE_22__entries_1_3_McArbDramTiming__SHIFT 0x0 3171#define MCARB_DRAM_TIMING_TABLE_23__entries_1_3_McArbDramTiming2_MASK 0xffffffff 3172#define MCARB_DRAM_TIMING_TABLE_23__entries_1_3_McArbDramTiming2__SHIFT 0x0 3173#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_2_MASK 0xff 3174#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_2__SHIFT 0x0 3175#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_1_MASK 0xff00 3176#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_1__SHIFT 0x8 3177#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_0_MASK 0xff0000 3178#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_0__SHIFT 0x10 3179#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_McArbBurstTime_MASK 0xff000000 3180#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_McArbBurstTime__SHIFT 0x18 3181#define MCARB_DRAM_TIMING_TABLE_25__entries_2_0_McArbDramTiming_MASK 0xffffffff 3182#define MCARB_DRAM_TIMING_TABLE_25__entries_2_0_McArbDramTiming__SHIFT 0x0 3183#define MCARB_DRAM_TIMING_TABLE_26__entries_2_0_McArbDramTiming2_MASK 0xffffffff 3184#define MCARB_DRAM_TIMING_TABLE_26__entries_2_0_McArbDramTiming2__SHIFT 0x0 3185#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_2_MASK 0xff 3186#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_2__SHIFT 0x0 3187#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_1_MASK 0xff00 3188#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_1__SHIFT 0x8 3189#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_0_MASK 0xff0000 3190#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_0__SHIFT 0x10 3191#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_McArbBurstTime_MASK 0xff000000 3192#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_McArbBurstTime__SHIFT 0x18 3193#define MCARB_DRAM_TIMING_TABLE_28__entries_2_1_McArbDramTiming_MASK 0xffffffff 3194#define MCARB_DRAM_TIMING_TABLE_28__entries_2_1_McArbDramTiming__SHIFT 0x0 3195#define MCARB_DRAM_TIMING_TABLE_29__entries_2_1_McArbDramTiming2_MASK 0xffffffff 3196#define MCARB_DRAM_TIMING_TABLE_29__entries_2_1_McArbDramTiming2__SHIFT 0x0 3197#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_2_MASK 0xff 3198#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_2__SHIFT 0x0 3199#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_1_MASK 0xff00 3200#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_1__SHIFT 0x8 3201#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_0_MASK 0xff0000 3202#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_0__SHIFT 0x10 3203#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_McArbBurstTime_MASK 0xff000000 3204#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_McArbBurstTime__SHIFT 0x18 3205#define MCARB_DRAM_TIMING_TABLE_31__entries_2_2_McArbDramTiming_MASK 0xffffffff 3206#define MCARB_DRAM_TIMING_TABLE_31__entries_2_2_McArbDramTiming__SHIFT 0x0 3207#define MCARB_DRAM_TIMING_TABLE_32__entries_2_2_McArbDramTiming2_MASK 0xffffffff 3208#define MCARB_DRAM_TIMING_TABLE_32__entries_2_2_McArbDramTiming2__SHIFT 0x0 3209#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_2_MASK 0xff 3210#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_2__SHIFT 0x0 3211#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_1_MASK 0xff00 3212#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_1__SHIFT 0x8 3213#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_0_MASK 0xff0000 3214#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_0__SHIFT 0x10 3215#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_McArbBurstTime_MASK 0xff000000 3216#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_McArbBurstTime__SHIFT 0x18 3217#define MCARB_DRAM_TIMING_TABLE_34__entries_2_3_McArbDramTiming_MASK 0xffffffff 3218#define MCARB_DRAM_TIMING_TABLE_34__entries_2_3_McArbDramTiming__SHIFT 0x0 3219#define MCARB_DRAM_TIMING_TABLE_35__entries_2_3_McArbDramTiming2_MASK 0xffffffff 3220#define MCARB_DRAM_TIMING_TABLE_35__entries_2_3_McArbDramTiming2__SHIFT 0x0 3221#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_2_MASK 0xff 3222#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_2__SHIFT 0x0 3223#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_1_MASK 0xff00 3224#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_1__SHIFT 0x8 3225#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_0_MASK 0xff0000 3226#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_0__SHIFT 0x10 3227#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_McArbBurstTime_MASK 0xff000000 3228#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_McArbBurstTime__SHIFT 0x18 3229#define MCARB_DRAM_TIMING_TABLE_37__entries_3_0_McArbDramTiming_MASK 0xffffffff 3230#define MCARB_DRAM_TIMING_TABLE_37__entries_3_0_McArbDramTiming__SHIFT 0x0 3231#define MCARB_DRAM_TIMING_TABLE_38__entries_3_0_McArbDramTiming2_MASK 0xffffffff 3232#define MCARB_DRAM_TIMING_TABLE_38__entries_3_0_McArbDramTiming2__SHIFT 0x0 3233#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_2_MASK 0xff 3234#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_2__SHIFT 0x0 3235#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_1_MASK 0xff00 3236#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_1__SHIFT 0x8 3237#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_0_MASK 0xff0000 3238#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_0__SHIFT 0x10 3239#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_McArbBurstTime_MASK 0xff000000 3240#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_McArbBurstTime__SHIFT 0x18 3241#define MCARB_DRAM_TIMING_TABLE_40__entries_3_1_McArbDramTiming_MASK 0xffffffff 3242#define MCARB_DRAM_TIMING_TABLE_40__entries_3_1_McArbDramTiming__SHIFT 0x0 3243#define MCARB_DRAM_TIMING_TABLE_41__entries_3_1_McArbDramTiming2_MASK 0xffffffff 3244#define MCARB_DRAM_TIMING_TABLE_41__entries_3_1_McArbDramTiming2__SHIFT 0x0 3245#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_2_MASK 0xff 3246#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_2__SHIFT 0x0 3247#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_1_MASK 0xff00 3248#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_1__SHIFT 0x8 3249#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_0_MASK 0xff0000 3250#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_0__SHIFT 0x10 3251#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_McArbBurstTime_MASK 0xff000000 3252#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_McArbBurstTime__SHIFT 0x18 3253#define MCARB_DRAM_TIMING_TABLE_43__entries_3_2_McArbDramTiming_MASK 0xffffffff 3254#define MCARB_DRAM_TIMING_TABLE_43__entries_3_2_McArbDramTiming__SHIFT 0x0 3255#define MCARB_DRAM_TIMING_TABLE_44__entries_3_2_McArbDramTiming2_MASK 0xffffffff 3256#define MCARB_DRAM_TIMING_TABLE_44__entries_3_2_McArbDramTiming2__SHIFT 0x0 3257#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_2_MASK 0xff 3258#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_2__SHIFT 0x0 3259#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_1_MASK 0xff00 3260#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_1__SHIFT 0x8 3261#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_0_MASK 0xff0000 3262#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_0__SHIFT 0x10 3263#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_McArbBurstTime_MASK 0xff000000 3264#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_McArbBurstTime__SHIFT 0x18 3265#define MCARB_DRAM_TIMING_TABLE_46__entries_3_3_McArbDramTiming_MASK 0xffffffff 3266#define MCARB_DRAM_TIMING_TABLE_46__entries_3_3_McArbDramTiming__SHIFT 0x0 3267#define MCARB_DRAM_TIMING_TABLE_47__entries_3_3_McArbDramTiming2_MASK 0xffffffff 3268#define MCARB_DRAM_TIMING_TABLE_47__entries_3_3_McArbDramTiming2__SHIFT 0x0 3269#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_2_MASK 0xff 3270#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_2__SHIFT 0x0 3271#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_1_MASK 0xff00 3272#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_1__SHIFT 0x8 3273#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_0_MASK 0xff0000 3274#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_0__SHIFT 0x10 3275#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_McArbBurstTime_MASK 0xff000000 3276#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_McArbBurstTime__SHIFT 0x18 3277#define MCARB_DRAM_TIMING_TABLE_49__entries_4_0_McArbDramTiming_MASK 0xffffffff 3278#define MCARB_DRAM_TIMING_TABLE_49__entries_4_0_McArbDramTiming__SHIFT 0x0 3279#define MCARB_DRAM_TIMING_TABLE_50__entries_4_0_McArbDramTiming2_MASK 0xffffffff 3280#define MCARB_DRAM_TIMING_TABLE_50__entries_4_0_McArbDramTiming2__SHIFT 0x0 3281#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_2_MASK 0xff 3282#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_2__SHIFT 0x0 3283#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_1_MASK 0xff00 3284#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_1__SHIFT 0x8 3285#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_0_MASK 0xff0000 3286#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_0__SHIFT 0x10 3287#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_McArbBurstTime_MASK 0xff000000 3288#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_McArbBurstTime__SHIFT 0x18 3289#define MCARB_DRAM_TIMING_TABLE_52__entries_4_1_McArbDramTiming_MASK 0xffffffff 3290#define MCARB_DRAM_TIMING_TABLE_52__entries_4_1_McArbDramTiming__SHIFT 0x0 3291#define MCARB_DRAM_TIMING_TABLE_53__entries_4_1_McArbDramTiming2_MASK 0xffffffff 3292#define MCARB_DRAM_TIMING_TABLE_53__entries_4_1_McArbDramTiming2__SHIFT 0x0 3293#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_2_MASK 0xff 3294#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_2__SHIFT 0x0 3295#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_1_MASK 0xff00 3296#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_1__SHIFT 0x8 3297#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_0_MASK 0xff0000 3298#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_0__SHIFT 0x10 3299#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_McArbBurstTime_MASK 0xff000000 3300#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_McArbBurstTime__SHIFT 0x18 3301#define MCARB_DRAM_TIMING_TABLE_55__entries_4_2_McArbDramTiming_MASK 0xffffffff 3302#define MCARB_DRAM_TIMING_TABLE_55__entries_4_2_McArbDramTiming__SHIFT 0x0 3303#define MCARB_DRAM_TIMING_TABLE_56__entries_4_2_McArbDramTiming2_MASK 0xffffffff 3304#define MCARB_DRAM_TIMING_TABLE_56__entries_4_2_McArbDramTiming2__SHIFT 0x0 3305#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_2_MASK 0xff 3306#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_2__SHIFT 0x0 3307#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_1_MASK 0xff00 3308#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_1__SHIFT 0x8 3309#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_0_MASK 0xff0000 3310#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_0__SHIFT 0x10 3311#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_McArbBurstTime_MASK 0xff000000 3312#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_McArbBurstTime__SHIFT 0x18 3313#define MCARB_DRAM_TIMING_TABLE_58__entries_4_3_McArbDramTiming_MASK 0xffffffff 3314#define MCARB_DRAM_TIMING_TABLE_58__entries_4_3_McArbDramTiming__SHIFT 0x0 3315#define MCARB_DRAM_TIMING_TABLE_59__entries_4_3_McArbDramTiming2_MASK 0xffffffff 3316#define MCARB_DRAM_TIMING_TABLE_59__entries_4_3_McArbDramTiming2__SHIFT 0x0 3317#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_2_MASK 0xff 3318#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_2__SHIFT 0x0 3319#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_1_MASK 0xff00 3320#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_1__SHIFT 0x8 3321#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_0_MASK 0xff0000 3322#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_0__SHIFT 0x10 3323#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_McArbBurstTime_MASK 0xff000000 3324#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_McArbBurstTime__SHIFT 0x18 3325#define MCARB_DRAM_TIMING_TABLE_61__entries_5_0_McArbDramTiming_MASK 0xffffffff 3326#define MCARB_DRAM_TIMING_TABLE_61__entries_5_0_McArbDramTiming__SHIFT 0x0 3327#define MCARB_DRAM_TIMING_TABLE_62__entries_5_0_McArbDramTiming2_MASK 0xffffffff 3328#define MCARB_DRAM_TIMING_TABLE_62__entries_5_0_McArbDramTiming2__SHIFT 0x0 3329#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_2_MASK 0xff 3330#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_2__SHIFT 0x0 3331#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_1_MASK 0xff00 3332#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_1__SHIFT 0x8 3333#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_0_MASK 0xff0000 3334#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_0__SHIFT 0x10 3335#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_McArbBurstTime_MASK 0xff000000 3336#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_McArbBurstTime__SHIFT 0x18 3337#define MCARB_DRAM_TIMING_TABLE_64__entries_5_1_McArbDramTiming_MASK 0xffffffff 3338#define MCARB_DRAM_TIMING_TABLE_64__entries_5_1_McArbDramTiming__SHIFT 0x0 3339#define MCARB_DRAM_TIMING_TABLE_65__entries_5_1_McArbDramTiming2_MASK 0xffffffff 3340#define MCARB_DRAM_TIMING_TABLE_65__entries_5_1_McArbDramTiming2__SHIFT 0x0 3341#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_2_MASK 0xff 3342#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_2__SHIFT 0x0 3343#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_1_MASK 0xff00 3344#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_1__SHIFT 0x8 3345#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_0_MASK 0xff0000 3346#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_0__SHIFT 0x10 3347#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_McArbBurstTime_MASK 0xff000000 3348#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_McArbBurstTime__SHIFT 0x18 3349#define MCARB_DRAM_TIMING_TABLE_67__entries_5_2_McArbDramTiming_MASK 0xffffffff 3350#define MCARB_DRAM_TIMING_TABLE_67__entries_5_2_McArbDramTiming__SHIFT 0x0 3351#define MCARB_DRAM_TIMING_TABLE_68__entries_5_2_McArbDramTiming2_MASK 0xffffffff 3352#define MCARB_DRAM_TIMING_TABLE_68__entries_5_2_McArbDramTiming2__SHIFT 0x0 3353#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_2_MASK 0xff 3354#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_2__SHIFT 0x0 3355#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_1_MASK 0xff00 3356#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_1__SHIFT 0x8 3357#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_0_MASK 0xff0000 3358#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_0__SHIFT 0x10 3359#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_McArbBurstTime_MASK 0xff000000 3360#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_McArbBurstTime__SHIFT 0x18 3361#define MCARB_DRAM_TIMING_TABLE_70__entries_5_3_McArbDramTiming_MASK 0xffffffff 3362#define MCARB_DRAM_TIMING_TABLE_70__entries_5_3_McArbDramTiming__SHIFT 0x0 3363#define MCARB_DRAM_TIMING_TABLE_71__entries_5_3_McArbDramTiming2_MASK 0xffffffff 3364#define MCARB_DRAM_TIMING_TABLE_71__entries_5_3_McArbDramTiming2__SHIFT 0x0 3365#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_2_MASK 0xff 3366#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_2__SHIFT 0x0 3367#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_1_MASK 0xff00 3368#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_1__SHIFT 0x8 3369#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_0_MASK 0xff0000 3370#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_0__SHIFT 0x10 3371#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_McArbBurstTime_MASK 0xff000000 3372#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_McArbBurstTime__SHIFT 0x18 3373#define MCARB_DRAM_TIMING_TABLE_73__entries_6_0_McArbDramTiming_MASK 0xffffffff 3374#define MCARB_DRAM_TIMING_TABLE_73__entries_6_0_McArbDramTiming__SHIFT 0x0 3375#define MCARB_DRAM_TIMING_TABLE_74__entries_6_0_McArbDramTiming2_MASK 0xffffffff 3376#define MCARB_DRAM_TIMING_TABLE_74__entries_6_0_McArbDramTiming2__SHIFT 0x0 3377#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_2_MASK 0xff 3378#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_2__SHIFT 0x0 3379#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_1_MASK 0xff00 3380#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_1__SHIFT 0x8 3381#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_0_MASK 0xff0000 3382#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_0__SHIFT 0x10 3383#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_McArbBurstTime_MASK 0xff000000 3384#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_McArbBurstTime__SHIFT 0x18 3385#define MCARB_DRAM_TIMING_TABLE_76__entries_6_1_McArbDramTiming_MASK 0xffffffff 3386#define MCARB_DRAM_TIMING_TABLE_76__entries_6_1_McArbDramTiming__SHIFT 0x0 3387#define MCARB_DRAM_TIMING_TABLE_77__entries_6_1_McArbDramTiming2_MASK 0xffffffff 3388#define MCARB_DRAM_TIMING_TABLE_77__entries_6_1_McArbDramTiming2__SHIFT 0x0 3389#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_2_MASK 0xff 3390#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_2__SHIFT 0x0 3391#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_1_MASK 0xff00 3392#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_1__SHIFT 0x8 3393#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_0_MASK 0xff0000 3394#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_0__SHIFT 0x10 3395#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_McArbBurstTime_MASK 0xff000000 3396#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_McArbBurstTime__SHIFT 0x18 3397#define MCARB_DRAM_TIMING_TABLE_79__entries_6_2_McArbDramTiming_MASK 0xffffffff 3398#define MCARB_DRAM_TIMING_TABLE_79__entries_6_2_McArbDramTiming__SHIFT 0x0 3399#define MCARB_DRAM_TIMING_TABLE_80__entries_6_2_McArbDramTiming2_MASK 0xffffffff 3400#define MCARB_DRAM_TIMING_TABLE_80__entries_6_2_McArbDramTiming2__SHIFT 0x0 3401#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_2_MASK 0xff 3402#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_2__SHIFT 0x0 3403#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_1_MASK 0xff00 3404#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_1__SHIFT 0x8 3405#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_0_MASK 0xff0000 3406#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_0__SHIFT 0x10 3407#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_McArbBurstTime_MASK 0xff000000 3408#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_McArbBurstTime__SHIFT 0x18 3409#define MCARB_DRAM_TIMING_TABLE_82__entries_6_3_McArbDramTiming_MASK 0xffffffff 3410#define MCARB_DRAM_TIMING_TABLE_82__entries_6_3_McArbDramTiming__SHIFT 0x0 3411#define MCARB_DRAM_TIMING_TABLE_83__entries_6_3_McArbDramTiming2_MASK 0xffffffff 3412#define MCARB_DRAM_TIMING_TABLE_83__entries_6_3_McArbDramTiming2__SHIFT 0x0 3413#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_2_MASK 0xff 3414#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_2__SHIFT 0x0 3415#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_1_MASK 0xff00 3416#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_1__SHIFT 0x8 3417#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_0_MASK 0xff0000 3418#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_0__SHIFT 0x10 3419#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_McArbBurstTime_MASK 0xff000000 3420#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_McArbBurstTime__SHIFT 0x18 3421#define MCARB_DRAM_TIMING_TABLE_85__entries_7_0_McArbDramTiming_MASK 0xffffffff 3422#define MCARB_DRAM_TIMING_TABLE_85__entries_7_0_McArbDramTiming__SHIFT 0x0 3423#define MCARB_DRAM_TIMING_TABLE_86__entries_7_0_McArbDramTiming2_MASK 0xffffffff 3424#define MCARB_DRAM_TIMING_TABLE_86__entries_7_0_McArbDramTiming2__SHIFT 0x0 3425#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_2_MASK 0xff 3426#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_2__SHIFT 0x0 3427#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_1_MASK 0xff00 3428#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_1__SHIFT 0x8 3429#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_0_MASK 0xff0000 3430#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_0__SHIFT 0x10 3431#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_McArbBurstTime_MASK 0xff000000 3432#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_McArbBurstTime__SHIFT 0x18 3433#define MCARB_DRAM_TIMING_TABLE_88__entries_7_1_McArbDramTiming_MASK 0xffffffff 3434#define MCARB_DRAM_TIMING_TABLE_88__entries_7_1_McArbDramTiming__SHIFT 0x0 3435#define MCARB_DRAM_TIMING_TABLE_89__entries_7_1_McArbDramTiming2_MASK 0xffffffff 3436#define MCARB_DRAM_TIMING_TABLE_89__entries_7_1_McArbDramTiming2__SHIFT 0x0 3437#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_2_MASK 0xff 3438#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_2__SHIFT 0x0 3439#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_1_MASK 0xff00 3440#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_1__SHIFT 0x8 3441#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_0_MASK 0xff0000 3442#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_0__SHIFT 0x10 3443#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_McArbBurstTime_MASK 0xff000000 3444#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_McArbBurstTime__SHIFT 0x18 3445#define MCARB_DRAM_TIMING_TABLE_91__entries_7_2_McArbDramTiming_MASK 0xffffffff 3446#define MCARB_DRAM_TIMING_TABLE_91__entries_7_2_McArbDramTiming__SHIFT 0x0 3447#define MCARB_DRAM_TIMING_TABLE_92__entries_7_2_McArbDramTiming2_MASK 0xffffffff 3448#define MCARB_DRAM_TIMING_TABLE_92__entries_7_2_McArbDramTiming2__SHIFT 0x0 3449#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_2_MASK 0xff 3450#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_2__SHIFT 0x0 3451#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_1_MASK 0xff00 3452#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_1__SHIFT 0x8 3453#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_0_MASK 0xff0000 3454#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_0__SHIFT 0x10 3455#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_McArbBurstTime_MASK 0xff000000 3456#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_McArbBurstTime__SHIFT 0x18 3457#define MCARB_DRAM_TIMING_TABLE_94__entries_7_3_McArbDramTiming_MASK 0xffffffff 3458#define MCARB_DRAM_TIMING_TABLE_94__entries_7_3_McArbDramTiming__SHIFT 0x0 3459#define MCARB_DRAM_TIMING_TABLE_95__entries_7_3_McArbDramTiming2_MASK 0xffffffff 3460#define MCARB_DRAM_TIMING_TABLE_95__entries_7_3_McArbDramTiming2__SHIFT 0x0 3461#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_2_MASK 0xff 3462#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_2__SHIFT 0x0 3463#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_1_MASK 0xff00 3464#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_1__SHIFT 0x8 3465#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_0_MASK 0xff0000 3466#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_0__SHIFT 0x10 3467#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_McArbBurstTime_MASK 0xff000000 3468#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_McArbBurstTime__SHIFT 0x18 3469#define MC_REGISTERS_TABLE_1__reserved_2_MASK 0xff 3470#define MC_REGISTERS_TABLE_1__reserved_2__SHIFT 0x0 3471#define MC_REGISTERS_TABLE_1__reserved_1_MASK 0xff00 3472#define MC_REGISTERS_TABLE_1__reserved_1__SHIFT 0x8 3473#define MC_REGISTERS_TABLE_1__reserved_0_MASK 0xff0000 3474#define MC_REGISTERS_TABLE_1__reserved_0__SHIFT 0x10 3475#define MC_REGISTERS_TABLE_1__last_MASK 0xff000000 3476#define MC_REGISTERS_TABLE_1__last__SHIFT 0x18 3477#define MC_REGISTERS_TABLE_2__address_0_s1_MASK 0xffff 3478#define MC_REGISTERS_TABLE_2__address_0_s1__SHIFT 0x0 3479#define MC_REGISTERS_TABLE_2__address_0_s0_MASK 0xffff0000 3480#define MC_REGISTERS_TABLE_2__address_0_s0__SHIFT 0x10 3481#define MC_REGISTERS_TABLE_3__address_1_s1_MASK 0xffff 3482#define MC_REGISTERS_TABLE_3__address_1_s1__SHIFT 0x0 3483#define MC_REGISTERS_TABLE_3__address_1_s0_MASK 0xffff0000 3484#define MC_REGISTERS_TABLE_3__address_1_s0__SHIFT 0x10 3485#define MC_REGISTERS_TABLE_4__address_2_s1_MASK 0xffff 3486#define MC_REGISTERS_TABLE_4__address_2_s1__SHIFT 0x0 3487#define MC_REGISTERS_TABLE_4__address_2_s0_MASK 0xffff0000 3488#define MC_REGISTERS_TABLE_4__address_2_s0__SHIFT 0x10 3489#define MC_REGISTERS_TABLE_5__address_3_s1_MASK 0xffff 3490#define MC_REGISTERS_TABLE_5__address_3_s1__SHIFT 0x0 3491#define MC_REGISTERS_TABLE_5__address_3_s0_MASK 0xffff0000 3492#define MC_REGISTERS_TABLE_5__address_3_s0__SHIFT 0x10 3493#define MC_REGISTERS_TABLE_6__address_4_s1_MASK 0xffff 3494#define MC_REGISTERS_TABLE_6__address_4_s1__SHIFT 0x0 3495#define MC_REGISTERS_TABLE_6__address_4_s0_MASK 0xffff0000 3496#define MC_REGISTERS_TABLE_6__address_4_s0__SHIFT 0x10 3497#define MC_REGISTERS_TABLE_7__address_5_s1_MASK 0xffff 3498#define MC_REGISTERS_TABLE_7__address_5_s1__SHIFT 0x0 3499#define MC_REGISTERS_TABLE_7__address_5_s0_MASK 0xffff0000 3500#define MC_REGISTERS_TABLE_7__address_5_s0__SHIFT 0x10 3501#define MC_REGISTERS_TABLE_8__address_6_s1_MASK 0xffff 3502#define MC_REGISTERS_TABLE_8__address_6_s1__SHIFT 0x0 3503#define MC_REGISTERS_TABLE_8__address_6_s0_MASK 0xffff0000 3504#define MC_REGISTERS_TABLE_8__address_6_s0__SHIFT 0x10 3505#define MC_REGISTERS_TABLE_9__address_7_s1_MASK 0xffff 3506#define MC_REGISTERS_TABLE_9__address_7_s1__SHIFT 0x0 3507#define MC_REGISTERS_TABLE_9__address_7_s0_MASK 0xffff0000 3508#define MC_REGISTERS_TABLE_9__address_7_s0__SHIFT 0x10 3509#define MC_REGISTERS_TABLE_10__address_8_s1_MASK 0xffff 3510#define MC_REGISTERS_TABLE_10__address_8_s1__SHIFT 0x0 3511#define MC_REGISTERS_TABLE_10__address_8_s0_MASK 0xffff0000 3512#define MC_REGISTERS_TABLE_10__address_8_s0__SHIFT 0x10 3513#define MC_REGISTERS_TABLE_11__address_9_s1_MASK 0xffff 3514#define MC_REGISTERS_TABLE_11__address_9_s1__SHIFT 0x0 3515#define MC_REGISTERS_TABLE_11__address_9_s0_MASK 0xffff0000 3516#define MC_REGISTERS_TABLE_11__address_9_s0__SHIFT 0x10 3517#define MC_REGISTERS_TABLE_12__address_10_s1_MASK 0xffff 3518#define MC_REGISTERS_TABLE_12__address_10_s1__SHIFT 0x0 3519#define MC_REGISTERS_TABLE_12__address_10_s0_MASK 0xffff0000 3520#define MC_REGISTERS_TABLE_12__address_10_s0__SHIFT 0x10 3521#define MC_REGISTERS_TABLE_13__address_11_s1_MASK 0xffff 3522#define MC_REGISTERS_TABLE_13__address_11_s1__SHIFT 0x0 3523#define MC_REGISTERS_TABLE_13__address_11_s0_MASK 0xffff0000 3524#define MC_REGISTERS_TABLE_13__address_11_s0__SHIFT 0x10 3525#define MC_REGISTERS_TABLE_14__address_12_s1_MASK 0xffff 3526#define MC_REGISTERS_TABLE_14__address_12_s1__SHIFT 0x0 3527#define MC_REGISTERS_TABLE_14__address_12_s0_MASK 0xffff0000 3528#define MC_REGISTERS_TABLE_14__address_12_s0__SHIFT 0x10 3529#define MC_REGISTERS_TABLE_15__address_13_s1_MASK 0xffff 3530#define MC_REGISTERS_TABLE_15__address_13_s1__SHIFT 0x0 3531#define MC_REGISTERS_TABLE_15__address_13_s0_MASK 0xffff0000 3532#define MC_REGISTERS_TABLE_15__address_13_s0__SHIFT 0x10 3533#define MC_REGISTERS_TABLE_16__address_14_s1_MASK 0xffff 3534#define MC_REGISTERS_TABLE_16__address_14_s1__SHIFT 0x0 3535#define MC_REGISTERS_TABLE_16__address_14_s0_MASK 0xffff0000 3536#define MC_REGISTERS_TABLE_16__address_14_s0__SHIFT 0x10 3537#define MC_REGISTERS_TABLE_17__address_15_s1_MASK 0xffff 3538#define MC_REGISTERS_TABLE_17__address_15_s1__SHIFT 0x0 3539#define MC_REGISTERS_TABLE_17__address_15_s0_MASK 0xffff0000 3540#define MC_REGISTERS_TABLE_17__address_15_s0__SHIFT 0x10 3541#define MC_REGISTERS_TABLE_18__data_0_value_0_MASK 0xffffffff 3542#define MC_REGISTERS_TABLE_18__data_0_value_0__SHIFT 0x0 3543#define MC_REGISTERS_TABLE_19__data_0_value_1_MASK 0xffffffff 3544#define MC_REGISTERS_TABLE_19__data_0_value_1__SHIFT 0x0 3545#define MC_REGISTERS_TABLE_20__data_0_value_2_MASK 0xffffffff 3546#define MC_REGISTERS_TABLE_20__data_0_value_2__SHIFT 0x0 3547#define MC_REGISTERS_TABLE_21__data_0_value_3_MASK 0xffffffff 3548#define MC_REGISTERS_TABLE_21__data_0_value_3__SHIFT 0x0 3549#define MC_REGISTERS_TABLE_22__data_0_value_4_MASK 0xffffffff 3550#define MC_REGISTERS_TABLE_22__data_0_value_4__SHIFT 0x0 3551#define MC_REGISTERS_TABLE_23__data_0_value_5_MASK 0xffffffff 3552#define MC_REGISTERS_TABLE_23__data_0_value_5__SHIFT 0x0 3553#define MC_REGISTERS_TABLE_24__data_0_value_6_MASK 0xffffffff 3554#define MC_REGISTERS_TABLE_24__data_0_value_6__SHIFT 0x0 3555#define MC_REGISTERS_TABLE_25__data_0_value_7_MASK 0xffffffff 3556#define MC_REGISTERS_TABLE_25__data_0_value_7__SHIFT 0x0 3557#define MC_REGISTERS_TABLE_26__data_0_value_8_MASK 0xffffffff 3558#define MC_REGISTERS_TABLE_26__data_0_value_8__SHIFT 0x0 3559#define MC_REGISTERS_TABLE_27__data_0_value_9_MASK 0xffffffff 3560#define MC_REGISTERS_TABLE_27__data_0_value_9__SHIFT 0x0 3561#define MC_REGISTERS_TABLE_28__data_0_value_10_MASK 0xffffffff 3562#define MC_REGISTERS_TABLE_28__data_0_value_10__SHIFT 0x0 3563#define MC_REGISTERS_TABLE_29__data_0_value_11_MASK 0xffffffff 3564#define MC_REGISTERS_TABLE_29__data_0_value_11__SHIFT 0x0 3565#define MC_REGISTERS_TABLE_30__data_0_value_12_MASK 0xffffffff 3566#define MC_REGISTERS_TABLE_30__data_0_value_12__SHIFT 0x0 3567#define MC_REGISTERS_TABLE_31__data_0_value_13_MASK 0xffffffff 3568#define MC_REGISTERS_TABLE_31__data_0_value_13__SHIFT 0x0 3569#define MC_REGISTERS_TABLE_32__data_0_value_14_MASK 0xffffffff 3570#define MC_REGISTERS_TABLE_32__data_0_value_14__SHIFT 0x0 3571#define MC_REGISTERS_TABLE_33__data_0_value_15_MASK 0xffffffff 3572#define MC_REGISTERS_TABLE_33__data_0_value_15__SHIFT 0x0 3573#define MC_REGISTERS_TABLE_34__data_1_value_0_MASK 0xffffffff 3574#define MC_REGISTERS_TABLE_34__data_1_value_0__SHIFT 0x0 3575#define MC_REGISTERS_TABLE_35__data_1_value_1_MASK 0xffffffff 3576#define MC_REGISTERS_TABLE_35__data_1_value_1__SHIFT 0x0 3577#define MC_REGISTERS_TABLE_36__data_1_value_2_MASK 0xffffffff 3578#define MC_REGISTERS_TABLE_36__data_1_value_2__SHIFT 0x0 3579#define MC_REGISTERS_TABLE_37__data_1_value_3_MASK 0xffffffff 3580#define MC_REGISTERS_TABLE_37__data_1_value_3__SHIFT 0x0 3581#define MC_REGISTERS_TABLE_38__data_1_value_4_MASK 0xffffffff 3582#define MC_REGISTERS_TABLE_38__data_1_value_4__SHIFT 0x0 3583#define MC_REGISTERS_TABLE_39__data_1_value_5_MASK 0xffffffff 3584#define MC_REGISTERS_TABLE_39__data_1_value_5__SHIFT 0x0 3585#define MC_REGISTERS_TABLE_40__data_1_value_6_MASK 0xffffffff 3586#define MC_REGISTERS_TABLE_40__data_1_value_6__SHIFT 0x0 3587#define MC_REGISTERS_TABLE_41__data_1_value_7_MASK 0xffffffff 3588#define MC_REGISTERS_TABLE_41__data_1_value_7__SHIFT 0x0 3589#define MC_REGISTERS_TABLE_42__data_1_value_8_MASK 0xffffffff 3590#define MC_REGISTERS_TABLE_42__data_1_value_8__SHIFT 0x0 3591#define MC_REGISTERS_TABLE_43__data_1_value_9_MASK 0xffffffff 3592#define MC_REGISTERS_TABLE_43__data_1_value_9__SHIFT 0x0 3593#define MC_REGISTERS_TABLE_44__data_1_value_10_MASK 0xffffffff 3594#define MC_REGISTERS_TABLE_44__data_1_value_10__SHIFT 0x0 3595#define MC_REGISTERS_TABLE_45__data_1_value_11_MASK 0xffffffff 3596#define MC_REGISTERS_TABLE_45__data_1_value_11__SHIFT 0x0 3597#define MC_REGISTERS_TABLE_46__data_1_value_12_MASK 0xffffffff 3598#define MC_REGISTERS_TABLE_46__data_1_value_12__SHIFT 0x0 3599#define MC_REGISTERS_TABLE_47__data_1_value_13_MASK 0xffffffff 3600#define MC_REGISTERS_TABLE_47__data_1_value_13__SHIFT 0x0 3601#define MC_REGISTERS_TABLE_48__data_1_value_14_MASK 0xffffffff 3602#define MC_REGISTERS_TABLE_48__data_1_value_14__SHIFT 0x0 3603#define MC_REGISTERS_TABLE_49__data_1_value_15_MASK 0xffffffff 3604#define MC_REGISTERS_TABLE_49__data_1_value_15__SHIFT 0x0 3605#define MC_REGISTERS_TABLE_50__data_2_value_0_MASK 0xffffffff 3606#define MC_REGISTERS_TABLE_50__data_2_value_0__SHIFT 0x0 3607#define MC_REGISTERS_TABLE_51__data_2_value_1_MASK 0xffffffff 3608#define MC_REGISTERS_TABLE_51__data_2_value_1__SHIFT 0x0 3609#define MC_REGISTERS_TABLE_52__data_2_value_2_MASK 0xffffffff 3610#define MC_REGISTERS_TABLE_52__data_2_value_2__SHIFT 0x0 3611#define MC_REGISTERS_TABLE_53__data_2_value_3_MASK 0xffffffff 3612#define MC_REGISTERS_TABLE_53__data_2_value_3__SHIFT 0x0 3613#define MC_REGISTERS_TABLE_54__data_2_value_4_MASK 0xffffffff 3614#define MC_REGISTERS_TABLE_54__data_2_value_4__SHIFT 0x0 3615#define MC_REGISTERS_TABLE_55__data_2_value_5_MASK 0xffffffff 3616#define MC_REGISTERS_TABLE_55__data_2_value_5__SHIFT 0x0 3617#define MC_REGISTERS_TABLE_56__data_2_value_6_MASK 0xffffffff 3618#define MC_REGISTERS_TABLE_56__data_2_value_6__SHIFT 0x0 3619#define MC_REGISTERS_TABLE_57__data_2_value_7_MASK 0xffffffff 3620#define MC_REGISTERS_TABLE_57__data_2_value_7__SHIFT 0x0 3621#define MC_REGISTERS_TABLE_58__data_2_value_8_MASK 0xffffffff 3622#define MC_REGISTERS_TABLE_58__data_2_value_8__SHIFT 0x0 3623#define MC_REGISTERS_TABLE_59__data_2_value_9_MASK 0xffffffff 3624#define MC_REGISTERS_TABLE_59__data_2_value_9__SHIFT 0x0 3625#define MC_REGISTERS_TABLE_60__data_2_value_10_MASK 0xffffffff 3626#define MC_REGISTERS_TABLE_60__data_2_value_10__SHIFT 0x0 3627#define MC_REGISTERS_TABLE_61__data_2_value_11_MASK 0xffffffff 3628#define MC_REGISTERS_TABLE_61__data_2_value_11__SHIFT 0x0 3629#define MC_REGISTERS_TABLE_62__data_2_value_12_MASK 0xffffffff 3630#define MC_REGISTERS_TABLE_62__data_2_value_12__SHIFT 0x0 3631#define MC_REGISTERS_TABLE_63__data_2_value_13_MASK 0xffffffff 3632#define MC_REGISTERS_TABLE_63__data_2_value_13__SHIFT 0x0 3633#define MC_REGISTERS_TABLE_64__data_2_value_14_MASK 0xffffffff 3634#define MC_REGISTERS_TABLE_64__data_2_value_14__SHIFT 0x0 3635#define MC_REGISTERS_TABLE_65__data_2_value_15_MASK 0xffffffff 3636#define MC_REGISTERS_TABLE_65__data_2_value_15__SHIFT 0x0 3637#define MC_REGISTERS_TABLE_66__data_3_value_0_MASK 0xffffffff 3638#define MC_REGISTERS_TABLE_66__data_3_value_0__SHIFT 0x0 3639#define MC_REGISTERS_TABLE_67__data_3_value_1_MASK 0xffffffff 3640#define MC_REGISTERS_TABLE_67__data_3_value_1__SHIFT 0x0 3641#define MC_REGISTERS_TABLE_68__data_3_value_2_MASK 0xffffffff 3642#define MC_REGISTERS_TABLE_68__data_3_value_2__SHIFT 0x0 3643#define MC_REGISTERS_TABLE_69__data_3_value_3_MASK 0xffffffff 3644#define MC_REGISTERS_TABLE_69__data_3_value_3__SHIFT 0x0 3645#define MC_REGISTERS_TABLE_70__data_3_value_4_MASK 0xffffffff 3646#define MC_REGISTERS_TABLE_70__data_3_value_4__SHIFT 0x0 3647#define MC_REGISTERS_TABLE_71__data_3_value_5_MASK 0xffffffff 3648#define MC_REGISTERS_TABLE_71__data_3_value_5__SHIFT 0x0 3649#define MC_REGISTERS_TABLE_72__data_3_value_6_MASK 0xffffffff 3650#define MC_REGISTERS_TABLE_72__data_3_value_6__SHIFT 0x0 3651#define MC_REGISTERS_TABLE_73__data_3_value_7_MASK 0xffffffff 3652#define MC_REGISTERS_TABLE_73__data_3_value_7__SHIFT 0x0 3653#define MC_REGISTERS_TABLE_74__data_3_value_8_MASK 0xffffffff 3654#define MC_REGISTERS_TABLE_74__data_3_value_8__SHIFT 0x0 3655#define MC_REGISTERS_TABLE_75__data_3_value_9_MASK 0xffffffff 3656#define MC_REGISTERS_TABLE_75__data_3_value_9__SHIFT 0x0 3657#define MC_REGISTERS_TABLE_76__data_3_value_10_MASK 0xffffffff 3658#define MC_REGISTERS_TABLE_76__data_3_value_10__SHIFT 0x0 3659#define MC_REGISTERS_TABLE_77__data_3_value_11_MASK 0xffffffff 3660#define MC_REGISTERS_TABLE_77__data_3_value_11__SHIFT 0x0 3661#define MC_REGISTERS_TABLE_78__data_3_value_12_MASK 0xffffffff 3662#define MC_REGISTERS_TABLE_78__data_3_value_12__SHIFT 0x0 3663#define MC_REGISTERS_TABLE_79__data_3_value_13_MASK 0xffffffff 3664#define MC_REGISTERS_TABLE_79__data_3_value_13__SHIFT 0x0 3665#define MC_REGISTERS_TABLE_80__data_3_value_14_MASK 0xffffffff 3666#define MC_REGISTERS_TABLE_80__data_3_value_14__SHIFT 0x0 3667#define MC_REGISTERS_TABLE_81__data_3_value_15_MASK 0xffffffff 3668#define MC_REGISTERS_TABLE_81__data_3_value_15__SHIFT 0x0 3669#define FAN_TABLE_1__TempMin_MASK 0xffff 3670#define FAN_TABLE_1__TempMin__SHIFT 0x0 3671#define FAN_TABLE_1__FdoMode_MASK 0xffff0000 3672#define FAN_TABLE_1__FdoMode__SHIFT 0x10 3673#define FAN_TABLE_2__TempMax_MASK 0xffff 3674#define FAN_TABLE_2__TempMax__SHIFT 0x0 3675#define FAN_TABLE_2__TempMed_MASK 0xffff0000 3676#define FAN_TABLE_2__TempMed__SHIFT 0x10 3677#define FAN_TABLE_3__Slope2_MASK 0xffff 3678#define FAN_TABLE_3__Slope2__SHIFT 0x0 3679#define FAN_TABLE_3__Slope1_MASK 0xffff0000 3680#define FAN_TABLE_3__Slope1__SHIFT 0x10 3681#define FAN_TABLE_4__HystUp_MASK 0xffff 3682#define FAN_TABLE_4__HystUp__SHIFT 0x0 3683#define FAN_TABLE_4__FdoMin_MASK 0xffff0000 3684#define FAN_TABLE_4__FdoMin__SHIFT 0x10 3685#define FAN_TABLE_5__HystSlope_MASK 0xffff 3686#define FAN_TABLE_5__HystSlope__SHIFT 0x0 3687#define FAN_TABLE_5__HystDown_MASK 0xffff0000 3688#define FAN_TABLE_5__HystDown__SHIFT 0x10 3689#define FAN_TABLE_6__TempCurr_MASK 0xffff 3690#define FAN_TABLE_6__TempCurr__SHIFT 0x0 3691#define FAN_TABLE_6__TempRespLim_MASK 0xffff0000 3692#define FAN_TABLE_6__TempRespLim__SHIFT 0x10 3693#define FAN_TABLE_7__PwmCurr_MASK 0xffff 3694#define FAN_TABLE_7__PwmCurr__SHIFT 0x0 3695#define FAN_TABLE_7__SlopeCurr_MASK 0xffff0000 3696#define FAN_TABLE_7__SlopeCurr__SHIFT 0x10 3697#define FAN_TABLE_8__RefreshPeriod_MASK 0xffffffff 3698#define FAN_TABLE_8__RefreshPeriod__SHIFT 0x0 3699#define FAN_TABLE_9__Padding_MASK 0xff 3700#define FAN_TABLE_9__Padding__SHIFT 0x0 3701#define FAN_TABLE_9__TempSrc_MASK 0xff00 3702#define FAN_TABLE_9__TempSrc__SHIFT 0x8 3703#define FAN_TABLE_9__FdoMax_MASK 0xffff0000 3704#define FAN_TABLE_9__FdoMax__SHIFT 0x10 3705#define SOFT_REGISTERS_TABLE_1__RefClockFrequency_MASK 0xffffffff 3706#define SOFT_REGISTERS_TABLE_1__RefClockFrequency__SHIFT 0x0 3707#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod_MASK 0xffffffff 3708#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod__SHIFT 0x0 3709#define SOFT_REGISTERS_TABLE_3__FeatureEnables_MASK 0xffffffff 3710#define SOFT_REGISTERS_TABLE_3__FeatureEnables__SHIFT 0x0 3711#define SOFT_REGISTERS_TABLE_4__PreVBlankGap_MASK 0xffffffff 3712#define SOFT_REGISTERS_TABLE_4__PreVBlankGap__SHIFT 0x0 3713#define SOFT_REGISTERS_TABLE_5__VBlankTimeout_MASK 0xffffffff 3714#define SOFT_REGISTERS_TABLE_5__VBlankTimeout__SHIFT 0x0 3715#define SOFT_REGISTERS_TABLE_6__TrainTimeGap_MASK 0xffffffff 3716#define SOFT_REGISTERS_TABLE_6__TrainTimeGap__SHIFT 0x0 3717#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime_MASK 0xffffffff 3718#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime__SHIFT 0x0 3719#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime_MASK 0xffffffff 3720#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime__SHIFT 0x0 3721#define SOFT_REGISTERS_TABLE_9__AcpiDelay_MASK 0xffffffff 3722#define SOFT_REGISTERS_TABLE_9__AcpiDelay__SHIFT 0x0 3723#define SOFT_REGISTERS_TABLE_10__G5TrainTime_MASK 0xffffffff 3724#define SOFT_REGISTERS_TABLE_10__G5TrainTime__SHIFT 0x0 3725#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron_MASK 0xffffffff 3726#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron__SHIFT 0x0 3727#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout_MASK 0xffffffff 3728#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout__SHIFT 0x0 3729#define SOFT_REGISTERS_TABLE_13__HandshakeDisables_MASK 0xffffffff 3730#define SOFT_REGISTERS_TABLE_13__HandshakeDisables__SHIFT 0x0 3731#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config_MASK 0xff 3732#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config__SHIFT 0x0 3733#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config_MASK 0xff00 3734#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config__SHIFT 0x8 3735#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config_MASK 0xff0000 3736#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config__SHIFT 0x10 3737#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config_MASK 0xff000000 3738#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config__SHIFT 0x18 3739#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config_MASK 0xff 3740#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config__SHIFT 0x0 3741#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config_MASK 0xff00 3742#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config__SHIFT 0x8 3743#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config_MASK 0xff0000 3744#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config__SHIFT 0x10 3745#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config_MASK 0xff000000 3746#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config__SHIFT 0x18 3747#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity_MASK 0xffffffff 3748#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity__SHIFT 0x0 3749#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity_MASK 0xffffffff 3750#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity__SHIFT 0x0 3751#define SOFT_REGISTERS_TABLE_18__AverageGioActivity_MASK 0xffffffff 3752#define SOFT_REGISTERS_TABLE_18__AverageGioActivity__SHIFT 0x0 3753#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels_MASK 0xff 3754#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels__SHIFT 0x0 3755#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels_MASK 0xff00 3756#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels__SHIFT 0x8 3757#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels_MASK 0xff0000 3758#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels__SHIFT 0x10 3759#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels_MASK 0xff000000 3760#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels__SHIFT 0x18 3761#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels_MASK 0xff 3762#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels__SHIFT 0x0 3763#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels_MASK 0xff00 3764#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels__SHIFT 0x8 3765#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels_MASK 0xff0000 3766#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels__SHIFT 0x10 3767#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels_MASK 0xff000000 3768#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels__SHIFT 0x18 3769#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_H_MASK 0xffffffff 3770#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_H__SHIFT 0x0 3771#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_ADDR_L_MASK 0xffffffff 3772#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_ADDR_L__SHIFT 0x0 3773#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_H_MASK 0xffffffff 3774#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_H__SHIFT 0x0 3775#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_PHY_ADDR_L_MASK 0xffffffff 3776#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_PHY_ADDR_L__SHIFT 0x0 3777#define SOFT_REGISTERS_TABLE_25__DRAM_LOG_BUFF_SIZE_MASK 0xffffffff 3778#define SOFT_REGISTERS_TABLE_25__DRAM_LOG_BUFF_SIZE__SHIFT 0x0 3779#define SOFT_REGISTERS_TABLE_26__UlvEnterCount_MASK 0xffffffff 3780#define SOFT_REGISTERS_TABLE_26__UlvEnterCount__SHIFT 0x0 3781#define SOFT_REGISTERS_TABLE_27__UlvTime_MASK 0xffffffff 3782#define SOFT_REGISTERS_TABLE_27__UlvTime__SHIFT 0x0 3783#define SOFT_REGISTERS_TABLE_28__UcodeLoadStatus_MASK 0xffffffff 3784#define SOFT_REGISTERS_TABLE_28__UcodeLoadStatus__SHIFT 0x0 3785#define SOFT_REGISTERS_TABLE_29__Reserved_0_MASK 0xffffffff 3786#define SOFT_REGISTERS_TABLE_29__Reserved_0__SHIFT 0x0 3787#define SOFT_REGISTERS_TABLE_30__Reserved_1_MASK 0xffffffff 3788#define SOFT_REGISTERS_TABLE_30__Reserved_1__SHIFT 0x0 3789#define PM_FUSES_1__SviLoadLineOffsetVddC_MASK 0xff 3790#define PM_FUSES_1__SviLoadLineOffsetVddC__SHIFT 0x0 3791#define PM_FUSES_1__SviLoadLineTrimVddC_MASK 0xff00 3792#define PM_FUSES_1__SviLoadLineTrimVddC__SHIFT 0x8 3793#define PM_FUSES_1__SviLoadLineVddC_MASK 0xff0000 3794#define PM_FUSES_1__SviLoadLineVddC__SHIFT 0x10 3795#define PM_FUSES_1__SviLoadLineEn_MASK 0xff000000 3796#define PM_FUSES_1__SviLoadLineEn__SHIFT 0x18 3797#define PM_FUSES_2__TDC_MAWt_MASK 0xff 3798#define PM_FUSES_2__TDC_MAWt__SHIFT 0x0 3799#define PM_FUSES_2__TDC_VDDC_ThrottleReleaseLimitPerc_MASK 0xff00 3800#define PM_FUSES_2__TDC_VDDC_ThrottleReleaseLimitPerc__SHIFT 0x8 3801#define PM_FUSES_2__TDC_VDDC_PkgLimit_MASK 0xffff0000 3802#define PM_FUSES_2__TDC_VDDC_PkgLimit__SHIFT 0x10 3803#define PM_FUSES_3__Reserved_MASK 0xff 3804#define PM_FUSES_3__Reserved__SHIFT 0x0 3805#define PM_FUSES_3__LPMLTemperatureMax_MASK 0xff00 3806#define PM_FUSES_3__LPMLTemperatureMax__SHIFT 0x8 3807#define PM_FUSES_3__LPMLTemperatureMin_MASK 0xff0000 3808#define PM_FUSES_3__LPMLTemperatureMin__SHIFT 0x10 3809#define PM_FUSES_3__TdcWaterfallCtl_MASK 0xff000000 3810#define PM_FUSES_3__TdcWaterfallCtl__SHIFT 0x18 3811#define PM_FUSES_4__LPMLTemperatureScaler_3_MASK 0xff 3812#define PM_FUSES_4__LPMLTemperatureScaler_3__SHIFT 0x0 3813#define PM_FUSES_4__LPMLTemperatureScaler_2_MASK 0xff00 3814#define PM_FUSES_4__LPMLTemperatureScaler_2__SHIFT 0x8 3815#define PM_FUSES_4__LPMLTemperatureScaler_1_MASK 0xff0000 3816#define PM_FUSES_4__LPMLTemperatureScaler_1__SHIFT 0x10 3817#define PM_FUSES_4__LPMLTemperatureScaler_0_MASK 0xff000000 3818#define PM_FUSES_4__LPMLTemperatureScaler_0__SHIFT 0x18 3819#define PM_FUSES_5__LPMLTemperatureScaler_7_MASK 0xff 3820#define PM_FUSES_5__LPMLTemperatureScaler_7__SHIFT 0x0 3821#define PM_FUSES_5__LPMLTemperatureScaler_6_MASK 0xff00 3822#define PM_FUSES_5__LPMLTemperatureScaler_6__SHIFT 0x8 3823#define PM_FUSES_5__LPMLTemperatureScaler_5_MASK 0xff0000 3824#define PM_FUSES_5__LPMLTemperatureScaler_5__SHIFT 0x10 3825#define PM_FUSES_5__LPMLTemperatureScaler_4_MASK 0xff000000 3826#define PM_FUSES_5__LPMLTemperatureScaler_4__SHIFT 0x18 3827#define PM_FUSES_6__LPMLTemperatureScaler_11_MASK 0xff 3828#define PM_FUSES_6__LPMLTemperatureScaler_11__SHIFT 0x0 3829#define PM_FUSES_6__LPMLTemperatureScaler_10_MASK 0xff00 3830#define PM_FUSES_6__LPMLTemperatureScaler_10__SHIFT 0x8 3831#define PM_FUSES_6__LPMLTemperatureScaler_9_MASK 0xff0000 3832#define PM_FUSES_6__LPMLTemperatureScaler_9__SHIFT 0x10 3833#define PM_FUSES_6__LPMLTemperatureScaler_8_MASK 0xff000000 3834#define PM_FUSES_6__LPMLTemperatureScaler_8__SHIFT 0x18 3835#define PM_FUSES_7__LPMLTemperatureScaler_15_MASK 0xff 3836#define PM_FUSES_7__LPMLTemperatureScaler_15__SHIFT 0x0 3837#define PM_FUSES_7__LPMLTemperatureScaler_14_MASK 0xff00 3838#define PM_FUSES_7__LPMLTemperatureScaler_14__SHIFT 0x8 3839#define PM_FUSES_7__LPMLTemperatureScaler_13_MASK 0xff0000 3840#define PM_FUSES_7__LPMLTemperatureScaler_13__SHIFT 0x10 3841#define PM_FUSES_7__LPMLTemperatureScaler_12_MASK 0xff000000 3842#define PM_FUSES_7__LPMLTemperatureScaler_12__SHIFT 0x18 3843#define PM_FUSES_8__FuzzyFan_ErrorRateSetDelta_MASK 0xffff 3844#define PM_FUSES_8__FuzzyFan_ErrorRateSetDelta__SHIFT 0x0 3845#define PM_FUSES_8__FuzzyFan_ErrorSetDelta_MASK 0xffff0000 3846#define PM_FUSES_8__FuzzyFan_ErrorSetDelta__SHIFT 0x10 3847#define PM_FUSES_9__Reserved6_MASK 0xffff 3848#define PM_FUSES_9__Reserved6__SHIFT 0x0 3849#define PM_FUSES_9__FuzzyFan_PwmSetDelta_MASK 0xffff0000 3850#define PM_FUSES_9__FuzzyFan_PwmSetDelta__SHIFT 0x10 3851#define PM_FUSES_10__GnbLPML_3_MASK 0xff 3852#define PM_FUSES_10__GnbLPML_3__SHIFT 0x0 3853#define PM_FUSES_10__GnbLPML_2_MASK 0xff00 3854#define PM_FUSES_10__GnbLPML_2__SHIFT 0x8 3855#define PM_FUSES_10__GnbLPML_1_MASK 0xff0000 3856#define PM_FUSES_10__GnbLPML_1__SHIFT 0x10 3857#define PM_FUSES_10__GnbLPML_0_MASK 0xff000000 3858#define PM_FUSES_10__GnbLPML_0__SHIFT 0x18 3859#define PM_FUSES_11__GnbLPML_7_MASK 0xff 3860#define PM_FUSES_11__GnbLPML_7__SHIFT 0x0 3861#define PM_FUSES_11__GnbLPML_6_MASK 0xff00 3862#define PM_FUSES_11__GnbLPML_6__SHIFT 0x8 3863#define PM_FUSES_11__GnbLPML_5_MASK 0xff0000 3864#define PM_FUSES_11__GnbLPML_5__SHIFT 0x10 3865#define PM_FUSES_11__GnbLPML_4_MASK 0xff000000 3866#define PM_FUSES_11__GnbLPML_4__SHIFT 0x18 3867#define PM_FUSES_12__GnbLPML_11_MASK 0xff 3868#define PM_FUSES_12__GnbLPML_11__SHIFT 0x0 3869#define PM_FUSES_12__GnbLPML_10_MASK 0xff00 3870#define PM_FUSES_12__GnbLPML_10__SHIFT 0x8 3871#define PM_FUSES_12__GnbLPML_9_MASK 0xff0000 3872#define PM_FUSES_12__GnbLPML_9__SHIFT 0x10 3873#define PM_FUSES_12__GnbLPML_8_MASK 0xff000000 3874#define PM_FUSES_12__GnbLPML_8__SHIFT 0x18 3875#define PM_FUSES_13__GnbLPML_15_MASK 0xff 3876#define PM_FUSES_13__GnbLPML_15__SHIFT 0x0 3877#define PM_FUSES_13__GnbLPML_14_MASK 0xff00 3878#define PM_FUSES_13__GnbLPML_14__SHIFT 0x8 3879#define PM_FUSES_13__GnbLPML_13_MASK 0xff0000 3880#define PM_FUSES_13__GnbLPML_13__SHIFT 0x10 3881#define PM_FUSES_13__GnbLPML_12_MASK 0xff000000 3882#define PM_FUSES_13__GnbLPML_12__SHIFT 0x18 3883#define PM_FUSES_14__Reserved1_1_MASK 0xff 3884#define PM_FUSES_14__Reserved1_1__SHIFT 0x0 3885#define PM_FUSES_14__Reserved1_0_MASK 0xff00 3886#define PM_FUSES_14__Reserved1_0__SHIFT 0x8 3887#define PM_FUSES_14__GnbLPMLMinVid_MASK 0xff0000 3888#define PM_FUSES_14__GnbLPMLMinVid__SHIFT 0x10 3889#define PM_FUSES_14__GnbLPMLMaxVid_MASK 0xff000000 3890#define PM_FUSES_14__GnbLPMLMaxVid__SHIFT 0x18 3891#define PM_FUSES_15__BapmVddCBaseLeakageLoSidd_MASK 0xffff 3892#define PM_FUSES_15__BapmVddCBaseLeakageLoSidd__SHIFT 0x0 3893#define PM_FUSES_15__BapmVddCBaseLeakageHiSidd_MASK 0xffff0000 3894#define PM_FUSES_15__BapmVddCBaseLeakageHiSidd__SHIFT 0x10 3895#define SMU_PM_STATUS_0__DATA_MASK 0xffffffff 3896#define SMU_PM_STATUS_0__DATA__SHIFT 0x0 3897#define SMU_PM_STATUS_1__DATA_MASK 0xffffffff 3898#define SMU_PM_STATUS_1__DATA__SHIFT 0x0 3899#define SMU_PM_STATUS_2__DATA_MASK 0xffffffff 3900#define SMU_PM_STATUS_2__DATA__SHIFT 0x0 3901#define SMU_PM_STATUS_3__DATA_MASK 0xffffffff 3902#define SMU_PM_STATUS_3__DATA__SHIFT 0x0 3903#define SMU_PM_STATUS_4__DATA_MASK 0xffffffff 3904#define SMU_PM_STATUS_4__DATA__SHIFT 0x0 3905#define SMU_PM_STATUS_5__DATA_MASK 0xffffffff 3906#define SMU_PM_STATUS_5__DATA__SHIFT 0x0 3907#define SMU_PM_STATUS_6__DATA_MASK 0xffffffff 3908#define SMU_PM_STATUS_6__DATA__SHIFT 0x0 3909#define SMU_PM_STATUS_7__DATA_MASK 0xffffffff 3910#define SMU_PM_STATUS_7__DATA__SHIFT 0x0 3911#define SMU_PM_STATUS_8__DATA_MASK 0xffffffff 3912#define SMU_PM_STATUS_8__DATA__SHIFT 0x0 3913#define SMU_PM_STATUS_9__DATA_MASK 0xffffffff 3914#define SMU_PM_STATUS_9__DATA__SHIFT 0x0 3915#define SMU_PM_STATUS_10__DATA_MASK 0xffffffff 3916#define SMU_PM_STATUS_10__DATA__SHIFT 0x0 3917#define SMU_PM_STATUS_11__DATA_MASK 0xffffffff 3918#define SMU_PM_STATUS_11__DATA__SHIFT 0x0 3919#define SMU_PM_STATUS_12__DATA_MASK 0xffffffff 3920#define SMU_PM_STATUS_12__DATA__SHIFT 0x0 3921#define SMU_PM_STATUS_13__DATA_MASK 0xffffffff 3922#define SMU_PM_STATUS_13__DATA__SHIFT 0x0 3923#define SMU_PM_STATUS_14__DATA_MASK 0xffffffff 3924#define SMU_PM_STATUS_14__DATA__SHIFT 0x0 3925#define SMU_PM_STATUS_15__DATA_MASK 0xffffffff 3926#define SMU_PM_STATUS_15__DATA__SHIFT 0x0 3927#define SMU_PM_STATUS_16__DATA_MASK 0xffffffff 3928#define SMU_PM_STATUS_16__DATA__SHIFT 0x0 3929#define SMU_PM_STATUS_17__DATA_MASK 0xffffffff 3930#define SMU_PM_STATUS_17__DATA__SHIFT 0x0 3931#define SMU_PM_STATUS_18__DATA_MASK 0xffffffff 3932#define SMU_PM_STATUS_18__DATA__SHIFT 0x0 3933#define SMU_PM_STATUS_19__DATA_MASK 0xffffffff 3934#define SMU_PM_STATUS_19__DATA__SHIFT 0x0 3935#define SMU_PM_STATUS_20__DATA_MASK 0xffffffff 3936#define SMU_PM_STATUS_20__DATA__SHIFT 0x0 3937#define SMU_PM_STATUS_21__DATA_MASK 0xffffffff 3938#define SMU_PM_STATUS_21__DATA__SHIFT 0x0 3939#define SMU_PM_STATUS_22__DATA_MASK 0xffffffff 3940#define SMU_PM_STATUS_22__DATA__SHIFT 0x0 3941#define SMU_PM_STATUS_23__DATA_MASK 0xffffffff 3942#define SMU_PM_STATUS_23__DATA__SHIFT 0x0 3943#define SMU_PM_STATUS_24__DATA_MASK 0xffffffff 3944#define SMU_PM_STATUS_24__DATA__SHIFT 0x0 3945#define SMU_PM_STATUS_25__DATA_MASK 0xffffffff 3946#define SMU_PM_STATUS_25__DATA__SHIFT 0x0 3947#define SMU_PM_STATUS_26__DATA_MASK 0xffffffff 3948#define SMU_PM_STATUS_26__DATA__SHIFT 0x0 3949#define SMU_PM_STATUS_27__DATA_MASK 0xffffffff 3950#define SMU_PM_STATUS_27__DATA__SHIFT 0x0 3951#define SMU_PM_STATUS_28__DATA_MASK 0xffffffff 3952#define SMU_PM_STATUS_28__DATA__SHIFT 0x0 3953#define SMU_PM_STATUS_29__DATA_MASK 0xffffffff 3954#define SMU_PM_STATUS_29__DATA__SHIFT 0x0 3955#define SMU_PM_STATUS_30__DATA_MASK 0xffffffff 3956#define SMU_PM_STATUS_30__DATA__SHIFT 0x0 3957#define SMU_PM_STATUS_31__DATA_MASK 0xffffffff 3958#define SMU_PM_STATUS_31__DATA__SHIFT 0x0 3959#define SMU_PM_STATUS_32__DATA_MASK 0xffffffff 3960#define SMU_PM_STATUS_32__DATA__SHIFT 0x0 3961#define SMU_PM_STATUS_33__DATA_MASK 0xffffffff 3962#define SMU_PM_STATUS_33__DATA__SHIFT 0x0 3963#define SMU_PM_STATUS_34__DATA_MASK 0xffffffff 3964#define SMU_PM_STATUS_34__DATA__SHIFT 0x0 3965#define SMU_PM_STATUS_35__DATA_MASK 0xffffffff 3966#define SMU_PM_STATUS_35__DATA__SHIFT 0x0 3967#define SMU_PM_STATUS_36__DATA_MASK 0xffffffff 3968#define SMU_PM_STATUS_36__DATA__SHIFT 0x0 3969#define SMU_PM_STATUS_37__DATA_MASK 0xffffffff 3970#define SMU_PM_STATUS_37__DATA__SHIFT 0x0 3971#define SMU_PM_STATUS_38__DATA_MASK 0xffffffff 3972#define SMU_PM_STATUS_38__DATA__SHIFT 0x0 3973#define SMU_PM_STATUS_39__DATA_MASK 0xffffffff 3974#define SMU_PM_STATUS_39__DATA__SHIFT 0x0 3975#define SMU_PM_STATUS_40__DATA_MASK 0xffffffff 3976#define SMU_PM_STATUS_40__DATA__SHIFT 0x0 3977#define SMU_PM_STATUS_41__DATA_MASK 0xffffffff 3978#define SMU_PM_STATUS_41__DATA__SHIFT 0x0 3979#define SMU_PM_STATUS_42__DATA_MASK 0xffffffff 3980#define SMU_PM_STATUS_42__DATA__SHIFT 0x0 3981#define SMU_PM_STATUS_43__DATA_MASK 0xffffffff 3982#define SMU_PM_STATUS_43__DATA__SHIFT 0x0 3983#define SMU_PM_STATUS_44__DATA_MASK 0xffffffff 3984#define SMU_PM_STATUS_44__DATA__SHIFT 0x0 3985#define SMU_PM_STATUS_45__DATA_MASK 0xffffffff 3986#define SMU_PM_STATUS_45__DATA__SHIFT 0x0 3987#define SMU_PM_STATUS_46__DATA_MASK 0xffffffff 3988#define SMU_PM_STATUS_46__DATA__SHIFT 0x0 3989#define SMU_PM_STATUS_47__DATA_MASK 0xffffffff 3990#define SMU_PM_STATUS_47__DATA__SHIFT 0x0 3991#define SMU_PM_STATUS_48__DATA_MASK 0xffffffff 3992#define SMU_PM_STATUS_48__DATA__SHIFT 0x0 3993#define SMU_PM_STATUS_49__DATA_MASK 0xffffffff 3994#define SMU_PM_STATUS_49__DATA__SHIFT 0x0 3995#define SMU_PM_STATUS_50__DATA_MASK 0xffffffff 3996#define SMU_PM_STATUS_50__DATA__SHIFT 0x0 3997#define SMU_PM_STATUS_51__DATA_MASK 0xffffffff 3998#define SMU_PM_STATUS_51__DATA__SHIFT 0x0 3999#define SMU_PM_STATUS_52__DATA_MASK 0xffffffff 4000#define SMU_PM_STATUS_52__DATA__SHIFT 0x0
4001#define SMU_PM_STATUS_53__DATA_MASK 0xffffffff 4002#define SMU_PM_STATUS_53__DATA__SHIFT 0x0 4003#define SMU_PM_STATUS_54__DATA_MASK 0xffffffff 4004#define SMU_PM_STATUS_54__DATA__SHIFT 0x0 4005#define SMU_PM_STATUS_55__DATA_MASK 0xffffffff 4006#define SMU_PM_STATUS_55__DATA__SHIFT 0x0 4007#define SMU_PM_STATUS_56__DATA_MASK 0xffffffff 4008#define SMU_PM_STATUS_56__DATA__SHIFT 0x0 4009#define SMU_PM_STATUS_57__DATA_MASK 0xffffffff 4010#define SMU_PM_STATUS_57__DATA__SHIFT 0x0 4011#define SMU_PM_STATUS_58__DATA_MASK 0xffffffff 4012#define SMU_PM_STATUS_58__DATA__SHIFT 0x0 4013#define SMU_PM_STATUS_59__DATA_MASK 0xffffffff 4014#define SMU_PM_STATUS_59__DATA__SHIFT 0x0 4015#define SMU_PM_STATUS_60__DATA_MASK 0xffffffff 4016#define SMU_PM_STATUS_60__DATA__SHIFT 0x0 4017#define SMU_PM_STATUS_61__DATA_MASK 0xffffffff 4018#define SMU_PM_STATUS_61__DATA__SHIFT 0x0 4019#define SMU_PM_STATUS_62__DATA_MASK 0xffffffff 4020#define SMU_PM_STATUS_62__DATA__SHIFT 0x0 4021#define SMU_PM_STATUS_63__DATA_MASK 0xffffffff 4022#define SMU_PM_STATUS_63__DATA__SHIFT 0x0 4023#define SMU_PM_STATUS_64__DATA_MASK 0xffffffff 4024#define SMU_PM_STATUS_64__DATA__SHIFT 0x0 4025#define SMU_PM_STATUS_65__DATA_MASK 0xffffffff 4026#define SMU_PM_STATUS_65__DATA__SHIFT 0x0 4027#define SMU_PM_STATUS_66__DATA_MASK 0xffffffff 4028#define SMU_PM_STATUS_66__DATA__SHIFT 0x0 4029#define SMU_PM_STATUS_67__DATA_MASK 0xffffffff 4030#define SMU_PM_STATUS_67__DATA__SHIFT 0x0 4031#define SMU_PM_STATUS_68__DATA_MASK 0xffffffff 4032#define SMU_PM_STATUS_68__DATA__SHIFT 0x0 4033#define SMU_PM_STATUS_69__DATA_MASK 0xffffffff 4034#define SMU_PM_STATUS_69__DATA__SHIFT 0x0 4035#define SMU_PM_STATUS_70__DATA_MASK 0xffffffff 4036#define SMU_PM_STATUS_70__DATA__SHIFT 0x0 4037#define SMU_PM_STATUS_71__DATA_MASK 0xffffffff 4038#define SMU_PM_STATUS_71__DATA__SHIFT 0x0 4039#define SMU_PM_STATUS_72__DATA_MASK 0xffffffff 4040#define SMU_PM_STATUS_72__DATA__SHIFT 0x0 4041#define SMU_PM_STATUS_73__DATA_MASK 0xffffffff 4042#define SMU_PM_STATUS_73__DATA__SHIFT 0x0 4043#define SMU_PM_STATUS_74__DATA_MASK 0xffffffff 4044#define SMU_PM_STATUS_74__DATA__SHIFT 0x0 4045#define SMU_PM_STATUS_75__DATA_MASK 0xffffffff 4046#define SMU_PM_STATUS_75__DATA__SHIFT 0x0 4047#define SMU_PM_STATUS_76__DATA_MASK 0xffffffff 4048#define SMU_PM_STATUS_76__DATA__SHIFT 0x0 4049#define SMU_PM_STATUS_77__DATA_MASK 0xffffffff 4050#define SMU_PM_STATUS_77__DATA__SHIFT 0x0 4051#define SMU_PM_STATUS_78__DATA_MASK 0xffffffff 4052#define SMU_PM_STATUS_78__DATA__SHIFT 0x0 4053#define SMU_PM_STATUS_79__DATA_MASK 0xffffffff 4054#define SMU_PM_STATUS_79__DATA__SHIFT 0x0 4055#define SMU_PM_STATUS_80__DATA_MASK 0xffffffff 4056#define SMU_PM_STATUS_80__DATA__SHIFT 0x0 4057#define SMU_PM_STATUS_81__DATA_MASK 0xffffffff 4058#define SMU_PM_STATUS_81__DATA__SHIFT 0x0 4059#define SMU_PM_STATUS_82__DATA_MASK 0xffffffff 4060#define SMU_PM_STATUS_82__DATA__SHIFT 0x0 4061#define SMU_PM_STATUS_83__DATA_MASK 0xffffffff 4062#define SMU_PM_STATUS_83__DATA__SHIFT 0x0 4063#define SMU_PM_STATUS_84__DATA_MASK 0xffffffff 4064#define SMU_PM_STATUS_84__DATA__SHIFT 0x0 4065#define SMU_PM_STATUS_85__DATA_MASK 0xffffffff 4066#define SMU_PM_STATUS_85__DATA__SHIFT 0x0 4067#define SMU_PM_STATUS_86__DATA_MASK 0xffffffff 4068#define SMU_PM_STATUS_86__DATA__SHIFT 0x0 4069#define SMU_PM_STATUS_87__DATA_MASK 0xffffffff 4070#define SMU_PM_STATUS_87__DATA__SHIFT 0x0 4071#define SMU_PM_STATUS_88__DATA_MASK 0xffffffff 4072#define SMU_PM_STATUS_88__DATA__SHIFT 0x0 4073#define SMU_PM_STATUS_89__DATA_MASK 0xffffffff 4074#define SMU_PM_STATUS_89__DATA__SHIFT 0x0 4075#define SMU_PM_STATUS_90__DATA_MASK 0xffffffff 4076#define SMU_PM_STATUS_90__DATA__SHIFT 0x0 4077#define SMU_PM_STATUS_91__DATA_MASK 0xffffffff 4078#define SMU_PM_STATUS_91__DATA__SHIFT 0x0 4079#define SMU_PM_STATUS_92__DATA_MASK 0xffffffff 4080#define SMU_PM_STATUS_92__DATA__SHIFT 0x0 4081#define SMU_PM_STATUS_93__DATA_MASK 0xffffffff 4082#define SMU_PM_STATUS_93__DATA__SHIFT 0x0 4083#define SMU_PM_STATUS_94__DATA_MASK 0xffffffff 4084#define SMU_PM_STATUS_94__DATA__SHIFT 0x0 4085#define SMU_PM_STATUS_95__DATA_MASK 0xffffffff 4086#define SMU_PM_STATUS_95__DATA__SHIFT 0x0 4087#define SMU_PM_STATUS_96__DATA_MASK 0xffffffff 4088#define SMU_PM_STATUS_96__DATA__SHIFT 0x0 4089#define SMU_PM_STATUS_97__DATA_MASK 0xffffffff 4090#define SMU_PM_STATUS_97__DATA__SHIFT 0x0 4091#define SMU_PM_STATUS_98__DATA_MASK 0xffffffff 4092#define SMU_PM_STATUS_98__DATA__SHIFT 0x0 4093#define SMU_PM_STATUS_99__DATA_MASK 0xffffffff 4094#define SMU_PM_STATUS_99__DATA__SHIFT 0x0 4095#define SMU_PM_STATUS_100__DATA_MASK 0xffffffff 4096#define SMU_PM_STATUS_100__DATA__SHIFT 0x0 4097#define SMU_PM_STATUS_101__DATA_MASK 0xffffffff 4098#define SMU_PM_STATUS_101__DATA__SHIFT 0x0 4099#define SMU_PM_STATUS_102__DATA_MASK 0xffffffff 4100#define SMU_PM_STATUS_102__DATA__SHIFT 0x0 4101#define SMU_PM_STATUS_103__DATA_MASK 0xffffffff 4102#define SMU_PM_STATUS_103__DATA__SHIFT 0x0 4103#define SMU_PM_STATUS_104__DATA_MASK 0xffffffff 4104#define SMU_PM_STATUS_104__DATA__SHIFT 0x0 4105#define SMU_PM_STATUS_105__DATA_MASK 0xffffffff 4106#define SMU_PM_STATUS_105__DATA__SHIFT 0x0 4107#define SMU_PM_STATUS_106__DATA_MASK 0xffffffff 4108#define SMU_PM_STATUS_106__DATA__SHIFT 0x0 4109#define SMU_PM_STATUS_107__DATA_MASK 0xffffffff 4110#define SMU_PM_STATUS_107__DATA__SHIFT 0x0 4111#define SMU_PM_STATUS_108__DATA_MASK 0xffffffff 4112#define SMU_PM_STATUS_108__DATA__SHIFT 0x0 4113#define SMU_PM_STATUS_109__DATA_MASK 0xffffffff 4114#define SMU_PM_STATUS_109__DATA__SHIFT 0x0 4115#define SMU_PM_STATUS_110__DATA_MASK 0xffffffff 4116#define SMU_PM_STATUS_110__DATA__SHIFT 0x0 4117#define SMU_PM_STATUS_111__DATA_MASK 0xffffffff 4118#define SMU_PM_STATUS_111__DATA__SHIFT 0x0 4119#define SMU_PM_STATUS_112__DATA_MASK 0xffffffff 4120#define SMU_PM_STATUS_112__DATA__SHIFT 0x0 4121#define SMU_PM_STATUS_113__DATA_MASK 0xffffffff 4122#define SMU_PM_STATUS_113__DATA__SHIFT 0x0 4123#define SMU_PM_STATUS_114__DATA_MASK 0xffffffff 4124#define SMU_PM_STATUS_114__DATA__SHIFT 0x0 4125#define SMU_PM_STATUS_115__DATA_MASK 0xffffffff 4126#define SMU_PM_STATUS_115__DATA__SHIFT 0x0 4127#define SMU_PM_STATUS_116__DATA_MASK 0xffffffff 4128#define SMU_PM_STATUS_116__DATA__SHIFT 0x0 4129#define SMU_PM_STATUS_117__DATA_MASK 0xffffffff 4130#define SMU_PM_STATUS_117__DATA__SHIFT 0x0 4131#define SMU_PM_STATUS_118__DATA_MASK 0xffffffff 4132#define SMU_PM_STATUS_118__DATA__SHIFT 0x0 4133#define SMU_PM_STATUS_119__DATA_MASK 0xffffffff 4134#define SMU_PM_STATUS_119__DATA__SHIFT 0x0 4135#define SMU_PM_STATUS_120__DATA_MASK 0xffffffff 4136#define SMU_PM_STATUS_120__DATA__SHIFT 0x0 4137#define SMU_PM_STATUS_121__DATA_MASK 0xffffffff 4138#define SMU_PM_STATUS_121__DATA__SHIFT 0x0 4139#define SMU_PM_STATUS_122__DATA_MASK 0xffffffff 4140#define SMU_PM_STATUS_122__DATA__SHIFT 0x0 4141#define SMU_PM_STATUS_123__DATA_MASK 0xffffffff 4142#define SMU_PM_STATUS_123__DATA__SHIFT 0x0 4143#define SMU_PM_STATUS_124__DATA_MASK 0xffffffff 4144#define SMU_PM_STATUS_124__DATA__SHIFT 0x0 4145#define SMU_PM_STATUS_125__DATA_MASK 0xffffffff 4146#define SMU_PM_STATUS_125__DATA__SHIFT 0x0 4147#define SMU_PM_STATUS_126__DATA_MASK 0xffffffff 4148#define SMU_PM_STATUS_126__DATA__SHIFT 0x0 4149#define SMU_PM_STATUS_127__DATA_MASK 0xffffffff 4150#define SMU_PM_STATUS_127__DATA__SHIFT 0x0 4151#define CG_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1 4152#define CG_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0 4153#define CG_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2 4154#define CG_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1 4155#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4 4156#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2 4157#define CG_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8 4158#define CG_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3 4159#define CG_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10 4160#define CG_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4 4161#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20 4162#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5 4163#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff 4164#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0 4165#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00 4166#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8 4167#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000 4168#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10 4169#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000 4170#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18 4171#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000 4172#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19 4173#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000 4174#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a 4175#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000 4176#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b 4177#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000 4178#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c 4179#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1 4180#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0 4181#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2 4182#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1 4183#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4 4184#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2 4185#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8 4186#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3 4187#define CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK 0x7 4188#define CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT 0x0 4189#define CG_THERMAL_CTRL__THERM_INC_CLK_MASK 0x8 4190#define CG_THERMAL_CTRL__THERM_INC_CLK__SHIFT 0x3 4191#define CG_THERMAL_CTRL__SPARE_MASK 0x3ff0 4192#define CG_THERMAL_CTRL__SPARE__SHIFT 0x4 4193#define CG_THERMAL_CTRL__DIG_THERM_DPM_MASK 0x3fc000 4194#define CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT 0xe 4195#define CG_THERMAL_CTRL__RESERVED_MASK 0x1c00000 4196#define CG_THERMAL_CTRL__RESERVED__SHIFT 0x16 4197#define CG_THERMAL_CTRL__CTF_PAD_POLARITY_MASK 0x2000000 4198#define CG_THERMAL_CTRL__CTF_PAD_POLARITY__SHIFT 0x19 4199#define CG_THERMAL_CTRL__CTF_PAD_EN_MASK 0x4000000 4200#define CG_THERMAL_CTRL__CTF_PAD_EN__SHIFT 0x1a 4201#define CG_THERMAL_STATUS__SPARE_MASK 0x1ff 4202#define CG_THERMAL_STATUS__SPARE__SHIFT 0x0 4203#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x1fe00 4204#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9 4205#define CG_THERMAL_STATUS__THERM_ALERT_MASK 0x20000 4206#define CG_THERMAL_STATUS__THERM_ALERT__SHIFT 0x11 4207#define CG_THERMAL_STATUS__GEN_STATUS_MASK 0x3c0000 4208#define CG_THERMAL_STATUS__GEN_STATUS__SHIFT 0x12 4209#define CG_THERMAL_INT__DIG_THERM_CTF_MASK 0xff 4210#define CG_THERMAL_INT__DIG_THERM_CTF__SHIFT 0x0 4211#define CG_THERMAL_INT__DIG_THERM_INTH_MASK 0xff00 4212#define CG_THERMAL_INT__DIG_THERM_INTH__SHIFT 0x8 4213#define CG_THERMAL_INT__DIG_THERM_INTL_MASK 0xff0000 4214#define CG_THERMAL_INT__DIG_THERM_INTL__SHIFT 0x10 4215#define CG_THERMAL_INT__THERM_INT_MASK_MASK 0xf000000 4216#define CG_THERMAL_INT__THERM_INT_MASK__SHIFT 0x18 4217#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0xf 4218#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0 4219#define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0x1f0 4220#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4 4221#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x200 4222#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9 4223#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0xff00000 4224#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14 4225#define CG_MULT_THERMAL_CTRL__THM_READY_CLEAR_MASK 0x10000000 4226#define CG_MULT_THERMAL_CTRL__THM_READY_CLEAR__SHIFT 0x1c 4227#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x1ff 4228#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0 4229#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x3fe00 4230#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9 4231#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0xff 4232#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0 4233#define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK 0xff00 4234#define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT 0x8 4235#define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK 0x10000 4236#define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT 0x10 4237#define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK 0x7e0000 4238#define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT 0x11 4239#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK 0x800000 4240#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT 0x17 4241#define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK 0xff000000 4242#define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT 0x18 4243#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0xff 4244#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0 4245#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0xff00 4246#define CG_FDO_CTRL1__FMIN_DUTY__SHIFT 0x8 4247#define CG_FDO_CTRL1__M_MASK 0xff0000 4248#define CG_FDO_CTRL1__M__SHIFT 0x10 4249#define CG_FDO_CTRL1__RESERVED_MASK 0x3f000000 4250#define CG_FDO_CTRL1__RESERVED__SHIFT 0x18 4251#define CG_FDO_CTRL1__FDO_PWRDNB_MASK 0x40000000 4252#define CG_FDO_CTRL1__FDO_PWRDNB__SHIFT 0x1e 4253#define CG_FDO_CTRL2__TMIN_MASK 0xff 4254#define CG_FDO_CTRL2__TMIN__SHIFT 0x0 4255#define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK 0x700 4256#define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT 0x8 4257#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x3800 4258#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb 4259#define CG_FDO_CTRL2__TMIN_HYSTER_MASK 0x1c000 4260#define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT 0xe 4261#define CG_FDO_CTRL2__TMAX_MASK 0x1fe0000 4262#define CG_FDO_CTRL2__TMAX__SHIFT 0x11 4263#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xfe000000 4264#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19 4265#define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x7 4266#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0 4267#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xfffffff8 4268#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3 4269#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xffffffff 4270#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0 4271#define CC_THM_STRAPS0__TMON0_BGADJ_MASK 0x1fe 4272#define CC_THM_STRAPS0__TMON0_BGADJ__SHIFT 0x1 4273#define CC_THM_STRAPS0__TMON1_BGADJ_MASK 0x1fe00 4274#define CC_THM_STRAPS0__TMON1_BGADJ__SHIFT 0x9 4275#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL_MASK 0x20000 4276#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL__SHIFT 0x11 4277#define CC_THM_STRAPS0__NUM_ACQ_MASK 0x1c0000 4278#define CC_THM_STRAPS0__NUM_ACQ__SHIFT 0x12 4279#define CC_THM_STRAPS0__TMON_CLK_SEL_MASK 0xe00000 4280#define CC_THM_STRAPS0__TMON_CLK_SEL__SHIFT 0x15 4281#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE_MASK 0x1000000 4282#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE__SHIFT 0x18 4283#define CC_THM_STRAPS0__CTF_DISABLE_MASK 0x2000000 4284#define CC_THM_STRAPS0__CTF_DISABLE__SHIFT 0x19 4285#define CC_THM_STRAPS0__TMON0_DISABLE_MASK 0x4000000 4286#define CC_THM_STRAPS0__TMON0_DISABLE__SHIFT 0x1a 4287#define CC_THM_STRAPS0__TMON1_DISABLE_MASK 0x8000000 4288#define CC_THM_STRAPS0__TMON1_DISABLE__SHIFT 0x1b 4289#define CC_THM_STRAPS0__TMON2_DISABLE_MASK 0x10000000 4290#define CC_THM_STRAPS0__TMON2_DISABLE__SHIFT 0x1c 4291#define CC_THM_STRAPS0__TMON3_DISABLE_MASK 0x20000000 4292#define CC_THM_STRAPS0__TMON3_DISABLE__SHIFT 0x1d 4293#define CC_THM_STRAPS0__UNUSED_MASK 0x80000000 4294#define CC_THM_STRAPS0__UNUSED__SHIFT 0x1f 4295#define THM_TMON0_RDIL0_DATA__Z_MASK 0x7ff 4296#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0 4297#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x800 4298#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb 4299#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0xfff000 4300#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc 4301#define THM_TMON0_RDIL1_DATA__Z_MASK 0x7ff 4302#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0 4303#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x800 4304#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb 4305#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0xfff000 4306#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc 4307#define THM_TMON0_RDIL2_DATA__Z_MASK 0x7ff 4308#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0 4309#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x800 4310#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb 4311#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0xfff000 4312#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc 4313#define THM_TMON0_RDIL3_DATA__Z_MASK 0x7ff 4314#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0 4315#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x800 4316#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb 4317#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0xfff000 4318#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc 4319#define THM_TMON0_RDIL4_DATA__Z_MASK 0x7ff 4320#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0 4321#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x800 4322#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb 4323#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0xfff000 4324#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc 4325#define THM_TMON0_RDIL5_DATA__Z_MASK 0x7ff 4326#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0 4327#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x800 4328#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb 4329#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0xfff000 4330#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc 4331#define THM_TMON0_RDIL6_DATA__Z_MASK 0x7ff 4332#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0 4333#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x800 4334#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb 4335#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0xfff000 4336#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc 4337#define THM_TMON0_RDIL7_DATA__Z_MASK 0x7ff 4338#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0 4339#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x800 4340#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb 4341#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0xfff000 4342#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc 4343#define THM_TMON0_RDIL8_DATA__Z_MASK 0x7ff 4344#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0 4345#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x800 4346#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb 4347#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0xfff000 4348#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc 4349#define THM_TMON0_RDIL9_DATA__Z_MASK 0x7ff 4350#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0 4351#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x800 4352#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb 4353#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0xfff000 4354#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc 4355#define THM_TMON0_RDIL10_DATA__Z_MASK 0x7ff 4356#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0 4357#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x800 4358#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb 4359#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0xfff000 4360#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc 4361#define THM_TMON0_RDIL11_DATA__Z_MASK 0x7ff 4362#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0 4363#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x800 4364#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb 4365#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0xfff000 4366#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc 4367#define THM_TMON0_RDIL12_DATA__Z_MASK 0x7ff 4368#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0 4369#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x800 4370#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb 4371#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0xfff000 4372#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc 4373#define THM_TMON0_RDIL13_DATA__Z_MASK 0x7ff 4374#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0 4375#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x800 4376#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb 4377#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0xfff000 4378#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc 4379#define THM_TMON0_RDIL14_DATA__Z_MASK 0x7ff 4380#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0 4381#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x800 4382#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb 4383#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0xfff000 4384#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc 4385#define THM_TMON0_RDIL15_DATA__Z_MASK 0x7ff 4386#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0 4387#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x800 4388#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb 4389#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0xfff000 4390#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc 4391#define THM_TMON0_RDIR0_DATA__Z_MASK 0x7ff 4392#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0 4393#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x800 4394#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb 4395#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0xfff000 4396#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc 4397#define THM_TMON0_RDIR1_DATA__Z_MASK 0x7ff 4398#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0 4399#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x800 4400#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb 4401#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0xfff000 4402#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc 4403#define THM_TMON0_RDIR2_DATA__Z_MASK 0x7ff 4404#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0 4405#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x800 4406#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb 4407#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0xfff000 4408#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc 4409#define THM_TMON0_RDIR3_DATA__Z_MASK 0x7ff 4410#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0 4411#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x800 4412#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb 4413#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0xfff000 4414#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc 4415#define THM_TMON0_RDIR4_DATA__Z_MASK 0x7ff 4416#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0 4417#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x800 4418#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb 4419#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0xfff000 4420#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc 4421#define THM_TMON0_RDIR5_DATA__Z_MASK 0x7ff 4422#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0 4423#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x800 4424#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb 4425#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0xfff000 4426#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc 4427#define THM_TMON0_RDIR6_DATA__Z_MASK 0x7ff 4428#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0 4429#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x800 4430#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb 4431#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0xfff000 4432#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc 4433#define THM_TMON0_RDIR7_DATA__Z_MASK 0x7ff 4434#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0 4435#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x800 4436#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb 4437#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0xfff000 4438#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc 4439#define THM_TMON0_RDIR8_DATA__Z_MASK 0x7ff 4440#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0 4441#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x800 4442#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb 4443#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0xfff000 4444#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc 4445#define THM_TMON0_RDIR9_DATA__Z_MASK 0x7ff 4446#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0 4447#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x800 4448#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb 4449#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0xfff000 4450#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc 4451#define THM_TMON0_RDIR10_DATA__Z_MASK 0x7ff 4452#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0 4453#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x800 4454#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb 4455#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0xfff000 4456#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc 4457#define THM_TMON0_RDIR11_DATA__Z_MASK 0x7ff 4458#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0 4459#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x800 4460#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb 4461#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0xfff000 4462#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc 4463#define THM_TMON0_RDIR12_DATA__Z_MASK 0x7ff 4464#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0 4465#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x800 4466#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb 4467#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0xfff000 4468#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc 4469#define THM_TMON0_RDIR13_DATA__Z_MASK 0x7ff 4470#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0 4471#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x800 4472#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb 4473#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0xfff000 4474#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc 4475#define THM_TMON0_RDIR14_DATA__Z_MASK 0x7ff 4476#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0 4477#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x800 4478#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb 4479#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0xfff000 4480#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc 4481#define THM_TMON0_RDIR15_DATA__Z_MASK 0x7ff 4482#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0 4483#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x800 4484#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb 4485#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0xfff000 4486#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc 4487#define THM_TMON1_RDIL0_DATA__Z_MASK 0x7ff 4488#define THM_TMON1_RDIL0_DATA__Z__SHIFT 0x0 4489#define THM_TMON1_RDIL0_DATA__VALID_MASK 0x800 4490#define THM_TMON1_RDIL0_DATA__VALID__SHIFT 0xb 4491#define THM_TMON1_RDIL0_DATA__TEMP_MASK 0xfff000 4492#define THM_TMON1_RDIL0_DATA__TEMP__SHIFT 0xc 4493#define THM_TMON1_RDIL1_DATA__Z_MASK 0x7ff 4494#define THM_TMON1_RDIL1_DATA__Z__SHIFT 0x0 4495#define THM_TMON1_RDIL1_DATA__VALID_MASK 0x800 4496#define THM_TMON1_RDIL1_DATA__VALID__SHIFT 0xb 4497#define THM_TMON1_RDIL1_DATA__TEMP_MASK 0xfff000 4498#define THM_TMON1_RDIL1_DATA__TEMP__SHIFT 0xc 4499#define THM_TMON1_RDIL2_DATA__Z_MASK 0x7ff 4500#define THM_TMON1_RDIL2_DATA__Z__SHIFT 0x0 4501#define THM_TMON1_RDIL2_DATA__VALID_MASK 0x800 4502#define THM_TMON1_RDIL2_DATA__VALID__SHIFT 0xb 4503#define THM_TMON1_RDIL2_DATA__TEMP_MASK 0xfff000 4504#define THM_TMON1_RDIL2_DATA__TEMP__SHIFT 0xc 4505#define THM_TMON1_RDIL3_DATA__Z_MASK 0x7ff 4506#define THM_TMON1_RDIL3_DATA__Z__SHIFT 0x0 4507#define THM_TMON1_RDIL3_DATA__VALID_MASK 0x800 4508#define THM_TMON1_RDIL3_DATA__VALID__SHIFT 0xb 4509#define THM_TMON1_RDIL3_DATA__TEMP_MASK 0xfff000 4510#define THM_TMON1_RDIL3_DATA__TEMP__SHIFT 0xc 4511#define THM_TMON1_RDIL4_DATA__Z_MASK 0x7ff 4512#define THM_TMON1_RDIL4_DATA__Z__SHIFT 0x0 4513#define THM_TMON1_RDIL4_DATA__VALID_MASK 0x800 4514#define THM_TMON1_RDIL4_DATA__VALID__SHIFT 0xb 4515#define THM_TMON1_RDIL4_DATA__TEMP_MASK 0xfff000 4516#define THM_TMON1_RDIL4_DATA__TEMP__SHIFT 0xc 4517#define THM_TMON1_RDIL5_DATA__Z_MASK 0x7ff 4518#define THM_TMON1_RDIL5_DATA__Z__SHIFT 0x0 4519#define THM_TMON1_RDIL5_DATA__VALID_MASK 0x800 4520#define THM_TMON1_RDIL5_DATA__VALID__SHIFT 0xb 4521#define THM_TMON1_RDIL5_DATA__TEMP_MASK 0xfff000 4522#define THM_TMON1_RDIL5_DATA__TEMP__SHIFT 0xc 4523#define THM_TMON1_RDIL6_DATA__Z_MASK 0x7ff 4524#define THM_TMON1_RDIL6_DATA__Z__SHIFT 0x0 4525#define THM_TMON1_RDIL6_DATA__VALID_MASK 0x800 4526#define THM_TMON1_RDIL6_DATA__VALID__SHIFT 0xb 4527#define THM_TMON1_RDIL6_DATA__TEMP_MASK 0xfff000 4528#define THM_TMON1_RDIL6_DATA__TEMP__SHIFT 0xc 4529#define THM_TMON1_RDIL7_DATA__Z_MASK 0x7ff 4530#define THM_TMON1_RDIL7_DATA__Z__SHIFT 0x0 4531#define THM_TMON1_RDIL7_DATA__VALID_MASK 0x800 4532#define THM_TMON1_RDIL7_DATA__VALID__SHIFT 0xb 4533#define THM_TMON1_RDIL7_DATA__TEMP_MASK 0xfff000 4534#define THM_TMON1_RDIL7_DATA__TEMP__SHIFT 0xc 4535#define THM_TMON1_RDIL8_DATA__Z_MASK 0x7ff 4536#define THM_TMON1_RDIL8_DATA__Z__SHIFT 0x0 4537#define THM_TMON1_RDIL8_DATA__VALID_MASK 0x800 4538#define THM_TMON1_RDIL8_DATA__VALID__SHIFT 0xb 4539#define THM_TMON1_RDIL8_DATA__TEMP_MASK 0xfff000 4540#define THM_TMON1_RDIL8_DATA__TEMP__SHIFT 0xc 4541#define THM_TMON1_RDIL9_DATA__Z_MASK 0x7ff 4542#define THM_TMON1_RDIL9_DATA__Z__SHIFT 0x0 4543#define THM_TMON1_RDIL9_DATA__VALID_MASK 0x800 4544#define THM_TMON1_RDIL9_DATA__VALID__SHIFT 0xb 4545#define THM_TMON1_RDIL9_DATA__TEMP_MASK 0xfff000 4546#define THM_TMON1_RDIL9_DATA__TEMP__SHIFT 0xc 4547#define THM_TMON1_RDIL10_DATA__Z_MASK 0x7ff 4548#define THM_TMON1_RDIL10_DATA__Z__SHIFT 0x0 4549#define THM_TMON1_RDIL10_DATA__VALID_MASK 0x800 4550#define THM_TMON1_RDIL10_DATA__VALID__SHIFT 0xb 4551#define THM_TMON1_RDIL10_DATA__TEMP_MASK 0xfff000 4552#define THM_TMON1_RDIL10_DATA__TEMP__SHIFT 0xc 4553#define THM_TMON1_RDIL11_DATA__Z_MASK 0x7ff 4554#define THM_TMON1_RDIL11_DATA__Z__SHIFT 0x0 4555#define THM_TMON1_RDIL11_DATA__VALID_MASK 0x800 4556#define THM_TMON1_RDIL11_DATA__VALID__SHIFT 0xb 4557#define THM_TMON1_RDIL11_DATA__TEMP_MASK 0xfff000 4558#define THM_TMON1_RDIL11_DATA__TEMP__SHIFT 0xc 4559#define THM_TMON1_RDIL12_DATA__Z_MASK 0x7ff 4560#define THM_TMON1_RDIL12_DATA__Z__SHIFT 0x0 4561#define THM_TMON1_RDIL12_DATA__VALID_MASK 0x800 4562#define THM_TMON1_RDIL12_DATA__VALID__SHIFT 0xb 4563#define THM_TMON1_RDIL12_DATA__TEMP_MASK 0xfff000 4564#define THM_TMON1_RDIL12_DATA__TEMP__SHIFT 0xc 4565#define THM_TMON1_RDIL13_DATA__Z_MASK 0x7ff 4566#define THM_TMON1_RDIL13_DATA__Z__SHIFT 0x0 4567#define THM_TMON1_RDIL13_DATA__VALID_MASK 0x800 4568#define THM_TMON1_RDIL13_DATA__VALID__SHIFT 0xb 4569#define THM_TMON1_RDIL13_DATA__TEMP_MASK 0xfff000 4570#define THM_TMON1_RDIL13_DATA__TEMP__SHIFT 0xc 4571#define THM_TMON1_RDIL14_DATA__Z_MASK 0x7ff 4572#define THM_TMON1_RDIL14_DATA__Z__SHIFT 0x0 4573#define THM_TMON1_RDIL14_DATA__VALID_MASK 0x800 4574#define THM_TMON1_RDIL14_DATA__VALID__SHIFT 0xb 4575#define THM_TMON1_RDIL14_DATA__TEMP_MASK 0xfff000 4576#define THM_TMON1_RDIL14_DATA__TEMP__SHIFT 0xc 4577#define THM_TMON1_RDIL15_DATA__Z_MASK 0x7ff 4578#define THM_TMON1_RDIL15_DATA__Z__SHIFT 0x0 4579#define THM_TMON1_RDIL15_DATA__VALID_MASK 0x800 4580#define THM_TMON1_RDIL15_DATA__VALID__SHIFT 0xb 4581#define THM_TMON1_RDIL15_DATA__TEMP_MASK 0xfff000 4582#define THM_TMON1_RDIL15_DATA__TEMP__SHIFT 0xc 4583#define THM_TMON1_RDIR0_DATA__Z_MASK 0x7ff 4584#define THM_TMON1_RDIR0_DATA__Z__SHIFT 0x0 4585#define THM_TMON1_RDIR0_DATA__VALID_MASK 0x800 4586#define THM_TMON1_RDIR0_DATA__VALID__SHIFT 0xb 4587#define THM_TMON1_RDIR0_DATA__TEMP_MASK 0xfff000 4588#define THM_TMON1_RDIR0_DATA__TEMP__SHIFT 0xc 4589#define THM_TMON1_RDIR1_DATA__Z_MASK 0x7ff 4590#define THM_TMON1_RDIR1_DATA__Z__SHIFT 0x0 4591#define THM_TMON1_RDIR1_DATA__VALID_MASK 0x800 4592#define THM_TMON1_RDIR1_DATA__VALID__SHIFT 0xb 4593#define THM_TMON1_RDIR1_DATA__TEMP_MASK 0xfff000 4594#define THM_TMON1_RDIR1_DATA__TEMP__SHIFT 0xc 4595#define THM_TMON1_RDIR2_DATA__Z_MASK 0x7ff 4596#define THM_TMON1_RDIR2_DATA__Z__SHIFT 0x0 4597#define THM_TMON1_RDIR2_DATA__VALID_MASK 0x800 4598#define THM_TMON1_RDIR2_DATA__VALID__SHIFT 0xb 4599#define THM_TMON1_RDIR2_DATA__TEMP_MASK 0xfff000 4600#define THM_TMON1_RDIR2_DATA__TEMP__SHIFT 0xc 4601#define THM_TMON1_RDIR3_DATA__Z_MASK 0x7ff 4602#define THM_TMON1_RDIR3_DATA__Z__SHIFT 0x0 4603#define THM_TMON1_RDIR3_DATA__VALID_MASK 0x800 4604#define THM_TMON1_RDIR3_DATA__VALID__SHIFT 0xb 4605#define THM_TMON1_RDIR3_DATA__TEMP_MASK 0xfff000 4606#define THM_TMON1_RDIR3_DATA__TEMP__SHIFT 0xc 4607#define THM_TMON1_RDIR4_DATA__Z_MASK 0x7ff 4608#define THM_TMON1_RDIR4_DATA__Z__SHIFT 0x0 4609#define THM_TMON1_RDIR4_DATA__VALID_MASK 0x800 4610#define THM_TMON1_RDIR4_DATA__VALID__SHIFT 0xb 4611#define THM_TMON1_RDIR4_DATA__TEMP_MASK 0xfff000 4612#define THM_TMON1_RDIR4_DATA__TEMP__SHIFT 0xc 4613#define THM_TMON1_RDIR5_DATA__Z_MASK 0x7ff 4614#define THM_TMON1_RDIR5_DATA__Z__SHIFT 0x0 4615#define THM_TMON1_RDIR5_DATA__VALID_MASK 0x800 4616#define THM_TMON1_RDIR5_DATA__VALID__SHIFT 0xb 4617#define THM_TMON1_RDIR5_DATA__TEMP_MASK 0xfff000 4618#define THM_TMON1_RDIR5_DATA__TEMP__SHIFT 0xc 4619#define THM_TMON1_RDIR6_DATA__Z_MASK 0x7ff 4620#define THM_TMON1_RDIR6_DATA__Z__SHIFT 0x0 4621#define THM_TMON1_RDIR6_DATA__VALID_MASK 0x800 4622#define THM_TMON1_RDIR6_DATA__VALID__SHIFT 0xb 4623#define THM_TMON1_RDIR6_DATA__TEMP_MASK 0xfff000 4624#define THM_TMON1_RDIR6_DATA__TEMP__SHIFT 0xc 4625#define THM_TMON1_RDIR7_DATA__Z_MASK 0x7ff 4626#define THM_TMON1_RDIR7_DATA__Z__SHIFT 0x0 4627#define THM_TMON1_RDIR7_DATA__VALID_MASK 0x800 4628#define THM_TMON1_RDIR7_DATA__VALID__SHIFT 0xb 4629#define THM_TMON1_RDIR7_DATA__TEMP_MASK 0xfff000 4630#define THM_TMON1_RDIR7_DATA__TEMP__SHIFT 0xc 4631#define THM_TMON1_RDIR8_DATA__Z_MASK 0x7ff 4632#define THM_TMON1_RDIR8_DATA__Z__SHIFT 0x0 4633#define THM_TMON1_RDIR8_DATA__VALID_MASK 0x800 4634#define THM_TMON1_RDIR8_DATA__VALID__SHIFT 0xb 4635#define THM_TMON1_RDIR8_DATA__TEMP_MASK 0xfff000 4636#define THM_TMON1_RDIR8_DATA__TEMP__SHIFT 0xc 4637#define THM_TMON1_RDIR9_DATA__Z_MASK 0x7ff 4638#define THM_TMON1_RDIR9_DATA__Z__SHIFT 0x0 4639#define THM_TMON1_RDIR9_DATA__VALID_MASK 0x800 4640#define THM_TMON1_RDIR9_DATA__VALID__SHIFT 0xb 4641#define THM_TMON1_RDIR9_DATA__TEMP_MASK 0xfff000 4642#define THM_TMON1_RDIR9_DATA__TEMP__SHIFT 0xc 4643#define THM_TMON1_RDIR10_DATA__Z_MASK 0x7ff 4644#define THM_TMON1_RDIR10_DATA__Z__SHIFT 0x0 4645#define THM_TMON1_RDIR10_DATA__VALID_MASK 0x800 4646#define THM_TMON1_RDIR10_DATA__VALID__SHIFT 0xb 4647#define THM_TMON1_RDIR10_DATA__TEMP_MASK 0xfff000 4648#define THM_TMON1_RDIR10_DATA__TEMP__SHIFT 0xc 4649#define THM_TMON1_RDIR11_DATA__Z_MASK 0x7ff 4650#define THM_TMON1_RDIR11_DATA__Z__SHIFT 0x0 4651#define THM_TMON1_RDIR11_DATA__VALID_MASK 0x800 4652#define THM_TMON1_RDIR11_DATA__VALID__SHIFT 0xb 4653#define THM_TMON1_RDIR11_DATA__TEMP_MASK 0xfff000 4654#define THM_TMON1_RDIR11_DATA__TEMP__SHIFT 0xc 4655#define THM_TMON1_RDIR12_DATA__Z_MASK 0x7ff 4656#define THM_TMON1_RDIR12_DATA__Z__SHIFT 0x0 4657#define THM_TMON1_RDIR12_DATA__VALID_MASK 0x800 4658#define THM_TMON1_RDIR12_DATA__VALID__SHIFT 0xb 4659#define THM_TMON1_RDIR12_DATA__TEMP_MASK 0xfff000 4660#define THM_TMON1_RDIR12_DATA__TEMP__SHIFT 0xc 4661#define THM_TMON1_RDIR13_DATA__Z_MASK 0x7ff 4662#define THM_TMON1_RDIR13_DATA__Z__SHIFT 0x0 4663#define THM_TMON1_RDIR13_DATA__VALID_MASK 0x800 4664#define THM_TMON1_RDIR13_DATA__VALID__SHIFT 0xb 4665#define THM_TMON1_RDIR13_DATA__TEMP_MASK 0xfff000 4666#define THM_TMON1_RDIR13_DATA__TEMP__SHIFT 0xc 4667#define THM_TMON1_RDIR14_DATA__Z_MASK 0x7ff 4668#define THM_TMON1_RDIR14_DATA__Z__SHIFT 0x0 4669#define THM_TMON1_RDIR14_DATA__VALID_MASK 0x800 4670#define THM_TMON1_RDIR14_DATA__VALID__SHIFT 0xb 4671#define THM_TMON1_RDIR14_DATA__TEMP_MASK 0xfff000 4672#define THM_TMON1_RDIR14_DATA__TEMP__SHIFT 0xc 4673#define THM_TMON1_RDIR15_DATA__Z_MASK 0x7ff 4674#define THM_TMON1_RDIR15_DATA__Z__SHIFT 0x0 4675#define THM_TMON1_RDIR15_DATA__VALID_MASK 0x800 4676#define THM_TMON1_RDIR15_DATA__VALID__SHIFT 0xb 4677#define THM_TMON1_RDIR15_DATA__TEMP_MASK 0xfff000 4678#define THM_TMON1_RDIR15_DATA__TEMP__SHIFT 0xc 4679#define THM_TMON0_INT_DATA__Z_MASK 0x7ff 4680#define THM_TMON0_INT_DATA__Z__SHIFT 0x0 4681#define THM_TMON0_INT_DATA__VALID_MASK 0x800 4682#define THM_TMON0_INT_DATA__VALID__SHIFT 0xb 4683#define THM_TMON0_INT_DATA__TEMP_MASK 0xfff000 4684#define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc 4685#define THM_TMON1_INT_DATA__Z_MASK 0x7ff 4686#define THM_TMON1_INT_DATA__Z__SHIFT 0x0 4687#define THM_TMON1_INT_DATA__VALID_MASK 0x800 4688#define THM_TMON1_INT_DATA__VALID__SHIFT 0xb 4689#define THM_TMON1_INT_DATA__TEMP_MASK 0xfff000 4690#define THM_TMON1_INT_DATA__TEMP__SHIFT 0xc 4691#define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x1f 4692#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x0 4693#define THM_TMON0_DEBUG__DEBUG_Z_MASK 0xffe0 4694#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x5 4695#define THM_TMON1_DEBUG__DEBUG_RDI_MASK 0x1f 4696#define THM_TMON1_DEBUG__DEBUG_RDI__SHIFT 0x0 4697#define THM_TMON1_DEBUG__DEBUG_Z_MASK 0xffe0 4698#define THM_TMON1_DEBUG__DEBUG_Z__SHIFT 0x5 4699#define THM_TMON0_STATUS__CURRENT_RDI_MASK 0x1f 4700#define THM_TMON0_STATUS__CURRENT_RDI__SHIFT 0x0 4701#define THM_TMON0_STATUS__MEAS_DONE_MASK 0x20 4702#define THM_TMON0_STATUS__MEAS_DONE__SHIFT 0x5 4703#define THM_TMON1_STATUS__CURRENT_RDI_MASK 0x1f 4704#define THM_TMON1_STATUS__CURRENT_RDI__SHIFT 0x0 4705#define THM_TMON1_STATUS__MEAS_DONE_MASK 0x20 4706#define THM_TMON1_STATUS__MEAS_DONE__SHIFT 0x5 4707#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1 4708#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0 4709#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2 4710#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1 4711#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4 4712#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2 4713#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8 4714#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3 4715#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40 4716#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6 4717#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100 4718#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8 4719#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200 4720#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9 4721#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400 4722#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa 4723#define GENERAL_PWRMGT__SPARE11_MASK 0x800 4724#define GENERAL_PWRMGT__SPARE11__SHIFT 0xb 4725#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000 4726#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe 4727#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000 4728#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf 4729#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000 4730#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10 4731#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000 4732#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11 4733#define GENERAL_PWRMGT__SPARE18_MASK 0x40000 4734#define GENERAL_PWRMGT__SPARE18__SHIFT 0x12 4735#define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000 4736#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13 4737#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000 4738#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17 4739#define GENERAL_PWRMGT__SPARE27_MASK 0x8000000 4740#define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b 4741#define GENERAL_PWRMGT__SPARE_MASK 0xf0000000 4742#define GENERAL_PWRMGT__SPARE__SHIFT 0x1c 4743#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3 4744#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0 4745#define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4 4746#define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2 4747#define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8 4748#define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3 4749#define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10 4750#define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4 4751#define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0 4752#define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5 4753#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK 0x1 4754#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF__SHIFT 0x0 4755#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10 4756#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4 4757#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20 4758#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5 4759#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN_MASK 0x4000 4760#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN__SHIFT 0xe 4761#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP_MASK 0x8000 4762#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP__SHIFT 0xf 4763#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER_MASK 0x1f0000 4764#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER__SHIFT 0x10 4765#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK 0x200000 4766#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN__SHIFT 0x15 4767#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE_MASK 0xf 4768#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE__SHIFT 0x0 4769#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_MASK 0xf0 4770#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4 4771#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00 4772#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8 4773#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000 4774#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc 4775#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000 4776#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10 4777#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000 4778#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15 4779#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000 4780#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a 4781#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000 4782#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d 4783#define PWR_PCC_CONTROL__PCC_POLARITY_MASK 0x1 4784#define PWR_PCC_CONTROL__PCC_POLARITY__SHIFT 0x0 4785#define PWR_PCC_GPIO_SELECT__GPIO_MASK 0xffffffff 4786#define PWR_PCC_GPIO_SELECT__GPIO__SHIFT 0x0 4787#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 4788#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 4789#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 4790#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 4791#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 4792#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 4793#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 4794#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 4795#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 4796#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 4797#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 4798#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 4799#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 4800#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 4801#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 4802#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 4803#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 4804#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 4805#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 4806#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 4807#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 4808#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 4809#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 4810#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 4811#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 4812#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc 4813#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 4814#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 4815#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 4816#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 4817#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 4818#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 4819#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 4820#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 4821#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 4822#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 4823#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 4824#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 4825#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 4826#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 4827#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 4828#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 4829#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 4830#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 4831#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 4832#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 4833#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 4834#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 4835#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 4836#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 4837#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 4838#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 4839#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 4840#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 4841#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 4842#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 4843#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 4844#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 4845#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 4846#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 4847#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 4848#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 4849#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 4850#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 4851#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 4852#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 4853#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 4854#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 4855#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 4856#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 4857#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 4858#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 4859#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 4860#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 4861#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 4862#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 4863#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 4864#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 4865#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 4866#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 4867#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 4868#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 4869#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 4870#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 4871#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 4872#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 4873#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 4874#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc 4875#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 4876#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 4877#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 4878#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 4879#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 4880#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 4881#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 4882#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 4883#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 4884#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 4885#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 4886#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 4887#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 4888#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 4889#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 4890#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 4891#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 4892#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 4893#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 4894#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 4895#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 4896#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 4897#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 4898#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 4899#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 4900#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 4901#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 4902#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 4903#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 4904#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 4905#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 4906#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 4907#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 4908#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 4909#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 4910#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 4911#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 4912#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 4913#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 4914#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 4915#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 4916#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 4917#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 4918#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 4919#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 4920#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 4921#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 4922#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 4923#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 4924#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 4925#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 4926#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 4927#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 4928#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 4929#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 4930#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 4931#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 4932#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 4933#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 4934#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 4935#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 4936#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc 4937#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 4938#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 4939#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 4940#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 4941#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 4942#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 4943#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 4944#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 4945#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 4946#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 4947#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 4948#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 4949#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 4950#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 4951#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 4952#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 4953#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 4954#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 4955#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 4956#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 4957#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 4958#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 4959#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 4960#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 4961#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 4962#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 4963#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 4964#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 4965#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 4966#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 4967#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 4968#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 4969#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 4970#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 4971#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 4972#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 4973#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 4974#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 4975#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 4976#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 4977#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 4978#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 4979#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 4980#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 4981#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 4982#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 4983#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 4984#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 4985#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 4986#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 4987#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 4988#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 4989#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 4990#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 4991#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 4992#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 4993#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 4994#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 4995#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 4996#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 4997#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 4998#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc 4999#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 5000#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
5001#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 5002#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 5003#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 5004#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 5005#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 5006#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 5007#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 5008#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 5009#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 5010#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 5011#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 5012#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 5013#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 5014#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 5015#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 5016#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 5017#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 5018#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 5019#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 5020#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 5021#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 5022#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 5023#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 5024#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 5025#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 5026#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 5027#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 5028#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 5029#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 5030#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 5031#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 5032#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 5033#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 5034#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 5035#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 5036#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 5037#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 5038#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 5039#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 5040#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 5041#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 5042#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 5043#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 5044#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 5045#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 5046#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 5047#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 5048#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 5049#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 5050#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 5051#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 5052#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 5053#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 5054#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 5055#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 5056#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 5057#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 5058#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 5059#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 5060#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc 5061#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 5062#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 5063#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 5064#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 5065#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 5066#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 5067#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 5068#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 5069#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 5070#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 5071#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 5072#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 5073#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 5074#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 5075#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 5076#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 5077#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 5078#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 5079#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 5080#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 5081#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 5082#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 5083#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 5084#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 5085#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 5086#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 5087#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 5088#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 5089#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 5090#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 5091#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 5092#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 5093#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 5094#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 5095#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 5096#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 5097#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 5098#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 5099#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 5100#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 5101#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 5102#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 5103#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 5104#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 5105#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 5106#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 5107#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 5108#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 5109#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 5110#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 5111#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 5112#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 5113#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 5114#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 5115#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 5116#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 5117#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 5118#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 5119#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 5120#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 5121#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 5122#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc 5123#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 5124#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 5125#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 5126#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 5127#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 5128#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 5129#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 5130#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 5131#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 5132#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 5133#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 5134#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 5135#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 5136#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 5137#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 5138#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 5139#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 5140#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 5141#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 5142#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 5143#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 5144#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 5145#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 5146#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 5147#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 5148#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 5149#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 5150#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 5151#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 5152#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 5153#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 5154#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 5155#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 5156#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 5157#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 5158#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 5159#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 5160#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 5161#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 5162#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 5163#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 5164#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 5165#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 5166#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 5167#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 5168#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 5169#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 5170#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 5171#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 5172#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 5173#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 5174#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 5175#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 5176#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 5177#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 5178#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 5179#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 5180#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 5181#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 5182#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 5183#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 5184#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc 5185#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 5186#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 5187#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 5188#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 5189#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 5190#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 5191#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 5192#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 5193#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 5194#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 5195#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 5196#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 5197#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 5198#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 5199#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 5200#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 5201#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 5202#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 5203#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 5204#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 5205#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 5206#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 5207#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 5208#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 5209#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 5210#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 5211#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 5212#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 5213#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 5214#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 5215#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 5216#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 5217#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 5218#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 5219#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 5220#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 5221#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 5222#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 5223#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 5224#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 5225#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 5226#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 5227#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 5228#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 5229#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 5230#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 5231#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 5232#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 5233#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 5234#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 5235#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 5236#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 5237#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 5238#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 5239#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 5240#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 5241#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 5242#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 5243#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 5244#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 5245#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 5246#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc 5247#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 5248#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 5249#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 5250#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 5251#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 5252#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 5253#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 5254#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 5255#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 5256#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 5257#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 5258#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 5259#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 5260#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 5261#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 5262#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 5263#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 5264#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 5265#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 5266#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 5267#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 5268#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 5269#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 5270#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 5271#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 5272#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 5273#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 5274#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 5275#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 5276#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 5277#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 5278#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 5279#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 5280#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 5281#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 5282#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 5283#define PLL_TEST_CNTL__TST_SRC_SEL_MASK 0xf 5284#define PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0 5285#define PLL_TEST_CNTL__TST_REF_SEL_MASK 0xf0 5286#define PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x4 5287#define PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x7f00 5288#define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8 5289#define PLL_TEST_CNTL__TST_RESET_MASK 0x8000 5290#define PLL_TEST_CNTL__TST_RESET__SHIFT 0xf 5291#define PLL_TEST_CNTL__TEST_COUNT_MASK 0xfffe0000 5292#define PLL_TEST_CNTL__TEST_COUNT__SHIFT 0x11 5293#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff 5294#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0 5295#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000 5296#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10 5297#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK 0x3 5298#define CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT 0x0 5299#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT_MASK 0x3fff0 5300#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT__SHIFT 0x4 5301#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT_MASK 0x700000 5302#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT__SHIFT 0x14 5303#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK 0x3000000 5304#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT 0x18 5305#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE_MASK 0x10000000 5306#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE__SHIFT 0x1c 5307#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION_MASK 0xffffffff 5308#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION__SHIFT 0x0 5309#define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f 5310#define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0 5311#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80 5312#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7 5313#define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 5314#define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 5315#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 5316#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 5317#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 5318#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 5319#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000 5320#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10 5321#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000 5322#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11 5323#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000 5324#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12 5325#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000 5326#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13 5327#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000 5328#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14 5329#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000 5330#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15 5331#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000 5332#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16 5333#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000 5334#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17 5335#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000 5336#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18 5337#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000 5338#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19 5339#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000 5340#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a 5341#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000 5342#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b 5343#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000 5344#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c 5345#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK_MASK 0x20000000 5346#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK__SHIFT 0x1d 5347#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000 5348#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e 5349#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 5350#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f 5351#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1 5352#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0 5353#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2 5354#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1 5355#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4 5356#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2 5357#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8 5358#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3 5359#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10 5360#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4 5361#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40 5362#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6 5363#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80 5364#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7 5365#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100 5366#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8 5367#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200 5368#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9 5369#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400 5370#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa 5371#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK_MASK 0x800 5372#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK__SHIFT 0xb 5373#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK_MASK 0x1000 5374#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK__SHIFT 0xc 5375#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK_MASK 0x2000 5376#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK__SHIFT 0xd 5377#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x4000 5378#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0xe 5379#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID_MASK 0xe00000 5380#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID__SHIFT 0x15 5381#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000 5382#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18 5383#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1 5384#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0 5385#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2 5386#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1 5387#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4 5388#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2 5389#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8 5390#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3 5391#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10 5392#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4 5393#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20 5394#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5 5395#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40 5396#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6 5397#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80 5398#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7 5399#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100 5400#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8 5401#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200 5402#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9 5403#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400 5404#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa 5405#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800 5406#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb 5407#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000 5408#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc 5409#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000 5410#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd 5411#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000 5412#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe 5413#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000 5414#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf 5415#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7 5416#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0 5417#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38 5418#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3 5419#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000 5420#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10 5421#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000 5422#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11 5423#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000 5424#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14 5425#define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 5426#define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 5427#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 5428#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 5429#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 5430#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 5431#define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000 5432#define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10 5433#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 5434#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f 5435#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1 5436#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0 5437#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2 5438#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1 5439#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4 5440#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2 5441#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8 5442#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3 5443#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10 5444#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4 5445#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20 5446#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5 5447#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40 5448#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6 5449#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80 5450#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7 5451#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100 5452#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8 5453#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200 5454#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9 5455#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400 5456#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa 5457#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800 5458#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb 5459#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000 5460#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc 5461#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000 5462#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd 5463#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000 5464#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe 5465#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000 5466#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf 5467#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000 5468#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10 5469#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000 5470#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11 5471#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000 5472#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12 5473#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000 5474#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13 5475#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000 5476#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14 5477#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x200000 5478#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0x15 5479#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xffc00000 5480#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x16 5481#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf 5482#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0 5483#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0 5484#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4 5485#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00 5486#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8 5487#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000 5488#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc 5489#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000 5490#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10 5491#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000 5492#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14 5493#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000 5494#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18 5495#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000 5496#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c 5497#define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff 5498#define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0 5499#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000 5500#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10 5501#define SCLK_MIN_DIV__FRACV_MASK 0xfff 5502#define SCLK_MIN_DIV__FRACV__SHIFT 0x0 5503#define SCLK_MIN_DIV__INTV_MASK 0x7f000 5504#define SCLK_MIN_DIV__INTV__SHIFT 0xc 5505#define PWR_CKS_ENABLE__STRETCH_ENABLE_MASK 0x1 5506#define PWR_CKS_ENABLE__STRETCH_ENABLE__SHIFT 0x0 5507#define PWR_CKS_ENABLE__masterReset_MASK 0x2 5508#define PWR_CKS_ENABLE__masterReset__SHIFT 0x1 5509#define PWR_CKS_ENABLE__staticEnable_MASK 0x4 5510#define PWR_CKS_ENABLE__staticEnable__SHIFT 0x2 5511#define PWR_CKS_CNTL__CKS_BYPASS_MASK 0x1 5512#define PWR_CKS_CNTL__CKS_BYPASS__SHIFT 0x0 5513#define PWR_CKS_CNTL__CKS_PCCEnable_MASK 0x2 5514#define PWR_CKS_CNTL__CKS_PCCEnable__SHIFT 0x1 5515#define PWR_CKS_CNTL__CKS_TEMP_COMP_MASK 0x4 5516#define PWR_CKS_CNTL__CKS_TEMP_COMP__SHIFT 0x2 5517#define PWR_CKS_CNTL__CKS_STRETCH_AMOUNT_MASK 0x78 5518#define PWR_CKS_CNTL__CKS_STRETCH_AMOUNT__SHIFT 0x3 5519#define PWR_CKS_CNTL__CKS_SKIP_PHASE_BYPASS_MASK 0x80 5520#define PWR_CKS_CNTL__CKS_SKIP_PHASE_BYPASS__SHIFT 0x7 5521#define PWR_CKS_CNTL__CKS_SAMPLE_SIZE_MASK 0xf00 5522#define PWR_CKS_CNTL__CKS_SAMPLE_SIZE__SHIFT 0x8 5523#define PWR_CKS_CNTL__CKS_FSM_WAIT_CYCLES_MASK 0xf000 5524#define PWR_CKS_CNTL__CKS_FSM_WAIT_CYCLES__SHIFT 0xc 5525#define PWR_CKS_CNTL__CKS_USE_FOR_LOW_FREQ_MASK 0x10000 5526#define PWR_CKS_CNTL__CKS_USE_FOR_LOW_FREQ__SHIFT 0x10 5527#define PWR_CKS_CNTL__CKS_NO_EXTRA_COARSE_STEP_MASK 0x20000 5528#define PWR_CKS_CNTL__CKS_NO_EXTRA_COARSE_STEP__SHIFT 0x11 5529#define PWR_CKS_CNTL__CKS_LDO_REFSEL_MASK 0x3c0000 5530#define PWR_CKS_CNTL__CKS_LDO_REFSEL__SHIFT 0x12 5531#define PWR_CKS_CNTL__DDT_DEBUS_SEL_MASK 0x400000 5532#define PWR_CKS_CNTL__DDT_DEBUS_SEL__SHIFT 0x16 5533#define PWR_CKS_CNTL__CKS_LDO_READY_COUNT_VAL_MASK 0x7f800000 5534#define PWR_CKS_CNTL__CKS_LDO_READY_COUNT_VAL__SHIFT 0x17 5535#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff 5536#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 5537#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 5538#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 5539#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x4000000 5540#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a 5541#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 5542#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 5543#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000 5544#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c 5545#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000 5546#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d 5547#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000 5548#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e 5549#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x1 5550#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0 5551#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT_MASK 0x2 5552#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1 5553#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_MASK 0x4 5554#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT__SHIFT 0x2 5555#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xffffff80 5556#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7 5557#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff 5558#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 5559#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 5560#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 5561#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x4000000 5562#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a 5563#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 5564#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 5565#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000 5566#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c 5567#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000 5568#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d 5569#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000 5570#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e 5571#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x1 5572#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0 5573#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT_MASK 0x2 5574#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1 5575#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_MASK 0x4 5576#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT__SHIFT 0x2 5577#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xffffff80 5578#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7 5579#define PWR_DISP_TIMER_CONTROL2__DISP_TIMER_PULSE_WIDTH_MASK 0x3ff 5580#define PWR_DISP_TIMER_CONTROL2__DISP_TIMER_PULSE_WIDTH__SHIFT 0x0 5581#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_MASK 0xffff 5582#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD__SHIFT 0x0 5583#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT_MASK 0xf0000 5584#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT__SHIFT 0x10 5585#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN_MASK 0x1 5586#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN__SHIFT 0x0 5587#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT_MASK 0x2 5588#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT__SHIFT 0x1 5589#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT_MASK 0x4 5590#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT__SHIFT 0x2 5591#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE_MASK 0x8 5592#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE__SHIFT 0x3 5593#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ_MASK 0x1 5594#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ__SHIFT 0x0 5595#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1 5596#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0 5597#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe 5598#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1 5599#define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000 5600#define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11 5601#define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000 5602#define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16 5603#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff 5604#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0 5605#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff 5606#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0 5607#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1 5608#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0 5609#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe 5610#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1 5611#define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000 5612#define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11 5613#define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000 5614#define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16 5615#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff 5616#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0 5617#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff 5618#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0 5619#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1 5620#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0 5621#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe 5622#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1 5623#define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000 5624#define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11 5625#define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000 5626#define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16 5627#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff 5628#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0 5629#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff 5630#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0 5631#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1 5632#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0 5633#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe 5634#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1 5635#define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000 5636#define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11 5637#define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000 5638#define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16 5639#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff 5640#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0 5641#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff 5642#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0 5643#define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1 5644#define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0 5645#define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe 5646#define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1 5647#define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000 5648#define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11 5649#define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000 5650#define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16 5651#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff 5652#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0 5653#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff 5654#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0 5655#define ROM_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 5656#define ROM_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 5657#define ROM_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 5658#define ROM_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 5659#define ROM_CNTL__SCK_OVERWRITE_MASK 0x2 5660#define ROM_CNTL__SCK_OVERWRITE__SHIFT 0x1 5661#define ROM_CNTL__CLOCK_GATING_EN_MASK 0x4 5662#define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x2 5663#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME_MASK 0xff00 5664#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME__SHIFT 0x8 5665#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME_MASK 0xff0000 5666#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME__SHIFT 0x10 5667#define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0xf000000 5668#define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18 5669#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK_MASK 0xf0000000 5670#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK__SHIFT 0x1c 5671#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0xffffff 5672#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0 5673#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x1000000 5674#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x18 5675#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x2000000 5676#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19 5677#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0xc000000 5678#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a 5679#define ROM_STATUS__ROM_BUSY_MASK 0x1 5680#define ROM_STATUS__ROM_BUSY__SHIFT 0x0 5681#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0xf 5682#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0 5683#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0 5684#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 5685#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000 5686#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e 5687#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000 5688#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f 5689#define ROM_INDEX__ROM_INDEX_MASK 0xffffff 5690#define ROM_INDEX__ROM_INDEX__SHIFT 0x0 5691#define ROM_DATA__ROM_DATA_MASK 0xffffffff 5692#define ROM_DATA__ROM_DATA__SHIFT 0x0 5693#define ROM_START__ROM_START_MASK 0xffffff 5694#define ROM_START__ROM_START__SHIFT 0x0 5695#define ROM_SW_CNTL__DATA_SIZE_MASK 0xffff 5696#define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0 5697#define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x30000 5698#define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10 5699#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x40000 5700#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x12 5701#define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x1 5702#define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0 5703#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0xff 5704#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0 5705#define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xffffff00 5706#define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8 5707#define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xffffffff 5708#define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0 5709#define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xffffffff 5710#define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0 5711#define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xffffffff 5712#define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0 5713#define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xffffffff 5714#define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0 5715#define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xffffffff 5716#define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0 5717#define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xffffffff 5718#define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0 5719#define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xffffffff 5720#define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0 5721#define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xffffffff 5722#define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0 5723#define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xffffffff 5724#define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0 5725#define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xffffffff 5726#define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0 5727#define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xffffffff 5728#define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0 5729#define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xffffffff 5730#define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0 5731#define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xffffffff 5732#define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0 5733#define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xffffffff 5734#define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0 5735#define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xffffffff 5736#define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0 5737#define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xffffffff 5738#define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0 5739#define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xffffffff 5740#define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0 5741#define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xffffffff 5742#define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0 5743#define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xffffffff 5744#define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0 5745#define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xffffffff 5746#define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0 5747#define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xffffffff 5748#define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0 5749#define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xffffffff 5750#define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0 5751#define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xffffffff 5752#define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0 5753#define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xffffffff 5754#define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0 5755#define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xffffffff 5756#define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0 5757#define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xffffffff 5758#define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0 5759#define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xffffffff 5760#define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0 5761#define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xffffffff 5762#define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0 5763#define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xffffffff 5764#define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0 5765#define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xffffffff 5766#define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0 5767#define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xffffffff 5768#define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0 5769#define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xffffffff 5770#define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0 5771#define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xffffffff 5772#define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0 5773#define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xffffffff 5774#define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0 5775#define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xffffffff 5776#define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0 5777#define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xffffffff 5778#define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0 5779#define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xffffffff 5780#define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0 5781#define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xffffffff 5782#define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0 5783#define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xffffffff 5784#define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0 5785#define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xffffffff 5786#define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0 5787#define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xffffffff 5788#define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0 5789#define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xffffffff 5790#define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0 5791#define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xffffffff 5792#define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0 5793#define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xffffffff 5794#define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0 5795#define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xffffffff 5796#define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0 5797#define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xffffffff 5798#define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0 5799#define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xffffffff 5800#define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0 5801#define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xffffffff 5802#define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0 5803#define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xffffffff 5804#define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0 5805#define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xffffffff 5806#define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0 5807#define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xffffffff 5808#define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0 5809#define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xffffffff 5810#define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0 5811#define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xffffffff 5812#define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0 5813#define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xffffffff 5814#define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0 5815#define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xffffffff 5816#define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0 5817#define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xffffffff 5818#define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0 5819#define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xffffffff 5820#define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0 5821#define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xffffffff 5822#define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0 5823#define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xffffffff 5824#define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0 5825#define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xffffffff 5826#define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0 5827#define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xffffffff 5828#define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0 5829#define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xffffffff 5830#define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0 5831#define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xffffffff 5832#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0 5833#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff 5834#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0 5835#define CURRENT_PG_STATUS__VCE_PG_STATUS_MASK 0x00000002 5836#define CURRENT_PG_STATUS__UVD_PG_STATUS_MASK 0x00000004 5837 5838#endif /* SMU_7_1_2_SH_MASK_H */ 5839