1/* 2 * UVD_6_0 Register documentation 3 * 4 * Copyright (C) 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24#ifndef UVD_6_0_SH_MASK_H 25#define UVD_6_0_SH_MASK_H 26 27#define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff 28#define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0 29#define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff 30#define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0 31#define UVD_SEMA_CMD__REQ_CMD_MASK 0xf 32#define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 33#define UVD_SEMA_CMD__WR_PHASE_MASK 0x30 34#define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 35#define UVD_SEMA_CMD__MODE_MASK 0x40 36#define UVD_SEMA_CMD__MODE__SHIFT 0x6 37#define UVD_SEMA_CMD__VMID_EN_MASK 0x80 38#define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7 39#define UVD_SEMA_CMD__VMID_MASK 0xf00 40#define UVD_SEMA_CMD__VMID__SHIFT 0x8 41#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1 42#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 43#define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7ffffffe 44#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 45#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000 46#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f 47#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffff 48#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 49#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xffffffff 50#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 51#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1 52#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 53#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2 54#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 55#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x7 56#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 57#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 58#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 59#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 60#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 61#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 62#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 63#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 64#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 65#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 66#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 67#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 68#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 69#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 70#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 71#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 72#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 73#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x7 74#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 75#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 76#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 77#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 78#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 79#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 80#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 81#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 82#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 83#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 84#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 85#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 86#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 87#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 88#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 89#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 90#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 91#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x7 92#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 93#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 94#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 95#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 96#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 97#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 98#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 99#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 100#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 101#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 102#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 103#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 104#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 105#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 106#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 107#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 108#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 109#define UVD_POWER_STATUS_U__UVD_POWER_STATUS_MASK 0x3 110#define UVD_POWER_STATUS_U__UVD_POWER_STATUS__SHIFT 0x0 111#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff 112#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 113#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff 114#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 115#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff 116#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 117#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff 118#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 119#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff 120#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 121#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff 122#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 123#define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x1 124#define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 125#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x2 126#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 127#define UVD_LMI_EXT40_ADDR__ADDR_MASK 0xff 128#define UVD_LMI_EXT40_ADDR__ADDR__SHIFT 0x0 129#define UVD_LMI_EXT40_ADDR__INDEX_MASK 0x1f0000 130#define UVD_LMI_EXT40_ADDR__INDEX__SHIFT 0x10 131#define UVD_LMI_EXT40_ADDR__WRITE_ADDR_MASK 0x80000000 132#define UVD_LMI_EXT40_ADDR__WRITE_ADDR__SHIFT 0x1f 133#define UVD_CTX_INDEX__INDEX_MASK 0x1ff 134#define UVD_CTX_INDEX__INDEX__SHIFT 0x0 135#define UVD_CTX_DATA__DATA_MASK 0xffffffff 136#define UVD_CTX_DATA__DATA__SHIFT 0x0 137#define UVD_CGC_GATE__SYS_MASK 0x1 138#define UVD_CGC_GATE__SYS__SHIFT 0x0 139#define UVD_CGC_GATE__UDEC_MASK 0x2 140#define UVD_CGC_GATE__UDEC__SHIFT 0x1 141#define UVD_CGC_GATE__MPEG2_MASK 0x4 142#define UVD_CGC_GATE__MPEG2__SHIFT 0x2 143#define UVD_CGC_GATE__REGS_MASK 0x8 144#define UVD_CGC_GATE__REGS__SHIFT 0x3 145#define UVD_CGC_GATE__RBC_MASK 0x10 146#define UVD_CGC_GATE__RBC__SHIFT 0x4 147#define UVD_CGC_GATE__LMI_MC_MASK 0x20 148#define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 149#define UVD_CGC_GATE__LMI_UMC_MASK 0x40 150#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 151#define UVD_CGC_GATE__IDCT_MASK 0x80 152#define UVD_CGC_GATE__IDCT__SHIFT 0x7 153#define UVD_CGC_GATE__MPRD_MASK 0x100 154#define UVD_CGC_GATE__MPRD__SHIFT 0x8 155#define UVD_CGC_GATE__MPC_MASK 0x200 156#define UVD_CGC_GATE__MPC__SHIFT 0x9 157#define UVD_CGC_GATE__LBSI_MASK 0x400 158#define UVD_CGC_GATE__LBSI__SHIFT 0xa 159#define UVD_CGC_GATE__LRBBM_MASK 0x800 160#define UVD_CGC_GATE__LRBBM__SHIFT 0xb 161#define UVD_CGC_GATE__UDEC_RE_MASK 0x1000 162#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc 163#define UVD_CGC_GATE__UDEC_CM_MASK 0x2000 164#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd 165#define UVD_CGC_GATE__UDEC_IT_MASK 0x4000 166#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe 167#define UVD_CGC_GATE__UDEC_DB_MASK 0x8000 168#define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf 169#define UVD_CGC_GATE__UDEC_MP_MASK 0x10000 170#define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 171#define UVD_CGC_GATE__WCB_MASK 0x20000 172#define UVD_CGC_GATE__WCB__SHIFT 0x11 173#define UVD_CGC_GATE__VCPU_MASK 0x40000 174#define UVD_CGC_GATE__VCPU__SHIFT 0x12 175#define UVD_CGC_GATE__SCPU_MASK 0x80000 176#define UVD_CGC_GATE__SCPU__SHIFT 0x13 177#define UVD_CGC_GATE__JPEG_MASK 0x100000 178#define UVD_CGC_GATE__JPEG__SHIFT 0x14 179#define UVD_CGC_GATE__JPEG2_MASK 0x200000 180#define UVD_CGC_GATE__JPEG2__SHIFT 0x15 181#define UVD_CGC_STATUS__SYS_SCLK_MASK 0x1 182#define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 183#define UVD_CGC_STATUS__SYS_DCLK_MASK 0x2 184#define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 185#define UVD_CGC_STATUS__SYS_VCLK_MASK 0x4 186#define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 187#define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x8 188#define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 189#define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x10 190#define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 191#define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x20 192#define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 193#define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x40 194#define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 195#define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x80 196#define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 197#define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x100 198#define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 199#define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200 200#define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 201#define UVD_CGC_STATUS__REGS_VCLK_MASK 0x400 202#define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa 203#define UVD_CGC_STATUS__RBC_SCLK_MASK 0x800 204#define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb 205#define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x1000 206#define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc 207#define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x2000 208#define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd 209#define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x4000 210#define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe 211#define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x8000 212#define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf 213#define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x10000 214#define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 215#define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x20000 216#define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 217#define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x40000 218#define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 219#define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000 220#define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 221#define UVD_CGC_STATUS__MPC_DCLK_MASK 0x100000 222#define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 223#define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x200000 224#define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 225#define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x400000 226#define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 227#define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x800000 228#define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 229#define UVD_CGC_STATUS__WCB_SCLK_MASK 0x1000000 230#define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 231#define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x2000000 232#define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 233#define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x4000000 234#define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a 235#define UVD_CGC_STATUS__SCPU_SCLK_MASK 0x8000000 236#define UVD_CGC_STATUS__SCPU_SCLK__SHIFT 0x1b 237#define UVD_CGC_STATUS__SCPU_VCLK_MASK 0x10000000 238#define UVD_CGC_STATUS__SCPU_VCLK__SHIFT 0x1c 239#define UVD_CGC_STATUS__JPEG_ACTIVE_MASK 0x40000000 240#define UVD_CGC_STATUS__JPEG_ACTIVE__SHIFT 0x1e 241#define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000 242#define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f 243#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1 244#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 245#define UVD_CGC_CTRL__JPEG2_MODE_MASK 0x2 246#define UVD_CGC_CTRL__JPEG2_MODE__SHIFT 0x1 247#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c 248#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 249#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x7c0 250#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 251#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800 252#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb 253#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000 254#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc 255#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x2000 256#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd 257#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x4000 258#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe 259#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x8000 260#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf 261#define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000 262#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 263#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x20000 264#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 265#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x40000 266#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 267#define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000 268#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 269#define UVD_CGC_CTRL__RBC_MODE_MASK 0x100000 270#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 271#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x200000 272#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 273#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x400000 274#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 275#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x800000 276#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 277#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x1000000 278#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 279#define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000 280#define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 281#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x4000000 282#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a 283#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x8000000 284#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b 285#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000 286#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c 287#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000 288#define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d 289#define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000 290#define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e 291#define UVD_CGC_CTRL__JPEG_MODE_MASK 0x80000000 292#define UVD_CGC_CTRL__JPEG_MODE__SHIFT 0x1f 293#define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x1 294#define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0 295#define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x2 296#define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1 297#define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x4 298#define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2 299#define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x8 300#define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3 301#define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x10 302#define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 303#define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x20 304#define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 305#define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x40 306#define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6 307#define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x80 308#define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7 309#define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x100 310#define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8 311#define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x200 312#define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9 313#define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x400 314#define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa 315#define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x800 316#define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb 317#define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x1000 318#define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc 319#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x2000 320#define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd 321#define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x4000 322#define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe 323#define UVD_CGC_UDEC_STATUS__JPEG_VCLK_MASK 0x8000 324#define UVD_CGC_UDEC_STATUS__JPEG_VCLK__SHIFT 0xf 325#define UVD_CGC_UDEC_STATUS__JPEG_SCLK_MASK 0x10000 326#define UVD_CGC_UDEC_STATUS__JPEG_SCLK__SHIFT 0x10 327#define UVD_CGC_UDEC_STATUS__JPEG2_VCLK_MASK 0x20000 328#define UVD_CGC_UDEC_STATUS__JPEG2_VCLK__SHIFT 0x11 329#define UVD_CGC_UDEC_STATUS__JPEG2_SCLK_MASK 0x40000 330#define UVD_CGC_UDEC_STATUS__JPEG2_SCLK__SHIFT 0x12 331#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x1 332#define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 333#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x2 334#define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 335#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x4 336#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 337#define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x8 338#define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 339#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK_MASK 0x70 340#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK__SHIFT 0x4 341#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x80 342#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 343#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100 344#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 345#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x600 346#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 347#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x1800 348#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb 349#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x2000 350#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd 351#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x4000 352#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe 353#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x8000 354#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf 355#define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x10000 356#define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10 357#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x1fe0000 358#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 359#define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x1 360#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 361#define UVD_MASTINT_EN__VCPU_EN_MASK 0x2 362#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 363#define UVD_MASTINT_EN__SYS_EN_MASK 0x4 364#define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 365#define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x7ffff0 366#define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 367#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT_MASK 0xf 368#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT__SHIFT 0x0 369#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT_MASK 0xf0 370#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT__SHIFT 0x4 371#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT_MASK 0xf00 372#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT__SHIFT 0x8 373#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT_MASK 0xf000 374#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT__SHIFT 0xc 375#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT_MASK 0xf0000 376#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT__SHIFT 0x10 377#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT_MASK 0xf00000 378#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x14 379#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT_MASK 0xf000000 380#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT__SHIFT 0x18 381#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT_MASK 0xf0000000 382#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT__SHIFT 0x1c 383#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0xff 384#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 385#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100 386#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 387#define UVD_LMI_CTRL__REQ_MODE_MASK 0x200 388#define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 389#define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x800 390#define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb 391#define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x1000 392#define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc 393#define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x2000 394#define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd 395#define UVD_LMI_CTRL__CRC_RESET_MASK 0x4000 396#define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe 397#define UVD_LMI_CTRL__CRC_SEL_MASK 0xf8000 398#define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf 399#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x100000 400#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14 401#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000 402#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 403#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x400000 404#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 405#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x800000 406#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 407#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x1000000 408#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 409#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x2000000 410#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 411#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x4000000 412#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a 413#define UVD_LMI_CTRL__RFU_MASK 0xf8000000 414#define UVD_LMI_CTRL__RFU__SHIFT 0x1b 415#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x1 416#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 417#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x2 418#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 419#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x4 420#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 421#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x8 422#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 423#define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x10 424#define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4 425#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x20 426#define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5 427#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x40 428#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 429#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x80 430#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7 431#define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x100 432#define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8 433#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x200 434#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 435#define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x400 436#define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa 437#define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x800 438#define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb 439#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x1000 440#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc 441#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x2000 442#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd 443#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x3 444#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 445#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0xc 446#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 447#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x30 448#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4 449#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0xc0 450#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6 451#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x300 452#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8 453#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0xc00 454#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa 455#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x3000 456#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc 457#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0xc000 458#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe 459#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x30000 460#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10 461#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0xc0000 462#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12 463#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0xc00000 464#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16 465#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x3000000 466#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18 467#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0xc000000 468#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a 469#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000 470#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c 471#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xc0000000 472#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e 473#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x3 474#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0 475#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0xc 476#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2 477#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x30 478#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4 479#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0xc0 480#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6 481#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x300 482#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8 483#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0xc00 484#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa 485#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x3000 486#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc 487#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0xc000 488#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe 489#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x30000 490#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10 491#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0xc0000 492#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12 493#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x300000 494#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14 495#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0xc00000 496#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16 497#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x3000000 498#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18 499#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0xc000000 500#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a 501#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000 502#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c 503#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xc0000000 504#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e 505#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x38 506#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3 507#define UVD_MPC_CNTL__PERF_RST_MASK 0x40 508#define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 509#define UVD_MPC_CNTL__DBG_MUX_MASK 0xf00 510#define UVD_MPC_CNTL__DBG_MUX__SHIFT 0x8 511#define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x30000 512#define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10 513#define UVD_MPC_CNTL__URGENT_EN_MASK 0x40000 514#define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12 515#define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f 516#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 517#define UVD_MPC_SET_MUXA0__VARA_1_MASK 0xfc0 518#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 519#define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x3f000 520#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc 521#define UVD_MPC_SET_MUXA0__VARA_3_MASK 0xfc0000 522#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 523#define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000 524#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 525#define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x3f 526#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 527#define UVD_MPC_SET_MUXA1__VARA_6_MASK 0xfc0 528#define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 529#define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000 530#define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc 531#define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x3f 532#define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 533#define UVD_MPC_SET_MUXB0__VARB_1_MASK 0xfc0 534#define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 535#define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x3f000 536#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc 537#define UVD_MPC_SET_MUXB0__VARB_3_MASK 0xfc0000 538#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 539#define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3f000000 540#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 541#define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x3f 542#define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 543#define UVD_MPC_SET_MUXB1__VARB_6_MASK 0xfc0 544#define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 545#define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x3f000 546#define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc 547#define UVD_MPC_SET_MUX__SET_0_MASK 0x7 548#define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 549#define UVD_MPC_SET_MUX__SET_1_MASK 0x38 550#define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 551#define UVD_MPC_SET_MUX__SET_2_MASK 0x1c0 552#define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 553#define UVD_MPC_SET_ALU__FUNCT_MASK 0x7 554#define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 555#define UVD_MPC_SET_ALU__OPERAND_MASK 0xff0 556#define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 557#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x1ffffff 558#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 559#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x1fffff 560#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 561#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x1ffffff 562#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 563#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x1fffff 564#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 565#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x1ffffff 566#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 567#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x1fffff 568#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 569#define UVD_VCPU_CNTL__IRQ_ERR_MASK 0xf 570#define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0 571#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x10 572#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x4 573#define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x20 574#define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5 575#define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x40 576#define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6 577#define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x80 578#define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 579#define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x100 580#define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8 581#define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 582#define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 583#define UVD_VCPU_CNTL__TRCE_EN_MASK 0x400 584#define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa 585#define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x1800 586#define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb 587#define UVD_VCPU_CNTL__DBG_MUX_MASK 0xe000 588#define UVD_VCPU_CNTL__DBG_MUX__SHIFT 0xd 589#define UVD_VCPU_CNTL__JTAG_EN_MASK 0x10000 590#define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10 591#define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x20000 592#define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11 593#define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x40000 594#define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12 595#define UVD_VCPU_CNTL__SUVD_EN_MASK 0x80000 596#define UVD_VCPU_CNTL__SUVD_EN__SHIFT 0x13 597#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0xff00000 598#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 599#define UVD_VCPU_CNTL__CABAC_MB_ACC_MASK 0x10000000 600#define UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT 0x1c 601#define UVD_VCPU_CNTL__WMV9_EN_MASK 0x40000000 602#define UVD_VCPU_CNTL__WMV9_EN__SHIFT 0x1e 603#define UVD_VCPU_CNTL__RE_OFFLOAD_EN_MASK 0x80000000 604#define UVD_VCPU_CNTL__RE_OFFLOAD_EN__SHIFT 0x1f 605#define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x1 606#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 607#define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x2 608#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 609#define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x4 610#define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 611#define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x8 612#define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 613#define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x10 614#define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 615#define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x20 616#define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5 617#define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x40 618#define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 619#define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x80 620#define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 621#define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x100 622#define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 623#define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS_MASK 0x200 624#define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS__SHIFT 0x9 625#define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x400 626#define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa 627#define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x800 628#define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb 629#define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x1000 630#define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc 631#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x2000 632#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd 633#define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x4000 634#define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe 635#define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x8000 636#define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf 637#define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x10000 638#define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 639#define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x20000 640#define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11 641#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x40000 642#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12 643#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x80000 644#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13 645#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x100000 646#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14 647#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x200000 648#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15 649#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x400000 650#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16 651#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x800000 652#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17 653#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x1000000 654#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18 655#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x2000000 656#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19 657#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x4000000 658#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a 659#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x8000000 660#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b 661#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000 662#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c 663#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000 664#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d 665#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000 666#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e 667#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000 668#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f 669#define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0xf 670#define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0 671#define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x7ffff0 672#define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 673#define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0xf 674#define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0 675#define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x7ffff0 676#define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 677#define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x7ffff0 678#define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 679#define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x1f 680#define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 681#define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x1f00 682#define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 683#define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x10000 684#define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 685#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x100000 686#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 687#define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x1000000 688#define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 689#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000 690#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c 691#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xffffffff 692#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 693#define UVD_STATUS__RBC_BUSY_MASK 0x1 694#define UVD_STATUS__RBC_BUSY__SHIFT 0x0 695#define UVD_STATUS__VCPU_REPORT_MASK 0xfe 696#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 697#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x1 698#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 699#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x2 700#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 701#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x4 702#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 703#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x8 704#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 705#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x1 706#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 707#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x1ffffe 708#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 709#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 710#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 711#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x1 712#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 713#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x1ffffe 714#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 715#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 716#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 717#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x1 718#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 719#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x1ffffe 720#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 721#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 722#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 723#define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xffffffff 724#define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 725#define UVD_SUVD_CGC_GATE__SRE_MASK 0x1 726#define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0 727#define UVD_SUVD_CGC_GATE__SIT_MASK 0x2 728#define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1 729#define UVD_SUVD_CGC_GATE__SMP_MASK 0x4 730#define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2 731#define UVD_SUVD_CGC_GATE__SCM_MASK 0x8 732#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3 733#define UVD_SUVD_CGC_GATE__SDB_MASK 0x10 734#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4 735#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x20 736#define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 737#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x40 738#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 739#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x80 740#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 741#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x100 742#define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 743#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x200 744#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 745#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x400 746#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 747#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x800 748#define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 749#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x1000 750#define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 751#define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x1 752#define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0 753#define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x2 754#define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1 755#define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x4 756#define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2 757#define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x8 758#define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3 759#define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x10 760#define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4 761#define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x20 762#define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5 763#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x40 764#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6 765#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x80 766#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7 767#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x100 768#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8 769#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x200 770#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9 771#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x400 772#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa 773#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x800 774#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb 775#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x1000 776#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc 777#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x2000 778#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd 779#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x1 780#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 781#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x2 782#define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 783#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x4 784#define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 785#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x8 786#define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 787#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x10 788#define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 789#define UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID_MASK 0xf 790#define UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID__SHIFT 0x0 791#define UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID_MASK 0xf0 792#define UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID__SHIFT 0x4 793#define UVD_LMI_VMID_INTERNAL__DPB_VMID_MASK 0xf00 794#define UVD_LMI_VMID_INTERNAL__DPB_VMID__SHIFT 0x8 795#define UVD_LMI_VMID_INTERNAL__DBW_VMID_MASK 0xf000 796#define UVD_LMI_VMID_INTERNAL__DBW_VMID__SHIFT 0xc 797#define UVD_LMI_VMID_INTERNAL__LBSI_VMID_MASK 0xf0000 798#define UVD_LMI_VMID_INTERNAL__LBSI_VMID__SHIFT 0x10 799#define UVD_LMI_VMID_INTERNAL__IDCT_VMID_MASK 0xf00000 800#define UVD_LMI_VMID_INTERNAL__IDCT_VMID__SHIFT 0x14 801#define UVD_LMI_VMID_INTERNAL__JPEG_VMID_MASK 0xf000000 802#define UVD_LMI_VMID_INTERNAL__JPEG_VMID__SHIFT 0x18 803#define UVD_LMI_VMID_INTERNAL__JPEG2_VMID_MASK 0xf0000000 804#define UVD_LMI_VMID_INTERNAL__JPEG2_VMID__SHIFT 0x1c 805#define UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID_MASK 0xf 806#define UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID__SHIFT 0x0 807#define UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID_MASK 0xf0 808#define UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID__SHIFT 0x4 809#define UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID_MASK 0xf00 810#define UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID__SHIFT 0x8 811#define UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID_MASK 0xf000 812#define UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID__SHIFT 0xc 813#define UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID_MASK 0xf0000 814#define UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID__SHIFT 0x10 815#define UVD_LMI_VMID_INTERNAL2__MIF_BSD_VMID_MASK 0xf00000 816#define UVD_LMI_VMID_INTERNAL2__MIF_BSD_VMID__SHIFT 0x14 817#define UVD_LMI_VMID_INTERNAL2__MIF_BSP_VMID_MASK 0xf000000 818#define UVD_LMI_VMID_INTERNAL2__MIF_BSP_VMID__SHIFT 0x18 819#define UVD_LMI_VMID_INTERNAL2__VDMA_VMID_MASK 0xf0000000 820#define UVD_LMI_VMID_INTERNAL2__VDMA_VMID__SHIFT 0x1c 821#define UVD_LMI_CACHE_CTRL__IT_EN_MASK 0x1 822#define UVD_LMI_CACHE_CTRL__IT_EN__SHIFT 0x0 823#define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK 0x2 824#define UVD_LMI_CACHE_CTRL__IT_FLUSH__SHIFT 0x1 825#define UVD_LMI_CACHE_CTRL__CM_EN_MASK 0x4 826#define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x2 827#define UVD_LMI_CACHE_CTRL__CM_FLUSH_MASK 0x8 828#define UVD_LMI_CACHE_CTRL__CM_FLUSH__SHIFT 0x3 829#define UVD_LMI_CACHE_CTRL__VCPU_EN_MASK 0x10 830#define UVD_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x4 831#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x20 832#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x5 833#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x3 834#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x0 835#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0xc 836#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x2 837#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT_MASK 0xf 838#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT__SHIFT 0x0 839#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT_MASK 0xf0 840#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT__SHIFT 0x4 841#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT_MASK 0xf00 842#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT__SHIFT 0x8 843#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT_MASK 0xf000 844#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT__SHIFT 0xc 845#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x1 846#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x0 847#define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x2 848#define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x1 849#define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x4 850#define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2 851#define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x8 852#define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x3 853#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x10 854#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x4 855#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x20 856#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5 857#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x40 858#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x6 859#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x80 860#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x7 861#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x100 862#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x8 863#define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x200 864#define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x9 865#define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x400 866#define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa 867#define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x800 868#define UVD_CGC_MEM_CTRL__SCPU_LS_EN__SHIFT 0xb 869#define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x1000 870#define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0xc 871#define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x2000 872#define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0xd 873#define UVD_CGC_MEM_CTRL__JPEG_LS_EN_MASK 0x4000 874#define UVD_CGC_MEM_CTRL__JPEG_LS_EN__SHIFT 0xe 875#define UVD_CGC_MEM_CTRL__JPEG2_LS_EN_MASK 0x8000 876#define UVD_CGC_MEM_CTRL__JPEG2_LS_EN__SHIFT 0xf 877#define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0xf0000 878#define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 879#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0xf00000 880#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 881#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x1 882#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0 883#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x2 884#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1 885#define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x1c 886#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2 887#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID_MASK 0xf 888#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID__SHIFT 0x0 889#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID_MASK 0xf0 890#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID__SHIFT 0x4 891#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID_MASK 0xf00 892#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID__SHIFT 0x8 893#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID_MASK 0xf000 894#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID__SHIFT 0xc 895#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK 0xff 896#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR__SHIFT 0x0 897#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x100 898#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN__SHIFT 0x8 899#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK 0x200 900#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP__SHIFT 0x9 901#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK 0x400 902#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT__SHIFT 0xa 903#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x800 904#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT__SHIFT 0xb 905#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK 0x1000 906#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE__SHIFT 0xc 907#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ_MASK 0x2000 908#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ__SHIFT 0xd 909#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR_MASK 0xf0000000 910#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR__SHIFT 0x1c 911#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE_MASK 0xffffff 912#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE__SHIFT 0x0 913#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE_MASK 0xffffff 914#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE__SHIFT 0x0 915#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x3 916#define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 917#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x4 918#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2 919#define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT_MASK 0x8 920#define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT__SHIFT 0x3 921#define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT_MASK 0x10 922#define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT__SHIFT 0x4 923#define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT_MASK 0x20 924#define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT__SHIFT 0x5 925#define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE_MASK 0xc0 926#define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE__SHIFT 0x6 927#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x100 928#define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8 929#define UVD_POWER_STATUS__PAUSE_DPG_REQ_MASK 0x200 930#define UVD_POWER_STATUS__PAUSE_DPG_REQ__SHIFT 0x9 931#define UVD_POWER_STATUS__PAUSE_DPG_ACK_MASK 0x400 932#define UVD_POWER_STATUS__PAUSE_DPG_ACK__SHIFT 0xa 933#define UVD_PGFSM_READ_TILE3__UVD_PGFSM_READ_TILE3_VALUE_MASK 0xffffff 934#define UVD_PGFSM_READ_TILE3__UVD_PGFSM_READ_TILE3_VALUE__SHIFT 0x0 935#define UVD_PGFSM_READ_TILE4__UVD_PGFSM_READ_TILE4_VALUE_MASK 0xffffff 936#define UVD_PGFSM_READ_TILE4__UVD_PGFSM_READ_TILE4_VALUE__SHIFT 0x0 937#define UVD_PGFSM_READ_TILE5__UVD_PGFSM_READ_TILE5_VALUE_MASK 0xffffff 938#define UVD_PGFSM_READ_TILE5__UVD_PGFSM_READ_TILE5_VALUE__SHIFT 0x0 939#define UVD_PGFSM_READ_TILE6__UVD_PGFSM_READ_TILE6_VALUE_MASK 0xffffff 940#define UVD_PGFSM_READ_TILE6__UVD_PGFSM_READ_TILE6_VALUE__SHIFT 0x0 941#define UVD_PGFSM_READ_TILE7__UVD_PGFSM_READ_TILE7_VALUE_MASK 0xffffff 942#define UVD_PGFSM_READ_TILE7__UVD_PGFSM_READ_TILE7_VALUE__SHIFT 0x0 943#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES_MASK 0x7 944#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 945#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 946#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 947#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 948#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 949#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 950#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 951#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 952#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 953#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 954#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 955#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 956#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 957#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 958#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 959#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 960#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 961#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES_MASK 0x7 962#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 963#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 964#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 965#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 966#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 967#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 968#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 969#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 970#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 971#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 972#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 973#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 974#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 975#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 976#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 977#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 978#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 979#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES_MASK 0x7 980#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 981#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 982#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 983#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 984#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 985#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 986#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 987#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 988#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 989#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 990#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 991#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 992#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 993#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 994#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 995#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 996#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 997#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_PIPES_MASK 0x7 998#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 999#define UVD_MIF_SCLR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 1000#define UVD_MIF_SCLR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
1001#define UVD_MIF_SCLR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 1002#define UVD_MIF_SCLR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 1003#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 1004#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 1005#define UVD_MIF_SCLR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 1006#define UVD_MIF_SCLR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 1007#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 1008#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 1009#define UVD_MIF_SCLR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 1010#define UVD_MIF_SCLR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 1011#define UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 1012#define UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 1013#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 1014#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 1015#define UVD_JPEG_ADDR_CONFIG__NUM_PIPES_MASK 0x7 1016#define UVD_JPEG_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 1017#define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 1018#define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 1019#define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 1020#define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 1021#define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 1022#define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 1023#define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 1024#define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 1025#define UVD_JPEG_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 1026#define UVD_JPEG_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 1027#define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 1028#define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 1029#define UVD_JPEG_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 1030#define UVD_JPEG_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 1031#define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 1032#define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 1033 1034#endif /* UVD_6_0_SH_MASK_H */ 1035