LXR linux/drivers/gpu/drm/amd/include/atomfirmware.h

   1/****************************************************************************\
   2* 
   3*  File Name      atomfirmware.h
   4*  Project        This is an interface header file between atombios and OS GPU drivers for SoC15 products
   5*
   6*  Description    header file of general definitions for OS nd pre-OS video drivers 
   7*
   8*  Copyright 2014 Advanced Micro Devices, Inc.
   9*
  10* Permission is hereby granted, free of charge, to any person obtaining a copy of this software 
  11* and associated documentation files (the "Software"), to deal in the Software without restriction,
  12* including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so,
  14* subject to the following conditions:
  15*
  16* The above copyright notice and this permission notice shall be included in all copies or substantial
  17* portions of the Software.
  18*
  19* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  25* OTHER DEALINGS IN THE SOFTWARE.
  26*
  27\****************************************************************************/
  28
  29/*IMPORTANT NOTES
  30* If a change in VBIOS/Driver/Tool's interface is only needed for SoC15 and forward products, then the change is only needed in this atomfirmware.h header file.
  31* If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the change is only needed in atombios.h header file.
  32* If a change is needed for both pre and post SoC15 products, then the change has to be made separately and might be differently in both atomfirmware.h and atombios.h.
  33*/
  34
  35#ifndef _ATOMFIRMWARE_H_
  36#define _ATOMFIRMWARE_H_
  37
  38enum  atom_bios_header_version_def{
  39  ATOM_MAJOR_VERSION        =0x0003,
  40  ATOM_MINOR_VERSION        =0x0003,
  41};
  42
  43#ifdef _H2INC
  44  #ifndef uint32_t
  45    typedef unsigned long uint32_t;
  46  #endif
  47
  48  #ifndef uint16_t
  49    typedef unsigned short uint16_t;
  50  #endif
  51
  52  #ifndef uint8_t 
  53    typedef unsigned char uint8_t;
  54  #endif
  55#endif
  56
  57enum atom_crtc_def{
  58  ATOM_CRTC1      =0,
  59  ATOM_CRTC2      =1,
  60  ATOM_CRTC3      =2,
  61  ATOM_CRTC4      =3,
  62  ATOM_CRTC5      =4,
  63  ATOM_CRTC6      =5,
  64  ATOM_CRTC_INVALID  =0xff,
  65};
  66
  67enum atom_ppll_def{
  68  ATOM_PPLL0          =2,
  69  ATOM_GCK_DFS        =8,
  70  ATOM_FCH_CLK        =9,
  71  ATOM_DP_DTO         =11,
  72  ATOM_COMBOPHY_PLL0  =20,
  73  ATOM_COMBOPHY_PLL1  =21,
  74  ATOM_COMBOPHY_PLL2  =22,
  75  ATOM_COMBOPHY_PLL3  =23,
  76  ATOM_COMBOPHY_PLL4  =24,
  77  ATOM_COMBOPHY_PLL5  =25,
  78  ATOM_PPLL_INVALID   =0xff,
  79};
  80
  81// define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSel
  82enum atom_dig_def{
  83  ASIC_INT_DIG1_ENCODER_ID  =0x03,
  84  ASIC_INT_DIG2_ENCODER_ID  =0x09,
  85  ASIC_INT_DIG3_ENCODER_ID  =0x0a,
  86  ASIC_INT_DIG4_ENCODER_ID  =0x0b,
  87  ASIC_INT_DIG5_ENCODER_ID  =0x0c,
  88  ASIC_INT_DIG6_ENCODER_ID  =0x0d,
  89  ASIC_INT_DIG7_ENCODER_ID  =0x0e,
  90};
  91
  92//ucEncoderMode
  93enum atom_encode_mode_def
  94{
  95  ATOM_ENCODER_MODE_DP          =0,
  96  ATOM_ENCODER_MODE_DP_SST      =0,
  97  ATOM_ENCODER_MODE_LVDS        =1,
  98  ATOM_ENCODER_MODE_DVI         =2,
  99  ATOM_ENCODER_MODE_HDMI        =3,
 100  ATOM_ENCODER_MODE_DP_AUDIO    =5,
 101  ATOM_ENCODER_MODE_DP_MST      =5,
 102  ATOM_ENCODER_MODE_CRT         =15,
 103  ATOM_ENCODER_MODE_DVO         =16,
 104};
 105
 106enum atom_encoder_refclk_src_def{
 107  ENCODER_REFCLK_SRC_P1PLL      =0,
 108  ENCODER_REFCLK_SRC_P2PLL      =1,
 109  ENCODER_REFCLK_SRC_P3PLL      =2,
 110  ENCODER_REFCLK_SRC_EXTCLK     =3,
 111  ENCODER_REFCLK_SRC_INVALID    =0xff,
 112};
 113
 114enum atom_scaler_def{
 115  ATOM_SCALER_DISABLE          =0,  /*scaler bypass mode, auto-center & no replication*/
 116  ATOM_SCALER_CENTER           =1,  //For Fudo, it's bypass and auto-center & auto replication
 117  ATOM_SCALER_EXPANSION        =2,  /*scaler expansion by 2 tap alpha blending mode*/
 118};
 119
 120enum atom_operation_def{
 121  ATOM_DISABLE             = 0,
 122  ATOM_ENABLE              = 1,
 123  ATOM_INIT                = 7,
 124  ATOM_GET_STATUS          = 8,
 125};
 126
 127enum atom_embedded_display_op_def{
 128  ATOM_LCD_BL_OFF                = 2,
 129  ATOM_LCD_BL_OM                 = 3,
 130  ATOM_LCD_BL_BRIGHTNESS_CONTROL = 4,
 131  ATOM_LCD_SELFTEST_START        = 5,
 132  ATOM_LCD_SELFTEST_STOP         = 6,
 133};
 134
 135enum atom_spread_spectrum_mode{
 136  ATOM_SS_CENTER_OR_DOWN_MODE_MASK  = 0x01,
 137  ATOM_SS_DOWN_SPREAD_MODE          = 0x00,
 138  ATOM_SS_CENTRE_SPREAD_MODE        = 0x01,
 139  ATOM_INT_OR_EXT_SS_MASK           = 0x02,
 140  ATOM_INTERNAL_SS_MASK             = 0x00,
 141  ATOM_EXTERNAL_SS_MASK             = 0x02,
 142};
 143
 144/* define panel bit per color  */
 145enum atom_panel_bit_per_color{
 146  PANEL_BPC_UNDEFINE     =0x00,
 147  PANEL_6BIT_PER_COLOR   =0x01,
 148  PANEL_8BIT_PER_COLOR   =0x02,
 149  PANEL_10BIT_PER_COLOR  =0x03,
 150  PANEL_12BIT_PER_COLOR  =0x04,
 151  PANEL_16BIT_PER_COLOR  =0x05,
 152};
 153
 154//ucVoltageType
 155enum atom_voltage_type
 156{
 157  VOLTAGE_TYPE_VDDC = 1,
 158  VOLTAGE_TYPE_MVDDC = 2,
 159  VOLTAGE_TYPE_MVDDQ = 3,
 160  VOLTAGE_TYPE_VDDCI = 4,
 161  VOLTAGE_TYPE_VDDGFX = 5,
 162  VOLTAGE_TYPE_PCC = 6,
 163  VOLTAGE_TYPE_MVPP = 7,
 164  VOLTAGE_TYPE_LEDDPM = 8,
 165  VOLTAGE_TYPE_PCC_MVDD = 9,
 166  VOLTAGE_TYPE_PCIE_VDDC = 10,
 167  VOLTAGE_TYPE_PCIE_VDDR = 11,
 168  VOLTAGE_TYPE_GENERIC_I2C_1 = 0x11,
 169  VOLTAGE_TYPE_GENERIC_I2C_2 = 0x12,
 170  VOLTAGE_TYPE_GENERIC_I2C_3 = 0x13,
 171  VOLTAGE_TYPE_GENERIC_I2C_4 = 0x14,
 172  VOLTAGE_TYPE_GENERIC_I2C_5 = 0x15,
 173  VOLTAGE_TYPE_GENERIC_I2C_6 = 0x16,
 174  VOLTAGE_TYPE_GENERIC_I2C_7 = 0x17,
 175  VOLTAGE_TYPE_GENERIC_I2C_8 = 0x18,
 176  VOLTAGE_TYPE_GENERIC_I2C_9 = 0x19,
 177  VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A,
 178};
 179
 180enum atom_dgpu_vram_type {
 181  ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50,
 182  ATOM_DGPU_VRAM_TYPE_HBM2  = 0x60,
 183  ATOM_DGPU_VRAM_TYPE_HBM2E = 0x61,
 184  ATOM_DGPU_VRAM_TYPE_GDDR6 = 0x70,
 185};
 186
 187enum atom_dp_vs_preemph_def{
 188  DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00,
 189  DP_VS_LEVEL1_PREEMPH_LEVEL0 = 0x01,
 190  DP_VS_LEVEL2_PREEMPH_LEVEL0 = 0x02,
 191  DP_VS_LEVEL3_PREEMPH_LEVEL0 = 0x03,
 192  DP_VS_LEVEL0_PREEMPH_LEVEL1 = 0x08,
 193  DP_VS_LEVEL1_PREEMPH_LEVEL1 = 0x09,
 194  DP_VS_LEVEL2_PREEMPH_LEVEL1 = 0x0a,
 195  DP_VS_LEVEL0_PREEMPH_LEVEL2 = 0x10,
 196  DP_VS_LEVEL1_PREEMPH_LEVEL2 = 0x11,
 197  DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18,
 198};
 199
 200#define BIOS_ATOM_PREFIX   "ATOMBIOS"
 201#define BIOS_VERSION_PREFIX  "ATOMBIOSBK-AMD"
 202#define BIOS_STRING_LENGTH 43
 203
 204/*
 205enum atom_string_def{
 206asic_bus_type_pcie_string = "PCI_EXPRESS", 
 207atom_fire_gl_string       = "FGL",
 208atom_bios_string          = "ATOM"
 209};
 210*/
 211
 212#pragma pack(1)                          /* BIOS data must use byte aligment*/
 213
 214enum atombios_image_offset{
 215  OFFSET_TO_ATOM_ROM_HEADER_POINTER          = 0x00000048,
 216  OFFSET_TO_ATOM_ROM_IMAGE_SIZE              = 0x00000002,
 217  OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE       = 0x94,
 218  MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE      = 20,  /*including the terminator 0x0!*/
 219  OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS   = 0x2f,
 220  OFFSET_TO_GET_ATOMBIOS_STRING_START        = 0x6e,
 221  OFFSET_TO_VBIOS_PART_NUMBER                = 0x80,
 222  OFFSET_TO_VBIOS_DATE                       = 0x50,
 223};
 224
 225/****************************************************************************   
 226* Common header for all tables (Data table, Command function).
 227* Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header. 
 228* And the pointer actually points to this header.
 229****************************************************************************/   
 230
 231struct atom_common_table_header
 232{
 233  uint16_t structuresize;
 234  uint8_t  format_revision;   //mainly used for a hw function, when the parser is not backward compatible 
 235  uint8_t  content_revision;  //change it when a data table has a structure change, or a hw function has a input/output parameter change                                
 236};
 237
 238/****************************************************************************  
 239* Structure stores the ROM header.
 240****************************************************************************/   
 241struct atom_rom_header_v2_2
 242{
 243  struct atom_common_table_header table_header;
 244  uint8_t  atom_bios_string[4];        //enum atom_string_def atom_bios_string;     //Signature to distinguish between Atombios and non-atombios, 
 245  uint16_t bios_segment_address;
 246  uint16_t protectedmodeoffset;
 247  uint16_t configfilenameoffset;
 248  uint16_t crc_block_offset;
 249  uint16_t vbios_bootupmessageoffset;
 250  uint16_t int10_offset;
 251  uint16_t pcibusdevinitcode;
 252  uint16_t iobaseaddress;
 253  uint16_t subsystem_vendor_id;
 254  uint16_t subsystem_id;
 255  uint16_t pci_info_offset;
 256  uint16_t masterhwfunction_offset;      //Offest for SW to get all command function offsets, Don't change the position
 257  uint16_t masterdatatable_offset;       //Offest for SW to get all data table offsets, Don't change the position
 258  uint16_t reserved;
 259  uint32_t pspdirtableoffset;
 260};
 261
 262/*==============================hw function portion======================================================================*/
 263
 264
 265/****************************************************************************   
 266* Structures used in Command.mtb, each function name is not given here since those function could change from time to time
 267* The real functionality of each function is associated with the parameter structure version when defined
 268* For all internal cmd function definitions, please reference to atomstruct.h
 269****************************************************************************/   
 270struct atom_master_list_of_command_functions_v2_1{
 271  uint16_t asic_init;                   //Function
 272  uint16_t cmd_function1;               //used as an internal one
 273  uint16_t cmd_function2;               //used as an internal one
 274  uint16_t cmd_function3;               //used as an internal one
 275  uint16_t digxencodercontrol;          //Function   
 276  uint16_t cmd_function5;               //used as an internal one
 277  uint16_t cmd_function6;               //used as an internal one 
 278  uint16_t cmd_function7;               //used as an internal one
 279  uint16_t cmd_function8;               //used as an internal one
 280  uint16_t cmd_function9;               //used as an internal one
 281  uint16_t setengineclock;              //Function
 282  uint16_t setmemoryclock;              //Function
 283  uint16_t setpixelclock;               //Function
 284  uint16_t enabledisppowergating;       //Function            
 285  uint16_t cmd_function14;              //used as an internal one             
 286  uint16_t cmd_function15;              //used as an internal one
 287  uint16_t cmd_function16;              //used as an internal one
 288  uint16_t cmd_function17;              //used as an internal one
 289  uint16_t cmd_function18;              //used as an internal one
 290  uint16_t cmd_function19;              //used as an internal one 
 291  uint16_t cmd_function20;              //used as an internal one               
 292  uint16_t cmd_function21;              //used as an internal one
 293  uint16_t cmd_function22;              //used as an internal one
 294  uint16_t cmd_function23;              //used as an internal one
 295  uint16_t cmd_function24;              //used as an internal one
 296  uint16_t cmd_function25;              //used as an internal one
 297  uint16_t cmd_function26;              //used as an internal one
 298  uint16_t cmd_function27;              //used as an internal one
 299  uint16_t cmd_function28;              //used as an internal one
 300  uint16_t cmd_function29;              //used as an internal one
 301  uint16_t cmd_function30;              //used as an internal one
 302  uint16_t cmd_function31;              //used as an internal one
 303  uint16_t cmd_function32;              //used as an internal one
 304  uint16_t cmd_function33;              //used as an internal one
 305  uint16_t blankcrtc;                   //Function
 306  uint16_t enablecrtc;                  //Function
 307  uint16_t cmd_function36;              //used as an internal one
 308  uint16_t cmd_function37;              //used as an internal one
 309  uint16_t cmd_function38;              //used as an internal one
 310  uint16_t cmd_function39;              //used as an internal one
 311  uint16_t cmd_function40;              //used as an internal one
 312  uint16_t getsmuclockinfo;             //Function
 313  uint16_t selectcrtc_source;           //Function
 314  uint16_t cmd_function43;              //used as an internal one
 315  uint16_t cmd_function44;              //used as an internal one
 316  uint16_t cmd_function45;              //used as an internal one
 317  uint16_t setdceclock;                 //Function
 318  uint16_t getmemoryclock;              //Function           
 319  uint16_t getengineclock;              //Function           
 320  uint16_t setcrtc_usingdtdtiming;      //Function
 321  uint16_t externalencodercontrol;      //Function 
 322  uint16_t cmd_function51;              //used as an internal one
 323  uint16_t cmd_function52;              //used as an internal one
 324  uint16_t cmd_function53;              //used as an internal one
 325  uint16_t processi2cchanneltransaction;//Function           
 326  uint16_t cmd_function55;              //used as an internal one
 327  uint16_t cmd_function56;              //used as an internal one
 328  uint16_t cmd_function57;              //used as an internal one
 329  uint16_t cmd_function58;              //used as an internal one
 330  uint16_t cmd_function59;              //used as an internal one
 331  uint16_t computegpuclockparam;        //Function         
 332  uint16_t cmd_function61;              //used as an internal one
 333  uint16_t cmd_function62;              //used as an internal one
 334  uint16_t dynamicmemorysettings;       //Function function
 335  uint16_t memorytraining;              //Function function
 336  uint16_t cmd_function65;              //used as an internal one
 337  uint16_t cmd_function66;              //used as an internal one
 338  uint16_t setvoltage;                  //Function
 339  uint16_t cmd_function68;              //used as an internal one
 340  uint16_t readefusevalue;              //Function
 341  uint16_t cmd_function70;              //used as an internal one 
 342  uint16_t cmd_function71;              //used as an internal one
 343  uint16_t cmd_function72;              //used as an internal one
 344  uint16_t cmd_function73;              //used as an internal one
 345  uint16_t cmd_function74;              //used as an internal one
 346  uint16_t cmd_function75;              //used as an internal one
 347  uint16_t dig1transmittercontrol;      //Function
 348  uint16_t cmd_function77;              //used as an internal one
 349  uint16_t processauxchanneltransaction;//Function
 350  uint16_t cmd_function79;              //used as an internal one
 351  uint16_t getvoltageinfo;              //Function
 352};
 353
 354struct atom_master_command_function_v2_1
 355{
 356  struct atom_common_table_header  table_header;
 357  struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions;
 358};
 359
 360/**************************************************************************** 
 361* Structures used in every command function
 362****************************************************************************/   
 363struct atom_function_attribute
 364{
 365  uint16_t  ws_in_bytes:8;            //[7:0]=Size of workspace in Bytes (in multiple of a dword), 
 366  uint16_t  ps_in_bytes:7;            //[14:8]=Size of parameter space in Bytes (multiple of a dword), 
 367  uint16_t  updated_by_util:1;        //[15]=flag to indicate the function is updated by util
 368};
 369
 370
 371/**************************************************************************** 
 372* Common header for all hw functions.
 373* Every function pointed by _master_list_of_hw_function has this common header. 
 374* And the pointer actually points to this header.
 375****************************************************************************/   
 376struct atom_rom_hw_function_header
 377{
 378  struct atom_common_table_header func_header;
 379  struct atom_function_attribute func_attrib;  
 380};
 381
 382
 383/*==============================sw data table portion======================================================================*/
 384/****************************************************************************
 385* Structures used in data.mtb, each data table name is not given here since those data table could change from time to time
 386* The real name of each table is given when its data structure version is defined
 387****************************************************************************/
 388struct atom_master_list_of_data_tables_v2_1{
 389  uint16_t utilitypipeline;               /* Offest for the utility to get parser info,Don't change this position!*/
 390  uint16_t multimedia_info;               
 391  uint16_t smc_dpm_info;
 392  uint16_t sw_datatable3;                 
 393  uint16_t firmwareinfo;                  /* Shared by various SW components */
 394  uint16_t sw_datatable5;
 395  uint16_t lcd_info;                      /* Shared by various SW components */
 396  uint16_t sw_datatable7;
 397  uint16_t smu_info;                 
 398  uint16_t sw_datatable9;
 399  uint16_t sw_datatable10; 
 400  uint16_t vram_usagebyfirmware;          /* Shared by various SW components */
 401  uint16_t gpio_pin_lut;                  /* Shared by various SW components */
 402  uint16_t sw_datatable13; 
 403  uint16_t gfx_info;
 404  uint16_t powerplayinfo;                 /* Shared by various SW components */
 405  uint16_t sw_datatable16;                
 406  uint16_t sw_datatable17;
 407  uint16_t sw_datatable18;
 408  uint16_t sw_datatable19;                
 409  uint16_t sw_datatable20;
 410  uint16_t sw_datatable21;
 411  uint16_t displayobjectinfo;             /* Shared by various SW components */
 412  uint16_t indirectioaccess;                      /* used as an internal one */
 413  uint16_t umc_info;                      /* Shared by various SW components */
 414  uint16_t sw_datatable25;
 415  uint16_t sw_datatable26;
 416  uint16_t dce_info;                      /* Shared by various SW components */
 417  uint16_t vram_info;                     /* Shared by various SW components */
 418  uint16_t sw_datatable29;
 419  uint16_t integratedsysteminfo;          /* Shared by various SW components */
 420  uint16_t asic_profiling_info;           /* Shared by various SW components */
 421  uint16_t voltageobject_info;            /* shared by various SW components */
 422  uint16_t sw_datatable33;
 423  uint16_t sw_datatable34;
 424};
 425
 426
 427struct atom_master_data_table_v2_1
 428{ 
 429  struct atom_common_table_header table_header;
 430  struct atom_master_list_of_data_tables_v2_1 listOfdatatables;
 431};
 432
 433
 434struct atom_dtd_format
 435{
 436  uint16_t  pixclk;
 437  uint16_t  h_active;
 438  uint16_t  h_blanking_time;
 439  uint16_t  v_active;
 440  uint16_t  v_blanking_time;
 441  uint16_t  h_sync_offset;
 442  uint16_t  h_sync_width;
 443  uint16_t  v_sync_offset;
 444  uint16_t  v_syncwidth;
 445  uint16_t  reserved;
 446  uint16_t  reserved0;
 447  uint8_t   h_border;
 448  uint8_t   v_border;
 449  uint16_t  miscinfo;
 450  uint8_t   atom_mode_id;
 451  uint8_t   refreshrate;
 452};
 453
 454/* atom_dtd_format.modemiscinfo defintion */
 455enum atom_dtd_format_modemiscinfo{
 456  ATOM_HSYNC_POLARITY    = 0x0002,
 457  ATOM_VSYNC_POLARITY    = 0x0004,
 458  ATOM_H_REPLICATIONBY2  = 0x0010,
 459  ATOM_V_REPLICATIONBY2  = 0x0020,
 460  ATOM_INTERLACE         = 0x0080,
 461  ATOM_COMPOSITESYNC     = 0x0040,
 462};
 463
 464
 465/* utilitypipeline
 466 * when format_revision==1 && content_revision==1, then this an info table for atomworks to use during debug session, no structure is associated with it.
 467 * the location of it can't change
 468*/
 469
 470
 471/* 
 472  ***************************************************************************
 473    Data Table firmwareinfo  structure
 474  ***************************************************************************
 475*/
 476
 477struct atom_firmware_info_v3_1
 478{
 479  struct atom_common_table_header table_header;
 480  uint32_t firmware_revision;
 481  uint32_t bootup_sclk_in10khz;
 482  uint32_t bootup_mclk_in10khz;
 483  uint32_t firmware_capability;             // enum atombios_firmware_capability
 484  uint32_t main_call_parser_entry;          /* direct address of main parser call in VBIOS binary. */
 485  uint32_t bios_scratch_reg_startaddr;      // 1st bios scratch register dword address 
 486  uint16_t bootup_vddc_mv;
 487  uint16_t bootup_vddci_mv; 
 488  uint16_t bootup_mvddc_mv;
 489  uint16_t bootup_vddgfx_mv;
 490  uint8_t  mem_module_id;       
 491  uint8_t  coolingsolution_id;              /*0: Air cooling; 1: Liquid cooling ... */
 492  uint8_t  reserved1[2];
 493  uint32_t mc_baseaddr_high;
 494  uint32_t mc_baseaddr_low;
 495  uint32_t reserved2[6];
 496};
 497
 498/* Total 32bit cap indication */
 499enum atombios_firmware_capability
 500{
 501        ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001,
 502        ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION  = 0x00000002,
 503        ATOM_FIRMWARE_CAP_WMI_SUPPORT  = 0x00000040,
 504        ATOM_FIRMWARE_CAP_HWEMU_ENABLE  = 0x00000080,
 505        ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x00000100,
 506        ATOM_FIRMWARE_CAP_SRAM_ECC      = 0x00000200,
 507        ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING  = 0x00000400,
 508        ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT = 0x0008000,
 509        ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE = 0x0020000,
 510};
 511
 512enum atom_cooling_solution_id{
 513  AIR_COOLING    = 0x00,
 514  LIQUID_COOLING = 0x01
 515};
 516
 517struct atom_firmware_info_v3_2 {
 518  struct atom_common_table_header table_header;
 519  uint32_t firmware_revision;
 520  uint32_t bootup_sclk_in10khz;
 521  uint32_t bootup_mclk_in10khz;
 522  uint32_t firmware_capability;             // enum atombios_firmware_capability
 523  uint32_t main_call_parser_entry;          /* direct address of main parser call in VBIOS binary. */
 524  uint32_t bios_scratch_reg_startaddr;      // 1st bios scratch register dword address
 525  uint16_t bootup_vddc_mv;
 526  uint16_t bootup_vddci_mv;
 527  uint16_t bootup_mvddc_mv;
 528  uint16_t bootup_vddgfx_mv;
 529  uint8_t  mem_module_id;
 530  uint8_t  coolingsolution_id;              /*0: Air cooling; 1: Liquid cooling ... */
 531  uint8_t  reserved1[2];
 532  uint32_t mc_baseaddr_high;
 533  uint32_t mc_baseaddr_low;
 534  uint8_t  board_i2c_feature_id;            // enum of atom_board_i2c_feature_id_def
 535  uint8_t  board_i2c_feature_gpio_id;       // i2c id find in gpio_lut data table gpio_id
 536  uint8_t  board_i2c_feature_slave_addr;
 537  uint8_t  reserved3;
 538  uint16_t bootup_mvddq_mv;
 539  uint16_t bootup_mvpp_mv;
 540  uint32_t zfbstartaddrin16mb;
 541  uint32_t reserved2[3];
 542};
 543
 544struct atom_firmware_info_v3_3
 545{
 546  struct atom_common_table_header table_header;
 547  uint32_t firmware_revision;
 548  uint32_t bootup_sclk_in10khz;
 549  uint32_t bootup_mclk_in10khz;
 550  uint32_t firmware_capability;             // enum atombios_firmware_capability
 551  uint32_t main_call_parser_entry;          /* direct address of main parser call in VBIOS binary. */
 552  uint32_t bios_scratch_reg_startaddr;      // 1st bios scratch register dword address
 553  uint16_t bootup_vddc_mv;
 554  uint16_t bootup_vddci_mv;
 555  uint16_t bootup_mvddc_mv;
 556  uint16_t bootup_vddgfx_mv;
 557  uint8_t  mem_module_id;
 558  uint8_t  coolingsolution_id;              /*0: Air cooling; 1: Liquid cooling ... */
 559  uint8_t  reserved1[2];
 560  uint32_t mc_baseaddr_high;
 561  uint32_t mc_baseaddr_low;
 562  uint8_t  board_i2c_feature_id;            // enum of atom_board_i2c_feature_id_def
 563  uint8_t  board_i2c_feature_gpio_id;       // i2c id find in gpio_lut data table gpio_id
 564  uint8_t  board_i2c_feature_slave_addr;
 565  uint8_t  reserved3;
 566  uint16_t bootup_mvddq_mv;
 567  uint16_t bootup_mvpp_mv;
 568  uint32_t zfbstartaddrin16mb;
 569  uint32_t pplib_pptable_id;                // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS
 570  uint32_t reserved2[2];
 571};
 572
 573struct atom_firmware_info_v3_4 {
 574        struct atom_common_table_header table_header;
 575        uint32_t firmware_revision;
 576        uint32_t bootup_sclk_in10khz;
 577        uint32_t bootup_mclk_in10khz;
 578        uint32_t firmware_capability;             // enum atombios_firmware_capability
 579        uint32_t main_call_parser_entry;          /* direct address of main parser call in VBIOS binary. */
 580        uint32_t bios_scratch_reg_startaddr;      // 1st bios scratch register dword address
 581        uint16_t bootup_vddc_mv;
 582        uint16_t bootup_vddci_mv;
 583        uint16_t bootup_mvddc_mv;
 584        uint16_t bootup_vddgfx_mv;
 585        uint8_t  mem_module_id;
 586        uint8_t  coolingsolution_id;              /*0: Air cooling; 1: Liquid cooling ... */
 587        uint8_t  reserved1[2];
 588        uint32_t mc_baseaddr_high;
 589        uint32_t mc_baseaddr_low;
 590        uint8_t  board_i2c_feature_id;            // enum of atom_board_i2c_feature_id_def
 591        uint8_t  board_i2c_feature_gpio_id;       // i2c id find in gpio_lut data table gpio_id
 592        uint8_t  board_i2c_feature_slave_addr;
 593        uint8_t  ras_rom_i2c_slave_addr;
 594        uint16_t bootup_mvddq_mv;
 595        uint16_t bootup_mvpp_mv;
 596        uint32_t zfbstartaddrin16mb;
 597        uint32_t pplib_pptable_id;                // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS
 598        uint32_t mvdd_ratio;                      // mvdd_raio = (real mvdd in power rail)*1000/(mvdd_output_from_svi2)
 599        uint16_t hw_bootup_vddgfx_mv;             // hw default vddgfx voltage level decide by board strap
 600        uint16_t hw_bootup_vddc_mv;               // hw default vddc voltage level decide by board strap
 601        uint16_t hw_bootup_mvddc_mv;              // hw default mvddc voltage level decide by board strap
 602        uint16_t hw_bootup_vddci_mv;              // hw default vddci voltage level decide by board strap
 603        uint32_t maco_pwrlimit_mw;                // bomaco mode power limit in unit of m-watt
 604        uint32_t usb_pwrlimit_mw;                 // power limit when USB is enable in unit of m-watt
 605        uint32_t fw_reserved_size_in_kb;          // VBIOS reserved extra fw size in unit of kb.
 606        uint32_t pspbl_init_done_reg_addr;
 607        uint32_t pspbl_init_done_value;
 608        uint32_t pspbl_init_done_check_timeout;   // time out in unit of us when polling pspbl init done
 609        uint32_t reserved[2];
 610};
 611
 612/* 
 613  ***************************************************************************
 614    Data Table lcd_info  structure
 615  ***************************************************************************
 616*/
 617
 618struct lcd_info_v2_1
 619{
 620  struct  atom_common_table_header table_header;
 621  struct  atom_dtd_format  lcd_timing;
 622  uint16_t backlight_pwm;
 623  uint16_t special_handle_cap;
 624  uint16_t panel_misc;
 625  uint16_t lvds_max_slink_pclk;
 626  uint16_t lvds_ss_percentage;
 627  uint16_t lvds_ss_rate_10hz;
 628  uint8_t  pwr_on_digon_to_de;          /*all pwr sequence numbers below are in uint of 4ms*/
 629  uint8_t  pwr_on_de_to_vary_bl;
 630  uint8_t  pwr_down_vary_bloff_to_de;
 631  uint8_t  pwr_down_de_to_digoff;
 632  uint8_t  pwr_off_delay;
 633  uint8_t  pwr_on_vary_bl_to_blon;
 634  uint8_t  pwr_down_bloff_to_vary_bloff;
 635  uint8_t  panel_bpc;
 636  uint8_t  dpcd_edp_config_cap;
 637  uint8_t  dpcd_max_link_rate;
 638  uint8_t  dpcd_max_lane_count;
 639  uint8_t  dpcd_max_downspread;
 640  uint8_t  min_allowed_bl_level;
 641  uint8_t  max_allowed_bl_level;
 642  uint8_t  bootup_bl_level;
 643  uint8_t  dplvdsrxid;
 644  uint32_t reserved1[8];
 645};
 646
 647/* lcd_info_v2_1.panel_misc defintion */
 648enum atom_lcd_info_panel_misc{
 649  ATOM_PANEL_MISC_FPDI            =0x0002,
 650};
 651
 652//uceDPToLVDSRxId
 653enum atom_lcd_info_dptolvds_rx_id
 654{
 655  eDP_TO_LVDS_RX_DISABLE                 = 0x00,       // no eDP->LVDS translator chip 
 656  eDP_TO_LVDS_COMMON_ID                  = 0x01,       // common eDP->LVDS translator chip without AMD SW init
 657  eDP_TO_LVDS_REALTEK_ID                 = 0x02,       // Realtek tansaltor which require AMD SW init
 658};
 659
 660    
 661/* 
 662  ***************************************************************************
 663    Data Table gpio_pin_lut  structure
 664  ***************************************************************************
 665*/
 666
 667struct atom_gpio_pin_assignment
 668{
 669  uint32_t data_a_reg_index;
 670  uint8_t  gpio_bitshift;
 671  uint8_t  gpio_mask_bitshift;
 672  uint8_t  gpio_id;
 673  uint8_t  reserved;
 674};
 675
 676/* atom_gpio_pin_assignment.gpio_id definition */
 677enum atom_gpio_pin_assignment_gpio_id {
 678  I2C_HW_LANE_MUX        =0x0f, /* only valid when bit7=1 */
 679  I2C_HW_ENGINE_ID_MASK  =0x70, /* only valid when bit7=1 */ 
 680  I2C_HW_CAP             =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C pin pair, otherwise, it's an generic GPIO pin */
 681
 682  /* gpio_id pre-define id for multiple usage */
 683  /* GPIO use to control PCIE_VDDC in certain SLT board */
 684  PCIE_VDDC_CONTROL_GPIO_PINID = 56,
 685  /* if PP_AC_DC_SWITCH_GPIO_PINID in Gpio_Pin_LutTable, AC/DC swithing feature is enable */
 686  PP_AC_DC_SWITCH_GPIO_PINID = 60,
 687  /* VDDC_REGULATOR_VRHOT_GPIO_PINID in Gpio_Pin_LutTable, VRHot feature is enable */
 688  VDDC_VRHOT_GPIO_PINID = 61,
 689  /*if VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled */
 690  VDDC_PCC_GPIO_PINID = 62,
 691  /* Only used on certain SLT/PA board to allow utility to cut Efuse. */
 692  EFUSE_CUT_ENABLE_GPIO_PINID = 63,
 693  /* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses  for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= */
 694  DRAM_SELF_REFRESH_GPIO_PINID = 64,
 695  /* Thermal interrupt output->system thermal chip GPIO pin */
 696  THERMAL_INT_OUTPUT_GPIO_PINID =65,
 697};
 698
 699
 700struct atom_gpio_pin_lut_v2_1
 701{
 702  struct  atom_common_table_header  table_header;
 703  /*the real number of this included in the structure is calcualted by using the (whole structure size - the header size)/size of atom_gpio_pin_lut  */
 704  struct  atom_gpio_pin_assignment  gpio_pin[8];
 705};
 706
 707
 708/* 
 709  ***************************************************************************
 710    Data Table vram_usagebyfirmware  structure
 711  ***************************************************************************
 712*/
 713
 714struct vram_usagebyfirmware_v2_1
 715{
 716  struct  atom_common_table_header  table_header;
 717  uint32_t  start_address_in_kb;
 718  uint16_t  used_by_firmware_in_kb;
 719  uint16_t  used_by_driver_in_kb; 
 720};
 721
 722
 723/* 
 724  ***************************************************************************
 725    Data Table displayobjectinfo  structure
 726  ***************************************************************************
 727*/
 728
 729enum atom_object_record_type_id 
 730{
 731  ATOM_I2C_RECORD_TYPE =1,
 732  ATOM_HPD_INT_RECORD_TYPE =2,
 733  ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE =9,
 734  ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE =16,
 735  ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE =17,
 736  ATOM_ENCODER_CAP_RECORD_TYPE=20,
 737  ATOM_BRACKET_LAYOUT_RECORD_TYPE=21,
 738  ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE=22,
 739  ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE=23,
 740  ATOM_RECORD_END_TYPE  =0xFF,
 741};
 742
 743struct atom_common_record_header
 744{
 745  uint8_t record_type;                      //An emun to indicate the record type
 746  uint8_t record_size;                      //The size of the whole record in byte
 747};
 748
 749struct atom_i2c_record
 750{
 751  struct atom_common_record_header record_header;   //record_type = ATOM_I2C_RECORD_TYPE
 752  uint8_t i2c_id; 
 753  uint8_t i2c_slave_addr;                   //The slave address, it's 0 when the record is attached to connector for DDC
 754};
 755
 756struct atom_hpd_int_record
 757{
 758  struct atom_common_record_header record_header;  //record_type = ATOM_HPD_INT_RECORD_TYPE
 759  uint8_t  pin_id;              //Corresponding block in GPIO_PIN_INFO table gives the pin info           
 760  uint8_t  plugin_pin_state;
 761};
 762
 763// Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap
 764enum atom_encoder_caps_def
 765{
 766  ATOM_ENCODER_CAP_RECORD_HBR2                  =0x01,         // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN
 767  ATOM_ENCODER_CAP_RECORD_MST_EN                =0x01,         // from SI, this bit means DP MST is enable or not. 
 768  ATOM_ENCODER_CAP_RECORD_HBR2_EN               =0x02,         // DP1.2 HBR2 setting is qualified and HBR2 can be enabled 
 769  ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN          =0x04,         // HDMI2.0 6Gbps enable or not. 
 770  ATOM_ENCODER_CAP_RECORD_HBR3_EN               =0x08,         // DP1.3 HBR3 is supported by board. 
 771  ATOM_ENCODER_CAP_RECORD_USB_C_TYPE            =0x100,        // the DP connector is a USB-C type.
 772};
 773
 774struct  atom_encoder_caps_record
 775{
 776  struct atom_common_record_header record_header;  //record_type = ATOM_ENCODER_CAP_RECORD_TYPE
 777  uint32_t  encodercaps;
 778};
 779
 780enum atom_connector_caps_def
 781{
 782  ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY         = 0x01,        //a cap bit to indicate that this non-embedded display connector is an internal display
 783  ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL      = 0x02,        //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq 
 784};
 785
 786struct atom_disp_connector_caps_record
 787{
 788  struct atom_common_record_header record_header;
 789  uint32_t connectcaps;                          
 790};
 791
 792//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually
 793struct atom_gpio_pin_control_pair
 794{
 795  uint8_t gpio_id;               // GPIO_ID, find the corresponding ID in GPIO_LUT table
 796  uint8_t gpio_pinstate;         // Pin state showing how to set-up the pin
 797};
 798
 799struct atom_object_gpio_cntl_record
 800{
 801  struct atom_common_record_header record_header;
 802  uint8_t flag;                   // Future expnadibility
 803  uint8_t number_of_pins;         // Number of GPIO pins used to control the object
 804  struct atom_gpio_pin_control_pair gpio[1];              // the real gpio pin pair determined by number of pins ucNumberOfPins
 805};
 806
 807//Definitions for GPIO pin state 
 808enum atom_gpio_pin_control_pinstate_def
 809{
 810  GPIO_PIN_TYPE_INPUT             = 0x00,
 811  GPIO_PIN_TYPE_OUTPUT            = 0x10,
 812  GPIO_PIN_TYPE_HW_CONTROL        = 0x20,
 813
 814//For GPIO_PIN_TYPE_OUTPUT the following is defined 
 815  GPIO_PIN_OUTPUT_STATE_MASK      = 0x01,
 816  GPIO_PIN_OUTPUT_STATE_SHIFT     = 0,
 817  GPIO_PIN_STATE_ACTIVE_LOW       = 0x0,
 818  GPIO_PIN_STATE_ACTIVE_HIGH      = 0x1,
 819};
 820
 821// Indexes to GPIO array in GLSync record 
 822// GLSync record is for Frame Lock/Gen Lock feature.
 823enum atom_glsync_record_gpio_index_def
 824{
 825  ATOM_GPIO_INDEX_GLSYNC_REFCLK    = 0,
 826  ATOM_GPIO_INDEX_GLSYNC_HSYNC     = 1,
 827  ATOM_GPIO_INDEX_GLSYNC_VSYNC     = 2,
 828  ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ  = 3,
 829  ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT  = 4,
 830  ATOM_GPIO_INDEX_GLSYNC_INTERRUPT = 5,
 831  ATOM_GPIO_INDEX_GLSYNC_V_RESET   = 6,
 832  ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL = 7,
 833  ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL  = 8,
 834  ATOM_GPIO_INDEX_GLSYNC_MAX       = 9,
 835};
 836
 837
 838struct atom_connector_hpdpin_lut_record     //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE
 839{
 840  struct atom_common_record_header record_header;
 841  uint8_t hpd_pin_map[8];             
 842};
 843
 844struct atom_connector_auxddc_lut_record     //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE
 845{
 846  struct atom_common_record_header record_header;
 847  uint8_t aux_ddc_map[8];
 848};
 849
 850struct atom_connector_forced_tmds_cap_record
 851{
 852  struct atom_common_record_header record_header;
 853  // override TMDS capability on this connector when it operate in TMDS mode.  usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5
 854  uint8_t  maxtmdsclkrate_in2_5mhz;
 855  uint8_t  reserved;
 856};    
 857
 858struct atom_connector_layout_info
 859{
 860  uint16_t connectorobjid;
 861  uint8_t  connector_type;
 862  uint8_t  position;
 863};
 864
 865// define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size
 866enum atom_connector_layout_info_connector_type_def
 867{
 868  CONNECTOR_TYPE_DVI_D                 = 1,
 869 
 870  CONNECTOR_TYPE_HDMI                  = 4,
 871  CONNECTOR_TYPE_DISPLAY_PORT          = 5,
 872  CONNECTOR_TYPE_MINI_DISPLAY_PORT     = 6,
 873};
 874
 875struct  atom_bracket_layout_record
 876{
 877  struct atom_common_record_header record_header;
 878  uint8_t bracketlen;
 879  uint8_t bracketwidth;
 880  uint8_t conn_num;
 881  uint8_t reserved;
 882  struct atom_connector_layout_info  conn_info[1];
 883};
 884
 885enum atom_display_device_tag_def{
 886  ATOM_DISPLAY_LCD1_SUPPORT            = 0x0002, //an embedded display is either an LVDS or eDP signal type of display
 887  ATOM_DISPLAY_LCD2_SUPPORT                            = 0x0020, //second edp device tag 0x0020 for backward compability
 888  ATOM_DISPLAY_DFP1_SUPPORT            = 0x0008,
 889  ATOM_DISPLAY_DFP2_SUPPORT            = 0x0080,
 890  ATOM_DISPLAY_DFP3_SUPPORT            = 0x0200,
 891  ATOM_DISPLAY_DFP4_SUPPORT            = 0x0400,
 892  ATOM_DISPLAY_DFP5_SUPPORT            = 0x0800,
 893  ATOM_DISPLAY_DFP6_SUPPORT            = 0x0040,
 894  ATOM_DISPLAY_DFPx_SUPPORT            = 0x0ec8,
 895};
 896
 897struct atom_display_object_path_v2
 898{
 899  uint16_t display_objid;                  //Connector Object ID or Misc Object ID
 900  uint16_t disp_recordoffset;
 901  uint16_t encoderobjid;                   //first encoder closer to the connector, could be either an external or intenal encoder
 902  uint16_t extencoderobjid;                //2nd encoder after the first encoder, from the connector point of view;
 903  uint16_t encoder_recordoffset;
 904  uint16_t extencoder_recordoffset;
 905  uint16_t device_tag;                     //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first 
 906  uint8_t  priority_id;
 907  uint8_t  reserved;
 908};
 909
 910struct display_object_info_table_v1_4
 911{
 912  struct    atom_common_table_header  table_header;
 913  uint16_t  supporteddevices;
 914  uint8_t   number_of_path;
 915  uint8_t   reserved;
 916  struct    atom_display_object_path_v2 display_path[8];   //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path
 917};
 918
 919
 920/* 
 921  ***************************************************************************
 922    Data Table dce_info  structure
 923  ***************************************************************************
 924*/
 925struct atom_display_controller_info_v4_1
 926{
 927  struct  atom_common_table_header  table_header;
 928  uint32_t display_caps;
 929  uint32_t bootup_dispclk_10khz;
 930  uint16_t dce_refclk_10khz;
 931  uint16_t i2c_engine_refclk_10khz;
 932  uint16_t dvi_ss_percentage;       // in unit of 0.001%
 933  uint16_t dvi_ss_rate_10hz;        
 934  uint16_t hdmi_ss_percentage;      // in unit of 0.001%
 935  uint16_t hdmi_ss_rate_10hz;
 936  uint16_t dp_ss_percentage;        // in unit of 0.001%
 937  uint16_t dp_ss_rate_10hz;
 938  uint8_t  dvi_ss_mode;             // enum of atom_spread_spectrum_mode
 939  uint8_t  hdmi_ss_mode;            // enum of atom_spread_spectrum_mode
 940  uint8_t  dp_ss_mode;              // enum of atom_spread_spectrum_mode 
 941  uint8_t  ss_reserved;
 942  uint8_t  hardcode_mode_num;       // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available
 943  uint8_t  reserved1[3];
 944  uint16_t dpphy_refclk_10khz;  
 945  uint16_t reserved2;
 946  uint8_t  dceip_min_ver;
 947  uint8_t  dceip_max_ver;
 948  uint8_t  max_disp_pipe_num;
 949  uint8_t  max_vbios_active_disp_pipe_num;
 950  uint8_t  max_ppll_num;
 951  uint8_t  max_disp_phy_num;
 952  uint8_t  max_aux_pairs;
 953  uint8_t  remotedisplayconfig;
 954  uint8_t  reserved3[8];
 955};
 956
 957struct atom_display_controller_info_v4_2
 958{
 959  struct  atom_common_table_header  table_header;
 960  uint32_t display_caps;            
 961  uint32_t bootup_dispclk_10khz;
 962  uint16_t dce_refclk_10khz;
 963  uint16_t i2c_engine_refclk_10khz;
 964  uint16_t dvi_ss_percentage;       // in unit of 0.001%   
 965  uint16_t dvi_ss_rate_10hz;
 966  uint16_t hdmi_ss_percentage;      // in unit of 0.001%
 967  uint16_t hdmi_ss_rate_10hz;
 968  uint16_t dp_ss_percentage;        // in unit of 0.001%
 969  uint16_t dp_ss_rate_10hz;
 970  uint8_t  dvi_ss_mode;             // enum of atom_spread_spectrum_mode
 971  uint8_t  hdmi_ss_mode;            // enum of atom_spread_spectrum_mode
 972  uint8_t  dp_ss_mode;              // enum of atom_spread_spectrum_mode 
 973  uint8_t  ss_reserved;
 974  uint8_t  dfp_hardcode_mode_num;   // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
 975  uint8_t  dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
 976  uint8_t  vga_hardcode_mode_num;   // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
 977  uint8_t  vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
 978  uint16_t dpphy_refclk_10khz;  
 979  uint16_t reserved2;
 980  uint8_t  dcnip_min_ver;
 981  uint8_t  dcnip_max_ver;
 982  uint8_t  max_disp_pipe_num;
 983  uint8_t  max_vbios_active_disp_pipe_num;
 984  uint8_t  max_ppll_num;
 985  uint8_t  max_disp_phy_num;
 986  uint8_t  max_aux_pairs;
 987  uint8_t  remotedisplayconfig;
 988  uint8_t  reserved3[8];
 989};
 990
 991struct atom_display_controller_info_v4_3
 992{
 993  struct  atom_common_table_header  table_header;
 994  uint32_t display_caps;
 995  uint32_t bootup_dispclk_10khz;
 996  uint16_t dce_refclk_10khz;
 997  uint16_t i2c_engine_refclk_10khz;
 998  uint16_t dvi_ss_percentage;       // in unit of 0.001%
 999  uint16_t dvi_ss_rate_10hz;
1000  uint16_t hdmi_ss_percentage;      // in unit of 0.001%

1001  uint16_t hdmi_ss_rate_10hz;
1002  uint16_t dp_ss_percentage;        // in unit of 0.001%
1003  uint16_t dp_ss_rate_10hz;
1004  uint8_t  dvi_ss_mode;             // enum of atom_spread_spectrum_mode
1005  uint8_t  hdmi_ss_mode;            // enum of atom_spread_spectrum_mode
1006  uint8_t  dp_ss_mode;              // enum of atom_spread_spectrum_mode
1007  uint8_t  ss_reserved;
1008  uint8_t  dfp_hardcode_mode_num;   // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
1009  uint8_t  dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
1010  uint8_t  vga_hardcode_mode_num;   // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1011  uint8_t  vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1012  uint16_t dpphy_refclk_10khz;
1013  uint16_t reserved2;
1014  uint8_t  dcnip_min_ver;
1015  uint8_t  dcnip_max_ver;
1016  uint8_t  max_disp_pipe_num;
1017  uint8_t  max_vbios_active_disp_pipe_num;
1018  uint8_t  max_ppll_num;
1019  uint8_t  max_disp_phy_num;
1020  uint8_t  max_aux_pairs;
1021  uint8_t  remotedisplayconfig;
1022  uint8_t  reserved3[8];
1023};
1024
1025struct atom_display_controller_info_v4_4 {
1026        struct atom_common_table_header table_header;
1027        uint32_t display_caps;
1028        uint32_t bootup_dispclk_10khz;
1029        uint16_t dce_refclk_10khz;
1030        uint16_t i2c_engine_refclk_10khz;
1031        uint16_t dvi_ss_percentage;      // in unit of 0.001%
1032        uint16_t dvi_ss_rate_10hz;
1033        uint16_t hdmi_ss_percentage;     // in unit of 0.001%
1034        uint16_t hdmi_ss_rate_10hz;
1035        uint16_t dp_ss_percentage;       // in unit of 0.001%
1036        uint16_t dp_ss_rate_10hz;
1037        uint8_t dvi_ss_mode;             // enum of atom_spread_spectrum_mode
1038        uint8_t hdmi_ss_mode;            // enum of atom_spread_spectrum_mode
1039        uint8_t dp_ss_mode;              // enum of atom_spread_spectrum_mode
1040        uint8_t ss_reserved;
1041        uint8_t dfp_hardcode_mode_num;   // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
1042        uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
1043        uint8_t vga_hardcode_mode_num;   // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1044        uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1045        uint16_t dpphy_refclk_10khz;
1046        uint16_t hw_chip_id;
1047        uint8_t dcnip_min_ver;
1048        uint8_t dcnip_max_ver;
1049        uint8_t max_disp_pipe_num;
1050        uint8_t max_vbios_active_disp_pipum;
1051        uint8_t max_ppll_num;
1052        uint8_t max_disp_phy_num;
1053        uint8_t max_aux_pairs;
1054        uint8_t remotedisplayconfig;
1055        uint32_t dispclk_pll_vco_freq;
1056        uint32_t dp_ref_clk_freq;
1057        uint32_t max_mclk_chg_lat;       // Worst case blackout duration for a memory clock frequency (p-state) change, units of 100s of ns (0.1 us)
1058        uint32_t max_sr_exit_lat;        // Worst case memory self refresh exit time, units of 100ns of ns (0.1us)
1059        uint32_t max_sr_enter_exit_lat;  // Worst case memory self refresh entry followed by immediate exit time, units of 100ns of ns (0.1us)
1060        uint16_t dc_golden_table_offset; // point of struct of atom_dc_golden_table_vxx
1061        uint16_t dc_golden_table_ver;
1062        uint32_t reserved3[3];
1063};
1064
1065struct atom_dc_golden_table_v1
1066{
1067        uint32_t aux_dphy_rx_control0_val;
1068        uint32_t aux_dphy_tx_control_val;
1069        uint32_t aux_dphy_rx_control1_val;
1070        uint32_t dc_gpio_aux_ctrl_0_val;
1071        uint32_t dc_gpio_aux_ctrl_1_val;
1072        uint32_t dc_gpio_aux_ctrl_2_val;
1073        uint32_t dc_gpio_aux_ctrl_3_val;
1074        uint32_t dc_gpio_aux_ctrl_4_val;
1075        uint32_t dc_gpio_aux_ctrl_5_val;
1076        uint32_t reserved[23];
1077};
1078
1079enum dce_info_caps_def
1080{
1081  // only for VBIOS
1082  DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED  =0x02,      
1083  // only for VBIOS
1084  DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2      =0x04,
1085  // only for VBIOS
1086  DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING   =0x08,
1087  // only for VBIOS
1088  DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE     =0x20,
1089  DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE = 0x40,
1090};
1091
1092/* 
1093  ***************************************************************************
1094    Data Table ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO  structure
1095  ***************************************************************************
1096*/
1097struct atom_ext_display_path
1098{
1099  uint16_t  device_tag;                      //A bit vector to show what devices are supported 
1100  uint16_t  device_acpi_enum;                //16bit device ACPI id. 
1101  uint16_t  connectorobjid;                  //A physical connector for displays to plug in, using object connector definitions
1102  uint8_t   auxddclut_index;                 //An index into external AUX/DDC channel LUT
1103  uint8_t   hpdlut_index;                    //An index into external HPD pin LUT
1104  uint16_t  ext_encoder_objid;               //external encoder object id
1105  uint8_t   channelmapping;                  // if ucChannelMapping=0, using default one to one mapping
1106  uint8_t   chpninvert;                      // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
1107  uint16_t  caps;
1108  uint16_t  reserved; 
1109};
1110
1111//usCaps
1112enum ext_display_path_cap_def {
1113        EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE =           0x0001,
1114        EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN =         0x0002,
1115        EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK =          0x007C,
1116        EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 =      (0x01 << 2), //PI redriver chip
1117        EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT = (0x02 << 2), //TI retimer chip
1118        EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 =    (0x03 << 2)  //Parade DP->HDMI recoverter chip
1119};
1120
1121struct atom_external_display_connection_info
1122{
1123  struct  atom_common_table_header  table_header;
1124  uint8_t                  guid[16];                                  // a GUID is a 16 byte long string
1125  struct atom_ext_display_path path[7];                               // total of fixed 7 entries.
1126  uint8_t                  checksum;                                  // a simple Checksum of the sum of whole structure equal to 0x0. 
1127  uint8_t                  stereopinid;                               // use for eDP panel
1128  uint8_t                  remotedisplayconfig;
1129  uint8_t                  edptolvdsrxid;
1130  uint8_t                  fixdpvoltageswing;                         // usCaps[1]=1, this indicate DP_LANE_SET value
1131  uint8_t                  reserved[3];                               // for potential expansion
1132};
1133
1134/* 
1135  ***************************************************************************
1136    Data Table integratedsysteminfo  structure
1137  ***************************************************************************
1138*/
1139
1140struct atom_camera_dphy_timing_param
1141{
1142  uint8_t  profile_id;       // SENSOR_PROFILES
1143  uint32_t param;
1144};
1145
1146struct atom_camera_dphy_elec_param
1147{
1148  uint16_t param[3];
1149};
1150
1151struct atom_camera_module_info
1152{
1153  uint8_t module_id;                    // 0: Rear, 1: Front right of user, 2: Front left of user
1154  uint8_t module_name[8];
1155  struct atom_camera_dphy_timing_param timingparam[6]; // Exact number is under estimation and confirmation from sensor vendor
1156};
1157
1158struct atom_camera_flashlight_info
1159{
1160  uint8_t flashlight_id;                // 0: Rear, 1: Front
1161  uint8_t name[8];
1162};
1163
1164struct atom_camera_data
1165{
1166  uint32_t versionCode;
1167  struct atom_camera_module_info cameraInfo[3];      // Assuming 3 camera sensors max
1168  struct atom_camera_flashlight_info flashInfo;      // Assuming 1 flashlight max
1169  struct atom_camera_dphy_elec_param dphy_param;
1170  uint32_t crc_val;         // CRC
1171};
1172
1173
1174struct atom_14nm_dpphy_dvihdmi_tuningset
1175{
1176  uint32_t max_symclk_in10khz;
1177  uint8_t encoder_mode;            //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1178  uint8_t phy_sel;                 //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 
1179  uint16_t margindeemph;           //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
1180  uint8_t deemph_6db_4;            //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1181  uint8_t boostadj;                //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj  [20]tx_boost_en  [23:22]tx_binary_ron_code_offset
1182  uint8_t tx_driver_fifty_ohms;    //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms
1183  uint8_t deemph_sel;              //MARGIN_DEEMPH_LANE0.DEEMPH_SEL
1184};
1185
1186struct atom_14nm_dpphy_dp_setting{
1187  uint8_t dp_vs_pemph_level;       //enum of atom_dp_vs_preemph_def
1188  uint16_t margindeemph;           //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
1189  uint8_t deemph_6db_4;            //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1190  uint8_t boostadj;                //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj  [20]tx_boost_en  [23:22]tx_binary_ron_code_offset
1191};
1192
1193struct atom_14nm_dpphy_dp_tuningset{
1194  uint8_t phy_sel;                 // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 
1195  uint8_t version;
1196  uint16_t table_size;             // size of atom_14nm_dpphy_dp_tuningset
1197  uint16_t reserved;
1198  struct atom_14nm_dpphy_dp_setting dptuning[10];
1199};
1200
1201struct atom_14nm_dig_transmitter_info_header_v4_0{  
1202  struct  atom_common_table_header  table_header;  
1203  uint16_t pcie_phy_tmds_hdmi_macro_settings_offset;     // offset of PCIEPhyTMDSHDMIMacroSettingsTbl 
1204  uint16_t uniphy_vs_emph_lookup_table_offset;           // offset of UniphyVSEmphLookUpTbl
1205  uint16_t uniphy_xbar_settings_table_offset;            // offset of UniphyXbarSettingsTbl
1206};
1207
1208struct atom_14nm_combphy_tmds_vs_set
1209{
1210  uint8_t sym_clk;
1211  uint8_t dig_mode;
1212  uint8_t phy_sel;
1213  uint16_t common_mar_deemph_nom__margin_deemph_val;
1214  uint8_t common_seldeemph60__deemph_6db_4_val;
1215  uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ;
1216  uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val;
1217  uint8_t margin_deemph_lane0__deemph_sel_val;         
1218};
1219
1220struct atom_DCN_dpphy_dvihdmi_tuningset
1221{
1222  uint32_t max_symclk_in10khz;
1223  uint8_t  encoder_mode;           //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1224  uint8_t  phy_sel;                //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 
1225  uint8_t  tx_eq_main;             // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)
1226  uint8_t  tx_eq_pre;              // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE)
1227  uint8_t  tx_eq_post;             // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST)
1228  uint8_t  reserved1;
1229  uint8_t  tx_vboost_lvl;          // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL
1230  uint8_t  reserved2;
1231};
1232
1233struct atom_DCN_dpphy_dp_setting{
1234  uint8_t dp_vs_pemph_level;       //enum of atom_dp_vs_preemph_def
1235  uint8_t tx_eq_main;             // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)
1236  uint8_t tx_eq_pre;              // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE)
1237  uint8_t tx_eq_post;             // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST)
1238  uint8_t tx_vboost_lvl;          // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL
1239};
1240
1241struct atom_DCN_dpphy_dp_tuningset{
1242  uint8_t phy_sel;                 // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 
1243  uint8_t version;
1244  uint16_t table_size;             // size of atom_14nm_dpphy_dp_setting
1245  uint16_t reserved;
1246  struct atom_DCN_dpphy_dp_setting dptunings[10];
1247};
1248
1249struct atom_i2c_reg_info {
1250  uint8_t ucI2cRegIndex;
1251  uint8_t ucI2cRegVal;
1252};
1253
1254struct atom_hdmi_retimer_redriver_set {
1255  uint8_t HdmiSlvAddr;
1256  uint8_t HdmiRegNum;
1257  uint8_t Hdmi6GRegNum;
1258  struct atom_i2c_reg_info HdmiRegSetting[9];        //For non 6G Hz use
1259  struct atom_i2c_reg_info Hdmi6GhzRegSetting[3];    //For 6G Hz use.
1260};
1261
1262struct atom_integrated_system_info_v1_11
1263{
1264  struct  atom_common_table_header  table_header;
1265  uint32_t  vbios_misc;                       //enum of atom_system_vbiosmisc_def
1266  uint32_t  gpucapinfo;                       //enum of atom_system_gpucapinf_def   
1267  uint32_t  system_config;                    
1268  uint32_t  cpucapinfo;
1269  uint16_t  gpuclk_ss_percentage;             //unit of 0.001%,   1000 mean 1% 
1270  uint16_t  gpuclk_ss_type;
1271  uint16_t  lvds_ss_percentage;               //unit of 0.001%,   1000 mean 1%
1272  uint16_t  lvds_ss_rate_10hz;
1273  uint16_t  hdmi_ss_percentage;               //unit of 0.001%,   1000 mean 1%
1274  uint16_t  hdmi_ss_rate_10hz;
1275  uint16_t  dvi_ss_percentage;                //unit of 0.001%,   1000 mean 1%
1276  uint16_t  dvi_ss_rate_10hz;
1277  uint16_t  dpphy_override;                   // bit vector, enum of atom_sysinfo_dpphy_override_def
1278  uint16_t  lvds_misc;                        // enum of atom_sys_info_lvds_misc_def
1279  uint16_t  backlight_pwm_hz;                 // pwm frequency in hz
1280  uint8_t   memorytype;                       // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1281  uint8_t   umachannelnumber;                 // number of memory channels
1282  uint8_t   pwr_on_digon_to_de;               /* all pwr sequence numbers below are in uint of 4ms */
1283  uint8_t   pwr_on_de_to_vary_bl;
1284  uint8_t   pwr_down_vary_bloff_to_de;
1285  uint8_t   pwr_down_de_to_digoff;
1286  uint8_t   pwr_off_delay;
1287  uint8_t   pwr_on_vary_bl_to_blon;
1288  uint8_t   pwr_down_bloff_to_vary_bloff;
1289  uint8_t   min_allowed_bl_level;
1290  uint8_t   htc_hyst_limit;
1291  uint8_t   htc_tmp_limit;
1292  uint8_t   reserved1;
1293  uint8_t   reserved2;
1294  struct atom_external_display_connection_info extdispconninfo;
1295  struct atom_14nm_dpphy_dvihdmi_tuningset dvi_tuningset;
1296  struct atom_14nm_dpphy_dvihdmi_tuningset hdmi_tuningset;
1297  struct atom_14nm_dpphy_dvihdmi_tuningset hdmi6g_tuningset;
1298  struct atom_14nm_dpphy_dp_tuningset dp_tuningset;        // rbr 1.62G dp tuning set
1299  struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset;   // HBR3 dp tuning set
1300  struct atom_camera_data  camera_info;
1301  struct atom_hdmi_retimer_redriver_set dp0_retimer_set;   //for DP0
1302  struct atom_hdmi_retimer_redriver_set dp1_retimer_set;   //for DP1
1303  struct atom_hdmi_retimer_redriver_set dp2_retimer_set;   //for DP2
1304  struct atom_hdmi_retimer_redriver_set dp3_retimer_set;   //for DP3
1305  struct atom_14nm_dpphy_dp_tuningset dp_hbr_tuningset;    //hbr 2.7G dp tuning set
1306  struct atom_14nm_dpphy_dp_tuningset dp_hbr2_tuningset;   //hbr2 5.4G dp turnig set
1307  struct atom_14nm_dpphy_dp_tuningset edp_tuningset;       //edp tuning set
1308  uint32_t  reserved[66];
1309};
1310
1311struct atom_integrated_system_info_v1_12
1312{
1313  struct  atom_common_table_header  table_header;
1314  uint32_t  vbios_misc;                       //enum of atom_system_vbiosmisc_def
1315  uint32_t  gpucapinfo;                       //enum of atom_system_gpucapinf_def   
1316  uint32_t  system_config;                    
1317  uint32_t  cpucapinfo;
1318  uint16_t  gpuclk_ss_percentage;             //unit of 0.001%,   1000 mean 1% 
1319  uint16_t  gpuclk_ss_type;
1320  uint16_t  lvds_ss_percentage;               //unit of 0.001%,   1000 mean 1%
1321  uint16_t  lvds_ss_rate_10hz;
1322  uint16_t  hdmi_ss_percentage;               //unit of 0.001%,   1000 mean 1%
1323  uint16_t  hdmi_ss_rate_10hz;
1324  uint16_t  dvi_ss_percentage;                //unit of 0.001%,   1000 mean 1%
1325  uint16_t  dvi_ss_rate_10hz;
1326  uint16_t  dpphy_override;                   // bit vector, enum of atom_sysinfo_dpphy_override_def
1327  uint16_t  lvds_misc;                        // enum of atom_sys_info_lvds_misc_def
1328  uint16_t  backlight_pwm_hz;                 // pwm frequency in hz
1329  uint8_t   memorytype;                       // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1330  uint8_t   umachannelnumber;                 // number of memory channels
1331  uint8_t   pwr_on_digon_to_de;               // all pwr sequence numbers below are in uint of 4ms //
1332  uint8_t   pwr_on_de_to_vary_bl;
1333  uint8_t   pwr_down_vary_bloff_to_de;
1334  uint8_t   pwr_down_de_to_digoff;
1335  uint8_t   pwr_off_delay;
1336  uint8_t   pwr_on_vary_bl_to_blon;
1337  uint8_t   pwr_down_bloff_to_vary_bloff;
1338  uint8_t   min_allowed_bl_level;
1339  uint8_t   htc_hyst_limit;
1340  uint8_t   htc_tmp_limit;
1341  uint8_t   reserved1;
1342  uint8_t   reserved2;
1343  struct atom_external_display_connection_info extdispconninfo;
1344  struct atom_DCN_dpphy_dvihdmi_tuningset  TMDS_tuningset;
1345  struct atom_DCN_dpphy_dvihdmi_tuningset  hdmiCLK5_tuningset;
1346  struct atom_DCN_dpphy_dvihdmi_tuningset  hdmiCLK8_tuningset;
1347  struct atom_DCN_dpphy_dp_tuningset rbr_tuningset;        // rbr 1.62G dp tuning set
1348  struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset;   // HBR3 dp tuning set  
1349  struct atom_camera_data  camera_info;
1350  struct atom_hdmi_retimer_redriver_set dp0_retimer_set;   //for DP0
1351  struct atom_hdmi_retimer_redriver_set dp1_retimer_set;   //for DP1
1352  struct atom_hdmi_retimer_redriver_set dp2_retimer_set;   //for DP2
1353  struct atom_hdmi_retimer_redriver_set dp3_retimer_set;   //for DP3
1354  struct atom_DCN_dpphy_dp_tuningset hbr_tuningset;    //hbr 2.7G dp tuning set
1355  struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset;   //hbr2 5.4G dp turnig set
1356  struct atom_DCN_dpphy_dp_tuningset edp_tunings;       //edp tuning set
1357  struct atom_DCN_dpphy_dvihdmi_tuningset  hdmiCLK6_tuningset;
1358  uint32_t  reserved[63];
1359};
1360
1361struct edp_info_table
1362{
1363        uint16_t edp_backlight_pwm_hz;
1364        uint16_t edp_ss_percentage;
1365        uint16_t edp_ss_rate_10hz;
1366        uint16_t reserved1;
1367        uint32_t reserved2;
1368        uint8_t  edp_pwr_on_off_delay;
1369        uint8_t  edp_pwr_on_vary_bl_to_blon;
1370        uint8_t  edp_pwr_down_bloff_to_vary_bloff;
1371        uint8_t  edp_panel_bpc;
1372        uint8_t  edp_bootup_bl_level;
1373        uint8_t  reserved3[3];
1374        uint32_t reserved4[3];
1375};
1376
1377struct atom_integrated_system_info_v2_1
1378{
1379        struct  atom_common_table_header  table_header;
1380        uint32_t  vbios_misc;                       //enum of atom_system_vbiosmisc_def
1381        uint32_t  gpucapinfo;                       //enum of atom_system_gpucapinf_def
1382        uint32_t  system_config;
1383        uint32_t  cpucapinfo;
1384        uint16_t  gpuclk_ss_percentage;             //unit of 0.001%,   1000 mean 1%
1385        uint16_t  gpuclk_ss_type;
1386        uint16_t  dpphy_override;                   // bit vector, enum of atom_sysinfo_dpphy_override_def
1387        uint8_t   memorytype;                       // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1388        uint8_t   umachannelnumber;                 // number of memory channels
1389        uint8_t   htc_hyst_limit;
1390        uint8_t   htc_tmp_limit;
1391        uint8_t   reserved1;
1392        uint8_t   reserved2;
1393        struct edp_info_table edp1_info;
1394        struct edp_info_table edp2_info;
1395        uint32_t  reserved3[8];
1396        struct atom_external_display_connection_info extdispconninfo;
1397        struct atom_DCN_dpphy_dvihdmi_tuningset  TMDS_tuningset;
1398        struct atom_DCN_dpphy_dvihdmi_tuningset  hdmiCLK5_tuningset; //add clk6
1399        struct atom_DCN_dpphy_dvihdmi_tuningset  hdmiCLK6_tuningset;
1400        struct atom_DCN_dpphy_dvihdmi_tuningset  hdmiCLK8_tuningset;
1401        uint32_t reserved4[6];//reserve 2*sizeof(atom_DCN_dpphy_dvihdmi_tuningset)
1402        struct atom_DCN_dpphy_dp_tuningset rbr_tuningset;        // rbr 1.62G dp tuning set
1403        struct atom_DCN_dpphy_dp_tuningset hbr_tuningset;    //hbr 2.7G dp tuning set
1404        struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset;   //hbr2 5.4G dp turnig set
1405        struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset;   // HBR3 dp tuning set
1406        struct atom_DCN_dpphy_dp_tuningset edp_tunings;       //edp tuning set
1407        uint32_t reserved5[28];//reserve 2*sizeof(atom_DCN_dpphy_dp_tuningset)
1408        struct atom_hdmi_retimer_redriver_set dp0_retimer_set;   //for DP0
1409        struct atom_hdmi_retimer_redriver_set dp1_retimer_set;   //for DP1
1410        struct atom_hdmi_retimer_redriver_set dp2_retimer_set;   //for DP2
1411        struct atom_hdmi_retimer_redriver_set dp3_retimer_set;   //for DP3
1412        uint32_t reserved6[30];// reserve size of(atom_camera_data) for camera_info
1413        uint32_t reserved7[32];
1414
1415};
1416
1417struct atom_n6_display_phy_tuning_set {
1418        uint8_t display_signal_type;
1419        uint8_t phy_sel;
1420        uint8_t preset_level;
1421        uint8_t reserved1;
1422        uint32_t reserved2;
1423        uint32_t speed_upto;
1424        uint8_t tx_vboost_level;
1425        uint8_t tx_vreg_v2i;
1426        uint8_t tx_vregdrv_byp;
1427        uint8_t tx_term_cntl;
1428        uint8_t tx_peak_level;
1429        uint8_t tx_slew_en;
1430        uint8_t tx_eq_pre;
1431        uint8_t tx_eq_main;
1432        uint8_t tx_eq_post;
1433        uint8_t tx_en_inv_pre;
1434        uint8_t tx_en_inv_post;
1435        uint8_t reserved3;
1436        uint32_t reserved4;
1437        uint32_t reserved5;
1438        uint32_t reserved6;
1439};
1440
1441struct atom_display_phy_tuning_info {
1442        struct atom_common_table_header table_header;
1443        struct atom_n6_display_phy_tuning_set disp_phy_tuning[1];
1444};
1445
1446struct atom_integrated_system_info_v2_2
1447{
1448        struct  atom_common_table_header  table_header;
1449        uint32_t  vbios_misc;                       //enum of atom_system_vbiosmisc_def
1450        uint32_t  gpucapinfo;                       //enum of atom_system_gpucapinf_def
1451        uint32_t  system_config;
1452        uint32_t  cpucapinfo;
1453        uint16_t  gpuclk_ss_percentage;             //unit of 0.001%,   1000 mean 1%
1454        uint16_t  gpuclk_ss_type;
1455        uint16_t  dpphy_override;                   // bit vector, enum of atom_sysinfo_dpphy_override_def
1456        uint8_t   memorytype;                       // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1457        uint8_t   umachannelnumber;                 // number of memory channels
1458        uint8_t   htc_hyst_limit;
1459        uint8_t   htc_tmp_limit;
1460        uint8_t   reserved1;
1461        uint8_t   reserved2;
1462        struct edp_info_table edp1_info;
1463        struct edp_info_table edp2_info;
1464        uint32_t  reserved3[8];
1465        struct atom_external_display_connection_info extdispconninfo;
1466
1467        uint32_t  reserved4[189];
1468};
1469
1470// system_config
1471enum atom_system_vbiosmisc_def{
1472  INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01,
1473};
1474
1475
1476// gpucapinfo
1477enum atom_system_gpucapinf_def{
1478  SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS  = 0x10,
1479};
1480
1481//dpphy_override
1482enum atom_sysinfo_dpphy_override_def{
1483  ATOM_ENABLE_DVI_TUNINGSET   = 0x01,
1484  ATOM_ENABLE_HDMI_TUNINGSET  = 0x02,
1485  ATOM_ENABLE_HDMI6G_TUNINGSET  = 0x04,
1486  ATOM_ENABLE_DP_TUNINGSET  = 0x08,
1487  ATOM_ENABLE_DP_HBR3_TUNINGSET  = 0x10,  
1488};
1489
1490//lvds_misc
1491enum atom_sys_info_lvds_misc_def
1492{
1493  SYS_INFO_LVDS_MISC_888_FPDI_MODE                 =0x01,
1494  SYS_INFO_LVDS_MISC_888_BPC_MODE                  =0x04,
1495  SYS_INFO_LVDS_MISC_OVERRIDE_EN                   =0x08,
1496};
1497
1498
1499//memorytype  DMI Type 17 offset 12h - Memory Type
1500enum atom_dmi_t17_mem_type_def{
1501  OtherMemType = 0x01,                                  ///< Assign 01 to Other
1502  UnknownMemType,                                       ///< Assign 02 to Unknown
1503  DramMemType,                                          ///< Assign 03 to DRAM
1504  EdramMemType,                                         ///< Assign 04 to EDRAM
1505  VramMemType,                                          ///< Assign 05 to VRAM
1506  SramMemType,                                          ///< Assign 06 to SRAM
1507  RamMemType,                                           ///< Assign 07 to RAM
1508  RomMemType,                                           ///< Assign 08 to ROM
1509  FlashMemType,                                         ///< Assign 09 to Flash
1510  EepromMemType,                                        ///< Assign 10 to EEPROM
1511  FepromMemType,                                        ///< Assign 11 to FEPROM
1512  EpromMemType,                                         ///< Assign 12 to EPROM
1513  CdramMemType,                                         ///< Assign 13 to CDRAM
1514  ThreeDramMemType,                                     ///< Assign 14 to 3DRAM
1515  SdramMemType,                                         ///< Assign 15 to SDRAM
1516  SgramMemType,                                         ///< Assign 16 to SGRAM
1517  RdramMemType,                                         ///< Assign 17 to RDRAM
1518  DdrMemType,                                           ///< Assign 18 to DDR
1519  Ddr2MemType,                                          ///< Assign 19 to DDR2
1520  Ddr2FbdimmMemType,                                    ///< Assign 20 to DDR2 FB-DIMM
1521  Ddr3MemType = 0x18,                                   ///< Assign 24 to DDR3
1522  Fbd2MemType,                                          ///< Assign 25 to FBD2
1523  Ddr4MemType,                                          ///< Assign 26 to DDR4
1524  LpDdrMemType,                                         ///< Assign 27 to LPDDR
1525  LpDdr2MemType,                                        ///< Assign 28 to LPDDR2
1526  LpDdr3MemType,                                        ///< Assign 29 to LPDDR3
1527  LpDdr4MemType,                                        ///< Assign 30 to LPDDR4
1528  GDdr6MemType,                                         ///< Assign 31 to GDDR6
1529  HbmMemType,                                           ///< Assign 32 to HBM
1530  Hbm2MemType,                                          ///< Assign 33 to HBM2
1531  Ddr5MemType,                                          ///< Assign 34 to DDR5
1532  LpDdr5MemType,                                        ///< Assign 35 to LPDDR5
1533};
1534
1535
1536// this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable 
1537struct atom_fusion_system_info_v4
1538{
1539  struct atom_integrated_system_info_v1_11   sysinfo;           // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition
1540  uint32_t   powerplayinfo[256];                                // Reserve 1024 bytes space for PowerPlayInfoTable
1541}; 
1542
1543
1544/* 
1545  ***************************************************************************
1546    Data Table gfx_info  structure
1547  ***************************************************************************
1548*/
1549
1550struct  atom_gfx_info_v2_2
1551{
1552  struct  atom_common_table_header  table_header;
1553  uint8_t gfxip_min_ver;
1554  uint8_t gfxip_max_ver;
1555  uint8_t max_shader_engines;
1556  uint8_t max_tile_pipes;
1557  uint8_t max_cu_per_sh;
1558  uint8_t max_sh_per_se;
1559  uint8_t max_backends_per_se;
1560  uint8_t max_texture_channel_caches;
1561  uint32_t regaddr_cp_dma_src_addr;
1562  uint32_t regaddr_cp_dma_src_addr_hi;
1563  uint32_t regaddr_cp_dma_dst_addr;
1564  uint32_t regaddr_cp_dma_dst_addr_hi;
1565  uint32_t regaddr_cp_dma_command; 
1566  uint32_t regaddr_cp_status;
1567  uint32_t regaddr_rlc_gpu_clock_32;
1568  uint32_t rlc_gpu_timer_refclk; 
1569};
1570
1571struct  atom_gfx_info_v2_3 {
1572  struct  atom_common_table_header  table_header;
1573  uint8_t gfxip_min_ver;
1574  uint8_t gfxip_max_ver;
1575  uint8_t max_shader_engines;
1576  uint8_t max_tile_pipes;
1577  uint8_t max_cu_per_sh;
1578  uint8_t max_sh_per_se;
1579  uint8_t max_backends_per_se;
1580  uint8_t max_texture_channel_caches;
1581  uint32_t regaddr_cp_dma_src_addr;
1582  uint32_t regaddr_cp_dma_src_addr_hi;
1583  uint32_t regaddr_cp_dma_dst_addr;
1584  uint32_t regaddr_cp_dma_dst_addr_hi;
1585  uint32_t regaddr_cp_dma_command;
1586  uint32_t regaddr_cp_status;
1587  uint32_t regaddr_rlc_gpu_clock_32;
1588  uint32_t rlc_gpu_timer_refclk;
1589  uint8_t active_cu_per_sh;
1590  uint8_t active_rb_per_se;
1591  uint16_t gcgoldenoffset;
1592  uint32_t rm21_sram_vmin_value;
1593};
1594
1595struct  atom_gfx_info_v2_4
1596{
1597  struct  atom_common_table_header  table_header;
1598  uint8_t gfxip_min_ver;
1599  uint8_t gfxip_max_ver;
1600  uint8_t max_shader_engines;
1601  uint8_t reserved;
1602  uint8_t max_cu_per_sh;
1603  uint8_t max_sh_per_se;
1604  uint8_t max_backends_per_se;
1605  uint8_t max_texture_channel_caches;
1606  uint32_t regaddr_cp_dma_src_addr;
1607  uint32_t regaddr_cp_dma_src_addr_hi;
1608  uint32_t regaddr_cp_dma_dst_addr;
1609  uint32_t regaddr_cp_dma_dst_addr_hi;
1610  uint32_t regaddr_cp_dma_command;
1611  uint32_t regaddr_cp_status;
1612  uint32_t regaddr_rlc_gpu_clock_32;
1613  uint32_t rlc_gpu_timer_refclk;
1614  uint8_t active_cu_per_sh;
1615  uint8_t active_rb_per_se;
1616  uint16_t gcgoldenoffset;
1617  uint16_t gc_num_gprs;
1618  uint16_t gc_gsprim_buff_depth;
1619  uint16_t gc_parameter_cache_depth;
1620  uint16_t gc_wave_size;
1621  uint16_t gc_max_waves_per_simd;
1622  uint16_t gc_lds_size;
1623  uint8_t gc_num_max_gs_thds;
1624  uint8_t gc_gs_table_depth;
1625  uint8_t gc_double_offchip_lds_buffer;
1626  uint8_t gc_max_scratch_slots_per_cu;
1627  uint32_t sram_rm_fuses_val;
1628  uint32_t sram_custom_rm_fuses_val;
1629};
1630
1631struct atom_gfx_info_v2_7 {
1632        struct atom_common_table_header table_header;
1633        uint8_t gfxip_min_ver;
1634        uint8_t gfxip_max_ver;
1635        uint8_t max_shader_engines;
1636        uint8_t reserved;
1637        uint8_t max_cu_per_sh;
1638        uint8_t max_sh_per_se;
1639        uint8_t max_backends_per_se;
1640        uint8_t max_texture_channel_caches;
1641        uint32_t regaddr_cp_dma_src_addr;
1642        uint32_t regaddr_cp_dma_src_addr_hi;
1643        uint32_t regaddr_cp_dma_dst_addr;
1644        uint32_t regaddr_cp_dma_dst_addr_hi;
1645        uint32_t regaddr_cp_dma_command;
1646        uint32_t regaddr_cp_status;
1647        uint32_t regaddr_rlc_gpu_clock_32;
1648        uint32_t rlc_gpu_timer_refclk;
1649        uint8_t active_cu_per_sh;
1650        uint8_t active_rb_per_se;
1651        uint16_t gcgoldenoffset;
1652        uint16_t gc_num_gprs;
1653        uint16_t gc_gsprim_buff_depth;
1654        uint16_t gc_parameter_cache_depth;
1655        uint16_t gc_wave_size;
1656        uint16_t gc_max_waves_per_simd;
1657        uint16_t gc_lds_size;
1658        uint8_t gc_num_max_gs_thds;
1659        uint8_t gc_gs_table_depth;
1660        uint8_t gc_double_offchip_lds_buffer;
1661        uint8_t gc_max_scratch_slots_per_cu;
1662        uint32_t sram_rm_fuses_val;
1663        uint32_t sram_custom_rm_fuses_val;
1664        uint8_t cut_cu;
1665        uint8_t active_cu_total;
1666        uint8_t cu_reserved[2];
1667        uint32_t gc_config;
1668        uint8_t inactive_cu_per_se[8];
1669        uint32_t reserved2[6];
1670};
1671
1672/* 
1673  ***************************************************************************
1674    Data Table smu_info  structure
1675  ***************************************************************************
1676*/
1677struct atom_smu_info_v3_1
1678{
1679  struct  atom_common_table_header  table_header;
1680  uint8_t smuip_min_ver;
1681  uint8_t smuip_max_ver;
1682  uint8_t smu_rsd1;
1683  uint8_t gpuclk_ss_mode;           // enum of atom_spread_spectrum_mode
1684  uint16_t sclk_ss_percentage;
1685  uint16_t sclk_ss_rate_10hz;
1686  uint16_t gpuclk_ss_percentage;    // in unit of 0.001%
1687  uint16_t gpuclk_ss_rate_10hz;
1688  uint32_t core_refclk_10khz;
1689  uint8_t  ac_dc_gpio_bit;          // GPIO bit shift in SMU_GPIOPAD_A  configured for AC/DC switching, =0xff means invalid
1690  uint8_t  ac_dc_polarity;          // GPIO polarity for AC/DC switching
1691  uint8_t  vr0hot_gpio_bit;         // GPIO bit shift in SMU_GPIOPAD_A  configured for VR0 HOT event, =0xff means invalid
1692  uint8_t  vr0hot_polarity;         // GPIO polarity for VR0 HOT event
1693  uint8_t  vr1hot_gpio_bit;         // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1694  uint8_t  vr1hot_polarity;         // GPIO polarity for VR1 HOT event 
1695  uint8_t  fw_ctf_gpio_bit;         // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1696  uint8_t  fw_ctf_polarity;         // GPIO polarity for CTF
1697};
1698
1699struct atom_smu_info_v3_2 {
1700  struct   atom_common_table_header  table_header;
1701  uint8_t  smuip_min_ver;
1702  uint8_t  smuip_max_ver;
1703  uint8_t  smu_rsd1;
1704  uint8_t  gpuclk_ss_mode;
1705  uint16_t sclk_ss_percentage;
1706  uint16_t sclk_ss_rate_10hz;
1707  uint16_t gpuclk_ss_percentage;    // in unit of 0.001%
1708  uint16_t gpuclk_ss_rate_10hz;
1709  uint32_t core_refclk_10khz;
1710  uint8_t  ac_dc_gpio_bit;          // GPIO bit shift in SMU_GPIOPAD_A  configured for AC/DC switching, =0xff means invalid
1711  uint8_t  ac_dc_polarity;          // GPIO polarity for AC/DC switching
1712  uint8_t  vr0hot_gpio_bit;         // GPIO bit shift in SMU_GPIOPAD_A  configured for VR0 HOT event, =0xff means invalid
1713  uint8_t  vr0hot_polarity;         // GPIO polarity for VR0 HOT event
1714  uint8_t  vr1hot_gpio_bit;         // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1715  uint8_t  vr1hot_polarity;         // GPIO polarity for VR1 HOT event
1716  uint8_t  fw_ctf_gpio_bit;         // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1717  uint8_t  fw_ctf_polarity;         // GPIO polarity for CTF
1718  uint8_t  pcc_gpio_bit;            // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1719  uint8_t  pcc_gpio_polarity;       // GPIO polarity for CTF
1720  uint16_t smugoldenoffset;
1721  uint32_t gpupll_vco_freq_10khz;
1722  uint32_t bootup_smnclk_10khz;
1723  uint32_t bootup_socclk_10khz;
1724  uint32_t bootup_mp0clk_10khz;
1725  uint32_t bootup_mp1clk_10khz;
1726  uint32_t bootup_lclk_10khz;
1727  uint32_t bootup_dcefclk_10khz;
1728  uint32_t ctf_threshold_override_value;
1729  uint32_t reserved[5];
1730};
1731
1732struct atom_smu_info_v3_3 {
1733  struct   atom_common_table_header  table_header;
1734  uint8_t  smuip_min_ver;
1735  uint8_t  smuip_max_ver;
1736  uint8_t  waflclk_ss_mode;
1737  uint8_t  gpuclk_ss_mode;
1738  uint16_t sclk_ss_percentage;
1739  uint16_t sclk_ss_rate_10hz;
1740  uint16_t gpuclk_ss_percentage;    // in unit of 0.001%
1741  uint16_t gpuclk_ss_rate_10hz;
1742  uint32_t core_refclk_10khz;
1743  uint8_t  ac_dc_gpio_bit;          // GPIO bit shift in SMU_GPIOPAD_A  configured for AC/DC switching, =0xff means invalid
1744  uint8_t  ac_dc_polarity;          // GPIO polarity for AC/DC switching
1745  uint8_t  vr0hot_gpio_bit;         // GPIO bit shift in SMU_GPIOPAD_A  configured for VR0 HOT event, =0xff means invalid
1746  uint8_t  vr0hot_polarity;         // GPIO polarity for VR0 HOT event
1747  uint8_t  vr1hot_gpio_bit;         // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1748  uint8_t  vr1hot_polarity;         // GPIO polarity for VR1 HOT event
1749  uint8_t  fw_ctf_gpio_bit;         // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1750  uint8_t  fw_ctf_polarity;         // GPIO polarity for CTF
1751  uint8_t  pcc_gpio_bit;            // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1752  uint8_t  pcc_gpio_polarity;       // GPIO polarity for CTF
1753  uint16_t smugoldenoffset;
1754  uint32_t gpupll_vco_freq_10khz;
1755  uint32_t bootup_smnclk_10khz;
1756  uint32_t bootup_socclk_10khz;
1757  uint32_t bootup_mp0clk_10khz;
1758  uint32_t bootup_mp1clk_10khz;
1759  uint32_t bootup_lclk_10khz;
1760  uint32_t bootup_dcefclk_10khz;
1761  uint32_t ctf_threshold_override_value;
1762  uint32_t syspll3_0_vco_freq_10khz;
1763  uint32_t syspll3_1_vco_freq_10khz;
1764  uint32_t bootup_fclk_10khz;
1765  uint32_t bootup_waflclk_10khz;
1766  uint32_t smu_info_caps;
1767  uint16_t waflclk_ss_percentage;    // in unit of 0.001%
1768  uint16_t smuinitoffset;
1769  uint32_t reserved;
1770};
1771
1772/*
1773 ***************************************************************************
1774   Data Table smc_dpm_info  structure
1775 ***************************************************************************
1776 */
1777struct atom_smc_dpm_info_v4_1
1778{
1779  struct   atom_common_table_header  table_header;
1780  uint8_t  liquid1_i2c_address;
1781  uint8_t  liquid2_i2c_address;
1782  uint8_t  vr_i2c_address;
1783  uint8_t  plx_i2c_address;
1784
1785  uint8_t  liquid_i2c_linescl;
1786  uint8_t  liquid_i2c_linesda;
1787  uint8_t  vr_i2c_linescl;
1788  uint8_t  vr_i2c_linesda;
1789
1790  uint8_t  plx_i2c_linescl;
1791  uint8_t  plx_i2c_linesda;
1792  uint8_t  vrsensorpresent;
1793  uint8_t  liquidsensorpresent;
1794
1795  uint16_t maxvoltagestepgfx;
1796  uint16_t maxvoltagestepsoc;
1797
1798  uint8_t  vddgfxvrmapping;
1799  uint8_t  vddsocvrmapping;
1800  uint8_t  vddmem0vrmapping;
1801  uint8_t  vddmem1vrmapping;
1802
1803  uint8_t  gfxulvphasesheddingmask;
1804  uint8_t  soculvphasesheddingmask;
1805  uint8_t  padding8_v[2];
1806
1807  uint16_t gfxmaxcurrent;
1808  uint8_t  gfxoffset;
1809  uint8_t  padding_telemetrygfx;
1810
1811  uint16_t socmaxcurrent;
1812  uint8_t  socoffset;
1813  uint8_t  padding_telemetrysoc;
1814
1815  uint16_t mem0maxcurrent;
1816  uint8_t  mem0offset;
1817  uint8_t  padding_telemetrymem0;
1818
1819  uint16_t mem1maxcurrent;
1820  uint8_t  mem1offset;
1821  uint8_t  padding_telemetrymem1;
1822
1823  uint8_t  acdcgpio;
1824  uint8_t  acdcpolarity;
1825  uint8_t  vr0hotgpio;
1826  uint8_t  vr0hotpolarity;
1827
1828  uint8_t  vr1hotgpio;
1829  uint8_t  vr1hotpolarity;
1830  uint8_t  padding1;
1831  uint8_t  padding2;
1832
1833  uint8_t  ledpin0;
1834  uint8_t  ledpin1;
1835  uint8_t  ledpin2;
1836  uint8_t  padding8_4;
1837
1838        uint8_t  pllgfxclkspreadenabled;
1839        uint8_t  pllgfxclkspreadpercent;
1840        uint16_t pllgfxclkspreadfreq;
1841
1842  uint8_t uclkspreadenabled;
1843  uint8_t uclkspreadpercent;
1844  uint16_t uclkspreadfreq;
1845
1846  uint8_t socclkspreadenabled;
1847  uint8_t socclkspreadpercent;
1848  uint16_t socclkspreadfreq;
1849
1850        uint8_t  acggfxclkspreadenabled;
1851        uint8_t  acggfxclkspreadpercent;
1852        uint16_t acggfxclkspreadfreq;
1853
1854        uint8_t Vr2_I2C_address;
1855        uint8_t padding_vr2[3];
1856
1857        uint32_t boardreserved[9];
1858};
1859
1860/*
1861 ***************************************************************************
1862   Data Table smc_dpm_info  structure
1863 ***************************************************************************
1864 */
1865struct atom_smc_dpm_info_v4_3
1866{
1867  struct   atom_common_table_header  table_header;
1868  uint8_t  liquid1_i2c_address;
1869  uint8_t  liquid2_i2c_address;
1870  uint8_t  vr_i2c_address;
1871  uint8_t  plx_i2c_address;
1872
1873  uint8_t  liquid_i2c_linescl;
1874  uint8_t  liquid_i2c_linesda;
1875  uint8_t  vr_i2c_linescl;
1876  uint8_t  vr_i2c_linesda;
1877
1878  uint8_t  plx_i2c_linescl;
1879  uint8_t  plx_i2c_linesda;
1880  uint8_t  vrsensorpresent;
1881  uint8_t  liquidsensorpresent;
1882
1883  uint16_t maxvoltagestepgfx;
1884  uint16_t maxvoltagestepsoc;
1885
1886  uint8_t  vddgfxvrmapping;
1887  uint8_t  vddsocvrmapping;
1888  uint8_t  vddmem0vrmapping;
1889  uint8_t  vddmem1vrmapping;
1890
1891  uint8_t  gfxulvphasesheddingmask;
1892  uint8_t  soculvphasesheddingmask;
1893  uint8_t  externalsensorpresent;
1894  uint8_t  padding8_v;
1895
1896  uint16_t gfxmaxcurrent;
1897  uint8_t  gfxoffset;
1898  uint8_t  padding_telemetrygfx;
1899
1900  uint16_t socmaxcurrent;
1901  uint8_t  socoffset;
1902  uint8_t  padding_telemetrysoc;
1903
1904  uint16_t mem0maxcurrent;
1905  uint8_t  mem0offset;
1906  uint8_t  padding_telemetrymem0;
1907
1908  uint16_t mem1maxcurrent;
1909  uint8_t  mem1offset;
1910  uint8_t  padding_telemetrymem1;
1911
1912  uint8_t  acdcgpio;
1913  uint8_t  acdcpolarity;
1914  uint8_t  vr0hotgpio;
1915  uint8_t  vr0hotpolarity;
1916
1917  uint8_t  vr1hotgpio;
1918  uint8_t  vr1hotpolarity;
1919  uint8_t  padding1;
1920  uint8_t  padding2;
1921
1922  uint8_t  ledpin0;
1923  uint8_t  ledpin1;
1924  uint8_t  ledpin2;
1925  uint8_t  padding8_4;
1926
1927  uint8_t  pllgfxclkspreadenabled;
1928  uint8_t  pllgfxclkspreadpercent;
1929  uint16_t pllgfxclkspreadfreq;
1930
1931  uint8_t uclkspreadenabled;
1932  uint8_t uclkspreadpercent;
1933  uint16_t uclkspreadfreq;
1934
1935  uint8_t fclkspreadenabled;
1936  uint8_t fclkspreadpercent;
1937  uint16_t fclkspreadfreq;
1938
1939  uint8_t fllgfxclkspreadenabled;
1940  uint8_t fllgfxclkspreadpercent;
1941  uint16_t fllgfxclkspreadfreq;
1942
1943  uint32_t boardreserved[10];
1944};
1945
1946struct smudpm_i2ccontrollerconfig_t {
1947  uint32_t  enabled;
1948  uint32_t  slaveaddress;
1949  uint32_t  controllerport;
1950  uint32_t  controllername;
1951  uint32_t  thermalthrottler;
1952  uint32_t  i2cprotocol;
1953  uint32_t  i2cspeed;
1954};
1955
1956struct atom_smc_dpm_info_v4_4
1957{
1958  struct   atom_common_table_header  table_header;
1959  uint32_t  i2c_padding[3];
1960
1961  uint16_t maxvoltagestepgfx;
1962  uint16_t maxvoltagestepsoc;
1963
1964  uint8_t  vddgfxvrmapping;
1965  uint8_t  vddsocvrmapping;
1966  uint8_t  vddmem0vrmapping;
1967  uint8_t  vddmem1vrmapping;
1968
1969  uint8_t  gfxulvphasesheddingmask;
1970  uint8_t  soculvphasesheddingmask;
1971  uint8_t  externalsensorpresent;
1972  uint8_t  padding8_v;
1973
1974  uint16_t gfxmaxcurrent;
1975  uint8_t  gfxoffset;
1976  uint8_t  padding_telemetrygfx;
1977
1978  uint16_t socmaxcurrent;
1979  uint8_t  socoffset;
1980  uint8_t  padding_telemetrysoc;
1981
1982  uint16_t mem0maxcurrent;
1983  uint8_t  mem0offset;
1984  uint8_t  padding_telemetrymem0;
1985
1986  uint16_t mem1maxcurrent;
1987  uint8_t  mem1offset;
1988  uint8_t  padding_telemetrymem1;
1989
1990
1991  uint8_t  acdcgpio;
1992  uint8_t  acdcpolarity;
1993  uint8_t  vr0hotgpio;
1994  uint8_t  vr0hotpolarity;
1995
1996  uint8_t  vr1hotgpio;
1997  uint8_t  vr1hotpolarity;
1998  uint8_t  padding1;
1999  uint8_t  padding2;
2000

2001
2002  uint8_t  ledpin0;
2003  uint8_t  ledpin1;
2004  uint8_t  ledpin2;
2005  uint8_t  padding8_4;
2006
2007
2008  uint8_t  pllgfxclkspreadenabled;
2009  uint8_t  pllgfxclkspreadpercent;
2010  uint16_t pllgfxclkspreadfreq;
2011
2012
2013  uint8_t  uclkspreadenabled;
2014  uint8_t  uclkspreadpercent;
2015  uint16_t uclkspreadfreq;
2016
2017
2018  uint8_t  fclkspreadenabled;
2019  uint8_t  fclkspreadpercent;
2020  uint16_t fclkspreadfreq;
2021
2022
2023  uint8_t  fllgfxclkspreadenabled;
2024  uint8_t  fllgfxclkspreadpercent;
2025  uint16_t fllgfxclkspreadfreq;
2026
2027
2028  struct smudpm_i2ccontrollerconfig_t  i2ccontrollers[7];
2029
2030
2031  uint32_t boardreserved[10];
2032};
2033
2034enum smudpm_v4_5_i2ccontrollername_e{
2035    SMC_V4_5_I2C_CONTROLLER_NAME_VR_GFX = 0,
2036    SMC_V4_5_I2C_CONTROLLER_NAME_VR_SOC,
2037    SMC_V4_5_I2C_CONTROLLER_NAME_VR_VDDCI,
2038    SMC_V4_5_I2C_CONTROLLER_NAME_VR_MVDD,
2039    SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID0,
2040    SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID1,
2041    SMC_V4_5_I2C_CONTROLLER_NAME_PLX,
2042    SMC_V4_5_I2C_CONTROLLER_NAME_SPARE,
2043    SMC_V4_5_I2C_CONTROLLER_NAME_COUNT,
2044};
2045
2046enum smudpm_v4_5_i2ccontrollerthrottler_e{
2047    SMC_V4_5_I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0,
2048    SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_GFX,
2049    SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_SOC,
2050    SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_VDDCI,
2051    SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_MVDD,
2052    SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID0,
2053    SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID1,
2054    SMC_V4_5_I2C_CONTROLLER_THROTTLER_PLX,
2055    SMC_V4_5_I2C_CONTROLLER_THROTTLER_COUNT,
2056};
2057
2058enum smudpm_v4_5_i2ccontrollerprotocol_e{
2059    SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_0,
2060    SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_1,
2061    SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_0,
2062    SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_1,
2063    SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_0,
2064    SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_1,
2065    SMC_V4_5_I2C_CONTROLLER_PROTOCOL_COUNT,
2066};
2067
2068struct smudpm_i2c_controller_config_v2
2069{
2070    uint8_t   Enabled;
2071    uint8_t   Speed;
2072    uint8_t   Padding[2];
2073    uint32_t  SlaveAddress;
2074    uint8_t   ControllerPort;
2075    uint8_t   ControllerName;
2076    uint8_t   ThermalThrotter;
2077    uint8_t   I2cProtocol;
2078};
2079
2080struct atom_smc_dpm_info_v4_5
2081{
2082  struct   atom_common_table_header  table_header;
2083    // SECTION: BOARD PARAMETERS
2084    // I2C Control
2085  struct smudpm_i2c_controller_config_v2  I2cControllers[8];
2086
2087  // SVI2 Board Parameters
2088  uint16_t     MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
2089  uint16_t     MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
2090
2091  uint8_t      VddGfxVrMapping;   // Use VR_MAPPING* bitfields
2092  uint8_t      VddSocVrMapping;   // Use VR_MAPPING* bitfields
2093  uint8_t      VddMem0VrMapping;  // Use VR_MAPPING* bitfields
2094  uint8_t      VddMem1VrMapping;  // Use VR_MAPPING* bitfields
2095
2096  uint8_t      GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2097  uint8_t      SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2098  uint8_t      ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
2099  uint8_t      Padding8_V;
2100
2101  // Telemetry Settings
2102  uint16_t     GfxMaxCurrent;   // in Amps
2103  uint8_t      GfxOffset;       // in Amps
2104  uint8_t      Padding_TelemetryGfx;
2105  uint16_t     SocMaxCurrent;   // in Amps
2106  uint8_t      SocOffset;       // in Amps
2107  uint8_t      Padding_TelemetrySoc;
2108
2109  uint16_t     Mem0MaxCurrent;   // in Amps
2110  uint8_t      Mem0Offset;       // in Amps
2111  uint8_t      Padding_TelemetryMem0;
2112
2113  uint16_t     Mem1MaxCurrent;   // in Amps
2114  uint8_t      Mem1Offset;       // in Amps
2115  uint8_t      Padding_TelemetryMem1;
2116
2117  // GPIO Settings
2118  uint8_t      AcDcGpio;        // GPIO pin configured for AC/DC switching
2119  uint8_t      AcDcPolarity;    // GPIO polarity for AC/DC switching
2120  uint8_t      VR0HotGpio;      // GPIO pin configured for VR0 HOT event
2121  uint8_t      VR0HotPolarity;  // GPIO polarity for VR0 HOT event
2122
2123  uint8_t      VR1HotGpio;      // GPIO pin configured for VR1 HOT event 
2124  uint8_t      VR1HotPolarity;  // GPIO polarity for VR1 HOT event 
2125  uint8_t      GthrGpio;        // GPIO pin configured for GTHR Event
2126  uint8_t      GthrPolarity;    // replace GPIO polarity for GTHR
2127
2128  // LED Display Settings
2129  uint8_t      LedPin0;         // GPIO number for LedPin[0]
2130  uint8_t      LedPin1;         // GPIO number for LedPin[1]
2131  uint8_t      LedPin2;         // GPIO number for LedPin[2]
2132  uint8_t      padding8_4;
2133
2134  // GFXCLK PLL Spread Spectrum
2135  uint8_t      PllGfxclkSpreadEnabled;   // on or off
2136  uint8_t      PllGfxclkSpreadPercent;   // Q4.4
2137  uint16_t     PllGfxclkSpreadFreq;      // kHz
2138
2139  // GFXCLK DFLL Spread Spectrum
2140  uint8_t      DfllGfxclkSpreadEnabled;   // on or off
2141  uint8_t      DfllGfxclkSpreadPercent;   // Q4.4
2142  uint16_t     DfllGfxclkSpreadFreq;      // kHz
2143
2144  // UCLK Spread Spectrum
2145  uint8_t      UclkSpreadEnabled;   // on or off
2146  uint8_t      UclkSpreadPercent;   // Q4.4
2147  uint16_t     UclkSpreadFreq;      // kHz
2148
2149  // SOCCLK Spread Spectrum
2150  uint8_t      SoclkSpreadEnabled;   // on or off
2151  uint8_t      SocclkSpreadPercent;   // Q4.4
2152  uint16_t     SocclkSpreadFreq;      // kHz
2153
2154  // Total board power
2155  uint16_t     TotalBoardPower;     //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
2156  uint16_t     BoardPadding; 
2157
2158  // Mvdd Svi2 Div Ratio Setting
2159  uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16)
2160  
2161  uint32_t     BoardReserved[9];
2162
2163};
2164
2165struct atom_smc_dpm_info_v4_6
2166{
2167  struct   atom_common_table_header  table_header;
2168  // section: board parameters
2169  uint32_t     i2c_padding[3];   // old i2c control are moved to new area
2170
2171  uint16_t     maxvoltagestepgfx; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value.
2172  uint16_t     maxvoltagestepsoc; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value.
2173
2174  uint8_t      vddgfxvrmapping;     // use vr_mapping* bitfields
2175  uint8_t      vddsocvrmapping;     // use vr_mapping* bitfields
2176  uint8_t      vddmemvrmapping;     // use vr_mapping* bitfields
2177  uint8_t      boardvrmapping;      // use vr_mapping* bitfields
2178
2179  uint8_t      gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in ulv mode
2180  uint8_t      externalsensorpresent; // external rdi connected to tmon (aka temp in)
2181  uint8_t      padding8_v[2];
2182
2183  // telemetry settings
2184  uint16_t     gfxmaxcurrent;   // in amps
2185  uint8_t      gfxoffset;       // in amps
2186  uint8_t      padding_telemetrygfx;
2187
2188  uint16_t     socmaxcurrent;   // in amps
2189  uint8_t      socoffset;       // in amps
2190  uint8_t      padding_telemetrysoc;
2191
2192  uint16_t     memmaxcurrent;   // in amps
2193  uint8_t      memoffset;       // in amps
2194  uint8_t      padding_telemetrymem;
2195
2196  uint16_t     boardmaxcurrent;   // in amps
2197  uint8_t      boardoffset;       // in amps
2198  uint8_t      padding_telemetryboardinput;
2199
2200  // gpio settings
2201  uint8_t      vr0hotgpio;      // gpio pin configured for vr0 hot event
2202  uint8_t      vr0hotpolarity;  // gpio polarity for vr0 hot event
2203  uint8_t      vr1hotgpio;      // gpio pin configured for vr1 hot event
2204  uint8_t      vr1hotpolarity;  // gpio polarity for vr1 hot event
2205
2206 // gfxclk pll spread spectrum
2207  uint8_t          pllgfxclkspreadenabled;      // on or off
2208  uint8_t          pllgfxclkspreadpercent;      // q4.4
2209  uint16_t         pllgfxclkspreadfreq;         // khz
2210
2211 // uclk spread spectrum
2212  uint8_t          uclkspreadenabled;   // on or off
2213  uint8_t          uclkspreadpercent;   // q4.4
2214  uint16_t         uclkspreadfreq;         // khz
2215
2216 // fclk spread spectrum
2217  uint8_t          fclkspreadenabled;   // on or off
2218  uint8_t          fclkspreadpercent;   // q4.4
2219  uint16_t         fclkspreadfreq;         // khz
2220
2221
2222  // gfxclk fll spread spectrum
2223  uint8_t      fllgfxclkspreadenabled;   // on or off
2224  uint8_t      fllgfxclkspreadpercent;   // q4.4
2225  uint16_t     fllgfxclkspreadfreq;      // khz
2226
2227  // i2c controller structure
2228  struct smudpm_i2c_controller_config_v2 i2ccontrollers[8];
2229
2230  // memory section
2231  uint32_t       memorychannelenabled; // for dram use only, max 32 channels enabled bit mask.
2232
2233  uint8_t        drambitwidth; // for dram use only.  see dram bit width type defines
2234  uint8_t        paddingmem[3];
2235
2236        // total board power
2237  uint16_t       totalboardpower;         //only needed for tcp estimated case, where tcp = tgp+total board power
2238  uint16_t       boardpadding;
2239
2240        // section: xgmi training
2241  uint8_t        xgmilinkspeed[4];
2242  uint8_t        xgmilinkwidth[4];
2243
2244  uint16_t       xgmifclkfreq[4];
2245  uint16_t       xgmisocvoltage[4];
2246
2247  // reserved
2248  uint32_t   boardreserved[10];
2249};
2250
2251struct atom_smc_dpm_info_v4_7
2252{
2253  struct   atom_common_table_header  table_header;
2254    // SECTION: BOARD PARAMETERS
2255    // I2C Control
2256  struct smudpm_i2c_controller_config_v2  I2cControllers[8];
2257
2258  // SVI2 Board Parameters
2259  uint16_t     MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
2260  uint16_t     MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
2261
2262  uint8_t      VddGfxVrMapping;   // Use VR_MAPPING* bitfields
2263  uint8_t      VddSocVrMapping;   // Use VR_MAPPING* bitfields
2264  uint8_t      VddMem0VrMapping;  // Use VR_MAPPING* bitfields
2265  uint8_t      VddMem1VrMapping;  // Use VR_MAPPING* bitfields
2266
2267  uint8_t      GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2268  uint8_t      SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2269  uint8_t      ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
2270  uint8_t      Padding8_V;
2271
2272  // Telemetry Settings
2273  uint16_t     GfxMaxCurrent;   // in Amps
2274  uint8_t      GfxOffset;       // in Amps
2275  uint8_t      Padding_TelemetryGfx;
2276  uint16_t     SocMaxCurrent;   // in Amps
2277  uint8_t      SocOffset;       // in Amps
2278  uint8_t      Padding_TelemetrySoc;
2279
2280  uint16_t     Mem0MaxCurrent;   // in Amps
2281  uint8_t      Mem0Offset;       // in Amps
2282  uint8_t      Padding_TelemetryMem0;
2283
2284  uint16_t     Mem1MaxCurrent;   // in Amps
2285  uint8_t      Mem1Offset;       // in Amps
2286  uint8_t      Padding_TelemetryMem1;
2287
2288  // GPIO Settings
2289  uint8_t      AcDcGpio;        // GPIO pin configured for AC/DC switching
2290  uint8_t      AcDcPolarity;    // GPIO polarity for AC/DC switching
2291  uint8_t      VR0HotGpio;      // GPIO pin configured for VR0 HOT event
2292  uint8_t      VR0HotPolarity;  // GPIO polarity for VR0 HOT event
2293
2294  uint8_t      VR1HotGpio;      // GPIO pin configured for VR1 HOT event
2295  uint8_t      VR1HotPolarity;  // GPIO polarity for VR1 HOT event
2296  uint8_t      GthrGpio;        // GPIO pin configured for GTHR Event
2297  uint8_t      GthrPolarity;    // replace GPIO polarity for GTHR
2298
2299  // LED Display Settings
2300  uint8_t      LedPin0;         // GPIO number for LedPin[0]
2301  uint8_t      LedPin1;         // GPIO number for LedPin[1]
2302  uint8_t      LedPin2;         // GPIO number for LedPin[2]
2303  uint8_t      padding8_4;
2304
2305  // GFXCLK PLL Spread Spectrum
2306  uint8_t      PllGfxclkSpreadEnabled;   // on or off
2307  uint8_t      PllGfxclkSpreadPercent;   // Q4.4
2308  uint16_t     PllGfxclkSpreadFreq;      // kHz
2309
2310  // GFXCLK DFLL Spread Spectrum
2311  uint8_t      DfllGfxclkSpreadEnabled;   // on or off
2312  uint8_t      DfllGfxclkSpreadPercent;   // Q4.4
2313  uint16_t     DfllGfxclkSpreadFreq;      // kHz
2314
2315  // UCLK Spread Spectrum
2316  uint8_t      UclkSpreadEnabled;   // on or off
2317  uint8_t      UclkSpreadPercent;   // Q4.4
2318  uint16_t     UclkSpreadFreq;      // kHz
2319
2320  // SOCCLK Spread Spectrum
2321  uint8_t      SoclkSpreadEnabled;   // on or off
2322  uint8_t      SocclkSpreadPercent;   // Q4.4
2323  uint16_t     SocclkSpreadFreq;      // kHz
2324
2325  // Total board power
2326  uint16_t     TotalBoardPower;     //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
2327  uint16_t     BoardPadding;
2328
2329  // Mvdd Svi2 Div Ratio Setting
2330  uint32_t     MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16)
2331
2332  // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence
2333  uint8_t      GpioI2cScl;          // Serial Clock
2334  uint8_t      GpioI2cSda;          // Serial Data
2335  uint16_t     GpioPadding;
2336
2337  // Additional LED Display Settings
2338  uint8_t      LedPin3;         // GPIO number for LedPin[3] - PCIE GEN Speed
2339  uint8_t      LedPin4;         // GPIO number for LedPin[4] - PMFW Error Status
2340  uint16_t     LedEnableMask;
2341
2342  // Power Limit Scalars
2343  uint8_t      PowerLimitScalar[4];    //[PPT_THROTTLER_COUNT]
2344
2345  uint8_t      MvddUlvPhaseSheddingMask;
2346  uint8_t      VddciUlvPhaseSheddingMask;
2347  uint8_t      Padding8_Psi1;
2348  uint8_t      Padding8_Psi2;
2349
2350  uint32_t     BoardReserved[5];
2351};
2352
2353struct smudpm_i2c_controller_config_v3
2354{
2355  uint8_t   Enabled;
2356  uint8_t   Speed;
2357  uint8_t   SlaveAddress;
2358  uint8_t   ControllerPort;
2359  uint8_t   ControllerName;
2360  uint8_t   ThermalThrotter;
2361  uint8_t   I2cProtocol;
2362  uint8_t   PaddingConfig;
2363};
2364
2365struct atom_smc_dpm_info_v4_9
2366{
2367  struct   atom_common_table_header  table_header;
2368
2369  //SECTION: Gaming Clocks
2370  //uint32_t     GamingClk[6];
2371
2372  // SECTION: I2C Control
2373  struct smudpm_i2c_controller_config_v3  I2cControllers[16];     
2374
2375  uint8_t      GpioScl;  // GPIO Number for SCL Line, used only for CKSVII2C1
2376  uint8_t      GpioSda;  // GPIO Number for SDA Line, used only for CKSVII2C1
2377  uint8_t      FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off
2378  uint8_t      I2cSpare;
2379
2380  // SECTION: SVI2 Board Parameters
2381  uint8_t      VddGfxVrMapping;   // Use VR_MAPPING* bitfields
2382  uint8_t      VddSocVrMapping;   // Use VR_MAPPING* bitfields
2383  uint8_t      VddMem0VrMapping;  // Use VR_MAPPING* bitfields
2384  uint8_t      VddMem1VrMapping;  // Use VR_MAPPING* bitfields
2385
2386  uint8_t      GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2387  uint8_t      SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2388  uint8_t      VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2389  uint8_t      MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2390
2391  // SECTION: Telemetry Settings
2392  uint16_t     GfxMaxCurrent;   // in Amps
2393  uint8_t      GfxOffset;       // in Amps
2394  uint8_t      Padding_TelemetryGfx;
2395
2396  uint16_t     SocMaxCurrent;   // in Amps
2397  uint8_t      SocOffset;       // in Amps
2398  uint8_t      Padding_TelemetrySoc;
2399
2400  uint16_t     Mem0MaxCurrent;   // in Amps
2401  uint8_t      Mem0Offset;       // in Amps
2402  uint8_t      Padding_TelemetryMem0;
2403  
2404  uint16_t     Mem1MaxCurrent;   // in Amps
2405  uint8_t      Mem1Offset;       // in Amps
2406  uint8_t      Padding_TelemetryMem1;
2407
2408  uint32_t     MvddRatio; // This is used for MVDD  Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16)
2409  
2410  // SECTION: GPIO Settings
2411  uint8_t      AcDcGpio;        // GPIO pin configured for AC/DC switching
2412  uint8_t      AcDcPolarity;    // GPIO polarity for AC/DC switching
2413  uint8_t      VR0HotGpio;      // GPIO pin configured for VR0 HOT event
2414  uint8_t      VR0HotPolarity;  // GPIO polarity for VR0 HOT event
2415
2416  uint8_t      VR1HotGpio;      // GPIO pin configured for VR1 HOT event 
2417  uint8_t      VR1HotPolarity;  // GPIO polarity for VR1 HOT event 
2418  uint8_t      GthrGpio;        // GPIO pin configured for GTHR Event
2419  uint8_t      GthrPolarity;    // replace GPIO polarity for GTHR
2420
2421  // LED Display Settings
2422  uint8_t      LedPin0;         // GPIO number for LedPin[0]
2423  uint8_t      LedPin1;         // GPIO number for LedPin[1]
2424  uint8_t      LedPin2;         // GPIO number for LedPin[2]
2425  uint8_t      LedEnableMask;
2426
2427  uint8_t      LedPcie;        // GPIO number for PCIE results
2428  uint8_t      LedError;       // GPIO number for Error Cases
2429  uint8_t      LedSpare1[2];
2430
2431  // SECTION: Clock Spread Spectrum
2432  
2433  // GFXCLK PLL Spread Spectrum
2434  uint8_t      PllGfxclkSpreadEnabled;   // on or off
2435  uint8_t      PllGfxclkSpreadPercent;   // Q4.4
2436  uint16_t     PllGfxclkSpreadFreq;      // kHz
2437
2438  // GFXCLK DFLL Spread Spectrum
2439  uint8_t      DfllGfxclkSpreadEnabled;   // on or off
2440  uint8_t      DfllGfxclkSpreadPercent;   // Q4.4
2441  uint16_t     DfllGfxclkSpreadFreq;      // kHz
2442  
2443  // UCLK Spread Spectrum
2444  uint8_t      UclkSpreadEnabled;   // on or off
2445  uint8_t      UclkSpreadPercent;   // Q4.4
2446  uint16_t     UclkSpreadFreq;      // kHz
2447
2448  // FCLK Spread Spectrum
2449  uint8_t      FclkSpreadEnabled;   // on or off
2450  uint8_t      FclkSpreadPercent;   // Q4.4
2451  uint16_t     FclkSpreadFreq;      // kHz
2452  
2453  // Section: Memory Config
2454  uint32_t     MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. 
2455  
2456  uint8_t      DramBitWidth; // For DRAM use only.  See Dram Bit width type defines
2457  uint8_t      PaddingMem1[3];
2458
2459  // Section: Total Board Power
2460  uint16_t     TotalBoardPower;     //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
2461  uint16_t     BoardPowerPadding; 
2462  
2463  // SECTION: XGMI Training
2464  uint8_t      XgmiLinkSpeed   [4];
2465  uint8_t      XgmiLinkWidth   [4];
2466
2467  uint16_t     XgmiFclkFreq    [4];
2468  uint16_t     XgmiSocVoltage  [4];
2469
2470  // SECTION: Board Reserved
2471
2472  uint32_t     BoardReserved[16];
2473
2474};
2475
2476struct atom_smc_dpm_info_v4_10
2477{
2478  struct   atom_common_table_header  table_header;
2479
2480  // SECTION: BOARD PARAMETERS
2481  // Telemetry Settings
2482  uint16_t GfxMaxCurrent; // in Amps
2483  uint8_t   GfxOffset;     // in Amps
2484  uint8_t  Padding_TelemetryGfx;
2485
2486  uint16_t SocMaxCurrent; // in Amps
2487  uint8_t   SocOffset;     // in Amps
2488  uint8_t  Padding_TelemetrySoc;
2489
2490  uint16_t MemMaxCurrent; // in Amps
2491  uint8_t   MemOffset;     // in Amps
2492  uint8_t  Padding_TelemetryMem;
2493
2494  uint16_t BoardMaxCurrent; // in Amps
2495  uint8_t   BoardOffset;     // in Amps
2496  uint8_t  Padding_TelemetryBoardInput;
2497
2498  // Platform input telemetry voltage coefficient
2499  uint32_t BoardVoltageCoeffA; // decode by /1000
2500  uint32_t BoardVoltageCoeffB; // decode by /1000
2501
2502  // GPIO Settings
2503  uint8_t  VR0HotGpio;     // GPIO pin configured for VR0 HOT event
2504  uint8_t  VR0HotPolarity; // GPIO polarity for VR0 HOT event
2505  uint8_t  VR1HotGpio;     // GPIO pin configured for VR1 HOT event
2506  uint8_t  VR1HotPolarity; // GPIO polarity for VR1 HOT event
2507
2508  // UCLK Spread Spectrum
2509  uint8_t  UclkSpreadEnabled; // on or off
2510  uint8_t  UclkSpreadPercent; // Q4.4
2511  uint16_t UclkSpreadFreq;    // kHz
2512
2513  // FCLK Spread Spectrum
2514  uint8_t  FclkSpreadEnabled; // on or off
2515  uint8_t  FclkSpreadPercent; // Q4.4
2516  uint16_t FclkSpreadFreq;    // kHz
2517
2518  // I2C Controller Structure
2519  struct smudpm_i2c_controller_config_v3  I2cControllers[8];
2520
2521  // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence
2522  uint8_t  GpioI2cScl; // Serial Clock
2523  uint8_t  GpioI2cSda; // Serial Data
2524  uint16_t spare5;
2525
2526  uint32_t reserved[16];
2527};
2528
2529/* 
2530  ***************************************************************************
2531    Data Table asic_profiling_info  structure
2532  ***************************************************************************
2533*/
2534struct  atom_asic_profiling_info_v4_1
2535{
2536  struct  atom_common_table_header  table_header;
2537  uint32_t  maxvddc;                 
2538  uint32_t  minvddc;               
2539  uint32_t  avfs_meannsigma_acontant0;
2540  uint32_t  avfs_meannsigma_acontant1;
2541  uint32_t  avfs_meannsigma_acontant2;
2542  uint16_t  avfs_meannsigma_dc_tol_sigma;
2543  uint16_t  avfs_meannsigma_platform_mean;
2544  uint16_t  avfs_meannsigma_platform_sigma;
2545  uint32_t  gb_vdroop_table_cksoff_a0;
2546  uint32_t  gb_vdroop_table_cksoff_a1;
2547  uint32_t  gb_vdroop_table_cksoff_a2;
2548  uint32_t  gb_vdroop_table_ckson_a0;
2549  uint32_t  gb_vdroop_table_ckson_a1;
2550  uint32_t  gb_vdroop_table_ckson_a2;
2551  uint32_t  avfsgb_fuse_table_cksoff_m1;
2552  uint32_t  avfsgb_fuse_table_cksoff_m2;
2553  uint32_t  avfsgb_fuse_table_cksoff_b;
2554  uint32_t  avfsgb_fuse_table_ckson_m1; 
2555  uint32_t  avfsgb_fuse_table_ckson_m2;
2556  uint32_t  avfsgb_fuse_table_ckson_b;
2557  uint16_t  max_voltage_0_25mv;
2558  uint8_t   enable_gb_vdroop_table_cksoff;
2559  uint8_t   enable_gb_vdroop_table_ckson;
2560  uint8_t   enable_gb_fuse_table_cksoff;
2561  uint8_t   enable_gb_fuse_table_ckson;
2562  uint16_t  psm_age_comfactor;
2563  uint8_t   enable_apply_avfs_cksoff_voltage;
2564  uint8_t   reserved;
2565  uint32_t  dispclk2gfxclk_a;
2566  uint32_t  dispclk2gfxclk_b;
2567  uint32_t  dispclk2gfxclk_c;
2568  uint32_t  pixclk2gfxclk_a;
2569  uint32_t  pixclk2gfxclk_b;
2570  uint32_t  pixclk2gfxclk_c;
2571  uint32_t  dcefclk2gfxclk_a;
2572  uint32_t  dcefclk2gfxclk_b;
2573  uint32_t  dcefclk2gfxclk_c;
2574  uint32_t  phyclk2gfxclk_a;
2575  uint32_t  phyclk2gfxclk_b;
2576  uint32_t  phyclk2gfxclk_c;
2577};
2578
2579struct  atom_asic_profiling_info_v4_2 {
2580        struct  atom_common_table_header  table_header;
2581        uint32_t  maxvddc;
2582        uint32_t  minvddc;
2583        uint32_t  avfs_meannsigma_acontant0;
2584        uint32_t  avfs_meannsigma_acontant1;
2585        uint32_t  avfs_meannsigma_acontant2;
2586        uint16_t  avfs_meannsigma_dc_tol_sigma;
2587        uint16_t  avfs_meannsigma_platform_mean;
2588        uint16_t  avfs_meannsigma_platform_sigma;
2589        uint32_t  gb_vdroop_table_cksoff_a0;
2590        uint32_t  gb_vdroop_table_cksoff_a1;
2591        uint32_t  gb_vdroop_table_cksoff_a2;
2592        uint32_t  gb_vdroop_table_ckson_a0;
2593        uint32_t  gb_vdroop_table_ckson_a1;
2594        uint32_t  gb_vdroop_table_ckson_a2;
2595        uint32_t  avfsgb_fuse_table_cksoff_m1;
2596        uint32_t  avfsgb_fuse_table_cksoff_m2;
2597        uint32_t  avfsgb_fuse_table_cksoff_b;
2598        uint32_t  avfsgb_fuse_table_ckson_m1;
2599        uint32_t  avfsgb_fuse_table_ckson_m2;
2600        uint32_t  avfsgb_fuse_table_ckson_b;
2601        uint16_t  max_voltage_0_25mv;
2602        uint8_t   enable_gb_vdroop_table_cksoff;
2603        uint8_t   enable_gb_vdroop_table_ckson;
2604        uint8_t   enable_gb_fuse_table_cksoff;
2605        uint8_t   enable_gb_fuse_table_ckson;
2606        uint16_t  psm_age_comfactor;
2607        uint8_t   enable_apply_avfs_cksoff_voltage;
2608        uint8_t   reserved;
2609        uint32_t  dispclk2gfxclk_a;
2610        uint32_t  dispclk2gfxclk_b;
2611        uint32_t  dispclk2gfxclk_c;
2612        uint32_t  pixclk2gfxclk_a;
2613        uint32_t  pixclk2gfxclk_b;
2614        uint32_t  pixclk2gfxclk_c;
2615        uint32_t  dcefclk2gfxclk_a;
2616        uint32_t  dcefclk2gfxclk_b;
2617        uint32_t  dcefclk2gfxclk_c;
2618        uint32_t  phyclk2gfxclk_a;
2619        uint32_t  phyclk2gfxclk_b;
2620        uint32_t  phyclk2gfxclk_c;
2621        uint32_t  acg_gb_vdroop_table_a0;
2622        uint32_t  acg_gb_vdroop_table_a1;
2623        uint32_t  acg_gb_vdroop_table_a2;
2624        uint32_t  acg_avfsgb_fuse_table_m1;
2625        uint32_t  acg_avfsgb_fuse_table_m2;
2626        uint32_t  acg_avfsgb_fuse_table_b;
2627        uint8_t   enable_acg_gb_vdroop_table;
2628        uint8_t   enable_acg_gb_fuse_table;
2629        uint32_t  acg_dispclk2gfxclk_a;
2630        uint32_t  acg_dispclk2gfxclk_b;
2631        uint32_t  acg_dispclk2gfxclk_c;
2632        uint32_t  acg_pixclk2gfxclk_a;
2633        uint32_t  acg_pixclk2gfxclk_b;
2634        uint32_t  acg_pixclk2gfxclk_c;
2635        uint32_t  acg_dcefclk2gfxclk_a;
2636        uint32_t  acg_dcefclk2gfxclk_b;
2637        uint32_t  acg_dcefclk2gfxclk_c;
2638        uint32_t  acg_phyclk2gfxclk_a;
2639        uint32_t  acg_phyclk2gfxclk_b;
2640        uint32_t  acg_phyclk2gfxclk_c;
2641};
2642
2643/* 
2644  ***************************************************************************
2645    Data Table multimedia_info  structure
2646  ***************************************************************************
2647*/
2648struct atom_multimedia_info_v2_1
2649{
2650  struct  atom_common_table_header  table_header;
2651  uint8_t uvdip_min_ver;
2652  uint8_t uvdip_max_ver;
2653  uint8_t vceip_min_ver;
2654  uint8_t vceip_max_ver;
2655  uint16_t uvd_enc_max_input_width_pixels;
2656  uint16_t uvd_enc_max_input_height_pixels;
2657  uint16_t vce_enc_max_input_width_pixels;
2658  uint16_t vce_enc_max_input_height_pixels; 
2659  uint32_t uvd_enc_max_bandwidth;           // 16x16 pixels/sec, codec independent
2660  uint32_t vce_enc_max_bandwidth;           // 16x16 pixels/sec, codec independent
2661};
2662
2663
2664/* 
2665  ***************************************************************************
2666    Data Table umc_info  structure
2667  ***************************************************************************
2668*/
2669struct atom_umc_info_v3_1
2670{
2671  struct  atom_common_table_header  table_header;
2672  uint32_t ucode_version;
2673  uint32_t ucode_rom_startaddr;
2674  uint32_t ucode_length;
2675  uint16_t umc_reg_init_offset;
2676  uint16_t customer_ucode_name_offset;
2677  uint16_t mclk_ss_percentage;
2678  uint16_t mclk_ss_rate_10hz;
2679  uint8_t umcip_min_ver;
2680  uint8_t umcip_max_ver;
2681  uint8_t vram_type;              //enum of atom_dgpu_vram_type
2682  uint8_t umc_config;
2683  uint32_t mem_refclk_10khz;
2684};
2685
2686// umc_info.umc_config
2687enum atom_umc_config_def {
2688  UMC_CONFIG__ENABLE_1KB_INTERLEAVE_MODE  =   0x00000001,
2689  UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE      =   0x00000002,
2690  UMC_CONFIG__ENABLE_HBM_LANE_REPAIR      =   0x00000004,
2691  UMC_CONFIG__ENABLE_BANK_HARVESTING      =   0x00000008,
2692  UMC_CONFIG__ENABLE_PHY_REINIT           =   0x00000010,
2693  UMC_CONFIG__DISABLE_UCODE_CHKSTATUS     =   0x00000020,
2694};
2695
2696struct atom_umc_info_v3_2
2697{
2698  struct  atom_common_table_header  table_header;
2699  uint32_t ucode_version;
2700  uint32_t ucode_rom_startaddr;
2701  uint32_t ucode_length;
2702  uint16_t umc_reg_init_offset;
2703  uint16_t customer_ucode_name_offset;
2704  uint16_t mclk_ss_percentage;
2705  uint16_t mclk_ss_rate_10hz;
2706  uint8_t umcip_min_ver;
2707  uint8_t umcip_max_ver;
2708  uint8_t vram_type;              //enum of atom_dgpu_vram_type
2709  uint8_t umc_config;
2710  uint32_t mem_refclk_10khz;
2711  uint32_t pstate_uclk_10khz[4];
2712  uint16_t umcgoldenoffset;
2713  uint16_t densitygoldenoffset;
2714};
2715
2716struct atom_umc_info_v3_3
2717{
2718  struct  atom_common_table_header  table_header;
2719  uint32_t ucode_reserved;
2720  uint32_t ucode_rom_startaddr;
2721  uint32_t ucode_length;
2722  uint16_t umc_reg_init_offset;
2723  uint16_t customer_ucode_name_offset;
2724  uint16_t mclk_ss_percentage;
2725  uint16_t mclk_ss_rate_10hz;
2726  uint8_t umcip_min_ver;
2727  uint8_t umcip_max_ver;
2728  uint8_t vram_type;              //enum of atom_dgpu_vram_type
2729  uint8_t umc_config;
2730  uint32_t mem_refclk_10khz;
2731  uint32_t pstate_uclk_10khz[4];
2732  uint16_t umcgoldenoffset;
2733  uint16_t densitygoldenoffset;
2734  uint32_t umc_config1;
2735  uint32_t bist_data_startaddr;
2736  uint32_t reserved[2];
2737};
2738
2739enum atom_umc_config1_def {
2740        UMC_CONFIG1__ENABLE_PSTATE_PHASE_STORE_TRAIN = 0x00000001,
2741        UMC_CONFIG1__ENABLE_AUTO_FRAMING = 0x00000002,
2742        UMC_CONFIG1__ENABLE_RESTORE_BIST_DATA = 0x00000004,
2743        UMC_CONFIG1__DISABLE_STROBE_MODE = 0x00000008,
2744        UMC_CONFIG1__DEBUG_DATA_PARITY_EN = 0x00000010,
2745        UMC_CONFIG1__ENABLE_ECC_CAPABLE = 0x00010000,
2746};
2747
2748/* 
2749  ***************************************************************************
2750    Data Table vram_info  structure
2751  ***************************************************************************
2752*/
2753struct atom_vram_module_v9 {
2754  // Design Specific Values
2755  uint32_t  memory_size;                   // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
2756  uint32_t  channel_enable;                // bit vector, each bit indicate specific channel enable or not
2757  uint32_t  max_mem_clk;                   // max memory clock of this memory in unit of 10kHz, =0 means it is not defined
2758  uint16_t  reserved[3];
2759  uint16_t  mem_voltage;                   // mem_voltage
2760  uint16_t  vram_module_size;              // Size of atom_vram_module_v9
2761  uint8_t   ext_memory_id;                 // Current memory module ID
2762  uint8_t   memory_type;                   // enum of atom_dgpu_vram_type
2763  uint8_t   channel_num;                   // Number of mem. channels supported in this module
2764  uint8_t   channel_width;                 // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
2765  uint8_t   density;                       // _8Mx32, _16Mx32, _16Mx16, _32Mx16
2766  uint8_t   tunningset_id;                 // MC phy registers set per. 
2767  uint8_t   vender_rev_id;                 // [7:4] Revision, [3:0] Vendor code
2768  uint8_t   refreshrate;                   // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
2769  uint8_t   hbm_ven_rev_id;                // hbm_ven_rev_id
2770  uint8_t   vram_rsd2;                     // reserved
2771  char    dram_pnstring[20];               // part number end with '0'. 
2772};
2773
2774struct atom_vram_info_header_v2_3 {
2775  struct   atom_common_table_header table_header;
2776  uint16_t mem_adjust_tbloffset;                         // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting
2777  uint16_t mem_clk_patch_tbloffset;                      // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting
2778  uint16_t mc_adjust_pertile_tbloffset;                  // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
2779  uint16_t mc_phyinit_tbloffset;                         // offset of atom_umc_init_reg_block structure for MC phy init set
2780  uint16_t dram_data_remap_tbloffset;                    // reserved for now
2781  uint16_t tmrs_seq_offset;                              // offset of HBM tmrs
2782  uint16_t post_ucode_init_offset;                       // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
2783  uint16_t vram_rsd2;
2784  uint8_t  vram_module_num;                              // indicate number of VRAM module
2785  uint8_t  umcip_min_ver;
2786  uint8_t  umcip_max_ver;
2787  uint8_t  mc_phy_tile_num;                              // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
2788  struct   atom_vram_module_v9  vram_module[16];         // just for allocation, real number of blocks is in ucNumOfVRAMModule;
2789};
2790
2791struct atom_umc_register_addr_info{
2792  uint32_t  umc_register_addr:24;
2793  uint32_t  umc_reg_type_ind:1;
2794  uint32_t  umc_reg_rsvd:7;
2795};
2796
2797//atom_umc_register_addr_info.
2798enum atom_umc_register_addr_info_flag{
2799  b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS  =0x01,
2800};
2801
2802union atom_umc_register_addr_info_access
2803{
2804  struct atom_umc_register_addr_info umc_reg_addr;
2805  uint32_t u32umc_reg_addr;
2806};
2807
2808struct atom_umc_reg_setting_id_config{
2809  uint32_t memclockrange:24;
2810  uint32_t mem_blk_id:8;
2811};
2812
2813union atom_umc_reg_setting_id_config_access
2814{
2815  struct atom_umc_reg_setting_id_config umc_id_access;
2816  uint32_t  u32umc_id_access;
2817};
2818
2819struct atom_umc_reg_setting_data_block{
2820  union atom_umc_reg_setting_id_config_access  block_id;
2821  uint32_t u32umc_reg_data[1];                       
2822};
2823
2824struct atom_umc_init_reg_block{
2825  uint16_t umc_reg_num;
2826  uint16_t reserved;    
2827  union atom_umc_register_addr_info_access umc_reg_list[1];     //for allocation purpose, the real number come from umc_reg_num;
2828  struct atom_umc_reg_setting_data_block umc_reg_setting_list[1];
2829};
2830
2831struct atom_vram_module_v10 {
2832  // Design Specific Values
2833  uint32_t  memory_size;                   // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
2834  uint32_t  channel_enable;                // bit vector, each bit indicate specific channel enable or not
2835  uint32_t  max_mem_clk;                   // max memory clock of this memory in unit of 10kHz, =0 means it is not defined
2836  uint16_t  reserved[3];
2837  uint16_t  mem_voltage;                   // mem_voltage
2838  uint16_t  vram_module_size;              // Size of atom_vram_module_v9
2839  uint8_t   ext_memory_id;                 // Current memory module ID
2840  uint8_t   memory_type;                   // enum of atom_dgpu_vram_type
2841  uint8_t   channel_num;                   // Number of mem. channels supported in this module
2842  uint8_t   channel_width;                 // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
2843  uint8_t   density;                       // _8Mx32, _16Mx32, _16Mx16, _32Mx16
2844  uint8_t   tunningset_id;                 // MC phy registers set per
2845  uint8_t   vender_rev_id;                 // [7:4] Revision, [3:0] Vendor code
2846  uint8_t   refreshrate;                   // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
2847  uint8_t   vram_flags;                    // bit0= bankgroup enable
2848  uint8_t   vram_rsd2;                     // reserved
2849  uint16_t  gddr6_mr10;                    // gddr6 mode register10 value
2850  uint16_t  gddr6_mr1;                     // gddr6 mode register1 value
2851  uint16_t  gddr6_mr2;                     // gddr6 mode register2 value
2852  uint16_t  gddr6_mr7;                     // gddr6 mode register7 value
2853  char    dram_pnstring[20];               // part number end with '0'
2854};
2855
2856struct atom_vram_info_header_v2_4 {
2857  struct   atom_common_table_header table_header;
2858  uint16_t mem_adjust_tbloffset;                         // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting
2859  uint16_t mem_clk_patch_tbloffset;                      // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting
2860  uint16_t mc_adjust_pertile_tbloffset;                  // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
2861  uint16_t mc_phyinit_tbloffset;                         // offset of atom_umc_init_reg_block structure for MC phy init set
2862  uint16_t dram_data_remap_tbloffset;                    // reserved for now
2863  uint16_t reserved;                                     // offset of reserved
2864  uint16_t post_ucode_init_offset;                       // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
2865  uint16_t vram_rsd2;
2866  uint8_t  vram_module_num;                              // indicate number of VRAM module
2867  uint8_t  umcip_min_ver;
2868  uint8_t  umcip_max_ver;
2869  uint8_t  mc_phy_tile_num;                              // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
2870  struct   atom_vram_module_v10  vram_module[16];        // just for allocation, real number of blocks is in ucNumOfVRAMModule;
2871};
2872
2873struct atom_vram_module_v11 {
2874        // Design Specific Values
2875        uint32_t  memory_size;                   // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
2876        uint32_t  channel_enable;                // bit vector, each bit indicate specific channel enable or not
2877        uint16_t  mem_voltage;                   // mem_voltage
2878        uint16_t  vram_module_size;              // Size of atom_vram_module_v9
2879        uint8_t   ext_memory_id;                 // Current memory module ID
2880        uint8_t   memory_type;                   // enum of atom_dgpu_vram_type
2881        uint8_t   channel_num;                   // Number of mem. channels supported in this module
2882        uint8_t   channel_width;                 // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
2883        uint8_t   density;                       // _8Mx32, _16Mx32, _16Mx16, _32Mx16
2884        uint8_t   tunningset_id;                 // MC phy registers set per.
2885        uint16_t  reserved[4];                   // reserved
2886        uint8_t   vender_rev_id;                 // [7:4] Revision, [3:0] Vendor code
2887        uint8_t   refreshrate;                   // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
2888        uint8_t   vram_flags;                    // bit0= bankgroup enable
2889        uint8_t   vram_rsd2;                     // reserved
2890        uint16_t  gddr6_mr10;                    // gddr6 mode register10 value
2891        uint16_t  gddr6_mr0;                     // gddr6 mode register0 value
2892        uint16_t  gddr6_mr1;                     // gddr6 mode register1 value
2893        uint16_t  gddr6_mr2;                     // gddr6 mode register2 value
2894        uint16_t  gddr6_mr4;                     // gddr6 mode register4 value
2895        uint16_t  gddr6_mr7;                     // gddr6 mode register7 value
2896        uint16_t  gddr6_mr8;                     // gddr6 mode register8 value
2897        char    dram_pnstring[40];               // part number end with '0'.
2898};
2899
2900struct atom_gddr6_ac_timing_v2_5 {
2901        uint32_t  u32umc_id_access;
2902        uint8_t  RL;
2903        uint8_t  WL;
2904        uint8_t  tRAS;
2905        uint8_t  tRC;
2906
2907        uint16_t  tREFI;
2908        uint8_t  tRFC;
2909        uint8_t  tRFCpb;
2910
2911        uint8_t  tRREFD;
2912        uint8_t  tRCDRD;
2913        uint8_t  tRCDWR;
2914        uint8_t  tRP;
2915
2916        uint8_t  tRRDS;
2917        uint8_t  tRRDL;
2918        uint8_t  tWR;
2919        uint8_t  tWTRS;
2920
2921        uint8_t  tWTRL;
2922        uint8_t  tFAW;
2923        uint8_t  tCCDS;
2924        uint8_t  tCCDL;
2925
2926        uint8_t  tCRCRL;
2927        uint8_t  tCRCWL;
2928        uint8_t  tCKE;
2929        uint8_t  tCKSRE;
2930
2931        uint8_t  tCKSRX;
2932        uint8_t  tRTPS;
2933        uint8_t  tRTPL;
2934        uint8_t  tMRD;
2935
2936        uint8_t  tMOD;
2937        uint8_t  tXS;
2938        uint8_t  tXHP;
2939        uint8_t  tXSMRS;
2940
2941        uint32_t  tXSH;
2942
2943        uint8_t  tPD;
2944        uint8_t  tXP;
2945        uint8_t  tCPDED;
2946        uint8_t  tACTPDE;
2947
2948        uint8_t  tPREPDE;
2949        uint8_t  tREFPDE;
2950        uint8_t  tMRSPDEN;
2951        uint8_t  tRDSRE;
2952
2953        uint8_t  tWRSRE;
2954        uint8_t  tPPD;
2955        uint8_t  tCCDMW;
2956        uint8_t  tWTRTR;
2957
2958        uint8_t  tLTLTR;
2959        uint8_t  tREFTR;
2960        uint8_t  VNDR;
2961        uint8_t  reserved[9];
2962};
2963
2964struct atom_gddr6_bit_byte_remap {
2965        uint32_t dphy_byteremap;    //mmUMC_DPHY_ByteRemap
2966        uint32_t dphy_bitremap0;    //mmUMC_DPHY_BitRemap0
2967        uint32_t dphy_bitremap1;    //mmUMC_DPHY_BitRemap1
2968        uint32_t dphy_bitremap2;    //mmUMC_DPHY_BitRemap2
2969        uint32_t aphy_bitremap0;    //mmUMC_APHY_BitRemap0
2970        uint32_t aphy_bitremap1;    //mmUMC_APHY_BitRemap1
2971        uint32_t phy_dram;          //mmUMC_PHY_DRAM
2972};
2973
2974struct atom_gddr6_dram_data_remap {
2975        uint32_t table_size;
2976        uint8_t phyintf_ck_inverted[8];     //UMC_PHY_PHYINTF_CNTL.INV_CK
2977        struct atom_gddr6_bit_byte_remap bit_byte_remap[16];
2978};
2979
2980struct atom_vram_info_header_v2_5 {
2981        struct   atom_common_table_header table_header;
2982        uint16_t mem_adjust_tbloffset;                         // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust settings
2983        uint16_t gddr6_ac_timing_offset;                     // offset of atom_gddr6_ac_timing_v2_5 structure for memory clock specific UMC settings
2984        uint16_t mc_adjust_pertile_tbloffset;                  // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
2985        uint16_t mc_phyinit_tbloffset;                         // offset of atom_umc_init_reg_block structure for MC phy init set
2986        uint16_t dram_data_remap_tbloffset;                    // offset of atom_gddr6_dram_data_remap array to indicate DRAM data lane to GPU mapping
2987        uint16_t reserved;                                     // offset of reserved
2988        uint16_t post_ucode_init_offset;                       // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
2989        uint16_t strobe_mode_patch_tbloffset;                  // offset of atom_umc_init_reg_block structure for Strobe Mode memory clock specific UMC settings
2990        uint8_t  vram_module_num;                              // indicate number of VRAM module
2991        uint8_t  umcip_min_ver;
2992        uint8_t  umcip_max_ver;
2993        uint8_t  mc_phy_tile_num;                              // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
2994        struct   atom_vram_module_v11  vram_module[16];        // just for allocation, real number of blocks is in ucNumOfVRAMModule;
2995};
2996
2997struct atom_vram_info_header_v2_6 {
2998        struct atom_common_table_header table_header;
2999        uint16_t mem_adjust_tbloffset;
3000        uint16_t mem_clk_patch_tbloffset;

3001        uint16_t mc_adjust_pertile_tbloffset;
3002        uint16_t mc_phyinit_tbloffset;
3003        uint16_t dram_data_remap_tbloffset;
3004        uint16_t tmrs_seq_offset;
3005        uint16_t post_ucode_init_offset;
3006        uint16_t vram_rsd2;
3007        uint8_t  vram_module_num;
3008        uint8_t  umcip_min_ver;
3009        uint8_t  umcip_max_ver;
3010        uint8_t  mc_phy_tile_num;
3011        struct atom_vram_module_v9 vram_module[16];
3012};
3013/* 
3014  ***************************************************************************
3015    Data Table voltageobject_info  structure
3016  ***************************************************************************
3017*/
3018struct  atom_i2c_data_entry
3019{
3020  uint16_t  i2c_reg_index;               // i2c register address, can be up to 16bit
3021  uint16_t  i2c_reg_data;                // i2c register data, can be up to 16bit
3022};
3023
3024struct atom_voltage_object_header_v4{
3025  uint8_t    voltage_type;                           //enum atom_voltage_type
3026  uint8_t    voltage_mode;                           //enum atom_voltage_object_mode 
3027  uint16_t   object_size;                            //Size of Object
3028};
3029
3030// atom_voltage_object_header_v4.voltage_mode
3031enum atom_voltage_object_mode 
3032{
3033   VOLTAGE_OBJ_GPIO_LUT              =  0,        //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage_object_v4
3034   VOLTAGE_OBJ_VR_I2C_INIT_SEQ       =  3,        //VOLTAGE REGULATOR INIT sequece through I2C -> atom_i2c_voltage_object_v4
3035   VOLTAGE_OBJ_PHASE_LUT             =  4,        //Set Vregulator Phase lookup table ->atom_gpio_voltage_object_v4
3036   VOLTAGE_OBJ_SVID2                 =  7,        //Indicate voltage control by SVID2 ->atom_svid2_voltage_object_v4
3037   VOLTAGE_OBJ_EVV                   =  8, 
3038   VOLTAGE_OBJ_MERGED_POWER          =  9,
3039};
3040
3041struct  atom_i2c_voltage_object_v4
3042{
3043   struct atom_voltage_object_header_v4 header;  // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ
3044   uint8_t  regulator_id;                        //Indicate Voltage Regulator Id
3045   uint8_t  i2c_id;
3046   uint8_t  i2c_slave_addr;
3047   uint8_t  i2c_control_offset;       
3048   uint8_t  i2c_flag;                            // Bit0: 0 - One byte data; 1 - Two byte data
3049   uint8_t  i2c_speed;                           // =0, use default i2c speed, otherwise use it in unit of kHz. 
3050   uint8_t  reserved[2];
3051   struct atom_i2c_data_entry i2cdatalut[1];     // end with 0xff
3052};
3053
3054// ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag
3055enum atom_i2c_voltage_control_flag
3056{
3057   VOLTAGE_DATA_ONE_BYTE = 0,
3058   VOLTAGE_DATA_TWO_BYTE = 1,
3059};
3060
3061
3062struct atom_voltage_gpio_map_lut
3063{
3064  uint32_t  voltage_gpio_reg_val;              // The Voltage ID which is used to program GPIO register
3065  uint16_t  voltage_level_mv;                  // The corresponding Voltage Value, in mV
3066};
3067
3068struct atom_gpio_voltage_object_v4
3069{
3070   struct atom_voltage_object_header_v4 header;  // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT
3071   uint8_t  gpio_control_id;                     // default is 0 which indicate control through CG VID mode 
3072   uint8_t  gpio_entry_num;                      // indiate the entry numbers of Votlage/Gpio value Look up table
3073   uint8_t  phase_delay_us;                      // phase delay in unit of micro second
3074   uint8_t  reserved;   
3075   uint32_t gpio_mask_val;                         // GPIO Mask value
3076   struct atom_voltage_gpio_map_lut voltage_gpio_lut[1];
3077};
3078
3079struct  atom_svid2_voltage_object_v4
3080{
3081   struct atom_voltage_object_header_v4 header;  // voltage mode = VOLTAGE_OBJ_SVID2
3082   uint8_t loadline_psi1;                        // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable
3083   uint8_t psi0_l_vid_thresd;                    // VR PSI0_L VID threshold
3084   uint8_t psi0_enable;                          // 
3085   uint8_t maxvstep;
3086   uint8_t telemetry_offset;
3087   uint8_t telemetry_gain; 
3088   uint16_t reserved1;
3089};
3090
3091struct atom_merged_voltage_object_v4
3092{
3093  struct atom_voltage_object_header_v4 header;  // voltage mode = VOLTAGE_OBJ_MERGED_POWER
3094  uint8_t  merged_powerrail_type;               //enum atom_voltage_type
3095  uint8_t  reserved[3];
3096};
3097
3098union atom_voltage_object_v4{
3099  struct atom_gpio_voltage_object_v4 gpio_voltage_obj;
3100  struct atom_i2c_voltage_object_v4 i2c_voltage_obj;
3101  struct atom_svid2_voltage_object_v4 svid2_voltage_obj;
3102  struct atom_merged_voltage_object_v4 merged_voltage_obj;
3103};
3104
3105struct  atom_voltage_objects_info_v4_1
3106{
3107  struct atom_common_table_header table_header; 
3108  union atom_voltage_object_v4 voltage_object[1];   //Info for Voltage control
3109};
3110
3111
3112/* 
3113  ***************************************************************************
3114              All Command Function structure definition 
3115  *************************************************************************** 
3116*/   
3117
3118/* 
3119  ***************************************************************************
3120              Structures used by asic_init
3121  *************************************************************************** 
3122*/   
3123
3124struct asic_init_engine_parameters
3125{
3126  uint32_t sclkfreqin10khz:24;
3127  uint32_t engineflag:8;              /* enum atom_asic_init_engine_flag  */
3128};
3129
3130struct asic_init_mem_parameters
3131{
3132  uint32_t mclkfreqin10khz:24;
3133  uint32_t memflag:8;                 /* enum atom_asic_init_mem_flag  */
3134};
3135
3136struct asic_init_parameters_v2_1
3137{
3138  struct asic_init_engine_parameters engineparam;
3139  struct asic_init_mem_parameters memparam;
3140};
3141
3142struct asic_init_ps_allocation_v2_1
3143{
3144  struct asic_init_parameters_v2_1 param;
3145  uint32_t reserved[16];
3146};
3147
3148
3149enum atom_asic_init_engine_flag
3150{
3151  b3NORMAL_ENGINE_INIT = 0,
3152  b3SRIOV_SKIP_ASIC_INIT = 0x02,
3153  b3SRIOV_LOAD_UCODE = 0x40,
3154};
3155
3156enum atom_asic_init_mem_flag
3157{
3158  b3NORMAL_MEM_INIT = 0,
3159  b3DRAM_SELF_REFRESH_EXIT =0x20,
3160};
3161
3162/* 
3163  ***************************************************************************
3164              Structures used by setengineclock
3165  *************************************************************************** 
3166*/   
3167
3168struct set_engine_clock_parameters_v2_1
3169{
3170  uint32_t sclkfreqin10khz:24;
3171  uint32_t sclkflag:8;              /* enum atom_set_engine_mem_clock_flag,  */
3172  uint32_t reserved[10];
3173};
3174
3175struct set_engine_clock_ps_allocation_v2_1
3176{
3177  struct set_engine_clock_parameters_v2_1 clockinfo;
3178  uint32_t reserved[10];
3179};
3180
3181
3182enum atom_set_engine_mem_clock_flag
3183{
3184  b3NORMAL_CHANGE_CLOCK = 0,
3185  b3FIRST_TIME_CHANGE_CLOCK = 0x08,
3186  b3STORE_DPM_TRAINGING = 0x40,         //Applicable to memory clock change,when set, it store specific DPM mode training result
3187};
3188
3189/* 
3190  ***************************************************************************
3191              Structures used by getengineclock
3192  *************************************************************************** 
3193*/   
3194struct get_engine_clock_parameter
3195{
3196  uint32_t sclk_10khz;          // current engine speed in 10KHz unit
3197  uint32_t reserved;
3198};
3199
3200/* 
3201  ***************************************************************************
3202              Structures used by setmemoryclock
3203  *************************************************************************** 
3204*/   
3205struct set_memory_clock_parameters_v2_1
3206{
3207  uint32_t mclkfreqin10khz:24;
3208  uint32_t mclkflag:8;              /* enum atom_set_engine_mem_clock_flag,  */
3209  uint32_t reserved[10];
3210};
3211
3212struct set_memory_clock_ps_allocation_v2_1
3213{
3214  struct set_memory_clock_parameters_v2_1 clockinfo;
3215  uint32_t reserved[10];
3216};
3217
3218
3219/* 
3220  ***************************************************************************
3221              Structures used by getmemoryclock
3222  *************************************************************************** 
3223*/   
3224struct get_memory_clock_parameter
3225{
3226  uint32_t mclk_10khz;          // current engine speed in 10KHz unit
3227  uint32_t reserved;
3228};
3229
3230
3231
3232/* 
3233  ***************************************************************************
3234              Structures used by setvoltage
3235  *************************************************************************** 
3236*/   
3237
3238struct set_voltage_parameters_v1_4
3239{
3240  uint8_t  voltagetype;                /* enum atom_voltage_type */
3241  uint8_t  command;                    /* Indicate action: Set voltage level, enum atom_set_voltage_command */
3242  uint16_t vlevel_mv;                  /* real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) */
3243};
3244
3245//set_voltage_parameters_v2_1.voltagemode
3246enum atom_set_voltage_command{
3247  ATOM_SET_VOLTAGE  = 0,
3248  ATOM_INIT_VOLTAGE_REGULATOR = 3,
3249  ATOM_SET_VOLTAGE_PHASE = 4,
3250  ATOM_GET_LEAKAGE_ID    = 8,
3251};
3252
3253struct set_voltage_ps_allocation_v1_4
3254{
3255  struct set_voltage_parameters_v1_4 setvoltageparam;
3256  uint32_t reserved[10];
3257};
3258
3259
3260/* 
3261  ***************************************************************************
3262              Structures used by computegpuclockparam
3263  *************************************************************************** 
3264*/   
3265
3266//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag
3267enum atom_gpu_clock_type 
3268{
3269  COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00,
3270  COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01,
3271  COMPUTE_GPUCLK_INPUT_FLAG_UCLK =0x02,
3272};
3273
3274struct compute_gpu_clock_input_parameter_v1_8
3275{
3276  uint32_t  gpuclock_10khz:24;         //Input= target clock, output = actual clock 
3277  uint32_t  gpu_clock_type:8;          //Input indicate clock type: enum atom_gpu_clock_type
3278  uint32_t  reserved[5];
3279};
3280
3281
3282struct compute_gpu_clock_output_parameter_v1_8
3283{
3284  uint32_t  gpuclock_10khz:24;              //Input= target clock, output = actual clock 
3285  uint32_t  dfs_did:8;                      //return parameter: DFS divider which is used to program to register directly
3286  uint32_t  pll_fb_mult;                    //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac
3287  uint32_t  pll_ss_fbsmult;                 // Spread FB Mult: bit 8:0 int, bit 31:16 frac
3288  uint16_t  pll_ss_slew_frac;
3289  uint8_t   pll_ss_enable;
3290  uint8_t   reserved;
3291  uint32_t  reserved1[2];
3292};
3293
3294
3295
3296/* 
3297  ***************************************************************************
3298              Structures used by ReadEfuseValue
3299  *************************************************************************** 
3300*/   
3301
3302struct read_efuse_input_parameters_v3_1
3303{
3304  uint16_t efuse_start_index;
3305  uint8_t  reserved;
3306  uint8_t  bitslen;
3307};
3308
3309// ReadEfuseValue input/output parameter
3310union read_efuse_value_parameters_v3_1
3311{
3312  struct read_efuse_input_parameters_v3_1 efuse_info;
3313  uint32_t efusevalue;
3314};
3315
3316
3317/* 
3318  ***************************************************************************
3319              Structures used by getsmuclockinfo
3320  *************************************************************************** 
3321*/   
3322struct atom_get_smu_clock_info_parameters_v3_1
3323{
3324  uint8_t syspll_id;          // 0= syspll0, 1=syspll1, 2=syspll2                
3325  uint8_t clk_id;             // atom_smu9_syspll0_clock_id  (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
3326  uint8_t command;            // enum of atom_get_smu_clock_info_command
3327  uint8_t dfsdid;             // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
3328};
3329
3330enum atom_get_smu_clock_info_command 
3331{
3332  GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ       = 0,
3333  GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ      = 1,
3334  GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ   = 2,
3335};
3336
3337enum atom_smu9_syspll0_clock_id
3338{
3339  SMU9_SYSPLL0_SMNCLK_ID   = 0,       //  SMNCLK
3340  SMU9_SYSPLL0_SOCCLK_ID   = 1,       //        SOCCLK (FCLK)
3341  SMU9_SYSPLL0_MP0CLK_ID   = 2,       //        MP0CLK
3342  SMU9_SYSPLL0_MP1CLK_ID   = 3,       //        MP1CLK
3343  SMU9_SYSPLL0_LCLK_ID     = 4,       //        LCLK
3344  SMU9_SYSPLL0_DCLK_ID     = 5,       //        DCLK
3345  SMU9_SYSPLL0_VCLK_ID     = 6,       //        VCLK
3346  SMU9_SYSPLL0_ECLK_ID     = 7,       //        ECLK
3347  SMU9_SYSPLL0_DCEFCLK_ID  = 8,       //        DCEFCLK
3348  SMU9_SYSPLL0_DPREFCLK_ID = 10,      //        DPREFCLK
3349  SMU9_SYSPLL0_DISPCLK_ID  = 11,      //        DISPCLK
3350};
3351
3352enum atom_smu11_syspll_id {
3353  SMU11_SYSPLL0_ID            = 0,
3354  SMU11_SYSPLL1_0_ID          = 1,
3355  SMU11_SYSPLL1_1_ID          = 2,
3356  SMU11_SYSPLL1_2_ID          = 3,
3357  SMU11_SYSPLL2_ID            = 4,
3358  SMU11_SYSPLL3_0_ID          = 5,
3359  SMU11_SYSPLL3_1_ID          = 6,
3360};
3361
3362enum atom_smu11_syspll0_clock_id {
3363  SMU11_SYSPLL0_ECLK_ID     = 0,       //       ECLK
3364  SMU11_SYSPLL0_SOCCLK_ID   = 1,       //       SOCCLK
3365  SMU11_SYSPLL0_MP0CLK_ID   = 2,       //       MP0CLK
3366  SMU11_SYSPLL0_DCLK_ID     = 3,       //       DCLK
3367  SMU11_SYSPLL0_VCLK_ID     = 4,       //       VCLK
3368  SMU11_SYSPLL0_DCEFCLK_ID  = 5,       //       DCEFCLK
3369};
3370
3371enum atom_smu11_syspll1_0_clock_id {
3372  SMU11_SYSPLL1_0_UCLKA_ID   = 0,       // UCLK_a
3373};
3374
3375enum atom_smu11_syspll1_1_clock_id {
3376  SMU11_SYSPLL1_0_UCLKB_ID   = 0,       // UCLK_b
3377};
3378
3379enum atom_smu11_syspll1_2_clock_id {
3380  SMU11_SYSPLL1_0_FCLK_ID   = 0,        // FCLK
3381};
3382
3383enum atom_smu11_syspll2_clock_id {
3384  SMU11_SYSPLL2_GFXCLK_ID   = 0,        // GFXCLK
3385};
3386
3387enum atom_smu11_syspll3_0_clock_id {
3388  SMU11_SYSPLL3_0_WAFCLK_ID = 0,       //       WAFCLK
3389  SMU11_SYSPLL3_0_DISPCLK_ID = 1,      //       DISPCLK
3390  SMU11_SYSPLL3_0_DPREFCLK_ID = 2,     //       DPREFCLK
3391};
3392
3393enum atom_smu11_syspll3_1_clock_id {
3394  SMU11_SYSPLL3_1_MP1CLK_ID = 0,       //       MP1CLK
3395  SMU11_SYSPLL3_1_SMNCLK_ID = 1,       //       SMNCLK
3396  SMU11_SYSPLL3_1_LCLK_ID = 2,         //       LCLK
3397};
3398
3399enum atom_smu12_syspll_id {
3400  SMU12_SYSPLL0_ID          = 0,
3401  SMU12_SYSPLL1_ID          = 1,
3402  SMU12_SYSPLL2_ID          = 2,
3403  SMU12_SYSPLL3_0_ID        = 3,
3404  SMU12_SYSPLL3_1_ID        = 4,
3405};
3406
3407enum atom_smu12_syspll0_clock_id {
3408  SMU12_SYSPLL0_SMNCLK_ID   = 0,                        //      SOCCLK
3409  SMU12_SYSPLL0_SOCCLK_ID   = 1,                        //      SOCCLK
3410  SMU12_SYSPLL0_MP0CLK_ID   = 2,                        //      MP0CLK
3411  SMU12_SYSPLL0_MP1CLK_ID   = 3,                        //      MP1CLK
3412  SMU12_SYSPLL0_MP2CLK_ID   = 4,                        //      MP2CLK
3413  SMU12_SYSPLL0_VCLK_ID     = 5,                        //      VCLK
3414  SMU12_SYSPLL0_LCLK_ID     = 6,                        //      LCLK
3415  SMU12_SYSPLL0_DCLK_ID     = 7,                        //      DCLK
3416  SMU12_SYSPLL0_ACLK_ID     = 8,                        //      ACLK
3417  SMU12_SYSPLL0_ISPCLK_ID   = 9,                        //      ISPCLK
3418  SMU12_SYSPLL0_SHUBCLK_ID  = 10,                       //      SHUBCLK
3419};
3420
3421enum atom_smu12_syspll1_clock_id {
3422  SMU12_SYSPLL1_DISPCLK_ID  = 0,      //        DISPCLK
3423  SMU12_SYSPLL1_DPPCLK_ID   = 1,      //        DPPCLK
3424  SMU12_SYSPLL1_DPREFCLK_ID = 2,      //        DPREFCLK
3425  SMU12_SYSPLL1_DCFCLK_ID   = 3,      //        DCFCLK
3426};
3427
3428enum atom_smu12_syspll2_clock_id {
3429  SMU12_SYSPLL2_Pre_GFXCLK_ID = 0,   // Pre_GFXCLK
3430};
3431
3432enum atom_smu12_syspll3_0_clock_id {
3433  SMU12_SYSPLL3_0_FCLK_ID = 0,      //  FCLK
3434};
3435
3436enum atom_smu12_syspll3_1_clock_id {
3437  SMU12_SYSPLL3_1_UMCCLK_ID = 0,    //  UMCCLK
3438};
3439
3440struct  atom_get_smu_clock_info_output_parameters_v3_1
3441{
3442  union {
3443    uint32_t smu_clock_freq_hz;
3444    uint32_t syspllvcofreq_10khz;
3445    uint32_t sysspllrefclk_10khz;
3446  }atom_smu_outputclkfreq;
3447};
3448
3449
3450
3451/* 
3452  ***************************************************************************
3453              Structures used by dynamicmemorysettings
3454  *************************************************************************** 
3455*/   
3456
3457enum atom_dynamic_memory_setting_command 
3458{
3459  COMPUTE_MEMORY_PLL_PARAM = 1,
3460  COMPUTE_ENGINE_PLL_PARAM = 2,
3461  ADJUST_MC_SETTING_PARAM = 3,
3462};
3463
3464/* when command = COMPUTE_MEMORY_PLL_PARAM or ADJUST_MC_SETTING_PARAM */
3465struct dynamic_mclk_settings_parameters_v2_1
3466{
3467  uint32_t  mclk_10khz:24;         //Input= target mclk
3468  uint32_t  command:8;             //command enum of atom_dynamic_memory_setting_command
3469  uint32_t  reserved;
3470};
3471
3472/* when command = COMPUTE_ENGINE_PLL_PARAM */
3473struct dynamic_sclk_settings_parameters_v2_1
3474{
3475  uint32_t  sclk_10khz:24;         //Input= target mclk
3476  uint32_t  command:8;             //command enum of atom_dynamic_memory_setting_command
3477  uint32_t  mclk_10khz;
3478  uint32_t  reserved;
3479};
3480
3481union dynamic_memory_settings_parameters_v2_1
3482{
3483  struct dynamic_mclk_settings_parameters_v2_1 mclk_setting;
3484  struct dynamic_sclk_settings_parameters_v2_1 sclk_setting;
3485};
3486
3487
3488
3489/* 
3490  ***************************************************************************
3491              Structures used by memorytraining
3492  *************************************************************************** 
3493*/   
3494
3495enum atom_umc6_0_ucode_function_call_enum_id
3496{
3497  UMC60_UCODE_FUNC_ID_REINIT                 = 0,
3498  UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH      = 1,
3499  UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH       = 2,
3500};
3501
3502
3503struct memory_training_parameters_v2_1
3504{
3505  uint8_t ucode_func_id;
3506  uint8_t ucode_reserved[3];
3507  uint32_t reserved[5];
3508};
3509
3510
3511/* 
3512  ***************************************************************************
3513              Structures used by setpixelclock
3514  *************************************************************************** 
3515*/   
3516
3517struct set_pixel_clock_parameter_v1_7
3518{
3519    uint32_t pixclk_100hz;               // target the pixel clock to drive the CRTC timing in unit of 100Hz. 
3520
3521    uint8_t  pll_id;                     // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0
3522    uint8_t  encoderobjid;               // ASIC encoder id defined in objectId.h, 
3523                                         // indicate which graphic encoder will be used. 
3524    uint8_t  encoder_mode;               // Encoder mode: 
3525    uint8_t  miscinfo;                   // enum atom_set_pixel_clock_v1_7_misc_info
3526    uint8_t  crtc_id;                    // enum of atom_crtc_def
3527    uint8_t  deep_color_ratio;           // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio
3528    uint8_t  reserved1[2];    
3529    uint32_t reserved2;
3530};
3531
3532//ucMiscInfo
3533enum atom_set_pixel_clock_v1_7_misc_info
3534{
3535  PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL         = 0x01,
3536  PIXEL_CLOCK_V7_MISC_PROG_PHYPLL             = 0x02,
3537  PIXEL_CLOCK_V7_MISC_YUV420_MODE             = 0x04,
3538  PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN         = 0x08,
3539  PIXEL_CLOCK_V7_MISC_REF_DIV_SRC             = 0x30,
3540  PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN      = 0x00,
3541  PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE        = 0x10,
3542  PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK       = 0x20,
3543  PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD      = 0x30, 
3544  PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE           = 0x40,
3545  PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS            = 0x80,
3546};
3547
3548/* deep_color_ratio */
3549enum atom_set_pixel_clock_v1_7_deepcolor_ratio
3550{
3551  PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS          = 0x00,      //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 
3552  PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4          = 0x01,      //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 
3553  PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2          = 0x02,      //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 
3554  PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1          = 0x03,      //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 
3555};
3556
3557/* 
3558  ***************************************************************************
3559              Structures used by setdceclock
3560  *************************************************************************** 
3561*/   
3562
3563// SetDCEClock input parameter for DCE11.2( ELM and BF ) and above 
3564struct set_dce_clock_parameters_v2_1
3565{
3566  uint32_t dceclk_10khz;                               // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency. 
3567  uint8_t  dceclktype;                                 // =0: DISPCLK  =1: DPREFCLK  =2: PIXCLK
3568  uint8_t  dceclksrc;                                  // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx
3569  uint8_t  dceclkflag;                                 // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 )
3570  uint8_t  crtc_id;                                    // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK
3571};
3572
3573//ucDCEClkType
3574enum atom_set_dce_clock_clock_type
3575{
3576  DCE_CLOCK_TYPE_DISPCLK                      = 0,
3577  DCE_CLOCK_TYPE_DPREFCLK                     = 1,
3578  DCE_CLOCK_TYPE_PIXELCLK                     = 2,        // used by VBIOS internally, called by SetPixelClock 
3579};
3580
3581//ucDCEClkFlag when ucDCEClkType == DPREFCLK 
3582enum atom_set_dce_clock_dprefclk_flag
3583{
3584  DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK          = 0x03,
3585  DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA      = 0x00,
3586  DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK         = 0x01,
3587  DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE          = 0x02,
3588  DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN        = 0x03,
3589};
3590
3591//ucDCEClkFlag when ucDCEClkType == PIXCLK 
3592enum atom_set_dce_clock_pixclk_flag
3593{
3594  DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK    = 0x03,
3595  DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS     = 0x00,      //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 
3596  DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4     = 0x01,      //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 
3597  DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2     = 0x02,      //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 
3598  DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1     = 0x03,      //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 
3599  DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE           = 0x04,
3600};
3601
3602struct set_dce_clock_ps_allocation_v2_1
3603{
3604  struct set_dce_clock_parameters_v2_1 param;
3605  uint32_t ulReserved[2];
3606};
3607
3608
3609/****************************************************************************/   
3610// Structures used by BlankCRTC
3611/****************************************************************************/   
3612struct blank_crtc_parameters
3613{
3614  uint8_t  crtc_id;                   // enum atom_crtc_def
3615  uint8_t  blanking;                  // enum atom_blank_crtc_command
3616  uint16_t reserved;
3617  uint32_t reserved1;
3618};
3619
3620enum atom_blank_crtc_command
3621{
3622  ATOM_BLANKING         = 1,
3623  ATOM_BLANKING_OFF     = 0,
3624};
3625
3626/****************************************************************************/   
3627// Structures used by enablecrtc
3628/****************************************************************************/   
3629struct enable_crtc_parameters
3630{
3631  uint8_t crtc_id;                    // enum atom_crtc_def
3632  uint8_t enable;                     // ATOM_ENABLE or ATOM_DISABLE 
3633  uint8_t padding[2];
3634};
3635
3636
3637/****************************************************************************/   
3638// Structure used by EnableDispPowerGating
3639/****************************************************************************/   
3640struct enable_disp_power_gating_parameters_v2_1
3641{
3642  uint8_t disp_pipe_id;                // ATOM_CRTC1, ATOM_CRTC2, ...
3643  uint8_t enable;                     // ATOM_ENABLE or ATOM_DISABLE
3644  uint8_t padding[2];
3645};
3646
3647struct enable_disp_power_gating_ps_allocation 
3648{
3649  struct enable_disp_power_gating_parameters_v2_1 param;
3650  uint32_t ulReserved[4];
3651};
3652
3653/****************************************************************************/   
3654// Structure used in setcrtc_usingdtdtiming
3655/****************************************************************************/   
3656struct set_crtc_using_dtd_timing_parameters
3657{
3658  uint16_t  h_size;
3659  uint16_t  h_blanking_time;
3660  uint16_t  v_size;
3661  uint16_t  v_blanking_time;
3662  uint16_t  h_syncoffset;
3663  uint16_t  h_syncwidth;
3664  uint16_t  v_syncoffset;
3665  uint16_t  v_syncwidth;
3666  uint16_t  modemiscinfo;  
3667  uint8_t   h_border;
3668  uint8_t   v_border;
3669  uint8_t   crtc_id;                   // enum atom_crtc_def
3670  uint8_t   encoder_mode;                          // atom_encode_mode_def
3671  uint8_t   padding[2];
3672};
3673
3674
3675/****************************************************************************/   
3676// Structures used by processi2cchanneltransaction
3677/****************************************************************************/   
3678struct process_i2c_channel_transaction_parameters
3679{
3680  uint8_t i2cspeed_khz;
3681  union {
3682    uint8_t regindex;
3683    uint8_t status;                  /* enum atom_process_i2c_flag */
3684  } regind_status;
3685  uint16_t  i2c_data_out;
3686  uint8_t   flag;                    /* enum atom_process_i2c_status */
3687  uint8_t   trans_bytes;
3688  uint8_t   slave_addr;
3689  uint8_t   i2c_id;
3690};
3691
3692//ucFlag
3693enum atom_process_i2c_flag
3694{
3695  HW_I2C_WRITE          = 1,
3696  HW_I2C_READ           = 0,
3697  I2C_2BYTE_ADDR        = 0x02,
3698  HW_I2C_SMBUS_BYTE_WR  = 0x04,
3699};
3700
3701//status
3702enum atom_process_i2c_status
3703{
3704  HW_ASSISTED_I2C_STATUS_FAILURE     =2,
3705  HW_ASSISTED_I2C_STATUS_SUCCESS     =1,
3706};
3707
3708
3709/****************************************************************************/   
3710// Structures used by processauxchanneltransaction
3711/****************************************************************************/   
3712
3713struct process_aux_channel_transaction_parameters_v1_2
3714{
3715  uint16_t aux_request;
3716  uint16_t dataout;
3717  uint8_t  channelid;
3718  union {
3719    uint8_t   reply_status;
3720    uint8_t   aux_delay;
3721  } aux_status_delay;
3722  uint8_t   dataout_len;
3723  uint8_t   hpd_id;                                       //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
3724};
3725
3726
3727/****************************************************************************/   
3728// Structures used by selectcrtc_source
3729/****************************************************************************/   
3730
3731struct select_crtc_source_parameters_v2_3
3732{
3733  uint8_t crtc_id;                        // enum atom_crtc_def
3734  uint8_t encoder_id;                     // enum atom_dig_def
3735  uint8_t encode_mode;                    // enum atom_encode_mode_def
3736  uint8_t dst_bpc;                        // enum atom_panel_bit_per_color
3737};
3738
3739
3740/****************************************************************************/   
3741// Structures used by digxencodercontrol
3742/****************************************************************************/   
3743
3744// ucAction:
3745enum atom_dig_encoder_control_action
3746{
3747  ATOM_ENCODER_CMD_DISABLE_DIG                  = 0,
3748  ATOM_ENCODER_CMD_ENABLE_DIG                   = 1,
3749  ATOM_ENCODER_CMD_DP_LINK_TRAINING_START       = 0x08,
3750  ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1    = 0x09,
3751  ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2    = 0x0a,
3752  ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3    = 0x13,
3753  ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE    = 0x0b,
3754  ATOM_ENCODER_CMD_DP_VIDEO_OFF                 = 0x0c,
3755  ATOM_ENCODER_CMD_DP_VIDEO_ON                  = 0x0d,
3756  ATOM_ENCODER_CMD_SETUP_PANEL_MODE             = 0x10,
3757  ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4    = 0x14,
3758  ATOM_ENCODER_CMD_STREAM_SETUP                 = 0x0F, 
3759  ATOM_ENCODER_CMD_LINK_SETUP                   = 0x11, 
3760  ATOM_ENCODER_CMD_ENCODER_BLANK                = 0x12,
3761};
3762
3763//define ucPanelMode
3764enum atom_dig_encoder_control_panelmode
3765{
3766  DP_PANEL_MODE_DISABLE                        = 0x00,
3767  DP_PANEL_MODE_ENABLE_eDP_MODE                = 0x01,
3768  DP_PANEL_MODE_ENABLE_LVLINK_MODE             = 0x11,
3769};
3770
3771//ucDigId
3772enum atom_dig_encoder_control_v5_digid
3773{
3774  ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER           = 0x00,
3775  ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER           = 0x01,
3776  ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER           = 0x02,
3777  ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER           = 0x03,
3778  ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER           = 0x04,
3779  ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER           = 0x05,
3780  ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER           = 0x06,
3781  ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER           = 0x07,
3782};
3783
3784struct dig_encoder_stream_setup_parameters_v1_5
3785{
3786  uint8_t digid;            // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
3787  uint8_t action;           // =  ATOM_ENOCODER_CMD_STREAM_SETUP
3788  uint8_t digmode;          // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
3789  uint8_t lanenum;          // Lane number     
3790  uint32_t pclk_10khz;      // Pixel Clock in 10Khz
3791  uint8_t bitpercolor;
3792  uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G  = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc
3793  uint8_t reserved[2];
3794};
3795
3796struct dig_encoder_link_setup_parameters_v1_5
3797{
3798  uint8_t digid;           // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
3799  uint8_t action;          // =  ATOM_ENOCODER_CMD_LINK_SETUP              
3800  uint8_t digmode;         // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
3801  uint8_t lanenum;         // Lane number     
3802  uint8_t symclk_10khz;    // Symbol Clock in 10Khz
3803  uint8_t hpd_sel;
3804  uint8_t digfe_sel;       // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 
3805  uint8_t reserved[2];
3806};
3807
3808struct dp_panel_mode_set_parameters_v1_5
3809{
3810  uint8_t digid;              // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
3811  uint8_t action;             // = ATOM_ENCODER_CMD_DPLINK_SETUP
3812  uint8_t panelmode;      // enum atom_dig_encoder_control_panelmode
3813  uint8_t reserved1;    
3814  uint32_t reserved2[2];
3815};
3816
3817struct dig_encoder_generic_cmd_parameters_v1_5 
3818{
3819  uint8_t digid;           // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
3820  uint8_t action;          // = rest of generic encoder command which does not carry any parameters
3821  uint8_t reserved1[2];    
3822  uint32_t reserved2[2];
3823};
3824
3825union dig_encoder_control_parameters_v1_5
3826{
3827  struct dig_encoder_generic_cmd_parameters_v1_5  cmd_param;
3828  struct dig_encoder_stream_setup_parameters_v1_5 stream_param;
3829  struct dig_encoder_link_setup_parameters_v1_5   link_param;
3830  struct dp_panel_mode_set_parameters_v1_5 dppanel_param;
3831};
3832
3833/* 
3834  ***************************************************************************
3835              Structures used by dig1transmittercontrol
3836  *************************************************************************** 
3837*/   
3838struct dig_transmitter_control_parameters_v1_6
3839{
3840  uint8_t phyid;           // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
3841  uint8_t action;          // define as ATOM_TRANSMITER_ACTION_xxx
3842  union {
3843    uint8_t digmode;        // enum atom_encode_mode_def
3844    uint8_t dplaneset;      // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV"
3845  } mode_laneset;
3846  uint8_t  lanenum;        // Lane number 1, 2, 4, 8    
3847  uint32_t symclk_10khz;   // Symbol Clock in 10Khz
3848  uint8_t  hpdsel;         // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
3849  uint8_t  digfe_sel;      // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 
3850  uint8_t  connobj_id;     // Connector Object Id defined in ObjectId.h
3851  uint8_t  reserved;
3852  uint32_t reserved1;
3853};
3854
3855struct dig_transmitter_control_ps_allocation_v1_6
3856{
3857  struct dig_transmitter_control_parameters_v1_6 param;
3858  uint32_t reserved[4];
3859};
3860
3861//ucAction
3862enum atom_dig_transmitter_control_action
3863{
3864  ATOM_TRANSMITTER_ACTION_DISABLE                 = 0,
3865  ATOM_TRANSMITTER_ACTION_ENABLE                  = 1,
3866  ATOM_TRANSMITTER_ACTION_LCD_BLOFF               = 2,
3867  ATOM_TRANSMITTER_ACTION_LCD_BLON                = 3,
3868  ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL   = 4,
3869  ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START      = 5,
3870  ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP       = 6,
3871  ATOM_TRANSMITTER_ACTION_INIT                    = 7,
3872  ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT          = 8,
3873  ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT           = 9,
3874  ATOM_TRANSMITTER_ACTION_SETUP                   = 10,
3875  ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH            = 11,
3876  ATOM_TRANSMITTER_ACTION_POWER_ON                = 12,
3877  ATOM_TRANSMITTER_ACTION_POWER_OFF               = 13,
3878};
3879
3880// digfe_sel
3881enum atom_dig_transmitter_control_digfe_sel
3882{
3883  ATOM_TRANMSITTER_V6__DIGA_SEL                   = 0x01,
3884  ATOM_TRANMSITTER_V6__DIGB_SEL                   = 0x02,
3885  ATOM_TRANMSITTER_V6__DIGC_SEL                   = 0x04,
3886  ATOM_TRANMSITTER_V6__DIGD_SEL                   = 0x08,
3887  ATOM_TRANMSITTER_V6__DIGE_SEL                   = 0x10,
3888  ATOM_TRANMSITTER_V6__DIGF_SEL                   = 0x20,
3889  ATOM_TRANMSITTER_V6__DIGG_SEL                   = 0x40,
3890};
3891
3892
3893//ucHPDSel
3894enum atom_dig_transmitter_control_hpd_sel
3895{
3896  ATOM_TRANSMITTER_V6_NO_HPD_SEL                  = 0x00,
3897  ATOM_TRANSMITTER_V6_HPD1_SEL                    = 0x01,
3898  ATOM_TRANSMITTER_V6_HPD2_SEL                    = 0x02,
3899  ATOM_TRANSMITTER_V6_HPD3_SEL                    = 0x03,
3900  ATOM_TRANSMITTER_V6_HPD4_SEL                    = 0x04,
3901  ATOM_TRANSMITTER_V6_HPD5_SEL                    = 0x05,
3902  ATOM_TRANSMITTER_V6_HPD6_SEL                    = 0x06,
3903};
3904
3905// ucDPLaneSet
3906enum atom_dig_transmitter_control_dplaneset
3907{
3908  DP_LANE_SET__0DB_0_4V                           = 0x00,
3909  DP_LANE_SET__0DB_0_6V                           = 0x01,
3910  DP_LANE_SET__0DB_0_8V                           = 0x02,
3911  DP_LANE_SET__0DB_1_2V                           = 0x03,
3912  DP_LANE_SET__3_5DB_0_4V                         = 0x08, 
3913  DP_LANE_SET__3_5DB_0_6V                         = 0x09,
3914  DP_LANE_SET__3_5DB_0_8V                         = 0x0a,
3915  DP_LANE_SET__6DB_0_4V                           = 0x10,
3916  DP_LANE_SET__6DB_0_6V                           = 0x11,
3917  DP_LANE_SET__9_5DB_0_4V                         = 0x18, 
3918};
3919
3920
3921
3922/****************************************************************************/ 
3923// Structures used by ExternalEncoderControl V2.4
3924/****************************************************************************/   
3925
3926struct external_encoder_control_parameters_v2_4
3927{
3928  uint16_t pixelclock_10khz;  // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT 
3929  uint8_t  config;            // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT  
3930  uint8_t  action;            // 
3931  uint8_t  encodermode;       // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
3932  uint8_t  lanenum;           // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT  
3933  uint8_t  bitpercolor;       // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
3934  uint8_t  hpd_id;        
3935};
3936
3937
3938// ucAction
3939enum external_encoder_control_action_def
3940{
3941  EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT           = 0x00,
3942  EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT            = 0x01,
3943  EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT             = 0x07,
3944  EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP            = 0x0f,
3945  EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF     = 0x10,
3946  EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING         = 0x11,
3947  EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION        = 0x12,
3948  EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP                = 0x14,
3949};
3950
3951// ucConfig
3952enum external_encoder_control_v2_4_config_def
3953{
3954  EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK          = 0x03,
3955  EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ       = 0x00,
3956  EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ       = 0x01,
3957  EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ       = 0x02,
3958  EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ       = 0x03,  
3959  EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS         = 0x70,
3960  EXTERNAL_ENCODER_CONFIG_V3_ENCODER1                 = 0x00,
3961  EXTERNAL_ENCODER_CONFIG_V3_ENCODER2                 = 0x10,
3962  EXTERNAL_ENCODER_CONFIG_V3_ENCODER3                 = 0x20,
3963};
3964
3965struct external_encoder_control_ps_allocation_v2_4
3966{
3967  struct external_encoder_control_parameters_v2_4 sExtEncoder;
3968  uint32_t reserved[2];
3969};
3970
3971
3972/* 
3973  ***************************************************************************
3974                           AMD ACPI Table
3975  
3976  *************************************************************************** 
3977*/   
3978
3979struct amd_acpi_description_header{
3980  uint32_t signature;
3981  uint32_t tableLength;      //Length
3982  uint8_t  revision;
3983  uint8_t  checksum;
3984  uint8_t  oemId[6];
3985  uint8_t  oemTableId[8];    //UINT64  OemTableId;
3986  uint32_t oemRevision;
3987  uint32_t creatorId;
3988  uint32_t creatorRevision;
3989};
3990
3991struct uefi_acpi_vfct{
3992  struct   amd_acpi_description_header sheader;
3993  uint8_t  tableUUID[16];    //0x24
3994  uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture.
3995  uint32_t lib1Imageoffset;  //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture.
3996  uint32_t reserved[4];      //0x3C
3997};
3998
3999struct vfct_image_header{
4000  uint32_t  pcibus;          //0x4C

4001  uint32_t  pcidevice;       //0x50
4002  uint32_t  pcifunction;     //0x54
4003  uint16_t  vendorid;        //0x58
4004  uint16_t  deviceid;        //0x5A
4005  uint16_t  ssvid;           //0x5C
4006  uint16_t  ssid;            //0x5E
4007  uint32_t  revision;        //0x60
4008  uint32_t  imagelength;     //0x64
4009};
4010
4011
4012struct gop_vbios_content {
4013  struct vfct_image_header vbiosheader;
4014  uint8_t                  vbioscontent[1];
4015};
4016
4017struct gop_lib1_content {
4018  struct vfct_image_header lib1header;
4019  uint8_t                  lib1content[1];
4020};
4021
4022
4023
4024/* 
4025  ***************************************************************************
4026                   Scratch Register definitions
4027  Each number below indicates which scratch regiser request, Active and 
4028  Connect all share the same definitions as display_device_tag defines
4029  *************************************************************************** 
4030*/   
4031
4032enum scratch_register_def{
4033  ATOM_DEVICE_CONNECT_INFO_DEF      = 0,
4034  ATOM_BL_BRI_LEVEL_INFO_DEF        = 2,
4035  ATOM_ACTIVE_INFO_DEF              = 3,
4036  ATOM_LCD_INFO_DEF                 = 4,
4037  ATOM_DEVICE_REQ_INFO_DEF          = 5,
4038  ATOM_ACC_CHANGE_INFO_DEF          = 6,
4039  ATOM_PRE_OS_MODE_INFO_DEF         = 7,
4040  ATOM_PRE_OS_ASSERTION_DEF      = 8,    //For GOP to record a 32bit assertion code, this is enabled by default in prodution GOP drivers.
4041  ATOM_INTERNAL_TIMER_INFO_DEF      = 10,
4042};
4043
4044enum scratch_device_connect_info_bit_def{
4045  ATOM_DISPLAY_LCD1_CONNECT           =0x0002,
4046  ATOM_DISPLAY_DFP1_CONNECT           =0x0008,
4047  ATOM_DISPLAY_DFP2_CONNECT           =0x0080,
4048  ATOM_DISPLAY_DFP3_CONNECT           =0x0200,
4049  ATOM_DISPLAY_DFP4_CONNECT           =0x0400,
4050  ATOM_DISPLAY_DFP5_CONNECT           =0x0800,
4051  ATOM_DISPLAY_DFP6_CONNECT           =0x0040,
4052  ATOM_DISPLAY_DFPx_CONNECT           =0x0ec8,
4053  ATOM_CONNECT_INFO_DEVICE_MASK       =0x0fff,
4054};
4055
4056enum scratch_bl_bri_level_info_bit_def{
4057  ATOM_CURRENT_BL_LEVEL_SHIFT         =0x8,
4058#ifndef _H2INC
4059  ATOM_CURRENT_BL_LEVEL_MASK          =0x0000ff00,
4060  ATOM_DEVICE_DPMS_STATE              =0x00010000,
4061#endif
4062};
4063
4064enum scratch_active_info_bits_def{
4065  ATOM_DISPLAY_LCD1_ACTIVE            =0x0002,
4066  ATOM_DISPLAY_DFP1_ACTIVE            =0x0008,
4067  ATOM_DISPLAY_DFP2_ACTIVE            =0x0080,
4068  ATOM_DISPLAY_DFP3_ACTIVE            =0x0200,
4069  ATOM_DISPLAY_DFP4_ACTIVE            =0x0400,
4070  ATOM_DISPLAY_DFP5_ACTIVE            =0x0800,
4071  ATOM_DISPLAY_DFP6_ACTIVE            =0x0040,
4072  ATOM_ACTIVE_INFO_DEVICE_MASK        =0x0fff,
4073};
4074
4075enum scratch_device_req_info_bits_def{
4076  ATOM_DISPLAY_LCD1_REQ               =0x0002,
4077  ATOM_DISPLAY_DFP1_REQ               =0x0008,
4078  ATOM_DISPLAY_DFP2_REQ               =0x0080,
4079  ATOM_DISPLAY_DFP3_REQ               =0x0200,
4080  ATOM_DISPLAY_DFP4_REQ               =0x0400,
4081  ATOM_DISPLAY_DFP5_REQ               =0x0800,
4082  ATOM_DISPLAY_DFP6_REQ               =0x0040,
4083  ATOM_REQ_INFO_DEVICE_MASK           =0x0fff,
4084};
4085
4086enum scratch_acc_change_info_bitshift_def{
4087  ATOM_ACC_CHANGE_ACC_MODE_SHIFT    =4,
4088  ATOM_ACC_CHANGE_LID_STATUS_SHIFT  =6,
4089};
4090
4091enum scratch_acc_change_info_bits_def{
4092  ATOM_ACC_CHANGE_ACC_MODE          =0x00000010,
4093  ATOM_ACC_CHANGE_LID_STATUS        =0x00000040,
4094};
4095
4096enum scratch_pre_os_mode_info_bits_def{
4097  ATOM_PRE_OS_MODE_MASK             =0x00000003,
4098  ATOM_PRE_OS_MODE_VGA              =0x00000000,
4099  ATOM_PRE_OS_MODE_VESA             =0x00000001,
4100  ATOM_PRE_OS_MODE_GOP              =0x00000002,
4101  ATOM_PRE_OS_MODE_PIXEL_DEPTH      =0x0000000C,
4102  ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK=0x000000F0,
4103  ATOM_PRE_OS_MODE_8BIT_PAL_EN      =0x00000100,
4104  ATOM_ASIC_INIT_COMPLETE           =0x00000200,
4105#ifndef _H2INC
4106  ATOM_PRE_OS_MODE_NUMBER_MASK      =0xFFFF0000,
4107#endif
4108};
4109
4110
4111
4112/* 
4113  ***************************************************************************
4114                       ATOM firmware ID header file
4115              !! Please keep it at end of the atomfirmware.h !!
4116  *************************************************************************** 
4117*/   
4118#include "atomfirmwareid.h"
4119#pragma pack()
4120
4121#endif
4122
4123