LXR linux/drivers/gpu/drm/amd/include/dm_pp

   1/*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23#ifndef _DM_PP_INTERFACE_
  24#define _DM_PP_INTERFACE_
  25
  26#include "dm_services_types.h"
  27
  28#define PP_MAX_CLOCK_LEVELS 16
  29
  30enum amd_pp_display_config_type{
  31        AMD_PP_DisplayConfigType_None = 0,
  32        AMD_PP_DisplayConfigType_DP54 ,
  33        AMD_PP_DisplayConfigType_DP432 ,
  34        AMD_PP_DisplayConfigType_DP324 ,
  35        AMD_PP_DisplayConfigType_DP27,
  36        AMD_PP_DisplayConfigType_DP243,
  37        AMD_PP_DisplayConfigType_DP216,
  38        AMD_PP_DisplayConfigType_DP162,
  39        AMD_PP_DisplayConfigType_HDMI6G ,
  40        AMD_PP_DisplayConfigType_HDMI297 ,
  41        AMD_PP_DisplayConfigType_HDMI162,
  42        AMD_PP_DisplayConfigType_LVDS,
  43        AMD_PP_DisplayConfigType_DVI,
  44        AMD_PP_DisplayConfigType_WIRELESS,
  45        AMD_PP_DisplayConfigType_VGA
  46};
  47
  48struct single_display_configuration
  49{
  50        uint32_t controller_index;
  51        uint32_t controller_id;
  52        uint32_t signal_type;
  53        uint32_t display_state;
  54        /* phy id for the primary internal transmitter */
  55        uint8_t primary_transmitter_phyi_d;
  56        /* bitmap with the active lanes */
  57        uint8_t primary_transmitter_active_lanemap;
  58        /* phy id for the secondary internal transmitter (for dual-link dvi) */
  59        uint8_t secondary_transmitter_phy_id;
  60        /* bitmap with the active lanes */
  61        uint8_t secondary_transmitter_active_lanemap;
  62        /* misc phy settings for SMU. */
  63        uint32_t config_flags;
  64        uint32_t display_type;
  65        uint32_t view_resolution_cx;
  66        uint32_t view_resolution_cy;
  67        enum amd_pp_display_config_type displayconfigtype;
  68        uint32_t vertical_refresh; /* for active display */
  69};
  70
  71#define MAX_NUM_DISPLAY 32
  72
  73struct amd_pp_display_configuration {
  74        bool nb_pstate_switch_disable;/* controls NB PState switch */
  75        bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
  76        bool cpu_pstate_disable;
  77        uint32_t cpu_pstate_separation_time;
  78
  79        uint32_t num_display;  /* total number of display*/
  80        uint32_t num_path_including_non_display;
  81        uint32_t crossfire_display_index;
  82        uint32_t min_mem_set_clock;
  83        uint32_t min_core_set_clock;
  84        /* unit 10KHz x bit*/
  85        uint32_t min_bus_bandwidth;
  86        /* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/
  87        uint32_t min_core_set_clock_in_sr;
  88
  89        struct single_display_configuration displays[MAX_NUM_DISPLAY];
  90
  91        uint32_t vrefresh; /* for active display*/
  92
  93        uint32_t min_vblank_time; /* for active display*/
  94        bool multi_monitor_in_sync;
  95        /* Controller Index of primary display - used in MCLK SMC switching hang
  96         * SW Workaround*/
  97        uint32_t crtc_index;
  98        /* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
  99        uint32_t line_time_in_us;
 100        bool invalid_vblank_time;
 101
 102        uint32_t display_clk;
 103        /*
 104         * for given display configuration if multimonitormnsync == false then
 105         * Memory clock DPMS with this latency or below is allowed, DPMS with
 106         * higher latency not allowed.
 107         */
 108        uint32_t dce_tolerable_mclk_in_active_latency;
 109        uint32_t min_dcef_set_clk;
 110        uint32_t min_dcef_deep_sleep_set_clk;
 111};
 112
 113struct amd_pp_simple_clock_info {
 114        uint32_t        engine_max_clock;
 115        uint32_t        memory_max_clock;
 116        uint32_t        level;
 117};
 118
 119enum PP_DAL_POWERLEVEL {
 120        PP_DAL_POWERLEVEL_INVALID = 0,
 121        PP_DAL_POWERLEVEL_ULTRALOW,
 122        PP_DAL_POWERLEVEL_LOW,
 123        PP_DAL_POWERLEVEL_NOMINAL,
 124        PP_DAL_POWERLEVEL_PERFORMANCE,
 125
 126        PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
 127        PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
 128        PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
 129        PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
 130        PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
 131        PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
 132        PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
 133        PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
 134};
 135
 136struct amd_pp_clock_info {
 137        uint32_t min_engine_clock;
 138        uint32_t max_engine_clock;
 139        uint32_t min_memory_clock;
 140        uint32_t max_memory_clock;
 141        uint32_t min_bus_bandwidth;
 142        uint32_t max_bus_bandwidth;
 143        uint32_t max_engine_clock_in_sr;
 144        uint32_t min_engine_clock_in_sr;
 145        enum PP_DAL_POWERLEVEL max_clocks_state;
 146};
 147
 148enum amd_pp_clock_type {
 149        amd_pp_disp_clock = 1,
 150        amd_pp_sys_clock,
 151        amd_pp_mem_clock,
 152        amd_pp_dcef_clock,
 153        amd_pp_soc_clock,
 154        amd_pp_pixel_clock,
 155        amd_pp_phy_clock,
 156        amd_pp_dcf_clock,
 157        amd_pp_dpp_clock,
 158        amd_pp_f_clock = amd_pp_dcef_clock,
 159};
 160
 161#define MAX_NUM_CLOCKS 16
 162
 163struct amd_pp_clocks {
 164        uint32_t count;
 165        uint32_t clock[MAX_NUM_CLOCKS];
 166        uint32_t latency[MAX_NUM_CLOCKS];
 167};
 168
 169struct pp_clock_with_latency {
 170        uint32_t clocks_in_khz;
 171        uint32_t latency_in_us;
 172};
 173
 174struct pp_clock_levels_with_latency {
 175        uint32_t num_levels;
 176        struct pp_clock_with_latency data[PP_MAX_CLOCK_LEVELS];
 177};
 178
 179struct pp_clock_with_voltage {
 180        uint32_t clocks_in_khz;
 181        uint32_t voltage_in_mv;
 182};
 183
 184struct pp_clock_levels_with_voltage {
 185        uint32_t num_levels;
 186        struct pp_clock_with_voltage data[PP_MAX_CLOCK_LEVELS];
 187};
 188
 189struct pp_display_clock_request {
 190        enum amd_pp_clock_type clock_type;
 191        uint32_t clock_freq_in_khz;
 192};
 193
 194#endif /* _DM_PP_INTERFACE_ */
 195