1/* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23/* 24 * This file defines the private interface between the 25 * AMD kernel graphics drivers and the AMD KFD. 26 */ 27 28#ifndef KGD_KFD_INTERFACE_H_INCLUDED 29#define KGD_KFD_INTERFACE_H_INCLUDED 30 31#include <linux/types.h> 32#include <linux/bitmap.h> 33#include <linux/dma-fence.h> 34 35struct pci_dev; 36 37#define KGD_MAX_QUEUES 128 38 39struct kfd_dev; 40struct kgd_dev; 41 42struct kgd_mem; 43 44enum kfd_preempt_type { 45 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN = 0, 46 KFD_PREEMPT_TYPE_WAVEFRONT_RESET, 47 KFD_PREEMPT_TYPE_WAVEFRONT_SAVE 48}; 49 50struct kfd_vm_fault_info { 51 uint64_t page_addr; 52 uint32_t vmid; 53 uint32_t mc_id; 54 uint32_t status; 55 bool prot_valid; 56 bool prot_read; 57 bool prot_write; 58 bool prot_exec; 59}; 60 61struct kfd_cu_info { 62 uint32_t num_shader_engines; 63 uint32_t num_shader_arrays_per_engine; 64 uint32_t num_cu_per_sh; 65 uint32_t cu_active_number; 66 uint32_t cu_ao_mask; 67 uint32_t simd_per_cu; 68 uint32_t max_waves_per_simd; 69 uint32_t wave_front_size; 70 uint32_t max_scratch_slots_per_cu; 71 uint32_t lds_size; 72 uint32_t cu_bitmap[4][4]; 73}; 74 75/* For getting GPU local memory information from KGD */ 76struct kfd_local_mem_info { 77 uint64_t local_mem_size_private; 78 uint64_t local_mem_size_public; 79 uint32_t vram_width; 80 uint32_t mem_clk_max; 81}; 82 83enum kgd_memory_pool { 84 KGD_POOL_SYSTEM_CACHEABLE = 1, 85 KGD_POOL_SYSTEM_WRITECOMBINE = 2, 86 KGD_POOL_FRAMEBUFFER = 3, 87}; 88 89/** 90 * enum kfd_sched_policy 91 * 92 * @KFD_SCHED_POLICY_HWS: H/W scheduling policy known as command processor (cp) 93 * scheduling. In this scheduling mode we're using the firmware code to 94 * schedule the user mode queues and kernel queues such as HIQ and DIQ. 95 * the HIQ queue is used as a special queue that dispatches the configuration 96 * to the cp and the user mode queues list that are currently running. 97 * the DIQ queue is a debugging queue that dispatches debugging commands to the 98 * firmware. 99 * in this scheduling mode user mode queues over subscription feature is 100 * enabled. 101 * 102 * @KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION: The same as above but the over 103 * subscription feature disabled. 104 * 105 * @KFD_SCHED_POLICY_NO_HWS: no H/W scheduling policy is a mode which directly 106 * set the command processor registers and sets the queues "manually". This 107 * mode is used *ONLY* for debugging proposes. 108 * 109 */ 110enum kfd_sched_policy { 111 KFD_SCHED_POLICY_HWS = 0, 112 KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION, 113 KFD_SCHED_POLICY_NO_HWS 114}; 115 116struct kgd2kfd_shared_resources { 117 /* Bit n == 1 means VMID n is available for KFD. */ 118 unsigned int compute_vmid_bitmap; 119 120 /* number of pipes per mec */ 121 uint32_t num_pipe_per_mec; 122 123 /* number of queues per pipe */ 124 uint32_t num_queue_per_pipe; 125 126 /* Bit n == 1 means Queue n is available for KFD */ 127 DECLARE_BITMAP(cp_queue_bitmap, KGD_MAX_QUEUES); 128 129 /* SDMA doorbell assignments (SOC15 and later chips only). Only 130 * specific doorbells are routed to each SDMA engine. Others 131 * are routed to IH and VCN. They are not usable by the CP. 132 */ 133 uint32_t *sdma_doorbell_idx; 134 135 /* From SOC15 onward, the doorbell index range not usable for CP 136 * queues. 137 */ 138 uint32_t non_cp_doorbells_start; 139 uint32_t non_cp_doorbells_end; 140 141 /* Base address of doorbell aperture. */ 142 phys_addr_t doorbell_physical_address; 143 144 /* Size in bytes of doorbell aperture. */ 145 size_t doorbell_aperture_size; 146 147 /* Number of bytes at start of aperture reserved for KGD. */ 148 size_t doorbell_start_offset; 149 150 /* GPUVM address space size in bytes */ 151 uint64_t gpuvm_size; 152 153 /* Minor device number of the render node */ 154 int drm_render_minor; 155 156}; 157 158struct tile_config { 159 uint32_t *tile_config_ptr; 160 uint32_t *macro_tile_config_ptr; 161 uint32_t num_tile_configs; 162 uint32_t num_macro_tile_configs; 163 164 uint32_t gb_addr_config; 165 uint32_t num_banks; 166 uint32_t num_ranks; 167}; 168 169#define KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT 4096 170 171/** 172 * struct kfd2kgd_calls 173 * 174 * @program_sh_mem_settings: A function that should initiate the memory 175 * properties such as main aperture memory type (cache / non cached) and 176 * secondary aperture base address, size and memory type. 177 * This function is used only for no cp scheduling mode. 178 * 179 * @set_pasid_vmid_mapping: Exposes pasid/vmid pair to the H/W for no cp 180 * scheduling mode. Only used for no cp scheduling mode. 181 * 182 * @hqd_load: Loads the mqd structure to a H/W hqd slot. used only for no cp 183 * sceduling mode. 184 * 185 * @hqd_sdma_load: Loads the SDMA mqd structure to a H/W SDMA hqd slot. 186 * used only for no HWS mode. 187 * 188 * @hqd_dump: Dumps CPC HQD registers to an array of address-value pairs. 189 * Array is allocated with kmalloc, needs to be freed with kfree by caller. 190 * 191 * @hqd_sdma_dump: Dumps SDMA HQD registers to an array of address-value pairs. 192 * Array is allocated with kmalloc, needs to be freed with kfree by caller. 193 * 194 * @hqd_is_occupies: Checks if a hqd slot is occupied. 195 * 196 * @hqd_destroy: Destructs and preempts the queue assigned to that hqd slot. 197 * 198 * @hqd_sdma_is_occupied: Checks if an SDMA hqd slot is occupied. 199 * 200 * @hqd_sdma_destroy: Destructs and preempts the SDMA queue assigned to that 201 * SDMA hqd slot. 202 * 203 * @set_scratch_backing_va: Sets VA for scratch backing memory of a VMID. 204 * Only used for no cp scheduling mode 205 * 206 * @set_vm_context_page_table_base: Program page table base for a VMID 207 * 208 * @invalidate_tlbs: Invalidate TLBs for a specific PASID 209 * 210 * @invalidate_tlbs_vmid: Invalidate TLBs for a specific VMID 211 * 212 * @read_vmid_from_vmfault_reg: On Hawaii the VMID is not set in the 213 * IH ring entry. This function allows the KFD ISR to get the VMID 214 * from the fault status register as early as possible. 215 * 216 * @get_cu_occupancy: Function pointer that returns to caller the number 217 * of wave fronts that are in flight for all of the queues of a process 218 * as identified by its pasid. It is important to note that the value 219 * returned by this function is a snapshot of current moment and cannot 220 * guarantee any minimum for the number of waves in-flight. This function 221 * is defined for devices that belong to GFX9 and later GFX families. Care 222 * must be taken in calling this function as it is not defined for devices 223 * that belong to GFX8 and below GFX families. 224 * 225 * This structure contains function pointers to services that the kgd driver 226 * provides to amdkfd driver. 227 * 228 */ 229struct kfd2kgd_calls { 230 /* Register access functions */ 231 void (*program_sh_mem_settings)(struct kgd_dev *kgd, uint32_t vmid, 232 uint32_t sh_mem_config, uint32_t sh_mem_ape1_base, 233 uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases); 234 235 int (*set_pasid_vmid_mapping)(struct kgd_dev *kgd, u32 pasid, 236 unsigned int vmid); 237 238 int (*init_interrupts)(struct kgd_dev *kgd, uint32_t pipe_id); 239 240 int (*hqd_load)(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 241 uint32_t queue_id, uint32_t __user *wptr, 242 uint32_t wptr_shift, uint32_t wptr_mask, 243 struct mm_struct *mm); 244 245 int (*hiq_mqd_load)(struct kgd_dev *kgd, void *mqd, 246 uint32_t pipe_id, uint32_t queue_id, 247 uint32_t doorbell_off); 248 249 int (*hqd_sdma_load)(struct kgd_dev *kgd, void *mqd, 250 uint32_t __user *wptr, struct mm_struct *mm); 251 252 int (*hqd_dump)(struct kgd_dev *kgd, 253 uint32_t pipe_id, uint32_t queue_id, 254 uint32_t (**dump)[2], uint32_t *n_regs); 255 256 int (*hqd_sdma_dump)(struct kgd_dev *kgd, 257 uint32_t engine_id, uint32_t queue_id, 258 uint32_t (**dump)[2], uint32_t *n_regs); 259 260 bool (*hqd_is_occupied)(struct kgd_dev *kgd, uint64_t queue_address, 261 uint32_t pipe_id, uint32_t queue_id); 262 263 int (*hqd_destroy)(struct kgd_dev *kgd, void *mqd, uint32_t reset_type, 264 unsigned int timeout, uint32_t pipe_id, 265 uint32_t queue_id); 266 267 bool (*hqd_sdma_is_occupied)(struct kgd_dev *kgd, void *mqd); 268 269 int (*hqd_sdma_destroy)(struct kgd_dev *kgd, void *mqd, 270 unsigned int timeout); 271 272 int (*address_watch_disable)(struct kgd_dev *kgd); 273 int (*address_watch_execute)(struct kgd_dev *kgd, 274 unsigned int watch_point_id, 275 uint32_t cntl_val, 276 uint32_t addr_hi, 277 uint32_t addr_lo); 278 int (*wave_control_execute)(struct kgd_dev *kgd, 279 uint32_t gfx_index_val, 280 uint32_t sq_cmd); 281 uint32_t (*address_watch_get_offset)(struct kgd_dev *kgd, 282 unsigned int watch_point_id, 283 unsigned int reg_offset); 284 bool (*get_atc_vmid_pasid_mapping_info)( 285 struct kgd_dev *kgd, 286 uint8_t vmid, 287 uint16_t *p_pasid); 288 289 /* No longer needed from GFXv9 onward. The scratch base address is 290 * passed to the shader by the CP. It's the user mode driver's 291 * responsibility. 292 */ 293 void (*set_scratch_backing_va)(struct kgd_dev *kgd, 294 uint64_t va, uint32_t vmid); 295 296 void (*set_vm_context_page_table_base)(struct kgd_dev *kgd, 297 uint32_t vmid, uint64_t page_table_base); 298 uint32_t (*read_vmid_from_vmfault_reg)(struct kgd_dev *kgd); 299 300 void (*get_cu_occupancy)(struct kgd_dev *kgd, int pasid, int *wave_cnt, 301 int *max_waves_per_cu); 302 void (*program_trap_handler_settings)(struct kgd_dev *kgd, 303 uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr); 304}; 305 306#endif /* KGD_KFD_INTERFACE_H_INCLUDED */ 307