LXR linux/drivers/gpu/drm/amd/include/vega10

   1/*
   2 * Copyright (C) 2017  Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included
  12 * in all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20 */
  21#if !defined (_vega10_ENUM_HEADER)
  22#define _vega10_ENUM_HEADER
  23
  24#ifndef _DRIVER_BUILD
  25#ifndef GL_ZERO
  26#define GL__ZERO                      BLEND_ZERO
  27#define GL__ONE                       BLEND_ONE
  28#define GL__SRC_COLOR                 BLEND_SRC_COLOR
  29#define GL__ONE_MINUS_SRC_COLOR       BLEND_ONE_MINUS_SRC_COLOR
  30#define GL__DST_COLOR                 BLEND_DST_COLOR
  31#define GL__ONE_MINUS_DST_COLOR       BLEND_ONE_MINUS_DST_COLOR
  32#define GL__SRC_ALPHA                 BLEND_SRC_ALPHA
  33#define GL__ONE_MINUS_SRC_ALPHA       BLEND_ONE_MINUS_SRC_ALPHA
  34#define GL__DST_ALPHA                 BLEND_DST_ALPHA
  35#define GL__ONE_MINUS_DST_ALPHA       BLEND_ONE_MINUS_DST_ALPHA
  36#define GL__SRC_ALPHA_SATURATE        BLEND_SRC_ALPHA_SATURATE
  37#define GL__CONSTANT_COLOR            BLEND_CONSTANT_COLOR
  38#define GL__ONE_MINUS_CONSTANT_COLOR  BLEND_ONE_MINUS_CONSTANT_COLOR
  39#define GL__CONSTANT_ALPHA            BLEND_CONSTANT_ALPHA
  40#define GL__ONE_MINUS_CONSTANT_ALPHA  BLEND_ONE_MINUS_CONSTANT_ALPHA
  41#endif
  42#endif
  43
  44/*******************************************************
  45 * GDS DATA_TYPE Enums
  46 *******************************************************/
  47
  48#ifndef ENUMS_GDS_PERFCOUNT_SELECT_H
  49#define ENUMS_GDS_PERFCOUNT_SELECT_H
  50typedef enum GDS_PERFCOUNT_SELECT {
  51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
  52 GDS_PERF_SEL_DS_BANK_CONFL = 1,
  53 GDS_PERF_SEL_WBUF_FLUSH = 2,
  54 GDS_PERF_SEL_WR_COMP = 3,
  55 GDS_PERF_SEL_WBUF_WR = 4,
  56 GDS_PERF_SEL_RBUF_HIT = 5,
  57 GDS_PERF_SEL_RBUF_MISS = 6,
  58 GDS_PERF_SEL_SE0_SH0_NORET = 7,
  59 GDS_PERF_SEL_SE0_SH0_RET = 8,
  60 GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9,
  61 GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10,
  62 GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11,
  63 GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12,
  64 GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13,
  65 GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14,
  66 GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15,
  67 GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16,
  68 GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17,
  69 GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18,
  70 GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19,
  71 GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20,
  72 GDS_PERF_SEL_SE0_SH1_NORET = 21,
  73 GDS_PERF_SEL_SE0_SH1_RET = 22,
  74 GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23,
  75 GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24,
  76 GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25,
  77 GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26,
  78 GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27,
  79 GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28,
  80 GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29,
  81 GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30,
  82 GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31,
  83 GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32,
  84 GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33,
  85 GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34,
  86 GDS_PERF_SEL_SE1_SH0_NORET = 35,
  87 GDS_PERF_SEL_SE1_SH0_RET = 36,
  88 GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37,
  89 GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38,
  90 GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39,
  91 GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40,
  92 GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41,
  93 GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42,
  94 GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43,
  95 GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44,
  96 GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45,
  97 GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46,
  98 GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47,
  99 GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48,
 100 GDS_PERF_SEL_SE1_SH1_NORET = 49,
 101 GDS_PERF_SEL_SE1_SH1_RET = 50,
 102 GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51,
 103 GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52,
 104 GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53,
 105 GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54,
 106 GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55,
 107 GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56,
 108 GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57,
 109 GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58,
 110 GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59,
 111 GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP = 60,
 112 GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP = 61,
 113 GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP = 62,
 114 GDS_PERF_SEL_SE2_SH0_NORET = 63,
 115 GDS_PERF_SEL_SE2_SH0_RET = 64,
 116 GDS_PERF_SEL_SE2_SH0_ORD_CNT = 65,
 117 GDS_PERF_SEL_SE2_SH0_2COMP_REQ = 66,
 118 GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID = 67,
 119 GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID = 68,
 120 GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD = 69,
 121 GDS_PERF_SEL_SE2_SH0_GDS_WR_OP = 70,
 122 GDS_PERF_SEL_SE2_SH0_GDS_RD_OP = 71,
 123 GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP = 72,
 124 GDS_PERF_SEL_SE2_SH0_GDS_REL_OP = 73,
 125 GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP = 74,
 126 GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP = 75,
 127 GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP = 76,
 128 GDS_PERF_SEL_SE2_SH1_NORET = 77,
 129 GDS_PERF_SEL_SE2_SH1_RET = 78,
 130 GDS_PERF_SEL_SE2_SH1_ORD_CNT = 79,
 131 GDS_PERF_SEL_SE2_SH1_2COMP_REQ = 80,
 132 GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID = 81,
 133 GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID = 82,
 134 GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD = 83,
 135 GDS_PERF_SEL_SE2_SH1_GDS_WR_OP = 84,
 136 GDS_PERF_SEL_SE2_SH1_GDS_RD_OP = 85,
 137 GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP = 86,
 138 GDS_PERF_SEL_SE2_SH1_GDS_REL_OP = 87,
 139 GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP = 88,
 140 GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP = 89,
 141 GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP = 90,
 142 GDS_PERF_SEL_SE3_SH0_NORET = 91,
 143 GDS_PERF_SEL_SE3_SH0_RET = 92,
 144 GDS_PERF_SEL_SE3_SH0_ORD_CNT = 93,
 145 GDS_PERF_SEL_SE3_SH0_2COMP_REQ = 94,
 146 GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID = 95,
 147 GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID = 96,
 148 GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD = 97,
 149 GDS_PERF_SEL_SE3_SH0_GDS_WR_OP = 98,
 150 GDS_PERF_SEL_SE3_SH0_GDS_RD_OP = 99,
 151 GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP = 100,
 152 GDS_PERF_SEL_SE3_SH0_GDS_REL_OP = 101,
 153 GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP = 102,
 154 GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP = 103,
 155 GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP = 104,
 156 GDS_PERF_SEL_SE3_SH1_NORET = 105,
 157 GDS_PERF_SEL_SE3_SH1_RET = 106,
 158 GDS_PERF_SEL_SE3_SH1_ORD_CNT = 107,
 159 GDS_PERF_SEL_SE3_SH1_2COMP_REQ = 108,
 160 GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID = 109,
 161 GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID = 110,
 162 GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD = 111,
 163 GDS_PERF_SEL_SE3_SH1_GDS_WR_OP = 112,
 164 GDS_PERF_SEL_SE3_SH1_GDS_RD_OP = 113,
 165 GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP = 114,
 166 GDS_PERF_SEL_SE3_SH1_GDS_REL_OP = 115,
 167 GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP = 116,
 168 GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP = 117,
 169 GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP = 118,
 170 GDS_PERF_SEL_GWS_RELEASED = 119,
 171 GDS_PERF_SEL_GWS_BYPASS = 120,
 172} GDS_PERFCOUNT_SELECT;
 173#endif /*ENUMS_GDS_PERFCOUNT_SELECT_H*/
 174
 175/*******************************************************
 176 * Chip Enums
 177 *******************************************************/
 178
 179/*
 180 * MEM_PWR_FORCE_CTRL enum
 181 */
 182
 183typedef enum MEM_PWR_FORCE_CTRL {
 184NO_FORCE_REQUEST                         = 0x00000000,
 185FORCE_LIGHT_SLEEP_REQUEST                = 0x00000001,
 186FORCE_DEEP_SLEEP_REQUEST                 = 0x00000002,
 187FORCE_SHUT_DOWN_REQUEST                  = 0x00000003,
 188} MEM_PWR_FORCE_CTRL;
 189
 190/*
 191 * MEM_PWR_FORCE_CTRL2 enum
 192 */
 193
 194typedef enum MEM_PWR_FORCE_CTRL2 {
 195NO_FORCE_REQ                             = 0x00000000,
 196FORCE_LIGHT_SLEEP_REQ                    = 0x00000001,
 197} MEM_PWR_FORCE_CTRL2;
 198
 199/*
 200 * MEM_PWR_DIS_CTRL enum
 201 */
 202
 203typedef enum MEM_PWR_DIS_CTRL {
 204ENABLE_MEM_PWR_CTRL                      = 0x00000000,
 205DISABLE_MEM_PWR_CTRL                     = 0x00000001,
 206} MEM_PWR_DIS_CTRL;
 207
 208/*
 209 * MEM_PWR_SEL_CTRL enum
 210 */
 211
 212typedef enum MEM_PWR_SEL_CTRL {
 213DYNAMIC_SHUT_DOWN_ENABLE                 = 0x00000000,
 214DYNAMIC_DEEP_SLEEP_ENABLE                = 0x00000001,
 215DYNAMIC_LIGHT_SLEEP_ENABLE               = 0x00000002,
 216} MEM_PWR_SEL_CTRL;
 217
 218/*
 219 * MEM_PWR_SEL_CTRL2 enum
 220 */
 221
 222typedef enum MEM_PWR_SEL_CTRL2 {
 223DYNAMIC_DEEP_SLEEP_EN                    = 0x00000000,
 224DYNAMIC_LIGHT_SLEEP_EN                   = 0x00000001,
 225} MEM_PWR_SEL_CTRL2;
 226
 227/*
 228 * RowSize enum
 229 */
 230
 231typedef enum RowSize {
 232ADDR_CONFIG_1KB_ROW                      = 0x00000000,
 233ADDR_CONFIG_2KB_ROW                      = 0x00000001,
 234ADDR_CONFIG_4KB_ROW                      = 0x00000002,
 235} RowSize;
 236
 237/*
 238 * SurfaceEndian enum
 239 */
 240
 241typedef enum SurfaceEndian {
 242ENDIAN_NONE                              = 0x00000000,
 243ENDIAN_8IN16                             = 0x00000001,
 244ENDIAN_8IN32                             = 0x00000002,
 245ENDIAN_8IN64                             = 0x00000003,
 246} SurfaceEndian;
 247
 248/*
 249 * ArrayMode enum
 250 */
 251
 252typedef enum ArrayMode {
 253ARRAY_LINEAR_GENERAL                     = 0x00000000,
 254ARRAY_LINEAR_ALIGNED                     = 0x00000001,
 255ARRAY_1D_TILED_THIN1                     = 0x00000002,
 256ARRAY_1D_TILED_THICK                     = 0x00000003,
 257ARRAY_2D_TILED_THIN1                     = 0x00000004,
 258ARRAY_PRT_TILED_THIN1                    = 0x00000005,
 259ARRAY_PRT_2D_TILED_THIN1                 = 0x00000006,
 260ARRAY_2D_TILED_THICK                     = 0x00000007,
 261ARRAY_2D_TILED_XTHICK                    = 0x00000008,
 262ARRAY_PRT_TILED_THICK                    = 0x00000009,
 263ARRAY_PRT_2D_TILED_THICK                 = 0x0000000a,
 264ARRAY_PRT_3D_TILED_THIN1                 = 0x0000000b,
 265ARRAY_3D_TILED_THIN1                     = 0x0000000c,
 266ARRAY_3D_TILED_THICK                     = 0x0000000d,
 267ARRAY_3D_TILED_XTHICK                    = 0x0000000e,
 268ARRAY_PRT_3D_TILED_THICK                 = 0x0000000f,
 269} ArrayMode;
 270
 271/*
 272 * NumPipes enum
 273 */
 274
 275typedef enum NumPipes {
 276ADDR_CONFIG_1_PIPE                       = 0x00000000,
 277ADDR_CONFIG_2_PIPE                       = 0x00000001,
 278ADDR_CONFIG_4_PIPE                       = 0x00000002,
 279ADDR_CONFIG_8_PIPE                       = 0x00000003,
 280ADDR_CONFIG_16_PIPE                      = 0x00000004,
 281ADDR_CONFIG_32_PIPE                      = 0x00000005,
 282} NumPipes;
 283
 284/*
 285 * NumBanksConfig enum
 286 */
 287
 288typedef enum NumBanksConfig {
 289ADDR_CONFIG_1_BANK                       = 0x00000000,
 290ADDR_CONFIG_2_BANK                       = 0x00000001,
 291ADDR_CONFIG_4_BANK                       = 0x00000002,
 292ADDR_CONFIG_8_BANK                       = 0x00000003,
 293ADDR_CONFIG_16_BANK                      = 0x00000004,
 294} NumBanksConfig;
 295
 296/*
 297 * PipeInterleaveSize enum
 298 */
 299
 300typedef enum PipeInterleaveSize {
 301ADDR_CONFIG_PIPE_INTERLEAVE_256B         = 0x00000000,
 302ADDR_CONFIG_PIPE_INTERLEAVE_512B         = 0x00000001,
 303ADDR_CONFIG_PIPE_INTERLEAVE_1KB          = 0x00000002,
 304ADDR_CONFIG_PIPE_INTERLEAVE_2KB          = 0x00000003,
 305} PipeInterleaveSize;
 306
 307/*
 308 * BankInterleaveSize enum
 309 */
 310
 311typedef enum BankInterleaveSize {
 312ADDR_CONFIG_BANK_INTERLEAVE_1            = 0x00000000,
 313ADDR_CONFIG_BANK_INTERLEAVE_2            = 0x00000001,
 314ADDR_CONFIG_BANK_INTERLEAVE_4            = 0x00000002,
 315ADDR_CONFIG_BANK_INTERLEAVE_8            = 0x00000003,
 316} BankInterleaveSize;
 317
 318/*
 319 * NumShaderEngines enum
 320 */
 321
 322typedef enum NumShaderEngines {
 323ADDR_CONFIG_1_SHADER_ENGINE              = 0x00000000,
 324ADDR_CONFIG_2_SHADER_ENGINE              = 0x00000001,
 325ADDR_CONFIG_4_SHADER_ENGINE              = 0x00000002,
 326ADDR_CONFIG_8_SHADER_ENGINE              = 0x00000003,
 327} NumShaderEngines;
 328
 329/*
 330 * NumRbPerShaderEngine enum
 331 */
 332
 333typedef enum NumRbPerShaderEngine {
 334ADDR_CONFIG_1_RB_PER_SHADER_ENGINE       = 0x00000000,
 335ADDR_CONFIG_2_RB_PER_SHADER_ENGINE       = 0x00000001,
 336ADDR_CONFIG_4_RB_PER_SHADER_ENGINE       = 0x00000002,
 337} NumRbPerShaderEngine;
 338
 339/*
 340 * NumGPUs enum
 341 */
 342
 343typedef enum NumGPUs {
 344ADDR_CONFIG_1_GPU                        = 0x00000000,
 345ADDR_CONFIG_2_GPU                        = 0x00000001,
 346ADDR_CONFIG_4_GPU                        = 0x00000002,
 347ADDR_CONFIG_8_GPU                        = 0x00000003,
 348} NumGPUs;
 349
 350/*
 351 * NumMaxCompressedFragments enum
 352 */
 353
 354typedef enum NumMaxCompressedFragments {
 355ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS   = 0x00000000,
 356ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS   = 0x00000001,
 357ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS   = 0x00000002,
 358ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS   = 0x00000003,
 359} NumMaxCompressedFragments;
 360
 361/*
 362 * ShaderEngineTileSize enum
 363 */
 364
 365typedef enum ShaderEngineTileSize {
 366ADDR_CONFIG_SE_TILE_16                   = 0x00000000,
 367ADDR_CONFIG_SE_TILE_32                   = 0x00000001,
 368} ShaderEngineTileSize;
 369
 370/*
 371 * MultiGPUTileSize enum
 372 */
 373
 374typedef enum MultiGPUTileSize {
 375ADDR_CONFIG_GPU_TILE_16                  = 0x00000000,
 376ADDR_CONFIG_GPU_TILE_32                  = 0x00000001,
 377ADDR_CONFIG_GPU_TILE_64                  = 0x00000002,
 378ADDR_CONFIG_GPU_TILE_128                 = 0x00000003,
 379} MultiGPUTileSize;
 380
 381/*
 382 * NumLowerPipes enum
 383 */
 384
 385typedef enum NumLowerPipes {
 386ADDR_CONFIG_1_LOWER_PIPES                = 0x00000000,
 387ADDR_CONFIG_2_LOWER_PIPES                = 0x00000001,
 388} NumLowerPipes;
 389
 390/*
 391 * ColorTransform enum
 392 */
 393
 394typedef enum ColorTransform {
 395DCC_CT_AUTO                              = 0x00000000,
 396DCC_CT_NONE                              = 0x00000001,
 397ABGR_TO_A_BG_G_RB                        = 0x00000002,
 398BGRA_TO_BG_G_RB_A                        = 0x00000003,
 399} ColorTransform;
 400
 401/*
 402 * CompareRef enum
 403 */
 404
 405typedef enum CompareRef {
 406REF_NEVER                                = 0x00000000,
 407REF_LESS                                 = 0x00000001,
 408REF_EQUAL                                = 0x00000002,
 409REF_LEQUAL                               = 0x00000003,
 410REF_GREATER                              = 0x00000004,
 411REF_NOTEQUAL                             = 0x00000005,
 412REF_GEQUAL                               = 0x00000006,
 413REF_ALWAYS                               = 0x00000007,
 414} CompareRef;
 415
 416/*
 417 * ReadSize enum
 418 */
 419
 420typedef enum ReadSize {
 421READ_256_BITS                            = 0x00000000,
 422READ_512_BITS                            = 0x00000001,
 423} ReadSize;
 424
 425/*
 426 * DepthFormat enum
 427 */
 428
 429typedef enum DepthFormat {
 430DEPTH_INVALID                            = 0x00000000,
 431DEPTH_16                                 = 0x00000001,
 432DEPTH_X8_24                              = 0x00000002,
 433DEPTH_8_24                               = 0x00000003,
 434DEPTH_X8_24_FLOAT                        = 0x00000004,
 435DEPTH_8_24_FLOAT                         = 0x00000005,
 436DEPTH_32_FLOAT                           = 0x00000006,
 437DEPTH_X24_8_32_FLOAT                     = 0x00000007,
 438} DepthFormat;
 439
 440/*
 441 * ZFormat enum
 442 */
 443
 444typedef enum ZFormat {
 445Z_INVALID                                = 0x00000000,
 446Z_16                                     = 0x00000001,
 447Z_24                                     = 0x00000002,
 448Z_32_FLOAT                               = 0x00000003,
 449} ZFormat;
 450
 451/*
 452 * StencilFormat enum
 453 */
 454
 455typedef enum StencilFormat {
 456STENCIL_INVALID                          = 0x00000000,
 457STENCIL_8                                = 0x00000001,
 458} StencilFormat;
 459
 460/*
 461 * CmaskMode enum
 462 */
 463
 464typedef enum CmaskMode {
 465CMASK_CLEAR_NONE                         = 0x00000000,
 466CMASK_CLEAR_ONE                          = 0x00000001,
 467CMASK_CLEAR_ALL                          = 0x00000002,
 468CMASK_ANY_EXPANDED                       = 0x00000003,
 469CMASK_ALPHA0_FRAG1                       = 0x00000004,
 470CMASK_ALPHA0_FRAG2                       = 0x00000005,
 471CMASK_ALPHA0_FRAG4                       = 0x00000006,
 472CMASK_ALPHA0_FRAGS                       = 0x00000007,
 473CMASK_ALPHA1_FRAG1                       = 0x00000008,
 474CMASK_ALPHA1_FRAG2                       = 0x00000009,
 475CMASK_ALPHA1_FRAG4                       = 0x0000000a,
 476CMASK_ALPHA1_FRAGS                       = 0x0000000b,
 477CMASK_ALPHAX_FRAG1                       = 0x0000000c,
 478CMASK_ALPHAX_FRAG2                       = 0x0000000d,
 479CMASK_ALPHAX_FRAG4                       = 0x0000000e,
 480CMASK_ALPHAX_FRAGS                       = 0x0000000f,
 481} CmaskMode;
 482
 483/*
 484 * QuadExportFormat enum
 485 */
 486
 487typedef enum QuadExportFormat {
 488EXPORT_UNUSED                            = 0x00000000,
 489EXPORT_32_R                              = 0x00000001,
 490EXPORT_32_GR                             = 0x00000002,
 491EXPORT_32_AR                             = 0x00000003,
 492EXPORT_FP16_ABGR                         = 0x00000004,
 493EXPORT_UNSIGNED16_ABGR                   = 0x00000005,
 494EXPORT_SIGNED16_ABGR                     = 0x00000006,
 495EXPORT_32_ABGR                           = 0x00000007,
 496EXPORT_32BPP_8PIX                        = 0x00000008,
 497EXPORT_16_16_UNSIGNED_8PIX               = 0x00000009,
 498EXPORT_16_16_SIGNED_8PIX                 = 0x0000000a,
 499EXPORT_16_16_FLOAT_8PIX                  = 0x0000000b,
 500} QuadExportFormat;
 501
 502/*
 503 * QuadExportFormatOld enum
 504 */
 505
 506typedef enum QuadExportFormatOld {
 507EXPORT_4P_32BPC_ABGR                     = 0x00000000,
 508EXPORT_4P_16BPC_ABGR                     = 0x00000001,
 509EXPORT_4P_32BPC_GR                       = 0x00000002,
 510EXPORT_4P_32BPC_AR                       = 0x00000003,
 511EXPORT_2P_32BPC_ABGR                     = 0x00000004,
 512EXPORT_8P_32BPC_R                        = 0x00000005,
 513} QuadExportFormatOld;
 514
 515/*
 516 * ColorFormat enum
 517 */
 518
 519typedef enum ColorFormat {
 520COLOR_INVALID                            = 0x00000000,
 521COLOR_8                                  = 0x00000001,
 522COLOR_16                                 = 0x00000002,
 523COLOR_8_8                                = 0x00000003,
 524COLOR_32                                 = 0x00000004,
 525COLOR_16_16                              = 0x00000005,
 526COLOR_10_11_11                           = 0x00000006,
 527COLOR_11_11_10                           = 0x00000007,
 528COLOR_10_10_10_2                         = 0x00000008,
 529COLOR_2_10_10_10                         = 0x00000009,
 530COLOR_8_8_8_8                            = 0x0000000a,
 531COLOR_32_32                              = 0x0000000b,
 532COLOR_16_16_16_16                        = 0x0000000c,
 533COLOR_RESERVED_13                        = 0x0000000d,
 534COLOR_32_32_32_32                        = 0x0000000e,
 535COLOR_RESERVED_15                        = 0x0000000f,
 536COLOR_5_6_5                              = 0x00000010,
 537COLOR_1_5_5_5                            = 0x00000011,
 538COLOR_5_5_5_1                            = 0x00000012,
 539COLOR_4_4_4_4                            = 0x00000013,
 540COLOR_8_24                               = 0x00000014,
 541COLOR_24_8                               = 0x00000015,
 542COLOR_X24_8_32_FLOAT                     = 0x00000016,
 543COLOR_RESERVED_23                        = 0x00000017,
 544COLOR_RESERVED_24                        = 0x00000018,
 545COLOR_RESERVED_25                        = 0x00000019,
 546COLOR_RESERVED_26                        = 0x0000001a,
 547COLOR_RESERVED_27                        = 0x0000001b,
 548COLOR_RESERVED_28                        = 0x0000001c,
 549COLOR_RESERVED_29                        = 0x0000001d,
 550COLOR_RESERVED_30                        = 0x0000001e,
 551COLOR_2_10_10_10_6E4                     = 0x0000001f,
 552} ColorFormat;
 553
 554/*
 555 * SurfaceFormat enum
 556 */
 557
 558typedef enum SurfaceFormat {
 559FMT_INVALID                              = 0x00000000,
 560FMT_8                                    = 0x00000001,
 561FMT_16                                   = 0x00000002,
 562FMT_8_8                                  = 0x00000003,
 563FMT_32                                   = 0x00000004,
 564FMT_16_16                                = 0x00000005,
 565FMT_10_11_11                             = 0x00000006,
 566FMT_11_11_10                             = 0x00000007,
 567FMT_10_10_10_2                           = 0x00000008,
 568FMT_2_10_10_10                           = 0x00000009,
 569FMT_8_8_8_8                              = 0x0000000a,
 570FMT_32_32                                = 0x0000000b,
 571FMT_16_16_16_16                          = 0x0000000c,
 572FMT_32_32_32                             = 0x0000000d,
 573FMT_32_32_32_32                          = 0x0000000e,
 574FMT_RESERVED_4                           = 0x0000000f,
 575FMT_5_6_5                                = 0x00000010,
 576FMT_1_5_5_5                              = 0x00000011,
 577FMT_5_5_5_1                              = 0x00000012,
 578FMT_4_4_4_4                              = 0x00000013,
 579FMT_8_24                                 = 0x00000014,
 580FMT_24_8                                 = 0x00000015,
 581FMT_X24_8_32_FLOAT                       = 0x00000016,
 582FMT_RESERVED_33                          = 0x00000017,
 583FMT_11_11_10_FLOAT                       = 0x00000018,
 584FMT_16_FLOAT                             = 0x00000019,
 585FMT_32_FLOAT                             = 0x0000001a,
 586FMT_16_16_FLOAT                          = 0x0000001b,
 587FMT_8_24_FLOAT                           = 0x0000001c,
 588FMT_24_8_FLOAT                           = 0x0000001d,
 589FMT_32_32_FLOAT                          = 0x0000001e,
 590FMT_10_11_11_FLOAT                       = 0x0000001f,
 591FMT_16_16_16_16_FLOAT                    = 0x00000020,
 592FMT_3_3_2                                = 0x00000021,
 593FMT_6_5_5                                = 0x00000022,
 594FMT_32_32_32_32_FLOAT                    = 0x00000023,
 595FMT_RESERVED_36                          = 0x00000024,
 596FMT_1                                    = 0x00000025,
 597FMT_1_REVERSED                           = 0x00000026,
 598FMT_GB_GR                                = 0x00000027,
 599FMT_BG_RG                                = 0x00000028,
 600FMT_32_AS_8                              = 0x00000029,
 601FMT_32_AS_8_8                            = 0x0000002a,
 602FMT_5_9_9_9_SHAREDEXP                    = 0x0000002b,
 603FMT_8_8_8                                = 0x0000002c,
 604FMT_16_16_16                             = 0x0000002d,
 605FMT_16_16_16_FLOAT                       = 0x0000002e,
 606FMT_4_4                                  = 0x0000002f,
 607FMT_32_32_32_FLOAT                       = 0x00000030,
 608FMT_BC1                                  = 0x00000031,
 609FMT_BC2                                  = 0x00000032,
 610FMT_BC3                                  = 0x00000033,
 611FMT_BC4                                  = 0x00000034,
 612FMT_BC5                                  = 0x00000035,
 613FMT_BC6                                  = 0x00000036,
 614FMT_BC7                                  = 0x00000037,
 615FMT_32_AS_32_32_32_32                    = 0x00000038,
 616FMT_APC3                                 = 0x00000039,
 617FMT_APC4                                 = 0x0000003a,
 618FMT_APC5                                 = 0x0000003b,
 619FMT_APC6                                 = 0x0000003c,
 620FMT_APC7                                 = 0x0000003d,
 621FMT_CTX1                                 = 0x0000003e,
 622FMT_RESERVED_63                          = 0x0000003f,
 623} SurfaceFormat;
 624
 625/*
 626 * BUF_DATA_FORMAT enum
 627 */
 628
 629typedef enum BUF_DATA_FORMAT {
 630BUF_DATA_FORMAT_INVALID                  = 0x00000000,
 631BUF_DATA_FORMAT_8                        = 0x00000001,
 632BUF_DATA_FORMAT_16                       = 0x00000002,
 633BUF_DATA_FORMAT_8_8                      = 0x00000003,
 634BUF_DATA_FORMAT_32                       = 0x00000004,
 635BUF_DATA_FORMAT_16_16                    = 0x00000005,
 636BUF_DATA_FORMAT_10_11_11                 = 0x00000006,
 637BUF_DATA_FORMAT_11_11_10                 = 0x00000007,
 638BUF_DATA_FORMAT_10_10_10_2               = 0x00000008,
 639BUF_DATA_FORMAT_2_10_10_10               = 0x00000009,
 640BUF_DATA_FORMAT_8_8_8_8                  = 0x0000000a,
 641BUF_DATA_FORMAT_32_32                    = 0x0000000b,
 642BUF_DATA_FORMAT_16_16_16_16              = 0x0000000c,
 643BUF_DATA_FORMAT_32_32_32                 = 0x0000000d,
 644BUF_DATA_FORMAT_32_32_32_32              = 0x0000000e,
 645BUF_DATA_FORMAT_RESERVED_15              = 0x0000000f,
 646} BUF_DATA_FORMAT;
 647
 648/*
 649 * IMG_DATA_FORMAT enum
 650 */
 651
 652typedef enum IMG_DATA_FORMAT {
 653IMG_DATA_FORMAT_INVALID                  = 0x00000000,
 654IMG_DATA_FORMAT_8                        = 0x00000001,
 655IMG_DATA_FORMAT_16                       = 0x00000002,
 656IMG_DATA_FORMAT_8_8                      = 0x00000003,
 657IMG_DATA_FORMAT_32                       = 0x00000004,
 658IMG_DATA_FORMAT_16_16                    = 0x00000005,
 659IMG_DATA_FORMAT_10_11_11                 = 0x00000006,
 660IMG_DATA_FORMAT_11_11_10                 = 0x00000007,
 661IMG_DATA_FORMAT_10_10_10_2               = 0x00000008,
 662IMG_DATA_FORMAT_2_10_10_10               = 0x00000009,
 663IMG_DATA_FORMAT_8_8_8_8                  = 0x0000000a,
 664IMG_DATA_FORMAT_32_32                    = 0x0000000b,
 665IMG_DATA_FORMAT_16_16_16_16              = 0x0000000c,
 666IMG_DATA_FORMAT_32_32_32                 = 0x0000000d,
 667IMG_DATA_FORMAT_32_32_32_32              = 0x0000000e,
 668IMG_DATA_FORMAT_RESERVED_15              = 0x0000000f,
 669IMG_DATA_FORMAT_5_6_5                    = 0x00000010,
 670IMG_DATA_FORMAT_1_5_5_5                  = 0x00000011,
 671IMG_DATA_FORMAT_5_5_5_1                  = 0x00000012,
 672IMG_DATA_FORMAT_4_4_4_4                  = 0x00000013,
 673IMG_DATA_FORMAT_8_24                     = 0x00000014,
 674IMG_DATA_FORMAT_24_8                     = 0x00000015,
 675IMG_DATA_FORMAT_X24_8_32                 = 0x00000016,
 676IMG_DATA_FORMAT_8_AS_8_8_8_8             = 0x00000017,
 677IMG_DATA_FORMAT_ETC2_RGB                 = 0x00000018,
 678IMG_DATA_FORMAT_ETC2_RGBA                = 0x00000019,
 679IMG_DATA_FORMAT_ETC2_R                   = 0x0000001a,
 680IMG_DATA_FORMAT_ETC2_RG                  = 0x0000001b,
 681IMG_DATA_FORMAT_ETC2_RGBA1               = 0x0000001c,
 682IMG_DATA_FORMAT_RESERVED_29              = 0x0000001d,
 683IMG_DATA_FORMAT_RESERVED_30              = 0x0000001e,
 684IMG_DATA_FORMAT_6E4                      = 0x0000001f,
 685IMG_DATA_FORMAT_GB_GR                    = 0x00000020,
 686IMG_DATA_FORMAT_BG_RG                    = 0x00000021,
 687IMG_DATA_FORMAT_5_9_9_9                  = 0x00000022,
 688IMG_DATA_FORMAT_BC1                      = 0x00000023,
 689IMG_DATA_FORMAT_BC2                      = 0x00000024,
 690IMG_DATA_FORMAT_BC3                      = 0x00000025,
 691IMG_DATA_FORMAT_BC4                      = 0x00000026,
 692IMG_DATA_FORMAT_BC5                      = 0x00000027,
 693IMG_DATA_FORMAT_BC6                      = 0x00000028,
 694IMG_DATA_FORMAT_BC7                      = 0x00000029,
 695IMG_DATA_FORMAT_16_AS_32_32              = 0x0000002a,
 696IMG_DATA_FORMAT_16_AS_16_16_16_16        = 0x0000002b,
 697IMG_DATA_FORMAT_16_AS_32_32_32_32        = 0x0000002c,
 698IMG_DATA_FORMAT_FMASK                    = 0x0000002d,
 699IMG_DATA_FORMAT_ASTC_2D_LDR              = 0x0000002e,
 700IMG_DATA_FORMAT_ASTC_2D_HDR              = 0x0000002f,
 701IMG_DATA_FORMAT_ASTC_2D_LDR_SRGB         = 0x00000030,
 702IMG_DATA_FORMAT_ASTC_3D_LDR              = 0x00000031,
 703IMG_DATA_FORMAT_ASTC_3D_HDR              = 0x00000032,
 704IMG_DATA_FORMAT_ASTC_3D_LDR_SRGB         = 0x00000033,
 705IMG_DATA_FORMAT_N_IN_16                  = 0x00000034,
 706IMG_DATA_FORMAT_N_IN_16_16               = 0x00000035,
 707IMG_DATA_FORMAT_N_IN_16_16_16_16         = 0x00000036,
 708IMG_DATA_FORMAT_N_IN_16_AS_16_16_16_16   = 0x00000037,
 709IMG_DATA_FORMAT_RESERVED_56              = 0x00000038,
 710IMG_DATA_FORMAT_4_4                      = 0x00000039,
 711IMG_DATA_FORMAT_6_5_5                    = 0x0000003a,
 712IMG_DATA_FORMAT_RESERVED_59              = 0x0000003b,
 713IMG_DATA_FORMAT_RESERVED_60              = 0x0000003c,
 714IMG_DATA_FORMAT_8_AS_32                  = 0x0000003d,
 715IMG_DATA_FORMAT_8_AS_32_32               = 0x0000003e,
 716IMG_DATA_FORMAT_32_AS_32_32_32_32        = 0x0000003f,
 717} IMG_DATA_FORMAT;
 718
 719/*
 720 * BUF_NUM_FORMAT enum
 721 */
 722
 723typedef enum BUF_NUM_FORMAT {
 724BUF_NUM_FORMAT_UNORM                     = 0x00000000,
 725BUF_NUM_FORMAT_SNORM                     = 0x00000001,
 726BUF_NUM_FORMAT_USCALED                   = 0x00000002,
 727BUF_NUM_FORMAT_SSCALED                   = 0x00000003,
 728BUF_NUM_FORMAT_UINT                      = 0x00000004,
 729BUF_NUM_FORMAT_SINT                      = 0x00000005,
 730BUF_NUM_FORMAT_UNORM_UINT                = 0x00000006,
 731BUF_NUM_FORMAT_FLOAT                     = 0x00000007,
 732} BUF_NUM_FORMAT;
 733
 734/*
 735 * IMG_NUM_FORMAT enum
 736 */
 737
 738typedef enum IMG_NUM_FORMAT {
 739IMG_NUM_FORMAT_UNORM                     = 0x00000000,
 740IMG_NUM_FORMAT_SNORM                     = 0x00000001,
 741IMG_NUM_FORMAT_USCALED                   = 0x00000002,
 742IMG_NUM_FORMAT_SSCALED                   = 0x00000003,
 743IMG_NUM_FORMAT_UINT                      = 0x00000004,
 744IMG_NUM_FORMAT_SINT                      = 0x00000005,
 745IMG_NUM_FORMAT_UNORM_UINT                = 0x00000006,
 746IMG_NUM_FORMAT_FLOAT                     = 0x00000007,
 747IMG_NUM_FORMAT_RESERVED_8                = 0x00000008,
 748IMG_NUM_FORMAT_SRGB                      = 0x00000009,
 749IMG_NUM_FORMAT_RESERVED_10               = 0x0000000a,
 750IMG_NUM_FORMAT_RESERVED_11               = 0x0000000b,
 751IMG_NUM_FORMAT_RESERVED_12               = 0x0000000c,
 752IMG_NUM_FORMAT_RESERVED_13               = 0x0000000d,
 753IMG_NUM_FORMAT_RESERVED_14               = 0x0000000e,
 754IMG_NUM_FORMAT_RESERVED_15               = 0x0000000f,
 755} IMG_NUM_FORMAT;
 756
 757/*
 758 * IMG_NUM_FORMAT_FMASK enum
 759 */
 760
 761typedef enum IMG_NUM_FORMAT_FMASK {
 762IMG_NUM_FORMAT_FMASK_8_2_1               = 0x00000000,
 763IMG_NUM_FORMAT_FMASK_8_4_1               = 0x00000001,
 764IMG_NUM_FORMAT_FMASK_8_8_1               = 0x00000002,
 765IMG_NUM_FORMAT_FMASK_8_2_2               = 0x00000003,
 766IMG_NUM_FORMAT_FMASK_8_4_2               = 0x00000004,
 767IMG_NUM_FORMAT_FMASK_8_4_4               = 0x00000005,
 768IMG_NUM_FORMAT_FMASK_16_16_1             = 0x00000006,
 769IMG_NUM_FORMAT_FMASK_16_8_2              = 0x00000007,
 770IMG_NUM_FORMAT_FMASK_32_16_2             = 0x00000008,
 771IMG_NUM_FORMAT_FMASK_32_8_4              = 0x00000009,
 772IMG_NUM_FORMAT_FMASK_32_8_8              = 0x0000000a,
 773IMG_NUM_FORMAT_FMASK_64_16_4             = 0x0000000b,
 774IMG_NUM_FORMAT_FMASK_64_16_8             = 0x0000000c,
 775IMG_NUM_FORMAT_FMASK_RESERVED_13         = 0x0000000d,
 776IMG_NUM_FORMAT_FMASK_RESERVED_14         = 0x0000000e,
 777IMG_NUM_FORMAT_FMASK_RESERVED_15         = 0x0000000f,
 778} IMG_NUM_FORMAT_FMASK;
 779
 780/*
 781 * IMG_NUM_FORMAT_N_IN_16 enum
 782 */
 783
 784typedef enum IMG_NUM_FORMAT_N_IN_16 {
 785IMG_NUM_FORMAT_N_IN_16_RESERVED_0        = 0x00000000,
 786IMG_NUM_FORMAT_N_IN_16_UNORM_10          = 0x00000001,
 787IMG_NUM_FORMAT_N_IN_16_UNORM_9           = 0x00000002,
 788IMG_NUM_FORMAT_N_IN_16_RESERVED_3        = 0x00000003,
 789IMG_NUM_FORMAT_N_IN_16_UINT_10           = 0x00000004,
 790IMG_NUM_FORMAT_N_IN_16_UINT_9            = 0x00000005,
 791IMG_NUM_FORMAT_N_IN_16_RESERVED_6        = 0x00000006,
 792IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10     = 0x00000007,
 793IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9      = 0x00000008,
 794IMG_NUM_FORMAT_N_IN_16_RESERVED_9        = 0x00000009,
 795IMG_NUM_FORMAT_N_IN_16_RESERVED_10       = 0x0000000a,
 796IMG_NUM_FORMAT_N_IN_16_RESERVED_11       = 0x0000000b,
 797IMG_NUM_FORMAT_N_IN_16_RESERVED_12       = 0x0000000c,
 798IMG_NUM_FORMAT_N_IN_16_RESERVED_13       = 0x0000000d,
 799IMG_NUM_FORMAT_N_IN_16_RESERVED_14       = 0x0000000e,
 800IMG_NUM_FORMAT_N_IN_16_RESERVED_15       = 0x0000000f,
 801} IMG_NUM_FORMAT_N_IN_16;
 802
 803/*
 804 * IMG_NUM_FORMAT_ASTC_2D enum
 805 */
 806
 807typedef enum IMG_NUM_FORMAT_ASTC_2D {
 808IMG_NUM_FORMAT_ASTC_2D_4x4               = 0x00000000,
 809IMG_NUM_FORMAT_ASTC_2D_5x4               = 0x00000001,
 810IMG_NUM_FORMAT_ASTC_2D_5x5               = 0x00000002,
 811IMG_NUM_FORMAT_ASTC_2D_6x5               = 0x00000003,
 812IMG_NUM_FORMAT_ASTC_2D_6x6               = 0x00000004,
 813IMG_NUM_FORMAT_ASTC_2D_8x5               = 0x00000005,
 814IMG_NUM_FORMAT_ASTC_2D_8x6               = 0x00000006,
 815IMG_NUM_FORMAT_ASTC_2D_8x8               = 0x00000007,
 816IMG_NUM_FORMAT_ASTC_2D_10x5              = 0x00000008,
 817IMG_NUM_FORMAT_ASTC_2D_10x6              = 0x00000009,
 818IMG_NUM_FORMAT_ASTC_2D_10x8              = 0x0000000a,
 819IMG_NUM_FORMAT_ASTC_2D_10x10             = 0x0000000b,
 820IMG_NUM_FORMAT_ASTC_2D_12x10             = 0x0000000c,
 821IMG_NUM_FORMAT_ASTC_2D_12x12             = 0x0000000d,
 822IMG_NUM_FORMAT_ASTC_2D_RESERVED_14       = 0x0000000e,
 823IMG_NUM_FORMAT_ASTC_2D_RESERVED_15       = 0x0000000f,
 824} IMG_NUM_FORMAT_ASTC_2D;
 825
 826/*
 827 * IMG_NUM_FORMAT_ASTC_3D enum
 828 */
 829
 830typedef enum IMG_NUM_FORMAT_ASTC_3D {
 831IMG_NUM_FORMAT_ASTC_3D_3x3x3             = 0x00000000,
 832IMG_NUM_FORMAT_ASTC_3D_4x3x3             = 0x00000001,
 833IMG_NUM_FORMAT_ASTC_3D_4x4x3             = 0x00000002,
 834IMG_NUM_FORMAT_ASTC_3D_4x4x4             = 0x00000003,
 835IMG_NUM_FORMAT_ASTC_3D_5x4x4             = 0x00000004,
 836IMG_NUM_FORMAT_ASTC_3D_5x5x4             = 0x00000005,
 837IMG_NUM_FORMAT_ASTC_3D_5x5x5             = 0x00000006,
 838IMG_NUM_FORMAT_ASTC_3D_6x5x5             = 0x00000007,
 839IMG_NUM_FORMAT_ASTC_3D_6x6x5             = 0x00000008,
 840IMG_NUM_FORMAT_ASTC_3D_6x6x6             = 0x00000009,
 841IMG_NUM_FORMAT_ASTC_3D_RESERVED_10       = 0x0000000a,
 842IMG_NUM_FORMAT_ASTC_3D_RESERVED_11       = 0x0000000b,
 843IMG_NUM_FORMAT_ASTC_3D_RESERVED_12       = 0x0000000c,
 844IMG_NUM_FORMAT_ASTC_3D_RESERVED_13       = 0x0000000d,
 845IMG_NUM_FORMAT_ASTC_3D_RESERVED_14       = 0x0000000e,
 846IMG_NUM_FORMAT_ASTC_3D_RESERVED_15       = 0x0000000f,
 847} IMG_NUM_FORMAT_ASTC_3D;
 848
 849/*
 850 * TileType enum
 851 */
 852
 853typedef enum TileType {
 854ARRAY_COLOR_TILE                         = 0x00000000,
 855ARRAY_DEPTH_TILE                         = 0x00000001,
 856} TileType;
 857
 858/*
 859 * NonDispTilingOrder enum
 860 */
 861
 862typedef enum NonDispTilingOrder {
 863ADDR_SURF_MICRO_TILING_DISPLAY           = 0x00000000,
 864ADDR_SURF_MICRO_TILING_NON_DISPLAY       = 0x00000001,
 865} NonDispTilingOrder;
 866
 867/*
 868 * MicroTileMode enum
 869 */
 870
 871typedef enum MicroTileMode {
 872ADDR_SURF_DISPLAY_MICRO_TILING           = 0x00000000,
 873ADDR_SURF_THIN_MICRO_TILING              = 0x00000001,
 874ADDR_SURF_DEPTH_MICRO_TILING             = 0x00000002,
 875ADDR_SURF_ROTATED_MICRO_TILING           = 0x00000003,
 876ADDR_SURF_THICK_MICRO_TILING             = 0x00000004,
 877} MicroTileMode;
 878
 879/*
 880 * TileSplit enum
 881 */
 882
 883typedef enum TileSplit {
 884ADDR_SURF_TILE_SPLIT_64B                 = 0x00000000,
 885ADDR_SURF_TILE_SPLIT_128B                = 0x00000001,
 886ADDR_SURF_TILE_SPLIT_256B                = 0x00000002,
 887ADDR_SURF_TILE_SPLIT_512B                = 0x00000003,
 888ADDR_SURF_TILE_SPLIT_1KB                 = 0x00000004,
 889ADDR_SURF_TILE_SPLIT_2KB                 = 0x00000005,
 890ADDR_SURF_TILE_SPLIT_4KB                 = 0x00000006,
 891} TileSplit;
 892
 893/*
 894 * SampleSplit enum
 895 */
 896
 897typedef enum SampleSplit {
 898ADDR_SURF_SAMPLE_SPLIT_1                 = 0x00000000,
 899ADDR_SURF_SAMPLE_SPLIT_2                 = 0x00000001,
 900ADDR_SURF_SAMPLE_SPLIT_4                 = 0x00000002,
 901ADDR_SURF_SAMPLE_SPLIT_8                 = 0x00000003,
 902} SampleSplit;
 903
 904/*
 905 * PipeConfig enum
 906 */
 907
 908typedef enum PipeConfig {
 909ADDR_SURF_P2                             = 0x00000000,
 910ADDR_SURF_P2_RESERVED0                   = 0x00000001,
 911ADDR_SURF_P2_RESERVED1                   = 0x00000002,
 912ADDR_SURF_P2_RESERVED2                   = 0x00000003,
 913ADDR_SURF_P4_8x16                        = 0x00000004,
 914ADDR_SURF_P4_16x16                       = 0x00000005,
 915ADDR_SURF_P4_16x32                       = 0x00000006,
 916ADDR_SURF_P4_32x32                       = 0x00000007,
 917ADDR_SURF_P8_16x16_8x16                  = 0x00000008,
 918ADDR_SURF_P8_16x32_8x16                  = 0x00000009,
 919ADDR_SURF_P8_32x32_8x16                  = 0x0000000a,
 920ADDR_SURF_P8_16x32_16x16                 = 0x0000000b,
 921ADDR_SURF_P8_32x32_16x16                 = 0x0000000c,
 922ADDR_SURF_P8_32x32_16x32                 = 0x0000000d,
 923ADDR_SURF_P8_32x64_32x32                 = 0x0000000e,
 924ADDR_SURF_P8_RESERVED0                   = 0x0000000f,
 925ADDR_SURF_P16_32x32_8x16                 = 0x00000010,
 926ADDR_SURF_P16_32x32_16x16                = 0x00000011,
 927} PipeConfig;
 928
 929/*
 930 * SeEnable enum
 931 */
 932
 933typedef enum SeEnable {
 934ADDR_CONFIG_DISABLE_SE                   = 0x00000000,
 935ADDR_CONFIG_ENABLE_SE                    = 0x00000001,
 936} SeEnable;
 937
 938/*
 939 * NumBanks enum
 940 */
 941
 942typedef enum NumBanks {
 943ADDR_SURF_2_BANK                         = 0x00000000,
 944ADDR_SURF_4_BANK                         = 0x00000001,
 945ADDR_SURF_8_BANK                         = 0x00000002,
 946ADDR_SURF_16_BANK                        = 0x00000003,
 947} NumBanks;
 948
 949/*
 950 * BankWidth enum
 951 */
 952
 953typedef enum BankWidth {
 954ADDR_SURF_BANK_WIDTH_1                   = 0x00000000,
 955ADDR_SURF_BANK_WIDTH_2                   = 0x00000001,
 956ADDR_SURF_BANK_WIDTH_4                   = 0x00000002,
 957ADDR_SURF_BANK_WIDTH_8                   = 0x00000003,
 958} BankWidth;
 959
 960/*
 961 * BankHeight enum
 962 */
 963
 964typedef enum BankHeight {
 965ADDR_SURF_BANK_HEIGHT_1                  = 0x00000000,
 966ADDR_SURF_BANK_HEIGHT_2                  = 0x00000001,
 967ADDR_SURF_BANK_HEIGHT_4                  = 0x00000002,
 968ADDR_SURF_BANK_HEIGHT_8                  = 0x00000003,
 969} BankHeight;
 970
 971/*
 972 * BankWidthHeight enum
 973 */
 974
 975typedef enum BankWidthHeight {
 976ADDR_SURF_BANK_WH_1                      = 0x00000000,
 977ADDR_SURF_BANK_WH_2                      = 0x00000001,
 978ADDR_SURF_BANK_WH_4                      = 0x00000002,
 979ADDR_SURF_BANK_WH_8                      = 0x00000003,
 980} BankWidthHeight;
 981
 982/*
 983 * MacroTileAspect enum
 984 */
 985
 986typedef enum MacroTileAspect {
 987ADDR_SURF_MACRO_ASPECT_1                 = 0x00000000,
 988ADDR_SURF_MACRO_ASPECT_2                 = 0x00000001,
 989ADDR_SURF_MACRO_ASPECT_4                 = 0x00000002,
 990ADDR_SURF_MACRO_ASPECT_8                 = 0x00000003,
 991} MacroTileAspect;
 992
 993/*
 994 * GATCL1RequestType enum
 995 */
 996
 997typedef enum GATCL1RequestType {
 998GATCL1_TYPE_NORMAL                       = 0x00000000,
 999GATCL1_TYPE_SHOOTDOWN                    = 0x00000001,
1000GATCL1_TYPE_BYPASS                       = 0x00000002,

1001} GATCL1RequestType;
1002
1003/*
1004 * UTCL1RequestType enum
1005 */
1006
1007typedef enum UTCL1RequestType {
1008UTCL1_TYPE_NORMAL                        = 0x00000000,
1009UTCL1_TYPE_SHOOTDOWN                     = 0x00000001,
1010UTCL1_TYPE_BYPASS                        = 0x00000002,
1011} UTCL1RequestType;
1012
1013/*
1014 * UTCL1FaultType enum
1015 */
1016
1017typedef enum UTCL1FaultType {
1018UTCL1_XNACK_SUCCESS                      = 0x00000000,
1019UTCL1_XNACK_RETRY                        = 0x00000001,
1020UTCL1_XNACK_PRT                          = 0x00000002,
1021UTCL1_XNACK_NO_RETRY                     = 0x00000003,
1022} UTCL1FaultType;
1023
1024/*
1025 * TCC_CACHE_POLICIES enum
1026 */
1027
1028typedef enum TCC_CACHE_POLICIES {
1029TCC_CACHE_POLICY_LRU                     = 0x00000000,
1030TCC_CACHE_POLICY_STREAM                  = 0x00000001,
1031} TCC_CACHE_POLICIES;
1032
1033/*
1034 * MTYPE enum
1035 */
1036
1037typedef enum MTYPE {
1038MTYPE_NC                                 = 0x00000000,
1039MTYPE_WC                                 = 0x00000001,
1040MTYPE_RW                                 = 0x00000001,
1041MTYPE_CC                                 = 0x00000002,
1042MTYPE_UC                                 = 0x00000003,
1043} MTYPE;
1044
1045/*
1046 * RMI_CID enum
1047 */
1048
1049typedef enum RMI_CID {
1050RMI_CID_CC                               = 0x00000000,
1051RMI_CID_FC                               = 0x00000001,
1052RMI_CID_CM                               = 0x00000002,
1053RMI_CID_DC                               = 0x00000003,
1054RMI_CID_Z                                = 0x00000004,
1055RMI_CID_S                                = 0x00000005,
1056RMI_CID_TILE                             = 0x00000006,
1057RMI_CID_ZPCPSD                           = 0x00000007,
1058} RMI_CID;
1059
1060/*
1061 * PERFMON_COUNTER_MODE enum
1062 */
1063
1064typedef enum PERFMON_COUNTER_MODE {
1065PERFMON_COUNTER_MODE_ACCUM               = 0x00000000,
1066PERFMON_COUNTER_MODE_ACTIVE_CYCLES       = 0x00000001,
1067PERFMON_COUNTER_MODE_MAX                 = 0x00000002,
1068PERFMON_COUNTER_MODE_DIRTY               = 0x00000003,
1069PERFMON_COUNTER_MODE_SAMPLE              = 0x00000004,
1070PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT  = 0x00000005,
1071PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT  = 0x00000006,
1072PERFMON_COUNTER_MODE_CYCLES_GE_HI        = 0x00000007,
1073PERFMON_COUNTER_MODE_CYCLES_EQ_HI        = 0x00000008,
1074PERFMON_COUNTER_MODE_INACTIVE_CYCLES     = 0x00000009,
1075PERFMON_COUNTER_MODE_RESERVED            = 0x0000000f,
1076} PERFMON_COUNTER_MODE;
1077
1078/*
1079 * PERFMON_SPM_MODE enum
1080 */
1081
1082typedef enum PERFMON_SPM_MODE {
1083PERFMON_SPM_MODE_OFF                     = 0x00000000,
1084PERFMON_SPM_MODE_16BIT_CLAMP             = 0x00000001,
1085PERFMON_SPM_MODE_16BIT_NO_CLAMP          = 0x00000002,
1086PERFMON_SPM_MODE_32BIT_CLAMP             = 0x00000003,
1087PERFMON_SPM_MODE_32BIT_NO_CLAMP          = 0x00000004,
1088PERFMON_SPM_MODE_RESERVED_5              = 0x00000005,
1089PERFMON_SPM_MODE_RESERVED_6              = 0x00000006,
1090PERFMON_SPM_MODE_RESERVED_7              = 0x00000007,
1091PERFMON_SPM_MODE_TEST_MODE_0             = 0x00000008,
1092PERFMON_SPM_MODE_TEST_MODE_1             = 0x00000009,
1093PERFMON_SPM_MODE_TEST_MODE_2             = 0x0000000a,
1094} PERFMON_SPM_MODE;
1095
1096/*
1097 * SurfaceTiling enum
1098 */
1099
1100typedef enum SurfaceTiling {
1101ARRAY_LINEAR                             = 0x00000000,
1102ARRAY_TILED                              = 0x00000001,
1103} SurfaceTiling;
1104
1105/*
1106 * SurfaceArray enum
1107 */
1108
1109typedef enum SurfaceArray {
1110ARRAY_1D                                 = 0x00000000,
1111ARRAY_2D                                 = 0x00000001,
1112ARRAY_3D                                 = 0x00000002,
1113ARRAY_3D_SLICE                           = 0x00000003,
1114} SurfaceArray;
1115
1116/*
1117 * ColorArray enum
1118 */
1119
1120typedef enum ColorArray {
1121ARRAY_2D_ALT_COLOR                       = 0x00000000,
1122ARRAY_2D_COLOR                           = 0x00000001,
1123ARRAY_3D_SLICE_COLOR                     = 0x00000003,
1124} ColorArray;
1125
1126/*
1127 * DepthArray enum
1128 */
1129
1130typedef enum DepthArray {
1131ARRAY_2D_ALT_DEPTH                       = 0x00000000,
1132ARRAY_2D_DEPTH                           = 0x00000001,
1133} DepthArray;
1134
1135/*
1136 * ENUM_NUM_SIMD_PER_CU enum
1137 */
1138
1139typedef enum ENUM_NUM_SIMD_PER_CU {
1140NUM_SIMD_PER_CU                          = 0x00000004,
1141} ENUM_NUM_SIMD_PER_CU;
1142
1143/*
1144 * DSM_ENABLE_ERROR_INJECT enum
1145 */
1146
1147typedef enum DSM_ENABLE_ERROR_INJECT {
1148DSM_ENABLE_ERROR_INJECT_FED_IN           = 0x00000000,
1149DSM_ENABLE_ERROR_INJECT_SINGLE           = 0x00000001,
1150DSM_ENABLE_ERROR_INJECT_DOUBLE           = 0x00000002,
1151DSM_ENABLE_ERROR_INJECT_DOUBLE_LIMITED   = 0x00000003,
1152} DSM_ENABLE_ERROR_INJECT;
1153
1154/*
1155 * DSM_SELECT_INJECT_DELAY enum
1156 */
1157
1158typedef enum DSM_SELECT_INJECT_DELAY {
1159DSM_SELECT_INJECT_DELAY_NO_DELAY         = 0x00000000,
1160DSM_SELECT_INJECT_DELAY_DELAY_ERROR      = 0x00000001,
1161} DSM_SELECT_INJECT_DELAY;
1162
1163/*
1164 * SWIZZLE_TYPE_ENUM enum
1165 */
1166
1167typedef enum SWIZZLE_TYPE_ENUM {
1168SW_Z                                     = 0x00000000,
1169SW_S                                     = 0x00000001,
1170SW_D                                     = 0x00000002,
1171SW_R                                     = 0x00000003,
1172SW_L                                     = 0x00000004,
1173} SWIZZLE_TYPE_ENUM;
1174
1175/*
1176 * TC_MICRO_TILE_MODE enum
1177 */
1178
1179typedef enum TC_MICRO_TILE_MODE {
1180MICRO_TILE_MODE_LINEAR                   = 0x00000000,
1181MICRO_TILE_MODE_ROTATED                  = 0x00000001,
1182MICRO_TILE_MODE_STD_2D                   = 0x00000002,
1183MICRO_TILE_MODE_STD_3D                   = 0x00000003,
1184MICRO_TILE_MODE_DISPLAY_2D               = 0x00000004,
1185MICRO_TILE_MODE_DISPLAY_3D               = 0x00000005,
1186MICRO_TILE_MODE_Z_2D                     = 0x00000006,
1187MICRO_TILE_MODE_Z_3D                     = 0x00000007,
1188} TC_MICRO_TILE_MODE;
1189
1190/*
1191 * SWIZZLE_MODE_ENUM enum
1192 */
1193
1194typedef enum SWIZZLE_MODE_ENUM {
1195SW_LINEAR                                = 0x00000000,
1196SW_256B_S                                = 0x00000001,
1197SW_256B_D                                = 0x00000002,
1198SW_256B_R                                = 0x00000003,
1199SW_4KB_Z                                 = 0x00000004,
1200SW_4KB_S                                 = 0x00000005,
1201SW_4KB_D                                 = 0x00000006,
1202SW_4KB_R                                 = 0x00000007,
1203SW_64KB_Z                                = 0x00000008,
1204SW_64KB_S                                = 0x00000009,
1205SW_64KB_D                                = 0x0000000a,
1206SW_64KB_R                                = 0x0000000b,
1207SW_VAR_Z                                 = 0x0000000c,
1208SW_VAR_S                                 = 0x0000000d,
1209SW_VAR_D                                 = 0x0000000e,
1210SW_VAR_R                                 = 0x0000000f,
1211SW_RESERVED_16                           = 0x00000010,
1212SW_RESERVED_17                           = 0x00000011,
1213SW_RESERVED_18                           = 0x00000012,
1214SW_RESERVED_19                           = 0x00000013,
1215SW_4KB_Z_X                               = 0x00000014,
1216SW_4KB_S_X                               = 0x00000015,
1217SW_4KB_D_X                               = 0x00000016,
1218SW_4KB_R_X                               = 0x00000017,
1219SW_64KB_Z_X                              = 0x00000018,
1220SW_64KB_S_X                              = 0x00000019,
1221SW_64KB_D_X                              = 0x0000001a,
1222SW_64KB_R_X                              = 0x0000001b,
1223SW_VAR_Z_X                               = 0x0000001c,
1224SW_VAR_S_X                               = 0x0000001d,
1225SW_VAR_D_X                               = 0x0000001e,
1226SW_VAR_R_X                               = 0x0000001f,
1227SW_RESERVED_12                           = 0x00000020,
1228SW_RESERVED_13                           = 0x00000021,
1229SW_RESERVED_14                           = 0x00000022,
1230SW_RESERVED_15                           = 0x00000023,
1231} SWIZZLE_MODE_ENUM;
1232
1233/*
1234 * PipeTiling enum
1235 */
1236
1237typedef enum PipeTiling {
1238CONFIG_1_PIPE                            = 0x00000000,
1239CONFIG_2_PIPE                            = 0x00000001,
1240CONFIG_4_PIPE                            = 0x00000002,
1241CONFIG_8_PIPE                            = 0x00000003,
1242} PipeTiling;
1243
1244/*
1245 * BankTiling enum
1246 */
1247
1248typedef enum BankTiling {
1249CONFIG_4_BANK                            = 0x00000000,
1250CONFIG_8_BANK                            = 0x00000001,
1251} BankTiling;
1252
1253/*
1254 * GroupInterleave enum
1255 */
1256
1257typedef enum GroupInterleave {
1258CONFIG_256B_GROUP                        = 0x00000000,
1259CONFIG_512B_GROUP                        = 0x00000001,
1260} GroupInterleave;
1261
1262/*
1263 * RowTiling enum
1264 */
1265
1266typedef enum RowTiling {
1267CONFIG_1KB_ROW                           = 0x00000000,
1268CONFIG_2KB_ROW                           = 0x00000001,
1269CONFIG_4KB_ROW                           = 0x00000002,
1270CONFIG_8KB_ROW                           = 0x00000003,
1271CONFIG_1KB_ROW_OPT                       = 0x00000004,
1272CONFIG_2KB_ROW_OPT                       = 0x00000005,
1273CONFIG_4KB_ROW_OPT                       = 0x00000006,
1274CONFIG_8KB_ROW_OPT                       = 0x00000007,
1275} RowTiling;
1276
1277/*
1278 * BankSwapBytes enum
1279 */
1280
1281typedef enum BankSwapBytes {
1282CONFIG_128B_SWAPS                        = 0x00000000,
1283CONFIG_256B_SWAPS                        = 0x00000001,
1284CONFIG_512B_SWAPS                        = 0x00000002,
1285CONFIG_1KB_SWAPS                         = 0x00000003,
1286} BankSwapBytes;
1287
1288/*
1289 * SampleSplitBytes enum
1290 */
1291
1292typedef enum SampleSplitBytes {
1293CONFIG_1KB_SPLIT                         = 0x00000000,
1294CONFIG_2KB_SPLIT                         = 0x00000001,
1295CONFIG_4KB_SPLIT                         = 0x00000002,
1296CONFIG_8KB_SPLIT                         = 0x00000003,
1297} SampleSplitBytes;
1298
1299/*******************************************************
1300 * AZSTREAM Enums
1301 *******************************************************/
1302
1303/*
1304 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR enum
1305 */
1306
1307typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR {
1308OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET  = 0x00000000,
1309OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET  = 0x00000001,
1310} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR;
1311
1312/*
1313 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR enum
1314 */
1315
1316typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR {
1317OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET  = 0x00000000,
1318OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET  = 0x00000001,
1319} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR;
1320
1321/*
1322 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS enum
1323 */
1324
1325typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS {
1326OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET  = 0x00000000,
1327OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET  = 0x00000001,
1328} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS;
1329
1330/*
1331 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY enum
1332 */
1333
1334typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY {
1335OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY  = 0x00000000,
1336OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY  = 0x00000001,
1337} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY;
1338
1339/*
1340 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE enum
1341 */
1342
1343typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE {
1344OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED  = 0x00000000,
1345OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED  = 0x00000001,
1346} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE;
1347
1348/*
1349 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE enum
1350 */
1351
1352typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE {
1353OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED  = 0x00000000,
1354OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED  = 0x00000001,
1355} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE;
1356
1357/*
1358 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE enum
1359 */
1360
1361typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE {
1362OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED  = 0x00000000,
1363OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED  = 0x00000001,
1364} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE;
1365
1366/*
1367 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN enum
1368 */
1369
1370typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN {
1371OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN  = 0x00000000,
1372OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN  = 0x00000001,
1373} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN;
1374
1375/*
1376 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET enum
1377 */
1378
1379typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET {
1380OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET  = 0x00000000,
1381OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET  = 0x00000001,
1382} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET;
1383
1384/*
1385 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE enum
1386 */
1387
1388typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE {
1389OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ  = 0x00000000,
1390OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ  = 0x00000001,
1391} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE;
1392
1393/*
1394 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE enum
1395 */
1396
1397typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE {
1398OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1  = 0x00000000,
1399OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2  = 0x00000001,
1400OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED  = 0x00000002,
1401OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4  = 0x00000003,
1402OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED  = 0x00000004,
1403} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE;
1404
1405/*
1406 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR enum
1407 */
1408
1409typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR {
1410OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1  = 0x00000000,
1411OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED  = 0x00000001,
1412OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3  = 0x00000002,
1413OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED  = 0x00000003,
1414OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED  = 0x00000004,
1415OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED  = 0x00000005,
1416OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED  = 0x00000006,
1417OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED  = 0x00000007,
1418} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR;
1419
1420/*
1421 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE enum
1422 */
1423
1424typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE {
1425OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED  = 0x00000000,
1426OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16  = 0x00000001,
1427OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20  = 0x00000002,
1428OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24  = 0x00000003,
1429OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED  = 0x00000004,
1430OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED  = 0x00000005,
1431} OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE;
1432
1433/*
1434 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS enum
1435 */
1436
1437typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS {
1438OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1  = 0x00000000,
1439OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2  = 0x00000001,
1440OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3  = 0x00000002,
1441OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4  = 0x00000003,
1442OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5  = 0x00000004,
1443OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6  = 0x00000005,
1444OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7  = 0x00000006,
1445OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8  = 0x00000007,
1446OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED  = 0x00000008,
1447OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED  = 0x00000009,
1448OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED  = 0x0000000a,
1449OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED  = 0x0000000b,
1450OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED  = 0x0000000c,
1451OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED  = 0x0000000d,
1452OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED  = 0x0000000e,
1453OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED  = 0x0000000f,
1454} OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS;
1455
1456/*******************************************************
1457 * BLNDV Enums
1458 *******************************************************/
1459
1460/*
1461 * BLNDV_CONTROL_BLND_MODE enum
1462 */
1463
1464typedef enum BLNDV_CONTROL_BLND_MODE {
1465BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x00000000,
1466BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY  = 0x00000001,
1467BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x00000002,
1468BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x00000003,
1469} BLNDV_CONTROL_BLND_MODE;
1470
1471/*
1472 * BLNDV_CONTROL_BLND_STEREO_TYPE enum
1473 */
1474
1475typedef enum BLNDV_CONTROL_BLND_STEREO_TYPE {
1476BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO = 0x00000000,
1477BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO = 0x00000001,
1478BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO = 0x00000002,
1479BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED    = 0x00000003,
1480} BLNDV_CONTROL_BLND_STEREO_TYPE;
1481
1482/*
1483 * BLNDV_CONTROL_BLND_STEREO_POLARITY enum
1484 */
1485
1486typedef enum BLNDV_CONTROL_BLND_STEREO_POLARITY {
1487BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW   = 0x00000000,
1488BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH  = 0x00000001,
1489} BLNDV_CONTROL_BLND_STEREO_POLARITY;
1490
1491/*
1492 * BLNDV_CONTROL_BLND_FEEDTHROUGH_EN enum
1493 */
1494
1495typedef enum BLNDV_CONTROL_BLND_FEEDTHROUGH_EN {
1496BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE  = 0x00000000,
1497BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE   = 0x00000001,
1498} BLNDV_CONTROL_BLND_FEEDTHROUGH_EN;
1499
1500/*
1501 * BLNDV_CONTROL_BLND_ALPHA_MODE enum
1502 */
1503
1504typedef enum BLNDV_CONTROL_BLND_ALPHA_MODE {
1505BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0x00000000,
1506BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 0x00000001,
1507BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x00000002,
1508BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED     = 0x00000003,
1509} BLNDV_CONTROL_BLND_ALPHA_MODE;
1510
1511/*
1512 * BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY enum
1513 */
1514
1515typedef enum BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY {
1516BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_FALSE  = 0x00000000,
1517BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_TRUE  = 0x00000001,
1518} BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY;
1519
1520/*
1521 * BLNDV_CONTROL_BLND_MULTIPLIED_MODE enum
1522 */
1523
1524typedef enum BLNDV_CONTROL_BLND_MULTIPLIED_MODE {
1525BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0x00000000,
1526BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE  = 0x00000001,
1527} BLNDV_CONTROL_BLND_MULTIPLIED_MODE;
1528
1529/*
1530 * BLNDV_SM_CONTROL2_SM_MODE enum
1531 */
1532
1533typedef enum BLNDV_SM_CONTROL2_SM_MODE {
1534BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE   = 0x00000000,
1535BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x00000002,
1536BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x00000004,
1537BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING = 0x00000006,
1538} BLNDV_SM_CONTROL2_SM_MODE;
1539
1540/*
1541 * BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE enum
1542 */
1543
1544typedef enum BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE {
1545BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x00000000,
1546BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x00000001,
1547} BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE;
1548
1549/*
1550 * BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE enum
1551 */
1552
1553typedef enum BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE {
1554BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x00000000,
1555BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x00000001,
1556} BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE;
1557
1558/*
1559 * BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL enum
1560 */
1561
1562typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
1563BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0x00000000,
1564BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED = 0x00000001,
1565BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 0x00000002,
1566BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 0x00000003,
1567} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;
1568
1569/*
1570 * BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL enum
1571 */
1572
1573typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
1574BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x00000000,
1575BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x00000001,
1576BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x00000002,
1577BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 0x00000003,
1578} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;
1579
1580/*
1581 * BLNDV_CONTROL2_PTI_ENABLE enum
1582 */
1583
1584typedef enum BLNDV_CONTROL2_PTI_ENABLE {
1585BLNDV_CONTROL2_PTI_ENABLE_FALSE          = 0x00000000,
1586BLNDV_CONTROL2_PTI_ENABLE_TRUE           = 0x00000001,
1587} BLNDV_CONTROL2_PTI_ENABLE;
1588
1589/*
1590 * BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN enum
1591 */
1592
1593typedef enum BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
1594BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x00000000,
1595BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x00000001,
1596} BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;
1597
1598/*
1599 * BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN enum
1600 */
1601
1602typedef enum BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
1603BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x00000000,
1604BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x00000001,
1605} BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN;
1606
1607/*
1608 * BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK enum
1609 */
1610
1611typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
1612BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE = 0x00000000,
1613BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE = 0x00000001,
1614} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;
1615
1616/*
1617 * BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK enum
1618 */
1619
1620typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
1621BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE = 0x00000000,
1622BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE = 0x00000001,
1623} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;
1624
1625/*
1626 * BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK enum
1627 */
1628
1629typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
1630BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE = 0x00000000,
1631BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE = 0x00000001,
1632} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;
1633
1634/*
1635 * BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK enum
1636 */
1637
1638typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
1639BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE = 0x00000000,
1640BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE = 0x00000001,
1641} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;
1642
1643/*
1644 * BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK enum
1645 */
1646
1647typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
1648BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE = 0x00000000,
1649BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE = 0x00000001,
1650} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;
1651
1652/*
1653 * BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK enum
1654 */
1655
1656typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
1657BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE = 0x00000000,
1658BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE = 0x00000001,
1659} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;
1660
1661/*
1662 * BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK enum
1663 */
1664
1665typedef enum BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
1666BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x00000000,
1667BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x00000001,
1668} BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;
1669
1670/*
1671 * BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK enum
1672 */
1673
1674typedef enum BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
1675BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0x00000000,
1676BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x00000001,
1677} BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;
1678
1679/*
1680 * BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE enum
1681 */
1682
1683typedef enum BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
1684BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0x00000000,
1685BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x00000001,
1686} BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;
1687
1688/*
1689 * BLNDV_DEBUG_BLND_CNV_MUX_SELECT enum
1690 */
1691
1692typedef enum BLNDV_DEBUG_BLND_CNV_MUX_SELECT {
1693BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW      = 0x00000000,
1694BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH     = 0x00000001,
1695} BLNDV_DEBUG_BLND_CNV_MUX_SELECT;
1696
1697/*
1698 * BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN enum
1699 */
1700
1701typedef enum BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
1702BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
1703BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
1704} BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;
1705
1706/*******************************************************
1707 * LBV Enums
1708 *******************************************************/
1709
1710/*
1711 * LBV_PIXEL_DEPTH enum
1712 */
1713
1714typedef enum LBV_PIXEL_DEPTH {
1715PIXEL_DEPTH_30BPP                        = 0x00000000,
1716PIXEL_DEPTH_24BPP                        = 0x00000001,
1717PIXEL_DEPTH_18BPP                        = 0x00000002,
1718PIXEL_DEPTH_38BPP                        = 0x00000003,
1719} LBV_PIXEL_DEPTH;
1720
1721/*
1722 * LBV_PIXEL_EXPAN_MODE enum
1723 */
1724
1725typedef enum LBV_PIXEL_EXPAN_MODE {
1726PIXEL_EXPAN_MODE_ZERO_EXP                = 0x00000000,
1727PIXEL_EXPAN_MODE_DYN_EXP                 = 0x00000001,
1728} LBV_PIXEL_EXPAN_MODE;
1729
1730/*
1731 * LBV_INTERLEAVE_EN enum
1732 */
1733
1734typedef enum LBV_INTERLEAVE_EN {
1735INTERLEAVE_DIS                           = 0x00000000,
1736INTERLEAVE_EN                            = 0x00000001,
1737} LBV_INTERLEAVE_EN;
1738
1739/*
1740 * LBV_PIXEL_REDUCE_MODE enum
1741 */
1742
1743typedef enum LBV_PIXEL_REDUCE_MODE {
1744PIXEL_REDUCE_MODE_TRUNCATION             = 0x00000000,
1745PIXEL_REDUCE_MODE_ROUNDING               = 0x00000001,
1746} LBV_PIXEL_REDUCE_MODE;
1747
1748/*
1749 * LBV_DYNAMIC_PIXEL_DEPTH enum
1750 */
1751
1752typedef enum LBV_DYNAMIC_PIXEL_DEPTH {
1753DYNAMIC_PIXEL_DEPTH_36BPP                = 0x00000000,
1754DYNAMIC_PIXEL_DEPTH_30BPP                = 0x00000001,
1755} LBV_DYNAMIC_PIXEL_DEPTH;
1756
1757/*
1758 * LBV_DITHER_EN enum
1759 */
1760
1761typedef enum LBV_DITHER_EN {
1762DITHER_DIS                               = 0x00000000,
1763DITHER_EN                                = 0x00000001,
1764} LBV_DITHER_EN;
1765
1766/*
1767 * LBV_DOWNSCALE_PREFETCH_EN enum
1768 */
1769
1770typedef enum LBV_DOWNSCALE_PREFETCH_EN {
1771DOWNSCALE_PREFETCH_DIS                   = 0x00000000,
1772DOWNSCALE_PREFETCH_EN                    = 0x00000001,
1773} LBV_DOWNSCALE_PREFETCH_EN;
1774
1775/*
1776 * LBV_MEMORY_CONFIG enum
1777 */
1778
1779typedef enum LBV_MEMORY_CONFIG {
1780MEMORY_CONFIG_0                          = 0x00000000,
1781MEMORY_CONFIG_1                          = 0x00000001,
1782MEMORY_CONFIG_2                          = 0x00000002,
1783MEMORY_CONFIG_3                          = 0x00000003,
1784} LBV_MEMORY_CONFIG;
1785
1786/*
1787 * LBV_SYNC_RESET_SEL2 enum
1788 */
1789
1790typedef enum LBV_SYNC_RESET_SEL2 {
1791SYNC_RESET_SEL2_VBLANK                   = 0x00000000,
1792SYNC_RESET_SEL2_VSYNC                    = 0x00000001,
1793} LBV_SYNC_RESET_SEL2;
1794
1795/*
1796 * LBV_SYNC_DURATION enum
1797 */
1798
1799typedef enum LBV_SYNC_DURATION {
1800SYNC_DURATION_16                         = 0x00000000,
1801SYNC_DURATION_32                         = 0x00000001,
1802SYNC_DURATION_64                         = 0x00000002,
1803SYNC_DURATION_128                        = 0x00000003,
1804} LBV_SYNC_DURATION;
1805
1806/*******************************************************
1807 * CRTC Enums
1808 *******************************************************/
1809
1810/*
1811 * CRTC_CONTROL_CRTC_START_POINT_CNTL enum
1812 */
1813
1814typedef enum CRTC_CONTROL_CRTC_START_POINT_CNTL {
1815CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL = 0x00000000,
1816CRTC_CONTROL_CRTC_START_POINT_CNTL_DP    = 0x00000001,
1817} CRTC_CONTROL_CRTC_START_POINT_CNTL;
1818
1819/*
1820 * CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL enum
1821 */
1822
1823typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL {
1824CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL = 0x00000000,
1825CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP   = 0x00000001,
1826} CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL;
1827
1828/*
1829 * CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL enum
1830 */
1831
1832typedef enum CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL {
1833CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE  = 0x00000000,
1834CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT  = 0x00000001,
1835CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED  = 0x00000002,
1836CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST  = 0x00000003,
1837} CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL;
1838
1839/*
1840 * CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY enum
1841 */
1842
1843typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY {
1844CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE  = 0x00000000,
1845CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE  = 0x00000001,
1846} CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY;
1847
1848/*
1849 * CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE enum
1850 */
1851
1852typedef enum CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE {
1853CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE  = 0x00000000,
1854CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE  = 0x00000001,
1855} CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE;
1856
1857/*
1858 * CRTC_CONTROL_CRTC_SOF_PULL_EN enum
1859 */
1860
1861typedef enum CRTC_CONTROL_CRTC_SOF_PULL_EN {
1862CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE      = 0x00000000,
1863CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE       = 0x00000001,
1864} CRTC_CONTROL_CRTC_SOF_PULL_EN;
1865
1866/*
1867 * CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL enum
1868 */
1869
1870typedef enum CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL {
1871CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE  = 0x00000000,
1872CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE  = 0x00000001,
1873} CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL;
1874
1875/*
1876 * CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL enum
1877 */
1878
1879typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL {
1880CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE  = 0x00000000,
1881CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE  = 0x00000001,
1882} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL;
1883
1884/*
1885 * CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL enum
1886 */
1887
1888typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL {
1889CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE  = 0x00000000,
1890CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE  = 0x00000001,
1891} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL;
1892
1893/*
1894 * CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN enum
1895 */
1896
1897typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN {
1898CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE  = 0x00000000,
1899CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE  = 0x00000001,
1900} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN;
1901
1902/*
1903 * CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC enum
1904 */
1905
1906typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC {
1907CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0x00000000,
1908CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE  = 0x00000001,
1909} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC;
1910
1911/*
1912 * CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT enum
1913 */
1914
1915typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT {
1916CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE = 0x00000000,
1917CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE  = 0x00000001,
1918} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT;
1919
1920/*
1921 * CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK enum
1922 */
1923
1924typedef enum CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK {
1925CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE = 0x00000000,
1926CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE  = 0x00000001,
1927} CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK;
1928
1929/*
1930 * CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR enum
1931 */
1932
1933typedef enum CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR {
1934CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE = 0x00000000,
1935CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE  = 0x00000001,
1936} CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR;
1937
1938/*
1939 * CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL enum
1940 */
1941
1942typedef enum CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL {
1943CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE  = 0x00000000,
1944CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE  = 0x00000001,
1945} CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL;
1946
1947/*
1948 * CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN enum
1949 */
1950
1951typedef enum CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN {
1952CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE  = 0x00000000,
1953CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE  = 0x00000001,
1954} CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN;
1955
1956/*
1957 * CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT enum
1958 */
1959
1960typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT {
1961CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER  = 0x00000001,
1962CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER  = 0x00000002,
1963CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF  = 0x00000005,
1964CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE  = 0x00000006,
1965CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA  = 0x00000007,
1966CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA  = 0x00000008,
1967CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB  = 0x00000009,
1968CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB  = 0x0000000a,
1969CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1  = 0x0000000b,
1970CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2  = 0x0000000c,
1971CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD  = 0x0000000d,
1972CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC  = 0x0000000e,
1973CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0  = 0x00000010,
1974CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1  = 0x00000011,
1975CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2  = 0x00000012,
1976CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON  = 0x00000013,
1977CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA  = 0x00000014,
1978CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB  = 0x00000015,
1979CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW  = 0x00000016,
1980CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW  = 0x00000017,
1981} CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT;
1982
1983/*
1984 * CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT enum
1985 */
1986
1987typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT {
1988CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE  = 0x00000001,
1989CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA  = 0x00000002,
1990CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB  = 0x00000003,
1991CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA  = 0x00000004,
1992CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB  = 0x00000005,
1993CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO  = 0x00000006,
1994CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC  = 0x00000007,
1995} CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT;
1996
1997/*
1998 * CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN enum
1999 */
2000

2001typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN {
2002CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE  = 0x00000000,
2003CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE  = 0x00000001,
2004} CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN;
2005
2006/*
2007 * CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR enum
2008 */
2009
2010typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR {
2011CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE   = 0x00000000,
2012CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE    = 0x00000001,
2013} CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR;
2014
2015/*
2016 * CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT enum
2017 */
2018
2019typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT {
2020CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER  = 0x00000001,
2021CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER  = 0x00000002,
2022CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF  = 0x00000005,
2023CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE  = 0x00000006,
2024CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA  = 0x00000007,
2025CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA  = 0x00000008,
2026CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB  = 0x00000009,
2027CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB  = 0x0000000a,
2028CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1  = 0x0000000b,
2029CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2  = 0x0000000c,
2030CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD  = 0x0000000d,
2031CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC  = 0x0000000e,
2032CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0  = 0x00000010,
2033CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1  = 0x00000011,
2034CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2  = 0x00000012,
2035CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON  = 0x00000013,
2036CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA  = 0x00000014,
2037CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB  = 0x00000015,
2038CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW  = 0x00000016,
2039CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW  = 0x00000017,
2040} CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT;
2041
2042/*
2043 * CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT enum
2044 */
2045
2046typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT {
2047CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE  = 0x00000001,
2048CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA  = 0x00000002,
2049CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB  = 0x00000003,
2050CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA  = 0x00000004,
2051CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB  = 0x00000005,
2052CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO  = 0x00000006,
2053CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC  = 0x00000007,
2054} CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT;
2055
2056/*
2057 * CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN enum
2058 */
2059
2060typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN {
2061CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE  = 0x00000000,
2062CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE  = 0x00000001,
2063} CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN;
2064
2065/*
2066 * CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR enum
2067 */
2068
2069typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR {
2070CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE   = 0x00000000,
2071CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE    = 0x00000001,
2072} CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR;
2073
2074/*
2075 * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE enum
2076 */
2077
2078typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE {
2079CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE  = 0x00000000,
2080CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT  = 0x00000001,
2081CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT  = 0x00000002,
2082CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED  = 0x00000003,
2083} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE;
2084
2085/*
2086 * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK enum
2087 */
2088
2089typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK {
2090CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE  = 0x00000000,
2091CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE  = 0x00000001,
2092} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK;
2093
2094/*
2095 * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL enum
2096 */
2097
2098typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL {
2099CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE  = 0x00000000,
2100CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE  = 0x00000001,
2101} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL;
2102
2103/*
2104 * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR enum
2105 */
2106
2107typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR {
2108CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE = 0x00000000,
2109CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE  = 0x00000001,
2110} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR;
2111
2112/*
2113 * CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT enum
2114 */
2115
2116typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT {
2117CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0  = 0x00000000,
2118CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF  = 0x00000001,
2119CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE  = 0x00000002,
2120CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1  = 0x00000003,
2121CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2  = 0x00000004,
2122CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA  = 0x00000005,
2123CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK  = 0x00000006,
2124CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA  = 0x00000007,
2125CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK  = 0x00000008,
2126CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK  = 0x00000009,
2127CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL  = 0x0000000a,
2128CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1  = 0x0000000b,
2129CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB  = 0x0000000c,
2130CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA  = 0x0000000d,
2131CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD  = 0x0000000e,
2132CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC  = 0x0000000f,
2133} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT;
2134
2135/*
2136 * CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY enum
2137 */
2138
2139typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY {
2140CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE  = 0x00000000,
2141CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE  = 0x00000001,
2142} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY;
2143
2144/*
2145 * CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY enum
2146 */
2147
2148typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY {
2149CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE  = 0x00000000,
2150CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE  = 0x00000001,
2151} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY;
2152
2153/*
2154 * CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE enum
2155 */
2156
2157typedef enum CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE {
2158CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO  = 0x00000000,
2159CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT  = 0x00000001,
2160CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT  = 0x00000002,
2161CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED  = 0x00000003,
2162} CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE;
2163
2164/*
2165 * CRTC_CONTROL_CRTC_MASTER_EN enum
2166 */
2167
2168typedef enum CRTC_CONTROL_CRTC_MASTER_EN {
2169CRTC_CONTROL_CRTC_MASTER_EN_FALSE        = 0x00000000,
2170CRTC_CONTROL_CRTC_MASTER_EN_TRUE         = 0x00000001,
2171} CRTC_CONTROL_CRTC_MASTER_EN;
2172
2173/*
2174 * CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN enum
2175 */
2176
2177typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN {
2178CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE  = 0x00000000,
2179CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE  = 0x00000001,
2180} CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN;
2181
2182/*
2183 * CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE enum
2184 */
2185
2186typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE {
2187CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE  = 0x00000000,
2188CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE  = 0x00000001,
2189} CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE;
2190
2191/*
2192 * CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE enum
2193 */
2194
2195typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE {
2196CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE  = 0x00000000,
2197CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE  = 0x00000001,
2198} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE;
2199
2200/*
2201 * CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD enum
2202 */
2203
2204typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD {
2205CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT  = 0x00000000,
2206CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD  = 0x00000001,
2207CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN  = 0x00000002,
2208CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2  = 0x00000003,
2209} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD;
2210
2211/*
2212 * CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY enum
2213 */
2214
2215typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY {
2216CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE  = 0x00000000,
2217CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE  = 0x00000001,
2218} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY;
2219
2220/*
2221 * CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT enum
2222 */
2223
2224typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT {
2225CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE  = 0x00000000,
2226CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE  = 0x00000001,
2227} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT;
2228
2229/*
2230 * CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN enum
2231 */
2232
2233typedef enum CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN {
2234CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE  = 0x00000000,
2235CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE  = 0x00000001,
2236} CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN;
2237
2238/*
2239 * CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE enum
2240 */
2241
2242typedef enum CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE {
2243CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0x00000000,
2244CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE  = 0x00000001,
2245} CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE;
2246
2247/*
2248 * CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR enum
2249 */
2250
2251typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR {
2252CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0x00000000,
2253CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE  = 0x00000001,
2254} CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR;
2255
2256/*
2257 * CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE enum
2258 */
2259
2260typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE {
2261CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE  = 0x00000000,
2262CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA  = 0x00000001,
2263CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB  = 0x00000002,
2264CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED  = 0x00000003,
2265} CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE;
2266
2267/*
2268 * CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY enum
2269 */
2270
2271typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY {
2272CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE  = 0x00000000,
2273CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE  = 0x00000001,
2274} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY;
2275
2276/*
2277 * CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY enum
2278 */
2279
2280typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY {
2281CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE  = 0x00000000,
2282CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE  = 0x00000001,
2283} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY;
2284
2285/*
2286 * CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY enum
2287 */
2288
2289typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY {
2290CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE  = 0x00000000,
2291CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE  = 0x00000001,
2292} CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY;
2293
2294/*
2295 * CRTC_STEREO_CONTROL_CRTC_STEREO_EN enum
2296 */
2297
2298typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EN {
2299CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE  = 0x00000000,
2300CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE  = 0x00000001,
2301} CRTC_STEREO_CONTROL_CRTC_STEREO_EN;
2302
2303/*
2304 * CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR enum
2305 */
2306
2307typedef enum CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR {
2308CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE = 0x00000000,
2309CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE  = 0x00000001,
2310} CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR;
2311
2312/*
2313 * CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL enum
2314 */
2315
2316typedef enum CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL {
2317CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE  = 0x00000000,
2318CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA  = 0x00000001,
2319CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB  = 0x00000002,
2320CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED  = 0x00000003,
2321} CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL;
2322
2323/*
2324 * CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY enum
2325 */
2326
2327typedef enum CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY {
2328CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE = 0x00000000,
2329CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE  = 0x00000001,
2330} CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY;
2331
2332/*
2333 * CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY enum
2334 */
2335
2336typedef enum CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY {
2337CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE = 0x00000000,
2338CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE  = 0x00000001,
2339} CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY;
2340
2341/*
2342 * CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN enum
2343 */
2344
2345typedef enum CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN {
2346CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE  = 0x00000000,
2347CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE  = 0x00000001,
2348} CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN;
2349
2350/*
2351 * CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN enum
2352 */
2353
2354typedef enum CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN {
2355CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE  = 0x00000000,
2356CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE  = 0x00000001,
2357} CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN;
2358
2359/*
2360 * CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK enum
2361 */
2362
2363typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK {
2364CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE  = 0x00000000,
2365CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE  = 0x00000001,
2366} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK;
2367
2368/*
2369 * CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE enum
2370 */
2371
2372typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE {
2373CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE  = 0x00000000,
2374CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE  = 0x00000001,
2375} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE;
2376
2377/*
2378 * CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK enum
2379 */
2380
2381typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK {
2382CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE  = 0x00000000,
2383CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE  = 0x00000001,
2384} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK;
2385
2386/*
2387 * CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE enum
2388 */
2389
2390typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE {
2391CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE  = 0x00000000,
2392CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE  = 0x00000001,
2393} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE;
2394
2395/*
2396 * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK enum
2397 */
2398
2399typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK {
2400CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE  = 0x00000000,
2401CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE  = 0x00000001,
2402} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK;
2403
2404/*
2405 * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE enum
2406 */
2407
2408typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE {
2409CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE  = 0x00000000,
2410CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE  = 0x00000001,
2411} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE;
2412
2413/*
2414 * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK enum
2415 */
2416
2417typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK {
2418CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE  = 0x00000000,
2419CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE  = 0x00000001,
2420} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK;
2421
2422/*
2423 * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE enum
2424 */
2425
2426typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE {
2427CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE  = 0x00000000,
2428CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE  = 0x00000001,
2429} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE;
2430
2431/*
2432 * CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK enum
2433 */
2434
2435typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK {
2436CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE  = 0x00000000,
2437CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE  = 0x00000001,
2438} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK;
2439
2440/*
2441 * CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE enum
2442 */
2443
2444typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE {
2445CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE  = 0x00000000,
2446CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE  = 0x00000001,
2447} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE;
2448
2449/*
2450 * CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK enum
2451 */
2452
2453typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK {
2454CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE  = 0x00000000,
2455CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE  = 0x00000001,
2456} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK;
2457
2458/*
2459 * CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE enum
2460 */
2461
2462typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE {
2463CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE  = 0x00000000,
2464CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE  = 0x00000001,
2465} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE;
2466
2467/*
2468 * CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK enum
2469 */
2470
2471typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK {
2472CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE  = 0x00000000,
2473CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE  = 0x00000001,
2474} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK;
2475
2476/*
2477 * CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE enum
2478 */
2479
2480typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE {
2481CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE  = 0x00000000,
2482CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE  = 0x00000001,
2483} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE;
2484
2485/*
2486 * CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK enum
2487 */
2488
2489typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK {
2490CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE  = 0x00000000,
2491CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE  = 0x00000001,
2492} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK;
2493
2494/*
2495 * CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE enum
2496 */
2497
2498typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE {
2499CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE  = 0x00000000,
2500CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE  = 0x00000001,
2501} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE;
2502
2503/*
2504 * CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK enum
2505 */
2506
2507typedef enum CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK {
2508CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE  = 0x00000000,
2509CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE   = 0x00000001,
2510} CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK;
2511
2512/*
2513 * CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY enum
2514 */
2515
2516typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY {
2517CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE  = 0x00000000,
2518CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE  = 0x00000001,
2519} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY;
2520
2521/*
2522 * CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN enum
2523 */
2524
2525typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN {
2526CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE  = 0x00000000,
2527CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE  = 0x00000001,
2528} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN;
2529
2530/*
2531 * CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE enum
2532 */
2533
2534typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE {
2535CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_0  = 0x00000000,
2536CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_1  = 0x00000001,
2537} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE;
2538
2539/*
2540 * CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE enum
2541 */
2542
2543typedef enum CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE {
2544CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE  = 0x00000000,
2545CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE  = 0x00000001,
2546} CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE;
2547
2548/*
2549 * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN enum
2550 */
2551
2552typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN {
2553CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE  = 0x00000000,
2554CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE  = 0x00000001,
2555} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN;
2556
2557/*
2558 * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE enum
2559 */
2560
2561typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE {
2562CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB  = 0x00000000,
2563CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601  = 0x00000001,
2564CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709  = 0x00000002,
2565CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS  = 0x00000003,
2566CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS  = 0x00000004,
2567CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB  = 0x00000005,
2568CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB  = 0x00000006,
2569CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS  = 0x00000007,
2570} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE;
2571
2572/*
2573 * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE enum
2574 */
2575
2576typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE {
2577CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE  = 0x00000000,
2578CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE  = 0x00000001,
2579} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE;
2580
2581/*
2582 * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT enum
2583 */
2584
2585typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT {
2586CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC  = 0x00000000,
2587CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC  = 0x00000001,
2588CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC  = 0x00000002,
2589CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED  = 0x00000003,
2590} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT;
2591
2592/*
2593 * MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK enum
2594 */
2595
2596typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {
2597MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE  = 0x00000000,
2598MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE  = 0x00000001,
2599} MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK;
2600
2601/*
2602 * MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK enum
2603 */
2604
2605typedef enum MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK {
2606MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE  = 0x00000000,
2607MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE  = 0x00000001,
2608} MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK;
2609
2610/*
2611 * MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK enum
2612 */
2613
2614typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK {
2615MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE  = 0x00000000,
2616MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE  = 0x00000001,
2617} MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK;
2618
2619/*
2620 * MASTER_UPDATE_MODE_MASTER_UPDATE_MODE enum
2621 */
2622
2623typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_MODE {
2624MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN  = 0x00000000,
2625MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA  = 0x00000001,
2626MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA  = 0x00000002,
2627MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE  = 0x00000003,
2628} MASTER_UPDATE_MODE_MASTER_UPDATE_MODE;
2629
2630/*
2631 * MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE enum
2632 */
2633
2634typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {
2635MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH  = 0x00000000,
2636MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN  = 0x00000001,
2637MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD  = 0x00000002,
2638MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED  = 0x00000003,
2639} MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE;
2640
2641/*
2642 * CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE enum
2643 */
2644
2645typedef enum CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE {
2646CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE  = 0x00000000,
2647CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG  = 0x00000001,
2648CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL  = 0x00000002,
2649} CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE;
2650
2651/*
2652 * CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR enum
2653 */
2654
2655typedef enum CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR {
2656CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE = 0x00000000,
2657CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE  = 0x00000001,
2658} CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR;
2659
2660/*
2661 * CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR enum
2662 */
2663
2664typedef enum CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR {
2665CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE = 0x00000000,
2666CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE  = 0x00000001,
2667} CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR;
2668
2669/*
2670 * CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR enum
2671 */
2672
2673typedef enum CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR {
2674CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE = 0x00000000,
2675CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE  = 0x00000001,
2676} CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR;
2677
2678/*
2679 * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY enum
2680 */
2681
2682typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {
2683CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE  = 0x00000000,
2684CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE  = 0x00000001,
2685} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY;
2686
2687/*
2688 * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE enum
2689 */
2690
2691typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE {
2692CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0x00000000,
2693CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE  = 0x00000001,
2694} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE;
2695
2696/*
2697 * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR enum
2698 */
2699
2700typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR {
2701CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0x00000000,
2702CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE  = 0x00000001,
2703} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR;
2704
2705/*
2706 * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE enum
2707 */
2708
2709typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE {
2710CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE  = 0x00000000,
2711CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE  = 0x00000001,
2712} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE;
2713
2714/*
2715 * CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR enum
2716 */
2717
2718typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR {
2719CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0x00000000,
2720CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE  = 0x00000001,
2721} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR;
2722
2723/*
2724 * CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE enum
2725 */
2726
2727typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE {
2728CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0x00000000,
2729CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE  = 0x00000001,
2730} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE;
2731
2732/*
2733 * CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE enum
2734 */
2735
2736typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE {
2737CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE  = 0x00000000,
2738CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE  = 0x00000001,
2739} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE;
2740
2741/*
2742 * CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR enum
2743 */
2744
2745typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR {
2746CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0x00000000,
2747CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE  = 0x00000001,
2748} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR;
2749
2750/*
2751 * CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE enum
2752 */
2753
2754typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE {
2755CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0x00000000,
2756CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE  = 0x00000001,
2757} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE;
2758
2759/*
2760 * CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE enum
2761 */
2762
2763typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE {
2764CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE  = 0x00000000,
2765CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE  = 0x00000001,
2766} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE;
2767
2768/*
2769 * CRTC_CRC_CNTL_CRTC_CRC_EN enum
2770 */
2771
2772typedef enum CRTC_CRC_CNTL_CRTC_CRC_EN {
2773CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE          = 0x00000000,
2774CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE           = 0x00000001,
2775} CRTC_CRC_CNTL_CRTC_CRC_EN;
2776
2777/*
2778 * CRTC_CRC_CNTL_CRTC_CRC_CONT_EN enum
2779 */
2780
2781typedef enum CRTC_CRC_CNTL_CRTC_CRC_CONT_EN {
2782CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE     = 0x00000000,
2783CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE      = 0x00000001,
2784} CRTC_CRC_CNTL_CRTC_CRC_CONT_EN;
2785
2786/*
2787 * CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE enum
2788 */
2789
2790typedef enum CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE {
2791CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT  = 0x00000000,
2792CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT  = 0x00000001,
2793CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES  = 0x00000002,
2794CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS  = 0x00000003,
2795} CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE;
2796
2797/*
2798 * CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE enum
2799 */
2800
2801typedef enum CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE {
2802CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP  = 0x00000000,
2803CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM  = 0x00000001,
2804CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM  = 0x00000002,
2805CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD  = 0x00000003,
2806} CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE;
2807
2808/*
2809 * CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS enum
2810 */
2811
2812typedef enum CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS {
2813CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0x00000000,
2814CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE  = 0x00000001,
2815} CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS;
2816
2817/*
2818 * CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT enum
2819 */
2820
2821typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT {
2822CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB  = 0x00000000,
2823CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B  = 0x00000001,
2824CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB  = 0x00000002,
2825CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B  = 0x00000003,
2826CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB  = 0x00000004,
2827CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B  = 0x00000005,
2828CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB  = 0x00000006,
2829CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B  = 0x00000007,
2830} CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT;
2831
2832/*
2833 * CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT enum
2834 */
2835
2836typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT {
2837CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB  = 0x00000000,
2838CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B  = 0x00000001,
2839CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB  = 0x00000002,
2840CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B  = 0x00000003,
2841CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB  = 0x00000004,
2842CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B  = 0x00000005,
2843CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB  = 0x00000006,
2844CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B  = 0x00000007,
2845} CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT;
2846
2847/*
2848 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE enum
2849 */
2850
2851typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE {
2852CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_DISABLE  = 0x00000000,
2853CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_ONESHOT  = 0x00000001,
2854CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_CONTINUOUS  = 0x00000002,
2855CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_RESERVED  = 0x00000003,
2856} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE;
2857
2858/*
2859 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE enum
2860 */
2861
2862typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE {
2863CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE  = 0x00000000,
2864CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE  = 0x00000001,
2865} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE;
2866
2867/*
2868 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE enum
2869 */
2870
2871typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE {
2872CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE  = 0x00000000,
2873CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE  = 0x00000001,
2874} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE;
2875
2876/*
2877 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW enum
2878 */
2879
2880typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW {
2881CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel  = 0x00000000,
2882CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel  = 0x00000001,
2883CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel  = 0x00000002,
2884CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel  = 0x00000003,
2885} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW;
2886
2887/*
2888 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE enum
2889 */
2890
2891typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE {
2892CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE  = 0x00000000,
2893CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE  = 0x00000001,
2894} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE;
2895
2896/*
2897 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE enum
2898 */
2899
2900typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE {
2901CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE = 0x00000000,
2902CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE  = 0x00000001,
2903} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE;
2904
2905/*
2906 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY enum
2907 */
2908
2909typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY {
2910CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE  = 0x00000000,
2911CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE  = 0x00000001,
2912} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY;
2913
2914/*
2915 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY enum
2916 */
2917
2918typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY {
2919CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE  = 0x00000000,
2920CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE  = 0x00000001,
2921} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY;
2922
2923/*
2924 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE enum
2925 */
2926
2927typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE {
2928CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE  = 0x00000000,
2929CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE  = 0x00000001,
2930} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE;
2931
2932/*
2933 * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE enum
2934 */
2935
2936typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE {
2937CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE  = 0x00000000,
2938CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE  = 0x00000001,
2939} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE;
2940
2941/*
2942 * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR enum
2943 */
2944
2945typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR {
2946CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE = 0x00000000,
2947CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE  = 0x00000001,
2948} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR;
2949
2950/*
2951 * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE enum
2952 */
2953
2954typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE {
2955CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE  = 0x00000000,
2956CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE  = 0x00000001,
2957} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE;
2958
2959/*
2960 * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT enum
2961 */
2962
2963typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT {
2964CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME  = 0x00000000,
2965CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME  = 0x00000001,
2966CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME  = 0x00000002,
2967CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME  = 0x00000003,
2968CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME  = 0x00000004,
2969CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME  = 0x00000005,
2970CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME  = 0x00000006,
2971CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME  = 0x00000007,
2972} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT;
2973
2974/*
2975 * CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE enum
2976 */
2977
2978typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE {
2979CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_FALSE  = 0x00000000,
2980CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_TRUE  = 0x00000001,
2981} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE;
2982
2983/*
2984 * CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR enum
2985 */
2986
2987typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR {
2988CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_FALSE = 0x00000000,
2989CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_TRUE  = 0x00000001,
2990} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR;
2991
2992/*
2993 * CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE enum
2994 */
2995
2996typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE {
2997CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_FALSE  = 0x00000000,
2998CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_TRUE  = 0x00000001,
2999} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE;
3000

3001/*
3002 * CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE enum
3003 */
3004
3005typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE {
3006CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE  = 0x00000000,
3007CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE  = 0x00000001,
3008} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE;
3009
3010/*
3011 * CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR enum
3012 */
3013
3014typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR {
3015CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE = 0x00000000,
3016CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE  = 0x00000001,
3017} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR;
3018
3019/*
3020 * CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE enum
3021 */
3022
3023typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE {
3024CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE  = 0x00000000,
3025CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE  = 0x00000001,
3026} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE;
3027
3028/*
3029 * CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE enum
3030 */
3031
3032typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE {
3033CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE  = 0x00000000,
3034CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE  = 0x00000001,
3035} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE;
3036
3037/*
3038 * CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR enum
3039 */
3040
3041typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR {
3042CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE = 0x00000000,
3043CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE  = 0x00000001,
3044} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR;
3045
3046/*
3047 * CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE enum
3048 */
3049
3050typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE {
3051CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE  = 0x00000000,
3052CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE  = 0x00000001,
3053} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE;
3054
3055/*
3056 * CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE enum
3057 */
3058
3059typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE {
3060CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_FALSE  = 0x00000000,
3061CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_TRUE  = 0x00000001,
3062} CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE;
3063
3064/*
3065 * CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE enum
3066 */
3067
3068typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE {
3069CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_OFF  = 0x00000000,
3070CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_ON  = 0x00000001,
3071} CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE;
3072
3073/*
3074 * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN enum
3075 */
3076
3077typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN {
3078CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE  = 0x00000000,
3079CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE  = 0x00000001,
3080} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN;
3081
3082/*
3083 * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB enum
3084 */
3085
3086typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB {
3087CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE  = 0x00000000,
3088CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE  = 0x00000001,
3089} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB;
3090
3091/*
3092 * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE enum
3093 */
3094
3095typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE {
3096CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH  = 0x00000000,
3097CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE  = 0x00000001,
3098CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE  = 0x00000002,
3099CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED  = 0x00000003,
3100} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE;
3101
3102/*
3103 * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR enum
3104 */
3105
3106typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR {
3107CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE  = 0x00000000,
3108CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE  = 0x00000001,
3109} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR;
3110
3111/*
3112 * CRTC_V_SYNC_A_POL enum
3113 */
3114
3115typedef enum CRTC_V_SYNC_A_POL {
3116CRTC_V_SYNC_A_POL_HIGH                   = 0x00000000,
3117CRTC_V_SYNC_A_POL_LOW                    = 0x00000001,
3118} CRTC_V_SYNC_A_POL;
3119
3120/*
3121 * CRTC_H_SYNC_A_POL enum
3122 */
3123
3124typedef enum CRTC_H_SYNC_A_POL {
3125CRTC_H_SYNC_A_POL_HIGH                   = 0x00000000,
3126CRTC_H_SYNC_A_POL_LOW                    = 0x00000001,
3127} CRTC_H_SYNC_A_POL;
3128
3129/*
3130 * CRTC_HORZ_REPETITION_COUNT enum
3131 */
3132
3133typedef enum CRTC_HORZ_REPETITION_COUNT {
3134CRTC_HORZ_REPETITION_COUNT_0             = 0x00000000,
3135CRTC_HORZ_REPETITION_COUNT_1             = 0x00000001,
3136CRTC_HORZ_REPETITION_COUNT_2             = 0x00000002,
3137CRTC_HORZ_REPETITION_COUNT_3             = 0x00000003,
3138CRTC_HORZ_REPETITION_COUNT_4             = 0x00000004,
3139CRTC_HORZ_REPETITION_COUNT_5             = 0x00000005,
3140CRTC_HORZ_REPETITION_COUNT_6             = 0x00000006,
3141CRTC_HORZ_REPETITION_COUNT_7             = 0x00000007,
3142CRTC_HORZ_REPETITION_COUNT_8             = 0x00000008,
3143CRTC_HORZ_REPETITION_COUNT_9             = 0x00000009,
3144CRTC_HORZ_REPETITION_COUNT_10            = 0x0000000a,
3145CRTC_HORZ_REPETITION_COUNT_11            = 0x0000000b,
3146CRTC_HORZ_REPETITION_COUNT_12            = 0x0000000c,
3147CRTC_HORZ_REPETITION_COUNT_13            = 0x0000000d,
3148CRTC_HORZ_REPETITION_COUNT_14            = 0x0000000e,
3149CRTC_HORZ_REPETITION_COUNT_15            = 0x0000000f,
3150} CRTC_HORZ_REPETITION_COUNT;
3151
3152/*
3153 * CRTC_DRR_MODE_DBUF_UPDATE_MODE enum
3154 */
3155
3156typedef enum CRTC_DRR_MODE_DBUF_UPDATE_MODE {
3157CRTC_DRR_MODE_DBUF_UPDATE_MODE_00_IMMEDIATE  = 0x00000000,
3158CRTC_DRR_MODE_DBUF_UPDATE_MODE_01_MANUAL  = 0x00000001,
3159CRTC_DRR_MODE_DBUF_UPDATE_MODE_10_DBUF   = 0x00000002,
3160CRTC_DRR_MODE_DBUF_UPDATE_MODE_11_SYNCED_DBUF  = 0x00000003,
3161} CRTC_DRR_MODE_DBUF_UPDATE_MODE;
3162
3163/*******************************************************
3164 * FMT Enums
3165 *******************************************************/
3166
3167/*
3168 * FMT_CONTROL_PIXEL_ENCODING enum
3169 */
3170
3171typedef enum FMT_CONTROL_PIXEL_ENCODING {
3172FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444  = 0x00000000,
3173FMT_CONTROL_PIXEL_ENCODING_YCBCR422      = 0x00000001,
3174FMT_CONTROL_PIXEL_ENCODING_YCBCR420      = 0x00000002,
3175FMT_CONTROL_PIXEL_ENCODING_RESERVED      = 0x00000003,
3176} FMT_CONTROL_PIXEL_ENCODING;
3177
3178/*
3179 * FMT_CONTROL_SUBSAMPLING_MODE enum
3180 */
3181
3182typedef enum FMT_CONTROL_SUBSAMPLING_MODE {
3183FMT_CONTROL_SUBSAMPLING_MODE_DROP        = 0x00000000,
3184FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE     = 0x00000001,
3185FMT_CONTROL_SUBSAMPLING_MOME_3_TAP       = 0x00000002,
3186FMT_CONTROL_SUBSAMPLING_MOME_RESERVED    = 0x00000003,
3187} FMT_CONTROL_SUBSAMPLING_MODE;
3188
3189/*
3190 * FMT_CONTROL_SUBSAMPLING_ORDER enum
3191 */
3192
3193typedef enum FMT_CONTROL_SUBSAMPLING_ORDER {
3194FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR  = 0x00000000,
3195FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB  = 0x00000001,
3196} FMT_CONTROL_SUBSAMPLING_ORDER;
3197
3198/*
3199 * FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS enum
3200 */
3201
3202typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS {
3203FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE  = 0x00000000,
3204FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE  = 0x00000001,
3205} FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS;
3206
3207/*
3208 * FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE enum
3209 */
3210
3211typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE {
3212FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION  = 0x00000000,
3213FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING  = 0x00000001,
3214} FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE;
3215
3216/*
3217 * FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH enum
3218 */
3219
3220typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH {
3221FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP  = 0x00000000,
3222FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP  = 0x00000001,
3223FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP  = 0x00000002,
3224} FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH;
3225
3226/*
3227 * FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH enum
3228 */
3229
3230typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH {
3231FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP  = 0x00000000,
3232FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP  = 0x00000001,
3233FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP  = 0x00000002,
3234} FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH;
3235
3236/*
3237 * FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH enum
3238 */
3239
3240typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH {
3241FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP  = 0x00000000,
3242FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP  = 0x00000001,
3243FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP  = 0x00000002,
3244} FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH;
3245
3246/*
3247 * FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL enum
3248 */
3249
3250typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL {
3251FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2  = 0x00000000,
3252FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4  = 0x00000001,
3253} FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL;
3254
3255/*
3256 * FMT_BIT_DEPTH_CONTROL_25FRC_SEL enum
3257 */
3258
3259typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL {
3260FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei       = 0x00000000,
3261FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi       = 0x00000001,
3262FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi       = 0x00000002,
3263FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED  = 0x00000003,
3264} FMT_BIT_DEPTH_CONTROL_25FRC_SEL;
3265
3266/*
3267 * FMT_BIT_DEPTH_CONTROL_50FRC_SEL enum
3268 */
3269
3270typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL {
3271FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A        = 0x00000000,
3272FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B        = 0x00000001,
3273FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C        = 0x00000002,
3274FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D        = 0x00000003,
3275} FMT_BIT_DEPTH_CONTROL_50FRC_SEL;
3276
3277/*
3278 * FMT_BIT_DEPTH_CONTROL_75FRC_SEL enum
3279 */
3280
3281typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL {
3282FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E        = 0x00000000,
3283FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F        = 0x00000001,
3284FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G        = 0x00000002,
3285FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED  = 0x00000003,
3286} FMT_BIT_DEPTH_CONTROL_75FRC_SEL;
3287
3288/*
3289 * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT enum
3290 */
3291
3292typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT {
3293FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN  = 0x00000000,
3294FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN  = 0x00000001,
3295} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT;
3296
3297/*
3298 * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 enum
3299 */
3300
3301typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 {
3302FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR  = 0x00000000,
3303FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB  = 0x00000001,
3304} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0;
3305
3306/*
3307 * FMT_CLAMP_CNTL_COLOR_FORMAT enum
3308 */
3309
3310typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT {
3311FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC         = 0x00000000,
3312FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC         = 0x00000001,
3313FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC        = 0x00000002,
3314FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC        = 0x00000003,
3315FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1    = 0x00000004,
3316FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2    = 0x00000005,
3317FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3    = 0x00000006,
3318FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE  = 0x00000007,
3319} FMT_CLAMP_CNTL_COLOR_FORMAT;
3320
3321/*
3322 * FMT_CRC_CNTL_CONT_EN enum
3323 */
3324
3325typedef enum FMT_CRC_CNTL_CONT_EN {
3326FMT_CRC_CNTL_CONT_EN_ONE_SHOT            = 0x00000000,
3327FMT_CRC_CNTL_CONT_EN_CONT                = 0x00000001,
3328} FMT_CRC_CNTL_CONT_EN;
3329
3330/*
3331 * FMT_CRC_CNTL_INCLUDE_OVERSCAN enum
3332 */
3333
3334typedef enum FMT_CRC_CNTL_INCLUDE_OVERSCAN {
3335FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE  = 0x00000000,
3336FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE    = 0x00000001,
3337} FMT_CRC_CNTL_INCLUDE_OVERSCAN;
3338
3339/*
3340 * FMT_CRC_CNTL_ONLY_BLANKB enum
3341 */
3342
3343typedef enum FMT_CRC_CNTL_ONLY_BLANKB {
3344FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD    = 0x00000000,
3345FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK       = 0x00000001,
3346} FMT_CRC_CNTL_ONLY_BLANKB;
3347
3348/*
3349 * FMT_CRC_CNTL_PSR_MODE_ENABLE enum
3350 */
3351
3352typedef enum FMT_CRC_CNTL_PSR_MODE_ENABLE {
3353FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL      = 0x00000000,
3354FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC  = 0x00000001,
3355} FMT_CRC_CNTL_PSR_MODE_ENABLE;
3356
3357/*
3358 * FMT_CRC_CNTL_INTERLACE_MODE enum
3359 */
3360
3361typedef enum FMT_CRC_CNTL_INTERLACE_MODE {
3362FMT_CRC_CNTL_INTERLACE_MODE_TOP          = 0x00000000,
3363FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM       = 0x00000001,
3364FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM  = 0x00000002,
3365FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH    = 0x00000003,
3366} FMT_CRC_CNTL_INTERLACE_MODE;
3367
3368/*
3369 * FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE enum
3370 */
3371
3372typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE {
3373FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL     = 0x00000000,
3374FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN  = 0x00000001,
3375} FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE;
3376
3377/*
3378 * FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT enum
3379 */
3380
3381typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT {
3382FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN    = 0x00000000,
3383FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD     = 0x00000001,
3384} FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT;
3385
3386/*
3387 * FMT_DEBUG_CNTL_COLOR_SELECT enum
3388 */
3389
3390typedef enum FMT_DEBUG_CNTL_COLOR_SELECT {
3391FMT_DEBUG_CNTL_COLOR_SELECT_BLUE         = 0x00000000,
3392FMT_DEBUG_CNTL_COLOR_SELECT_GREEN        = 0x00000001,
3393FMT_DEBUG_CNTL_COLOR_SELECT_RED1         = 0x00000002,
3394FMT_DEBUG_CNTL_COLOR_SELECT_RED2         = 0x00000003,
3395} FMT_DEBUG_CNTL_COLOR_SELECT;
3396
3397/*
3398 * FMT_SPATIAL_DITHER_MODE enum
3399 */
3400
3401typedef enum FMT_SPATIAL_DITHER_MODE {
3402FMT_SPATIAL_DITHER_MODE_0                = 0x00000000,
3403FMT_SPATIAL_DITHER_MODE_1                = 0x00000001,
3404FMT_SPATIAL_DITHER_MODE_2                = 0x00000002,
3405FMT_SPATIAL_DITHER_MODE_3                = 0x00000003,
3406} FMT_SPATIAL_DITHER_MODE;
3407
3408/*
3409 * FMT_STEREOSYNC_OVR_POL enum
3410 */
3411
3412typedef enum FMT_STEREOSYNC_OVR_POL {
3413FMT_STEREOSYNC_OVR_POL_INVERTED          = 0x00000000,
3414FMT_STEREOSYNC_OVR_POL_NOT_INVERTED      = 0x00000001,
3415} FMT_STEREOSYNC_OVR_POL;
3416
3417/*
3418 * FMT_DYNAMIC_EXP_MODE enum
3419 */
3420
3421typedef enum FMT_DYNAMIC_EXP_MODE {
3422FMT_DYNAMIC_EXP_MODE_10to12              = 0x00000000,
3423FMT_DYNAMIC_EXP_MODE_8to12               = 0x00000001,
3424} FMT_DYNAMIC_EXP_MODE;
3425
3426/*******************************************************
3427 * HPD Enums
3428 *******************************************************/
3429
3430/*
3431 * HPD_INT_CONTROL_ACK enum
3432 */
3433
3434typedef enum HPD_INT_CONTROL_ACK {
3435HPD_INT_CONTROL_ACK_0                    = 0x00000000,
3436HPD_INT_CONTROL_ACK_1                    = 0x00000001,
3437} HPD_INT_CONTROL_ACK;
3438
3439/*
3440 * HPD_INT_CONTROL_POLARITY enum
3441 */
3442
3443typedef enum HPD_INT_CONTROL_POLARITY {
3444HPD_INT_CONTROL_GEN_INT_ON_DISCON        = 0x00000000,
3445HPD_INT_CONTROL_GEN_INT_ON_CON           = 0x00000001,
3446} HPD_INT_CONTROL_POLARITY;
3447
3448/*
3449 * HPD_INT_CONTROL_RX_INT_ACK enum
3450 */
3451
3452typedef enum HPD_INT_CONTROL_RX_INT_ACK {
3453HPD_INT_CONTROL_RX_INT_ACK_0             = 0x00000000,
3454HPD_INT_CONTROL_RX_INT_ACK_1             = 0x00000001,
3455} HPD_INT_CONTROL_RX_INT_ACK;
3456
3457/*******************************************************
3458 * LB Enums
3459 *******************************************************/
3460
3461/*
3462 * LB_DATA_FORMAT_PIXEL_DEPTH enum
3463 */
3464
3465typedef enum LB_DATA_FORMAT_PIXEL_DEPTH {
3466LB_DATA_FORMAT_PIXEL_DEPTH_30BPP         = 0x00000000,
3467LB_DATA_FORMAT_PIXEL_DEPTH_24BPP         = 0x00000001,
3468LB_DATA_FORMAT_PIXEL_DEPTH_18BPP         = 0x00000002,
3469LB_DATA_FORMAT_PIXEL_DEPTH_36BPP         = 0x00000003,
3470} LB_DATA_FORMAT_PIXEL_DEPTH;
3471
3472/*
3473 * LB_DATA_FORMAT_PIXEL_EXPAN_MODE enum
3474 */
3475
3476typedef enum LB_DATA_FORMAT_PIXEL_EXPAN_MODE {
3477LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION = 0x00000000,
3478LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION = 0x00000001,
3479} LB_DATA_FORMAT_PIXEL_EXPAN_MODE;
3480
3481/*
3482 * LB_DATA_FORMAT_PIXEL_REDUCE_MODE enum
3483 */
3484
3485typedef enum LB_DATA_FORMAT_PIXEL_REDUCE_MODE {
3486LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION = 0x00000000,
3487LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING = 0x00000001,
3488} LB_DATA_FORMAT_PIXEL_REDUCE_MODE;
3489
3490/*
3491 * LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH enum
3492 */
3493
3494typedef enum LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH {
3495LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP = 0x00000000,
3496LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP = 0x00000001,
3497} LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH;
3498
3499/*
3500 * LB_DATA_FORMAT_INTERLEAVE_EN enum
3501 */
3502
3503typedef enum LB_DATA_FORMAT_INTERLEAVE_EN {
3504LB_DATA_FORMAT_INTERLEAVE_DISABLE        = 0x00000000,
3505LB_DATA_FORMAT_INTERLEAVE_ENABLE         = 0x00000001,
3506} LB_DATA_FORMAT_INTERLEAVE_EN;
3507
3508/*
3509 * LB_DATA_FORMAT_REQUEST_MODE enum
3510 */
3511
3512typedef enum LB_DATA_FORMAT_REQUEST_MODE {
3513LB_DATA_FORMAT_REQUEST_MODE_NORMAL       = 0x00000000,
3514LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE  = 0x00000001,
3515} LB_DATA_FORMAT_REQUEST_MODE;
3516
3517/*
3518 * LB_DATA_FORMAT_ALPHA_EN enum
3519 */
3520
3521typedef enum LB_DATA_FORMAT_ALPHA_EN {
3522LB_DATA_FORMAT_ALPHA_DISABLE             = 0x00000000,
3523LB_DATA_FORMAT_ALPHA_ENABLE              = 0x00000001,
3524} LB_DATA_FORMAT_ALPHA_EN;
3525
3526/*
3527 * LB_VLINE_START_END_VLINE_INV enum
3528 */
3529
3530typedef enum LB_VLINE_START_END_VLINE_INV {
3531LB_VLINE_START_END_VLINE_NORMAL          = 0x00000000,
3532LB_VLINE_START_END_VLINE_INVERSE         = 0x00000001,
3533} LB_VLINE_START_END_VLINE_INV;
3534
3535/*
3536 * LB_VLINE2_START_END_VLINE2_INV enum
3537 */
3538
3539typedef enum LB_VLINE2_START_END_VLINE2_INV {
3540LB_VLINE2_START_END_VLINE2_NORMAL        = 0x00000000,
3541LB_VLINE2_START_END_VLINE2_INVERSE       = 0x00000001,
3542} LB_VLINE2_START_END_VLINE2_INV;
3543
3544/*
3545 * LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK enum
3546 */
3547
3548typedef enum LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK {
3549LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE = 0x00000000,
3550LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE = 0x00000001,
3551} LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK;
3552
3553/*
3554 * LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK enum
3555 */
3556
3557typedef enum LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK {
3558LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE = 0x00000000,
3559LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE = 0x00000001,
3560} LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK;
3561
3562/*
3563 * LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK enum
3564 */
3565
3566typedef enum LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK {
3567LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE = 0x00000000,
3568LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE = 0x00000001,
3569} LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK;
3570
3571/*
3572 * LB_VLINE_STATUS_VLINE_ACK enum
3573 */
3574
3575typedef enum LB_VLINE_STATUS_VLINE_ACK {
3576LB_VLINE_STATUS_VLINE_NORMAL             = 0x00000000,
3577LB_VLINE_STATUS_VLINE_CLEAR              = 0x00000001,
3578} LB_VLINE_STATUS_VLINE_ACK;
3579
3580/*
3581 * LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE enum
3582 */
3583
3584typedef enum LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE {
3585LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED  = 0x00000000,
3586LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED  = 0x00000001,
3587} LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE;
3588
3589/*
3590 * LB_VLINE2_STATUS_VLINE2_ACK enum
3591 */
3592
3593typedef enum LB_VLINE2_STATUS_VLINE2_ACK {
3594LB_VLINE2_STATUS_VLINE2_NORMAL           = 0x00000000,
3595LB_VLINE2_STATUS_VLINE2_CLEAR            = 0x00000001,
3596} LB_VLINE2_STATUS_VLINE2_ACK;
3597
3598/*
3599 * LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE enum
3600 */
3601
3602typedef enum LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE {
3603LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED  = 0x00000000,
3604LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED  = 0x00000001,
3605} LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE;
3606
3607/*
3608 * LB_VBLANK_STATUS_VBLANK_ACK enum
3609 */
3610
3611typedef enum LB_VBLANK_STATUS_VBLANK_ACK {
3612LB_VBLANK_STATUS_VBLANK_NORMAL           = 0x00000000,
3613LB_VBLANK_STATUS_VBLANK_CLEAR            = 0x00000001,
3614} LB_VBLANK_STATUS_VBLANK_ACK;
3615
3616/*
3617 * LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE enum
3618 */
3619
3620typedef enum LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE {
3621LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED  = 0x00000000,
3622LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED  = 0x00000001,
3623} LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE;
3624
3625/*
3626 * LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL enum
3627 */
3628
3629typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL {
3630LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE  = 0x00000000,
3631LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK  = 0x00000001,
3632LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET  = 0x00000002,
3633LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET  = 0x00000003,
3634} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL;
3635
3636/*
3637 * LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 enum
3638 */
3639
3640typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 {
3641LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK  = 0x00000000,
3642LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC  = 0x00000001,
3643} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2;
3644
3645/*
3646 * LB_SYNC_RESET_SEL_LB_SYNC_DURATION enum
3647 */
3648
3649typedef enum LB_SYNC_RESET_SEL_LB_SYNC_DURATION {
3650LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS = 0x00000000,
3651LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS = 0x00000001,
3652LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS = 0x00000002,
3653LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS = 0x00000003,
3654} LB_SYNC_RESET_SEL_LB_SYNC_DURATION;
3655
3656/*
3657 * LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN enum
3658 */
3659
3660typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN {
3661LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE = 0x00000000,
3662LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE = 0x00000001,
3663} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN;
3664
3665/*
3666 * LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN enum
3667 */
3668
3669typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN {
3670LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE = 0x00000000,
3671LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE = 0x00000001,
3672} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN;
3673
3674/*
3675 * LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK enum
3676 */
3677
3678typedef enum LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK {
3679LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL  = 0x00000000,
3680LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET   = 0x00000001,
3681} LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK;
3682
3683/*
3684 * LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK enum
3685 */
3686
3687typedef enum LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK {
3688LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL   = 0x00000000,
3689LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET    = 0x00000001,
3690} LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK;
3691
3692/*
3693 * LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE enum
3694 */
3695
3696typedef enum LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE {
3697LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP  = 0x00000002,
3698LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP  = 0x00000003,
3699} LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE;
3700
3701/*
3702 * LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET enum
3703 */
3704
3705typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET {
3706LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL = 0x00000000,
3707LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE  = 0x00000001,
3708} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET;
3709
3710/*
3711 * LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK enum
3712 */
3713
3714typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK {
3715LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0 = 0x00000000,
3716LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1 = 0x00000001,
3717} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK;
3718
3719/*
3720 * LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE enum
3721 */
3722
3723typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE {
3724LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT  = 0x00000000,
3725LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG  = 0x00000001,
3726LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE  = 0x00000002,
3727} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE;
3728
3729/*
3730 * LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE enum
3731 */
3732
3733typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE {
3734LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE  = 0x00000000,
3735LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN  = 0x00000001,
3736} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE;
3737
3738/*
3739 * LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE enum
3740 */
3741
3742typedef enum LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE {
3743ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER  = 0x00000001,
3744ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE  = 0x00000002,
3745} LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE;
3746
3747/*
3748 * LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL enum
3749 */
3750
3751typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL {
3752LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0 = 0x00000000,
3753LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1 = 0x00000001,
3754} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL;
3755
3756/*
3757 * LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE enum
3758 */
3759
3760typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE {
3761LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE = 0x00000000,
3762LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE  = 0x00000001,
3763} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE;
3764
3765/*
3766 * LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO enum
3767 */
3768
3769typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO {
3770LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO = 0x00000000,
3771LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO  = 0x00000001,
3772} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO;
3773
3774/*
3775 * LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN enum
3776 */
3777
3778typedef enum LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN {
3779LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0 = 0x00000000,
3780LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1 = 0x00000001,
3781} LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN;
3782
3783/*******************************************************
3784 * DIG Enums
3785 *******************************************************/
3786
3787/*
3788 * HDMI_KEEPOUT_MODE enum
3789 */
3790
3791typedef enum HDMI_KEEPOUT_MODE {
3792HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC        = 0x00000000,
3793HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC      = 0x00000001,
3794} HDMI_KEEPOUT_MODE;
3795
3796/*
3797 * HDMI_DATA_SCRAMBLE_EN enum
3798 */
3799
3800typedef enum HDMI_DATA_SCRAMBLE_EN {
3801HDMI_DATA_SCRAMBLE_DISABLE               = 0x00000000,
3802HDMI_DATA_SCRAMBLE_ENABLE                = 0x00000001,
3803} HDMI_DATA_SCRAMBLE_EN;
3804
3805/*
3806 * HDMI_CLOCK_CHANNEL_RATE enum
3807 */
3808
3809typedef enum HDMI_CLOCK_CHANNEL_RATE {
3810HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE  = 0x00000000,
3811HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE  = 0x00000001,
3812} HDMI_CLOCK_CHANNEL_RATE;
3813
3814/*
3815 * HDMI_NO_EXTRA_NULL_PACKET_FILLED enum
3816 */
3817
3818typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED {
3819HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE     = 0x00000000,
3820HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE    = 0x00000001,
3821} HDMI_NO_EXTRA_NULL_PACKET_FILLED;
3822
3823/*
3824 * HDMI_PACKET_GEN_VERSION enum
3825 */
3826
3827typedef enum HDMI_PACKET_GEN_VERSION {
3828HDMI_PACKET_GEN_VERSION_OLD              = 0x00000000,
3829HDMI_PACKET_GEN_VERSION_NEW              = 0x00000001,
3830} HDMI_PACKET_GEN_VERSION;
3831
3832/*
3833 * HDMI_ERROR_ACK enum
3834 */
3835
3836typedef enum HDMI_ERROR_ACK {
3837HDMI_ERROR_ACK_INT                       = 0x00000000,
3838HDMI_ERROR_NOT_ACK                       = 0x00000001,
3839} HDMI_ERROR_ACK;
3840
3841/*
3842 * HDMI_ERROR_MASK enum
3843 */
3844
3845typedef enum HDMI_ERROR_MASK {
3846HDMI_ERROR_MASK_INT                      = 0x00000000,
3847HDMI_ERROR_NOT_MASK                      = 0x00000001,
3848} HDMI_ERROR_MASK;
3849
3850/*
3851 * HDMI_DEEP_COLOR_DEPTH enum
3852 */
3853
3854typedef enum HDMI_DEEP_COLOR_DEPTH {
3855HDMI_DEEP_COLOR_DEPTH_24BPP              = 0x00000000,
3856HDMI_DEEP_COLOR_DEPTH_30BPP              = 0x00000001,
3857HDMI_DEEP_COLOR_DEPTH_36BPP              = 0x00000002,
3858HDMI_DEEP_COLOR_DEPTH_RESERVED           = 0x00000003,
3859} HDMI_DEEP_COLOR_DEPTH;
3860
3861/*
3862 * HDMI_AUDIO_DELAY_EN enum
3863 */
3864
3865typedef enum HDMI_AUDIO_DELAY_EN {
3866HDMI_AUDIO_DELAY_DISABLE                 = 0x00000000,
3867HDMI_AUDIO_DELAY_58CLK                   = 0x00000001,
3868HDMI_AUDIO_DELAY_56CLK                   = 0x00000002,
3869HDMI_AUDIO_DELAY_RESERVED                = 0x00000003,
3870} HDMI_AUDIO_DELAY_EN;
3871
3872/*
3873 * HDMI_AUDIO_SEND_MAX_PACKETS enum
3874 */
3875
3876typedef enum HDMI_AUDIO_SEND_MAX_PACKETS {
3877HDMI_NOT_SEND_MAX_AUDIO_PACKETS          = 0x00000000,
3878HDMI_SEND_MAX_AUDIO_PACKETS              = 0x00000001,
3879} HDMI_AUDIO_SEND_MAX_PACKETS;
3880
3881/*
3882 * HDMI_ACR_SEND enum
3883 */
3884
3885typedef enum HDMI_ACR_SEND {
3886HDMI_ACR_NOT_SEND                        = 0x00000000,
3887HDMI_ACR_PKT_SEND                        = 0x00000001,
3888} HDMI_ACR_SEND;
3889
3890/*
3891 * HDMI_ACR_CONT enum
3892 */
3893
3894typedef enum HDMI_ACR_CONT {
3895HDMI_ACR_CONT_DISABLE                    = 0x00000000,
3896HDMI_ACR_CONT_ENABLE                     = 0x00000001,
3897} HDMI_ACR_CONT;
3898
3899/*
3900 * HDMI_ACR_SELECT enum
3901 */
3902
3903typedef enum HDMI_ACR_SELECT {
3904HDMI_ACR_SELECT_HW                       = 0x00000000,
3905HDMI_ACR_SELECT_32K                      = 0x00000001,
3906HDMI_ACR_SELECT_44K                      = 0x00000002,
3907HDMI_ACR_SELECT_48K                      = 0x00000003,
3908} HDMI_ACR_SELECT;
3909
3910/*
3911 * HDMI_ACR_SOURCE enum
3912 */
3913
3914typedef enum HDMI_ACR_SOURCE {
3915HDMI_ACR_SOURCE_HW                       = 0x00000000,
3916HDMI_ACR_SOURCE_SW                       = 0x00000001,
3917} HDMI_ACR_SOURCE;
3918
3919/*
3920 * HDMI_ACR_N_MULTIPLE enum
3921 */
3922
3923typedef enum HDMI_ACR_N_MULTIPLE {
3924HDMI_ACR_0_MULTIPLE_RESERVED             = 0x00000000,
3925HDMI_ACR_1_MULTIPLE                      = 0x00000001,
3926HDMI_ACR_2_MULTIPLE                      = 0x00000002,
3927HDMI_ACR_3_MULTIPLE_RESERVED             = 0x00000003,
3928HDMI_ACR_4_MULTIPLE                      = 0x00000004,
3929HDMI_ACR_5_MULTIPLE_RESERVED             = 0x00000005,
3930HDMI_ACR_6_MULTIPLE_RESERVED             = 0x00000006,
3931HDMI_ACR_7_MULTIPLE_RESERVED             = 0x00000007,
3932} HDMI_ACR_N_MULTIPLE;
3933
3934/*
3935 * HDMI_ACR_AUDIO_PRIORITY enum
3936 */
3937
3938typedef enum HDMI_ACR_AUDIO_PRIORITY {
3939HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE  = 0x00000000,
3940HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT  = 0x00000001,
3941} HDMI_ACR_AUDIO_PRIORITY;
3942
3943/*
3944 * HDMI_NULL_SEND enum
3945 */
3946
3947typedef enum HDMI_NULL_SEND {
3948HDMI_NULL_NOT_SEND                       = 0x00000000,
3949HDMI_NULL_PKT_SEND                       = 0x00000001,
3950} HDMI_NULL_SEND;
3951
3952/*
3953 * HDMI_GC_SEND enum
3954 */
3955
3956typedef enum HDMI_GC_SEND {
3957HDMI_GC_NOT_SEND                         = 0x00000000,
3958HDMI_GC_PKT_SEND                         = 0x00000001,
3959} HDMI_GC_SEND;
3960
3961/*
3962 * HDMI_GC_CONT enum
3963 */
3964
3965typedef enum HDMI_GC_CONT {
3966HDMI_GC_CONT_DISABLE                     = 0x00000000,
3967HDMI_GC_CONT_ENABLE                      = 0x00000001,
3968} HDMI_GC_CONT;
3969
3970/*
3971 * HDMI_ISRC_SEND enum
3972 */
3973
3974typedef enum HDMI_ISRC_SEND {
3975HDMI_ISRC_NOT_SEND                       = 0x00000000,
3976HDMI_ISRC_PKT_SEND                       = 0x00000001,
3977} HDMI_ISRC_SEND;
3978
3979/*
3980 * HDMI_ISRC_CONT enum
3981 */
3982
3983typedef enum HDMI_ISRC_CONT {
3984HDMI_ISRC_CONT_DISABLE                   = 0x00000000,
3985HDMI_ISRC_CONT_ENABLE                    = 0x00000001,
3986} HDMI_ISRC_CONT;
3987
3988/*
3989 * HDMI_AVI_INFO_SEND enum
3990 */
3991
3992typedef enum HDMI_AVI_INFO_SEND {
3993HDMI_AVI_INFO_NOT_SEND                   = 0x00000000,
3994HDMI_AVI_INFO_PKT_SEND                   = 0x00000001,
3995} HDMI_AVI_INFO_SEND;
3996
3997/*
3998 * HDMI_AVI_INFO_CONT enum
3999 */
4000

4001typedef enum HDMI_AVI_INFO_CONT {
4002HDMI_AVI_INFO_CONT_DISABLE               = 0x00000000,
4003HDMI_AVI_INFO_CONT_ENABLE                = 0x00000001,
4004} HDMI_AVI_INFO_CONT;
4005
4006/*
4007 * HDMI_AUDIO_INFO_SEND enum
4008 */
4009
4010typedef enum HDMI_AUDIO_INFO_SEND {
4011HDMI_AUDIO_INFO_NOT_SEND                 = 0x00000000,
4012HDMI_AUDIO_INFO_PKT_SEND                 = 0x00000001,
4013} HDMI_AUDIO_INFO_SEND;
4014
4015/*
4016 * HDMI_AUDIO_INFO_CONT enum
4017 */
4018
4019typedef enum HDMI_AUDIO_INFO_CONT {
4020HDMI_AUDIO_INFO_CONT_DISABLE             = 0x00000000,
4021HDMI_AUDIO_INFO_CONT_ENABLE              = 0x00000001,
4022} HDMI_AUDIO_INFO_CONT;
4023
4024/*
4025 * HDMI_MPEG_INFO_SEND enum
4026 */
4027
4028typedef enum HDMI_MPEG_INFO_SEND {
4029HDMI_MPEG_INFO_NOT_SEND                  = 0x00000000,
4030HDMI_MPEG_INFO_PKT_SEND                  = 0x00000001,
4031} HDMI_MPEG_INFO_SEND;
4032
4033/*
4034 * HDMI_MPEG_INFO_CONT enum
4035 */
4036
4037typedef enum HDMI_MPEG_INFO_CONT {
4038HDMI_MPEG_INFO_CONT_DISABLE              = 0x00000000,
4039HDMI_MPEG_INFO_CONT_ENABLE               = 0x00000001,
4040} HDMI_MPEG_INFO_CONT;
4041
4042/*
4043 * HDMI_GENERIC0_SEND enum
4044 */
4045
4046typedef enum HDMI_GENERIC0_SEND {
4047HDMI_GENERIC0_NOT_SEND                   = 0x00000000,
4048HDMI_GENERIC0_PKT_SEND                   = 0x00000001,
4049} HDMI_GENERIC0_SEND;
4050
4051/*
4052 * HDMI_GENERIC0_CONT enum
4053 */
4054
4055typedef enum HDMI_GENERIC0_CONT {
4056HDMI_GENERIC0_CONT_DISABLE               = 0x00000000,
4057HDMI_GENERIC0_CONT_ENABLE                = 0x00000001,
4058} HDMI_GENERIC0_CONT;
4059
4060/*
4061 * HDMI_GENERIC1_SEND enum
4062 */
4063
4064typedef enum HDMI_GENERIC1_SEND {
4065HDMI_GENERIC1_NOT_SEND                   = 0x00000000,
4066HDMI_GENERIC1_PKT_SEND                   = 0x00000001,
4067} HDMI_GENERIC1_SEND;
4068
4069/*
4070 * HDMI_GENERIC1_CONT enum
4071 */
4072
4073typedef enum HDMI_GENERIC1_CONT {
4074HDMI_GENERIC1_CONT_DISABLE               = 0x00000000,
4075HDMI_GENERIC1_CONT_ENABLE                = 0x00000001,
4076} HDMI_GENERIC1_CONT;
4077
4078/*
4079 * HDMI_GC_AVMUTE_CONT enum
4080 */
4081
4082typedef enum HDMI_GC_AVMUTE_CONT {
4083HDMI_GC_AVMUTE_CONT_DISABLE              = 0x00000000,
4084HDMI_GC_AVMUTE_CONT_ENABLE               = 0x00000001,
4085} HDMI_GC_AVMUTE_CONT;
4086
4087/*
4088 * HDMI_PACKING_PHASE_OVERRIDE enum
4089 */
4090
4091typedef enum HDMI_PACKING_PHASE_OVERRIDE {
4092HDMI_PACKING_PHASE_SET_BY_HW             = 0x00000000,
4093HDMI_PACKING_PHASE_SET_BY_SW             = 0x00000001,
4094} HDMI_PACKING_PHASE_OVERRIDE;
4095
4096/*
4097 * HDMI_GENERIC2_SEND enum
4098 */
4099
4100typedef enum HDMI_GENERIC2_SEND {
4101HDMI_GENERIC2_NOT_SEND                   = 0x00000000,
4102HDMI_GENERIC2_PKT_SEND                   = 0x00000001,
4103} HDMI_GENERIC2_SEND;
4104
4105/*
4106 * HDMI_GENERIC2_CONT enum
4107 */
4108
4109typedef enum HDMI_GENERIC2_CONT {
4110HDMI_GENERIC2_CONT_DISABLE               = 0x00000000,
4111HDMI_GENERIC2_CONT_ENABLE                = 0x00000001,
4112} HDMI_GENERIC2_CONT;
4113
4114/*
4115 * HDMI_GENERIC3_SEND enum
4116 */
4117
4118typedef enum HDMI_GENERIC3_SEND {
4119HDMI_GENERIC3_NOT_SEND                   = 0x00000000,
4120HDMI_GENERIC3_PKT_SEND                   = 0x00000001,
4121} HDMI_GENERIC3_SEND;
4122
4123/*
4124 * HDMI_GENERIC3_CONT enum
4125 */
4126
4127typedef enum HDMI_GENERIC3_CONT {
4128HDMI_GENERIC3_CONT_DISABLE               = 0x00000000,
4129HDMI_GENERIC3_CONT_ENABLE                = 0x00000001,
4130} HDMI_GENERIC3_CONT;
4131
4132/*
4133 * TMDS_PIXEL_ENCODING enum
4134 */
4135
4136typedef enum TMDS_PIXEL_ENCODING {
4137TMDS_PIXEL_ENCODING_444_OR_420           = 0x00000000,
4138TMDS_PIXEL_ENCODING_422                  = 0x00000001,
4139} TMDS_PIXEL_ENCODING;
4140
4141/*
4142 * TMDS_COLOR_FORMAT enum
4143 */
4144
4145typedef enum TMDS_COLOR_FORMAT {
4146TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP  = 0x00000000,
4147TMDS_COLOR_FORMAT_TWIN30BPP_LSB          = 0x00000001,
4148TMDS_COLOR_FORMAT_DUAL30BPP              = 0x00000002,
4149TMDS_COLOR_FORMAT_RESERVED               = 0x00000003,
4150} TMDS_COLOR_FORMAT;
4151
4152/*
4153 * TMDS_STEREOSYNC_CTL_SEL_REG enum
4154 */
4155
4156typedef enum TMDS_STEREOSYNC_CTL_SEL_REG {
4157TMDS_STEREOSYNC_CTL0                     = 0x00000000,
4158TMDS_STEREOSYNC_CTL1                     = 0x00000001,
4159TMDS_STEREOSYNC_CTL2                     = 0x00000002,
4160TMDS_STEREOSYNC_CTL3                     = 0x00000003,
4161} TMDS_STEREOSYNC_CTL_SEL_REG;
4162
4163/*
4164 * TMDS_CTL0_DATA_SEL enum
4165 */
4166
4167typedef enum TMDS_CTL0_DATA_SEL {
4168TMDS_CTL0_DATA_SEL0_RESERVED             = 0x00000000,
4169TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE       = 0x00000001,
4170TMDS_CTL0_DATA_SEL2_VSYNC                = 0x00000002,
4171TMDS_CTL0_DATA_SEL3_RESERVED             = 0x00000003,
4172TMDS_CTL0_DATA_SEL4_HSYNC                = 0x00000004,
4173TMDS_CTL0_DATA_SEL5_SEL7_RESERVED        = 0x00000005,
4174TMDS_CTL0_DATA_SEL8_RANDOM_DATA          = 0x00000006,
4175TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA    = 0x00000007,
4176} TMDS_CTL0_DATA_SEL;
4177
4178/*
4179 * TMDS_CTL0_DATA_INVERT enum
4180 */
4181
4182typedef enum TMDS_CTL0_DATA_INVERT {
4183TMDS_CTL0_DATA_NORMAL                    = 0x00000000,
4184TMDS_CTL0_DATA_INVERT_EN                 = 0x00000001,
4185} TMDS_CTL0_DATA_INVERT;
4186
4187/*
4188 * TMDS_CTL0_DATA_MODULATION enum
4189 */
4190
4191typedef enum TMDS_CTL0_DATA_MODULATION {
4192TMDS_CTL0_DATA_MODULATION_DISABLE        = 0x00000000,
4193TMDS_CTL0_DATA_MODULATION_BIT0           = 0x00000001,
4194TMDS_CTL0_DATA_MODULATION_BIT1           = 0x00000002,
4195TMDS_CTL0_DATA_MODULATION_BIT2           = 0x00000003,
4196} TMDS_CTL0_DATA_MODULATION;
4197
4198/*
4199 * TMDS_CTL0_PATTERN_OUT_EN enum
4200 */
4201
4202typedef enum TMDS_CTL0_PATTERN_OUT_EN {
4203TMDS_CTL0_PATTERN_OUT_DISABLE            = 0x00000000,
4204TMDS_CTL0_PATTERN_OUT_ENABLE             = 0x00000001,
4205} TMDS_CTL0_PATTERN_OUT_EN;
4206
4207/*
4208 * TMDS_CTL1_DATA_SEL enum
4209 */
4210
4211typedef enum TMDS_CTL1_DATA_SEL {
4212TMDS_CTL1_DATA_SEL0_RESERVED             = 0x00000000,
4213TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE       = 0x00000001,
4214TMDS_CTL1_DATA_SEL2_VSYNC                = 0x00000002,
4215TMDS_CTL1_DATA_SEL3_RESERVED             = 0x00000003,
4216TMDS_CTL1_DATA_SEL4_HSYNC                = 0x00000004,
4217TMDS_CTL1_DATA_SEL5_SEL7_RESERVED        = 0x00000005,
4218TMDS_CTL1_DATA_SEL8_BLANK_TIME           = 0x00000006,
4219TMDS_CTL1_DATA_SEL9_SEL15_RESERVED       = 0x00000007,
4220} TMDS_CTL1_DATA_SEL;
4221
4222/*
4223 * TMDS_CTL1_DATA_INVERT enum
4224 */
4225
4226typedef enum TMDS_CTL1_DATA_INVERT {
4227TMDS_CTL1_DATA_NORMAL                    = 0x00000000,
4228TMDS_CTL1_DATA_INVERT_EN                 = 0x00000001,
4229} TMDS_CTL1_DATA_INVERT;
4230
4231/*
4232 * TMDS_CTL1_DATA_MODULATION enum
4233 */
4234
4235typedef enum TMDS_CTL1_DATA_MODULATION {
4236TMDS_CTL1_DATA_MODULATION_DISABLE        = 0x00000000,
4237TMDS_CTL1_DATA_MODULATION_BIT0           = 0x00000001,
4238TMDS_CTL1_DATA_MODULATION_BIT1           = 0x00000002,
4239TMDS_CTL1_DATA_MODULATION_BIT2           = 0x00000003,
4240} TMDS_CTL1_DATA_MODULATION;
4241
4242/*
4243 * TMDS_CTL1_PATTERN_OUT_EN enum
4244 */
4245
4246typedef enum TMDS_CTL1_PATTERN_OUT_EN {
4247TMDS_CTL1_PATTERN_OUT_DISABLE            = 0x00000000,
4248TMDS_CTL1_PATTERN_OUT_ENABLE             = 0x00000001,
4249} TMDS_CTL1_PATTERN_OUT_EN;
4250
4251/*
4252 * TMDS_CTL2_DATA_SEL enum
4253 */
4254
4255typedef enum TMDS_CTL2_DATA_SEL {
4256TMDS_CTL2_DATA_SEL0_RESERVED             = 0x00000000,
4257TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE       = 0x00000001,
4258TMDS_CTL2_DATA_SEL2_VSYNC                = 0x00000002,
4259TMDS_CTL2_DATA_SEL3_RESERVED             = 0x00000003,
4260TMDS_CTL2_DATA_SEL4_HSYNC                = 0x00000004,
4261TMDS_CTL2_DATA_SEL5_SEL7_RESERVED        = 0x00000005,
4262TMDS_CTL2_DATA_SEL8_BLANK_TIME           = 0x00000006,
4263TMDS_CTL2_DATA_SEL9_SEL15_RESERVED       = 0x00000007,
4264} TMDS_CTL2_DATA_SEL;
4265
4266/*
4267 * TMDS_CTL2_DATA_INVERT enum
4268 */
4269
4270typedef enum TMDS_CTL2_DATA_INVERT {
4271TMDS_CTL2_DATA_NORMAL                    = 0x00000000,
4272TMDS_CTL2_DATA_INVERT_EN                 = 0x00000001,
4273} TMDS_CTL2_DATA_INVERT;
4274
4275/*
4276 * TMDS_CTL2_DATA_MODULATION enum
4277 */
4278
4279typedef enum TMDS_CTL2_DATA_MODULATION {
4280TMDS_CTL2_DATA_MODULATION_DISABLE        = 0x00000000,
4281TMDS_CTL2_DATA_MODULATION_BIT0           = 0x00000001,
4282TMDS_CTL2_DATA_MODULATION_BIT1           = 0x00000002,
4283TMDS_CTL2_DATA_MODULATION_BIT2           = 0x00000003,
4284} TMDS_CTL2_DATA_MODULATION;
4285
4286/*
4287 * TMDS_CTL2_PATTERN_OUT_EN enum
4288 */
4289
4290typedef enum TMDS_CTL2_PATTERN_OUT_EN {
4291TMDS_CTL2_PATTERN_OUT_DISABLE            = 0x00000000,
4292TMDS_CTL2_PATTERN_OUT_ENABLE             = 0x00000001,
4293} TMDS_CTL2_PATTERN_OUT_EN;
4294
4295/*
4296 * TMDS_CTL3_DATA_INVERT enum
4297 */
4298
4299typedef enum TMDS_CTL3_DATA_INVERT {
4300TMDS_CTL3_DATA_NORMAL                    = 0x00000000,
4301TMDS_CTL3_DATA_INVERT_EN                 = 0x00000001,
4302} TMDS_CTL3_DATA_INVERT;
4303
4304/*
4305 * TMDS_CTL3_DATA_MODULATION enum
4306 */
4307
4308typedef enum TMDS_CTL3_DATA_MODULATION {
4309TMDS_CTL3_DATA_MODULATION_DISABLE        = 0x00000000,
4310TMDS_CTL3_DATA_MODULATION_BIT0           = 0x00000001,
4311TMDS_CTL3_DATA_MODULATION_BIT1           = 0x00000002,
4312TMDS_CTL3_DATA_MODULATION_BIT2           = 0x00000003,
4313} TMDS_CTL3_DATA_MODULATION;
4314
4315/*
4316 * TMDS_CTL3_PATTERN_OUT_EN enum
4317 */
4318
4319typedef enum TMDS_CTL3_PATTERN_OUT_EN {
4320TMDS_CTL3_PATTERN_OUT_DISABLE            = 0x00000000,
4321TMDS_CTL3_PATTERN_OUT_ENABLE             = 0x00000001,
4322} TMDS_CTL3_PATTERN_OUT_EN;
4323
4324/*
4325 * TMDS_CTL3_DATA_SEL enum
4326 */
4327
4328typedef enum TMDS_CTL3_DATA_SEL {
4329TMDS_CTL3_DATA_SEL0_RESERVED             = 0x00000000,
4330TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE       = 0x00000001,
4331TMDS_CTL3_DATA_SEL2_VSYNC                = 0x00000002,
4332TMDS_CTL3_DATA_SEL3_RESERVED             = 0x00000003,
4333TMDS_CTL3_DATA_SEL4_HSYNC                = 0x00000004,
4334TMDS_CTL3_DATA_SEL5_SEL7_RESERVED        = 0x00000005,
4335TMDS_CTL3_DATA_SEL8_BLANK_TIME           = 0x00000006,
4336TMDS_CTL3_DATA_SEL9_SEL15_RESERVED       = 0x00000007,
4337} TMDS_CTL3_DATA_SEL;
4338
4339/*
4340 * DIG_FE_CNTL_SOURCE_SELECT enum
4341 */
4342
4343typedef enum DIG_FE_CNTL_SOURCE_SELECT {
4344DIG_FE_SOURCE_FROM_FMT0                  = 0x00000000,
4345DIG_FE_SOURCE_FROM_FMT1                  = 0x00000001,
4346DIG_FE_SOURCE_FROM_FMT2                  = 0x00000002,
4347DIG_FE_SOURCE_FROM_FMT3                  = 0x00000003,
4348DIG_FE_SOURCE_FROM_FMT4                  = 0x00000004,
4349DIG_FE_SOURCE_FROM_FMT5                  = 0x00000005,
4350} DIG_FE_CNTL_SOURCE_SELECT;
4351
4352/*
4353 * DIG_FE_CNTL_STEREOSYNC_SELECT enum
4354 */
4355
4356typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT {
4357DIG_FE_STEREOSYNC_FROM_FMT0              = 0x00000000,
4358DIG_FE_STEREOSYNC_FROM_FMT1              = 0x00000001,
4359DIG_FE_STEREOSYNC_FROM_FMT2              = 0x00000002,
4360DIG_FE_STEREOSYNC_FROM_FMT3              = 0x00000003,
4361DIG_FE_STEREOSYNC_FROM_FMT4              = 0x00000004,
4362DIG_FE_STEREOSYNC_FROM_FMT5              = 0x00000005,
4363} DIG_FE_CNTL_STEREOSYNC_SELECT;
4364
4365/*
4366 * DIG_FIFO_READ_CLOCK_SRC enum
4367 */
4368
4369typedef enum DIG_FIFO_READ_CLOCK_SRC {
4370DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG        = 0x00000000,
4371DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE  = 0x00000001,
4372} DIG_FIFO_READ_CLOCK_SRC;
4373
4374/*
4375 * DIG_OUTPUT_CRC_CNTL_LINK_SEL enum
4376 */
4377
4378typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL {
4379DIG_OUTPUT_CRC_ON_LINK0                  = 0x00000000,
4380DIG_OUTPUT_CRC_ON_LINK1                  = 0x00000001,
4381} DIG_OUTPUT_CRC_CNTL_LINK_SEL;
4382
4383/*
4384 * DIG_OUTPUT_CRC_DATA_SEL enum
4385 */
4386
4387typedef enum DIG_OUTPUT_CRC_DATA_SEL {
4388DIG_OUTPUT_CRC_FOR_FULLFRAME             = 0x00000000,
4389DIG_OUTPUT_CRC_FOR_ACTIVEONLY            = 0x00000001,
4390DIG_OUTPUT_CRC_FOR_VBI                   = 0x00000002,
4391DIG_OUTPUT_CRC_FOR_AUDIO                 = 0x00000003,
4392} DIG_OUTPUT_CRC_DATA_SEL;
4393
4394/*
4395 * DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN enum
4396 */
4397
4398typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN {
4399DIG_IN_NORMAL_OPERATION                  = 0x00000000,
4400DIG_IN_DEBUG_MODE                        = 0x00000001,
4401} DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN;
4402
4403/*
4404 * DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL enum
4405 */
4406
4407typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL {
4408DIG_10BIT_TEST_PATTERN                   = 0x00000000,
4409DIG_ALTERNATING_TEST_PATTERN             = 0x00000001,
4410} DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL;
4411
4412/*
4413 * DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN enum
4414 */
4415
4416typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN {
4417DIG_TEST_PATTERN_NORMAL                  = 0x00000000,
4418DIG_TEST_PATTERN_RANDOM                  = 0x00000001,
4419} DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN;
4420
4421/*
4422 * DIG_TEST_PATTERN_RANDOM_PATTERN_RESET enum
4423 */
4424
4425typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET {
4426DIG_RANDOM_PATTERN_ENABLED               = 0x00000000,
4427DIG_RANDOM_PATTERN_RESETED               = 0x00000001,
4428} DIG_TEST_PATTERN_RANDOM_PATTERN_RESET;
4429
4430/*
4431 * DIG_TEST_PATTERN_EXTERNAL_RESET_EN enum
4432 */
4433
4434typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN {
4435DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE   = 0x00000000,
4436DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG  = 0x00000001,
4437} DIG_TEST_PATTERN_EXTERNAL_RESET_EN;
4438
4439/*
4440 * DIG_RANDOM_PATTERN_SEED_RAN_PAT enum
4441 */
4442
4443typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT {
4444DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS  = 0x00000000,
4445DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH  = 0x00000001,
4446} DIG_RANDOM_PATTERN_SEED_RAN_PAT;
4447
4448/*
4449 * DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL enum
4450 */
4451
4452typedef enum DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL {
4453DIG_FIFO_USE_OVERWRITE_LEVEL             = 0x00000000,
4454DIG_FIFO_USE_CAL_AVERAGE_LEVEL           = 0x00000001,
4455} DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL;
4456
4457/*
4458 * DIG_FIFO_ERROR_ACK enum
4459 */
4460
4461typedef enum DIG_FIFO_ERROR_ACK {
4462DIG_FIFO_ERROR_ACK_INT                   = 0x00000000,
4463DIG_FIFO_ERROR_NOT_ACK                   = 0x00000001,
4464} DIG_FIFO_ERROR_ACK;
4465
4466/*
4467 * DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE enum
4468 */
4469
4470typedef enum DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE {
4471DIG_FIFO_NOT_FORCE_RECAL_AVERAGE         = 0x00000000,
4472DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL       = 0x00000001,
4473} DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE;
4474
4475/*
4476 * DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX enum
4477 */
4478
4479typedef enum DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX {
4480DIG_FIFO_NOT_FORCE_RECOMP_MINMAX         = 0x00000000,
4481DIG_FIFO_FORCE_RECOMP_MINMAX             = 0x00000001,
4482} DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX;
4483
4484/*
4485 * AFMT_INTERRUPT_STATUS_CHG_MASK enum
4486 */
4487
4488typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK {
4489AFMT_INTERRUPT_DISABLE                   = 0x00000000,
4490AFMT_INTERRUPT_ENABLE                    = 0x00000001,
4491} AFMT_INTERRUPT_STATUS_CHG_MASK;
4492
4493/*
4494 * HDMI_GC_AVMUTE enum
4495 */
4496
4497typedef enum HDMI_GC_AVMUTE {
4498HDMI_GC_AVMUTE_SET                       = 0x00000000,
4499HDMI_GC_AVMUTE_UNSET                     = 0x00000001,
4500} HDMI_GC_AVMUTE;
4501
4502/*
4503 * HDMI_DEFAULT_PAHSE enum
4504 */
4505
4506typedef enum HDMI_DEFAULT_PAHSE {
4507HDMI_DEFAULT_PHASE_IS_0                  = 0x00000000,
4508HDMI_DEFAULT_PHASE_IS_1                  = 0x00000001,
4509} HDMI_DEFAULT_PAHSE;
4510
4511/*
4512 * AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD enum
4513 */
4514
4515typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD {
4516AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS  = 0x00000000,
4517AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER       = 0x00000001,
4518} AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD;
4519
4520/*
4521 * AUDIO_LAYOUT_SELECT enum
4522 */
4523
4524typedef enum AUDIO_LAYOUT_SELECT {
4525AUDIO_LAYOUT_0                           = 0x00000000,
4526AUDIO_LAYOUT_1                           = 0x00000001,
4527} AUDIO_LAYOUT_SELECT;
4528
4529/*
4530 * AFMT_AUDIO_CRC_CONTROL_CONT enum
4531 */
4532
4533typedef enum AFMT_AUDIO_CRC_CONTROL_CONT {
4534AFMT_AUDIO_CRC_ONESHOT                   = 0x00000000,
4535AFMT_AUDIO_CRC_AUTO_RESTART              = 0x00000001,
4536} AFMT_AUDIO_CRC_CONTROL_CONT;
4537
4538/*
4539 * AFMT_AUDIO_CRC_CONTROL_SOURCE enum
4540 */
4541
4542typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE {
4543AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT    = 0x00000000,
4544AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT   = 0x00000001,
4545} AFMT_AUDIO_CRC_CONTROL_SOURCE;
4546
4547/*
4548 * AFMT_AUDIO_CRC_CONTROL_CH_SEL enum
4549 */
4550
4551typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL {
4552AFMT_AUDIO_CRC_CH0_SIG                   = 0x00000000,
4553AFMT_AUDIO_CRC_CH1_SIG                   = 0x00000001,
4554AFMT_AUDIO_CRC_CH2_SIG                   = 0x00000002,
4555AFMT_AUDIO_CRC_CH3_SIG                   = 0x00000003,
4556AFMT_AUDIO_CRC_CH4_SIG                   = 0x00000004,
4557AFMT_AUDIO_CRC_CH5_SIG                   = 0x00000005,
4558AFMT_AUDIO_CRC_CH6_SIG                   = 0x00000006,
4559AFMT_AUDIO_CRC_CH7_SIG                   = 0x00000007,
4560AFMT_AUDIO_CRC_RESERVED_8                = 0x00000008,
4561AFMT_AUDIO_CRC_RESERVED_9                = 0x00000009,
4562AFMT_AUDIO_CRC_RESERVED_10               = 0x0000000a,
4563AFMT_AUDIO_CRC_RESERVED_11               = 0x0000000b,
4564AFMT_AUDIO_CRC_RESERVED_12               = 0x0000000c,
4565AFMT_AUDIO_CRC_RESERVED_13               = 0x0000000d,
4566AFMT_AUDIO_CRC_RESERVED_14               = 0x0000000e,
4567AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT        = 0x0000000f,
4568} AFMT_AUDIO_CRC_CONTROL_CH_SEL;
4569
4570/*
4571 * AFMT_RAMP_CONTROL0_SIGN enum
4572 */
4573
4574typedef enum AFMT_RAMP_CONTROL0_SIGN {
4575AFMT_RAMP_SIGNED                         = 0x00000000,
4576AFMT_RAMP_UNSIGNED                       = 0x00000001,
4577} AFMT_RAMP_CONTROL0_SIGN;
4578
4579/*
4580 * AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND enum
4581 */
4582
4583typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND {
4584AFMT_AUDIO_PACKET_SENT_DISABLED          = 0x00000000,
4585AFMT_AUDIO_PACKET_SENT_ENABLED           = 0x00000001,
4586} AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND;
4587
4588/*
4589 * AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS enum
4590 */
4591
4592typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS {
4593AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED  = 0x00000000,
4594AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED  = 0x00000001,
4595} AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS;
4596
4597/*
4598 * AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE enum
4599 */
4600
4601typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE {
4602AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK  = 0x00000000,
4603AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS  = 0x00000001,
4604} AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE;
4605
4606/*
4607 * AFMT_AUDIO_SRC_CONTROL_SELECT enum
4608 */
4609
4610typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT {
4611AFMT_AUDIO_SRC_FROM_AZ_STREAM0           = 0x00000000,
4612AFMT_AUDIO_SRC_FROM_AZ_STREAM1           = 0x00000001,
4613AFMT_AUDIO_SRC_FROM_AZ_STREAM2           = 0x00000002,
4614AFMT_AUDIO_SRC_FROM_AZ_STREAM3           = 0x00000003,
4615AFMT_AUDIO_SRC_FROM_AZ_STREAM4           = 0x00000004,
4616AFMT_AUDIO_SRC_FROM_AZ_STREAM5           = 0x00000005,
4617AFMT_AUDIO_SRC_RESERVED                  = 0x00000006,
4618} AFMT_AUDIO_SRC_CONTROL_SELECT;
4619
4620/*
4621 * DIG_BE_CNTL_MODE enum
4622 */
4623
4624typedef enum DIG_BE_CNTL_MODE {
4625DIG_BE_DP_SST_MODE                       = 0x00000000,
4626DIG_BE_RESERVED1                         = 0x00000001,
4627DIG_BE_TMDS_DVI_MODE                     = 0x00000002,
4628DIG_BE_TMDS_HDMI_MODE                    = 0x00000003,
4629DIG_BE_SDVO_RESERVED                     = 0x00000004,
4630DIG_BE_DP_MST_MODE                       = 0x00000005,
4631DIG_BE_RESERVED2                         = 0x00000006,
4632DIG_BE_RESERVED3                         = 0x00000007,
4633} DIG_BE_CNTL_MODE;
4634
4635/*
4636 * DIG_BE_CNTL_HPD_SELECT enum
4637 */
4638
4639typedef enum DIG_BE_CNTL_HPD_SELECT {
4640DIG_BE_CNTL_HPD1                         = 0x00000000,
4641DIG_BE_CNTL_HPD2                         = 0x00000001,
4642DIG_BE_CNTL_HPD3                         = 0x00000002,
4643DIG_BE_CNTL_HPD4                         = 0x00000003,
4644DIG_BE_CNTL_HPD5                         = 0x00000004,
4645DIG_BE_CNTL_HPD6                         = 0x00000005,
4646} DIG_BE_CNTL_HPD_SELECT;
4647
4648/*
4649 * LVTMA_RANDOM_PATTERN_SEED_RAN_PAT enum
4650 */
4651
4652typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT {
4653LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS     = 0x00000000,
4654LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH   = 0x00000001,
4655} LVTMA_RANDOM_PATTERN_SEED_RAN_PAT;
4656
4657/*
4658 * TMDS_SYNC_PHASE enum
4659 */
4660
4661typedef enum TMDS_SYNC_PHASE {
4662TMDS_NOT_SYNC_PHASE_ON_FRAME_START       = 0x00000000,
4663TMDS_SYNC_PHASE_ON_FRAME_START           = 0x00000001,
4664} TMDS_SYNC_PHASE;
4665
4666/*
4667 * TMDS_DATA_SYNCHRONIZATION_DSINTSEL enum
4668 */
4669
4670typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL {
4671TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS  = 0x00000000,
4672TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL  = 0x00000001,
4673} TMDS_DATA_SYNCHRONIZATION_DSINTSEL;
4674
4675/*
4676 * TMDS_TRANSMITTER_ENABLE_HPD_MASK enum
4677 */
4678
4679typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK {
4680TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE   = 0x00000000,
4681TMDS_TRANSMITTER_HPD_MASK_OVERRIDE       = 0x00000001,
4682} TMDS_TRANSMITTER_ENABLE_HPD_MASK;
4683
4684/*
4685 * TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK enum
4686 */
4687
4688typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK {
4689TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE  = 0x00000000,
4690TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE  = 0x00000001,
4691} TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK;
4692
4693/*
4694 * TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK enum
4695 */
4696
4697typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK {
4698TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE  = 0x00000000,
4699TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE  = 0x00000001,
4700} TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK;
4701
4702/*
4703 * TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK enum
4704 */
4705
4706typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK {
4707TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE  = 0x00000000,
4708TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON  = 0x00000001,
4709TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON  = 0x00000002,
4710TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE  = 0x00000003,
4711} TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK;
4712
4713/*
4714 * TMDS_TRANSMITTER_CONTROL_IDSCKSELA enum
4715 */
4716
4717typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA {
4718TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK   = 0x00000000,
4719TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK     = 0x00000001,
4720} TMDS_TRANSMITTER_CONTROL_IDSCKSELA;
4721
4722/*
4723 * TMDS_TRANSMITTER_CONTROL_IDSCKSELB enum
4724 */
4725
4726typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB {
4727TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK   = 0x00000000,
4728TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK     = 0x00000001,
4729} TMDS_TRANSMITTER_CONTROL_IDSCKSELB;
4730
4731/*
4732 * TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN enum
4733 */
4734
4735typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN {
4736TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE   = 0x00000000,
4737TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE    = 0x00000001,
4738} TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN;
4739
4740/*
4741 * TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK enum
4742 */
4743
4744typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK {
4745TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD      = 0x00000000,
4746TMDS_TRANSMITTER_PLL_RST_ON_HPD          = 0x00000001,
4747} TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK;
4748
4749/*
4750 * TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS enum
4751 */
4752
4753typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS {
4754TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK   = 0x00000000,
4755TMDS_TRANSMITTER_TMCLK_FROM_PADS         = 0x00000001,
4756} TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS;
4757
4758/*
4759 * TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS enum
4760 */
4761
4762typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS {
4763TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK   = 0x00000000,
4764TMDS_TRANSMITTER_TDCLK_FROM_PADS         = 0x00000001,
4765} TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS;
4766
4767/*
4768 * TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN enum
4769 */
4770
4771typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN {
4772TMDS_TRANSMITTER_PLLSEL_BY_HW            = 0x00000000,
4773TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW  = 0x00000001,
4774} TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN;
4775
4776/*
4777 * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA enum
4778 */
4779
4780typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA {
4781TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT    = 0x00000000,
4782TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT  = 0x00000001,
4783} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA;
4784
4785/*
4786 * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB enum
4787 */
4788
4789typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB {
4790TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT    = 0x00000000,
4791TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT  = 0x00000001,
4792} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB;
4793
4794/*
4795 * TMDS_REG_TEST_OUTPUTA_CNTLA enum
4796 */
4797
4798typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA {
4799TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0      = 0x00000000,
4800TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1      = 0x00000001,
4801TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2      = 0x00000002,
4802TMDS_REG_TEST_OUTPUTA_CNTLA_NA           = 0x00000003,
4803} TMDS_REG_TEST_OUTPUTA_CNTLA;
4804
4805/*
4806 * TMDS_REG_TEST_OUTPUTB_CNTLB enum
4807 */
4808
4809typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB {
4810TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0      = 0x00000000,
4811TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1      = 0x00000001,
4812TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2      = 0x00000002,
4813TMDS_REG_TEST_OUTPUTB_CNTLB_NA           = 0x00000003,
4814} TMDS_REG_TEST_OUTPUTB_CNTLB;
4815
4816/*******************************************************
4817 * DCP Enums
4818 *******************************************************/
4819
4820/*
4821 * DCP_GRPH_ENABLE enum
4822 */
4823
4824typedef enum DCP_GRPH_ENABLE {
4825DCP_GRPH_ENABLE_FALSE                    = 0x00000000,
4826DCP_GRPH_ENABLE_TRUE                     = 0x00000001,
4827} DCP_GRPH_ENABLE;
4828
4829/*
4830 * DCP_GRPH_KEYER_ALPHA_SEL enum
4831 */
4832
4833typedef enum DCP_GRPH_KEYER_ALPHA_SEL {
4834DCP_GRPH_KEYER_ALPHA_SEL_FALSE           = 0x00000000,
4835DCP_GRPH_KEYER_ALPHA_SEL_TRUE            = 0x00000001,
4836} DCP_GRPH_KEYER_ALPHA_SEL;
4837
4838/*
4839 * DCP_GRPH_DEPTH enum
4840 */
4841
4842typedef enum DCP_GRPH_DEPTH {
4843DCP_GRPH_DEPTH_8BPP                      = 0x00000000,
4844DCP_GRPH_DEPTH_16BPP                     = 0x00000001,
4845DCP_GRPH_DEPTH_32BPP                     = 0x00000002,
4846DCP_GRPH_DEPTH_64BPP                     = 0x00000003,
4847} DCP_GRPH_DEPTH;
4848
4849/*
4850 * DCP_GRPH_NUM_BANKS enum
4851 */
4852
4853typedef enum DCP_GRPH_NUM_BANKS {
4854DCP_GRPH_NUM_BANKS_1BANK                 = 0x00000000,
4855DCP_GRPH_NUM_BANKS_2BANK                 = 0x00000001,
4856DCP_GRPH_NUM_BANKS_4BANK                 = 0x00000002,
4857DCP_GRPH_NUM_BANKS_8BANK                 = 0x00000003,
4858DCP_GRPH_NUM_BANKS_16BANK                = 0x00000004,
4859} DCP_GRPH_NUM_BANKS;
4860
4861/*
4862 * DCP_GRPH_NUM_PIPES enum
4863 */
4864
4865typedef enum DCP_GRPH_NUM_PIPES {
4866DCP_GRPH_NUM_PIPES_1PIPE                 = 0x00000000,
4867DCP_GRPH_NUM_PIPES_2PIPE                 = 0x00000001,
4868DCP_GRPH_NUM_PIPES_4PIPE                 = 0x00000002,
4869DCP_GRPH_NUM_PIPES_8PIPE                 = 0x00000003,
4870} DCP_GRPH_NUM_PIPES;
4871
4872/*
4873 * DCP_GRPH_FORMAT enum
4874 */
4875
4876typedef enum DCP_GRPH_FORMAT {
4877DCP_GRPH_FORMAT_8BPP                     = 0x00000000,
4878DCP_GRPH_FORMAT_16BPP                    = 0x00000001,
4879DCP_GRPH_FORMAT_32BPP                    = 0x00000002,
4880DCP_GRPH_FORMAT_64BPP                    = 0x00000003,
4881} DCP_GRPH_FORMAT;
4882
4883/*
4884 * DCP_GRPH_ADDRESS_TRANSLATION_ENABLE enum
4885 */
4886
4887typedef enum DCP_GRPH_ADDRESS_TRANSLATION_ENABLE {
4888DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE  = 0x00000000,
4889DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE  = 0x00000001,
4890} DCP_GRPH_ADDRESS_TRANSLATION_ENABLE;
4891
4892/*
4893 * DCP_GRPH_SW_MODE enum
4894 */
4895
4896typedef enum DCP_GRPH_SW_MODE {
4897DCP_GRPH_SW_MODE_0                       = 0x00000000,
4898DCP_GRPH_SW_MODE_2                       = 0x00000002,
4899DCP_GRPH_SW_MODE_3                       = 0x00000003,
4900DCP_GRPH_SW_MODE_22                      = 0x00000016,
4901DCP_GRPH_SW_MODE_23                      = 0x00000017,
4902DCP_GRPH_SW_MODE_26                      = 0x0000001a,
4903DCP_GRPH_SW_MODE_27                      = 0x0000001b,
4904DCP_GRPH_SW_MODE_30                      = 0x0000001e,
4905DCP_GRPH_SW_MODE_31                      = 0x0000001f,
4906} DCP_GRPH_SW_MODE;
4907
4908/*
4909 * DCP_GRPH_COLOR_EXPANSION_MODE enum
4910 */
4911
4912typedef enum DCP_GRPH_COLOR_EXPANSION_MODE {
4913DCP_GRPH_COLOR_EXPANSION_MODE_DEXP       = 0x00000000,
4914DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP       = 0x00000001,
4915} DCP_GRPH_COLOR_EXPANSION_MODE;
4916
4917/*
4918 * DCP_GRPH_LUT_10BIT_BYPASS_EN enum
4919 */
4920
4921typedef enum DCP_GRPH_LUT_10BIT_BYPASS_EN {
4922DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE       = 0x00000000,
4923DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE        = 0x00000001,
4924} DCP_GRPH_LUT_10BIT_BYPASS_EN;
4925
4926/*
4927 * DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN enum
4928 */
4929
4930typedef enum DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN {
4931DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE  = 0x00000000,
4932DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE  = 0x00000001,
4933} DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN;
4934
4935/*
4936 * DCP_GRPH_ENDIAN_SWAP enum
4937 */
4938
4939typedef enum DCP_GRPH_ENDIAN_SWAP {
4940DCP_GRPH_ENDIAN_SWAP_NONE                = 0x00000000,
4941DCP_GRPH_ENDIAN_SWAP_8IN16               = 0x00000001,
4942DCP_GRPH_ENDIAN_SWAP_8IN32               = 0x00000002,
4943DCP_GRPH_ENDIAN_SWAP_8IN64               = 0x00000003,
4944} DCP_GRPH_ENDIAN_SWAP;
4945
4946/*
4947 * DCP_GRPH_RED_CROSSBAR enum
4948 */
4949
4950typedef enum DCP_GRPH_RED_CROSSBAR {
4951DCP_GRPH_RED_CROSSBAR_FROM_R             = 0x00000000,
4952DCP_GRPH_RED_CROSSBAR_FROM_G             = 0x00000001,
4953DCP_GRPH_RED_CROSSBAR_FROM_B             = 0x00000002,
4954DCP_GRPH_RED_CROSSBAR_FROM_A             = 0x00000003,
4955} DCP_GRPH_RED_CROSSBAR;
4956
4957/*
4958 * DCP_GRPH_GREEN_CROSSBAR enum
4959 */
4960
4961typedef enum DCP_GRPH_GREEN_CROSSBAR {
4962DCP_GRPH_GREEN_CROSSBAR_FROM_G           = 0x00000000,
4963DCP_GRPH_GREEN_CROSSBAR_FROM_B           = 0x00000001,
4964DCP_GRPH_GREEN_CROSSBAR_FROM_A           = 0x00000002,
4965DCP_GRPH_GREEN_CROSSBAR_FROM_R           = 0x00000003,
4966} DCP_GRPH_GREEN_CROSSBAR;
4967
4968/*
4969 * DCP_GRPH_BLUE_CROSSBAR enum
4970 */
4971
4972typedef enum DCP_GRPH_BLUE_CROSSBAR {
4973DCP_GRPH_BLUE_CROSSBAR_FROM_B            = 0x00000000,
4974DCP_GRPH_BLUE_CROSSBAR_FROM_A            = 0x00000001,
4975DCP_GRPH_BLUE_CROSSBAR_FROM_R            = 0x00000002,
4976DCP_GRPH_BLUE_CROSSBAR_FROM_G            = 0x00000003,
4977} DCP_GRPH_BLUE_CROSSBAR;
4978
4979/*
4980 * DCP_GRPH_ALPHA_CROSSBAR enum
4981 */
4982
4983typedef enum DCP_GRPH_ALPHA_CROSSBAR {
4984DCP_GRPH_ALPHA_CROSSBAR_FROM_A           = 0x00000000,
4985DCP_GRPH_ALPHA_CROSSBAR_FROM_R           = 0x00000001,
4986DCP_GRPH_ALPHA_CROSSBAR_FROM_G           = 0x00000002,
4987DCP_GRPH_ALPHA_CROSSBAR_FROM_B           = 0x00000003,
4988} DCP_GRPH_ALPHA_CROSSBAR;
4989
4990/*
4991 * DCP_GRPH_PRIMARY_DFQ_ENABLE enum
4992 */
4993
4994typedef enum DCP_GRPH_PRIMARY_DFQ_ENABLE {
4995DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE        = 0x00000000,
4996DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE         = 0x00000001,
4997} DCP_GRPH_PRIMARY_DFQ_ENABLE;
4998
4999/*
5000 * DCP_GRPH_SECONDARY_DFQ_ENABLE enum

5001 */
5002
5003typedef enum DCP_GRPH_SECONDARY_DFQ_ENABLE {
5004DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE      = 0x00000000,
5005DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE       = 0x00000001,
5006} DCP_GRPH_SECONDARY_DFQ_ENABLE;
5007
5008/*
5009 * DCP_GRPH_INPUT_GAMMA_MODE enum
5010 */
5011
5012typedef enum DCP_GRPH_INPUT_GAMMA_MODE {
5013DCP_GRPH_INPUT_GAMMA_MODE_LUT            = 0x00000000,
5014DCP_GRPH_INPUT_GAMMA_MODE_BYPASS         = 0x00000001,
5015} DCP_GRPH_INPUT_GAMMA_MODE;
5016
5017/*
5018 * DCP_GRPH_MODE_UPDATE_PENDING enum
5019 */
5020
5021typedef enum DCP_GRPH_MODE_UPDATE_PENDING {
5022DCP_GRPH_MODE_UPDATE_PENDING_FALSE       = 0x00000000,
5023DCP_GRPH_MODE_UPDATE_PENDING_TRUE        = 0x00000001,
5024} DCP_GRPH_MODE_UPDATE_PENDING;
5025
5026/*
5027 * DCP_GRPH_MODE_UPDATE_TAKEN enum
5028 */
5029
5030typedef enum DCP_GRPH_MODE_UPDATE_TAKEN {
5031DCP_GRPH_MODE_UPDATE_TAKEN_FALSE         = 0x00000000,
5032DCP_GRPH_MODE_UPDATE_TAKEN_TRUE          = 0x00000001,
5033} DCP_GRPH_MODE_UPDATE_TAKEN;
5034
5035/*
5036 * DCP_GRPH_SURFACE_UPDATE_PENDING enum
5037 */
5038
5039typedef enum DCP_GRPH_SURFACE_UPDATE_PENDING {
5040DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE    = 0x00000000,
5041DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE     = 0x00000001,
5042} DCP_GRPH_SURFACE_UPDATE_PENDING;
5043
5044/*
5045 * DCP_GRPH_SURFACE_UPDATE_TAKEN enum
5046 */
5047
5048typedef enum DCP_GRPH_SURFACE_UPDATE_TAKEN {
5049DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE      = 0x00000000,
5050DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE       = 0x00000001,
5051} DCP_GRPH_SURFACE_UPDATE_TAKEN;
5052
5053/*
5054 * DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE enum
5055 */
5056
5057typedef enum DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE {
5058DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE = 0x00000000,
5059DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE = 0x00000001,
5060} DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE;
5061
5062/*
5063 * DCP_GRPH_UPDATE_LOCK enum
5064 */
5065
5066typedef enum DCP_GRPH_UPDATE_LOCK {
5067DCP_GRPH_UPDATE_LOCK_FALSE               = 0x00000000,
5068DCP_GRPH_UPDATE_LOCK_TRUE                = 0x00000001,
5069} DCP_GRPH_UPDATE_LOCK;
5070
5071/*
5072 * DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK enum
5073 */
5074
5075typedef enum DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
5076DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE  = 0x00000000,
5077DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE  = 0x00000001,
5078} DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK;
5079
5080/*
5081 * DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE enum
5082 */
5083
5084typedef enum DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
5085DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE  = 0x00000000,
5086DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE  = 0x00000001,
5087} DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE;
5088
5089/*
5090 * DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE enum
5091 */
5092
5093typedef enum DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
5094DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE  = 0x00000000,
5095DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE  = 0x00000001,
5096} DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE;
5097
5098/*
5099 * DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN enum
5100 */
5101
5102typedef enum DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN {
5103DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE  = 0x00000000,
5104DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE  = 0x00000001,
5105} DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
5106
5107/*
5108 * DCP_GRPH_XDMA_SUPER_AA_EN enum
5109 */
5110
5111typedef enum DCP_GRPH_XDMA_SUPER_AA_EN {
5112DCP_GRPH_XDMA_SUPER_AA_EN_FALSE          = 0x00000000,
5113DCP_GRPH_XDMA_SUPER_AA_EN_TRUE           = 0x00000001,
5114} DCP_GRPH_XDMA_SUPER_AA_EN;
5115
5116/*
5117 * DCP_GRPH_DFQ_RESET enum
5118 */
5119
5120typedef enum DCP_GRPH_DFQ_RESET {
5121DCP_GRPH_DFQ_RESET_FALSE                 = 0x00000000,
5122DCP_GRPH_DFQ_RESET_TRUE                  = 0x00000001,
5123} DCP_GRPH_DFQ_RESET;
5124
5125/*
5126 * DCP_GRPH_DFQ_SIZE enum
5127 */
5128
5129typedef enum DCP_GRPH_DFQ_SIZE {
5130DCP_GRPH_DFQ_SIZE_DEEP1                  = 0x00000000,
5131DCP_GRPH_DFQ_SIZE_DEEP2                  = 0x00000001,
5132DCP_GRPH_DFQ_SIZE_DEEP3                  = 0x00000002,
5133DCP_GRPH_DFQ_SIZE_DEEP4                  = 0x00000003,
5134DCP_GRPH_DFQ_SIZE_DEEP5                  = 0x00000004,
5135DCP_GRPH_DFQ_SIZE_DEEP6                  = 0x00000005,
5136DCP_GRPH_DFQ_SIZE_DEEP7                  = 0x00000006,
5137DCP_GRPH_DFQ_SIZE_DEEP8                  = 0x00000007,
5138} DCP_GRPH_DFQ_SIZE;
5139
5140/*
5141 * DCP_GRPH_DFQ_MIN_FREE_ENTRIES enum
5142 */
5143
5144typedef enum DCP_GRPH_DFQ_MIN_FREE_ENTRIES {
5145DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1          = 0x00000000,
5146DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2          = 0x00000001,
5147DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3          = 0x00000002,
5148DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4          = 0x00000003,
5149DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5          = 0x00000004,
5150DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6          = 0x00000005,
5151DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7          = 0x00000006,
5152DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8          = 0x00000007,
5153} DCP_GRPH_DFQ_MIN_FREE_ENTRIES;
5154
5155/*
5156 * DCP_GRPH_DFQ_RESET_ACK enum
5157 */
5158
5159typedef enum DCP_GRPH_DFQ_RESET_ACK {
5160DCP_GRPH_DFQ_RESET_ACK_FALSE             = 0x00000000,
5161DCP_GRPH_DFQ_RESET_ACK_TRUE              = 0x00000001,
5162} DCP_GRPH_DFQ_RESET_ACK;
5163
5164/*
5165 * DCP_GRPH_PFLIP_INT_CLEAR enum
5166 */
5167
5168typedef enum DCP_GRPH_PFLIP_INT_CLEAR {
5169DCP_GRPH_PFLIP_INT_CLEAR_FALSE           = 0x00000000,
5170DCP_GRPH_PFLIP_INT_CLEAR_TRUE            = 0x00000001,
5171} DCP_GRPH_PFLIP_INT_CLEAR;
5172
5173/*
5174 * DCP_GRPH_PFLIP_INT_MASK enum
5175 */
5176
5177typedef enum DCP_GRPH_PFLIP_INT_MASK {
5178DCP_GRPH_PFLIP_INT_MASK_FALSE            = 0x00000000,
5179DCP_GRPH_PFLIP_INT_MASK_TRUE             = 0x00000001,
5180} DCP_GRPH_PFLIP_INT_MASK;
5181
5182/*
5183 * DCP_GRPH_PFLIP_INT_TYPE enum
5184 */
5185
5186typedef enum DCP_GRPH_PFLIP_INT_TYPE {
5187DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL     = 0x00000000,
5188DCP_GRPH_PFLIP_INT_TYPE_PULSE            = 0x00000001,
5189} DCP_GRPH_PFLIP_INT_TYPE;
5190
5191/*
5192 * DCP_GRPH_PRESCALE_SELECT enum
5193 */
5194
5195typedef enum DCP_GRPH_PRESCALE_SELECT {
5196DCP_GRPH_PRESCALE_SELECT_FIXED           = 0x00000000,
5197DCP_GRPH_PRESCALE_SELECT_FLOATING        = 0x00000001,
5198} DCP_GRPH_PRESCALE_SELECT;
5199
5200/*
5201 * DCP_GRPH_PRESCALE_R_SIGN enum
5202 */
5203
5204typedef enum DCP_GRPH_PRESCALE_R_SIGN {
5205DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED        = 0x00000000,
5206DCP_GRPH_PRESCALE_R_SIGN_SIGNED          = 0x00000001,
5207} DCP_GRPH_PRESCALE_R_SIGN;
5208
5209/*
5210 * DCP_GRPH_PRESCALE_G_SIGN enum
5211 */
5212
5213typedef enum DCP_GRPH_PRESCALE_G_SIGN {
5214DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED        = 0x00000000,
5215DCP_GRPH_PRESCALE_G_SIGN_SIGNED          = 0x00000001,
5216} DCP_GRPH_PRESCALE_G_SIGN;
5217
5218/*
5219 * DCP_GRPH_PRESCALE_B_SIGN enum
5220 */
5221
5222typedef enum DCP_GRPH_PRESCALE_B_SIGN {
5223DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED        = 0x00000000,
5224DCP_GRPH_PRESCALE_B_SIGN_SIGNED          = 0x00000001,
5225} DCP_GRPH_PRESCALE_B_SIGN;
5226
5227/*
5228 * DCP_GRPH_PRESCALE_BYPASS enum
5229 */
5230
5231typedef enum DCP_GRPH_PRESCALE_BYPASS {
5232DCP_GRPH_PRESCALE_BYPASS_FALSE           = 0x00000000,
5233DCP_GRPH_PRESCALE_BYPASS_TRUE            = 0x00000001,
5234} DCP_GRPH_PRESCALE_BYPASS;
5235
5236/*
5237 * DCP_INPUT_CSC_GRPH_MODE enum
5238 */
5239
5240typedef enum DCP_INPUT_CSC_GRPH_MODE {
5241DCP_INPUT_CSC_GRPH_MODE_BYPASS           = 0x00000000,
5242DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF   = 0x00000001,
5243DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF      = 0x00000002,
5244DCP_INPUT_CSC_GRPH_MODE_RESERVED         = 0x00000003,
5245} DCP_INPUT_CSC_GRPH_MODE;
5246
5247/*
5248 * DCP_OUTPUT_CSC_GRPH_MODE enum
5249 */
5250
5251typedef enum DCP_OUTPUT_CSC_GRPH_MODE {
5252DCP_OUTPUT_CSC_GRPH_MODE_BYPASS          = 0x00000000,
5253DCP_OUTPUT_CSC_GRPH_MODE_RGB             = 0x00000001,
5254DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601        = 0x00000002,
5255DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709        = 0x00000003,
5256DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF  = 0x00000004,
5257DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF     = 0x00000005,
5258DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0       = 0x00000006,
5259DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1       = 0x00000007,
5260} DCP_OUTPUT_CSC_GRPH_MODE;
5261
5262/*
5263 * DCP_DENORM_MODE enum
5264 */
5265
5266typedef enum DCP_DENORM_MODE {
5267DCP_DENORM_MODE_UNITY                    = 0x00000000,
5268DCP_DENORM_MODE_6BIT                     = 0x00000001,
5269DCP_DENORM_MODE_8BIT                     = 0x00000002,
5270DCP_DENORM_MODE_10BIT                    = 0x00000003,
5271DCP_DENORM_MODE_11BIT                    = 0x00000004,
5272DCP_DENORM_MODE_12BIT                    = 0x00000005,
5273DCP_DENORM_MODE_RESERVED0                = 0x00000006,
5274DCP_DENORM_MODE_RESERVED1                = 0x00000007,
5275} DCP_DENORM_MODE;
5276
5277/*
5278 * DCP_DENORM_14BIT_OUT enum
5279 */
5280
5281typedef enum DCP_DENORM_14BIT_OUT {
5282DCP_DENORM_14BIT_OUT_FALSE               = 0x00000000,
5283DCP_DENORM_14BIT_OUT_TRUE                = 0x00000001,
5284} DCP_DENORM_14BIT_OUT;
5285
5286/*
5287 * DCP_OUT_ROUND_TRUNC_MODE enum
5288 */
5289
5290typedef enum DCP_OUT_ROUND_TRUNC_MODE {
5291DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12     = 0x00000000,
5292DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11     = 0x00000001,
5293DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10     = 0x00000002,
5294DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9      = 0x00000003,
5295DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8      = 0x00000004,
5296DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED  = 0x00000005,
5297DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14     = 0x00000006,
5298DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13     = 0x00000007,
5299DCP_OUT_ROUND_TRUNC_MODE_ROUND_12        = 0x00000008,
5300DCP_OUT_ROUND_TRUNC_MODE_ROUND_11        = 0x00000009,
5301DCP_OUT_ROUND_TRUNC_MODE_ROUND_10        = 0x0000000a,
5302DCP_OUT_ROUND_TRUNC_MODE_ROUND_9         = 0x0000000b,
5303DCP_OUT_ROUND_TRUNC_MODE_ROUND_8         = 0x0000000c,
5304DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED  = 0x0000000d,
5305DCP_OUT_ROUND_TRUNC_MODE_ROUND_14        = 0x0000000e,
5306DCP_OUT_ROUND_TRUNC_MODE_ROUND_13        = 0x0000000f,
5307} DCP_OUT_ROUND_TRUNC_MODE;
5308
5309/*
5310 * DCP_KEY_MODE enum
5311 */
5312
5313typedef enum DCP_KEY_MODE {
5314DCP_KEY_MODE_ALPHA0                      = 0x00000000,
5315DCP_KEY_MODE_ALPHA1                      = 0x00000001,
5316DCP_KEY_MODE_IN_RANGE_ALPHA1             = 0x00000002,
5317DCP_KEY_MODE_IN_RANGE_ALPHA0             = 0x00000003,
5318} DCP_KEY_MODE;
5319
5320/*
5321 * DCP_GRPH_DEGAMMA_MODE enum
5322 */
5323
5324typedef enum DCP_GRPH_DEGAMMA_MODE {
5325DCP_GRPH_DEGAMMA_MODE_BYPASS             = 0x00000000,
5326DCP_GRPH_DEGAMMA_MODE_ROMA               = 0x00000001,
5327DCP_GRPH_DEGAMMA_MODE_ROMB               = 0x00000002,
5328DCP_GRPH_DEGAMMA_MODE_RESERVED           = 0x00000003,
5329} DCP_GRPH_DEGAMMA_MODE;
5330
5331/*
5332 * DCP_CURSOR_DEGAMMA_MODE enum
5333 */
5334
5335typedef enum DCP_CURSOR_DEGAMMA_MODE {
5336DCP_CURSOR_DEGAMMA_MODE_BYPASS           = 0x00000000,
5337DCP_CURSOR_DEGAMMA_MODE_ROMA             = 0x00000001,
5338DCP_CURSOR_DEGAMMA_MODE_ROMB             = 0x00000002,
5339DCP_CURSOR_DEGAMMA_MODE_RESERVED         = 0x00000003,
5340} DCP_CURSOR_DEGAMMA_MODE;
5341
5342/*
5343 * DCP_GRPH_GAMUT_REMAP_MODE enum
5344 */
5345
5346typedef enum DCP_GRPH_GAMUT_REMAP_MODE {
5347DCP_GRPH_GAMUT_REMAP_MODE_BYPASS         = 0x00000000,
5348DCP_GRPH_GAMUT_REMAP_MODE_ROMA           = 0x00000001,
5349DCP_GRPH_GAMUT_REMAP_MODE_ROMB           = 0x00000002,
5350DCP_GRPH_GAMUT_REMAP_MODE_RESERVED       = 0x00000003,
5351} DCP_GRPH_GAMUT_REMAP_MODE;
5352
5353/*
5354 * DCP_SPATIAL_DITHER_EN enum
5355 */
5356
5357typedef enum DCP_SPATIAL_DITHER_EN {
5358DCP_SPATIAL_DITHER_EN_FALSE              = 0x00000000,
5359DCP_SPATIAL_DITHER_EN_TRUE               = 0x00000001,
5360} DCP_SPATIAL_DITHER_EN;
5361
5362/*
5363 * DCP_SPATIAL_DITHER_MODE enum
5364 */
5365
5366typedef enum DCP_SPATIAL_DITHER_MODE {
5367DCP_SPATIAL_DITHER_MODE_BYPASS           = 0x00000000,
5368DCP_SPATIAL_DITHER_MODE_ROMA             = 0x00000001,
5369DCP_SPATIAL_DITHER_MODE_ROMB             = 0x00000002,
5370DCP_SPATIAL_DITHER_MODE_RESERVED         = 0x00000003,
5371} DCP_SPATIAL_DITHER_MODE;
5372
5373/*
5374 * DCP_SPATIAL_DITHER_DEPTH enum
5375 */
5376
5377typedef enum DCP_SPATIAL_DITHER_DEPTH {
5378DCP_SPATIAL_DITHER_DEPTH_30BPP           = 0x00000000,
5379DCP_SPATIAL_DITHER_DEPTH_24BPP           = 0x00000001,
5380DCP_SPATIAL_DITHER_DEPTH_36BPP           = 0x00000002,
5381DCP_SPATIAL_DITHER_DEPTH_UNDEFINED       = 0x00000003,
5382} DCP_SPATIAL_DITHER_DEPTH;
5383
5384/*
5385 * DCP_FRAME_RANDOM_ENABLE enum
5386 */
5387
5388typedef enum DCP_FRAME_RANDOM_ENABLE {
5389DCP_FRAME_RANDOM_ENABLE_FALSE            = 0x00000000,
5390DCP_FRAME_RANDOM_ENABLE_TRUE             = 0x00000001,
5391} DCP_FRAME_RANDOM_ENABLE;
5392
5393/*
5394 * DCP_RGB_RANDOM_ENABLE enum
5395 */
5396
5397typedef enum DCP_RGB_RANDOM_ENABLE {
5398DCP_RGB_RANDOM_ENABLE_FALSE              = 0x00000000,
5399DCP_RGB_RANDOM_ENABLE_TRUE               = 0x00000001,
5400} DCP_RGB_RANDOM_ENABLE;
5401
5402/*
5403 * DCP_HIGHPASS_RANDOM_ENABLE enum
5404 */
5405
5406typedef enum DCP_HIGHPASS_RANDOM_ENABLE {
5407DCP_HIGHPASS_RANDOM_ENABLE_FALSE         = 0x00000000,
5408DCP_HIGHPASS_RANDOM_ENABLE_TRUE          = 0x00000001,
5409} DCP_HIGHPASS_RANDOM_ENABLE;
5410
5411/*
5412 * DCP_CURSOR_EN enum
5413 */
5414
5415typedef enum DCP_CURSOR_EN {
5416DCP_CURSOR_EN_FALSE                      = 0x00000000,
5417DCP_CURSOR_EN_TRUE                       = 0x00000001,
5418} DCP_CURSOR_EN;
5419
5420/*
5421 * DCP_CUR_INV_TRANS_CLAMP enum
5422 */
5423
5424typedef enum DCP_CUR_INV_TRANS_CLAMP {
5425DCP_CUR_INV_TRANS_CLAMP_FALSE            = 0x00000000,
5426DCP_CUR_INV_TRANS_CLAMP_TRUE             = 0x00000001,
5427} DCP_CUR_INV_TRANS_CLAMP;
5428
5429/*
5430 * DCP_CURSOR_MODE enum
5431 */
5432
5433typedef enum DCP_CURSOR_MODE {
5434DCP_CURSOR_MODE_MONO_2BPP                = 0x00000000,
5435DCP_CURSOR_MODE_24BPP_1BIT               = 0x00000001,
5436DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI      = 0x00000002,
5437DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI    = 0x00000003,
5438} DCP_CURSOR_MODE;
5439
5440/*
5441 * DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM enum
5442 */
5443
5444typedef enum DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM {
5445DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_ONE  = 0x00000000,
5446DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_TWO  = 0x00000001,
5447} DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM;
5448
5449/*
5450 * DCP_CURSOR_2X_MAGNIFY enum
5451 */
5452
5453typedef enum DCP_CURSOR_2X_MAGNIFY {
5454DCP_CURSOR_2X_MAGNIFY_FALSE              = 0x00000000,
5455DCP_CURSOR_2X_MAGNIFY_TRUE               = 0x00000001,
5456} DCP_CURSOR_2X_MAGNIFY;
5457
5458/*
5459 * DCP_CURSOR_FORCE_MC_ON enum
5460 */
5461
5462typedef enum DCP_CURSOR_FORCE_MC_ON {
5463DCP_CURSOR_FORCE_MC_ON_FALSE             = 0x00000000,
5464DCP_CURSOR_FORCE_MC_ON_TRUE              = 0x00000001,
5465} DCP_CURSOR_FORCE_MC_ON;
5466
5467/*
5468 * DCP_CURSOR_URGENT_CONTROL enum
5469 */
5470
5471typedef enum DCP_CURSOR_URGENT_CONTROL {
5472DCP_CURSOR_URGENT_CONTROL_MODE_0         = 0x00000000,
5473DCP_CURSOR_URGENT_CONTROL_MODE_1         = 0x00000001,
5474DCP_CURSOR_URGENT_CONTROL_MODE_2         = 0x00000002,
5475DCP_CURSOR_URGENT_CONTROL_MODE_3         = 0x00000003,
5476DCP_CURSOR_URGENT_CONTROL_MODE_4         = 0x00000004,
5477} DCP_CURSOR_URGENT_CONTROL;
5478
5479/*
5480 * DCP_CURSOR_UPDATE_PENDING enum
5481 */
5482
5483typedef enum DCP_CURSOR_UPDATE_PENDING {
5484DCP_CURSOR_UPDATE_PENDING_FALSE          = 0x00000000,
5485DCP_CURSOR_UPDATE_PENDING_TRUE           = 0x00000001,
5486} DCP_CURSOR_UPDATE_PENDING;
5487
5488/*
5489 * DCP_CURSOR_UPDATE_TAKEN enum
5490 */
5491
5492typedef enum DCP_CURSOR_UPDATE_TAKEN {
5493DCP_CURSOR_UPDATE_TAKEN_FALSE            = 0x00000000,
5494DCP_CURSOR_UPDATE_TAKEN_TRUE             = 0x00000001,
5495} DCP_CURSOR_UPDATE_TAKEN;
5496
5497/*
5498 * DCP_CURSOR_UPDATE_LOCK enum
5499 */
5500
5501typedef enum DCP_CURSOR_UPDATE_LOCK {
5502DCP_CURSOR_UPDATE_LOCK_FALSE             = 0x00000000,
5503DCP_CURSOR_UPDATE_LOCK_TRUE              = 0x00000001,
5504} DCP_CURSOR_UPDATE_LOCK;
5505
5506/*
5507 * DCP_CURSOR_DISABLE_MULTIPLE_UPDATE enum
5508 */
5509
5510typedef enum DCP_CURSOR_DISABLE_MULTIPLE_UPDATE {
5511DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE  = 0x00000000,
5512DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE  = 0x00000001,
5513} DCP_CURSOR_DISABLE_MULTIPLE_UPDATE;
5514
5515/*
5516 * DCP_CURSOR_UPDATE_STEREO_MODE enum
5517 */
5518
5519typedef enum DCP_CURSOR_UPDATE_STEREO_MODE {
5520DCP_CURSOR_UPDATE_STEREO_MODE_BOTH       = 0x00000000,
5521DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY  = 0x00000001,
5522DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED  = 0x00000002,
5523DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY  = 0x00000003,
5524} DCP_CURSOR_UPDATE_STEREO_MODE;
5525
5526/*
5527 * DCP_CUR2_INV_TRANS_CLAMP enum
5528 */
5529
5530typedef enum DCP_CUR2_INV_TRANS_CLAMP {
5531DCP_CUR2_INV_TRANS_CLAMP_FALSE           = 0x00000000,
5532DCP_CUR2_INV_TRANS_CLAMP_TRUE            = 0x00000001,
5533} DCP_CUR2_INV_TRANS_CLAMP;
5534
5535/*
5536 * DCP_CUR_REQUEST_FILTER_DIS enum
5537 */
5538
5539typedef enum DCP_CUR_REQUEST_FILTER_DIS {
5540DCP_CUR_REQUEST_FILTER_DIS_FALSE         = 0x00000000,
5541DCP_CUR_REQUEST_FILTER_DIS_TRUE          = 0x00000001,
5542} DCP_CUR_REQUEST_FILTER_DIS;
5543
5544/*
5545 * DCP_CURSOR_STEREO_EN enum
5546 */
5547
5548typedef enum DCP_CURSOR_STEREO_EN {
5549DCP_CURSOR_STEREO_EN_FALSE               = 0x00000000,
5550DCP_CURSOR_STEREO_EN_TRUE                = 0x00000001,
5551} DCP_CURSOR_STEREO_EN;
5552
5553/*
5554 * DCP_CURSOR_STEREO_OFFSET_YNX enum
5555 */
5556
5557typedef enum DCP_CURSOR_STEREO_OFFSET_YNX {
5558DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION  = 0x00000000,
5559DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION  = 0x00000001,
5560} DCP_CURSOR_STEREO_OFFSET_YNX;
5561
5562/*
5563 * DCP_DC_LUT_RW_MODE enum
5564 */
5565
5566typedef enum DCP_DC_LUT_RW_MODE {
5567DCP_DC_LUT_RW_MODE_256_ENTRY             = 0x00000000,
5568DCP_DC_LUT_RW_MODE_PWL                   = 0x00000001,
5569} DCP_DC_LUT_RW_MODE;
5570
5571/*
5572 * DCP_DC_LUT_VGA_ACCESS_ENABLE enum
5573 */
5574
5575typedef enum DCP_DC_LUT_VGA_ACCESS_ENABLE {
5576DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE       = 0x00000000,
5577DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE        = 0x00000001,
5578} DCP_DC_LUT_VGA_ACCESS_ENABLE;
5579
5580/*
5581 * DCP_DC_LUT_AUTOFILL enum
5582 */
5583
5584typedef enum DCP_DC_LUT_AUTOFILL {
5585DCP_DC_LUT_AUTOFILL_FALSE                = 0x00000000,
5586DCP_DC_LUT_AUTOFILL_TRUE                 = 0x00000001,
5587} DCP_DC_LUT_AUTOFILL;
5588
5589/*
5590 * DCP_DC_LUT_AUTOFILL_DONE enum
5591 */
5592
5593typedef enum DCP_DC_LUT_AUTOFILL_DONE {
5594DCP_DC_LUT_AUTOFILL_DONE_FALSE           = 0x00000000,
5595DCP_DC_LUT_AUTOFILL_DONE_TRUE            = 0x00000001,
5596} DCP_DC_LUT_AUTOFILL_DONE;
5597
5598/*
5599 * DCP_DC_LUT_INC_B enum
5600 */
5601
5602typedef enum DCP_DC_LUT_INC_B {
5603DCP_DC_LUT_INC_B_NA                      = 0x00000000,
5604DCP_DC_LUT_INC_B_2                       = 0x00000001,
5605DCP_DC_LUT_INC_B_4                       = 0x00000002,
5606DCP_DC_LUT_INC_B_8                       = 0x00000003,
5607DCP_DC_LUT_INC_B_16                      = 0x00000004,
5608DCP_DC_LUT_INC_B_32                      = 0x00000005,
5609DCP_DC_LUT_INC_B_64                      = 0x00000006,
5610DCP_DC_LUT_INC_B_128                     = 0x00000007,
5611DCP_DC_LUT_INC_B_256                     = 0x00000008,
5612DCP_DC_LUT_INC_B_512                     = 0x00000009,
5613} DCP_DC_LUT_INC_B;
5614
5615/*
5616 * DCP_DC_LUT_DATA_B_SIGNED_EN enum
5617 */
5618
5619typedef enum DCP_DC_LUT_DATA_B_SIGNED_EN {
5620DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE        = 0x00000000,
5621DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE         = 0x00000001,
5622} DCP_DC_LUT_DATA_B_SIGNED_EN;
5623
5624/*
5625 * DCP_DC_LUT_DATA_B_FLOAT_POINT_EN enum
5626 */
5627
5628typedef enum DCP_DC_LUT_DATA_B_FLOAT_POINT_EN {
5629DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE   = 0x00000000,
5630DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE    = 0x00000001,
5631} DCP_DC_LUT_DATA_B_FLOAT_POINT_EN;
5632
5633/*
5634 * DCP_DC_LUT_DATA_B_FORMAT enum
5635 */
5636
5637typedef enum DCP_DC_LUT_DATA_B_FORMAT {
5638DCP_DC_LUT_DATA_B_FORMAT_U0P10           = 0x00000000,
5639DCP_DC_LUT_DATA_B_FORMAT_S1P10           = 0x00000001,
5640DCP_DC_LUT_DATA_B_FORMAT_U1P11           = 0x00000002,
5641DCP_DC_LUT_DATA_B_FORMAT_U0P12           = 0x00000003,
5642} DCP_DC_LUT_DATA_B_FORMAT;
5643
5644/*
5645 * DCP_DC_LUT_INC_G enum
5646 */
5647
5648typedef enum DCP_DC_LUT_INC_G {
5649DCP_DC_LUT_INC_G_NA                      = 0x00000000,
5650DCP_DC_LUT_INC_G_2                       = 0x00000001,
5651DCP_DC_LUT_INC_G_4                       = 0x00000002,
5652DCP_DC_LUT_INC_G_8                       = 0x00000003,
5653DCP_DC_LUT_INC_G_16                      = 0x00000004,
5654DCP_DC_LUT_INC_G_32                      = 0x00000005,
5655DCP_DC_LUT_INC_G_64                      = 0x00000006,
5656DCP_DC_LUT_INC_G_128                     = 0x00000007,
5657DCP_DC_LUT_INC_G_256                     = 0x00000008,
5658DCP_DC_LUT_INC_G_512                     = 0x00000009,
5659} DCP_DC_LUT_INC_G;
5660
5661/*
5662 * DCP_DC_LUT_DATA_G_SIGNED_EN enum
5663 */
5664
5665typedef enum DCP_DC_LUT_DATA_G_SIGNED_EN {
5666DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE        = 0x00000000,
5667DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE         = 0x00000001,
5668} DCP_DC_LUT_DATA_G_SIGNED_EN;
5669
5670/*
5671 * DCP_DC_LUT_DATA_G_FLOAT_POINT_EN enum
5672 */
5673
5674typedef enum DCP_DC_LUT_DATA_G_FLOAT_POINT_EN {
5675DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE   = 0x00000000,
5676DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE    = 0x00000001,
5677} DCP_DC_LUT_DATA_G_FLOAT_POINT_EN;
5678
5679/*
5680 * DCP_DC_LUT_DATA_G_FORMAT enum
5681 */
5682
5683typedef enum DCP_DC_LUT_DATA_G_FORMAT {
5684DCP_DC_LUT_DATA_G_FORMAT_U0P10           = 0x00000000,
5685DCP_DC_LUT_DATA_G_FORMAT_S1P10           = 0x00000001,
5686DCP_DC_LUT_DATA_G_FORMAT_U1P11           = 0x00000002,
5687DCP_DC_LUT_DATA_G_FORMAT_U0P12           = 0x00000003,
5688} DCP_DC_LUT_DATA_G_FORMAT;
5689
5690/*
5691 * DCP_DC_LUT_INC_R enum
5692 */
5693
5694typedef enum DCP_DC_LUT_INC_R {
5695DCP_DC_LUT_INC_R_NA                      = 0x00000000,
5696DCP_DC_LUT_INC_R_2                       = 0x00000001,
5697DCP_DC_LUT_INC_R_4                       = 0x00000002,
5698DCP_DC_LUT_INC_R_8                       = 0x00000003,
5699DCP_DC_LUT_INC_R_16                      = 0x00000004,
5700DCP_DC_LUT_INC_R_32                      = 0x00000005,
5701DCP_DC_LUT_INC_R_64                      = 0x00000006,
5702DCP_DC_LUT_INC_R_128                     = 0x00000007,
5703DCP_DC_LUT_INC_R_256                     = 0x00000008,
5704DCP_DC_LUT_INC_R_512                     = 0x00000009,
5705} DCP_DC_LUT_INC_R;
5706
5707/*
5708 * DCP_DC_LUT_DATA_R_SIGNED_EN enum
5709 */
5710
5711typedef enum DCP_DC_LUT_DATA_R_SIGNED_EN {
5712DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE        = 0x00000000,
5713DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE         = 0x00000001,
5714} DCP_DC_LUT_DATA_R_SIGNED_EN;
5715
5716/*
5717 * DCP_DC_LUT_DATA_R_FLOAT_POINT_EN enum
5718 */
5719
5720typedef enum DCP_DC_LUT_DATA_R_FLOAT_POINT_EN {
5721DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE   = 0x00000000,
5722DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE    = 0x00000001,
5723} DCP_DC_LUT_DATA_R_FLOAT_POINT_EN;
5724
5725/*
5726 * DCP_DC_LUT_DATA_R_FORMAT enum
5727 */
5728
5729typedef enum DCP_DC_LUT_DATA_R_FORMAT {
5730DCP_DC_LUT_DATA_R_FORMAT_U0P10           = 0x00000000,
5731DCP_DC_LUT_DATA_R_FORMAT_S1P10           = 0x00000001,
5732DCP_DC_LUT_DATA_R_FORMAT_U1P11           = 0x00000002,
5733DCP_DC_LUT_DATA_R_FORMAT_U0P12           = 0x00000003,
5734} DCP_DC_LUT_DATA_R_FORMAT;
5735
5736/*
5737 * DCP_CRC_ENABLE enum
5738 */
5739
5740typedef enum DCP_CRC_ENABLE {
5741DCP_CRC_ENABLE_FALSE                     = 0x00000000,
5742DCP_CRC_ENABLE_TRUE                      = 0x00000001,
5743} DCP_CRC_ENABLE;
5744
5745/*
5746 * DCP_CRC_SOURCE_SEL enum
5747 */
5748
5749typedef enum DCP_CRC_SOURCE_SEL {
5750DCP_CRC_SOURCE_SEL_OUTPUT_PIX            = 0x00000000,
5751DCP_CRC_SOURCE_SEL_INPUT_L32             = 0x00000001,
5752DCP_CRC_SOURCE_SEL_INPUT_H32             = 0x00000002,
5753DCP_CRC_SOURCE_SEL_OUTPUT_CNTL           = 0x00000004,
5754} DCP_CRC_SOURCE_SEL;
5755
5756/*
5757 * DCP_CRC_LINE_SEL enum
5758 */
5759
5760typedef enum DCP_CRC_LINE_SEL {
5761DCP_CRC_LINE_SEL_RESERVED                = 0x00000000,
5762DCP_CRC_LINE_SEL_EVEN                    = 0x00000001,
5763DCP_CRC_LINE_SEL_ODD                     = 0x00000002,
5764DCP_CRC_LINE_SEL_BOTH                    = 0x00000003,
5765} DCP_CRC_LINE_SEL;
5766
5767/*
5768 * DCP_GRPH_FLIP_RATE enum
5769 */
5770
5771typedef enum DCP_GRPH_FLIP_RATE {
5772DCP_GRPH_FLIP_RATE_1FRAME                = 0x00000000,
5773DCP_GRPH_FLIP_RATE_2FRAME                = 0x00000001,
5774DCP_GRPH_FLIP_RATE_3FRAME                = 0x00000002,
5775DCP_GRPH_FLIP_RATE_4FRAME                = 0x00000003,
5776DCP_GRPH_FLIP_RATE_5FRAME                = 0x00000004,
5777DCP_GRPH_FLIP_RATE_6FRAME                = 0x00000005,
5778DCP_GRPH_FLIP_RATE_7FRAME                = 0x00000006,
5779DCP_GRPH_FLIP_RATE_8FRAME                = 0x00000007,
5780} DCP_GRPH_FLIP_RATE;
5781
5782/*
5783 * DCP_GRPH_FLIP_RATE_ENABLE enum
5784 */
5785
5786typedef enum DCP_GRPH_FLIP_RATE_ENABLE {
5787DCP_GRPH_FLIP_RATE_ENABLE_FALSE          = 0x00000000,
5788DCP_GRPH_FLIP_RATE_ENABLE_TRUE           = 0x00000001,
5789} DCP_GRPH_FLIP_RATE_ENABLE;
5790
5791/*
5792 * DCP_GSL0_EN enum
5793 */
5794
5795typedef enum DCP_GSL0_EN {
5796DCP_GSL0_EN_FALSE                        = 0x00000000,
5797DCP_GSL0_EN_TRUE                         = 0x00000001,
5798} DCP_GSL0_EN;
5799
5800/*
5801 * DCP_GSL1_EN enum
5802 */
5803
5804typedef enum DCP_GSL1_EN {
5805DCP_GSL1_EN_FALSE                        = 0x00000000,
5806DCP_GSL1_EN_TRUE                         = 0x00000001,
5807} DCP_GSL1_EN;
5808
5809/*
5810 * DCP_GSL2_EN enum
5811 */
5812
5813typedef enum DCP_GSL2_EN {
5814DCP_GSL2_EN_FALSE                        = 0x00000000,
5815DCP_GSL2_EN_TRUE                         = 0x00000001,
5816} DCP_GSL2_EN;
5817
5818/*
5819 * DCP_GSL_MASTER_EN enum
5820 */
5821
5822typedef enum DCP_GSL_MASTER_EN {
5823DCP_GSL_MASTER_EN_FALSE                  = 0x00000000,
5824DCP_GSL_MASTER_EN_TRUE                   = 0x00000001,
5825} DCP_GSL_MASTER_EN;
5826
5827/*
5828 * DCP_GSL_XDMA_GROUP enum
5829 */
5830
5831typedef enum DCP_GSL_XDMA_GROUP {
5832DCP_GSL_XDMA_GROUP_VSYNC                 = 0x00000000,
5833DCP_GSL_XDMA_GROUP_HSYNC0                = 0x00000001,
5834DCP_GSL_XDMA_GROUP_HSYNC1                = 0x00000002,
5835DCP_GSL_XDMA_GROUP_HSYNC2                = 0x00000003,
5836} DCP_GSL_XDMA_GROUP;
5837
5838/*
5839 * DCP_GSL_XDMA_GROUP_UNDERFLOW_EN enum
5840 */
5841
5842typedef enum DCP_GSL_XDMA_GROUP_UNDERFLOW_EN {
5843DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE    = 0x00000000,
5844DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE     = 0x00000001,
5845} DCP_GSL_XDMA_GROUP_UNDERFLOW_EN;
5846
5847/*
5848 * DCP_GSL_SYNC_SOURCE enum
5849 */
5850
5851typedef enum DCP_GSL_SYNC_SOURCE {
5852DCP_GSL_SYNC_SOURCE_FLIP                 = 0x00000000,
5853DCP_GSL_SYNC_SOURCE_PHASE0               = 0x00000001,
5854DCP_GSL_SYNC_SOURCE_RESET                = 0x00000002,
5855DCP_GSL_SYNC_SOURCE_PHASE1               = 0x00000003,
5856} DCP_GSL_SYNC_SOURCE;
5857
5858/*
5859 * DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC enum
5860 */
5861
5862typedef enum DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC {
5863DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_DIS  = 0x00000000,
5864DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_EN  = 0x00000001,
5865} DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC;
5866
5867/*
5868 * DCP_GSL_DELAY_SURFACE_UPDATE_PENDING enum
5869 */
5870
5871typedef enum DCP_GSL_DELAY_SURFACE_UPDATE_PENDING {
5872DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE  = 0x00000000,
5873DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE  = 0x00000001,
5874} DCP_GSL_DELAY_SURFACE_UPDATE_PENDING;
5875
5876/*
5877 * DCP_TEST_DEBUG_WRITE_EN enum
5878 */
5879
5880typedef enum DCP_TEST_DEBUG_WRITE_EN {
5881DCP_TEST_DEBUG_WRITE_EN_FALSE            = 0x00000000,
5882DCP_TEST_DEBUG_WRITE_EN_TRUE             = 0x00000001,
5883} DCP_TEST_DEBUG_WRITE_EN;
5884
5885/*
5886 * DCP_GRPH_STEREOSYNC_FLIP_EN enum
5887 */
5888
5889typedef enum DCP_GRPH_STEREOSYNC_FLIP_EN {
5890DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE        = 0x00000000,
5891DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE         = 0x00000001,
5892} DCP_GRPH_STEREOSYNC_FLIP_EN;
5893
5894/*
5895 * DCP_GRPH_STEREOSYNC_FLIP_MODE enum
5896 */
5897
5898typedef enum DCP_GRPH_STEREOSYNC_FLIP_MODE {
5899DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP       = 0x00000000,
5900DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0     = 0x00000001,
5901DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET      = 0x00000002,
5902DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1     = 0x00000003,
5903} DCP_GRPH_STEREOSYNC_FLIP_MODE;
5904
5905/*
5906 * DCP_GRPH_STEREOSYNC_SELECT_DISABLE enum
5907 */
5908
5909typedef enum DCP_GRPH_STEREOSYNC_SELECT_DISABLE {
5910DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE  = 0x00000000,
5911DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE  = 0x00000001,
5912} DCP_GRPH_STEREOSYNC_SELECT_DISABLE;
5913
5914/*
5915 * DCP_GRPH_ROTATION_ANGLE enum
5916 */
5917
5918typedef enum DCP_GRPH_ROTATION_ANGLE {
5919DCP_GRPH_ROTATION_ANGLE_0                = 0x00000000,
5920DCP_GRPH_ROTATION_ANGLE_90               = 0x00000001,
5921DCP_GRPH_ROTATION_ANGLE_180              = 0x00000002,
5922DCP_GRPH_ROTATION_ANGLE_270              = 0x00000003,
5923} DCP_GRPH_ROTATION_ANGLE;
5924
5925/*
5926 * DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN enum
5927 */
5928
5929typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN {
5930DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE  = 0x00000000,
5931DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE  = 0x00000001,
5932} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN;
5933
5934/*
5935 * DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE enum
5936 */
5937
5938typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE {
5939DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM  = 0x00000000,
5940DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE  = 0x00000001,
5941} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE;
5942
5943/*
5944 * DCP_GRPH_REGAMMA_MODE enum
5945 */
5946
5947typedef enum DCP_GRPH_REGAMMA_MODE {
5948DCP_GRPH_REGAMMA_MODE_BYPASS             = 0x00000000,
5949DCP_GRPH_REGAMMA_MODE_SRGB               = 0x00000001,
5950DCP_GRPH_REGAMMA_MODE_XVYCC              = 0x00000002,
5951DCP_GRPH_REGAMMA_MODE_PROGA              = 0x00000003,
5952DCP_GRPH_REGAMMA_MODE_PROGB              = 0x00000004,
5953} DCP_GRPH_REGAMMA_MODE;
5954
5955/*
5956 * DCP_ALPHA_ROUND_TRUNC_MODE enum
5957 */
5958
5959typedef enum DCP_ALPHA_ROUND_TRUNC_MODE {
5960DCP_ALPHA_ROUND_TRUNC_MODE_ROUND         = 0x00000000,
5961DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC         = 0x00000001,
5962} DCP_ALPHA_ROUND_TRUNC_MODE;
5963
5964/*
5965 * DCP_CURSOR_ALPHA_BLND_ENA enum
5966 */
5967
5968typedef enum DCP_CURSOR_ALPHA_BLND_ENA {
5969DCP_CURSOR_ALPHA_BLND_ENA_FALSE          = 0x00000000,
5970DCP_CURSOR_ALPHA_BLND_ENA_TRUE           = 0x00000001,
5971} DCP_CURSOR_ALPHA_BLND_ENA;
5972
5973/*
5974 * DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK enum
5975 */
5976
5977typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK {
5978DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE  = 0x00000000,
5979DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE  = 0x00000001,
5980} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK;
5981
5982/*
5983 * DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK enum
5984 */
5985
5986typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK {
5987DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE = 0x00000000,
5988DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE  = 0x00000001,
5989} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK;
5990
5991/*
5992 * DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK enum
5993 */
5994
5995typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK {
5996DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE  = 0x00000000,
5997DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE  = 0x00000001,
5998} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK;
5999
6000/*

6001 * DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK enum
6002 */
6003
6004typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK {
6005DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE = 0x00000000,
6006DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE  = 0x00000001,
6007} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK;
6008
6009/*
6010 * DCP_GRPH_SURFACE_COUNTER_EN enum
6011 */
6012
6013typedef enum DCP_GRPH_SURFACE_COUNTER_EN {
6014DCP_GRPH_SURFACE_COUNTER_EN_DISABLE      = 0x00000000,
6015DCP_GRPH_SURFACE_COUNTER_EN_ENABLE       = 0x00000001,
6016} DCP_GRPH_SURFACE_COUNTER_EN;
6017
6018/*
6019 * DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT enum
6020 */
6021
6022typedef enum DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT {
6023DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0  = 0x00000000,
6024DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1  = 0x00000001,
6025DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2  = 0x00000002,
6026DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3  = 0x00000003,
6027DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4  = 0x00000004,
6028DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5  = 0x00000005,
6029DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6  = 0x00000006,
6030DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7  = 0x00000007,
6031DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8  = 0x00000008,
6032DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9  = 0x00000009,
6033DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10  = 0x0000000a,
6034DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11  = 0x0000000b,
6035} DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT;
6036
6037/*
6038 * DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED enum
6039 */
6040
6041typedef enum DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED {
6042DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO  = 0x00000000,
6043DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES  = 0x00000001,
6044} DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED;
6045
6046/*
6047 * DCP_GRPH_XDMA_FLIP_TYPE_CLEAR enum
6048 */
6049
6050typedef enum DCP_GRPH_XDMA_FLIP_TYPE_CLEAR {
6051DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_DISABLE    = 0x00000000,
6052DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_ENABLE     = 0x00000001,
6053} DCP_GRPH_XDMA_FLIP_TYPE_CLEAR;
6054
6055/*
6056 * DCP_GRPH_XDMA_DRR_MODE_ENABLE enum
6057 */
6058
6059typedef enum DCP_GRPH_XDMA_DRR_MODE_ENABLE {
6060DCP_GRPH_XDMA_DRR_MODE_ENABLE_DISABLE    = 0x00000000,
6061DCP_GRPH_XDMA_DRR_MODE_ENABLE_ENABLE     = 0x00000001,
6062} DCP_GRPH_XDMA_DRR_MODE_ENABLE;
6063
6064/*
6065 * DCP_GRPH_XDMA_MULTIFLIP_ENABLE enum
6066 */
6067
6068typedef enum DCP_GRPH_XDMA_MULTIFLIP_ENABLE {
6069DCP_GRPH_XDMA_MULTIFLIP_ENABLE_DISABLE   = 0x00000000,
6070DCP_GRPH_XDMA_MULTIFLIP_ENABLE_ENABLE    = 0x00000001,
6071} DCP_GRPH_XDMA_MULTIFLIP_ENABLE;
6072
6073/*
6074 * DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK enum
6075 */
6076
6077typedef enum DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK {
6078DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_FALSE    = 0x00000000,
6079DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_TRUE     = 0x00000001,
6080} DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK;
6081
6082/*
6083 * DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK enum
6084 */
6085
6086typedef enum DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK {
6087DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_FALSE     = 0x00000000,
6088DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_TRUE      = 0x00000001,
6089} DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK;
6090
6091/*******************************************************
6092 * DC_PERFMON Enums
6093 *******************************************************/
6094
6095/*
6096 * PERFCOUNTER_CVALUE_SEL enum
6097 */
6098
6099typedef enum PERFCOUNTER_CVALUE_SEL {
6100PERFCOUNTER_CVALUE_SEL_47_0              = 0x00000000,
6101PERFCOUNTER_CVALUE_SEL_15_0              = 0x00000001,
6102PERFCOUNTER_CVALUE_SEL_31_16             = 0x00000002,
6103PERFCOUNTER_CVALUE_SEL_47_32             = 0x00000003,
6104PERFCOUNTER_CVALUE_SEL_11_0              = 0x00000004,
6105PERFCOUNTER_CVALUE_SEL_23_12             = 0x00000005,
6106PERFCOUNTER_CVALUE_SEL_35_24             = 0x00000006,
6107PERFCOUNTER_CVALUE_SEL_47_36             = 0x00000007,
6108} PERFCOUNTER_CVALUE_SEL;
6109
6110/*
6111 * PERFCOUNTER_INC_MODE enum
6112 */
6113
6114typedef enum PERFCOUNTER_INC_MODE {
6115PERFCOUNTER_INC_MODE_MULTI_BIT           = 0x00000000,
6116PERFCOUNTER_INC_MODE_BOTH_EDGE           = 0x00000001,
6117PERFCOUNTER_INC_MODE_LSB                 = 0x00000002,
6118PERFCOUNTER_INC_MODE_POS_EDGE            = 0x00000003,
6119PERFCOUNTER_INC_MODE_NEG_EDGE            = 0x00000004,
6120} PERFCOUNTER_INC_MODE;
6121
6122/*
6123 * PERFCOUNTER_HW_CNTL_SEL enum
6124 */
6125
6126typedef enum PERFCOUNTER_HW_CNTL_SEL {
6127PERFCOUNTER_HW_CNTL_SEL_RUNEN            = 0x00000000,
6128PERFCOUNTER_HW_CNTL_SEL_CNTOFF           = 0x00000001,
6129} PERFCOUNTER_HW_CNTL_SEL;
6130
6131/*
6132 * PERFCOUNTER_RUNEN_MODE enum
6133 */
6134
6135typedef enum PERFCOUNTER_RUNEN_MODE {
6136PERFCOUNTER_RUNEN_MODE_LEVEL             = 0x00000000,
6137PERFCOUNTER_RUNEN_MODE_EDGE              = 0x00000001,
6138} PERFCOUNTER_RUNEN_MODE;
6139
6140/*
6141 * PERFCOUNTER_CNTOFF_START_DIS enum
6142 */
6143
6144typedef enum PERFCOUNTER_CNTOFF_START_DIS {
6145PERFCOUNTER_CNTOFF_START_ENABLE          = 0x00000000,
6146PERFCOUNTER_CNTOFF_START_DISABLE         = 0x00000001,
6147} PERFCOUNTER_CNTOFF_START_DIS;
6148
6149/*
6150 * PERFCOUNTER_RESTART_EN enum
6151 */
6152
6153typedef enum PERFCOUNTER_RESTART_EN {
6154PERFCOUNTER_RESTART_DISABLE              = 0x00000000,
6155PERFCOUNTER_RESTART_ENABLE               = 0x00000001,
6156} PERFCOUNTER_RESTART_EN;
6157
6158/*
6159 * PERFCOUNTER_INT_EN enum
6160 */
6161
6162typedef enum PERFCOUNTER_INT_EN {
6163PERFCOUNTER_INT_DISABLE                  = 0x00000000,
6164PERFCOUNTER_INT_ENABLE                   = 0x00000001,
6165} PERFCOUNTER_INT_EN;
6166
6167/*
6168 * PERFCOUNTER_OFF_MASK enum
6169 */
6170
6171typedef enum PERFCOUNTER_OFF_MASK {
6172PERFCOUNTER_OFF_MASK_DISABLE             = 0x00000000,
6173PERFCOUNTER_OFF_MASK_ENABLE              = 0x00000001,
6174} PERFCOUNTER_OFF_MASK;
6175
6176/*
6177 * PERFCOUNTER_ACTIVE enum
6178 */
6179
6180typedef enum PERFCOUNTER_ACTIVE {
6181PERFCOUNTER_IS_IDLE                      = 0x00000000,
6182PERFCOUNTER_IS_ACTIVE                    = 0x00000001,
6183} PERFCOUNTER_ACTIVE;
6184
6185/*
6186 * PERFCOUNTER_INT_TYPE enum
6187 */
6188
6189typedef enum PERFCOUNTER_INT_TYPE {
6190PERFCOUNTER_INT_TYPE_LEVEL               = 0x00000000,
6191PERFCOUNTER_INT_TYPE_PULSE               = 0x00000001,
6192} PERFCOUNTER_INT_TYPE;
6193
6194/*
6195 * PERFCOUNTER_COUNTED_VALUE_TYPE enum
6196 */
6197
6198typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {
6199PERFCOUNTER_COUNTED_VALUE_TYPE_ACC       = 0x00000000,
6200PERFCOUNTER_COUNTED_VALUE_TYPE_MAX       = 0x00000001,
6201PERFCOUNTER_COUNTED_VALUE_TYPE_MIN       = 0x00000002,
6202} PERFCOUNTER_COUNTED_VALUE_TYPE;
6203
6204/*
6205 * PERFCOUNTER_CNTL_SEL enum
6206 */
6207
6208typedef enum PERFCOUNTER_CNTL_SEL {
6209PERFCOUNTER_CNTL_SEL_0                   = 0x00000000,
6210PERFCOUNTER_CNTL_SEL_1                   = 0x00000001,
6211PERFCOUNTER_CNTL_SEL_2                   = 0x00000002,
6212PERFCOUNTER_CNTL_SEL_3                   = 0x00000003,
6213PERFCOUNTER_CNTL_SEL_4                   = 0x00000004,
6214PERFCOUNTER_CNTL_SEL_5                   = 0x00000005,
6215PERFCOUNTER_CNTL_SEL_6                   = 0x00000006,
6216PERFCOUNTER_CNTL_SEL_7                   = 0x00000007,
6217} PERFCOUNTER_CNTL_SEL;
6218
6219/*
6220 * PERFCOUNTER_CNT0_STATE enum
6221 */
6222
6223typedef enum PERFCOUNTER_CNT0_STATE {
6224PERFCOUNTER_CNT0_STATE_RESET             = 0x00000000,
6225PERFCOUNTER_CNT0_STATE_START             = 0x00000001,
6226PERFCOUNTER_CNT0_STATE_FREEZE            = 0x00000002,
6227PERFCOUNTER_CNT0_STATE_HW                = 0x00000003,
6228} PERFCOUNTER_CNT0_STATE;
6229
6230/*
6231 * PERFCOUNTER_STATE_SEL0 enum
6232 */
6233
6234typedef enum PERFCOUNTER_STATE_SEL0 {
6235PERFCOUNTER_STATE_SEL0_GLOBAL            = 0x00000000,
6236PERFCOUNTER_STATE_SEL0_LOCAL             = 0x00000001,
6237} PERFCOUNTER_STATE_SEL0;
6238
6239/*
6240 * PERFCOUNTER_CNT1_STATE enum
6241 */
6242
6243typedef enum PERFCOUNTER_CNT1_STATE {
6244PERFCOUNTER_CNT1_STATE_RESET             = 0x00000000,
6245PERFCOUNTER_CNT1_STATE_START             = 0x00000001,
6246PERFCOUNTER_CNT1_STATE_FREEZE            = 0x00000002,
6247PERFCOUNTER_CNT1_STATE_HW                = 0x00000003,
6248} PERFCOUNTER_CNT1_STATE;
6249
6250/*
6251 * PERFCOUNTER_STATE_SEL1 enum
6252 */
6253
6254typedef enum PERFCOUNTER_STATE_SEL1 {
6255PERFCOUNTER_STATE_SEL1_GLOBAL            = 0x00000000,
6256PERFCOUNTER_STATE_SEL1_LOCAL             = 0x00000001,
6257} PERFCOUNTER_STATE_SEL1;
6258
6259/*
6260 * PERFCOUNTER_CNT2_STATE enum
6261 */
6262
6263typedef enum PERFCOUNTER_CNT2_STATE {
6264PERFCOUNTER_CNT2_STATE_RESET             = 0x00000000,
6265PERFCOUNTER_CNT2_STATE_START             = 0x00000001,
6266PERFCOUNTER_CNT2_STATE_FREEZE            = 0x00000002,
6267PERFCOUNTER_CNT2_STATE_HW                = 0x00000003,
6268} PERFCOUNTER_CNT2_STATE;
6269
6270/*
6271 * PERFCOUNTER_STATE_SEL2 enum
6272 */
6273
6274typedef enum PERFCOUNTER_STATE_SEL2 {
6275PERFCOUNTER_STATE_SEL2_GLOBAL            = 0x00000000,
6276PERFCOUNTER_STATE_SEL2_LOCAL             = 0x00000001,
6277} PERFCOUNTER_STATE_SEL2;
6278
6279/*
6280 * PERFCOUNTER_CNT3_STATE enum
6281 */
6282
6283typedef enum PERFCOUNTER_CNT3_STATE {
6284PERFCOUNTER_CNT3_STATE_RESET             = 0x00000000,
6285PERFCOUNTER_CNT3_STATE_START             = 0x00000001,
6286PERFCOUNTER_CNT3_STATE_FREEZE            = 0x00000002,
6287PERFCOUNTER_CNT3_STATE_HW                = 0x00000003,
6288} PERFCOUNTER_CNT3_STATE;
6289
6290/*
6291 * PERFCOUNTER_STATE_SEL3 enum
6292 */
6293
6294typedef enum PERFCOUNTER_STATE_SEL3 {
6295PERFCOUNTER_STATE_SEL3_GLOBAL            = 0x00000000,
6296PERFCOUNTER_STATE_SEL3_LOCAL             = 0x00000001,
6297} PERFCOUNTER_STATE_SEL3;
6298
6299/*
6300 * PERFCOUNTER_CNT4_STATE enum
6301 */
6302
6303typedef enum PERFCOUNTER_CNT4_STATE {
6304PERFCOUNTER_CNT4_STATE_RESET             = 0x00000000,
6305PERFCOUNTER_CNT4_STATE_START             = 0x00000001,
6306PERFCOUNTER_CNT4_STATE_FREEZE            = 0x00000002,
6307PERFCOUNTER_CNT4_STATE_HW                = 0x00000003,
6308} PERFCOUNTER_CNT4_STATE;
6309
6310/*
6311 * PERFCOUNTER_STATE_SEL4 enum
6312 */
6313
6314typedef enum PERFCOUNTER_STATE_SEL4 {
6315PERFCOUNTER_STATE_SEL4_GLOBAL            = 0x00000000,
6316PERFCOUNTER_STATE_SEL4_LOCAL             = 0x00000001,
6317} PERFCOUNTER_STATE_SEL4;
6318
6319/*
6320 * PERFCOUNTER_CNT5_STATE enum
6321 */
6322
6323typedef enum PERFCOUNTER_CNT5_STATE {
6324PERFCOUNTER_CNT5_STATE_RESET             = 0x00000000,
6325PERFCOUNTER_CNT5_STATE_START             = 0x00000001,
6326PERFCOUNTER_CNT5_STATE_FREEZE            = 0x00000002,
6327PERFCOUNTER_CNT5_STATE_HW                = 0x00000003,
6328} PERFCOUNTER_CNT5_STATE;
6329
6330/*
6331 * PERFCOUNTER_STATE_SEL5 enum
6332 */
6333
6334typedef enum PERFCOUNTER_STATE_SEL5 {
6335PERFCOUNTER_STATE_SEL5_GLOBAL            = 0x00000000,
6336PERFCOUNTER_STATE_SEL5_LOCAL             = 0x00000001,
6337} PERFCOUNTER_STATE_SEL5;
6338
6339/*
6340 * PERFCOUNTER_CNT6_STATE enum
6341 */
6342
6343typedef enum PERFCOUNTER_CNT6_STATE {
6344PERFCOUNTER_CNT6_STATE_RESET             = 0x00000000,
6345PERFCOUNTER_CNT6_STATE_START             = 0x00000001,
6346PERFCOUNTER_CNT6_STATE_FREEZE            = 0x00000002,
6347PERFCOUNTER_CNT6_STATE_HW                = 0x00000003,
6348} PERFCOUNTER_CNT6_STATE;
6349
6350/*
6351 * PERFCOUNTER_STATE_SEL6 enum
6352 */
6353
6354typedef enum PERFCOUNTER_STATE_SEL6 {
6355PERFCOUNTER_STATE_SEL6_GLOBAL            = 0x00000000,
6356PERFCOUNTER_STATE_SEL6_LOCAL             = 0x00000001,
6357} PERFCOUNTER_STATE_SEL6;
6358
6359/*
6360 * PERFCOUNTER_CNT7_STATE enum
6361 */
6362
6363typedef enum PERFCOUNTER_CNT7_STATE {
6364PERFCOUNTER_CNT7_STATE_RESET             = 0x00000000,
6365PERFCOUNTER_CNT7_STATE_START             = 0x00000001,
6366PERFCOUNTER_CNT7_STATE_FREEZE            = 0x00000002,
6367PERFCOUNTER_CNT7_STATE_HW                = 0x00000003,
6368} PERFCOUNTER_CNT7_STATE;
6369
6370/*
6371 * PERFCOUNTER_STATE_SEL7 enum
6372 */
6373
6374typedef enum PERFCOUNTER_STATE_SEL7 {
6375PERFCOUNTER_STATE_SEL7_GLOBAL            = 0x00000000,
6376PERFCOUNTER_STATE_SEL7_LOCAL             = 0x00000001,
6377} PERFCOUNTER_STATE_SEL7;
6378
6379/*
6380 * PERFMON_STATE enum
6381 */
6382
6383typedef enum PERFMON_STATE {
6384PERFMON_STATE_RESET                      = 0x00000000,
6385PERFMON_STATE_START                      = 0x00000001,
6386PERFMON_STATE_FREEZE                     = 0x00000002,
6387PERFMON_STATE_HW                         = 0x00000003,
6388} PERFMON_STATE;
6389
6390/*
6391 * PERFMON_CNTOFF_AND_OR enum
6392 */
6393
6394typedef enum PERFMON_CNTOFF_AND_OR {
6395PERFMON_CNTOFF_OR                        = 0x00000000,
6396PERFMON_CNTOFF_AND                       = 0x00000001,
6397} PERFMON_CNTOFF_AND_OR;
6398
6399/*
6400 * PERFMON_CNTOFF_INT_EN enum
6401 */
6402
6403typedef enum PERFMON_CNTOFF_INT_EN {
6404PERFMON_CNTOFF_INT_DISABLE               = 0x00000000,
6405PERFMON_CNTOFF_INT_ENABLE                = 0x00000001,
6406} PERFMON_CNTOFF_INT_EN;
6407
6408/*
6409 * PERFMON_CNTOFF_INT_TYPE enum
6410 */
6411
6412typedef enum PERFMON_CNTOFF_INT_TYPE {
6413PERFMON_CNTOFF_INT_TYPE_LEVEL            = 0x00000000,
6414PERFMON_CNTOFF_INT_TYPE_PULSE            = 0x00000001,
6415} PERFMON_CNTOFF_INT_TYPE;
6416
6417/*******************************************************
6418 * SCL Enums
6419 *******************************************************/
6420
6421/*
6422 * SCL_C_RAM_TAP_PAIR_IDX enum
6423 */
6424
6425typedef enum SCL_C_RAM_TAP_PAIR_IDX {
6426SCL_C_RAM_TAP_PAIR_ID0                   = 0x00000000,
6427SCL_C_RAM_TAP_PAIR_ID1                   = 0x00000001,
6428SCL_C_RAM_TAP_PAIR_ID2                   = 0x00000002,
6429SCL_C_RAM_TAP_PAIR_ID3                   = 0x00000003,
6430SCL_C_RAM_TAP_PAIR_ID4                   = 0x00000004,
6431} SCL_C_RAM_TAP_PAIR_IDX;
6432
6433/*
6434 * SCL_C_RAM_PHASE enum
6435 */
6436
6437typedef enum SCL_C_RAM_PHASE {
6438SCL_C_RAM_PHASE_0                        = 0x00000000,
6439SCL_C_RAM_PHASE_1                        = 0x00000001,
6440SCL_C_RAM_PHASE_2                        = 0x00000002,
6441SCL_C_RAM_PHASE_3                        = 0x00000003,
6442SCL_C_RAM_PHASE_4                        = 0x00000004,
6443SCL_C_RAM_PHASE_5                        = 0x00000005,
6444SCL_C_RAM_PHASE_6                        = 0x00000006,
6445SCL_C_RAM_PHASE_7                        = 0x00000007,
6446SCL_C_RAM_PHASE_8                        = 0x00000008,
6447} SCL_C_RAM_PHASE;
6448
6449/*
6450 * SCL_C_RAM_FILTER_TYPE enum
6451 */
6452
6453typedef enum SCL_C_RAM_FILTER_TYPE {
6454SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT  = 0x00000000,
6455SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT    = 0x00000001,
6456SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT  = 0x00000002,
6457SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT    = 0x00000003,
6458} SCL_C_RAM_FILTER_TYPE;
6459
6460/*
6461 * SCL_MODE_SEL enum
6462 */
6463
6464typedef enum SCL_MODE_SEL {
6465SCL_MODE_RGB_BYPASS                      = 0x00000000,
6466SCL_MODE_RGB_SCALING                     = 0x00000001,
6467SCL_MODE_YCBCR_SCALING                   = 0x00000002,
6468SCL_MODE_YCBCR_BYPASS                    = 0x00000003,
6469} SCL_MODE_SEL;
6470
6471/*
6472 * SCL_PSCL_EN enum
6473 */
6474
6475typedef enum SCL_PSCL_EN {
6476SCL_PSCL_DISABLE                         = 0x00000000,
6477SCL_PSCL_ENANBLE                         = 0x00000001,
6478} SCL_PSCL_EN;
6479
6480/*
6481 * SCL_V_NUM_OF_TAPS enum
6482 */
6483
6484typedef enum SCL_V_NUM_OF_TAPS {
6485SCL_V_NUM_OF_TAPS_1                      = 0x00000000,
6486SCL_V_NUM_OF_TAPS_2                      = 0x00000001,
6487SCL_V_NUM_OF_TAPS_3                      = 0x00000002,
6488SCL_V_NUM_OF_TAPS_4                      = 0x00000003,
6489SCL_V_NUM_OF_TAPS_5                      = 0x00000004,
6490SCL_V_NUM_OF_TAPS_6                      = 0x00000005,
6491} SCL_V_NUM_OF_TAPS;
6492
6493/*
6494 * SCL_H_NUM_OF_TAPS enum
6495 */
6496
6497typedef enum SCL_H_NUM_OF_TAPS {
6498SCL_H_NUM_OF_TAPS_1                      = 0x00000000,
6499SCL_H_NUM_OF_TAPS_2                      = 0x00000001,
6500SCL_H_NUM_OF_TAPS_4                      = 0x00000003,
6501SCL_H_NUM_OF_TAPS_6                      = 0x00000005,
6502SCL_H_NUM_OF_TAPS_8                      = 0x00000007,
6503SCL_H_NUM_OF_TAPS_10                     = 0x00000009,
6504} SCL_H_NUM_OF_TAPS;
6505
6506/*
6507 * SCL_BOUNDARY_MODE enum
6508 */
6509
6510typedef enum SCL_BOUNDARY_MODE {
6511SCL_BOUNDARY_MODE_BLACK                  = 0x00000000,
6512SCL_BOUNDARY_MODE_EDGE                   = 0x00000001,
6513} SCL_BOUNDARY_MODE;
6514
6515/*
6516 * SCL_EARLY_EOL_MOD enum
6517 */
6518
6519typedef enum SCL_EARLY_EOL_MOD {
6520SCL_EARLY_EOL_MODE_CRTC                  = 0x00000000,
6521SCL_EARLY_EOL_MODE_INTERNAL              = 0x00000001,
6522} SCL_EARLY_EOL_MOD;
6523
6524/*
6525 * SCL_BYPASS_MODE enum
6526 */
6527
6528typedef enum SCL_BYPASS_MODE {
6529SCL_BYPASS_MODE_MC_MR                    = 0x00000000,
6530SCL_BYPASS_MODE_AC_NR                    = 0x00000001,
6531SCL_BYPASS_MODE_AC_AR                    = 0x00000002,
6532SCL_BYPASS_MODE_RESERVED                 = 0x00000003,
6533} SCL_BYPASS_MODE;
6534
6535/*
6536 * SCL_V_MANUAL_REPLICATE_FACTOR enum
6537 */
6538
6539typedef enum SCL_V_MANUAL_REPLICATE_FACTOR {
6540SCL_V_MANUAL_REPLICATE_FACTOR_1          = 0x00000000,
6541SCL_V_MANUAL_REPLICATE_FACTOR_2          = 0x00000001,
6542SCL_V_MANUAL_REPLICATE_FACTOR_3          = 0x00000002,
6543SCL_V_MANUAL_REPLICATE_FACTOR_4          = 0x00000003,
6544SCL_V_MANUAL_REPLICATE_FACTOR_5          = 0x00000004,
6545SCL_V_MANUAL_REPLICATE_FACTOR_6          = 0x00000005,
6546SCL_V_MANUAL_REPLICATE_FACTOR_7          = 0x00000006,
6547SCL_V_MANUAL_REPLICATE_FACTOR_8          = 0x00000007,
6548SCL_V_MANUAL_REPLICATE_FACTOR_9          = 0x00000008,
6549SCL_V_MANUAL_REPLICATE_FACTOR_10         = 0x00000009,
6550SCL_V_MANUAL_REPLICATE_FACTOR_11         = 0x0000000a,
6551SCL_V_MANUAL_REPLICATE_FACTOR_12         = 0x0000000b,
6552SCL_V_MANUAL_REPLICATE_FACTOR_13         = 0x0000000c,
6553SCL_V_MANUAL_REPLICATE_FACTOR_14         = 0x0000000d,
6554SCL_V_MANUAL_REPLICATE_FACTOR_15         = 0x0000000e,
6555SCL_V_MANUAL_REPLICATE_FACTOR_16         = 0x0000000f,
6556} SCL_V_MANUAL_REPLICATE_FACTOR;
6557
6558/*
6559 * SCL_H_MANUAL_REPLICATE_FACTOR enum
6560 */
6561
6562typedef enum SCL_H_MANUAL_REPLICATE_FACTOR {
6563SCL_H_MANUAL_REPLICATE_FACTOR_1          = 0x00000000,
6564SCL_H_MANUAL_REPLICATE_FACTOR_2          = 0x00000001,
6565SCL_H_MANUAL_REPLICATE_FACTOR_3          = 0x00000002,
6566SCL_H_MANUAL_REPLICATE_FACTOR_4          = 0x00000003,
6567SCL_H_MANUAL_REPLICATE_FACTOR_5          = 0x00000004,
6568SCL_H_MANUAL_REPLICATE_FACTOR_6          = 0x00000005,
6569SCL_H_MANUAL_REPLICATE_FACTOR_7          = 0x00000006,
6570SCL_H_MANUAL_REPLICATE_FACTOR_8          = 0x00000007,
6571SCL_H_MANUAL_REPLICATE_FACTOR_9          = 0x00000008,
6572SCL_H_MANUAL_REPLICATE_FACTOR_10         = 0x00000009,
6573SCL_H_MANUAL_REPLICATE_FACTOR_11         = 0x0000000a,
6574SCL_H_MANUAL_REPLICATE_FACTOR_12         = 0x0000000b,
6575SCL_H_MANUAL_REPLICATE_FACTOR_13         = 0x0000000c,
6576SCL_H_MANUAL_REPLICATE_FACTOR_14         = 0x0000000d,
6577SCL_H_MANUAL_REPLICATE_FACTOR_15         = 0x0000000e,
6578SCL_H_MANUAL_REPLICATE_FACTOR_16         = 0x0000000f,
6579} SCL_H_MANUAL_REPLICATE_FACTOR;
6580
6581/*
6582 * SCL_V_CALC_AUTO_RATIO_EN enum
6583 */
6584
6585typedef enum SCL_V_CALC_AUTO_RATIO_EN {
6586SCL_V_CALC_AUTO_RATIO_DISABLE            = 0x00000000,
6587SCL_V_CALC_AUTO_RATIO_ENABLE             = 0x00000001,
6588} SCL_V_CALC_AUTO_RATIO_EN;
6589
6590/*
6591 * SCL_H_CALC_AUTO_RATIO_EN enum
6592 */
6593
6594typedef enum SCL_H_CALC_AUTO_RATIO_EN {
6595SCL_H_CALC_AUTO_RATIO_DISABLE            = 0x00000000,
6596SCL_H_CALC_AUTO_RATIO_ENABLE             = 0x00000001,
6597} SCL_H_CALC_AUTO_RATIO_EN;
6598
6599/*
6600 * SCL_H_FILTER_PICK_NEAREST enum
6601 */
6602
6603typedef enum SCL_H_FILTER_PICK_NEAREST {
6604SCL_H_FILTER_PICK_NEAREST_DISABLE        = 0x00000000,
6605SCL_H_FILTER_PICK_NEAREST_ENABLE         = 0x00000001,
6606} SCL_H_FILTER_PICK_NEAREST;
6607
6608/*
6609 * SCL_H_2TAP_HARDCODE_COEF_EN enum
6610 */
6611
6612typedef enum SCL_H_2TAP_HARDCODE_COEF_EN {
6613SCL_H_2TAP_HARDCODE_COEF_DISABLE         = 0x00000000,
6614SCL_H_2TAP_HARDCODE_COEF_ENABLE          = 0x00000001,
6615} SCL_H_2TAP_HARDCODE_COEF_EN;
6616
6617/*
6618 * SCL_V_FILTER_PICK_NEAREST enum
6619 */
6620
6621typedef enum SCL_V_FILTER_PICK_NEAREST {
6622SCL_V_FILTER_PICK_NEAREST_DISABLE        = 0x00000000,
6623SCL_V_FILTER_PICK_NEAREST_ENABLE         = 0x00000001,
6624} SCL_V_FILTER_PICK_NEAREST;
6625
6626/*
6627 * SCL_V_2TAP_HARDCODE_COEF_EN enum
6628 */
6629
6630typedef enum SCL_V_2TAP_HARDCODE_COEF_EN {
6631SCL_V_2TAP_HARDCODE_COEF_DISABLE         = 0x00000000,
6632SCL_V_2TAP_HARDCODE_COEF_ENABLE          = 0x00000001,
6633} SCL_V_2TAP_HARDCODE_COEF_EN;
6634
6635/*
6636 * SCL_UPDATE_TAKEN enum
6637 */
6638
6639typedef enum SCL_UPDATE_TAKEN {
6640SCL_UPDATE_TAKEN_NO                      = 0x00000000,
6641SCL_UPDATE_TAKEN_YES                     = 0x00000001,
6642} SCL_UPDATE_TAKEN;
6643
6644/*
6645 * SCL_UPDATE_LOCK enum
6646 */
6647
6648typedef enum SCL_UPDATE_LOCK {
6649SCL_UPDATE_UNLOCKED                      = 0x00000000,
6650SCL_UPDATE_LOCKED                        = 0x00000001,
6651} SCL_UPDATE_LOCK;
6652
6653/*
6654 * SCL_COEF_UPDATE_COMPLETE enum
6655 */
6656
6657typedef enum SCL_COEF_UPDATE_COMPLETE {
6658SCL_COEF_UPDATE_NOT_COMPLETED            = 0x00000000,
6659SCL_COEF_UPDATE_COMPLETED                = 0x00000001,
6660} SCL_COEF_UPDATE_COMPLETE;
6661
6662/*
6663 * SCL_HF_SHARP_SCALE_FACTOR enum
6664 */
6665
6666typedef enum SCL_HF_SHARP_SCALE_FACTOR {
6667SCL_HF_SHARP_SCALE_FACTOR_0              = 0x00000000,
6668SCL_HF_SHARP_SCALE_FACTOR_1              = 0x00000001,
6669SCL_HF_SHARP_SCALE_FACTOR_2              = 0x00000002,
6670SCL_HF_SHARP_SCALE_FACTOR_3              = 0x00000003,
6671SCL_HF_SHARP_SCALE_FACTOR_4              = 0x00000004,
6672SCL_HF_SHARP_SCALE_FACTOR_5              = 0x00000005,
6673SCL_HF_SHARP_SCALE_FACTOR_6              = 0x00000006,
6674SCL_HF_SHARP_SCALE_FACTOR_7              = 0x00000007,
6675} SCL_HF_SHARP_SCALE_FACTOR;
6676
6677/*
6678 * SCL_HF_SHARP_EN enum
6679 */
6680
6681typedef enum SCL_HF_SHARP_EN {
6682SCL_HF_SHARP_DISABLE                     = 0x00000000,
6683SCL_HF_SHARP_ENABLE                      = 0x00000001,
6684} SCL_HF_SHARP_EN;
6685
6686/*
6687 * SCL_VF_SHARP_SCALE_FACTOR enum
6688 */
6689
6690typedef enum SCL_VF_SHARP_SCALE_FACTOR {
6691SCL_VF_SHARP_SCALE_FACTOR_0              = 0x00000000,
6692SCL_VF_SHARP_SCALE_FACTOR_1              = 0x00000001,
6693SCL_VF_SHARP_SCALE_FACTOR_2              = 0x00000002,
6694SCL_VF_SHARP_SCALE_FACTOR_3              = 0x00000003,
6695SCL_VF_SHARP_SCALE_FACTOR_4              = 0x00000004,
6696SCL_VF_SHARP_SCALE_FACTOR_5              = 0x00000005,
6697SCL_VF_SHARP_SCALE_FACTOR_6              = 0x00000006,
6698SCL_VF_SHARP_SCALE_FACTOR_7              = 0x00000007,
6699} SCL_VF_SHARP_SCALE_FACTOR;
6700
6701/*
6702 * SCL_VF_SHARP_EN enum
6703 */
6704
6705typedef enum SCL_VF_SHARP_EN {
6706SCL_VF_SHARP_DISABLE                     = 0x00000000,
6707SCL_VF_SHARP_ENABLE                      = 0x00000001,
6708} SCL_VF_SHARP_EN;
6709
6710/*
6711 * SCL_ALU_DISABLE enum
6712 */
6713
6714typedef enum SCL_ALU_DISABLE {
6715SCL_ALU_ENABLED                          = 0x00000000,
6716SCL_ALU_DISABLED                         = 0x00000001,
6717} SCL_ALU_DISABLE;
6718
6719/*
6720 * SCL_HOST_CONFLICT_MASK enum
6721 */
6722
6723typedef enum SCL_HOST_CONFLICT_MASK {
6724SCL_HOST_CONFLICT_DISABLE_INTERRUPT      = 0x00000000,
6725SCL_HOST_CONFLICT_ENABLE_INTERRUPT       = 0x00000001,
6726} SCL_HOST_CONFLICT_MASK;
6727
6728/*
6729 * SCL_SCL_MODE_CHANGE_MASK enum
6730 */
6731
6732typedef enum SCL_SCL_MODE_CHANGE_MASK {
6733SCL_MODE_CHANGE_DISABLE_INTERRUPT        = 0x00000000,
6734SCL_MODE_CHANGE_ENABLE_INTERRUPT         = 0x00000001,
6735} SCL_SCL_MODE_CHANGE_MASK;
6736
6737/*******************************************************
6738 * SCLV Enums
6739 *******************************************************/
6740
6741/*
6742 * SCLV_MODE_SEL enum
6743 */
6744
6745typedef enum SCLV_MODE_SEL {
6746SCLV_MODE_RGB_BYPASS                     = 0x00000000,
6747SCLV_MODE_RGB_SCALING                    = 0x00000001,
6748SCLV_MODE_YCBCR_SCALING                  = 0x00000002,
6749SCLV_MODE_YCBCR_BYPASS                   = 0x00000003,
6750} SCLV_MODE_SEL;
6751
6752/*
6753 * SCLV_INTERLACE_SOURCE enum
6754 */
6755
6756typedef enum SCLV_INTERLACE_SOURCE {
6757INTERLACE_SOURCE_PROGRESSIVE             = 0x00000000,
6758INTERLACE_SOURCE_INTERLEAVE              = 0x00000001,
6759INTERLACE_SOURCE_STACK                   = 0x00000002,
6760} SCLV_INTERLACE_SOURCE;
6761
6762/*
6763 * SCLV_UPDATE_LOCK enum
6764 */
6765
6766typedef enum SCLV_UPDATE_LOCK {
6767UPDATE_UNLOCKED                          = 0x00000000,
6768UPDATE_LOCKED                            = 0x00000001,
6769} SCLV_UPDATE_LOCK;
6770
6771/*
6772 * SCLV_COEF_UPDATE_COMPLETE enum
6773 */
6774
6775typedef enum SCLV_COEF_UPDATE_COMPLETE {
6776COEF_UPDATE_NOT_COMPLETE                 = 0x00000000,
6777COEF_UPDATE_COMPLETE                     = 0x00000001,
6778} SCLV_COEF_UPDATE_COMPLETE;
6779
6780/*******************************************************
6781 * DPRX_SD Enums
6782 *******************************************************/
6783
6784/*
6785 * DPRX_SD_PIXEL_ENCODING enum
6786 */
6787
6788typedef enum DPRX_SD_PIXEL_ENCODING {
6789PIXEL_FORMAT_RGB_444                     = 0x00000000,
6790PIXEL_FORMAT_YCBCR_444                   = 0x00000001,
6791PIXEL_FORMAT_YCBCR_422                   = 0x00000002,
6792PIXEL_FORMAT_Y_ONLY                      = 0x00000003,
6793} DPRX_SD_PIXEL_ENCODING;
6794
6795/*
6796 * DPRX_SD_COMPONENT_DEPTH enum
6797 */
6798
6799typedef enum DPRX_SD_COMPONENT_DEPTH {
6800COMPONENT_DEPTH_6BPC                     = 0x00000000,
6801COMPONENT_DEPTH_8BPC                     = 0x00000001,
6802COMPONENT_DEPTH_10BPC                    = 0x00000002,
6803COMPONENT_DEPTH_12BPC                    = 0x00000003,
6804COMPONENT_DEPTH_16BPC                    = 0x00000004,
6805} DPRX_SD_COMPONENT_DEPTH;
6806
6807/*******************************************************
6808 * AZF0STREAM Enums
6809 *******************************************************/
6810
6811/*
6812 * AZ_LATENCY_COUNTER_CONTROL enum
6813 */
6814
6815typedef enum AZ_LATENCY_COUNTER_CONTROL {
6816AZ_LATENCY_COUNTER_NO_RESET              = 0x00000000,
6817AZ_LATENCY_COUNTER_RESET_DONE            = 0x00000001,
6818} AZ_LATENCY_COUNTER_CONTROL;
6819
6820/*******************************************************
6821 * BLND Enums
6822 *******************************************************/
6823
6824/*
6825 * BLND_CONTROL_BLND_MODE enum
6826 */
6827
6828typedef enum BLND_CONTROL_BLND_MODE {
6829BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x00000000,
6830BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY   = 0x00000001,
6831BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x00000002,
6832BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x00000003,
6833} BLND_CONTROL_BLND_MODE;
6834
6835/*
6836 * BLND_CONTROL_BLND_STEREO_TYPE enum
6837 */
6838
6839typedef enum BLND_CONTROL_BLND_STEREO_TYPE {
6840BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO = 0x00000000,
6841BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO = 0x00000001,
6842BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO = 0x00000002,
6843BLND_CONTROL_BLND_STEREO_TYPE_UNUSED     = 0x00000003,
6844} BLND_CONTROL_BLND_STEREO_TYPE;
6845
6846/*
6847 * BLND_CONTROL_BLND_STEREO_POLARITY enum
6848 */
6849
6850typedef enum BLND_CONTROL_BLND_STEREO_POLARITY {
6851BLND_CONTROL_BLND_STEREO_POLARITY_LOW    = 0x00000000,
6852BLND_CONTROL_BLND_STEREO_POLARITY_HIGH   = 0x00000001,
6853} BLND_CONTROL_BLND_STEREO_POLARITY;
6854
6855/*
6856 * BLND_CONTROL_BLND_FEEDTHROUGH_EN enum
6857 */
6858
6859typedef enum BLND_CONTROL_BLND_FEEDTHROUGH_EN {
6860BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE   = 0x00000000,
6861BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE    = 0x00000001,
6862} BLND_CONTROL_BLND_FEEDTHROUGH_EN;
6863
6864/*
6865 * BLND_CONTROL_BLND_ALPHA_MODE enum
6866 */
6867
6868typedef enum BLND_CONTROL_BLND_ALPHA_MODE {
6869BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0x00000000,
6870BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 0x00000001,
6871BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x00000002,
6872BLND_CONTROL_BLND_ALPHA_MODE_UNUSED      = 0x00000003,
6873} BLND_CONTROL_BLND_ALPHA_MODE;
6874
6875/*
6876 * BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY enum
6877 */
6878
6879typedef enum BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY {
6880BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_FALSE  = 0x00000000,
6881BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_TRUE  = 0x00000001,
6882} BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY;
6883
6884/*
6885 * BLND_CONTROL_BLND_MULTIPLIED_MODE enum
6886 */
6887
6888typedef enum BLND_CONTROL_BLND_MULTIPLIED_MODE {
6889BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE  = 0x00000000,
6890BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE   = 0x00000001,
6891} BLND_CONTROL_BLND_MULTIPLIED_MODE;
6892
6893/*
6894 * BLND_SM_CONTROL2_SM_MODE enum
6895 */
6896
6897typedef enum BLND_SM_CONTROL2_SM_MODE {
6898BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE    = 0x00000000,
6899BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x00000002,
6900BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x00000004,
6901BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING = 0x00000006,
6902} BLND_SM_CONTROL2_SM_MODE;
6903
6904/*
6905 * BLND_SM_CONTROL2_SM_FRAME_ALTERNATE enum
6906 */
6907
6908typedef enum BLND_SM_CONTROL2_SM_FRAME_ALTERNATE {
6909BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x00000000,
6910BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x00000001,
6911} BLND_SM_CONTROL2_SM_FRAME_ALTERNATE;
6912
6913/*
6914 * BLND_SM_CONTROL2_SM_FIELD_ALTERNATE enum
6915 */
6916
6917typedef enum BLND_SM_CONTROL2_SM_FIELD_ALTERNATE {
6918BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x00000000,
6919BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x00000001,
6920} BLND_SM_CONTROL2_SM_FIELD_ALTERNATE;
6921
6922/*
6923 * BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL enum
6924 */
6925
6926typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
6927BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0x00000000,
6928BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED = 0x00000001,
6929BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 0x00000002,
6930BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 0x00000003,
6931} BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;
6932
6933/*
6934 * BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL enum
6935 */
6936
6937typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
6938BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x00000000,
6939BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x00000001,
6940BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x00000002,
6941BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 0x00000003,
6942} BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;
6943
6944/*
6945 * BLND_CONTROL2_PTI_ENABLE enum
6946 */
6947
6948typedef enum BLND_CONTROL2_PTI_ENABLE {
6949BLND_CONTROL2_PTI_ENABLE_FALSE           = 0x00000000,
6950BLND_CONTROL2_PTI_ENABLE_TRUE            = 0x00000001,
6951} BLND_CONTROL2_PTI_ENABLE;
6952
6953/*
6954 * BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN enum
6955 */
6956
6957typedef enum BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
6958BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x00000000,
6959BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x00000001,
6960} BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;
6961
6962/*
6963 * BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN enum
6964 */
6965
6966typedef enum BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
6967BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x00000000,
6968BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x00000001,
6969} BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN;
6970
6971/*
6972 * BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK enum
6973 */
6974
6975typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
6976BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE = 0x00000000,
6977BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE = 0x00000001,
6978} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;
6979
6980/*
6981 * BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK enum
6982 */
6983
6984typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
6985BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE = 0x00000000,
6986BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE = 0x00000001,
6987} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;
6988
6989/*
6990 * BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK enum
6991 */
6992
6993typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
6994BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE = 0x00000000,
6995BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE = 0x00000001,
6996} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;
6997
6998/*
6999 * BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK enum
7000 */

7001
7002typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
7003BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE = 0x00000000,
7004BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE = 0x00000001,
7005} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;
7006
7007/*
7008 * BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK enum
7009 */
7010
7011typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
7012BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE = 0x00000000,
7013BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE = 0x00000001,
7014} BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;
7015
7016/*
7017 * BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK enum
7018 */
7019
7020typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
7021BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE = 0x00000000,
7022BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE = 0x00000001,
7023} BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;
7024
7025/*
7026 * BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK enum
7027 */
7028
7029typedef enum BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
7030BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x00000000,
7031BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x00000001,
7032} BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;
7033
7034/*
7035 * BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK enum
7036 */
7037
7038typedef enum BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
7039BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0x00000000,
7040BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x00000001,
7041} BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;
7042
7043/*
7044 * BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE enum
7045 */
7046
7047typedef enum BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
7048BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0x00000000,
7049BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x00000001,
7050} BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;
7051
7052/*
7053 * BLND_DEBUG_BLND_CNV_MUX_SELECT enum
7054 */
7055
7056typedef enum BLND_DEBUG_BLND_CNV_MUX_SELECT {
7057BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW       = 0x00000000,
7058BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH      = 0x00000001,
7059} BLND_DEBUG_BLND_CNV_MUX_SELECT;
7060
7061/*
7062 * BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN enum
7063 */
7064
7065typedef enum BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
7066BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
7067BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
7068} BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;
7069
7070/*******************************************************
7071 * AZF0ENDPOINT Enums
7072 *******************************************************/
7073
7074/*
7075 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
7076 */
7077
7078typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
7079AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED  = 0x00000000,
7080AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED  = 0x00000001,
7081AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED  = 0x00000002,
7082AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED  = 0x00000003,
7083AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED  = 0x00000004,
7084AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED  = 0x00000005,
7085AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED  = 0x00000006,
7086AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED  = 0x00000007,
7087AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED  = 0x00000008,
7088AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED  = 0x00000009,
7089} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
7090
7091/*
7092 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
7093 */
7094
7095typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
7096AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY  = 0x00000000,
7097AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY  = 0x00000001,
7098} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
7099
7100/*
7101 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
7102 */
7103
7104typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
7105AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY  = 0x00000000,
7106AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY  = 0x00000001,
7107} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
7108
7109/*
7110 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
7111 */
7112
7113typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
7114AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG  = 0x00000000,
7115AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL  = 0x00000001,
7116} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
7117
7118/*
7119 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
7120 */
7121
7122typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
7123AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST  = 0x00000000,
7124AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST  = 0x00000001,
7125} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
7126
7127/*
7128 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
7129 */
7130
7131typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
7132AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000000,
7133AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000001,
7134} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
7135
7136/*
7137 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
7138 */
7139
7140typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
7141AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES  = 0x00000000,
7142AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES  = 0x00000001,
7143} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
7144
7145/*
7146 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
7147 */
7148
7149typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
7150AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING  = 0x00000000,
7151AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING  = 0x00000001,
7152} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
7153
7154/*
7155 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
7156 */
7157
7158typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
7159AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE  = 0x00000000,
7160AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE  = 0x00000001,
7161} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
7162
7163/*
7164 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
7165 */
7166
7167typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
7168AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER  = 0x00000000,
7169AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE  = 0x00000001,
7170} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
7171
7172/*
7173 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
7174 */
7175
7176typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
7177AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER  = 0x00000000,
7178AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER  = 0x00000001,
7179} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
7180
7181/*
7182 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
7183 */
7184
7185typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
7186AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER  = 0x00000000,
7187AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER  = 0x00000001,
7188} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
7189
7190/*
7191 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
7192 */
7193
7194typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
7195AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC  = 0x00000000,
7196AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO  = 0x00000001,
7197} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
7198
7199/*
7200 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
7201 */
7202
7203typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
7204AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED  = 0x00000000,
7205AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED  = 0x00000001,
7206AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED  = 0x00000002,
7207AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED  = 0x00000003,
7208AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED  = 0x00000004,
7209AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED  = 0x00000005,
7210AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED  = 0x00000006,
7211AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED  = 0x00000007,
7212AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED  = 0x00000008,
7213AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED  = 0x00000009,
7214} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
7215
7216/*
7217 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
7218 */
7219
7220typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
7221AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY  = 0x00000000,
7222AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY  = 0x00000001,
7223} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
7224
7225/*
7226 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
7227 */
7228
7229typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
7230AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY  = 0x00000000,
7231AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY  = 0x00000001,
7232} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
7233
7234/*
7235 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
7236 */
7237
7238typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
7239AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG  = 0x00000000,
7240AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL  = 0x00000001,
7241} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
7242
7243/*
7244 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
7245 */
7246
7247typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
7248AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST  = 0x00000000,
7249AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST  = 0x00000001,
7250} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
7251
7252/*
7253 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
7254 */
7255
7256typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
7257AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000000,
7258AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000001,
7259} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
7260
7261/*
7262 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
7263 */
7264
7265typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
7266AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES  = 0x00000000,
7267AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES  = 0x00000001,
7268} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
7269
7270/*
7271 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
7272 */
7273
7274typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
7275AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING  = 0x00000000,
7276AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING  = 0x00000001,
7277} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
7278
7279/*
7280 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
7281 */
7282
7283typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
7284AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER  = 0x00000000,
7285AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE  = 0x00000001,
7286} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
7287
7288/*
7289 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
7290 */
7291
7292typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
7293AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER  = 0x00000000,
7294AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER  = 0x00000001,
7295} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
7296
7297/*
7298 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
7299 */
7300
7301typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
7302AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT  = 0x00000000,
7303AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER  = 0x00000001,
7304} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
7305
7306/*
7307 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
7308 */
7309
7310typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
7311AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN  = 0x00000000,
7312AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN  = 0x00000001,
7313} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
7314
7315/*
7316 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
7317 */
7318
7319typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
7320AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED  = 0x00000000,
7321AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED  = 0x00000001,
7322} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
7323
7324/*
7325 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
7326 */
7327
7328typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
7329AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN  = 0x00000000,
7330AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN  = 0x00000001,
7331} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
7332
7333/*
7334 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
7335 */
7336
7337typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
7338AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN  = 0x00000000,
7339AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN  = 0x00000001,
7340} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
7341
7342/*
7343 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
7344 */
7345
7346typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
7347AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY  = 0x00000000,
7348AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY  = 0x00000001,
7349} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
7350
7351/*
7352 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
7353 */
7354
7355typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
7356AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY  = 0x00000000,
7357AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY  = 0x00000001,
7358} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
7359
7360/*
7361 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
7362 */
7363
7364typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
7365AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT  = 0x00000000,
7366AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT  = 0x00000001,
7367} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
7368
7369/*
7370 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
7371 */
7372
7373typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
7374AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY  = 0x00000000,
7375AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY  = 0x00000001,
7376} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
7377
7378/*
7379 * AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
7380 */
7381
7382typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
7383AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE  = 0x00000000,
7384AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE  = 0x00000001,
7385} AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
7386
7387/*
7388 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
7389 */
7390
7391typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
7392AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY  = 0x00000000,
7393AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY  = 0x00000001,
7394} AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
7395
7396/*******************************************************
7397 * AZF0INPUTENDPOINT Enums
7398 *******************************************************/
7399
7400/*
7401 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
7402 */
7403
7404typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
7405AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED  = 0x00000000,
7406AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED  = 0x00000001,
7407AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED  = 0x00000002,
7408AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED  = 0x00000003,
7409AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED  = 0x00000004,
7410AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED  = 0x00000005,
7411AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED  = 0x00000006,
7412AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED  = 0x00000007,
7413AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED  = 0x00000008,
7414AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED  = 0x00000009,
7415} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
7416
7417/*
7418 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
7419 */
7420
7421typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
7422AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY  = 0x00000000,
7423AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY  = 0x00000001,
7424} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
7425
7426/*
7427 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
7428 */
7429
7430typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
7431AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY  = 0x00000000,
7432AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY  = 0x00000001,
7433} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
7434
7435/*
7436 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
7437 */
7438
7439typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
7440AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG  = 0x00000000,
7441AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL  = 0x00000001,
7442} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
7443
7444/*
7445 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
7446 */
7447
7448typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
7449AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST  = 0x00000000,
7450AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST  = 0x00000001,
7451} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
7452
7453/*
7454 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
7455 */
7456
7457typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
7458AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000000,
7459AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000001,
7460} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
7461
7462/*
7463 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
7464 */
7465
7466typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
7467AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES  = 0x00000000,
7468AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES  = 0x00000001,
7469} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
7470
7471/*
7472 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
7473 */
7474
7475typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
7476AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING  = 0x00000000,
7477AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING  = 0x00000001,
7478} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
7479
7480/*
7481 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
7482 */
7483
7484typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
7485AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE  = 0x00000000,
7486AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE  = 0x00000001,
7487} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
7488
7489/*
7490 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
7491 */
7492
7493typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
7494AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER  = 0x00000000,
7495AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER  = 0x00000001,
7496} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
7497
7498/*
7499 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
7500 */
7501
7502typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
7503AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER  = 0x00000000,
7504AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER  = 0x00000001,
7505} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
7506
7507/*
7508 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
7509 */
7510
7511typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
7512AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER  = 0x00000000,
7513AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER  = 0x00000001,
7514} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
7515
7516/*
7517 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
7518 */
7519
7520typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
7521AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC  = 0x00000000,
7522AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO  = 0x00000001,
7523} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
7524
7525/*
7526 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
7527 */
7528
7529typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
7530AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED  = 0x00000000,
7531AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED  = 0x00000001,
7532AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED  = 0x00000002,
7533AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED  = 0x00000003,
7534AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED  = 0x00000004,
7535AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED  = 0x00000005,
7536AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED  = 0x00000006,
7537AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED  = 0x00000007,
7538AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED  = 0x00000008,
7539AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED  = 0x00000009,
7540} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
7541
7542/*
7543 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
7544 */
7545
7546typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
7547AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP  = 0x00000000,
7548AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP  = 0x00000001,
7549} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
7550
7551/*
7552 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
7553 */
7554
7555typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
7556AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY  = 0x00000000,
7557AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY  = 0x00000001,
7558} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
7559
7560/*
7561 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
7562 */
7563
7564typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
7565AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG  = 0x00000000,
7566AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL  = 0x00000001,
7567} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
7568
7569/*
7570 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
7571 */
7572
7573typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
7574AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST  = 0x00000000,
7575AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST  = 0x00000001,
7576} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
7577
7578/*
7579 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
7580 */
7581
7582typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
7583AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000000,
7584AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000001,
7585} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
7586
7587/*
7588 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
7589 */
7590
7591typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
7592AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES  = 0x00000000,
7593AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES  = 0x00000001,
7594} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
7595
7596/*
7597 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
7598 */
7599
7600typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
7601AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING  = 0x00000000,
7602AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING  = 0x00000001,
7603} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
7604
7605/*
7606 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
7607 */
7608
7609typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
7610AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER  = 0x00000000,
7611AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE  = 0x00000001,
7612} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
7613
7614/*
7615 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
7616 */
7617
7618typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
7619AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER  = 0x00000000,
7620AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER  = 0x00000001,
7621} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
7622
7623/*
7624 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
7625 */
7626
7627typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
7628AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER  = 0x00000000,
7629AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER  = 0x00000001,
7630} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
7631
7632/*
7633 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP enum
7634 */
7635
7636typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP {
7637AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED  = 0x00000000,
7638AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED  = 0x00000001,
7639} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP;
7640
7641/*
7642 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
7643 */
7644
7645typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
7646AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN  = 0x00000000,
7647AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN  = 0x00000001,
7648} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
7649
7650/*
7651 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI enum
7652 */
7653
7654typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI {
7655AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED  = 0x00000000,
7656AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED  = 0x00000001,
7657} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI;
7658
7659/*
7660 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
7661 */
7662
7663typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
7664AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED  = 0x00000000,
7665AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED  = 0x00000001,
7666} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
7667
7668/*
7669 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
7670 */
7671
7672typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
7673AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN  = 0x00000000,
7674AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN  = 0x00000001,
7675} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
7676
7677/*
7678 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
7679 */
7680
7681typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
7682AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN  = 0x00000000,
7683AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN  = 0x00000001,
7684} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
7685
7686/*
7687 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
7688 */
7689
7690typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
7691AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY  = 0x00000000,
7692AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY  = 0x00000001,
7693} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
7694
7695/*
7696 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
7697 */
7698
7699typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
7700AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY  = 0x00000000,
7701AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY  = 0x00000001,
7702} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
7703
7704/*
7705 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
7706 */
7707
7708typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
7709AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT  = 0x00000000,
7710AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT  = 0x00000001,
7711} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
7712
7713/*
7714 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
7715 */
7716
7717typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
7718AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY  = 0x00000000,
7719AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY  = 0x00000001,
7720} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
7721
7722/*
7723 * AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
7724 */
7725
7726typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
7727AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY  = 0x00000000,
7728AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY  = 0x00000001,
7729} AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
7730
7731/*******************************************************
7732 * UNP Enums
7733 *******************************************************/
7734
7735/*
7736 * UNP_GRPH_EN enum
7737 */
7738
7739typedef enum UNP_GRPH_EN {
7740UNP_GRPH_DISABLED                        = 0x00000000,
7741UNP_GRPH_ENABLED                         = 0x00000001,
7742} UNP_GRPH_EN;
7743
7744/*
7745 * UNP_GRPH_DEPTH enum
7746 */
7747
7748typedef enum UNP_GRPH_DEPTH {
7749UNP_GRPH_8BPP                            = 0x00000000,
7750UNP_GRPH_16BPP                           = 0x00000001,
7751UNP_GRPH_32BPP                           = 0x00000002,
7752} UNP_GRPH_DEPTH;
7753
7754/*
7755 * UNP_GRPH_NUM_BANKS enum
7756 */
7757
7758typedef enum UNP_GRPH_NUM_BANKS {
7759UNP_GRPH_ADDR_SURF_2_BANK                = 0x00000000,
7760UNP_GRPH_ADDR_SURF_4_BANK                = 0x00000001,
7761UNP_GRPH_ADDR_SURF_8_BANK                = 0x00000002,
7762UNP_GRPH_ADDR_SURF_16_BANK               = 0x00000003,
7763} UNP_GRPH_NUM_BANKS;
7764
7765/*
7766 * UNP_GRPH_BANK_WIDTH enum
7767 */
7768
7769typedef enum UNP_GRPH_BANK_WIDTH {
7770UNP_GRPH_ADDR_SURF_BANK_WIDTH_1          = 0x00000000,
7771UNP_GRPH_ADDR_SURF_BANK_WIDTH_2          = 0x00000001,
7772UNP_GRPH_ADDR_SURF_BANK_WIDTH_4          = 0x00000002,
7773UNP_GRPH_ADDR_SURF_BANK_WIDTH_8          = 0x00000003,
7774} UNP_GRPH_BANK_WIDTH;
7775
7776/*
7777 * UNP_GRPH_BANK_HEIGHT enum
7778 */
7779
7780typedef enum UNP_GRPH_BANK_HEIGHT {
7781UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1         = 0x00000000,
7782UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2         = 0x00000001,
7783UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4         = 0x00000002,
7784UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8         = 0x00000003,
7785} UNP_GRPH_BANK_HEIGHT;
7786
7787/*
7788 * UNP_GRPH_TILE_SPLIT enum
7789 */
7790
7791typedef enum UNP_GRPH_TILE_SPLIT {
7792UNP_ADDR_SURF_TILE_SPLIT_64B             = 0x00000000,
7793UNP_ADDR_SURF_TILE_SPLIT_128B            = 0x00000001,
7794UNP_ADDR_SURF_TILE_SPLIT_256B            = 0x00000002,
7795UNP_ADDR_SURF_TILE_SPLIT_512B            = 0x00000003,
7796UNP_ADDR_SURF_TILE_SPLIT_1KB             = 0x00000004,
7797UNP_ADDR_SURF_TILE_SPLIT_2KB             = 0x00000005,
7798UNP_ADDR_SURF_TILE_SPLIT_4KB             = 0x00000006,
7799} UNP_GRPH_TILE_SPLIT;
7800
7801/*
7802 * UNP_GRPH_ADDRESS_TRANSLATION_ENABLE enum
7803 */
7804
7805typedef enum UNP_GRPH_ADDRESS_TRANSLATION_ENABLE {
7806UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0     = 0x00000000,
7807UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1     = 0x00000001,
7808} UNP_GRPH_ADDRESS_TRANSLATION_ENABLE;
7809
7810/*
7811 * UNP_GRPH_MACRO_TILE_ASPECT enum
7812 */
7813
7814typedef enum UNP_GRPH_MACRO_TILE_ASPECT {
7815UNP_ADDR_SURF_MACRO_ASPECT_1             = 0x00000000,
7816UNP_ADDR_SURF_MACRO_ASPECT_2             = 0x00000001,
7817UNP_ADDR_SURF_MACRO_ASPECT_4             = 0x00000002,
7818UNP_ADDR_SURF_MACRO_ASPECT_8             = 0x00000003,
7819} UNP_GRPH_MACRO_TILE_ASPECT;
7820
7821/*
7822 * UNP_GRPH_COLOR_EXPANSION_MODE enum
7823 */
7824
7825typedef enum UNP_GRPH_COLOR_EXPANSION_MODE {
7826UNP_GRPH_DYNAMIC_EXPANSION               = 0x00000000,
7827UNP_GRPH_ZERO_EXPANSION                  = 0x00000001,
7828} UNP_GRPH_COLOR_EXPANSION_MODE;
7829
7830/*
7831 * UNP_VIDEO_FORMAT enum
7832 */
7833
7834typedef enum UNP_VIDEO_FORMAT {
7835UNP_VIDEO_FORMAT0                        = 0x00000000,
7836UNP_VIDEO_FORMAT1                        = 0x00000001,
7837UNP_VIDEO_FORMAT_YUV420_YCbCr            = 0x00000002,
7838UNP_VIDEO_FORMAT_YUV420_YCrCb            = 0x00000003,
7839UNP_VIDEO_FORMAT_YUV422_YCb              = 0x00000004,
7840UNP_VIDEO_FORMAT_YUV422_YCr              = 0x00000005,
7841UNP_VIDEO_FORMAT_YUV422_CbY              = 0x00000006,
7842UNP_VIDEO_FORMAT_YUV422_CrY              = 0x00000007,
7843} UNP_VIDEO_FORMAT;
7844
7845/*
7846 * UNP_GRPH_ENDIAN_SWAP enum
7847 */
7848
7849typedef enum UNP_GRPH_ENDIAN_SWAP {
7850UNP_GRPH_ENDIAN_SWAP_NONE                = 0x00000000,
7851UNP_GRPH_ENDIAN_SWAP_8IN16               = 0x00000001,
7852UNP_GRPH_ENDIAN_SWAP_8IN32               = 0x00000002,
7853UNP_GRPH_ENDIAN_SWAP_8IN43               = 0x00000003,
7854} UNP_GRPH_ENDIAN_SWAP;
7855
7856/*
7857 * UNP_GRPH_RED_CROSSBAR enum
7858 */
7859
7860typedef enum UNP_GRPH_RED_CROSSBAR {
7861UNP_GRPH_RED_CROSSBAR_R_Cr               = 0x00000000,
7862UNP_GRPH_RED_CROSSBAR_G_Y                = 0x00000001,
7863UNP_GRPH_RED_CROSSBAR_B_Cb               = 0x00000002,
7864UNP_GRPH_RED_CROSSBAR_A                  = 0x00000003,
7865} UNP_GRPH_RED_CROSSBAR;
7866
7867/*
7868 * UNP_GRPH_GREEN_CROSSBAR enum
7869 */
7870
7871typedef enum UNP_GRPH_GREEN_CROSSBAR {
7872UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y     = 0x00000000,
7873UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C   = 0x00000001,
7874UNP_UNP_GRPH_GREEN_CROSSBAR_A            = 0x00000002,
7875UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr         = 0x00000003,
7876} UNP_GRPH_GREEN_CROSSBAR;
7877
7878/*
7879 * UNP_GRPH_BLUE_CROSSBAR enum
7880 */
7881
7882typedef enum UNP_GRPH_BLUE_CROSSBAR {
7883UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C        = 0x00000000,
7884UNP_GRPH_BLUE_CROSSBAR_A                 = 0x00000001,
7885UNP_GRPH_BLUE_CROSSBAR_R_Cr              = 0x00000002,
7886UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y          = 0x00000003,
7887} UNP_GRPH_BLUE_CROSSBAR;
7888
7889/*
7890 * UNP_GRPH_MODE_UPDATE_LOCKG enum
7891 */
7892
7893typedef enum UNP_GRPH_MODE_UPDATE_LOCKG {
7894UNP_GRPH_UPDATE_LOCK_0                   = 0x00000000,
7895UNP_GRPH_UPDATE_LOCK_1                   = 0x00000001,
7896} UNP_GRPH_MODE_UPDATE_LOCKG;
7897
7898/*
7899 * UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK enum
7900 */
7901
7902typedef enum UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
7903UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0    = 0x00000000,
7904UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1    = 0x00000001,
7905} UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK;
7906
7907/*
7908 * UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE enum
7909 */
7910
7911typedef enum UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
7912UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0  = 0x00000000,
7913UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1  = 0x00000001,
7914} UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE;
7915
7916/*
7917 * UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE enum
7918 */
7919
7920typedef enum UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
7921UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0  = 0x00000000,
7922UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1  = 0x00000001,
7923} UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE;
7924
7925/*
7926 * UNP_GRPH_STEREOSYNC_FLIP_EN enum
7927 */
7928
7929typedef enum UNP_GRPH_STEREOSYNC_FLIP_EN {
7930UNP_GRPH_STEREOSYNC_FLIP_DISABLE         = 0x00000000,
7931UNP_GRPH_STEREOSYNC_FLIP_ENABLE          = 0x00000001,
7932} UNP_GRPH_STEREOSYNC_FLIP_EN;
7933
7934/*
7935 * UNP_GRPH_STEREOSYNC_FLIP_MODE enum
7936 */
7937
7938typedef enum UNP_GRPH_STEREOSYNC_FLIP_MODE {
7939UNP_GRPH_STEREOSYNC_FLIP_MODE_0          = 0x00000000,
7940UNP_GRPH_STEREOSYNC_FLIP_MODE_1          = 0x00000001,
7941UNP_GRPH_STEREOSYNC_FLIP_MODE_2          = 0x00000002,
7942UNP_GRPH_STEREOSYNC_FLIP_MODE_3          = 0x00000003,
7943} UNP_GRPH_STEREOSYNC_FLIP_MODE;
7944
7945/*
7946 * UNP_GRPH_STACK_INTERLACE_FLIP_EN enum
7947 */
7948
7949typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_EN {
7950UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE    = 0x00000000,
7951UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE     = 0x00000001,
7952} UNP_GRPH_STACK_INTERLACE_FLIP_EN;
7953
7954/*
7955 * UNP_GRPH_STACK_INTERLACE_FLIP_MODE enum
7956 */
7957
7958typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_MODE {
7959UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0     = 0x00000000,
7960UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1     = 0x00000001,
7961UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2     = 0x00000002,
7962UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3     = 0x00000003,
7963} UNP_GRPH_STACK_INTERLACE_FLIP_MODE;
7964
7965/*
7966 * UNP_GRPH_STEREOSYNC_SELECT_DISABLE enum
7967 */
7968
7969typedef enum UNP_GRPH_STEREOSYNC_SELECT_DISABLE {
7970UNP_GRPH_STEREOSYNC_SELECT_EN            = 0x00000000,
7971UNP_GRPH_STEREOSYNC_SELECT_DIS           = 0x00000001,
7972} UNP_GRPH_STEREOSYNC_SELECT_DISABLE;
7973
7974/*
7975 * UNP_CRC_SOURCE_SEL enum
7976 */
7977
7978typedef enum UNP_CRC_SOURCE_SEL {
7979UNP_CRC_SOURCE_SEL_NP_TO_LBV             = 0x00000000,
7980UNP_CRC_SOURCE_SEL_LOWER32               = 0x00000001,
7981UNP_CRC_SOURCE_SEL_RESERVED              = 0x00000002,
7982UNP_CRC_SOURCE_SEL_LOWER16               = 0x00000003,
7983UNP_CRC_SOURCE_SEL_UNP_TO_LBV            = 0x00000004,
7984} UNP_CRC_SOURCE_SEL;
7985
7986/*
7987 * UNP_CRC_LINE_SEL enum
7988 */
7989
7990typedef enum UNP_CRC_LINE_SEL {
7991UNP_CRC_LINE_SEL_RESERVED                = 0x00000000,
7992UNP_CRC_LINE_SEL_EVEN_ONLY               = 0x00000001,
7993UNP_CRC_LINE_SEL_ODD_ONLY                = 0x00000002,
7994UNP_CRC_LINE_SEL_ODD_EVEN                = 0x00000003,
7995} UNP_CRC_LINE_SEL;
7996
7997/*
7998 * UNP_ROTATION_ANGLE enum
7999 */
8000

8001typedef enum UNP_ROTATION_ANGLE {
8002UNP_ROTATION_ANGLE_0                     = 0x00000000,
8003UNP_ROTATION_ANGLE_90                    = 0x00000001,
8004UNP_ROTATION_ANGLE_180                   = 0x00000002,
8005UNP_ROTATION_ANGLE_270                   = 0x00000003,
8006UNP_ROTATION_ANGLE_0m                    = 0x00000004,
8007UNP_ROTATION_ANGLE_90m                   = 0x00000005,
8008UNP_ROTATION_ANGLE_180m                  = 0x00000006,
8009UNP_ROTATION_ANGLE_270m                  = 0x00000007,
8010} UNP_ROTATION_ANGLE;
8011
8012/*
8013 * UNP_PIXEL_DROP enum
8014 */
8015
8016typedef enum UNP_PIXEL_DROP {
8017UNP_PIXEL_NO_DROP                        = 0x00000000,
8018UNP_PIXEL_DROPPING                       = 0x00000001,
8019} UNP_PIXEL_DROP;
8020
8021/*
8022 * UNP_BUFFER_MODE enum
8023 */
8024
8025typedef enum UNP_BUFFER_MODE {
8026UNP_BUFFER_MODE_LUMA                     = 0x00000000,
8027UNP_BUFFER_MODE_LUMA_CHROMA              = 0x00000001,
8028} UNP_BUFFER_MODE;
8029
8030/*******************************************************
8031 * DP Enums
8032 *******************************************************/
8033
8034/*
8035 * DP_LINK_TRAINING_COMPLETE enum
8036 */
8037
8038typedef enum DP_LINK_TRAINING_COMPLETE {
8039DP_LINK_TRAINING_NOT_COMPLETE            = 0x00000000,
8040DP_LINK_TRAINING_ALREADY_COMPLETE        = 0x00000001,
8041} DP_LINK_TRAINING_COMPLETE;
8042
8043/*
8044 * DP_EMBEDDED_PANEL_MODE enum
8045 */
8046
8047typedef enum DP_EMBEDDED_PANEL_MODE {
8048DP_EXTERNAL_PANEL                        = 0x00000000,
8049DP_EMBEDDED_PANEL                        = 0x00000001,
8050} DP_EMBEDDED_PANEL_MODE;
8051
8052/*
8053 * DP_PIXEL_ENCODING enum
8054 */
8055
8056typedef enum DP_PIXEL_ENCODING {
8057DP_PIXEL_ENCODING_RGB444                 = 0x00000000,
8058DP_PIXEL_ENCODING_YCBCR422               = 0x00000001,
8059DP_PIXEL_ENCODING_YCBCR444               = 0x00000002,
8060DP_PIXEL_ENCODING_RGB_WIDE_GAMUT         = 0x00000003,
8061DP_PIXEL_ENCODING_Y_ONLY                 = 0x00000004,
8062DP_PIXEL_ENCODING_YCBCR420               = 0x00000005,
8063DP_PIXEL_ENCODING_RESERVED               = 0x00000006,
8064} DP_PIXEL_ENCODING;
8065
8066/*
8067 * DP_DYN_RANGE enum
8068 */
8069
8070typedef enum DP_DYN_RANGE {
8071DP_DYN_VESA_RANGE                        = 0x00000000,
8072DP_DYN_CEA_RANGE                         = 0x00000001,
8073} DP_DYN_RANGE;
8074
8075/*
8076 * DP_YCBCR_RANGE enum
8077 */
8078
8079typedef enum DP_YCBCR_RANGE {
8080DP_YCBCR_RANGE_BT601_5                   = 0x00000000,
8081DP_YCBCR_RANGE_BT709_5                   = 0x00000001,
8082} DP_YCBCR_RANGE;
8083
8084/*
8085 * DP_COMPONENT_DEPTH enum
8086 */
8087
8088typedef enum DP_COMPONENT_DEPTH {
8089DP_COMPONENT_DEPTH_6BPC                  = 0x00000000,
8090DP_COMPONENT_DEPTH_8BPC                  = 0x00000001,
8091DP_COMPONENT_DEPTH_10BPC                 = 0x00000002,
8092DP_COMPONENT_DEPTH_12BPC                 = 0x00000003,
8093DP_COMPONENT_DEPTH_16BPC_RESERVED        = 0x00000004,
8094DP_COMPONENT_DEPTH_RESERVED              = 0x00000005,
8095} DP_COMPONENT_DEPTH;
8096
8097/*
8098 * DP_MSA_MISC0_OVERRIDE_ENABLE enum
8099 */
8100
8101typedef enum DP_MSA_MISC0_OVERRIDE_ENABLE {
8102MSA_MISC0_OVERRIDE_DISABLE               = 0x00000000,
8103MSA_MISC0_OVERRIDE_ENABLE                = 0x00000001,
8104} DP_MSA_MISC0_OVERRIDE_ENABLE;
8105
8106/*
8107 * DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE enum
8108 */
8109
8110typedef enum DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE {
8111MSA_MISC1_BIT7_OVERRIDE_DISABLE          = 0x00000000,
8112MSA_MISC1_BIT7_OVERRIDE_ENABLE           = 0x00000001,
8113} DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE;
8114
8115/*
8116 * DP_UDI_LANES enum
8117 */
8118
8119typedef enum DP_UDI_LANES {
8120DP_UDI_1_LANE                            = 0x00000000,
8121DP_UDI_2_LANES                           = 0x00000001,
8122DP_UDI_LANES_RESERVED                    = 0x00000002,
8123DP_UDI_4_LANES                           = 0x00000003,
8124} DP_UDI_LANES;
8125
8126/*
8127 * DP_VID_STREAM_DIS_DEFER enum
8128 */
8129
8130typedef enum DP_VID_STREAM_DIS_DEFER {
8131DP_VID_STREAM_DIS_NO_DEFER               = 0x00000000,
8132DP_VID_STREAM_DIS_DEFER_TO_HBLANK        = 0x00000001,
8133DP_VID_STREAM_DIS_DEFER_TO_VBLANK        = 0x00000002,
8134} DP_VID_STREAM_DIS_DEFER;
8135
8136/*
8137 * DP_STEER_OVERFLOW_ACK enum
8138 */
8139
8140typedef enum DP_STEER_OVERFLOW_ACK {
8141DP_STEER_OVERFLOW_ACK_NO_EFFECT          = 0x00000000,
8142DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT      = 0x00000001,
8143} DP_STEER_OVERFLOW_ACK;
8144
8145/*
8146 * DP_STEER_OVERFLOW_MASK enum
8147 */
8148
8149typedef enum DP_STEER_OVERFLOW_MASK {
8150DP_STEER_OVERFLOW_MASKED                 = 0x00000000,
8151DP_STEER_OVERFLOW_UNMASK                 = 0x00000001,
8152} DP_STEER_OVERFLOW_MASK;
8153
8154/*
8155 * DP_TU_OVERFLOW_ACK enum
8156 */
8157
8158typedef enum DP_TU_OVERFLOW_ACK {
8159DP_TU_OVERFLOW_ACK_NO_EFFECT             = 0x00000000,
8160DP_TU_OVERFLOW_ACK_CLR_INTERRUPT         = 0x00000001,
8161} DP_TU_OVERFLOW_ACK;
8162
8163/*
8164 * DPHY_ALT_SCRAMBLER_RESET_EN enum
8165 */
8166
8167typedef enum DPHY_ALT_SCRAMBLER_RESET_EN {
8168DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE   = 0x00000000,
8169DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION  = 0x00000001,
8170} DPHY_ALT_SCRAMBLER_RESET_EN;
8171
8172/*
8173 * DPHY_ALT_SCRAMBLER_RESET_SEL enum
8174 */
8175
8176typedef enum DPHY_ALT_SCRAMBLER_RESET_SEL {
8177DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE  = 0x00000000,
8178DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE  = 0x00000001,
8179} DPHY_ALT_SCRAMBLER_RESET_SEL;
8180
8181/*
8182 * DP_VID_TIMING_MODE enum
8183 */
8184
8185typedef enum DP_VID_TIMING_MODE {
8186DP_VID_TIMING_MODE_ASYNC                 = 0x00000000,
8187DP_VID_TIMING_MODE_SYNC                  = 0x00000001,
8188} DP_VID_TIMING_MODE;
8189
8190/*
8191 * DP_VID_M_N_DOUBLE_BUFFER_MODE enum
8192 */
8193
8194typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE {
8195DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE  = 0x00000000,
8196DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START  = 0x00000001,
8197} DP_VID_M_N_DOUBLE_BUFFER_MODE;
8198
8199/*
8200 * DP_VID_M_N_GEN_EN enum
8201 */
8202
8203typedef enum DP_VID_M_N_GEN_EN {
8204DP_VID_M_N_PROGRAMMED_VIA_REG            = 0x00000000,
8205DP_VID_M_N_CALC_AUTO                     = 0x00000001,
8206} DP_VID_M_N_GEN_EN;
8207
8208/*
8209 * DP_VID_M_DOUBLE_VALUE_EN enum
8210 */
8211
8212typedef enum DP_VID_M_DOUBLE_VALUE_EN {
8213DP_VID_M_INPUT_PIXEL_RATE                = 0x00000000,
8214DP_VID_M_DOUBLE_INPUT_PIXEL_RATE         = 0x00000001,
8215} DP_VID_M_DOUBLE_VALUE_EN;
8216
8217/*
8218 * DP_VID_ENHANCED_FRAME_MODE enum
8219 */
8220
8221typedef enum DP_VID_ENHANCED_FRAME_MODE {
8222VID_NORMAL_FRAME_MODE                    = 0x00000000,
8223VID_ENHANCED_MODE                        = 0x00000001,
8224} DP_VID_ENHANCED_FRAME_MODE;
8225
8226/*
8227 * DP_VID_MSA_TOP_FIELD_MODE enum
8228 */
8229
8230typedef enum DP_VID_MSA_TOP_FIELD_MODE {
8231DP_TOP_FIELD_ONLY                        = 0x00000000,
8232DP_TOP_PLUS_BOTTOM_FIELD                 = 0x00000001,
8233} DP_VID_MSA_TOP_FIELD_MODE;
8234
8235/*
8236 * DP_VID_VBID_FIELD_POL enum
8237 */
8238
8239typedef enum DP_VID_VBID_FIELD_POL {
8240DP_VID_VBID_FIELD_POL_NORMAL             = 0x00000000,
8241DP_VID_VBID_FIELD_POL_INV                = 0x00000001,
8242} DP_VID_VBID_FIELD_POL;
8243
8244/*
8245 * DP_VID_STREAM_DISABLE_ACK enum
8246 */
8247
8248typedef enum DP_VID_STREAM_DISABLE_ACK {
8249ID_STREAM_DISABLE_NO_ACK                 = 0x00000000,
8250ID_STREAM_DISABLE_ACKED                  = 0x00000001,
8251} DP_VID_STREAM_DISABLE_ACK;
8252
8253/*
8254 * DP_VID_STREAM_DISABLE_MASK enum
8255 */
8256
8257typedef enum DP_VID_STREAM_DISABLE_MASK {
8258VID_STREAM_DISABLE_MASKED                = 0x00000000,
8259VID_STREAM_DISABLE_UNMASK                = 0x00000001,
8260} DP_VID_STREAM_DISABLE_MASK;
8261
8262/*
8263 * DPHY_ATEST_SEL_LANE0 enum
8264 */
8265
8266typedef enum DPHY_ATEST_SEL_LANE0 {
8267DPHY_ATEST_LANE0_PRBS_PATTERN            = 0x00000000,
8268DPHY_ATEST_LANE0_REG_PATTERN             = 0x00000001,
8269} DPHY_ATEST_SEL_LANE0;
8270
8271/*
8272 * DPHY_ATEST_SEL_LANE1 enum
8273 */
8274
8275typedef enum DPHY_ATEST_SEL_LANE1 {
8276DPHY_ATEST_LANE1_PRBS_PATTERN            = 0x00000000,
8277DPHY_ATEST_LANE1_REG_PATTERN             = 0x00000001,
8278} DPHY_ATEST_SEL_LANE1;
8279
8280/*
8281 * DPHY_ATEST_SEL_LANE2 enum
8282 */
8283
8284typedef enum DPHY_ATEST_SEL_LANE2 {
8285DPHY_ATEST_LANE2_PRBS_PATTERN            = 0x00000000,
8286DPHY_ATEST_LANE2_REG_PATTERN             = 0x00000001,
8287} DPHY_ATEST_SEL_LANE2;
8288
8289/*
8290 * DPHY_ATEST_SEL_LANE3 enum
8291 */
8292
8293typedef enum DPHY_ATEST_SEL_LANE3 {
8294DPHY_ATEST_LANE3_PRBS_PATTERN            = 0x00000000,
8295DPHY_ATEST_LANE3_REG_PATTERN             = 0x00000001,
8296} DPHY_ATEST_SEL_LANE3;
8297
8298/*
8299 * DPHY_SCRAMBLER_SEL enum
8300 */
8301
8302typedef enum DPHY_SCRAMBLER_SEL {
8303DPHY_SCRAMBLER_SEL_LANE_DATA             = 0x00000000,
8304DPHY_SCRAMBLER_SEL_DBG_DATA              = 0x00000001,
8305} DPHY_SCRAMBLER_SEL;
8306
8307/*
8308 * DPHY_BYPASS enum
8309 */
8310
8311typedef enum DPHY_BYPASS {
8312DPHY_8B10B_OUTPUT                        = 0x00000000,
8313DPHY_DBG_OUTPUT                          = 0x00000001,
8314} DPHY_BYPASS;
8315
8316/*
8317 * DPHY_SKEW_BYPASS enum
8318 */
8319
8320typedef enum DPHY_SKEW_BYPASS {
8321DPHY_WITH_SKEW                           = 0x00000000,
8322DPHY_NO_SKEW                             = 0x00000001,
8323} DPHY_SKEW_BYPASS;
8324
8325/*
8326 * DPHY_TRAINING_PATTERN_SEL enum
8327 */
8328
8329typedef enum DPHY_TRAINING_PATTERN_SEL {
8330DPHY_TRAINING_PATTERN_1                  = 0x00000000,
8331DPHY_TRAINING_PATTERN_2                  = 0x00000001,
8332DPHY_TRAINING_PATTERN_3                  = 0x00000002,
8333DPHY_TRAINING_PATTERN_4                  = 0x00000003,
8334} DPHY_TRAINING_PATTERN_SEL;
8335
8336/*
8337 * DPHY_8B10B_RESET enum
8338 */
8339
8340typedef enum DPHY_8B10B_RESET {
8341DPHY_8B10B_NOT_RESET                     = 0x00000000,
8342DPHY_8B10B_RESETET                       = 0x00000001,
8343} DPHY_8B10B_RESET;
8344
8345/*
8346 * DP_DPHY_8B10B_EXT_DISP enum
8347 */
8348
8349typedef enum DP_DPHY_8B10B_EXT_DISP {
8350DP_DPHY_8B10B_EXT_DISP_ZERO              = 0x00000000,
8351DP_DPHY_8B10B_EXT_DISP_ONE               = 0x00000001,
8352} DP_DPHY_8B10B_EXT_DISP;
8353
8354/*
8355 * DPHY_8B10B_CUR_DISP enum
8356 */
8357
8358typedef enum DPHY_8B10B_CUR_DISP {
8359DPHY_8B10B_CUR_DISP_ZERO                 = 0x00000000,
8360DPHY_8B10B_CUR_DISP_ONE                  = 0x00000001,
8361} DPHY_8B10B_CUR_DISP;
8362
8363/*
8364 * DPHY_PRBS_EN enum
8365 */
8366
8367typedef enum DPHY_PRBS_EN {
8368DPHY_PRBS_DISABLE                        = 0x00000000,
8369DPHY_PRBS_ENABLE                         = 0x00000001,
8370} DPHY_PRBS_EN;
8371
8372/*
8373 * DPHY_PRBS_SEL enum
8374 */
8375
8376typedef enum DPHY_PRBS_SEL {
8377DPHY_PRBS7_SELECTED                      = 0x00000000,
8378DPHY_PRBS23_SELECTED                     = 0x00000001,
8379DPHY_PRBS11_SELECTED                     = 0x00000002,
8380} DPHY_PRBS_SEL;
8381
8382/*
8383 * DPHY_SCRAMBLER_DIS enum
8384 */
8385
8386typedef enum DPHY_SCRAMBLER_DIS {
8387DPHY_SCR_ENABLED                         = 0x00000000,
8388DPHY_SCR_DISABLED                        = 0x00000001,
8389} DPHY_SCRAMBLER_DIS;
8390
8391/*
8392 * DPHY_SCRAMBLER_ADVANCE enum
8393 */
8394
8395typedef enum DPHY_SCRAMBLER_ADVANCE {
8396DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY  = 0x00000000,
8397DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL  = 0x00000001,
8398} DPHY_SCRAMBLER_ADVANCE;
8399
8400/*
8401 * DPHY_SCRAMBLER_KCODE enum
8402 */
8403
8404typedef enum DPHY_SCRAMBLER_KCODE {
8405DPHY_SCRAMBLER_KCODE_DISABLED            = 0x00000000,
8406DPHY_SCRAMBLER_KCODE_ENABLED             = 0x00000001,
8407} DPHY_SCRAMBLER_KCODE;
8408
8409/*
8410 * DPHY_LOAD_BS_COUNT_START enum
8411 */
8412
8413typedef enum DPHY_LOAD_BS_COUNT_START {
8414DPHY_LOAD_BS_COUNT_STARTED               = 0x00000000,
8415DPHY_LOAD_BS_COUNT_NOT_STARTED           = 0x00000001,
8416} DPHY_LOAD_BS_COUNT_START;
8417
8418/*
8419 * DPHY_CRC_EN enum
8420 */
8421
8422typedef enum DPHY_CRC_EN {
8423DPHY_CRC_DISABLED                        = 0x00000000,
8424DPHY_CRC_ENABLED                         = 0x00000001,
8425} DPHY_CRC_EN;
8426
8427/*
8428 * DPHY_CRC_CONT_EN enum
8429 */
8430
8431typedef enum DPHY_CRC_CONT_EN {
8432DPHY_CRC_ONE_SHOT                        = 0x00000000,
8433DPHY_CRC_CONTINUOUS                      = 0x00000001,
8434} DPHY_CRC_CONT_EN;
8435
8436/*
8437 * DPHY_CRC_FIELD enum
8438 */
8439
8440typedef enum DPHY_CRC_FIELD {
8441DPHY_CRC_START_FROM_TOP_FIELD            = 0x00000000,
8442DPHY_CRC_START_FROM_BOTTOM_FIELD         = 0x00000001,
8443} DPHY_CRC_FIELD;
8444
8445/*
8446 * DPHY_CRC_SEL enum
8447 */
8448
8449typedef enum DPHY_CRC_SEL {
8450DPHY_CRC_LANE0_SELECTED                  = 0x00000000,
8451DPHY_CRC_LANE1_SELECTED                  = 0x00000001,
8452DPHY_CRC_LANE2_SELECTED                  = 0x00000002,
8453DPHY_CRC_LANE3_SELECTED                  = 0x00000003,
8454} DPHY_CRC_SEL;
8455
8456/*
8457 * DPHY_RX_FAST_TRAINING_CAPABLE enum
8458 */
8459
8460typedef enum DPHY_RX_FAST_TRAINING_CAPABLE {
8461DPHY_FAST_TRAINING_NOT_CAPABLE_0         = 0x00000000,
8462DPHY_FAST_TRAINING_CAPABLE               = 0x00000001,
8463} DPHY_RX_FAST_TRAINING_CAPABLE;
8464
8465/*
8466 * DP_SEC_COLLISION_ACK enum
8467 */
8468
8469typedef enum DP_SEC_COLLISION_ACK {
8470DP_SEC_COLLISION_ACK_NO_EFFECT           = 0x00000000,
8471DP_SEC_COLLISION_ACK_CLR_FLAG            = 0x00000001,
8472} DP_SEC_COLLISION_ACK;
8473
8474/*
8475 * DP_SEC_AUDIO_MUTE enum
8476 */
8477
8478typedef enum DP_SEC_AUDIO_MUTE {
8479DP_SEC_AUDIO_MUTE_HW_CTRL                = 0x00000000,
8480DP_SEC_AUDIO_MUTE_SW_CTRL                = 0x00000001,
8481} DP_SEC_AUDIO_MUTE;
8482
8483/*
8484 * DP_SEC_TIMESTAMP_MODE enum
8485 */
8486
8487typedef enum DP_SEC_TIMESTAMP_MODE {
8488DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE       = 0x00000000,
8489DP_SEC_TIMESTAMP_AUTO_CALC_MODE          = 0x00000001,
8490} DP_SEC_TIMESTAMP_MODE;
8491
8492/*
8493 * DP_SEC_ASP_PRIORITY enum
8494 */
8495
8496typedef enum DP_SEC_ASP_PRIORITY {
8497DP_SEC_ASP_LOW_PRIORITY                  = 0x00000000,
8498DP_SEC_ASP_HIGH_PRIORITY                 = 0x00000001,
8499} DP_SEC_ASP_PRIORITY;
8500
8501/*
8502 * DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE enum
8503 */
8504
8505typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE {
8506DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ         = 0x00000000,
8507DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED  = 0x00000001,
8508} DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE;
8509
8510/*
8511 * DP_MSE_SAT_UPDATE_ACT enum
8512 */
8513
8514typedef enum DP_MSE_SAT_UPDATE_ACT {
8515DP_MSE_SAT_UPDATE_NO_ACTION              = 0x00000000,
8516DP_MSE_SAT_UPDATE_WITH_TRIGGER           = 0x00000001,
8517DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER        = 0x00000002,
8518} DP_MSE_SAT_UPDATE_ACT;
8519
8520/*
8521 * DP_MSE_LINK_LINE enum
8522 */
8523
8524typedef enum DP_MSE_LINK_LINE {
8525DP_MSE_LINK_LINE_32_MTP_LONG             = 0x00000000,
8526DP_MSE_LINK_LINE_64_MTP_LONG             = 0x00000001,
8527DP_MSE_LINK_LINE_128_MTP_LONG            = 0x00000002,
8528DP_MSE_LINK_LINE_256_MTP_LONG            = 0x00000003,
8529} DP_MSE_LINK_LINE;
8530
8531/*
8532 * DP_MSE_BLANK_CODE enum
8533 */
8534
8535typedef enum DP_MSE_BLANK_CODE {
8536DP_MSE_BLANK_CODE_SF_FILLED              = 0x00000000,
8537DP_MSE_BLANK_CODE_ZERO_FILLED            = 0x00000001,
8538} DP_MSE_BLANK_CODE;
8539
8540/*
8541 * DP_MSE_TIMESTAMP_MODE enum
8542 */
8543
8544typedef enum DP_MSE_TIMESTAMP_MODE {
8545DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE  = 0x00000000,
8546DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE   = 0x00000001,
8547} DP_MSE_TIMESTAMP_MODE;
8548
8549/*
8550 * DP_MSE_ZERO_ENCODER enum
8551 */
8552
8553typedef enum DP_MSE_ZERO_ENCODER {
8554DP_MSE_NOT_ZERO_FE_ENCODER               = 0x00000000,
8555DP_MSE_ZERO_FE_ENCODER                   = 0x00000001,
8556} DP_MSE_ZERO_ENCODER;
8557
8558/*
8559 * DP_MSE_OUTPUT_DPDBG_DATA enum
8560 */
8561
8562typedef enum DP_MSE_OUTPUT_DPDBG_DATA {
8563DP_MSE_OUTPUT_DPDBG_DATA_DIS             = 0x00000000,
8564DP_MSE_OUTPUT_DPDBG_DATA_EN              = 0x00000001,
8565} DP_MSE_OUTPUT_DPDBG_DATA;
8566
8567/*
8568 * DP_DPHY_HBR2_PATTERN_CONTROL_MODE enum
8569 */
8570
8571typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE {
8572DP_DPHY_HBR2_PASS_THROUGH                = 0x00000000,
8573DP_DPHY_HBR2_PATTERN_1                   = 0x00000001,
8574DP_DPHY_HBR2_PATTERN_2_NEG               = 0x00000002,
8575DP_DPHY_HBR2_PATTERN_3                   = 0x00000003,
8576DP_DPHY_HBR2_PATTERN_2_POS               = 0x00000006,
8577} DP_DPHY_HBR2_PATTERN_CONTROL_MODE;
8578
8579/*
8580 * DPHY_CRC_MST_PHASE_ERROR_ACK enum
8581 */
8582
8583typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK {
8584DPHY_CRC_MST_PHASE_ERROR_NO_ACK          = 0x00000000,
8585DPHY_CRC_MST_PHASE_ERROR_ACKED           = 0x00000001,
8586} DPHY_CRC_MST_PHASE_ERROR_ACK;
8587
8588/*
8589 * DPHY_SW_FAST_TRAINING_START enum
8590 */
8591
8592typedef enum DPHY_SW_FAST_TRAINING_START {
8593DPHY_SW_FAST_TRAINING_NOT_STARTED        = 0x00000000,
8594DPHY_SW_FAST_TRAINING_STARTED            = 0x00000001,
8595} DPHY_SW_FAST_TRAINING_START;
8596
8597/*
8598 * DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN enum
8599 */
8600
8601typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN {
8602DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED  = 0x00000000,
8603DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED  = 0x00000001,
8604} DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN;
8605
8606/*
8607 * DP_DPHY_FAST_TRAINING_COMPLETE_MASK enum
8608 */
8609
8610typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK {
8611DP_DPHY_FAST_TRAINING_COMPLETE_MASKED    = 0x00000000,
8612DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED  = 0x00000001,
8613} DP_DPHY_FAST_TRAINING_COMPLETE_MASK;
8614
8615/*
8616 * DP_DPHY_FAST_TRAINING_COMPLETE_ACK enum
8617 */
8618
8619typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK {
8620DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED  = 0x00000000,
8621DP_DPHY_FAST_TRAINING_COMPLETE_ACKED     = 0x00000001,
8622} DP_DPHY_FAST_TRAINING_COMPLETE_ACK;
8623
8624/*
8625 * DP_MSA_V_TIMING_OVERRIDE_EN enum
8626 */
8627
8628typedef enum DP_MSA_V_TIMING_OVERRIDE_EN {
8629MSA_V_TIMING_OVERRIDE_DISABLED           = 0x00000000,
8630MSA_V_TIMING_OVERRIDE_ENABLED            = 0x00000001,
8631} DP_MSA_V_TIMING_OVERRIDE_EN;
8632
8633/*
8634 * DP_SEC_GSP0_PRIORITY enum
8635 */
8636
8637typedef enum DP_SEC_GSP0_PRIORITY {
8638SEC_GSP0_PRIORITY_LOW                    = 0x00000000,
8639SEC_GSP0_PRIORITY_HIGH                   = 0x00000001,
8640} DP_SEC_GSP0_PRIORITY;
8641
8642/*
8643 * DP_SEC_GSP0_SEND enum
8644 */
8645
8646typedef enum DP_SEC_GSP0_SEND {
8647NOT_SENT                                 = 0x00000000,
8648FORCE_SENT                               = 0x00000001,
8649} DP_SEC_GSP0_SEND;
8650
8651/*******************************************************
8652 * COL_MAN Enums
8653 *******************************************************/
8654
8655/*
8656 * COL_MAN_UPDATE_LOCK enum
8657 */
8658
8659typedef enum COL_MAN_UPDATE_LOCK {
8660COL_MAN_UPDATE_UNLOCKED                  = 0x00000000,
8661COL_MAN_UPDATE_LOCKED                    = 0x00000001,
8662} COL_MAN_UPDATE_LOCK;
8663
8664/*
8665 * COL_MAN_DISABLE_MULTIPLE_UPDATE enum
8666 */
8667
8668typedef enum COL_MAN_DISABLE_MULTIPLE_UPDATE {
8669COL_MAN_MULTIPLE_UPDATE                  = 0x00000000,
8670COL_MAN_MULTIPLE_UPDAT_EDISABLE          = 0x00000001,
8671} COL_MAN_DISABLE_MULTIPLE_UPDATE;
8672
8673/*
8674 * COL_MAN_INPUTCSC_MODE enum
8675 */
8676
8677typedef enum COL_MAN_INPUTCSC_MODE {
8678INPUTCSC_MODE_BYPASS                     = 0x00000000,
8679INPUTCSC_MODE_A                          = 0x00000001,
8680INPUTCSC_MODE_B                          = 0x00000002,
8681INPUTCSC_MODE_UNITY                      = 0x00000003,
8682} COL_MAN_INPUTCSC_MODE;
8683
8684/*
8685 * COL_MAN_INPUTCSC_TYPE enum
8686 */
8687
8688typedef enum COL_MAN_INPUTCSC_TYPE {
8689INPUTCSC_TYPE_12_0                       = 0x00000000,
8690INPUTCSC_TYPE_10_2                       = 0x00000001,
8691INPUTCSC_TYPE_8_4                        = 0x00000002,
8692} COL_MAN_INPUTCSC_TYPE;
8693
8694/*
8695 * COL_MAN_INPUTCSC_CONVERT enum
8696 */
8697
8698typedef enum COL_MAN_INPUTCSC_CONVERT {
8699INPUTCSC_ROUND                           = 0x00000000,
8700INPUTCSC_TRUNCATE                        = 0x00000001,
8701} COL_MAN_INPUTCSC_CONVERT;
8702
8703/*
8704 * COL_MAN_PRESCALE_MODE enum
8705 */
8706
8707typedef enum COL_MAN_PRESCALE_MODE {
8708PRESCALE_MODE_BYPASS                     = 0x00000000,
8709PRESCALE_MODE_PROGRAM                    = 0x00000001,
8710PRESCALE_MODE_UNITY                      = 0x00000002,
8711} COL_MAN_PRESCALE_MODE;
8712
8713/*
8714 * COL_MAN_INPUT_GAMMA_MODE enum
8715 */
8716
8717typedef enum COL_MAN_INPUT_GAMMA_MODE {
8718INGAMMA_MODE_BYPASS                      = 0x00000000,
8719INGAMMA_MODE_FIX                         = 0x00000001,
8720INGAMMA_MODE_FLOAT                       = 0x00000002,
8721} COL_MAN_INPUT_GAMMA_MODE;
8722
8723/*
8724 * COL_MAN_OUTPUT_CSC_MODE enum
8725 */
8726
8727typedef enum COL_MAN_OUTPUT_CSC_MODE {
8728COL_MAN_OUTPUT_CSC_BYPASS                = 0x00000000,
8729COL_MAN_OUTPUT_CSC_RGB                   = 0x00000001,
8730COL_MAN_OUTPUT_CSC_YCrCb601              = 0x00000002,
8731COL_MAN_OUTPUT_CSC_YCrCb709              = 0x00000003,
8732COL_MAN_OUTPUT_CSC_A                     = 0x00000004,
8733COL_MAN_OUTPUT_CSC_B                     = 0x00000005,
8734COL_MAN_OUTPUT_CSC_UNITY                 = 0x00000006,
8735} COL_MAN_OUTPUT_CSC_MODE;
8736
8737/*
8738 * COL_MAN_DENORM_CLAMP_CONTROL enum
8739 */
8740
8741typedef enum COL_MAN_DENORM_CLAMP_CONTROL {
8742DENORM_CLAMP_MODE_UNITY                  = 0x00000000,
8743DENORM_CLAMP_MODE_8                      = 0x00000001,
8744DENORM_CLAMP_MODE_10                     = 0x00000002,
8745DENORM_CLAMP_MODE_12                     = 0x00000003,
8746} COL_MAN_DENORM_CLAMP_CONTROL;
8747
8748/*
8749 * COL_MAN_REGAMMA_MODE_CONTROL enum
8750 */
8751
8752typedef enum COL_MAN_REGAMMA_MODE_CONTROL {
8753COL_MAN_REGAMMA_MODE_BYPASS              = 0x00000000,
8754COL_MAN_REGAMMA_MODE_ROM_A               = 0x00000001,
8755COL_MAN_REGAMMA_MODE_ROM_B               = 0x00000002,
8756COL_MAN_REGAMMA_MODE_A                   = 0x00000003,
8757COL_MAN_REGAMMA_MODE_B                   = 0x00000004,
8758} COL_MAN_REGAMMA_MODE_CONTROL;
8759
8760/*
8761 * COL_MAN_GLOBAL_PASSTHROUGH_ENABLE enum
8762 */
8763
8764typedef enum COL_MAN_GLOBAL_PASSTHROUGH_ENABLE {
8765CM_GLOBAL_PASSTHROUGH_DISBALE            = 0x00000000,
8766CM_GLOBAL_PASSTHROUGH_ENABLE             = 0x00000001,
8767} COL_MAN_GLOBAL_PASSTHROUGH_ENABLE;
8768
8769/*
8770 * COL_MAN_DEGAMMA_MODE enum
8771 */
8772
8773typedef enum COL_MAN_DEGAMMA_MODE {
8774DEGAMMA_MODE_BYPASS                      = 0x00000000,
8775DEGAMMA_MODE_A                           = 0x00000001,
8776DEGAMMA_MODE_B                           = 0x00000002,
8777} COL_MAN_DEGAMMA_MODE;
8778
8779/*
8780 * COL_MAN_GAMUT_REMAP_MODE enum
8781 */
8782
8783typedef enum COL_MAN_GAMUT_REMAP_MODE {
8784GAMUT_REMAP_MODE_BYPASS                  = 0x00000000,
8785GAMUT_REMAP_MODE_1                       = 0x00000001,
8786GAMUT_REMAP_MODE_2                       = 0x00000002,
8787GAMUT_REMAP_MODE_3                       = 0x00000003,
8788} COL_MAN_GAMUT_REMAP_MODE;
8789
8790/*******************************************************
8791 * MCIF_WB Enums
8792 *******************************************************/
8793
8794/*******************************************************
8795 * DP_AUX Enums
8796 *******************************************************/
8797
8798/*
8799 * DP_AUX_CONTROL_HPD_SEL enum
8800 */
8801
8802typedef enum DP_AUX_CONTROL_HPD_SEL {
8803DP_AUX_CONTROL_HPD1_SELECTED             = 0x00000000,
8804DP_AUX_CONTROL_HPD2_SELECTED             = 0x00000001,
8805DP_AUX_CONTROL_HPD3_SELECTED             = 0x00000002,
8806DP_AUX_CONTROL_HPD4_SELECTED             = 0x00000003,
8807DP_AUX_CONTROL_HPD5_SELECTED             = 0x00000004,
8808DP_AUX_CONTROL_HPD6_SELECTED             = 0x00000005,
8809} DP_AUX_CONTROL_HPD_SEL;
8810
8811/*
8812 * DP_AUX_CONTROL_TEST_MODE enum
8813 */
8814
8815typedef enum DP_AUX_CONTROL_TEST_MODE {
8816DP_AUX_CONTROL_TEST_MODE_DISABLE         = 0x00000000,
8817DP_AUX_CONTROL_TEST_MODE_ENABLE          = 0x00000001,
8818} DP_AUX_CONTROL_TEST_MODE;
8819
8820/*
8821 * DP_AUX_SW_CONTROL_SW_GO enum
8822 */
8823
8824typedef enum DP_AUX_SW_CONTROL_SW_GO {
8825DP_AUX_SW_CONTROL_SW__NOT_GO             = 0x00000000,
8826DP_AUX_SW_CONTROL_SW__GO                 = 0x00000001,
8827} DP_AUX_SW_CONTROL_SW_GO;
8828
8829/*
8830 * DP_AUX_SW_CONTROL_LS_READ_TRIG enum
8831 */
8832
8833typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG {
8834DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG      = 0x00000000,
8835DP_AUX_SW_CONTROL_LS_READ__TRIG          = 0x00000001,
8836} DP_AUX_SW_CONTROL_LS_READ_TRIG;
8837
8838/*
8839 * DP_AUX_ARB_CONTROL_ARB_PRIORITY enum
8840 */
8841
8842typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY {
8843DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW  = 0x00000000,
8844DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW  = 0x00000001,
8845DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC  = 0x00000002,
8846DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS  = 0x00000003,
8847} DP_AUX_ARB_CONTROL_ARB_PRIORITY;
8848
8849/*
8850 * DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ enum
8851 */
8852
8853typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ {
8854DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ  = 0x00000000,
8855DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ      = 0x00000001,
8856} DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ;
8857
8858/*
8859 * DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG enum
8860 */
8861
8862typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG {
8863DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0x00000000,
8864DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG   = 0x00000001,
8865} DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG;
8866
8867/*
8868 * DP_AUX_INT_ACK enum
8869 */
8870
8871typedef enum DP_AUX_INT_ACK {
8872DP_AUX_INT__NOT_ACK                      = 0x00000000,
8873DP_AUX_INT__ACK                          = 0x00000001,
8874} DP_AUX_INT_ACK;
8875
8876/*
8877 * DP_AUX_LS_UPDATE_ACK enum
8878 */
8879
8880typedef enum DP_AUX_LS_UPDATE_ACK {
8881DP_AUX_INT_LS_UPDATE_NOT_ACK             = 0x00000000,
8882DP_AUX_INT_LS_UPDATE_ACK                 = 0x00000001,
8883} DP_AUX_LS_UPDATE_ACK;
8884
8885/*
8886 * DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL enum
8887 */
8888
8889typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL {
8890DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK  = 0x00000000,
8891DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF  = 0x00000001,
8892} DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL;
8893
8894/*
8895 * DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE enum
8896 */
8897
8898typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE {
8899DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0x00000000,
8900DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 0x00000001,
8901DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 0x00000002,
8902DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 0x00000003,
8903} DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE;
8904
8905/*
8906 * DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN enum
8907 */
8908
8909typedef enum DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN {
8910DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US = 0x00000000,
8911DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US = 0x00000001,
8912DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US = 0x00000002,
8913DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US = 0x00000003,
8914DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US = 0x00000004,
8915DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US = 0x00000005,
8916DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US = 0x00000006,
8917DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US = 0x00000007,
8918} DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN;
8919
8920/*
8921 * DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY enum
8922 */
8923
8924typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY {
8925DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0x00000000,
8926DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 0x00000001,
8927DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 0x00000002,
8928DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 0x00000003,
8929DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 0x00000004,
8930DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 0x00000005,
8931} DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY;
8932
8933/*
8934 * DP_AUX_DPHY_RX_CONTROL_START_WINDOW enum
8935 */
8936
8937typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW {
8938DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD  = 0x00000000,
8939DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD  = 0x00000001,
8940DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD  = 0x00000002,
8941DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD  = 0x00000003,
8942DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD  = 0x00000004,
8943DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD  = 0x00000005,
8944DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD  = 0x00000006,
8945DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD  = 0x00000007,
8946} DP_AUX_DPHY_RX_CONTROL_START_WINDOW;
8947
8948/*
8949 * DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW enum
8950 */
8951
8952typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW {
8953DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD  = 0x00000000,
8954DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD  = 0x00000001,
8955DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD  = 0x00000002,
8956DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD  = 0x00000003,
8957DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD  = 0x00000004,
8958DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD  = 0x00000005,
8959DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD  = 0x00000006,
8960DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD  = 0x00000007,
8961} DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW;
8962
8963/*
8964 * DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN enum
8965 */
8966
8967typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN {
8968DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0x00000000,
8969DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 0x00000001,
8970DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 0x00000002,
8971DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 0x00000003,
8972} DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN;
8973
8974/*
8975 * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT enum
8976 */
8977
8978typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT {
8979DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000000,
8980DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000001,
8981} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT;
8982
8983/*
8984 * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START enum
8985 */
8986
8987typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START {
8988DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0x00000000,
8989DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 0x00000001,
8990} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START;
8991
8992/*
8993 * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP enum
8994 */
8995
8996typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP {
8997DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0x00000000,
8998DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 0x00000001,
8999} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP;
9000

9001/*
9002 * DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN enum
9003 */
9004
9005typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN {
9006DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0x00000000,
9007DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 0x00000001,
9008DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 0x00000002,
9009DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 0x00000003,
9010} DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN;
9011
9012/*
9013 * DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN enum
9014 */
9015
9016typedef enum DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN {
9017DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US = 0x00000000,
9018DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US = 0x00000001,
9019DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US = 0x00000002,
9020DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US = 0x00000003,
9021DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US = 0x00000004,
9022DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US = 0x00000005,
9023DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US = 0x00000006,
9024DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US = 0x00000007,
9025} DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN;
9026
9027/*
9028 * DP_AUX_DPHY_RX_DETECTION_THRESHOLD enum
9029 */
9030
9031typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD {
9032DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2  = 0x00000000,
9033DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4  = 0x00000001,
9034DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8  = 0x00000002,
9035DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16  = 0x00000003,
9036DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32  = 0x00000004,
9037DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64  = 0x00000005,
9038DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128  = 0x00000006,
9039DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256  = 0x00000007,
9040} DP_AUX_DPHY_RX_DETECTION_THRESHOLD;
9041
9042/*
9043 * DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ enum
9044 */
9045
9046typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ {
9047DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX  = 0x00000000,
9048DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX  = 0x00000001,
9049} DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ;
9050
9051/*
9052 * DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW enum
9053 */
9054
9055typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW {
9056DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0x00000000,
9057DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 0x00000001,
9058DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 0x00000002,
9059DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 0x00000003,
9060} DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW;
9061
9062/*
9063 * DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT enum
9064 */
9065
9066typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT {
9067DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0x00000000,
9068DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 0x00000001,
9069DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 0x00000002,
9070DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 0x00000003,
9071} DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT;
9072
9073/*
9074 * DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN enum
9075 */
9076
9077typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN {
9078DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0  = 0x00000000,
9079DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64  = 0x00000001,
9080DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128  = 0x00000002,
9081DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256  = 0x00000003,
9082} DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN;
9083
9084/*
9085 * DP_AUX_ERR_OCCURRED_ACK enum
9086 */
9087
9088typedef enum DP_AUX_ERR_OCCURRED_ACK {
9089DP_AUX_ERR_OCCURRED__NOT_ACK             = 0x00000000,
9090DP_AUX_ERR_OCCURRED__ACK                 = 0x00000001,
9091} DP_AUX_ERR_OCCURRED_ACK;
9092
9093/*
9094 * DP_AUX_POTENTIAL_ERR_REACHED_ACK enum
9095 */
9096
9097typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK {
9098DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK    = 0x00000000,
9099DP_AUX_POTENTIAL_ERR_REACHED__ACK        = 0x00000001,
9100} DP_AUX_POTENTIAL_ERR_REACHED_ACK;
9101
9102/*
9103 * DP_AUX_DEFINITE_ERR_REACHED_ACK enum
9104 */
9105
9106typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK {
9107ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0x00000000,
9108ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK    = 0x00000001,
9109} DP_AUX_DEFINITE_ERR_REACHED_ACK;
9110
9111/*
9112 * DP_AUX_RESET enum
9113 */
9114
9115typedef enum DP_AUX_RESET {
9116DP_AUX_RESET_DEASSERTED                  = 0x00000000,
9117DP_AUX_RESET_ASSERTED                    = 0x00000001,
9118} DP_AUX_RESET;
9119
9120/*
9121 * DP_AUX_RESET_DONE enum
9122 */
9123
9124typedef enum DP_AUX_RESET_DONE {
9125DP_AUX_RESET_SEQUENCE_NOT_DONE           = 0x00000000,
9126DP_AUX_RESET_SEQUENCE_DONE               = 0x00000001,
9127} DP_AUX_RESET_DONE;
9128
9129/*******************************************************
9130 * DSI Enums
9131 *******************************************************/
9132
9133/*
9134 * DSI_COMMAND_MODE_SRC_FORMAT enum
9135 */
9136
9137typedef enum DSI_COMMAND_MODE_SRC_FORMAT {
9138DSI_COMMAND_SRC_FORMAT_RGB8BIT           = 0x00000002,
9139DSI_COMMAND_SRC_FORMAT_RGB332            = 0x00000003,
9140DSI_COMMAND_SRC_FORMAT_RGB444            = 0x00000004,
9141DSI_COMMAND_SRC_FORMAT_RGB555            = 0x00000005,
9142DSI_COMMAND_SRC_FORMAT_RGB565            = 0x00000006,
9143DSI_COMMAND_SRC_FORMAT_RGB888            = 0x00000008,
9144} DSI_COMMAND_MODE_SRC_FORMAT;
9145
9146/*
9147 * DSI_COMMAND_MODE_DST_FORMAT enum
9148 */
9149
9150typedef enum DSI_COMMAND_MODE_DST_FORMAT {
9151DSI_COMMAND_DST_FORMAT_RGB111            = 0x00000000,
9152DSI_COMMAND_DST_FORMAT_RGB332            = 0x00000003,
9153DSI_COMMAND_DST_FORMAT_RGB444            = 0x00000004,
9154DSI_COMMAND_DST_FORMAT_RGB565            = 0x00000006,
9155DSI_COMMAND_DST_FORMAT_RGB666            = 0x00000007,
9156DSI_COMMAND_DST_FORMAT_RGB888            = 0x00000008,
9157} DSI_COMMAND_MODE_DST_FORMAT;
9158
9159/*
9160 * DSI_FLAG_CLR enum
9161 */
9162
9163typedef enum DSI_FLAG_CLR {
9164DSI_FLAG_NO_CLEAR                        = 0x00000000,
9165DSI_FLAG_CLEAR                           = 0x00000001,
9166} DSI_FLAG_CLR;
9167
9168/*
9169 * DSI_BIT_SWAP enum
9170 */
9171
9172typedef enum DSI_BIT_SWAP {
9173DSI_BIT_SWAP_DISABLE                     = 0x00000000,
9174DSI_BIT_SWAP_ENABLE                      = 0x00000001,
9175} DSI_BIT_SWAP;
9176
9177/*
9178 * DSI_CLK_GATING enum
9179 */
9180
9181typedef enum DSI_CLK_GATING {
9182DSI_CLK_GATING_ENABLE                    = 0x00000000,
9183DSI_CLK_GATING_DISABLE                   = 0x00000001,
9184} DSI_CLK_GATING;
9185
9186/*
9187 * DSI_LANE_ULPS_REQUEST enum
9188 */
9189
9190typedef enum DSI_LANE_ULPS_REQUEST {
9191DSI_LANE_ULPS_REQUEST_DEASSERT           = 0x00000000,
9192DSI_LANE_ULPS_REQUEST_ASSERT             = 0x00000001,
9193} DSI_LANE_ULPS_REQUEST;
9194
9195/*
9196 * DSI_LANE_ULPS_EXIT enum
9197 */
9198
9199typedef enum DSI_LANE_ULPS_EXIT {
9200DSI_LANE_ULPS_EXIT_DEASSERT              = 0x00000000,
9201DSI_LANE_ULPS_EXIT_ASSERT                = 0x00000001,
9202} DSI_LANE_ULPS_EXIT;
9203
9204/*
9205 * DSI_LANE_FORCE_TX_STOP enum
9206 */
9207
9208typedef enum DSI_LANE_FORCE_TX_STOP {
9209DSI_LANE_FORCE_TX_STOP_DEASSERT          = 0x00000000,
9210DSI_LANE_FORCE_TX_STOP_ASSERT            = 0x00000001,
9211} DSI_LANE_FORCE_TX_STOP;
9212
9213/*
9214 * DSI_CLOCK_LANE_HS_FORCE_REQUEST enum
9215 */
9216
9217typedef enum DSI_CLOCK_LANE_HS_FORCE_REQUEST {
9218DSI_CLOCK_LANE_HS_FORCE_REQUEST_DEASSERT  = 0x00000000,
9219DSI_CLOCK_LANE_HS_FORCE_REQUEST_ASSERT   = 0x00000001,
9220} DSI_CLOCK_LANE_HS_FORCE_REQUEST;
9221
9222/*
9223 * DSI_CONTROLLER_EN enum
9224 */
9225
9226typedef enum DSI_CONTROLLER_EN {
9227DSI_CONTROLLER_DISABLE                   = 0x00000000,
9228DSI_CONTROLLER_ENABLE                    = 0x00000001,
9229} DSI_CONTROLLER_EN;
9230
9231/*
9232 * DSI_VIDEO_MODE_EN enum
9233 */
9234
9235typedef enum DSI_VIDEO_MODE_EN {
9236DSI_VIDEO_MODE_DISABLE                   = 0x00000000,
9237DSI_VIDEO_MODE_ENABLE                    = 0x00000001,
9238} DSI_VIDEO_MODE_EN;
9239
9240/*
9241 * DSI_CMD_MODE_EN enum
9242 */
9243
9244typedef enum DSI_CMD_MODE_EN {
9245DSI_CMD_MODE_DISABLE                     = 0x00000000,
9246DSI_CMD_MODE_ENABLE                      = 0x00000001,
9247} DSI_CMD_MODE_EN;
9248
9249/*
9250 * DSI_DATA_LANE0_EN enum
9251 */
9252
9253typedef enum DSI_DATA_LANE0_EN {
9254DSI_DATA_LANE0_DISABLE                   = 0x00000000,
9255DSI_DATA_LANE0_ENABLE                    = 0x00000001,
9256} DSI_DATA_LANE0_EN;
9257
9258/*
9259 * DSI_DATA_LANE1_EN enum
9260 */
9261
9262typedef enum DSI_DATA_LANE1_EN {
9263DSI_DATA_LANE1_DISABLE                   = 0x00000000,
9264DSI_DATA_LANE1_ENABLE                    = 0x00000001,
9265} DSI_DATA_LANE1_EN;
9266
9267/*
9268 * DSI_DATA_LANE2_EN enum
9269 */
9270
9271typedef enum DSI_DATA_LANE2_EN {
9272DSI_DATA_LANE2_DISABLE                   = 0x00000000,
9273DSI_DATA_LANE2_ENABLE                    = 0x00000001,
9274} DSI_DATA_LANE2_EN;
9275
9276/*
9277 * DSI_DATA_LANE3_EN enum
9278 */
9279
9280typedef enum DSI_DATA_LANE3_EN {
9281DSI_DATA_LANE3_DISABLE                   = 0x00000000,
9282DSI_DATA_LANE3_ENABLE                    = 0x00000001,
9283} DSI_DATA_LANE3_EN;
9284
9285/*
9286 * DSI_CLOCK_LANE_EN enum
9287 */
9288
9289typedef enum DSI_CLOCK_LANE_EN {
9290DSI_CLOCK_LANE_DISABLE                   = 0x00000000,
9291DSI_CLOCK_LANE_ENABLE                    = 0x00000001,
9292} DSI_CLOCK_LANE_EN;
9293
9294/*
9295 * DSI_PHY_DATA_LANE0_EN enum
9296 */
9297
9298typedef enum DSI_PHY_DATA_LANE0_EN {
9299DSI_PHY_DATA_LANE0_DISABLE               = 0x00000000,
9300DSI_PHY_DATA_LANE0_ENABLE                = 0x00000001,
9301} DSI_PHY_DATA_LANE0_EN;
9302
9303/*
9304 * DSI_PHY_DATA_LANE1_EN enum
9305 */
9306
9307typedef enum DSI_PHY_DATA_LANE1_EN {
9308DSI_PHY_DATA_LANE1_DISABLE               = 0x00000000,
9309DSI_PHY_DATA_LANE1_ENABLE                = 0x00000001,
9310} DSI_PHY_DATA_LANE1_EN;
9311
9312/*
9313 * DSI_PHY_DATA_LANE2_EN enum
9314 */
9315
9316typedef enum DSI_PHY_DATA_LANE2_EN {
9317DSI_PHY_DATA_LANE2_DISABLE               = 0x00000000,
9318DSI_PHY_DATA_LANE2_ENABLE                = 0x00000001,
9319} DSI_PHY_DATA_LANE2_EN;
9320
9321/*
9322 * DSI_PHY_DATA_LANE3_EN enum
9323 */
9324
9325typedef enum DSI_PHY_DATA_LANE3_EN {
9326DSI_PHY_DATA_LANE3_DISABLE               = 0x00000000,
9327DSI_PHY_DATA_LANE3_ENABLE                = 0x00000001,
9328} DSI_PHY_DATA_LANE3_EN;
9329
9330/*
9331 * DSI_RESET_DISPCLK enum
9332 */
9333
9334typedef enum DSI_RESET_DISPCLK {
9335DSI_NO_RESET_ON_DISPCLK_DOMAIN_LOGIC     = 0x00000000,
9336DSI_RESET_ON_DISPCLK_DOMAIN_LOGIC        = 0x00000001,
9337} DSI_RESET_DISPCLK;
9338
9339/*
9340 * DSI_RESET_DSICLK enum
9341 */
9342
9343typedef enum DSI_RESET_DSICLK {
9344DSI_NO_RESET_ON_DSICLK_DOMAIN_LOGIC      = 0x00000000,
9345DSI_RESET_ON_DSICLK_DOMAIN_LOGIC         = 0x00000001,
9346} DSI_RESET_DSICLK;
9347
9348/*
9349 * DSI_RESET_BYTECLK enum
9350 */
9351
9352typedef enum DSI_RESET_BYTECLK {
9353DSI_NO_RESET_ON_BYTECLK_DOMAIN_LOGIC     = 0x00000000,
9354DSI_RESET_ON_BYTECLK_DOMAIN_LOGIC        = 0x00000001,
9355} DSI_RESET_BYTECLK;
9356
9357/*
9358 * DSI_RESET_ESCCLK enum
9359 */
9360
9361typedef enum DSI_RESET_ESCCLK {
9362DSI_NO_RESET_ON_ESCCLK_DOMAIN_LOGIC      = 0x00000000,
9363DSI_RESET_ON_ESCCLK_DOMAIN_LOGIC         = 0x00000001,
9364} DSI_RESET_ESCCLK;
9365
9366/*
9367 * DSI_CRTC_SEL enum
9368 */
9369
9370typedef enum DSI_CRTC_SEL {
9371DSI_GET_PIXEL_STREAM_FROM_FMT0           = 0x00000000,
9372DSI_GET_PIXEL_STREAM_FROM_FMT1           = 0x00000001,
9373DSI_GET_PIXEL_STREAM_FROM_FMT2           = 0x00000002,
9374DSI_GET_PIXEL_STREAM_FROM_FMT3           = 0x00000003,
9375DSI_GET_PIXEL_STREAM_FROM_FMT4           = 0x00000004,
9376DSI_GET_PIXEL_STREAM_FROM_FMT5           = 0x00000005,
9377} DSI_CRTC_SEL;
9378
9379/*
9380 * DSI_PACKET_BYTE_MSB_LSB_FLIP enum
9381 */
9382
9383typedef enum DSI_PACKET_BYTE_MSB_LSB_FLIP {
9384DSI_PACKET_BYTE_MSB_LSB_FLIP_NO_SWAP     = 0x00000000,
9385DSI_PACKET_BYTE_MSB_LSB_FLIP_SWAP        = 0x00000001,
9386} DSI_PACKET_BYTE_MSB_LSB_FLIP;
9387
9388/*
9389 * DSI_VIDEO_MODE_DST_FORMAT enum
9390 */
9391
9392typedef enum DSI_VIDEO_MODE_DST_FORMAT {
9393DSI_VIDEO_DST_FORMAT_RGB565              = 0x00000000,
9394DSI_VIDEO_DST_FORMAT_RGB666_PACKED       = 0x00000001,
9395DSI_VIDEO_DST_FORMAT_RGB666_LOOSELY_PACKED = 0x00000002,
9396DSI_VIDEO_DST_FORMAT_RGB888              = 0x00000003,
9397} DSI_VIDEO_MODE_DST_FORMAT;
9398
9399/*
9400 * DSI_VIDEO_TRAFFIC_MODE enum
9401 */
9402
9403typedef enum DSI_VIDEO_TRAFFIC_MODE {
9404DSI_TRAFFIC_MODE_SYNC_PULSES             = 0x00000000,
9405DSI_TRAFFIC_MODE_SYNC_EVENTS             = 0x00000001,
9406DSI_TRAFFIC_MODE_BURST                   = 0x00000002,
9407DSI_TRAFFIC_MODE_RESERVED                = 0x00000003,
9408} DSI_VIDEO_TRAFFIC_MODE;
9409
9410/*
9411 * DSI_VIDEO_BLLP_PWR_MODE enum
9412 */
9413
9414typedef enum DSI_VIDEO_BLLP_PWR_MODE {
9415DSI_VIDEO_BLLP_PWR_MODE_HS               = 0x00000000,
9416DSI_VIDEO_BLLP_PWR_MODE_LP               = 0x00000001,
9417} DSI_VIDEO_BLLP_PWR_MODE;
9418
9419/*
9420 * DSI_VIDEO_EOF_BLLP_PWR_MODE enum
9421 */
9422
9423typedef enum DSI_VIDEO_EOF_BLLP_PWR_MODE {
9424DSI_VIDEO_EOF_BLLP_PWR_MODE_HS           = 0x00000000,
9425DSI_VIDEO_EOF_BLLP_PWR_MODE_LP           = 0x00000001,
9426} DSI_VIDEO_EOF_BLLP_PWR_MODE;
9427
9428/*
9429 * DSI_VIDEO_PWR_MODE enum
9430 */
9431
9432typedef enum DSI_VIDEO_PWR_MODE {
9433DSI_VIDEO_PWR_MODE_HS                    = 0x00000000,
9434DSI_VIDEO_PWR_MODE_LP                    = 0x00000001,
9435} DSI_VIDEO_PWR_MODE;
9436
9437/*
9438 * DSI_VIDEO_PULSE_MODE_OPT enum
9439 */
9440
9441typedef enum DSI_VIDEO_PULSE_MODE_OPT {
9442PULSE_MODE_OPT_NO_HSA                    = 0x00000000,
9443PULSE_MODE_OPT_SEND                      = 0x00000001,
9444} DSI_VIDEO_PULSE_MODE_OPT;
9445
9446/*
9447 * DSI_RGB_SWAP enum
9448 */
9449
9450typedef enum DSI_RGB_SWAP {
9451DSI_SWAP_RGB                             = 0x00000000,
9452DSI_SWAP_RBG                             = 0x00000001,
9453DSI_SWAP_BGR                             = 0x00000002,
9454DSI_SWAP_BRG                             = 0x00000003,
9455DSI_SWAP_GRB                             = 0x00000004,
9456DSI_SWAP_GBR                             = 0x00000005,
9457} DSI_RGB_SWAP;
9458
9459/*
9460 * DSI_CMD_PACKET_TYPE enum
9461 */
9462
9463typedef enum DSI_CMD_PACKET_TYPE {
9464DSI_CMD_PACKET_TYPE_SHORT                = 0x00000000,
9465DSI_CMD_PACKET_TYPE_LONG                 = 0x00000001,
9466} DSI_CMD_PACKET_TYPE;
9467
9468/*
9469 * DSI_CMD_PWR_MODE enum
9470 */
9471
9472typedef enum DSI_CMD_PWR_MODE {
9473DSI_CMD_PWR_MODE_HS                      = 0x00000000,
9474DSI_CMD_PWR_MODE_LP                      = 0x00000001,
9475} DSI_CMD_PWR_MODE;
9476
9477/*
9478 * DSI_CMD_EMBEDDED_MODE enum
9479 */
9480
9481typedef enum DSI_CMD_EMBEDDED_MODE {
9482CMD_EMBEDDED_MODE_DISABLE                = 0x00000000,
9483CMD_EMBEDDED_MODE_ENABLE                 = 0x00000001,
9484} DSI_CMD_EMBEDDED_MODE;
9485
9486/*
9487 * DSI_CMD_ORDER enum
9488 */
9489
9490typedef enum DSI_CMD_ORDER {
9491DSI_CMD_ORDER_COMMAND_FIRST              = 0x00000000,
9492DSI_CMD_ORDER_DATA_FIRST                 = 0x00000001,
9493} DSI_CMD_ORDER;
9494
9495/*
9496 * DSI_DATA_BUFFER_ID enum
9497 */
9498
9499typedef enum DSI_DATA_BUFFER_ID {
9500DSI_DATA_BUFFER_OFFSET0                  = 0x00000000,
9501DSI_DATA_BUFFER_OFFSET1                  = 0x00000001,
9502} DSI_DATA_BUFFER_ID;
9503
9504/*
9505 * DSI_DWORD_BYTE_SWAP enum
9506 */
9507
9508typedef enum DSI_DWORD_BYTE_SWAP {
9509DWORD_BYTE_SWAP_NO_SWAP                  = 0x00000000,
9510DWORD_BYTE_SWAP_BYTE_SWAP                = 0x00000001,
9511DWORD_BYTE_SWAP_WORD_SWAP                = 0x00000002,
9512DWORD_BYTE_SWAP_BOTH_SWAP                = 0x00000003,
9513} DSI_DWORD_BYTE_SWAP;
9514
9515/*
9516 * DSI_INSERT_DCS_COMMAND enum
9517 */
9518
9519typedef enum DSI_INSERT_DCS_COMMAND {
9520DSI_INSERT_DCS_COMMAND_DISABLE           = 0x00000000,
9521DSI_INSERT_DCS_COMMAND_ENABLE            = 0x00000001,
9522} DSI_INSERT_DCS_COMMAND;
9523
9524/*
9525 * DSI_DMAFIFO_WRITE_WATERMARK enum
9526 */
9527
9528typedef enum DSI_DMAFIFO_WRITE_WATERMARK {
9529DSI_DMAFIFO_WRITE_WATERMARK_HALF         = 0x00000000,
9530DSI_DMAFIFO_WRITE_WATERMARK_FOURTH       = 0x00000001,
9531DSI_DMAFIFO_WRITE_WATERMARK_EIGHTH       = 0x00000002,
9532DSI_DMAFIFO_WRITE_WATERMARK_SIXTEENTH    = 0x00000003,
9533} DSI_DMAFIFO_WRITE_WATERMARK;
9534
9535/*
9536 * DSI_DMAFIFO_READ_WATERMARK enum
9537 */
9538
9539typedef enum DSI_DMAFIFO_READ_WATERMARK {
9540DSI_DMAFIFO_READ_WATERMARK_HALF          = 0x00000000,
9541DSI_DMAFIFO_READ_WATERMARK_FOURTH        = 0x00000001,
9542DSI_DMAFIFO_READ_WATERMARK_EIGHTH        = 0x00000002,
9543DSI_DMAFIFO_READ_WATERMARK_SIXTEENTH     = 0x00000003,
9544} DSI_DMAFIFO_READ_WATERMARK;
9545
9546/*
9547 * DSI_USE_DENG_LENGTH enum
9548 */
9549
9550typedef enum DSI_USE_DENG_LENGTH {
9551DSI_USE_DENG_LENGTH_DISABLE              = 0x00000000,
9552DSI_USE_DENG_LENGTH_ENABLE               = 0x00000001,
9553} DSI_USE_DENG_LENGTH;
9554
9555/*
9556 * DSI_COMMAND_TRIGGER_MODE enum
9557 */
9558
9559typedef enum DSI_COMMAND_TRIGGER_MODE {
9560DSI_COMMAND_TRIGGER_MODE_AUTO            = 0x00000000,
9561DSI_COMMAND_TRIGGER_MODE_MANUAL          = 0x00000001,
9562} DSI_COMMAND_TRIGGER_MODE;
9563
9564/*
9565 * DSI_COMMAND_TRIGGER_SEL enum
9566 */
9567
9568typedef enum DSI_COMMAND_TRIGGER_SEL {
9569DSI_COMMAND_TRIGGER_SEL_NONE             = 0x00000000,
9570DSI_COMMAND_TRIGGER_SEL_CRTC             = 0x00000001,
9571DSI_COMMAND_TRIGGER_SEL_TE               = 0x00000002,
9572DSI_COMMAND_TRIGGER_SEL_HW               = 0x00000003,
9573} DSI_COMMAND_TRIGGER_SEL;
9574
9575/*
9576 * DSI_HW_SOURCE_SEL enum
9577 */
9578
9579typedef enum DSI_HW_SOURCE_SEL {
9580HW_SOURCE_SEL_NONE                       = 0x00000000,
9581HW_SOURCE_SEL_DSC_VUP                    = 0x00000001,
9582HW_SOURCE_SEL_DSC_VLP                    = 0x00000002,
9583HW_SOURCE_SEL_DSC_JPEG                   = 0x00000003,
9584} DSI_HW_SOURCE_SEL;
9585
9586/*
9587 * DSI_COMMAND_TRIGGER_ORDER enum
9588 */
9589
9590typedef enum DSI_COMMAND_TRIGGER_ORDER {
9591DSI_COMMAND_TRIGGER_ORDER_DMA            = 0x00000000,
9592DSI_COMMAND_TRIGGER_ORDER_DENG           = 0x00000001,
9593} DSI_COMMAND_TRIGGER_ORDER;
9594
9595/*
9596 * DSI_TE_SRC_SEL enum
9597 */
9598
9599typedef enum DSI_TE_SRC_SEL {
9600DSI_TE_SEL_LINK                          = 0x00000000,
9601DSI_TE_SEL_PIN                           = 0x00000001,
9602} DSI_TE_SRC_SEL;
9603
9604/*
9605 * DSI_EXT_TE_MUX enum
9606 */
9607
9608typedef enum DSI_EXT_TE_MUX {
9609DSI_XT_TE_MUX_LCDD17                     = 0x00000000,
9610DSI_XT_TE_MUX_DCLK                       = 0x00000001,
9611DSI_XT_TE_MUX_SS                         = 0x00000002,
9612DSI_XT_TE_MUX_GCLK                       = 0x00000003,
9613DSI_XT_TE_MUX_GOE                        = 0x00000004,
9614DSI_XT_TE_MUX_DINV                       = 0x00000005,
9615DSI_XT_TE_MUX_FRAME                      = 0x00000006,
9616DSI_XT_TE_MUX_GPIO4                      = 0x00000007,
9617DSI_XT_TE_MUX_GPIO5                      = 0x00000008,
9618} DSI_EXT_TE_MUX;
9619
9620/*
9621 * DSI_EXT_TE_MODE enum
9622 */
9623
9624typedef enum DSI_EXT_TE_MODE {
9625DSI_EXT_TE_MODE_VSYNC_EDGE               = 0x00000000,
9626DSI_EXT_TE_MODE_VSYNC_WIDTH              = 0x00000001,
9627DSI_EXT_TE_MODE_HVSYNC_EDGE              = 0x00000002,
9628DSI_EXT_TE_MODE_HVSYNC_WIDTH             = 0x00000003,
9629} DSI_EXT_TE_MODE;
9630
9631/*
9632 * DSI_EXT_RESET_POL enum
9633 */
9634
9635typedef enum DSI_EXT_RESET_POL {
9636DSI_EXT_RESET_POL_HIGH                   = 0x00000000,
9637DSI_EXT_RESET_POL_LOW                    = 0x00000001,
9638} DSI_EXT_RESET_POL;
9639
9640/*
9641 * DSI_EXT_TE_POL enum
9642 */
9643
9644typedef enum DSI_EXT_TE_POL {
9645DSI_EXT_TE_POL_RISING                    = 0x00000000,
9646DSI_EXT_TE_POL_FALLING                   = 0x00000001,
9647} DSI_EXT_TE_POL;
9648
9649/*
9650 * DSI_RESET_PANEL enum
9651 */
9652
9653typedef enum DSI_RESET_PANEL {
9654DSI_RESET_PANEL_DEASSERT                 = 0x00000000,
9655DSI_RESET_PANEL_ASSERT                   = 0x00000001,
9656} DSI_RESET_PANEL;
9657
9658/*
9659 * DSI_CRC_ENABLE enum
9660 */
9661
9662typedef enum DSI_CRC_ENABLE {
9663DSI_CRC_CAL_DISABLE                      = 0x00000000,
9664DSI_CRC_CAL_ENABLE                       = 0x00000001,
9665} DSI_CRC_ENABLE;
9666
9667/*
9668 * DSI_TX_EOT_APPEND enum
9669 */
9670
9671typedef enum DSI_TX_EOT_APPEND {
9672DSI_TX_EOT_APPEND_DISABLE                = 0x00000000,
9673DSI_TX_EOT_APPEND_ENABLE                 = 0x00000001,
9674} DSI_TX_EOT_APPEND;
9675
9676/*
9677 * DSI_RX_EOT_IGNORE enum
9678 */
9679
9680typedef enum DSI_RX_EOT_IGNORE {
9681DSI_RX_EOT_IGNORE_DISABLE                = 0x00000000,
9682DSI_RX_EOT_IGNORE_ENABLE                 = 0x00000001,
9683} DSI_RX_EOT_IGNORE;
9684
9685/*
9686 * DSI_MIPI_BIST_RESET enum
9687 */
9688
9689typedef enum DSI_MIPI_BIST_RESET {
9690DSI_MIPI_BIST_RESET_DEASSERT             = 0x00000000,
9691DSI_MIPI_BIST_RESET_ASSERT               = 0x00000001,
9692} DSI_MIPI_BIST_RESET;
9693
9694/*
9695 * DSI_MIPI_BIST_VIDEO_FRMT enum
9696 */
9697
9698typedef enum DSI_MIPI_BIST_VIDEO_FRMT {
9699DSI_MIPI_BIST_VIDEO_FRMT_YUV422          = 0x00000000,
9700DSI_MIPI_BIST_VIDEO_FRMT_RAW8            = 0x00000001,
9701} DSI_MIPI_BIST_VIDEO_FRMT;
9702
9703/*
9704 * DSI_MIPI_BIST_START enum
9705 */
9706
9707typedef enum DSI_MIPI_BIST_START {
9708DSI_MIPI_BIST_START_DEASSERT             = 0x00000000,
9709DSI_MIPI_BIST_START_ASSERT               = 0x00000001,
9710} DSI_MIPI_BIST_START;
9711
9712/*
9713 * DSI_DBG_CLK_SEL enum
9714 */
9715
9716typedef enum DSI_DBG_CLK_SEL {
9717DSI_TEST_CLK_SEL_DISPCLK_P               = 0x00000000,
9718DSI_TEST_CLK_SEL_DISPCLK_G               = 0x00000001,
9719DSI_TEST_CLK_SEL_DISPCLK_R               = 0x00000002,
9720DSI_TEST_CLK_SEL_ESCCLK_G                = 0x00000003,
9721DSI_TEST_CLK_SEL_BYTECLK_G               = 0x00000004,
9722DSI_TEST_CLK_SEL_DSICLK_P                = 0x00000005,
9723DSI_TEST_CLK_SEL_DSICLK_R                = 0x00000006,
9724DSI_TEST_CLK_SEL_DSICLK_G                = 0x00000007,
9725DSI_TEST_CLK_SEL_DSICLK_TRN              = 0x00000008,
9726} DSI_DBG_CLK_SEL;
9727
9728/*
9729 * DSI_DENG_FIFO_USE_OVERWRITE_LEVEL enum
9730 */
9731
9732typedef enum DSI_DENG_FIFO_USE_OVERWRITE_LEVEL {
9733DSI_DENG_FIFO_LEVEL_OVERWRITE            = 0x00000000,
9734DSI_DENG_FIFO_LEVEL_CAL_AVERAGE          = 0x00000001,
9735} DSI_DENG_FIFO_USE_OVERWRITE_LEVEL;
9736
9737/*
9738 * DSI_DENG_FIFO_FORCE_RECAL_AVERAGE enum
9739 */
9740
9741typedef enum DSI_DENG_FIFO_FORCE_RECAL_AVERAGE {
9742DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_DEASSERT  = 0x00000000,
9743DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_ASSERT  = 0x00000001,
9744} DSI_DENG_FIFO_FORCE_RECAL_AVERAGE;
9745
9746/*
9747 * DSI_DENG_FIFO_FORCE_RECOMP_MINMAX enum
9748 */
9749
9750typedef enum DSI_DENG_FIFO_FORCE_RECOMP_MINMAX {
9751DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_DEASSERT  = 0x00000000,
9752DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_ASSERT  = 0x00000001,
9753} DSI_DENG_FIFO_FORCE_RECOMP_MINMAX;
9754
9755/*
9756 * DSI_DENG_FIFO_START enum
9757 */
9758
9759typedef enum DSI_DENG_FIFO_START {
9760DSI_DENG_FIFO_START_DEASSERT             = 0x00000000,
9761DSI_DENG_FIFO_START_ASSERT               = 0x00000001,
9762} DSI_DENG_FIFO_START;
9763
9764/*
9765 * DSI_USE_CMDFIFO enum
9766 */
9767
9768typedef enum DSI_USE_CMDFIFO {
9769DSI_CMD_USE_DMAFIFO                      = 0x00000000,
9770DSI_CMD_USE_CMDFIFO                      = 0x00000001,
9771} DSI_USE_CMDFIFO;
9772
9773/*
9774 * DSI_CRTC_FREEZE_TRIG enum
9775 */
9776
9777typedef enum DSI_CRTC_FREEZE_TRIG {
9778DSI_CRTC_FREEZE_TRIG_DEASSERT            = 0x00000000,
9779DSI_CRTC_FREEZE_TRIG_ASSERT              = 0x00000001,
9780} DSI_CRTC_FREEZE_TRIG;
9781
9782/*
9783 * DSI_PERF_LATENCY_SEL enum
9784 */
9785
9786typedef enum DSI_PERF_LATENCY_SEL {
9787DSI_PERF_LATENCY_SEL_DATA_LANE0          = 0x00000000,
9788DSI_PERF_LATENCY_SEL_DATA_LANE1          = 0x00000001,
9789DSI_PERF_LATENCY_SEL_DATA_LANE2          = 0x00000002,
9790DSI_PERF_LATENCY_SEL_DATA_LANE3          = 0x00000003,
9791} DSI_PERF_LATENCY_SEL;
9792
9793/*
9794 * DSI_DEBUG_DSICLK_SEL enum
9795 */
9796
9797typedef enum DSI_DEBUG_DSICLK_SEL {
9798DSI_DEBUG_DSICLK_SEL_VIDEO_ENGINE        = 0x00000000,
9799DSI_DEBUG_DSICLK_SEL_CMD_ENGINE          = 0x00000001,
9800DSI_DEBUG_DSICLK_SEL_RESYNC_FIFO         = 0x00000002,
9801DSI_DEBUG_DSICLK_SEL_CMDFIFO             = 0x00000003,
9802DSI_DEBUG_DSICLK_SEL_CMDBUFFER           = 0x00000004,
9803DSI_DEBUG_DSICLK_SEL_AFIFO               = 0x00000005,
9804DSI_DEBUG_DSICLK_SEL_LANECTRL            = 0x00000006,
9805} DSI_DEBUG_DSICLK_SEL;
9806
9807/*
9808 * DSI_DEBUG_BYTECLK_SEL enum
9809 */
9810
9811typedef enum DSI_DEBUG_BYTECLK_SEL {
9812DSI_DEBUG_BYTECLK_SEL_AFIFO              = 0x00000000,
9813DSI_DEBUG_BYTECLK_SEL_LANEFIFO0          = 0x00000001,
9814DSI_DEBUG_BYTECLK_SEL_LANEFIFO1          = 0x00000002,
9815DSI_DEBUG_BYTECLK_SEL_LANEFIFO2          = 0x00000003,
9816DSI_DEBUG_BYTECLK_SEL_LANEFIFO3          = 0x00000004,
9817DSI_DEBUG_BYTECLK_SEL_LANEBUF0           = 0x00000005,
9818DSI_DEBUG_BYTECLK_SEL_LANEBUF1           = 0x00000006,
9819DSI_DEBUG_BYTECLK_SEL_LANEBUF2           = 0x00000007,
9820DSI_DEBUG_BYTECLK_SEL_LANEBUF3           = 0x00000008,
9821DSI_DEBUG_BYTECLK_SEL_PINGPONG0          = 0x00000009,
9822DSI_DEBUG_BYTECLK_SEL_PINGPONG1          = 0x0000000a,
9823DSI_DEBUG_BYTECLK_SEL_PINGPING2          = 0x0000000b,
9824DSI_DEBUG_BYTECLK_SEL_PINGPING3          = 0x0000000c,
9825DSI_DEBUG_BYTECLK_SEL_EOT                = 0x0000000d,
9826DSI_DEBUG_BYTECLK_SEL_LANECTRL           = 0x0000000e,
9827} DSI_DEBUG_BYTECLK_SEL;
9828
9829/*******************************************************
9830 * DCIO_CHIP Enums
9831 *******************************************************/
9832
9833/*
9834 * DCIOCHIP_HPD_SEL enum
9835 */
9836
9837typedef enum DCIOCHIP_HPD_SEL {
9838DCIOCHIP_HPD_SEL_ASYNC                   = 0x00000000,
9839DCIOCHIP_HPD_SEL_CLOCKED                 = 0x00000001,
9840} DCIOCHIP_HPD_SEL;
9841
9842/*
9843 * DCIOCHIP_PAD_MODE enum
9844 */
9845
9846typedef enum DCIOCHIP_PAD_MODE {
9847DCIOCHIP_PAD_MODE_DDC                    = 0x00000000,
9848DCIOCHIP_PAD_MODE_DP                     = 0x00000001,
9849} DCIOCHIP_PAD_MODE;
9850
9851/*
9852 * DCIOCHIP_AUXSLAVE_PAD_MODE enum
9853 */
9854
9855typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE {
9856DCIOCHIP_AUXSLAVE_PAD_MODE_I2C           = 0x00000000,
9857DCIOCHIP_AUXSLAVE_PAD_MODE_AUX           = 0x00000001,
9858} DCIOCHIP_AUXSLAVE_PAD_MODE;
9859
9860/*
9861 * DCIOCHIP_INVERT enum
9862 */
9863
9864typedef enum DCIOCHIP_INVERT {
9865DCIOCHIP_POL_NON_INVERT                  = 0x00000000,
9866DCIOCHIP_POL_INVERT                      = 0x00000001,
9867} DCIOCHIP_INVERT;
9868
9869/*
9870 * DCIOCHIP_PD_EN enum
9871 */
9872
9873typedef enum DCIOCHIP_PD_EN {
9874DCIOCHIP_PD_EN_NOTALLOW                  = 0x00000000,
9875DCIOCHIP_PD_EN_ALLOW                     = 0x00000001,
9876} DCIOCHIP_PD_EN;
9877
9878/*
9879 * DCIOCHIP_GPIO_MASK_EN enum
9880 */
9881
9882typedef enum DCIOCHIP_GPIO_MASK_EN {
9883DCIOCHIP_GPIO_MASK_EN_HARDWARE           = 0x00000000,
9884DCIOCHIP_GPIO_MASK_EN_SOFTWARE           = 0x00000001,
9885} DCIOCHIP_GPIO_MASK_EN;
9886
9887/*
9888 * DCIOCHIP_MASK enum
9889 */
9890
9891typedef enum DCIOCHIP_MASK {
9892DCIOCHIP_MASK_DISABLE                    = 0x00000000,
9893DCIOCHIP_MASK_ENABLE                     = 0x00000001,
9894} DCIOCHIP_MASK;
9895
9896/*
9897 * DCIOCHIP_GPIO_I2C_MASK enum
9898 */
9899
9900typedef enum DCIOCHIP_GPIO_I2C_MASK {
9901DCIOCHIP_GPIO_I2C_MASK_DISABLE           = 0x00000000,
9902DCIOCHIP_GPIO_I2C_MASK_ENABLE            = 0x00000001,
9903} DCIOCHIP_GPIO_I2C_MASK;
9904
9905/*
9906 * DCIOCHIP_GPIO_I2C_DRIVE enum
9907 */
9908
9909typedef enum DCIOCHIP_GPIO_I2C_DRIVE {
9910DCIOCHIP_GPIO_I2C_DRIVE_LOW              = 0x00000000,
9911DCIOCHIP_GPIO_I2C_DRIVE_HIGH             = 0x00000001,
9912} DCIOCHIP_GPIO_I2C_DRIVE;
9913
9914/*
9915 * DCIOCHIP_GPIO_I2C_EN enum
9916 */
9917
9918typedef enum DCIOCHIP_GPIO_I2C_EN {
9919DCIOCHIP_GPIO_I2C_DISABLE                = 0x00000000,
9920DCIOCHIP_GPIO_I2C_ENABLE                 = 0x00000001,
9921} DCIOCHIP_GPIO_I2C_EN;
9922
9923/*
9924 * DCIOCHIP_MASK_4BIT enum
9925 */
9926
9927typedef enum DCIOCHIP_MASK_4BIT {
9928DCIOCHIP_MASK_4BIT_DISABLE               = 0x00000000,
9929DCIOCHIP_MASK_4BIT_ENABLE                = 0x0000000f,
9930} DCIOCHIP_MASK_4BIT;
9931
9932/*
9933 * DCIOCHIP_ENABLE_4BIT enum
9934 */
9935
9936typedef enum DCIOCHIP_ENABLE_4BIT {
9937DCIOCHIP_4BIT_DISABLE                    = 0x00000000,
9938DCIOCHIP_4BIT_ENABLE                     = 0x0000000f,
9939} DCIOCHIP_ENABLE_4BIT;
9940
9941/*
9942 * DCIOCHIP_MASK_5BIT enum
9943 */
9944
9945typedef enum DCIOCHIP_MASK_5BIT {
9946DCIOCHIP_MASIK_5BIT_DISABLE              = 0x00000000,
9947DCIOCHIP_MASIK_5BIT_ENABLE               = 0x0000001f,
9948} DCIOCHIP_MASK_5BIT;
9949
9950/*
9951 * DCIOCHIP_ENABLE_5BIT enum
9952 */
9953
9954typedef enum DCIOCHIP_ENABLE_5BIT {
9955DCIOCHIP_5BIT_DISABLE                    = 0x00000000,
9956DCIOCHIP_5BIT_ENABLE                     = 0x0000001f,
9957} DCIOCHIP_ENABLE_5BIT;
9958
9959/*
9960 * DCIOCHIP_MASK_2BIT enum
9961 */
9962
9963typedef enum DCIOCHIP_MASK_2BIT {
9964DCIOCHIP_MASK_2BIT_DISABLE               = 0x00000000,
9965DCIOCHIP_MASK_2BIT_ENABLE                = 0x00000003,
9966} DCIOCHIP_MASK_2BIT;
9967
9968/*
9969 * DCIOCHIP_ENABLE_2BIT enum
9970 */
9971
9972typedef enum DCIOCHIP_ENABLE_2BIT {
9973DCIOCHIP_2BIT_DISABLE                    = 0x00000000,
9974DCIOCHIP_2BIT_ENABLE                     = 0x00000003,
9975} DCIOCHIP_ENABLE_2BIT;
9976
9977/*
9978 * DCIOCHIP_REF_27_SRC_SEL enum
9979 */
9980
9981typedef enum DCIOCHIP_REF_27_SRC_SEL {
9982DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER     = 0x00000000,
9983DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER  = 0x00000001,
9984DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS      = 0x00000002,
9985DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS  = 0x00000003,
9986} DCIOCHIP_REF_27_SRC_SEL;
9987
9988/*
9989 * DCIOCHIP_DVO_VREFPON enum
9990 */
9991
9992typedef enum DCIOCHIP_DVO_VREFPON {
9993DCIOCHIP_DVO_VREFPON_DISABLE             = 0x00000000,
9994DCIOCHIP_DVO_VREFPON_ENABLE              = 0x00000001,
9995} DCIOCHIP_DVO_VREFPON;
9996
9997/*
9998 * DCIOCHIP_DVO_VREFSEL enum
9999 */
10000

10001typedef enum DCIOCHIP_DVO_VREFSEL {
10002DCIOCHIP_DVO_VREFSEL_ONCHIP              = 0x00000000,
10003DCIOCHIP_DVO_VREFSEL_EXTERNAL            = 0x00000001,
10004} DCIOCHIP_DVO_VREFSEL;
10005
10006/*
10007 * DCIOCHIP_SPDIF1_IMODE enum
10008 */
10009
10010typedef enum DCIOCHIP_SPDIF1_IMODE {
10011DCIOCHIP_SPDIF1_IMODE_OE_A               = 0x00000000,
10012DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO          = 0x00000001,
10013} DCIOCHIP_SPDIF1_IMODE;
10014
10015/*
10016 * DCIOCHIP_AUX_FALLSLEWSEL enum
10017 */
10018
10019typedef enum DCIOCHIP_AUX_FALLSLEWSEL {
10020DCIOCHIP_AUX_FALLSLEWSEL_LOW             = 0x00000000,
10021DCIOCHIP_AUX_FALLSLEWSEL_HIGH0           = 0x00000001,
10022DCIOCHIP_AUX_FALLSLEWSEL_HIGH1           = 0x00000002,
10023DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH       = 0x00000003,
10024} DCIOCHIP_AUX_FALLSLEWSEL;
10025
10026/*
10027 * DCIOCHIP_AUX_SPIKESEL enum
10028 */
10029
10030typedef enum DCIOCHIP_AUX_SPIKESEL {
10031DCIOCHIP_AUX_SPIKESEL_50NS               = 0x00000000,
10032DCIOCHIP_AUX_SPIKESEL_10NS               = 0x00000001,
10033} DCIOCHIP_AUX_SPIKESEL;
10034
10035/*
10036 * DCIOCHIP_AUX_CSEL0P9 enum
10037 */
10038
10039typedef enum DCIOCHIP_AUX_CSEL0P9 {
10040DCIOCHIP_AUX_CSEL_DEC1P0                 = 0x00000000,
10041DCIOCHIP_AUX_CSEL_DEC0P9                 = 0x00000001,
10042} DCIOCHIP_AUX_CSEL0P9;
10043
10044/*
10045 * DCIOCHIP_AUX_CSEL1P1 enum
10046 */
10047
10048typedef enum DCIOCHIP_AUX_CSEL1P1 {
10049DCIOCHIP_AUX_CSEL_INC1P0                 = 0x00000000,
10050DCIOCHIP_AUX_CSEL_INC1P1                 = 0x00000001,
10051} DCIOCHIP_AUX_CSEL1P1;
10052
10053/*
10054 * DCIOCHIP_AUX_RSEL0P9 enum
10055 */
10056
10057typedef enum DCIOCHIP_AUX_RSEL0P9 {
10058DCIOCHIP_AUX_RSEL_DEC1P0                 = 0x00000000,
10059DCIOCHIP_AUX_RSEL_DEC0P9                 = 0x00000001,
10060} DCIOCHIP_AUX_RSEL0P9;
10061
10062/*
10063 * DCIOCHIP_AUX_RSEL1P1 enum
10064 */
10065
10066typedef enum DCIOCHIP_AUX_RSEL1P1 {
10067DCIOCHIP_AUX_RSEL_INC1P0                 = 0x00000000,
10068DCIOCHIP_AUX_RSEL_INC1P1                 = 0x00000001,
10069} DCIOCHIP_AUX_RSEL1P1;
10070
10071/*******************************************************
10072 * AZCONTROLLER Enums
10073 *******************************************************/
10074
10075/*
10076 * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL enum
10077 */
10078
10079typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL {
10080GENERIC_AZ_CONTROLLER_REGISTER_DISABLE   = 0x00000000,
10081GENERIC_AZ_CONTROLLER_REGISTER_ENABLE    = 0x00000001,
10082} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL;
10083
10084/*
10085 * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED enum
10086 */
10087
10088typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED {
10089GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED  = 0x00000000,
10090GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED  = 0x00000001,
10091} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED;
10092
10093/*
10094 * GENERIC_AZ_CONTROLLER_REGISTER_STATUS enum
10095 */
10096
10097typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS {
10098GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET  = 0x00000000,
10099GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET  = 0x00000001,
10100} GENERIC_AZ_CONTROLLER_REGISTER_STATUS;
10101
10102/*
10103 * GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED enum
10104 */
10105
10106typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED {
10107GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED  = 0x00000000,
10108GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED  = 0x00000001,
10109} GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED;
10110
10111/*
10112 * AZ_GLOBAL_CAPABILITIES enum
10113 */
10114
10115typedef enum AZ_GLOBAL_CAPABILITIES {
10116AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED  = 0x00000000,
10117AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED  = 0x00000001,
10118} AZ_GLOBAL_CAPABILITIES;
10119
10120/*
10121 * GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE enum
10122 */
10123
10124typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE {
10125ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE   = 0x00000000,
10126ACCEPT_UNSOLICITED_RESPONSE_ENABLE       = 0x00000001,
10127} GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE;
10128
10129/*
10130 * GLOBAL_CONTROL_FLUSH_CONTROL enum
10131 */
10132
10133typedef enum GLOBAL_CONTROL_FLUSH_CONTROL {
10134FLUSH_CONTROL_FLUSH_NOT_STARTED          = 0x00000000,
10135FLUSH_CONTROL_FLUSH_STARTED              = 0x00000001,
10136} GLOBAL_CONTROL_FLUSH_CONTROL;
10137
10138/*
10139 * GLOBAL_CONTROL_CONTROLLER_RESET enum
10140 */
10141
10142typedef enum GLOBAL_CONTROL_CONTROLLER_RESET {
10143CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET  = 0x00000000,
10144CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET  = 0x00000001,
10145} GLOBAL_CONTROL_CONTROLLER_RESET;
10146
10147/*
10148 * AZ_STATE_CHANGE_STATUS enum
10149 */
10150
10151typedef enum AZ_STATE_CHANGE_STATUS {
10152AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT  = 0x00000000,
10153AZ_STATE_CHANGE_STATUS_CODEC_PRESENT     = 0x00000001,
10154} AZ_STATE_CHANGE_STATUS;
10155
10156/*
10157 * GLOBAL_STATUS_FLUSH_STATUS enum
10158 */
10159
10160typedef enum GLOBAL_STATUS_FLUSH_STATUS {
10161GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED  = 0x00000000,
10162GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED   = 0x00000001,
10163} GLOBAL_STATUS_FLUSH_STATUS;
10164
10165/*
10166 * STREAM_0_SYNCHRONIZATION enum
10167 */
10168
10169typedef enum STREAM_0_SYNCHRONIZATION {
10170STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED  = 0x00000000,
10171STREAM_0_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
10172} STREAM_0_SYNCHRONIZATION;
10173
10174/*
10175 * STREAM_1_SYNCHRONIZATION enum
10176 */
10177
10178typedef enum STREAM_1_SYNCHRONIZATION {
10179STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED  = 0x00000000,
10180STREAM_1_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
10181} STREAM_1_SYNCHRONIZATION;
10182
10183/*
10184 * STREAM_2_SYNCHRONIZATION enum
10185 */
10186
10187typedef enum STREAM_2_SYNCHRONIZATION {
10188STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED  = 0x00000000,
10189STREAM_2_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
10190} STREAM_2_SYNCHRONIZATION;
10191
10192/*
10193 * STREAM_3_SYNCHRONIZATION enum
10194 */
10195
10196typedef enum STREAM_3_SYNCHRONIZATION {
10197STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED  = 0x00000000,
10198STREAM_3_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
10199} STREAM_3_SYNCHRONIZATION;
10200
10201/*
10202 * STREAM_4_SYNCHRONIZATION enum
10203 */
10204
10205typedef enum STREAM_4_SYNCHRONIZATION {
10206STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED  = 0x00000000,
10207STREAM_4_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
10208} STREAM_4_SYNCHRONIZATION;
10209
10210/*
10211 * STREAM_5_SYNCHRONIZATION enum
10212 */
10213
10214typedef enum STREAM_5_SYNCHRONIZATION {
10215STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED  = 0x00000000,
10216STREAM_5_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
10217} STREAM_5_SYNCHRONIZATION;
10218
10219/*
10220 * STREAM_6_SYNCHRONIZATION enum
10221 */
10222
10223typedef enum STREAM_6_SYNCHRONIZATION {
10224STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
10225STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
10226} STREAM_6_SYNCHRONIZATION;
10227
10228/*
10229 * STREAM_7_SYNCHRONIZATION enum
10230 */
10231
10232typedef enum STREAM_7_SYNCHRONIZATION {
10233STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
10234STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
10235} STREAM_7_SYNCHRONIZATION;
10236
10237/*
10238 * STREAM_8_SYNCHRONIZATION enum
10239 */
10240
10241typedef enum STREAM_8_SYNCHRONIZATION {
10242STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
10243STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
10244} STREAM_8_SYNCHRONIZATION;
10245
10246/*
10247 * STREAM_9_SYNCHRONIZATION enum
10248 */
10249
10250typedef enum STREAM_9_SYNCHRONIZATION {
10251STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
10252STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
10253} STREAM_9_SYNCHRONIZATION;
10254
10255/*
10256 * STREAM_10_SYNCHRONIZATION enum
10257 */
10258
10259typedef enum STREAM_10_SYNCHRONIZATION {
10260STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
10261STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
10262} STREAM_10_SYNCHRONIZATION;
10263
10264/*
10265 * STREAM_11_SYNCHRONIZATION enum
10266 */
10267
10268typedef enum STREAM_11_SYNCHRONIZATION {
10269STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
10270STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
10271} STREAM_11_SYNCHRONIZATION;
10272
10273/*
10274 * STREAM_12_SYNCHRONIZATION enum
10275 */
10276
10277typedef enum STREAM_12_SYNCHRONIZATION {
10278STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
10279STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
10280} STREAM_12_SYNCHRONIZATION;
10281
10282/*
10283 * STREAM_13_SYNCHRONIZATION enum
10284 */
10285
10286typedef enum STREAM_13_SYNCHRONIZATION {
10287STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
10288STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
10289} STREAM_13_SYNCHRONIZATION;
10290
10291/*
10292 * STREAM_14_SYNCHRONIZATION enum
10293 */
10294
10295typedef enum STREAM_14_SYNCHRONIZATION {
10296STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
10297STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
10298} STREAM_14_SYNCHRONIZATION;
10299
10300/*
10301 * STREAM_15_SYNCHRONIZATION enum
10302 */
10303
10304typedef enum STREAM_15_SYNCHRONIZATION {
10305STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
10306STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
10307} STREAM_15_SYNCHRONIZATION;
10308
10309/*
10310 * CORB_READ_POINTER_RESET enum
10311 */
10312
10313typedef enum CORB_READ_POINTER_RESET {
10314CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET  = 0x00000000,
10315CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET  = 0x00000001,
10316} CORB_READ_POINTER_RESET;
10317
10318/*
10319 * AZ_CORB_SIZE enum
10320 */
10321
10322typedef enum AZ_CORB_SIZE {
10323AZ_CORB_SIZE_2ENTRIES_RESERVED           = 0x00000000,
10324AZ_CORB_SIZE_16ENTRIES_RESERVED          = 0x00000001,
10325AZ_CORB_SIZE_256ENTRIES                  = 0x00000002,
10326AZ_CORB_SIZE_RESERVED                    = 0x00000003,
10327} AZ_CORB_SIZE;
10328
10329/*
10330 * AZ_RIRB_WRITE_POINTER_RESET enum
10331 */
10332
10333typedef enum AZ_RIRB_WRITE_POINTER_RESET {
10334AZ_RIRB_WRITE_POINTER_NOT_RESET          = 0x00000000,
10335AZ_RIRB_WRITE_POINTER_DO_RESET           = 0x00000001,
10336} AZ_RIRB_WRITE_POINTER_RESET;
10337
10338/*
10339 * RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL enum
10340 */
10341
10342typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL {
10343RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED  = 0x00000000,
10344RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED  = 0x00000001,
10345} RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL;
10346
10347/*
10348 * RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL enum
10349 */
10350
10351typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL {
10352RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED  = 0x00000000,
10353RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED  = 0x00000001,
10354} RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL;
10355
10356/*
10357 * AZ_RIRB_SIZE enum
10358 */
10359
10360typedef enum AZ_RIRB_SIZE {
10361AZ_RIRB_SIZE_2ENTRIES_RESERVED           = 0x00000000,
10362AZ_RIRB_SIZE_16ENTRIES_RESERVED          = 0x00000001,
10363AZ_RIRB_SIZE_256ENTRIES                  = 0x00000002,
10364AZ_RIRB_SIZE_UNDEFINED                   = 0x00000003,
10365} AZ_RIRB_SIZE;
10366
10367/*
10368 * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID enum
10369 */
10370
10371typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID {
10372IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID  = 0x00000000,
10373IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID  = 0x00000001,
10374} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID;
10375
10376/*
10377 * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY enum
10378 */
10379
10380typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY {
10381IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY  = 0x00000000,
10382IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY  = 0x00000001,
10383} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY;
10384
10385/*
10386 * DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE enum
10387 */
10388
10389typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE {
10390DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE  = 0x00000000,
10391DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE  = 0x00000001,
10392} DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE;
10393
10394/*******************************************************
10395 * AZENDPOINT Enums
10396 *******************************************************/
10397
10398/*
10399 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
10400 */
10401
10402typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
10403AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM  = 0x00000000,
10404AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM  = 0x00000001,
10405} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
10406
10407/*
10408 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
10409 */
10410
10411typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
10412AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ  = 0x00000000,
10413AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ  = 0x00000001,
10414} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
10415
10416/*
10417 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
10418 */
10419
10420typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
10421AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1  = 0x00000000,
10422AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2  = 0x00000001,
10423AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED  = 0x00000002,
10424AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4  = 0x00000003,
10425AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED  = 0x00000004,
10426} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
10427
10428/*
10429 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
10430 */
10431
10432typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
10433AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1  = 0x00000000,
10434AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED  = 0x00000001,
10435AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3  = 0x00000002,
10436AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED  = 0x00000003,
10437AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED  = 0x00000004,
10438AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED  = 0x00000005,
10439AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED  = 0x00000006,
10440AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED  = 0x00000007,
10441} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
10442
10443/*
10444 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
10445 */
10446
10447typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
10448AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED  = 0x00000000,
10449AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16  = 0x00000001,
10450AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20  = 0x00000002,
10451AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24  = 0x00000003,
10452AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED  = 0x00000004,
10453AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED  = 0x00000005,
10454} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
10455
10456/*
10457 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
10458 */
10459
10460typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
10461AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1  = 0x00000000,
10462AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2  = 0x00000001,
10463AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3  = 0x00000002,
10464AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4  = 0x00000003,
10465AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5  = 0x00000004,
10466AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6  = 0x00000005,
10467AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7  = 0x00000006,
10468AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8  = 0x00000007,
10469AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED  = 0x00000008,
10470} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
10471
10472/*
10473 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L enum
10474 */
10475
10476typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L {
10477AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET  = 0x00000000,
10478AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET  = 0x00000001,
10479} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L;
10480
10481/*
10482 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO enum
10483 */
10484
10485typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO {
10486AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET  = 0x00000000,
10487AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET  = 0x00000001,
10488} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO;
10489
10490/*
10491 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO enum
10492 */
10493
10494typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO {
10495AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET  = 0x00000000,
10496AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET  = 0x00000001,
10497} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO;
10498
10499/*
10500 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY enum
10501 */
10502
10503typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY {
10504AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET  = 0x00000000,
10505AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET  = 0x00000001,
10506} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY;
10507
10508/*
10509 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE enum
10510 */
10511
10512typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE {
10513AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET  = 0x00000000,
10514AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET  = 0x00000001,
10515} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE;
10516
10517/*
10518 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG enum
10519 */
10520
10521typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG {
10522AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON  = 0x00000000,
10523AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON  = 0x00000001,
10524} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG;
10525
10526/*
10527 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V enum
10528 */
10529
10530typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V {
10531AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO  = 0x00000000,
10532AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE  = 0x00000001,
10533} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V;
10534
10535/*
10536 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
10537 */
10538
10539typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
10540AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED  = 0x00000000,
10541AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED  = 0x00000001,
10542} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
10543
10544/*
10545 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE enum
10546 */
10547
10548typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE {
10549AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE  = 0x00000000,
10550AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE  = 0x00000001,
10551} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE;
10552
10553/*
10554 * AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE enum
10555 */
10556
10557typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE {
10558AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF  = 0x00000000,
10559AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN  = 0x00000001,
10560} AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE;
10561
10562/*
10563 * AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
10564 */
10565
10566typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
10567AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED  = 0x00000000,
10568AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED  = 0x00000001,
10569} AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
10570
10571/*
10572 * AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT enum
10573 */
10574
10575typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT {
10576AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED  = 0x00000000,
10577AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN  = 0x00000001,
10578} AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT;
10579
10580/*
10581 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE enum
10582 */
10583
10584typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE {
10585AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED  = 0x00000000,
10586AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED  = 0x00000001,
10587} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE;
10588
10589/*
10590 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE enum
10591 */
10592
10593typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE {
10594AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED  = 0x00000000,
10595AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED  = 0x00000001,
10596} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE;
10597
10598/*
10599 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE enum
10600 */
10601
10602typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE {
10603AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED  = 0x00000000,
10604AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED  = 0x00000001,
10605} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE;
10606
10607/*
10608 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE enum
10609 */
10610
10611typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE {
10612AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED  = 0x00000000,
10613AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED  = 0x00000001,
10614} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE;
10615
10616/*
10617 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
10618 */
10619
10620typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
10621AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED  = 0x00000000,
10622AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED  = 0x00000001,
10623} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
10624
10625/*
10626 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
10627 */
10628
10629typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
10630AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED  = 0x00000000,
10631AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED  = 0x00000001,
10632} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
10633
10634/*
10635 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
10636 */
10637
10638typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
10639AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED  = 0x00000000,
10640AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED  = 0x00000001,
10641} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
10642
10643/*
10644 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
10645 */
10646
10647typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
10648AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED  = 0x00000000,
10649AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED  = 0x00000001,
10650} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
10651
10652/*
10653 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
10654 */
10655
10656typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
10657AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE  = 0x00000000,
10658AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE  = 0x00000001,
10659} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
10660
10661/*******************************************************
10662 * AZF0CONTROLLER Enums
10663 *******************************************************/
10664
10665/*
10666 * AZALIA_SOFT_RESET_REFCLK_SOFT_RESET enum
10667 */
10668
10669typedef enum AZALIA_SOFT_RESET_REFCLK_SOFT_RESET {
10670AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET  = 0x00000000,
10671AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC  = 0x00000001,
10672} AZALIA_SOFT_RESET_REFCLK_SOFT_RESET;
10673
10674/*******************************************************
10675 * AZF0ROOT Enums
10676 *******************************************************/
10677
10678/*
10679 * CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY enum
10680 */
10681
10682typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY {
10683CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL  = 0x00000000,
10684CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6  = 0x00000001,
10685CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5  = 0x00000002,
10686CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4  = 0x00000003,
10687CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3  = 0x00000004,
10688CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2  = 0x00000005,
10689CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1  = 0x00000006,
10690CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0  = 0x00000007,
10691} CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY;
10692
10693/*
10694 * CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY enum
10695 */
10696
10697typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY {
10698CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL  = 0x00000000,
10699CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6  = 0x00000001,
10700CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5  = 0x00000002,
10701CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4  = 0x00000003,
10702CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3  = 0x00000004,
10703CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2  = 0x00000005,
10704CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1  = 0x00000006,
10705CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0  = 0x00000007,
10706} CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY;
10707
10708/*******************************************************
10709 * AZINPUTENDPOINT Enums
10710 *******************************************************/
10711
10712/*
10713 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
10714 */
10715
10716typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
10717AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM  = 0x00000000,
10718AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM  = 0x00000001,
10719} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
10720
10721/*
10722 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
10723 */
10724
10725typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
10726AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ  = 0x00000000,
10727AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ  = 0x00000001,
10728} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
10729
10730/*
10731 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
10732 */
10733
10734typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
10735AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1  = 0x00000000,
10736AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2  = 0x00000001,
10737AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED  = 0x00000002,
10738AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4  = 0x00000003,
10739AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED  = 0x00000004,
10740} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
10741
10742/*
10743 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
10744 */
10745
10746typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
10747AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1  = 0x00000000,
10748AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED  = 0x00000001,
10749AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3  = 0x00000002,
10750AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED  = 0x00000003,
10751AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED  = 0x00000004,
10752AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED  = 0x00000005,
10753AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED  = 0x00000006,
10754AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED  = 0x00000007,
10755} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
10756
10757/*
10758 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
10759 */
10760
10761typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
10762AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED  = 0x00000000,
10763AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16  = 0x00000001,
10764AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20  = 0x00000002,
10765AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24  = 0x00000003,
10766AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED  = 0x00000004,
10767AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED  = 0x00000005,
10768} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
10769
10770/*
10771 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
10772 */
10773
10774typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
10775AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1  = 0x00000000,
10776AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2  = 0x00000001,
10777AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3  = 0x00000002,
10778AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4  = 0x00000003,
10779AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5  = 0x00000004,
10780AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6  = 0x00000005,
10781AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7  = 0x00000006,
10782AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8  = 0x00000007,
10783AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED  = 0x00000008,
10784} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
10785
10786/*
10787 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
10788 */
10789
10790typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
10791AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED  = 0x00000000,
10792AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED  = 0x00000001,
10793} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
10794
10795/*
10796 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE enum
10797 */
10798
10799typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE {
10800AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF  = 0x00000000,
10801AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN  = 0x00000001,
10802} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE;
10803
10804/*
10805 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
10806 */
10807
10808typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
10809AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED  = 0x00000000,
10810AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED  = 0x00000001,
10811} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
10812
10813/*
10814 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE enum
10815 */
10816
10817typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE {
10818AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED  = 0x00000000,
10819AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED  = 0x00000001,
10820} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE;
10821
10822/*
10823 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
10824 */
10825
10826typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
10827AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED  = 0x00000000,
10828AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED  = 0x00000001,
10829} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
10830
10831/*
10832 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE enum
10833 */
10834
10835typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE {
10836AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED  = 0x00000000,
10837AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED  = 0x00000001,
10838} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE;
10839
10840/*
10841 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
10842 */
10843
10844typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
10845AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED  = 0x00000000,
10846AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED  = 0x00000001,
10847} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
10848
10849/*
10850 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE enum
10851 */
10852
10853typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE {
10854AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED  = 0x00000000,
10855AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED  = 0x00000001,
10856} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE;
10857
10858/*
10859 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
10860 */
10861
10862typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
10863AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED  = 0x00000000,
10864AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED  = 0x00000001,
10865} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
10866
10867/*
10868 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE enum
10869 */
10870
10871typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE {
10872AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED  = 0x00000000,
10873AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED  = 0x00000001,
10874} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE;
10875
10876/*
10877 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
10878 */
10879
10880typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
10881AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED  = 0x00000000,
10882AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED  = 0x00000001,
10883} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
10884
10885/*******************************************************
10886 * AZROOT Enums
10887 *******************************************************/
10888
10889/*
10890 * AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET enum
10891 */
10892
10893typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET {
10894AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET  = 0x00000000,
10895AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET  = 0x00000001,
10896} AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET;
10897
10898/*******************************************************
10899 * DCCG Enums
10900 *******************************************************/
10901
10902/*
10903 * ENABLE enum
10904 */
10905
10906typedef enum ENABLE {
10907DISABLE_THE_FEATURE                      = 0x00000000,
10908ENABLE_THE_FEATURE                       = 0x00000001,
10909} ENABLE;
10910
10911/*
10912 * ENABLE_CLOCK enum
10913 */
10914
10915typedef enum ENABLE_CLOCK {
10916DISABLE_THE_CLOCK                        = 0x00000000,
10917ENABLE_THE_CLOCK                         = 0x00000001,
10918} ENABLE_CLOCK;
10919
10920/*
10921 * FORCE_VBI enum
10922 */
10923
10924typedef enum FORCE_VBI {
10925FORCE_VBI_LOW                            = 0x00000000,
10926FORCE_VBI_HIGH                           = 0x00000001,
10927} FORCE_VBI;
10928
10929/*
10930 * OVERRIDE_CGTT_SCLK enum
10931 */
10932
10933typedef enum OVERRIDE_CGTT_SCLK {
10934OVERRIDE_CGTT_SCLK_NOOP                  = 0x00000000,
10935SET_OVERRIDE_CGTT_SCLK                   = 0x00000001,
10936} OVERRIDE_CGTT_SCLK;
10937
10938/*
10939 * CLEAR_SMU_INTR enum
10940 */
10941
10942typedef enum CLEAR_SMU_INTR {
10943SMU_INTR_STATUS_NOOP                     = 0x00000000,
10944SMU_INTR_STATUS_CLEAR                    = 0x00000001,
10945} CLEAR_SMU_INTR;
10946
10947/*
10948 * STATIC_SCREEN_SMU_INTR enum
10949 */
10950
10951typedef enum STATIC_SCREEN_SMU_INTR {
10952STATIC_SCREEN_SMU_INTR_NOOP              = 0x00000000,
10953SET_STATIC_SCREEN_SMU_INTR               = 0x00000001,
10954} STATIC_SCREEN_SMU_INTR;
10955
10956/*
10957 * JITTER_REMOVE_DISABLE enum
10958 */
10959
10960typedef enum JITTER_REMOVE_DISABLE {
10961ENABLE_JITTER_REMOVAL                    = 0x00000000,
10962DISABLE_JITTER_REMOVAL                   = 0x00000001,
10963} JITTER_REMOVE_DISABLE;
10964
10965/*
10966 * DS_REF_SRC enum
10967 */
10968
10969typedef enum DS_REF_SRC {
10970DS_REF_IS_XTALIN                         = 0x00000000,
10971DS_REF_IS_EXT_GENLOCK                    = 0x00000001,
10972DS_REF_IS_PCIE                           = 0x00000002,
10973} DS_REF_SRC;
10974
10975/*
10976 * DISABLE_CLOCK_GATING enum
10977 */
10978
10979typedef enum DISABLE_CLOCK_GATING {
10980CLOCK_GATING_ENABLED                     = 0x00000000,
10981CLOCK_GATING_DISABLED                    = 0x00000001,
10982} DISABLE_CLOCK_GATING;
10983
10984/*
10985 * DISABLE_CLOCK_GATING_IN_DCO enum
10986 */
10987
10988typedef enum DISABLE_CLOCK_GATING_IN_DCO {
10989CLOCK_GATING_ENABLED_IN_DCO              = 0x00000000,
10990CLOCK_GATING_DISABLED_IN_DCO             = 0x00000001,
10991} DISABLE_CLOCK_GATING_IN_DCO;
10992
10993/*
10994 * DCCG_DEEP_COLOR_CNTL enum
10995 */
10996
10997typedef enum DCCG_DEEP_COLOR_CNTL {
10998DCCG_DEEP_COLOR_DTO_DISABLE              = 0x00000000,
10999DCCG_DEEP_COLOR_DTO_5_4_RATIO            = 0x00000001,
11000DCCG_DEEP_COLOR_DTO_3_2_RATIO            = 0x00000002,

11001DCCG_DEEP_COLOR_DTO_2_1_RATIO            = 0x00000003,
11002} DCCG_DEEP_COLOR_CNTL;
11003
11004/*
11005 * REFCLK_CLOCK_EN enum
11006 */
11007
11008typedef enum REFCLK_CLOCK_EN {
11009REFCLK_CLOCK_EN_XTALIN_CLK               = 0x00000000,
11010REFCLK_CLOCK_EN_ALLOW_SRC_SEL            = 0x00000001,
11011} REFCLK_CLOCK_EN;
11012
11013/*
11014 * REFCLK_SRC_SEL enum
11015 */
11016
11017typedef enum REFCLK_SRC_SEL {
11018REFCLK_SRC_SEL_PCIE_REFCLK               = 0x00000000,
11019REFCLK_SRC_SEL_CPL_REFCLK                = 0x00000001,
11020} REFCLK_SRC_SEL;
11021
11022/*
11023 * DPREFCLK_SRC_SEL enum
11024 */
11025
11026typedef enum DPREFCLK_SRC_SEL {
11027DPREFCLK_SRC_SEL_CK                      = 0x00000000,
11028DPREFCLK_SRC_SEL_P0PLL                   = 0x00000001,
11029DPREFCLK_SRC_SEL_P1PLL                   = 0x00000002,
11030DPREFCLK_SRC_SEL_P2PLL                   = 0x00000003,
11031DPREFCLK_SRC_SEL_P3PLL                   = 0x00000004,
11032} DPREFCLK_SRC_SEL;
11033
11034/*
11035 * XTAL_REF_SEL enum
11036 */
11037
11038typedef enum XTAL_REF_SEL {
11039XTAL_REF_SEL_1X                          = 0x00000000,
11040XTAL_REF_SEL_2X                          = 0x00000001,
11041} XTAL_REF_SEL;
11042
11043/*
11044 * XTAL_REF_CLOCK_SOURCE_SEL enum
11045 */
11046
11047typedef enum XTAL_REF_CLOCK_SOURCE_SEL {
11048XTAL_REF_CLOCK_SOURCE_SEL_XTALIN         = 0x00000000,
11049XTAL_REF_CLOCK_SOURCE_SEL_PPLL           = 0x00000001,
11050} XTAL_REF_CLOCK_SOURCE_SEL;
11051
11052/*
11053 * MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
11054 */
11055
11056typedef enum MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL {
11057MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN    = 0x00000000,
11058MICROSECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK  = 0x00000001,
11059} MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL;
11060
11061/*
11062 * ALLOW_SR_ON_TRANS_REQ enum
11063 */
11064
11065typedef enum ALLOW_SR_ON_TRANS_REQ {
11066ALLOW_SR_ON_TRANS_REQ_ENABLE             = 0x00000000,
11067ALLOW_SR_ON_TRANS_REQ_DISABLE            = 0x00000001,
11068} ALLOW_SR_ON_TRANS_REQ;
11069
11070/*
11071 * MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
11072 */
11073
11074typedef enum MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL {
11075MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN    = 0x00000000,
11076MILLISECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK  = 0x00000001,
11077} MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL;
11078
11079/*
11080 * PIPE_PIXEL_RATE_SOURCE enum
11081 */
11082
11083typedef enum PIPE_PIXEL_RATE_SOURCE {
11084PIPE_PIXEL_RATE_SOURCE_P0PLL             = 0x00000000,
11085PIPE_PIXEL_RATE_SOURCE_P1PLL             = 0x00000001,
11086PIPE_PIXEL_RATE_SOURCE_P2PLL             = 0x00000002,
11087} PIPE_PIXEL_RATE_SOURCE;
11088
11089/*
11090 * PIPE_PHYPLL_PIXEL_RATE_SOURCE enum
11091 */
11092
11093typedef enum PIPE_PHYPLL_PIXEL_RATE_SOURCE {
11094PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA    = 0x00000000,
11095PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB    = 0x00000001,
11096PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC    = 0x00000002,
11097PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD    = 0x00000003,
11098PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE    = 0x00000004,
11099PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF    = 0x00000005,
11100PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYG    = 0x00000006,
11101} PIPE_PHYPLL_PIXEL_RATE_SOURCE;
11102
11103/*
11104 * PIPE_PIXEL_RATE_PLL_SOURCE enum
11105 */
11106
11107typedef enum PIPE_PIXEL_RATE_PLL_SOURCE {
11108PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL        = 0x00000000,
11109PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL       = 0x00000001,
11110} PIPE_PIXEL_RATE_PLL_SOURCE;
11111
11112/*
11113 * DP_DTO_DS_DISABLE enum
11114 */
11115
11116typedef enum DP_DTO_DS_DISABLE {
11117DP_DTO_DESPREAD_DISABLE                  = 0x00000000,
11118DP_DTO_DESPREAD_ENABLE                   = 0x00000001,
11119} DP_DTO_DS_DISABLE;
11120
11121/*
11122 * CRTC_ADD_PIXEL enum
11123 */
11124
11125typedef enum CRTC_ADD_PIXEL {
11126CRTC_ADD_PIXEL_NOOP                      = 0x00000000,
11127CRTC_ADD_PIXEL_FORCE                     = 0x00000001,
11128} CRTC_ADD_PIXEL;
11129
11130/*
11131 * CRTC_DROP_PIXEL enum
11132 */
11133
11134typedef enum CRTC_DROP_PIXEL {
11135CRTC_DROP_PIXEL_NOOP                     = 0x00000000,
11136CRTC_DROP_PIXEL_FORCE                    = 0x00000001,
11137} CRTC_DROP_PIXEL;
11138
11139/*
11140 * SYMCLK_FE_FORCE_EN enum
11141 */
11142
11143typedef enum SYMCLK_FE_FORCE_EN {
11144SYMCLK_FE_FORCE_EN_DISABLE               = 0x00000000,
11145SYMCLK_FE_FORCE_EN_ENABLE                = 0x00000001,
11146} SYMCLK_FE_FORCE_EN;
11147
11148/*
11149 * SYMCLK_FE_FORCE_SRC enum
11150 */
11151
11152typedef enum SYMCLK_FE_FORCE_SRC {
11153SYMCLK_FE_FORCE_SRC_UNIPHYA              = 0x00000000,
11154SYMCLK_FE_FORCE_SRC_UNIPHYB              = 0x00000001,
11155SYMCLK_FE_FORCE_SRC_UNIPHYC              = 0x00000002,
11156SYMCLK_FE_FORCE_SRC_UNIPHYD              = 0x00000003,
11157SYMCLK_FE_FORCE_SRC_UNIPHYE              = 0x00000004,
11158SYMCLK_FE_FORCE_SRC_UNIPHYF              = 0x00000005,
11159SYMCLK_FE_FORCE_SRC_UNIPHYG              = 0x00000006,
11160} SYMCLK_FE_FORCE_SRC;
11161
11162/*
11163 * DPDBG_CLK_FORCE_EN enum
11164 */
11165
11166typedef enum DPDBG_CLK_FORCE_EN {
11167DPDBG_CLK_FORCE_EN_DISABLE               = 0x00000000,
11168DPDBG_CLK_FORCE_EN_ENABLE                = 0x00000001,
11169} DPDBG_CLK_FORCE_EN;
11170
11171/*
11172 * DVOACLK_COARSE_SKEW_CNTL enum
11173 */
11174
11175typedef enum DVOACLK_COARSE_SKEW_CNTL {
11176DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT   = 0x00000000,
11177DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP    = 0x00000001,
11178DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS   = 0x00000002,
11179DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS   = 0x00000003,
11180DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS   = 0x00000004,
11181DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS   = 0x00000005,
11182DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS   = 0x00000006,
11183DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS   = 0x00000007,
11184DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS   = 0x00000008,
11185DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS   = 0x00000009,
11186DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS  = 0x0000000a,
11187DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS  = 0x0000000b,
11188DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS  = 0x0000000c,
11189DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS  = 0x0000000d,
11190DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS  = 0x0000000e,
11191DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS  = 0x0000000f,
11192DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP    = 0x00000010,
11193DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS   = 0x00000011,
11194DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS   = 0x00000012,
11195DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS   = 0x00000013,
11196DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS   = 0x00000014,
11197DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS   = 0x00000015,
11198DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS   = 0x00000016,
11199DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS   = 0x00000017,
11200DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS   = 0x00000018,
11201DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS  = 0x00000019,
11202DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS  = 0x0000001a,
11203DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS  = 0x0000001b,
11204DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS  = 0x0000001c,
11205DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS  = 0x0000001d,
11206DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS  = 0x0000001e,
11207} DVOACLK_COARSE_SKEW_CNTL;
11208
11209/*
11210 * DVOACLK_FINE_SKEW_CNTL enum
11211 */
11212
11213typedef enum DVOACLK_FINE_SKEW_CNTL {
11214DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT     = 0x00000000,
11215DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP      = 0x00000001,
11216DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS     = 0x00000002,
11217DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS     = 0x00000003,
11218DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP      = 0x00000004,
11219DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS     = 0x00000005,
11220DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS     = 0x00000006,
11221DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS     = 0x00000007,
11222} DVOACLK_FINE_SKEW_CNTL;
11223
11224/*
11225 * DVOACLKD_IN_PHASE enum
11226 */
11227
11228typedef enum DVOACLKD_IN_PHASE {
11229DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO  = 0x00000000,
11230DVOACLKD_IN_PHASE_WITH_PCLK_DVO          = 0x00000001,
11231} DVOACLKD_IN_PHASE;
11232
11233/*
11234 * DVOACLKC_IN_PHASE enum
11235 */
11236
11237typedef enum DVOACLKC_IN_PHASE {
11238DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO  = 0x00000000,
11239DVOACLKC_IN_PHASE_WITH_PCLK_DVO          = 0x00000001,
11240} DVOACLKC_IN_PHASE;
11241
11242/*
11243 * DVOACLKC_MVP_IN_PHASE enum
11244 */
11245
11246typedef enum DVOACLKC_MVP_IN_PHASE {
11247DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO  = 0x00000000,
11248DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO      = 0x00000001,
11249} DVOACLKC_MVP_IN_PHASE;
11250
11251/*
11252 * DVOACLKC_MVP_SKEW_PHASE_OVERRIDE enum
11253 */
11254
11255typedef enum DVOACLKC_MVP_SKEW_PHASE_OVERRIDE {
11256DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE  = 0x00000000,
11257DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE  = 0x00000001,
11258} DVOACLKC_MVP_SKEW_PHASE_OVERRIDE;
11259
11260/*
11261 * MVP_CLK_SRC_SEL enum
11262 */
11263
11264typedef enum MVP_CLK_SRC_SEL {
11265MVP_CLK_SRC_SEL_RSRV                     = 0x00000000,
11266MVP_CLK_SRC_SEL_IO_1                     = 0x00000001,
11267MVP_CLK_SRC_SEL_IO_2                     = 0x00000002,
11268MVP_CLK_SRC_SEL_REFCLK                   = 0x00000003,
11269} MVP_CLK_SRC_SEL;
11270
11271/*
11272 * DCCG_AUDIO_DTO0_SOURCE_SEL enum
11273 */
11274
11275typedef enum DCCG_AUDIO_DTO0_SOURCE_SEL {
11276DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC0         = 0x00000000,
11277DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC1         = 0x00000001,
11278DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC2         = 0x00000002,
11279DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC3         = 0x00000003,
11280DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC4         = 0x00000004,
11281DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC5         = 0x00000005,
11282DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED      = 0x00000006,
11283} DCCG_AUDIO_DTO0_SOURCE_SEL;
11284
11285/*
11286 * DCCG_AUDIO_DTO_SEL enum
11287 */
11288
11289typedef enum DCCG_AUDIO_DTO_SEL {
11290DCCG_AUDIO_DTO_SEL_AUDIO_DTO0            = 0x00000000,
11291DCCG_AUDIO_DTO_SEL_AUDIO_DTO1            = 0x00000001,
11292DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO          = 0x00000002,
11293} DCCG_AUDIO_DTO_SEL;
11294
11295/*
11296 * DCCG_AUDIO_DTO2_SOURCE_SEL enum
11297 */
11298
11299typedef enum DCCG_AUDIO_DTO2_SOURCE_SEL {
11300DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0        = 0x00000000,
11301DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1        = 0x00000001,
11302} DCCG_AUDIO_DTO2_SOURCE_SEL;
11303
11304/*
11305 * DCCG_AUDIO_DTO_USE_512FBR_DTO enum
11306 */
11307
11308typedef enum DCCG_AUDIO_DTO_USE_512FBR_DTO {
11309DCCG_AUDIO_DTO_USE_128FBR_FOR_DP         = 0x00000000,
11310DCCG_AUDIO_DTO_USE_512FBR_FOR_DP         = 0x00000001,
11311} DCCG_AUDIO_DTO_USE_512FBR_DTO;
11312
11313/*
11314 * DCCG_DBG_EN enum
11315 */
11316
11317typedef enum DCCG_DBG_EN {
11318DCCG_DBG_EN_DISABLE                      = 0x00000000,
11319DCCG_DBG_EN_ENABLE                       = 0x00000001,
11320} DCCG_DBG_EN;
11321
11322/*
11323 * DCCG_DBG_BLOCK_SEL enum
11324 */
11325
11326typedef enum DCCG_DBG_BLOCK_SEL {
11327DCCG_DBG_BLOCK_SEL_DCCG                  = 0x00000000,
11328DCCG_DBG_BLOCK_SEL_PMON                  = 0x00000001,
11329DCCG_DBG_BLOCK_SEL_PMON2                 = 0x00000002,
11330} DCCG_DBG_BLOCK_SEL;
11331
11332/*
11333 * DISPCLK_FREQ_RAMP_DONE enum
11334 */
11335
11336typedef enum DISPCLK_FREQ_RAMP_DONE {
11337DISPCLK_FREQ_RAMP_IN_PROGRESS            = 0x00000000,
11338DISPCLK_FREQ_RAMP_COMPLETED              = 0x00000001,
11339} DISPCLK_FREQ_RAMP_DONE;
11340
11341/*
11342 * DCCG_FIFO_ERRDET_RESET enum
11343 */
11344
11345typedef enum DCCG_FIFO_ERRDET_RESET {
11346DCCG_FIFO_ERRDET_RESET_NOOP              = 0x00000000,
11347DCCG_FIFO_ERRDET_RESET_FORCE             = 0x00000001,
11348} DCCG_FIFO_ERRDET_RESET;
11349
11350/*
11351 * DCCG_FIFO_ERRDET_STATE enum
11352 */
11353
11354typedef enum DCCG_FIFO_ERRDET_STATE {
11355DCCG_FIFO_ERRDET_STATE_DETECTION         = 0x00000000,
11356DCCG_FIFO_ERRDET_STATE_CALIBRATION       = 0x00000001,
11357} DCCG_FIFO_ERRDET_STATE;
11358
11359/*
11360 * DCCG_FIFO_ERRDET_OVR_EN enum
11361 */
11362
11363typedef enum DCCG_FIFO_ERRDET_OVR_EN {
11364DCCG_FIFO_ERRDET_OVR_DISABLE             = 0x00000000,
11365DCCG_FIFO_ERRDET_OVR_ENABLE              = 0x00000001,
11366} DCCG_FIFO_ERRDET_OVR_EN;
11367
11368/*
11369 * DISPCLK_CHG_FWD_CORR_DISABLE enum
11370 */
11371
11372typedef enum DISPCLK_CHG_FWD_CORR_DISABLE {
11373DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING  = 0x00000000,
11374DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING  = 0x00000001,
11375} DISPCLK_CHG_FWD_CORR_DISABLE;
11376
11377/*
11378 * DC_MEM_GLOBAL_PWR_REQ_DIS enum
11379 */
11380
11381typedef enum DC_MEM_GLOBAL_PWR_REQ_DIS {
11382DC_MEM_GLOBAL_PWR_REQ_ENABLE             = 0x00000000,
11383DC_MEM_GLOBAL_PWR_REQ_DISABLE            = 0x00000001,
11384} DC_MEM_GLOBAL_PWR_REQ_DIS;
11385
11386/*
11387 * DCCG_PERF_RUN enum
11388 */
11389
11390typedef enum DCCG_PERF_RUN {
11391DCCG_PERF_RUN_NOOP                       = 0x00000000,
11392DCCG_PERF_RUN_START                      = 0x00000001,
11393} DCCG_PERF_RUN;
11394
11395/*
11396 * DCCG_PERF_MODE_VSYNC enum
11397 */
11398
11399typedef enum DCCG_PERF_MODE_VSYNC {
11400DCCG_PERF_MODE_VSYNC_NOOP                = 0x00000000,
11401DCCG_PERF_MODE_VSYNC_START               = 0x00000001,
11402} DCCG_PERF_MODE_VSYNC;
11403
11404/*
11405 * DCCG_PERF_MODE_HSYNC enum
11406 */
11407
11408typedef enum DCCG_PERF_MODE_HSYNC {
11409DCCG_PERF_MODE_HSYNC_NOOP                = 0x00000000,
11410DCCG_PERF_MODE_HSYNC_START               = 0x00000001,
11411} DCCG_PERF_MODE_HSYNC;
11412
11413/*
11414 * DCCG_PERF_CRTC_SELECT enum
11415 */
11416
11417typedef enum DCCG_PERF_CRTC_SELECT {
11418DCCG_PERF_SEL_CRTC0                      = 0x00000000,
11419DCCG_PERF_SEL_CRTC1                      = 0x00000001,
11420DCCG_PERF_SEL_CRTC2                      = 0x00000002,
11421DCCG_PERF_SEL_CRTC3                      = 0x00000003,
11422DCCG_PERF_SEL_CRTC4                      = 0x00000004,
11423DCCG_PERF_SEL_CRTC5                      = 0x00000005,
11424} DCCG_PERF_CRTC_SELECT;
11425
11426/*
11427 * CLOCK_BRANCH_SOFT_RESET enum
11428 */
11429
11430typedef enum CLOCK_BRANCH_SOFT_RESET {
11431CLOCK_BRANCH_SOFT_RESET_NOOP             = 0x00000000,
11432CLOCK_BRANCH_SOFT_RESET_FORCE            = 0x00000001,
11433} CLOCK_BRANCH_SOFT_RESET;
11434
11435/*
11436 * PLL_CFG_IF_SOFT_RESET enum
11437 */
11438
11439typedef enum PLL_CFG_IF_SOFT_RESET {
11440PLL_CFG_IF_SOFT_RESET_NOOP               = 0x00000000,
11441PLL_CFG_IF_SOFT_RESET_FORCE              = 0x00000001,
11442} PLL_CFG_IF_SOFT_RESET;
11443
11444/*
11445 * DVO_ENABLE_RST enum
11446 */
11447
11448typedef enum DVO_ENABLE_RST {
11449DVO_ENABLE_RST_DISABLE                   = 0x00000000,
11450DVO_ENABLE_RST_ENABLE                    = 0x00000001,
11451} DVO_ENABLE_RST;
11452
11453/*******************************************************
11454 * DCI Enums
11455 *******************************************************/
11456
11457/*
11458 * LptNumPipes enum
11459 */
11460
11461typedef enum LptNumPipes {
11462LPT_NUM_PIPES_1CH                        = 0x00000000,
11463LPT_NUM_PIPES_2CH                        = 0x00000001,
11464LPT_NUM_PIPES_4CH                        = 0x00000002,
11465LPT_NUM_PIPES_8CH                        = 0x00000003,
11466} LptNumPipes;
11467
11468/*
11469 * LptNumBanks enum
11470 */
11471
11472typedef enum LptNumBanks {
11473LPT_NUM_BANKS_2BANK                      = 0x00000000,
11474LPT_NUM_BANKS_4BANK                      = 0x00000001,
11475LPT_NUM_BANKS_8BANK                      = 0x00000002,
11476LPT_NUM_BANKS_16BANK                     = 0x00000003,
11477LPT_NUM_BANKS_32BANK                     = 0x00000004,
11478} LptNumBanks;
11479
11480/*
11481 * OVERRIDE_CGTT_DCEFCLK enum
11482 */
11483
11484typedef enum OVERRIDE_CGTT_DCEFCLK {
11485OVERRIDE_CGTT_DCEFCLK_NOOP               = 0x00000000,
11486SET_OVERRIDE_CGTT_DCEFCLK                = 0x00000001,
11487} OVERRIDE_CGTT_DCEFCLK;
11488
11489/*******************************************************
11490 * DCIO Enums
11491 *******************************************************/
11492
11493/*
11494 * DCIO_DC_GENERICA_SEL enum
11495 */
11496
11497typedef enum DCIO_DC_GENERICA_SEL {
11498DCIO_GENERICA_SEL_DACA_STEREOSYNC        = 0x00000000,
11499DCIO_GENERICA_SEL_STEREOSYNC             = 0x00000001,
11500DCIO_GENERICA_SEL_DACA_PIXCLK            = 0x00000002,
11501DCIO_GENERICA_SEL_DACB_PIXCLK            = 0x00000003,
11502DCIO_GENERICA_SEL_DVOA_CTL3              = 0x00000004,
11503DCIO_GENERICA_SEL_P1_PLLCLK              = 0x00000005,
11504DCIO_GENERICA_SEL_P2_PLLCLK              = 0x00000006,
11505DCIO_GENERICA_SEL_DVOA_STEREOSYNC        = 0x00000007,
11506DCIO_GENERICA_SEL_DACA_FIELD_NUMBER      = 0x00000008,
11507DCIO_GENERICA_SEL_DACB_FIELD_NUMBER      = 0x00000009,
11508DCIO_GENERICA_SEL_GENERICA_DCCG          = 0x0000000a,
11509DCIO_GENERICA_SEL_SYNCEN                 = 0x0000000b,
11510DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK      = 0x0000000c,
11511DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK       = 0x0000000d,
11512DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK   = 0x0000000e,
11513DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2  = 0x0000000f,
11514DCIO_GENERICA_SEL_GENERICA_DPRX          = 0x00000010,
11515DCIO_GENERICA_SEL_GENERICB_DPRX          = 0x00000011,
11516} DCIO_DC_GENERICA_SEL;
11517
11518/*
11519 * DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL enum
11520 */
11521
11522typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
11523DCIO_UNIPHYA_TEST_REFDIV_CLK             = 0x00000000,
11524DCIO_UNIPHYB_TEST_REFDIV_CLK             = 0x00000001,
11525DCIO_UNIPHYC_TEST_REFDIV_CLK             = 0x00000002,
11526DCIO_UNIPHYD_TEST_REFDIV_CLK             = 0x00000003,
11527DCIO_UNIPHYE_TEST_REFDIV_CLK             = 0x00000004,
11528DCIO_UNIPHYF_TEST_REFDIV_CLK             = 0x00000005,
11529DCIO_UNIPHYG_TEST_REFDIV_CLK             = 0x00000006,
11530DCIO_UNIPHYLPA_TEST_REFDIV_CLK           = 0x00000007,
11531DCIO_UNIPHYLPB_TEST_REFDIV_CLK           = 0x00000008,
11532} DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL;
11533
11534/*
11535 * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL enum
11536 */
11537
11538typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
11539DCIO_UNIPHYA_FBDIV_CLK                   = 0x00000000,
11540DCIO_UNIPHYB_FBDIV_CLK                   = 0x00000001,
11541DCIO_UNIPHYC_FBDIV_CLK                   = 0x00000002,
11542DCIO_UNIPHYD_FBDIV_CLK                   = 0x00000003,
11543DCIO_UNIPHYE_FBDIV_CLK                   = 0x00000004,
11544DCIO_UNIPHYF_FBDIV_CLK                   = 0x00000005,
11545DCIO_UNIPHYG_FBDIV_CLK                   = 0x00000006,
11546DCIO_UNIPHYLPA_FBDIV_CLK                 = 0x00000007,
11547DCIO_UNIPHYLPB_FBDIV_CLK                 = 0x00000008,
11548} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL;
11549
11550/*
11551 * DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL enum
11552 */
11553
11554typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
11555DCIO_UNIPHYA_FBDIV_SSC_CLK               = 0x00000000,
11556DCIO_UNIPHYB_FBDIV_SSC_CLK               = 0x00000001,
11557DCIO_UNIPHYC_FBDIV_SSC_CLK               = 0x00000002,
11558DCIO_UNIPHYD_FBDIV_SSC_CLK               = 0x00000003,
11559DCIO_UNIPHYE_FBDIV_SSC_CLK               = 0x00000004,
11560DCIO_UNIPHYF_FBDIV_SSC_CLK               = 0x00000005,
11561DCIO_UNIPHYG_FBDIV_SSC_CLK               = 0x00000006,
11562DCIO_UNIPHYLPA_FBDIV_SSC_CLK             = 0x00000007,
11563DCIO_UNIPHYLPB_FBDIV_SSC_CLK             = 0x00000008,
11564} DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL;
11565
11566/*
11567 * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL enum
11568 */
11569
11570typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
11571DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2         = 0x00000000,
11572DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2         = 0x00000001,
11573DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2         = 0x00000002,
11574DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2         = 0x00000003,
11575DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2         = 0x00000004,
11576DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2         = 0x00000005,
11577DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2         = 0x00000006,
11578DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2       = 0x00000007,
11579DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2       = 0x00000008,
11580} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL;
11581
11582/*
11583 * DCIO_DC_GENERICB_SEL enum
11584 */
11585
11586typedef enum DCIO_DC_GENERICB_SEL {
11587DCIO_GENERICB_SEL_DACA_STEREOSYNC        = 0x00000000,
11588DCIO_GENERICB_SEL_STEREOSYNC             = 0x00000001,
11589DCIO_GENERICB_SEL_DACA_PIXCLK            = 0x00000002,
11590DCIO_GENERICB_SEL_DACB_PIXCLK            = 0x00000003,
11591DCIO_GENERICB_SEL_DVOA_CTL3              = 0x00000004,
11592DCIO_GENERICB_SEL_P1_PLLCLK              = 0x00000005,
11593DCIO_GENERICB_SEL_P2_PLLCLK              = 0x00000006,
11594DCIO_GENERICB_SEL_DVOA_STEREOSYNC        = 0x00000007,
11595DCIO_GENERICB_SEL_DACA_FIELD_NUMBER      = 0x00000008,
11596DCIO_GENERICB_SEL_DACB_FIELD_NUMBER      = 0x00000009,
11597DCIO_GENERICB_SEL_GENERICB_DCCG          = 0x0000000a,
11598DCIO_GENERICB_SEL_SYNCEN                 = 0x0000000b,
11599DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK      = 0x0000000c,
11600DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK       = 0x0000000d,
11601DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK   = 0x0000000e,
11602DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2  = 0x0000000f,
11603} DCIO_DC_GENERICB_SEL;
11604
11605/*
11606 * DCIO_DC_PAD_EXTERN_SIG_SEL enum
11607 */
11608
11609typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL {
11610DCIO_DC_PAD_EXTERN_SIG_SEL_MVP           = 0x00000000,
11611DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA        = 0x00000001,
11612DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK     = 0x00000002,
11613DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC   = 0x00000003,
11614DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA      = 0x00000004,
11615DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB      = 0x00000005,
11616DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC      = 0x00000006,
11617DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1          = 0x00000007,
11618DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2          = 0x00000008,
11619DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK       = 0x00000009,
11620DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA      = 0x0000000a,
11621DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK       = 0x0000000b,
11622DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA      = 0x0000000c,
11623DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1         = 0x0000000d,
11624DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0         = 0x0000000e,
11625DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL        = 0x0000000f,
11626} DCIO_DC_PAD_EXTERN_SIG_SEL;
11627
11628/*
11629 * DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS enum
11630 */
11631
11632typedef enum DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS {
11633DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA         = 0x00000000,
11634DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE  = 0x00000001,
11635DCIO_MVP_PIXEL_SRC_STATUS_CRTC           = 0x00000002,
11636DCIO_MVP_PIXEL_SRC_STATUS_LB             = 0x00000003,
11637} DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS;
11638
11639/*
11640 * DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL enum
11641 */
11642
11643typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL {
11644DCIO_HSYNCA_OUTPUT_SEL_DISABLE           = 0x00000000,
11645DCIO_HSYNCA_OUTPUT_SEL_PPLL1             = 0x00000001,
11646DCIO_HSYNCA_OUTPUT_SEL_PPLL2             = 0x00000002,
11647DCIO_HSYNCA_OUTPUT_SEL_RESERVED          = 0x00000003,
11648} DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL;
11649
11650/*
11651 * DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL enum
11652 */
11653
11654typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {
11655DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE        = 0x00000000,
11656DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1          = 0x00000001,
11657DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2          = 0x00000002,
11658DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3  = 0x00000003,
11659} DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL;
11660
11661/*
11662 * DCIO_DC_GPIO_VIP_DEBUG enum
11663 */
11664
11665typedef enum DCIO_DC_GPIO_VIP_DEBUG {
11666DCIO_DC_GPIO_VIP_DEBUG_NORMAL            = 0x00000000,
11667DCIO_DC_GPIO_VIP_DEBUG_CG_BIG            = 0x00000001,
11668} DCIO_DC_GPIO_VIP_DEBUG;
11669
11670/*
11671 * DCIO_DC_GPIO_MACRO_DEBUG enum
11672 */
11673
11674typedef enum DCIO_DC_GPIO_MACRO_DEBUG {
11675DCIO_DC_GPIO_MACRO_DEBUG_NORMAL          = 0x00000000,
11676DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF        = 0x00000001,
11677DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2  = 0x00000002,
11678DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3  = 0x00000003,
11679} DCIO_DC_GPIO_MACRO_DEBUG;
11680
11681/*
11682 * DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL enum
11683 */
11684
11685typedef enum DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL {
11686DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL  = 0x00000000,
11687DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP  = 0x00000001,
11688} DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL;
11689
11690/*
11691 * DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN enum
11692 */
11693
11694typedef enum DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN {
11695DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS    = 0x00000000,
11696DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE    = 0x00000001,
11697} DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN;
11698
11699/*
11700 * DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE enum
11701 */
11702
11703typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE {
11704DCIO_DPRX_LOOPBACK_ENABLE_NORMAL         = 0x00000000,
11705DCIO_DPRX_LOOPBACK_ENABLE_LOOP           = 0x00000001,
11706} DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE;
11707
11708/*
11709 * DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION enum
11710 */
11711
11712typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION {
11713DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x00000000,
11714DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x00000001,
11715DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS = 0x00000002,
11716DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS = 0x00000003,
11717DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS = 0x00000004,
11718DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS = 0x00000005,
11719DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS = 0x00000006,
11720DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS = 0x00000007,
11721} DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION;
11722
11723/*
11724 * DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT enum
11725 */
11726
11727typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {
11728DCIO_UNIPHY_CHANNEL_NO_INVERSION         = 0x00000000,
11729DCIO_UNIPHY_CHANNEL_INVERTED             = 0x00000001,
11730} DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT;
11731
11732/*
11733 * DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK enum
11734 */
11735
11736typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {
11737DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW  = 0x00000000,
11738DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW   = 0x00000001,
11739DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED  = 0x00000002,
11740DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED  = 0x00000003,
11741} DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK;
11742
11743/*
11744 * DCIO_UNIPHY_CHANNEL_XBAR_SOURCE enum
11745 */
11746
11747typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {
11748DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0      = 0x00000000,
11749DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1      = 0x00000001,
11750DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2      = 0x00000002,
11751DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3      = 0x00000003,
11752} DCIO_UNIPHY_CHANNEL_XBAR_SOURCE;
11753
11754/*
11755 * DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN enum
11756 */
11757
11758typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN {
11759DCIO_VIP_MUX_EN_DVO                      = 0x00000000,
11760DCIO_VIP_MUX_EN_VIP                      = 0x00000001,
11761} DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN;
11762
11763/*
11764 * DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN enum
11765 */
11766
11767typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN {
11768DCIO_VIP_ALTER_MAPPING_EN_DEFAULT        = 0x00000000,
11769DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE    = 0x00000001,
11770} DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN;
11771
11772/*
11773 * DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN enum
11774 */
11775
11776typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN {
11777DCIO_DVO_ALTER_MAPPING_EN_DEFAULT        = 0x00000000,
11778DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE    = 0x00000001,
11779} DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN;
11780
11781/*
11782 * DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN enum
11783 */
11784
11785typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN {
11786DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE  = 0x00000000,
11787DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE  = 0x00000001,
11788} DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN;
11789
11790/*
11791 * DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE enum
11792 */
11793
11794typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE {
11795DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF   = 0x00000000,
11796DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON    = 0x00000001,
11797} DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE;
11798
11799/*
11800 * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL enum
11801 */
11802
11803typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL {
11804DCIO_LVTMA_SYNCEN_POL_NON_INVERT         = 0x00000000,
11805DCIO_LVTMA_SYNCEN_POL_INVERT             = 0x00000001,
11806} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL;
11807
11808/*
11809 * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON enum
11810 */
11811
11812typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON {
11813DCIO_LVTMA_DIGON_OFF                     = 0x00000000,
11814DCIO_LVTMA_DIGON_ON                      = 0x00000001,
11815} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON;
11816
11817/*
11818 * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL enum
11819 */
11820
11821typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL {
11822DCIO_LVTMA_DIGON_POL_NON_INVERT          = 0x00000000,
11823DCIO_LVTMA_DIGON_POL_INVERT              = 0x00000001,
11824} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL;
11825
11826/*
11827 * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON enum
11828 */
11829
11830typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON {
11831DCIO_LVTMA_BLON_OFF                      = 0x00000000,
11832DCIO_LVTMA_BLON_ON                       = 0x00000001,
11833} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON;
11834
11835/*
11836 * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL enum
11837 */
11838
11839typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL {
11840DCIO_LVTMA_BLON_POL_NON_INVERT           = 0x00000000,
11841DCIO_LVTMA_BLON_POL_INVERT               = 0x00000001,
11842} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL;
11843
11844/*
11845 * DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN enum
11846 */
11847
11848typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN {
11849DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON      = 0x00000000,
11850DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE  = 0x00000001,
11851} DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN;
11852
11853/*
11854 * DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN enum
11855 */
11856
11857typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {
11858DCIO_BL_PWM_FRACTIONAL_DISABLE           = 0x00000000,
11859DCIO_BL_PWM_FRACTIONAL_ENABLE            = 0x00000001,
11860} DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN;
11861
11862/*
11863 * DCIO_BL_PWM_CNTL_BL_PWM_EN enum
11864 */
11865
11866typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN {
11867DCIO_BL_PWM_DISABLE                      = 0x00000000,
11868DCIO_BL_PWM_ENABLE                       = 0x00000001,
11869} DCIO_BL_PWM_CNTL_BL_PWM_EN;
11870
11871/*
11872 * DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT enum
11873 */
11874
11875typedef enum DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT {
11876DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL  = 0x00000000,
11877DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1  = 0x00000001,
11878DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2  = 0x00000002,
11879DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3  = 0x00000003,
11880} DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT;
11881
11882/*
11883 * DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE enum
11884 */
11885
11886typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {
11887DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE      = 0x00000000,
11888DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE       = 0x00000001,
11889} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE;
11890
11891/*
11892 * DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN enum
11893 */
11894
11895typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN {
11896DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL  = 0x00000000,
11897DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM  = 0x00000001,
11898} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN;
11899
11900/*
11901 * DCIO_BL_PWM_GRP1_REG_LOCK enum
11902 */
11903
11904typedef enum DCIO_BL_PWM_GRP1_REG_LOCK {
11905DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE        = 0x00000000,
11906DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE         = 0x00000001,
11907} DCIO_BL_PWM_GRP1_REG_LOCK;
11908
11909/*
11910 * DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START enum
11911 */
11912
11913typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START {
11914DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE  = 0x00000000,
11915DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE  = 0x00000001,
11916} DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START;
11917
11918/*
11919 * DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL enum
11920 */
11921
11922typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {
11923DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1  = 0x00000000,
11924DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2  = 0x00000001,
11925DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3  = 0x00000002,
11926DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4  = 0x00000003,
11927DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5  = 0x00000004,
11928DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6  = 0x00000005,
11929} DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL;
11930
11931/*
11932 * DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN enum
11933 */
11934
11935typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {
11936DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM  = 0x00000000,
11937DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM  = 0x00000001,
11938} DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN;
11939
11940/*
11941 * DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN enum
11942 */
11943
11944typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {
11945DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE  = 0x00000000,
11946DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE  = 0x00000001,
11947} DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN;
11948
11949/*
11950 * DCIO_GSL_SEL enum
11951 */
11952
11953typedef enum DCIO_GSL_SEL {
11954DCIO_GSL_SEL_GROUP_0                     = 0x00000000,
11955DCIO_GSL_SEL_GROUP_1                     = 0x00000001,
11956DCIO_GSL_SEL_GROUP_2                     = 0x00000002,
11957} DCIO_GSL_SEL;
11958
11959/*
11960 * DCIO_GENLK_CLK_GSL_MASK enum
11961 */
11962
11963typedef enum DCIO_GENLK_CLK_GSL_MASK {
11964DCIO_GENLK_CLK_GSL_MASK_NO               = 0x00000000,
11965DCIO_GENLK_CLK_GSL_MASK_TIMING           = 0x00000001,
11966DCIO_GENLK_CLK_GSL_MASK_STEREO           = 0x00000002,
11967} DCIO_GENLK_CLK_GSL_MASK;
11968
11969/*
11970 * DCIO_GENLK_VSYNC_GSL_MASK enum
11971 */
11972
11973typedef enum DCIO_GENLK_VSYNC_GSL_MASK {
11974DCIO_GENLK_VSYNC_GSL_MASK_NO             = 0x00000000,
11975DCIO_GENLK_VSYNC_GSL_MASK_TIMING         = 0x00000001,
11976DCIO_GENLK_VSYNC_GSL_MASK_STEREO         = 0x00000002,
11977} DCIO_GENLK_VSYNC_GSL_MASK;
11978
11979/*
11980 * DCIO_SWAPLOCK_A_GSL_MASK enum
11981 */
11982
11983typedef enum DCIO_SWAPLOCK_A_GSL_MASK {
11984DCIO_SWAPLOCK_A_GSL_MASK_NO              = 0x00000000,
11985DCIO_SWAPLOCK_A_GSL_MASK_TIMING          = 0x00000001,
11986DCIO_SWAPLOCK_A_GSL_MASK_STEREO          = 0x00000002,
11987} DCIO_SWAPLOCK_A_GSL_MASK;
11988
11989/*
11990 * DCIO_SWAPLOCK_B_GSL_MASK enum
11991 */
11992
11993typedef enum DCIO_SWAPLOCK_B_GSL_MASK {
11994DCIO_SWAPLOCK_B_GSL_MASK_NO              = 0x00000000,
11995DCIO_SWAPLOCK_B_GSL_MASK_TIMING          = 0x00000001,
11996DCIO_SWAPLOCK_B_GSL_MASK_STEREO          = 0x00000002,
11997} DCIO_SWAPLOCK_B_GSL_MASK;
11998
11999/*
12000 * DCIO_GSL_VSYNC_SEL enum

12001 */
12002
12003typedef enum DCIO_GSL_VSYNC_SEL {
12004DCIO_GSL_VSYNC_SEL_PIPE0                 = 0x00000000,
12005DCIO_GSL_VSYNC_SEL_PIPE1                 = 0x00000001,
12006DCIO_GSL_VSYNC_SEL_PIPE2                 = 0x00000002,
12007DCIO_GSL_VSYNC_SEL_PIPE3                 = 0x00000003,
12008DCIO_GSL_VSYNC_SEL_PIPE4                 = 0x00000004,
12009DCIO_GSL_VSYNC_SEL_PIPE5                 = 0x00000005,
12010} DCIO_GSL_VSYNC_SEL;
12011
12012/*
12013 * DCIO_GSL0_TIMING_SYNC_SEL enum
12014 */
12015
12016typedef enum DCIO_GSL0_TIMING_SYNC_SEL {
12017DCIO_GSL0_TIMING_SYNC_SEL_PIPE           = 0x00000000,
12018DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC   = 0x00000001,
12019DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK     = 0x00000002,
12020DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A     = 0x00000003,
12021DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B     = 0x00000004,
12022} DCIO_GSL0_TIMING_SYNC_SEL;
12023
12024/*
12025 * DCIO_GSL0_GLOBAL_UNLOCK_SEL enum
12026 */
12027
12028typedef enum DCIO_GSL0_GLOBAL_UNLOCK_SEL {
12029DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION    = 0x00000000,
12030DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC  = 0x00000001,
12031DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK    = 0x00000002,
12032DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A   = 0x00000003,
12033DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B   = 0x00000004,
12034} DCIO_GSL0_GLOBAL_UNLOCK_SEL;
12035
12036/*
12037 * DCIO_GSL1_TIMING_SYNC_SEL enum
12038 */
12039
12040typedef enum DCIO_GSL1_TIMING_SYNC_SEL {
12041DCIO_GSL1_TIMING_SYNC_SEL_PIPE           = 0x00000000,
12042DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC   = 0x00000001,
12043DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK     = 0x00000002,
12044DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A     = 0x00000003,
12045DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B     = 0x00000004,
12046} DCIO_GSL1_TIMING_SYNC_SEL;
12047
12048/*
12049 * DCIO_GSL1_GLOBAL_UNLOCK_SEL enum
12050 */
12051
12052typedef enum DCIO_GSL1_GLOBAL_UNLOCK_SEL {
12053DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION    = 0x00000000,
12054DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC  = 0x00000001,
12055DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK    = 0x00000002,
12056DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A   = 0x00000003,
12057DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B   = 0x00000004,
12058} DCIO_GSL1_GLOBAL_UNLOCK_SEL;
12059
12060/*
12061 * DCIO_GSL2_TIMING_SYNC_SEL enum
12062 */
12063
12064typedef enum DCIO_GSL2_TIMING_SYNC_SEL {
12065DCIO_GSL2_TIMING_SYNC_SEL_PIPE           = 0x00000000,
12066DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC   = 0x00000001,
12067DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK     = 0x00000002,
12068DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A     = 0x00000003,
12069DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B     = 0x00000004,
12070} DCIO_GSL2_TIMING_SYNC_SEL;
12071
12072/*
12073 * DCIO_GSL2_GLOBAL_UNLOCK_SEL enum
12074 */
12075
12076typedef enum DCIO_GSL2_GLOBAL_UNLOCK_SEL {
12077DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION    = 0x00000000,
12078DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC  = 0x00000001,
12079DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK    = 0x00000002,
12080DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A   = 0x00000003,
12081DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B   = 0x00000004,
12082} DCIO_GSL2_GLOBAL_UNLOCK_SEL;
12083
12084/*
12085 * DCIO_DC_GPU_TIMER_START_POSITION enum
12086 */
12087
12088typedef enum DCIO_DC_GPU_TIMER_START_POSITION {
12089DCIO_GPU_TIMER_START_0_END_27            = 0x00000000,
12090DCIO_GPU_TIMER_START_1_END_28            = 0x00000001,
12091DCIO_GPU_TIMER_START_2_END_29            = 0x00000002,
12092DCIO_GPU_TIMER_START_3_END_30            = 0x00000003,
12093DCIO_GPU_TIMER_START_4_END_31            = 0x00000004,
12094DCIO_GPU_TIMER_START_6_END_33            = 0x00000005,
12095DCIO_GPU_TIMER_START_8_END_35            = 0x00000006,
12096DCIO_GPU_TIMER_START_10_END_37           = 0x00000007,
12097} DCIO_DC_GPU_TIMER_START_POSITION;
12098
12099/*
12100 * DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL enum
12101 */
12102
12103typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {
12104DCIO_TEST_CLK_SEL_DISPCLK                = 0x00000000,
12105DCIO_TEST_CLK_SEL_GATED_DISPCLK          = 0x00000001,
12106DCIO_TEST_CLK_SEL_SCLK                   = 0x00000002,
12107} DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL;
12108
12109/*
12110 * DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS enum
12111 */
12112
12113typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {
12114DCIO_DISPCLK_R_DCIO_GATE_DISABLE         = 0x00000000,
12115DCIO_DISPCLK_R_DCIO_GATE_ENABLE          = 0x00000001,
12116} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS;
12117
12118/*
12119 * DCIO_DCO_DCFE_EXT_VSYNC_MUX enum
12120 */
12121
12122typedef enum DCIO_DCO_DCFE_EXT_VSYNC_MUX {
12123DCIO_EXT_VSYNC_MUX_SWAPLOCKB             = 0x00000000,
12124DCIO_EXT_VSYNC_MUX_CRTC0                 = 0x00000001,
12125DCIO_EXT_VSYNC_MUX_CRTC1                 = 0x00000002,
12126DCIO_EXT_VSYNC_MUX_CRTC2                 = 0x00000003,
12127DCIO_EXT_VSYNC_MUX_CRTC3                 = 0x00000004,
12128DCIO_EXT_VSYNC_MUX_CRTC4                 = 0x00000005,
12129DCIO_EXT_VSYNC_MUX_CRTC5                 = 0x00000006,
12130DCIO_EXT_VSYNC_MUX_GENERICB              = 0x00000007,
12131} DCIO_DCO_DCFE_EXT_VSYNC_MUX;
12132
12133/*
12134 * DCIO_DCO_EXT_VSYNC_MASK enum
12135 */
12136
12137typedef enum DCIO_DCO_EXT_VSYNC_MASK {
12138DCIO_EXT_VSYNC_MASK_NONE                 = 0x00000000,
12139DCIO_EXT_VSYNC_MASK_PIPE0                = 0x00000001,
12140DCIO_EXT_VSYNC_MASK_PIPE1                = 0x00000002,
12141DCIO_EXT_VSYNC_MASK_PIPE2                = 0x00000003,
12142DCIO_EXT_VSYNC_MASK_PIPE3                = 0x00000004,
12143DCIO_EXT_VSYNC_MASK_PIPE4                = 0x00000005,
12144DCIO_EXT_VSYNC_MASK_PIPE5                = 0x00000006,
12145DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE       = 0x00000007,
12146} DCIO_DCO_EXT_VSYNC_MASK;
12147
12148/*
12149 * DCIO_DSYNC_SOFT_RESET enum
12150 */
12151
12152typedef enum DCIO_DSYNC_SOFT_RESET {
12153DCIO_DSYNC_SOFT_RESET_DEASSERT           = 0x00000000,
12154DCIO_DSYNC_SOFT_RESET_ASSERT             = 0x00000001,
12155} DCIO_DSYNC_SOFT_RESET;
12156
12157/*
12158 * DCIO_DACA_SOFT_RESET enum
12159 */
12160
12161typedef enum DCIO_DACA_SOFT_RESET {
12162DCIO_DACA_SOFT_RESET_DEASSERT            = 0x00000000,
12163DCIO_DACA_SOFT_RESET_ASSERT              = 0x00000001,
12164} DCIO_DACA_SOFT_RESET;
12165
12166/*
12167 * DCIO_DCRXPHY_SOFT_RESET enum
12168 */
12169
12170typedef enum DCIO_DCRXPHY_SOFT_RESET {
12171DCIO_DCRXPHY_SOFT_RESET_DEASSERT         = 0x00000000,
12172DCIO_DCRXPHY_SOFT_RESET_ASSERT           = 0x00000001,
12173} DCIO_DCRXPHY_SOFT_RESET;
12174
12175/*
12176 * DCIO_DPHY_LANE_SEL enum
12177 */
12178
12179typedef enum DCIO_DPHY_LANE_SEL {
12180DCIO_DPHY_LANE_SEL_LANE0                 = 0x00000000,
12181DCIO_DPHY_LANE_SEL_LANE1                 = 0x00000001,
12182DCIO_DPHY_LANE_SEL_LANE2                 = 0x00000002,
12183DCIO_DPHY_LANE_SEL_LANE3                 = 0x00000003,
12184} DCIO_DPHY_LANE_SEL;
12185
12186/*
12187 * DCIO_DPCS_INTERRUPT_TYPE enum
12188 */
12189
12190typedef enum DCIO_DPCS_INTERRUPT_TYPE {
12191DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED     = 0x00000000,
12192DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED     = 0x00000001,
12193} DCIO_DPCS_INTERRUPT_TYPE;
12194
12195/*
12196 * DCIO_DPCS_INTERRUPT_MASK enum
12197 */
12198
12199typedef enum DCIO_DPCS_INTERRUPT_MASK {
12200DCIO_DPCS_INTERRUPT_DISABLE              = 0x00000000,
12201DCIO_DPCS_INTERRUPT_ENABLE               = 0x00000001,
12202} DCIO_DPCS_INTERRUPT_MASK;
12203
12204/*
12205 * DCIO_DC_GPU_TIMER_READ_SELECT enum
12206 */
12207
12208typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
12209DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE  = 0x00000000,
12210DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE  = 0x00000001,
12211DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE  = 0x00000002,
12212DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE  = 0x00000003,
12213DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE  = 0x00000004,
12214DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE  = 0x00000005,
12215DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE  = 0x00000006,
12216DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE  = 0x00000007,
12217DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE  = 0x00000008,
12218DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE  = 0x00000009,
12219DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE  = 0x0000000a,
12220DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE  = 0x0000000b,
12221DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP  = 0x0000000c,
12222DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP  = 0x0000000d,
12223DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP  = 0x0000000e,
12224DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP  = 0x0000000f,
12225DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP  = 0x00000010,
12226DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP  = 0x00000011,
12227DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP  = 0x00000012,
12228DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP  = 0x00000013,
12229DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP  = 0x00000014,
12230DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP  = 0x00000015,
12231DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP  = 0x00000016,
12232DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP  = 0x00000017,
12233DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM  = 0x00000018,
12234DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM  = 0x00000019,
12235DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM  = 0x0000001a,
12236DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM  = 0x0000001b,
12237DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM  = 0x0000001c,
12238DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM  = 0x0000001d,
12239DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM  = 0x0000001e,
12240DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM  = 0x0000001f,
12241DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM  = 0x00000020,
12242DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM  = 0x00000021,
12243DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM  = 0x00000022,
12244DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM  = 0x00000023,
12245} DCIO_DC_GPU_TIMER_READ_SELECT;
12246
12247/*
12248 * DCIO_IMPCAL_STEP_DELAY enum
12249 */
12250
12251typedef enum DCIO_IMPCAL_STEP_DELAY {
12252DCIO_IMPCAL_STEP_DELAY_1us               = 0x00000000,
12253DCIO_IMPCAL_STEP_DELAY_2us               = 0x00000001,
12254DCIO_IMPCAL_STEP_DELAY_3us               = 0x00000002,
12255DCIO_IMPCAL_STEP_DELAY_4us               = 0x00000003,
12256DCIO_IMPCAL_STEP_DELAY_5us               = 0x00000004,
12257DCIO_IMPCAL_STEP_DELAY_6us               = 0x00000005,
12258DCIO_IMPCAL_STEP_DELAY_7us               = 0x00000006,
12259DCIO_IMPCAL_STEP_DELAY_8us               = 0x00000007,
12260DCIO_IMPCAL_STEP_DELAY_9us               = 0x00000008,
12261DCIO_IMPCAL_STEP_DELAY_10us              = 0x00000009,
12262DCIO_IMPCAL_STEP_DELAY_11us              = 0x0000000a,
12263DCIO_IMPCAL_STEP_DELAY_12us              = 0x0000000b,
12264DCIO_IMPCAL_STEP_DELAY_13us              = 0x0000000c,
12265DCIO_IMPCAL_STEP_DELAY_14us              = 0x0000000d,
12266DCIO_IMPCAL_STEP_DELAY_15us              = 0x0000000e,
12267DCIO_IMPCAL_STEP_DELAY_16us              = 0x0000000f,
12268} DCIO_IMPCAL_STEP_DELAY;
12269
12270/*
12271 * DCIO_UNIPHY_IMPCAL_SEL enum
12272 */
12273
12274typedef enum DCIO_UNIPHY_IMPCAL_SEL {
12275DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE       = 0x00000000,
12276DCIO_UNIPHY_IMPCAL_SEL_BINARY            = 0x00000001,
12277} DCIO_UNIPHY_IMPCAL_SEL;
12278
12279/*
12280 * DCIO_DBG_ASYNC_BLOCK_SEL enum
12281 */
12282
12283typedef enum DCIO_DBG_ASYNC_BLOCK_SEL {
12284DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE        = 0x00000000,
12285DCIO_DBG_ASYNC_BLOCK_SEL_DCCG            = 0x00000001,
12286DCIO_DBG_ASYNC_BLOCK_SEL_DCIO            = 0x00000002,
12287DCIO_DBG_ASYNC_BLOCK_SEL_DCO             = 0x00000003,
12288} DCIO_DBG_ASYNC_BLOCK_SEL;
12289
12290/*
12291 * DCIO_DBG_ASYNC_4BIT_SEL enum
12292 */
12293
12294typedef enum DCIO_DBG_ASYNC_4BIT_SEL {
12295DCIO_DBG_ASYNC_4BIT_SEL_3TO0             = 0x00000000,
12296DCIO_DBG_ASYNC_4BIT_SEL_7TO4             = 0x00000001,
12297DCIO_DBG_ASYNC_4BIT_SEL_11TO8            = 0x00000002,
12298DCIO_DBG_ASYNC_4BIT_SEL_15TO12           = 0x00000003,
12299DCIO_DBG_ASYNC_4BIT_SEL_19TO16           = 0x00000004,
12300DCIO_DBG_ASYNC_4BIT_SEL_23TO20           = 0x00000005,
12301DCIO_DBG_ASYNC_4BIT_SEL_27TO24           = 0x00000006,
12302DCIO_DBG_ASYNC_4BIT_SEL_31TO28           = 0x00000007,
12303} DCIO_DBG_ASYNC_4BIT_SEL;
12304
12305/*******************************************************
12306 * AOUT Enums
12307 *******************************************************/
12308
12309/*
12310 * AOUT_EN enum
12311 */
12312
12313typedef enum AOUT_EN {
12314AOUT_DISABLE                             = 0x00000000,
12315AOUT_ENABLE                              = 0x00000001,
12316} AOUT_EN;
12317
12318/*
12319 * AOUT_FIFO_START_ADDR enum
12320 */
12321
12322typedef enum AOUT_FIFO_START_ADDR {
12323AOUT_FIFO_START_ADDR_2                   = 0x00000000,
12324AOUT_FIFO_START_ADDR_3                   = 0x00000001,
12325} AOUT_FIFO_START_ADDR;
12326
12327/*
12328 * AOUT_CRC_TEST_EN enum
12329 */
12330
12331typedef enum AOUT_CRC_TEST_EN {
12332AOUT_CRC_DISABLE                         = 0x00000000,
12333AOUT_CRC_ENABLE                          = 0x00000001,
12334} AOUT_CRC_TEST_EN;
12335
12336/*
12337 * AOUT_CRC_SOFT_RESET enum
12338 */
12339
12340typedef enum AOUT_CRC_SOFT_RESET {
12341AOUT_CRC_NO_RESET                        = 0x00000000,
12342AOUT_CRC_RESET                           = 0x00000001,
12343} AOUT_CRC_SOFT_RESET;
12344
12345/*
12346 * AOUT_CRC_CONT_EN enum
12347 */
12348
12349typedef enum AOUT_CRC_CONT_EN {
12350AOUT_CRC_ONE_SHOT                        = 0x00000000,
12351AOUT_CRC_CONT                            = 0x00000001,
12352} AOUT_CRC_CONT_EN;
12353
12354/*
12355 * I2S_WORD_SIZE enum
12356 */
12357
12358typedef enum I2S_WORD_SIZE {
12359I2S_WORD_SIZE_32                         = 0x00000000,
12360I2S_WORD_SIZE_16                         = 0x00000001,
12361} I2S_WORD_SIZE;
12362
12363/*
12364 * I2S_SAMPLE_ALIGNMENT enum
12365 */
12366
12367typedef enum I2S_SAMPLE_ALIGNMENT {
12368I2S_SAMPLE_LEFT_ALIGNED                  = 0x00000000,
12369I2S_SAMPLE_RIGHT_ALIGNED                 = 0x00000001,
12370} I2S_SAMPLE_ALIGNMENT;
12371
12372/*
12373 * I2S_SAMPLE_BIT_ORDER enum
12374 */
12375
12376typedef enum I2S_SAMPLE_BIT_ORDER {
12377I2S_SAMPLE_BIT_ORDER_MSB                 = 0x00000000,
12378I2S_SAMPLE_BIT_ORDER_LSB                 = 0x00000001,
12379} I2S_SAMPLE_BIT_ORDER;
12380
12381/*
12382 * I2S_LRCLK_POLARITY enum
12383 */
12384
12385typedef enum I2S_LRCLK_POLARITY {
12386I2S_LRCLK_LOW_LEFT                       = 0x00000000,
12387I2S_LRCLK_HIGH_LEFT                      = 0x00000001,
12388} I2S_LRCLK_POLARITY;
12389
12390/*
12391 * I2S_WORD_ALIGNMENT enum
12392 */
12393
12394typedef enum I2S_WORD_ALIGNMENT {
12395I2S_WORD_ALTERNATE_ALIGNMENT             = 0x00000000,
12396I2S_WORD_I2S_ALIGNMENT                   = 0x00000001,
12397} I2S_WORD_ALIGNMENT;
12398
12399/*
12400 * SPDIF_INVERT_EN enum
12401 */
12402
12403typedef enum SPDIF_INVERT_EN {
12404SPDIF_INVERT_DISABLE                     = 0x00000000,
12405SPDIF_INVERT_ENABLE                      = 0x00000001,
12406} SPDIF_INVERT_EN;
12407
12408/*******************************************************
12409 * DCO Enums
12410 *******************************************************/
12411
12412/*
12413 * DPDBG_EN enum
12414 */
12415
12416typedef enum DPDBG_EN {
12417DPDBG_DISABLE                            = 0x00000000,
12418DPDBG_ENABLE                             = 0x00000001,
12419} DPDBG_EN;
12420
12421/*
12422 * DPDBG_INPUT_EN enum
12423 */
12424
12425typedef enum DPDBG_INPUT_EN {
12426DPDBG_INPUT_DISABLE                      = 0x00000000,
12427DPDBG_INPUT_ENABLE                       = 0x00000001,
12428} DPDBG_INPUT_EN;
12429
12430/*
12431 * DPDBG_ERROR_DETECTION_MODE enum
12432 */
12433
12434typedef enum DPDBG_ERROR_DETECTION_MODE {
12435DPDBG_ERROR_DETECTION_MODE_CSC           = 0x00000000,
12436DPDBG_ERROR_DETECTION_MODE_RS_ENCODING   = 0x00000001,
12437} DPDBG_ERROR_DETECTION_MODE;
12438
12439/*
12440 * DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK enum
12441 */
12442
12443typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK {
12444DPDBG_FIFO_OVERFLOW_INT_DISABLE          = 0x00000000,
12445DPDBG_FIFO_OVERFLOW_INT_ENABLE           = 0x00000001,
12446} DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK;
12447
12448/*
12449 * DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE enum
12450 */
12451
12452typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE {
12453DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED      = 0x00000000,
12454DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED      = 0x00000001,
12455} DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE;
12456
12457/*
12458 * DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK enum
12459 */
12460
12461typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK {
12462DPDBG_FIFO_OVERFLOW_INT_NO_ACK           = 0x00000000,
12463DPDBG_FIFO_OVERFLOW_INT_CLEAR            = 0x00000001,
12464} DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK;
12465
12466/*
12467 * PM_ASSERT_RESET enum
12468 */
12469
12470typedef enum PM_ASSERT_RESET {
12471PM_ASSERT_RESET_0                        = 0x00000000,
12472PM_ASSERT_RESET_1                        = 0x00000001,
12473} PM_ASSERT_RESET;
12474
12475/*
12476 * DAC_MUX_SELECT enum
12477 */
12478
12479typedef enum DAC_MUX_SELECT {
12480DAC_MUX_SELECT_DACA                      = 0x00000000,
12481DAC_MUX_SELECT_DACB                      = 0x00000001,
12482} DAC_MUX_SELECT;
12483
12484/*
12485 * TMDS_DVO_MUX_SELECT enum
12486 */
12487
12488typedef enum TMDS_DVO_MUX_SELECT {
12489TMDS_DVO_MUX_SELECT_B                    = 0x00000000,
12490TMDS_DVO_MUX_SELECT_G                    = 0x00000001,
12491TMDS_DVO_MUX_SELECT_R                    = 0x00000002,
12492TMDS_DVO_MUX_SELECT_RESERVED             = 0x00000003,
12493} TMDS_DVO_MUX_SELECT;
12494
12495/*
12496 * DACA_SOFT_RESET enum
12497 */
12498
12499typedef enum DACA_SOFT_RESET {
12500DACA_SOFT_RESET_0                        = 0x00000000,
12501DACA_SOFT_RESET_1                        = 0x00000001,
12502} DACA_SOFT_RESET;
12503
12504/*
12505 * I2S0_SPDIF0_SOFT_RESET enum
12506 */
12507
12508typedef enum I2S0_SPDIF0_SOFT_RESET {
12509I2S0_SPDIF0_SOFT_RESET_0                 = 0x00000000,
12510I2S0_SPDIF0_SOFT_RESET_1                 = 0x00000001,
12511} I2S0_SPDIF0_SOFT_RESET;
12512
12513/*
12514 * I2S1_SOFT_RESET enum
12515 */
12516
12517typedef enum I2S1_SOFT_RESET {
12518I2S1_SOFT_RESET_0                        = 0x00000000,
12519I2S1_SOFT_RESET_1                        = 0x00000001,
12520} I2S1_SOFT_RESET;
12521
12522/*
12523 * SPDIF1_SOFT_RESET enum
12524 */
12525
12526typedef enum SPDIF1_SOFT_RESET {
12527SPDIF1_SOFT_RESET_0                      = 0x00000000,
12528SPDIF1_SOFT_RESET_1                      = 0x00000001,
12529} SPDIF1_SOFT_RESET;
12530
12531/*
12532 * DB_CLK_SOFT_RESET enum
12533 */
12534
12535typedef enum DB_CLK_SOFT_RESET {
12536DB_CLK_SOFT_RESET_0                      = 0x00000000,
12537DB_CLK_SOFT_RESET_1                      = 0x00000001,
12538} DB_CLK_SOFT_RESET;
12539
12540/*
12541 * FMT0_SOFT_RESET enum
12542 */
12543
12544typedef enum FMT0_SOFT_RESET {
12545FMT0_SOFT_RESET_0                        = 0x00000000,
12546FMT0_SOFT_RESET_1                        = 0x00000001,
12547} FMT0_SOFT_RESET;
12548
12549/*
12550 * FMT1_SOFT_RESET enum
12551 */
12552
12553typedef enum FMT1_SOFT_RESET {
12554FMT1_SOFT_RESET_0                        = 0x00000000,
12555FMT1_SOFT_RESET_1                        = 0x00000001,
12556} FMT1_SOFT_RESET;
12557
12558/*
12559 * FMT2_SOFT_RESET enum
12560 */
12561
12562typedef enum FMT2_SOFT_RESET {
12563FMT2_SOFT_RESET_0                        = 0x00000000,
12564FMT2_SOFT_RESET_1                        = 0x00000001,
12565} FMT2_SOFT_RESET;
12566
12567/*
12568 * FMT3_SOFT_RESET enum
12569 */
12570
12571typedef enum FMT3_SOFT_RESET {
12572FMT3_SOFT_RESET_0                        = 0x00000000,
12573FMT3_SOFT_RESET_1                        = 0x00000001,
12574} FMT3_SOFT_RESET;
12575
12576/*
12577 * FMT4_SOFT_RESET enum
12578 */
12579
12580typedef enum FMT4_SOFT_RESET {
12581FMT4_SOFT_RESET_0                        = 0x00000000,
12582FMT4_SOFT_RESET_1                        = 0x00000001,
12583} FMT4_SOFT_RESET;
12584
12585/*
12586 * FMT5_SOFT_RESET enum
12587 */
12588
12589typedef enum FMT5_SOFT_RESET {
12590FMT5_SOFT_RESET_0                        = 0x00000000,
12591FMT5_SOFT_RESET_1                        = 0x00000001,
12592} FMT5_SOFT_RESET;
12593
12594/*
12595 * MVP_SOFT_RESET enum
12596 */
12597
12598typedef enum MVP_SOFT_RESET {
12599MVP_SOFT_RESET_0                         = 0x00000000,
12600MVP_SOFT_RESET_1                         = 0x00000001,
12601} MVP_SOFT_RESET;
12602
12603/*
12604 * ABM_SOFT_RESET enum
12605 */
12606
12607typedef enum ABM_SOFT_RESET {
12608ABM_SOFT_RESET_0                         = 0x00000000,
12609ABM_SOFT_RESET_1                         = 0x00000001,
12610} ABM_SOFT_RESET;
12611
12612/*
12613 * DVO_SOFT_RESET enum
12614 */
12615
12616typedef enum DVO_SOFT_RESET {
12617DVO_SOFT_RESET_0                         = 0x00000000,
12618DVO_SOFT_RESET_1                         = 0x00000001,
12619} DVO_SOFT_RESET;
12620
12621/*
12622 * DIGA_FE_SOFT_RESET enum
12623 */
12624
12625typedef enum DIGA_FE_SOFT_RESET {
12626DIGA_FE_SOFT_RESET_0                     = 0x00000000,
12627DIGA_FE_SOFT_RESET_1                     = 0x00000001,
12628} DIGA_FE_SOFT_RESET;
12629
12630/*
12631 * DIGA_BE_SOFT_RESET enum
12632 */
12633
12634typedef enum DIGA_BE_SOFT_RESET {
12635DIGA_BE_SOFT_RESET_0                     = 0x00000000,
12636DIGA_BE_SOFT_RESET_1                     = 0x00000001,
12637} DIGA_BE_SOFT_RESET;
12638
12639/*
12640 * DIGB_FE_SOFT_RESET enum
12641 */
12642
12643typedef enum DIGB_FE_SOFT_RESET {
12644DIGB_FE_SOFT_RESET_0                     = 0x00000000,
12645DIGB_FE_SOFT_RESET_1                     = 0x00000001,
12646} DIGB_FE_SOFT_RESET;
12647
12648/*
12649 * DIGB_BE_SOFT_RESET enum
12650 */
12651
12652typedef enum DIGB_BE_SOFT_RESET {
12653DIGB_BE_SOFT_RESET_0                     = 0x00000000,
12654DIGB_BE_SOFT_RESET_1                     = 0x00000001,
12655} DIGB_BE_SOFT_RESET;
12656
12657/*
12658 * DIGC_FE_SOFT_RESET enum
12659 */
12660
12661typedef enum DIGC_FE_SOFT_RESET {
12662DIGC_FE_SOFT_RESET_0                     = 0x00000000,
12663DIGC_FE_SOFT_RESET_1                     = 0x00000001,
12664} DIGC_FE_SOFT_RESET;
12665
12666/*
12667 * DIGC_BE_SOFT_RESET enum
12668 */
12669
12670typedef enum DIGC_BE_SOFT_RESET {
12671DIGC_BE_SOFT_RESET_0                     = 0x00000000,
12672DIGC_BE_SOFT_RESET_1                     = 0x00000001,
12673} DIGC_BE_SOFT_RESET;
12674
12675/*
12676 * DIGD_FE_SOFT_RESET enum
12677 */
12678
12679typedef enum DIGD_FE_SOFT_RESET {
12680DIGD_FE_SOFT_RESET_0                     = 0x00000000,
12681DIGD_FE_SOFT_RESET_1                     = 0x00000001,
12682} DIGD_FE_SOFT_RESET;
12683
12684/*
12685 * DIGD_BE_SOFT_RESET enum
12686 */
12687
12688typedef enum DIGD_BE_SOFT_RESET {
12689DIGD_BE_SOFT_RESET_0                     = 0x00000000,
12690DIGD_BE_SOFT_RESET_1                     = 0x00000001,
12691} DIGD_BE_SOFT_RESET;
12692
12693/*
12694 * DIGE_FE_SOFT_RESET enum
12695 */
12696
12697typedef enum DIGE_FE_SOFT_RESET {
12698DIGE_FE_SOFT_RESET_0                     = 0x00000000,
12699DIGE_FE_SOFT_RESET_1                     = 0x00000001,
12700} DIGE_FE_SOFT_RESET;
12701
12702/*
12703 * DIGE_BE_SOFT_RESET enum
12704 */
12705
12706typedef enum DIGE_BE_SOFT_RESET {
12707DIGE_BE_SOFT_RESET_0                     = 0x00000000,
12708DIGE_BE_SOFT_RESET_1                     = 0x00000001,
12709} DIGE_BE_SOFT_RESET;
12710
12711/*
12712 * DIGF_FE_SOFT_RESET enum
12713 */
12714
12715typedef enum DIGF_FE_SOFT_RESET {
12716DIGF_FE_SOFT_RESET_0                     = 0x00000000,
12717DIGF_FE_SOFT_RESET_1                     = 0x00000001,
12718} DIGF_FE_SOFT_RESET;
12719
12720/*
12721 * DIGF_BE_SOFT_RESET enum
12722 */
12723
12724typedef enum DIGF_BE_SOFT_RESET {
12725DIGF_BE_SOFT_RESET_0                     = 0x00000000,
12726DIGF_BE_SOFT_RESET_1                     = 0x00000001,
12727} DIGF_BE_SOFT_RESET;
12728
12729/*
12730 * DIGG_FE_SOFT_RESET enum
12731 */
12732
12733typedef enum DIGG_FE_SOFT_RESET {
12734DIGG_FE_SOFT_RESET_0                     = 0x00000000,
12735DIGG_FE_SOFT_RESET_1                     = 0x00000001,
12736} DIGG_FE_SOFT_RESET;
12737
12738/*
12739 * DIGG_BE_SOFT_RESET enum
12740 */
12741
12742typedef enum DIGG_BE_SOFT_RESET {
12743DIGG_BE_SOFT_RESET_0                     = 0x00000000,
12744DIGG_BE_SOFT_RESET_1                     = 0x00000001,
12745} DIGG_BE_SOFT_RESET;
12746
12747/*
12748 * DPDBG_SOFT_RESET enum
12749 */
12750
12751typedef enum DPDBG_SOFT_RESET {
12752DPDBG_SOFT_RESET_0                       = 0x00000000,
12753DPDBG_SOFT_RESET_1                       = 0x00000001,
12754} DPDBG_SOFT_RESET;
12755
12756/*
12757 * DIGLPA_FE_SOFT_RESET enum
12758 */
12759
12760typedef enum DIGLPA_FE_SOFT_RESET {
12761DIGLPA_FE_SOFT_RESET_0                   = 0x00000000,
12762DIGLPA_FE_SOFT_RESET_1                   = 0x00000001,
12763} DIGLPA_FE_SOFT_RESET;
12764
12765/*
12766 * DIGLPA_BE_SOFT_RESET enum
12767 */
12768
12769typedef enum DIGLPA_BE_SOFT_RESET {
12770DIGLPA_BE_SOFT_RESET_0                   = 0x00000000,
12771DIGLPA_BE_SOFT_RESET_1                   = 0x00000001,
12772} DIGLPA_BE_SOFT_RESET;
12773
12774/*
12775 * DIGLPB_FE_SOFT_RESET enum
12776 */
12777
12778typedef enum DIGLPB_FE_SOFT_RESET {
12779DIGLPB_FE_SOFT_RESET_0                   = 0x00000000,
12780DIGLPB_FE_SOFT_RESET_1                   = 0x00000001,
12781} DIGLPB_FE_SOFT_RESET;
12782
12783/*
12784 * DIGLPB_BE_SOFT_RESET enum
12785 */
12786
12787typedef enum DIGLPB_BE_SOFT_RESET {
12788DIGLPB_BE_SOFT_RESET_0                   = 0x00000000,
12789DIGLPB_BE_SOFT_RESET_1                   = 0x00000001,
12790} DIGLPB_BE_SOFT_RESET;
12791
12792/*
12793 * GENERICA_STEREOSYNC_SEL enum
12794 */
12795
12796typedef enum GENERICA_STEREOSYNC_SEL {
12797GENERICA_STEREOSYNC_SEL_D1               = 0x00000000,
12798GENERICA_STEREOSYNC_SEL_D2               = 0x00000001,
12799GENERICA_STEREOSYNC_SEL_D3               = 0x00000002,
12800GENERICA_STEREOSYNC_SEL_D4               = 0x00000003,
12801GENERICA_STEREOSYNC_SEL_D5               = 0x00000004,
12802GENERICA_STEREOSYNC_SEL_D6               = 0x00000005,
12803GENERICA_STEREOSYNC_SEL_RESERVED         = 0x00000006,
12804} GENERICA_STEREOSYNC_SEL;
12805
12806/*
12807 * GENERICB_STEREOSYNC_SEL enum
12808 */
12809
12810typedef enum GENERICB_STEREOSYNC_SEL {
12811GENERICB_STEREOSYNC_SEL_D1               = 0x00000000,
12812GENERICB_STEREOSYNC_SEL_D2               = 0x00000001,
12813GENERICB_STEREOSYNC_SEL_D3               = 0x00000002,
12814GENERICB_STEREOSYNC_SEL_D4               = 0x00000003,
12815GENERICB_STEREOSYNC_SEL_D5               = 0x00000004,
12816GENERICB_STEREOSYNC_SEL_D6               = 0x00000005,
12817GENERICB_STEREOSYNC_SEL_RESERVED         = 0x00000006,
12818} GENERICB_STEREOSYNC_SEL;
12819
12820/*
12821 * DCO_DBG_BLOCK_SEL enum
12822 */
12823
12824typedef enum DCO_DBG_BLOCK_SEL {
12825DCO_DBG_BLOCK_SEL_DCO                    = 0x00000000,
12826DCO_DBG_BLOCK_SEL_ABM                    = 0x00000001,
12827DCO_DBG_BLOCK_SEL_DVO                    = 0x00000002,
12828DCO_DBG_BLOCK_SEL_DAC                    = 0x00000003,
12829DCO_DBG_BLOCK_SEL_MVP                    = 0x00000004,
12830DCO_DBG_BLOCK_SEL_FMT0                   = 0x00000005,
12831DCO_DBG_BLOCK_SEL_FMT1                   = 0x00000006,
12832DCO_DBG_BLOCK_SEL_FMT2                   = 0x00000007,
12833DCO_DBG_BLOCK_SEL_FMT3                   = 0x00000008,
12834DCO_DBG_BLOCK_SEL_FMT4                   = 0x00000009,
12835DCO_DBG_BLOCK_SEL_FMT5                   = 0x0000000a,
12836DCO_DBG_BLOCK_SEL_DIGFE_A                = 0x0000000b,
12837DCO_DBG_BLOCK_SEL_DIGFE_B                = 0x0000000c,
12838DCO_DBG_BLOCK_SEL_DIGFE_C                = 0x0000000d,
12839DCO_DBG_BLOCK_SEL_DIGFE_D                = 0x0000000e,
12840DCO_DBG_BLOCK_SEL_DIGFE_E                = 0x0000000f,
12841DCO_DBG_BLOCK_SEL_DIGFE_F                = 0x00000010,
12842DCO_DBG_BLOCK_SEL_DIGFE_G                = 0x00000011,
12843DCO_DBG_BLOCK_SEL_DIGA                   = 0x00000012,
12844DCO_DBG_BLOCK_SEL_DIGB                   = 0x00000013,
12845DCO_DBG_BLOCK_SEL_DIGC                   = 0x00000014,
12846DCO_DBG_BLOCK_SEL_DIGD                   = 0x00000015,
12847DCO_DBG_BLOCK_SEL_DIGE                   = 0x00000016,
12848DCO_DBG_BLOCK_SEL_DIGF                   = 0x00000017,
12849DCO_DBG_BLOCK_SEL_DIGG                   = 0x00000018,
12850DCO_DBG_BLOCK_SEL_DPFE_A                 = 0x00000019,
12851DCO_DBG_BLOCK_SEL_DPFE_B                 = 0x0000001a,
12852DCO_DBG_BLOCK_SEL_DPFE_C                 = 0x0000001b,
12853DCO_DBG_BLOCK_SEL_DPFE_D                 = 0x0000001c,
12854DCO_DBG_BLOCK_SEL_DPFE_E                 = 0x0000001d,
12855DCO_DBG_BLOCK_SEL_DPFE_F                 = 0x0000001e,
12856DCO_DBG_BLOCK_SEL_DPFE_G                 = 0x0000001f,
12857DCO_DBG_BLOCK_SEL_DPA                    = 0x00000020,
12858DCO_DBG_BLOCK_SEL_DPB                    = 0x00000021,
12859DCO_DBG_BLOCK_SEL_DPC                    = 0x00000022,
12860DCO_DBG_BLOCK_SEL_DPD                    = 0x00000023,
12861DCO_DBG_BLOCK_SEL_DPE                    = 0x00000024,
12862DCO_DBG_BLOCK_SEL_DPF                    = 0x00000025,
12863DCO_DBG_BLOCK_SEL_DPG                    = 0x00000026,
12864DCO_DBG_BLOCK_SEL_AUX0                   = 0x00000027,
12865DCO_DBG_BLOCK_SEL_AUX1                   = 0x00000028,
12866DCO_DBG_BLOCK_SEL_AUX2                   = 0x00000029,
12867DCO_DBG_BLOCK_SEL_AUX3                   = 0x0000002a,
12868DCO_DBG_BLOCK_SEL_AUX4                   = 0x0000002b,
12869DCO_DBG_BLOCK_SEL_AUX5                   = 0x0000002c,
12870DCO_DBG_BLOCK_SEL_PERFMON_DCO            = 0x0000002d,
12871DCO_DBG_BLOCK_SEL_AUDIO_OUT              = 0x0000002e,
12872DCO_DBG_BLOCK_SEL_DIGLPFEA               = 0x0000002f,
12873DCO_DBG_BLOCK_SEL_DIGLPFEB               = 0x00000030,
12874DCO_DBG_BLOCK_SEL_DIGLPA                 = 0x00000031,
12875DCO_DBG_BLOCK_SEL_DIGLPB                 = 0x00000032,
12876DCO_DBG_BLOCK_SEL_DPLPFEA                = 0x00000033,
12877DCO_DBG_BLOCK_SEL_DPLPFEB                = 0x00000034,
12878DCO_DBG_BLOCK_SEL_DPLPA                  = 0x00000035,
12879DCO_DBG_BLOCK_SEL_DPLPB                  = 0x00000036,
12880} DCO_DBG_BLOCK_SEL;
12881
12882/*
12883 * DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE enum
12884 */
12885
12886typedef enum DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE {
12887DCO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL       = 0x00000000,
12888DCO_HDMI_RXSTATUS_TIMER_TYPE_PULSE       = 0x00000001,
12889} DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE;
12890
12891/*
12892 * FMT420_MEMORY_SOURCE_SEL enum
12893 */
12894
12895typedef enum FMT420_MEMORY_SOURCE_SEL {
12896FMT420_MEMORY_SOURCE_SEL_FMT0            = 0x00000000,
12897FMT420_MEMORY_SOURCE_SEL_FMT1            = 0x00000001,
12898FMT420_MEMORY_SOURCE_SEL_FMT2            = 0x00000002,
12899FMT420_MEMORY_SOURCE_SEL_FMT3            = 0x00000003,
12900FMT420_MEMORY_SOURCE_SEL_FMT4            = 0x00000004,
12901FMT420_MEMORY_SOURCE_SEL_FMT5            = 0x00000005,
12902FMT420_MEMORY_SOURCE_SEL_FMT_RESERVED    = 0x00000006,
12903} FMT420_MEMORY_SOURCE_SEL;
12904
12905/*******************************************************
12906 * DOUT_I2C Enums
12907 *******************************************************/
12908
12909/*
12910 * DOUT_I2C_CONTROL_GO enum
12911 */
12912
12913typedef enum DOUT_I2C_CONTROL_GO {
12914DOUT_I2C_CONTROL_STOP_TRANSFER           = 0x00000000,
12915DOUT_I2C_CONTROL_START_TRANSFER          = 0x00000001,
12916} DOUT_I2C_CONTROL_GO;
12917
12918/*
12919 * DOUT_I2C_CONTROL_SOFT_RESET enum
12920 */
12921
12922typedef enum DOUT_I2C_CONTROL_SOFT_RESET {
12923DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0x00000000,
12924DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER    = 0x00000001,
12925} DOUT_I2C_CONTROL_SOFT_RESET;
12926
12927/*
12928 * DOUT_I2C_CONTROL_SEND_RESET enum
12929 */
12930
12931typedef enum DOUT_I2C_CONTROL_SEND_RESET {
12932DOUT_I2C_CONTROL__NOT_SEND_RESET         = 0x00000000,
12933DOUT_I2C_CONTROL__SEND_RESET             = 0x00000001,
12934} DOUT_I2C_CONTROL_SEND_RESET;
12935
12936/*
12937 * DOUT_I2C_CONTROL_SW_STATUS_RESET enum
12938 */
12939
12940typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET {
12941DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS     = 0x00000000,
12942DOUT_I2C_CONTROL_RESET_SW_STATUS         = 0x00000001,
12943} DOUT_I2C_CONTROL_SW_STATUS_RESET;
12944
12945/*
12946 * DOUT_I2C_CONTROL_DDC_SELECT enum
12947 */
12948
12949typedef enum DOUT_I2C_CONTROL_DDC_SELECT {
12950DOUT_I2C_CONTROL_SELECT_DDC1             = 0x00000000,
12951DOUT_I2C_CONTROL_SELECT_DDC2             = 0x00000001,
12952DOUT_I2C_CONTROL_SELECT_DDC3             = 0x00000002,
12953DOUT_I2C_CONTROL_SELECT_DDC4             = 0x00000003,
12954DOUT_I2C_CONTROL_SELECT_DDC5             = 0x00000004,
12955DOUT_I2C_CONTROL_SELECT_DDC6             = 0x00000005,
12956DOUT_I2C_CONTROL_SELECT_DDCVGA           = 0x00000006,
12957} DOUT_I2C_CONTROL_DDC_SELECT;
12958
12959/*
12960 * DOUT_I2C_CONTROL_TRANSACTION_COUNT enum
12961 */
12962
12963typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT {
12964DOUT_I2C_CONTROL_TRANS0                  = 0x00000000,
12965DOUT_I2C_CONTROL_TRANS0_TRANS1           = 0x00000001,
12966DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2    = 0x00000002,
12967DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3  = 0x00000003,
12968} DOUT_I2C_CONTROL_TRANSACTION_COUNT;
12969
12970/*
12971 * DOUT_I2C_CONTROL_DBG_REF_SEL enum
12972 */
12973
12974typedef enum DOUT_I2C_CONTROL_DBG_REF_SEL {
12975DOUT_I2C_CONTROL_NORMAL_DEBUG            = 0x00000000,
12976DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG    = 0x00000001,
12977} DOUT_I2C_CONTROL_DBG_REF_SEL;
12978
12979/*
12980 * DOUT_I2C_ARBITRATION_SW_PRIORITY enum
12981 */
12982
12983typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY {
12984DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL  = 0x00000000,
12985DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH    = 0x00000001,
12986DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 0x00000002,
12987DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 0x00000003,
12988} DOUT_I2C_ARBITRATION_SW_PRIORITY;
12989
12990/*
12991 * DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO enum
12992 */
12993
12994typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO {
12995DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED    = 0x00000000,
12996DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED   = 0x00000001,
12997} DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO;
12998
12999/*
13000 * DOUT_I2C_ARBITRATION_ABORT_XFER enum

13001 */
13002
13003typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER {
13004DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0x00000000,
13005DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER  = 0x00000001,
13006} DOUT_I2C_ARBITRATION_ABORT_XFER;
13007
13008/*
13009 * DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ enum
13010 */
13011
13012typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ {
13013DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0x00000000,
13014DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ    = 0x00000001,
13015} DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ;
13016
13017/*
13018 * DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG enum
13019 */
13020
13021typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG {
13022DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0x00000000,
13023DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG  = 0x00000001,
13024} DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG;
13025
13026/*
13027 * DOUT_I2C_ACK enum
13028 */
13029
13030typedef enum DOUT_I2C_ACK {
13031DOUT_I2C_NO_ACK                          = 0x00000000,
13032DOUT_I2C_ACK_TO_CLEAN                    = 0x00000001,
13033} DOUT_I2C_ACK;
13034
13035/*
13036 * DOUT_I2C_DDC_SPEED_THRESHOLD enum
13037 */
13038
13039typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD {
13040DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO  = 0x00000000,
13041DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE  = 0x00000001,
13042DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE  = 0x00000002,
13043DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE  = 0x00000003,
13044} DOUT_I2C_DDC_SPEED_THRESHOLD;
13045
13046/*
13047 * DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN enum
13048 */
13049
13050typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN {
13051DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR  = 0x00000000,
13052DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA     = 0x00000001,
13053} DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN;
13054
13055/*
13056 * DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL enum
13057 */
13058
13059typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL {
13060DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS  = 0x00000000,
13061DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS  = 0x00000001,
13062} DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL;
13063
13064/*
13065 * DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE enum
13066 */
13067
13068typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE {
13069DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT   = 0x00000000,
13070DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT  = 0x00000001,
13071} DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE;
13072
13073/*
13074 * DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN enum
13075 */
13076
13077typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN {
13078DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR  = 0x00000000,
13079DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL     = 0x00000001,
13080} DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN;
13081
13082/*
13083 * DOUT_I2C_TRANSACTION_STOP_ON_NACK enum
13084 */
13085
13086typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK {
13087DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS  = 0x00000000,
13088DOUT_I2C_TRANSACTION_STOP_ALL_TRANS      = 0x00000001,
13089} DOUT_I2C_TRANSACTION_STOP_ON_NACK;
13090
13091/*
13092 * DOUT_I2C_DATA_INDEX_WRITE enum
13093 */
13094
13095typedef enum DOUT_I2C_DATA_INDEX_WRITE {
13096DOUT_I2C_DATA__NOT_INDEX_WRITE           = 0x00000000,
13097DOUT_I2C_DATA__INDEX_WRITE               = 0x00000001,
13098} DOUT_I2C_DATA_INDEX_WRITE;
13099
13100/*
13101 * DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET enum
13102 */
13103
13104typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET {
13105DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0x00000000,
13106DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION  = 0x00000001,
13107} DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET;
13108
13109/*
13110 * DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE enum
13111 */
13112
13113typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE {
13114DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL  = 0x00000000,
13115DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE  = 0x00000001,
13116} DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE;
13117
13118/*******************************************************
13119 * FBC Enums
13120 *******************************************************/
13121
13122/*
13123 * FBC_IDLE_MASK_MASK_BITS enum
13124 */
13125
13126typedef enum FBC_IDLE_MASK_MASK_BITS {
13127FBC_IDLE_MASK_DISP_REG_UPDATE            = 0x00000000,
13128FBC_IDLE_MASK_RESERVED1                  = 0x00000001,
13129FBC_IDLE_MASK_FBC_GRPH_COMP_EN           = 0x00000002,
13130FBC_IDLE_MASK_FBC_MIN_COMPRESSION        = 0x00000003,
13131FBC_IDLE_MASK_FBC_ALPHA_COMP_EN          = 0x00000004,
13132FBC_IDLE_MASK_FBC_ZERO_ALPHA_CHUNK_SKIP_EN  = 0x00000005,
13133FBC_IDLE_MASK_FBC_FORCE_COPY_TO_COMP_BUF  = 0x00000006,
13134FBC_IDLE_MASK_RESERVED7                  = 0x00000007,
13135FBC_IDLE_MASK_RESERVED8                  = 0x00000008,
13136FBC_IDLE_MASK_RESERVED9                  = 0x00000009,
13137FBC_IDLE_MASK_RESERVED10                 = 0x0000000a,
13138FBC_IDLE_MASK_RESERVED11                 = 0x0000000b,
13139FBC_IDLE_MASK_RESERVED12                 = 0x0000000c,
13140FBC_IDLE_MASK_RESERVED13                 = 0x0000000d,
13141FBC_IDLE_MASK_RESERVED14                 = 0x0000000e,
13142FBC_IDLE_MASK_RESERVED15                 = 0x0000000f,
13143FBC_IDLE_MASK_RESERVED16                 = 0x00000010,
13144FBC_IDLE_MASK_RESERVED17                 = 0x00000011,
13145FBC_IDLE_MASK_RESERVED18                 = 0x00000012,
13146FBC_IDLE_MASK_RESERVED19                 = 0x00000013,
13147FBC_IDLE_MASK_RESERVED20                 = 0x00000014,
13148FBC_IDLE_MASK_RESERVED21                 = 0x00000015,
13149FBC_IDLE_MASK_RESERVED22                 = 0x00000016,
13150FBC_IDLE_MASK_RESERVED23                 = 0x00000017,
13151FBC_IDLE_MASK_MC_HIT_REGION_0            = 0x00000018,
13152FBC_IDLE_MASK_MC_HIT_REGION_1            = 0x00000019,
13153FBC_IDLE_MASK_MC_HIT_REGION_2            = 0x0000001a,
13154FBC_IDLE_MASK_MC_HIT_REGION_3            = 0x0000001b,
13155FBC_IDLE_MASK_MC_WRITE                   = 0x0000001c,
13156FBC_IDLE_MASK_RESERVED29                 = 0x0000001d,
13157FBC_IDLE_MASK_RESERVED30                 = 0x0000001e,
13158FBC_IDLE_MASK_RESERVED31                 = 0x0000001f,
13159} FBC_IDLE_MASK_MASK_BITS;
13160
13161/*******************************************************
13162 * DPCSRX Enums
13163 *******************************************************/
13164
13165/*
13166 * DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL enum
13167 */
13168
13169typedef enum DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL {
13170DPCSRX_BPHY_PCS_RX0_CLK                  = 0x00000000,
13171DPCSRX_BPHY_PCS_RX1_CLK                  = 0x00000001,
13172DPCSRX_BPHY_PCS_RX2_CLK                  = 0x00000002,
13173DPCSRX_BPHY_PCS_RX3_CLK                  = 0x00000003,
13174} DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL;
13175
13176/*
13177 * DPCSRX_DBG_CFGCLK_SEL enum
13178 */
13179
13180typedef enum DPCSRX_DBG_CFGCLK_SEL {
13181DPCSRX_DBG_CFGCLK_SEL_DC_DPCS_INF        = 0x00000000,
13182DPCSRX_DBG_CFGCLK_SEL_DPCS_BPHY_INF      = 0x00000001,
13183DPCSRX_DBG_CFGCLK_SEL_CBUS_SLAVE         = 0x00000002,
13184DPCSRX_DBG_CFGCLK_SEL_CBUS_MASTER        = 0x00000003,
13185} DPCSRX_DBG_CFGCLK_SEL;
13186
13187/*
13188 * DPCSRX_RX_SYMCLK_SEL enum
13189 */
13190
13191typedef enum DPCSRX_RX_SYMCLK_SEL {
13192DPCSRX_DBG_RX_SYMCLK_SEL_OUT0            = 0x00000000,
13193DPCSRX_DBG_RX_SYMCLK_SEL_OUT1            = 0x00000001,
13194DPCSRX_DBG_RX_SYMCLK_SEL_INT             = 0x00000002,
13195} DPCSRX_RX_SYMCLK_SEL;
13196
13197/*******************************************************
13198 * DPCSTX Enums
13199 *******************************************************/
13200
13201/*
13202 * DPCSTX_DBG_CFGCLK_SEL enum
13203 */
13204
13205typedef enum DPCSTX_DBG_CFGCLK_SEL {
13206DPCSTX_DBG_CFGCLK_SEL_DC_DPCS_INF        = 0x00000000,
13207DPCSTX_DBG_CFGCLK_SEL_DPCS_BPHY_INF      = 0x00000001,
13208DPCSTX_DBG_CFGCLK_SEL_CBUS_SLAVE         = 0x00000002,
13209DPCSTX_DBG_CFGCLK_SEL_CBUS_MASTER        = 0x00000003,
13210} DPCSTX_DBG_CFGCLK_SEL;
13211
13212/*
13213 * DPCSTX_TX_SYMCLK_SEL enum
13214 */
13215
13216typedef enum DPCSTX_TX_SYMCLK_SEL {
13217DPCSTX_DBG_TX_SYMCLK_SEL_IN0             = 0x00000000,
13218DPCSTX_DBG_TX_SYMCLK_SEL_IN1             = 0x00000001,
13219DPCSTX_DBG_TX_SYMCLK_SEL_FIFO_WR         = 0x00000002,
13220} DPCSTX_TX_SYMCLK_SEL;
13221
13222/*
13223 * DPCSTX_TX_SYMCLK_DIV2_SEL enum
13224 */
13225
13226typedef enum DPCSTX_TX_SYMCLK_DIV2_SEL {
13227DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT0       = 0x00000000,
13228DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT1       = 0x00000001,
13229DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT2       = 0x00000002,
13230DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT3       = 0x00000003,
13231DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_FIFO_RD    = 0x00000004,
13232DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_INT        = 0x00000005,
13233} DPCSTX_TX_SYMCLK_DIV2_SEL;
13234
13235/*******************************************************
13236 * CB Enums
13237 *******************************************************/
13238
13239/*
13240 * SurfaceNumber enum
13241 */
13242
13243typedef enum SurfaceNumber {
13244NUMBER_UNORM                             = 0x00000000,
13245NUMBER_SNORM                             = 0x00000001,
13246NUMBER_USCALED                           = 0x00000002,
13247NUMBER_SSCALED                           = 0x00000003,
13248NUMBER_UINT                              = 0x00000004,
13249NUMBER_SINT                              = 0x00000005,
13250NUMBER_SRGB                              = 0x00000006,
13251NUMBER_FLOAT                             = 0x00000007,
13252} SurfaceNumber;
13253
13254/*
13255 * SurfaceSwap enum
13256 */
13257
13258typedef enum SurfaceSwap {
13259SWAP_STD                                 = 0x00000000,
13260SWAP_ALT                                 = 0x00000001,
13261SWAP_STD_REV                             = 0x00000002,
13262SWAP_ALT_REV                             = 0x00000003,
13263} SurfaceSwap;
13264
13265/*
13266 * CBMode enum
13267 */
13268
13269typedef enum CBMode {
13270CB_DISABLE                               = 0x00000000,
13271CB_NORMAL                                = 0x00000001,
13272CB_ELIMINATE_FAST_CLEAR                  = 0x00000002,
13273CB_RESOLVE                               = 0x00000003,
13274CB_DECOMPRESS                            = 0x00000004,
13275CB_FMASK_DECOMPRESS                      = 0x00000005,
13276CB_DCC_DECOMPRESS                        = 0x00000006,
13277} CBMode;
13278
13279/*
13280 * RoundMode enum
13281 */
13282
13283typedef enum RoundMode {
13284ROUND_BY_HALF                            = 0x00000000,
13285ROUND_TRUNCATE                           = 0x00000001,
13286} RoundMode;
13287
13288/*
13289 * SourceFormat enum
13290 */
13291
13292typedef enum SourceFormat {
13293EXPORT_4C_32BPC                          = 0x00000000,
13294EXPORT_4C_16BPC                          = 0x00000001,
13295EXPORT_2C_32BPC_GR                       = 0x00000002,
13296EXPORT_2C_32BPC_AR                       = 0x00000003,
13297} SourceFormat;
13298
13299/*
13300 * BlendOp enum
13301 */
13302
13303typedef enum BlendOp {
13304BLEND_ZERO                               = 0x00000000,
13305BLEND_ONE                                = 0x00000001,
13306BLEND_SRC_COLOR                          = 0x00000002,
13307BLEND_ONE_MINUS_SRC_COLOR                = 0x00000003,
13308BLEND_SRC_ALPHA                          = 0x00000004,
13309BLEND_ONE_MINUS_SRC_ALPHA                = 0x00000005,
13310BLEND_DST_ALPHA                          = 0x00000006,
13311BLEND_ONE_MINUS_DST_ALPHA                = 0x00000007,
13312BLEND_DST_COLOR                          = 0x00000008,
13313BLEND_ONE_MINUS_DST_COLOR                = 0x00000009,
13314BLEND_SRC_ALPHA_SATURATE                 = 0x0000000a,
13315BLEND_BOTH_SRC_ALPHA                     = 0x0000000b,
13316BLEND_BOTH_INV_SRC_ALPHA                 = 0x0000000c,
13317BLEND_CONSTANT_COLOR                     = 0x0000000d,
13318BLEND_ONE_MINUS_CONSTANT_COLOR           = 0x0000000e,
13319BLEND_SRC1_COLOR                         = 0x0000000f,
13320BLEND_INV_SRC1_COLOR                     = 0x00000010,
13321BLEND_SRC1_ALPHA                         = 0x00000011,
13322BLEND_INV_SRC1_ALPHA                     = 0x00000012,
13323BLEND_CONSTANT_ALPHA                     = 0x00000013,
13324BLEND_ONE_MINUS_CONSTANT_ALPHA           = 0x00000014,
13325} BlendOp;
13326
13327/*
13328 * CombFunc enum
13329 */
13330
13331typedef enum CombFunc {
13332COMB_DST_PLUS_SRC                        = 0x00000000,
13333COMB_SRC_MINUS_DST                       = 0x00000001,
13334COMB_MIN_DST_SRC                         = 0x00000002,
13335COMB_MAX_DST_SRC                         = 0x00000003,
13336COMB_DST_MINUS_SRC                       = 0x00000004,
13337} CombFunc;
13338
13339/*
13340 * BlendOpt enum
13341 */
13342
13343typedef enum BlendOpt {
13344FORCE_OPT_AUTO                           = 0x00000000,
13345FORCE_OPT_DISABLE                        = 0x00000001,
13346FORCE_OPT_ENABLE_IF_SRC_A_0              = 0x00000002,
13347FORCE_OPT_ENABLE_IF_SRC_RGB_0            = 0x00000003,
13348FORCE_OPT_ENABLE_IF_SRC_ARGB_0           = 0x00000004,
13349FORCE_OPT_ENABLE_IF_SRC_A_1              = 0x00000005,
13350FORCE_OPT_ENABLE_IF_SRC_RGB_1            = 0x00000006,
13351FORCE_OPT_ENABLE_IF_SRC_ARGB_1           = 0x00000007,
13352} BlendOpt;
13353
13354/*
13355 * CmaskCode enum
13356 */
13357
13358typedef enum CmaskCode {
13359CMASK_CLR00_F0                           = 0x00000000,
13360CMASK_CLR00_F1                           = 0x00000001,
13361CMASK_CLR00_F2                           = 0x00000002,
13362CMASK_CLR00_FX                           = 0x00000003,
13363CMASK_CLR01_F0                           = 0x00000004,
13364CMASK_CLR01_F1                           = 0x00000005,
13365CMASK_CLR01_F2                           = 0x00000006,
13366CMASK_CLR01_FX                           = 0x00000007,
13367CMASK_CLR10_F0                           = 0x00000008,
13368CMASK_CLR10_F1                           = 0x00000009,
13369CMASK_CLR10_F2                           = 0x0000000a,
13370CMASK_CLR10_FX                           = 0x0000000b,
13371CMASK_CLR11_F0                           = 0x0000000c,
13372CMASK_CLR11_F1                           = 0x0000000d,
13373CMASK_CLR11_F2                           = 0x0000000e,
13374CMASK_CLR11_FX                           = 0x0000000f,
13375} CmaskCode;
13376
13377/*
13378 * CmaskAddr enum
13379 */
13380
13381typedef enum CmaskAddr {
13382CMASK_ADDR_TILED                         = 0x00000000,
13383CMASK_ADDR_LINEAR                        = 0x00000001,
13384CMASK_ADDR_COMPATIBLE                    = 0x00000002,
13385} CmaskAddr;
13386
13387/*
13388 * MemArbMode enum
13389 */
13390
13391typedef enum MemArbMode {
13392MEM_ARB_MODE_FIXED                       = 0x00000000,
13393MEM_ARB_MODE_AGE                         = 0x00000001,
13394MEM_ARB_MODE_WEIGHT                      = 0x00000002,
13395MEM_ARB_MODE_BOTH                        = 0x00000003,
13396} MemArbMode;
13397
13398/*
13399 * CBPerfSel enum
13400 */
13401
13402typedef enum CBPerfSel {
13403CB_PERF_SEL_NONE                         = 0x00000000,
13404CB_PERF_SEL_BUSY                         = 0x00000001,
13405CB_PERF_SEL_CORE_SCLK_VLD                = 0x00000002,
13406CB_PERF_SEL_REG_SCLK0_VLD                = 0x00000003,
13407CB_PERF_SEL_REG_SCLK1_VLD                = 0x00000004,
13408CB_PERF_SEL_DRAWN_QUAD                   = 0x00000005,
13409CB_PERF_SEL_DRAWN_PIXEL                  = 0x00000006,
13410CB_PERF_SEL_DRAWN_QUAD_FRAGMENT          = 0x00000007,
13411CB_PERF_SEL_DRAWN_TILE                   = 0x00000008,
13412CB_PERF_SEL_DB_CB_TILE_VALID_READY       = 0x00000009,
13413CB_PERF_SEL_DB_CB_TILE_VALID_READYB      = 0x0000000a,
13414CB_PERF_SEL_DB_CB_TILE_VALIDB_READY      = 0x0000000b,
13415CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB     = 0x0000000c,
13416CB_PERF_SEL_CM_FC_TILE_VALID_READY       = 0x0000000d,
13417CB_PERF_SEL_CM_FC_TILE_VALID_READYB      = 0x0000000e,
13418CB_PERF_SEL_CM_FC_TILE_VALIDB_READY      = 0x0000000f,
13419CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB     = 0x00000010,
13420CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY  = 0x00000011,
13421CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB  = 0x00000012,
13422CB_PERF_SEL_DB_CB_LQUAD_VALID_READY      = 0x00000013,
13423CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB     = 0x00000014,
13424CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY     = 0x00000015,
13425CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB    = 0x00000016,
13426CB_PERF_SEL_LQUAD_NO_TILE                = 0x00000017,
13427CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R  = 0x00000018,
13428CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR  = 0x00000019,
13429CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR  = 0x0000001a,
13430CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR  = 0x0000001b,
13431CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR  = 0x0000001c,
13432CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR  = 0x0000001d,
13433CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR  = 0x0000001e,
13434CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT  = 0x0000001f,
13435CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID  = 0x00000020,
13436CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK  = 0x00000021,
13437CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK  = 0x00000022,
13438CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL  = 0x00000023,
13439CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY    = 0x00000024,
13440CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB   = 0x00000025,
13441CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY   = 0x00000026,
13442CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB  = 0x00000027,
13443CB_PERF_SEL_FOP_IN_VALID_READY           = 0x00000028,
13444CB_PERF_SEL_FOP_IN_VALID_READYB          = 0x00000029,
13445CB_PERF_SEL_FOP_IN_VALIDB_READY          = 0x0000002a,
13446CB_PERF_SEL_FOP_IN_VALIDB_READYB         = 0x0000002b,
13447CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY   = 0x0000002c,
13448CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB  = 0x0000002d,
13449CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY  = 0x0000002e,
13450CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB  = 0x0000002f,
13451CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY    = 0x00000030,
13452CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB   = 0x00000031,
13453CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY   = 0x00000032,
13454CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB  = 0x00000033,
13455CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY    = 0x00000034,
13456CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB   = 0x00000035,
13457CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY   = 0x00000036,
13458CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB  = 0x00000037,
13459CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY  = 0x00000038,
13460CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB  = 0x00000039,
13461CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY  = 0x0000003a,
13462CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB  = 0x0000003b,
13463CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY  = 0x0000003c,
13464CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB  = 0x0000003d,
13465CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY  = 0x0000003e,
13466CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB  = 0x0000003f,
13467CB_PERF_SEL_CC_BC_CS_FRAG_VALID          = 0x00000040,
13468CB_PERF_SEL_CM_CACHE_HIT                 = 0x00000041,
13469CB_PERF_SEL_CM_CACHE_TAG_MISS            = 0x00000042,
13470CB_PERF_SEL_CM_CACHE_SECTOR_MISS         = 0x00000043,
13471CB_PERF_SEL_CM_CACHE_REEVICTION_STALL    = 0x00000044,
13472CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL  = 0x00000045,
13473CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL  = 0x00000046,
13474CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL  = 0x00000047,
13475CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL   = 0x00000048,
13476CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL  = 0x00000049,
13477CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL    = 0x0000004a,
13478CB_PERF_SEL_CM_CACHE_STALL               = 0x0000004b,
13479CB_PERF_SEL_CM_CACHE_FLUSH               = 0x0000004c,
13480CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED        = 0x0000004d,
13481CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED     = 0x0000004e,
13482CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED  = 0x0000004f,
13483CB_PERF_SEL_FC_CACHE_HIT                 = 0x00000050,
13484CB_PERF_SEL_FC_CACHE_TAG_MISS            = 0x00000051,
13485CB_PERF_SEL_FC_CACHE_SECTOR_MISS         = 0x00000052,
13486CB_PERF_SEL_FC_CACHE_REEVICTION_STALL    = 0x00000053,
13487CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL  = 0x00000054,
13488CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL  = 0x00000055,
13489CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL  = 0x00000056,
13490CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL   = 0x00000057,
13491CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL  = 0x00000058,
13492CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL    = 0x00000059,
13493CB_PERF_SEL_FC_CACHE_STALL               = 0x0000005a,
13494CB_PERF_SEL_FC_CACHE_FLUSH               = 0x0000005b,
13495CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED        = 0x0000005c,
13496CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED     = 0x0000005d,
13497CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED  = 0x0000005e,
13498CB_PERF_SEL_CC_CACHE_HIT                 = 0x0000005f,
13499CB_PERF_SEL_CC_CACHE_TAG_MISS            = 0x00000060,
13500CB_PERF_SEL_CC_CACHE_SECTOR_MISS         = 0x00000061,
13501CB_PERF_SEL_CC_CACHE_REEVICTION_STALL    = 0x00000062,
13502CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL  = 0x00000063,
13503CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL  = 0x00000064,
13504CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL  = 0x00000065,
13505CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL   = 0x00000066,
13506CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL  = 0x00000067,
13507CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL    = 0x00000068,
13508CB_PERF_SEL_CC_CACHE_STALL               = 0x00000069,
13509CB_PERF_SEL_CC_CACHE_FLUSH               = 0x0000006a,
13510CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED        = 0x0000006b,
13511CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED     = 0x0000006c,
13512CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED  = 0x0000006d,
13513CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION  = 0x0000006e,
13514CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC  = 0x0000006f,
13515CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY     = 0x00000070,
13516CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB    = 0x00000071,
13517CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY    = 0x00000072,
13518CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB   = 0x00000073,
13519CB_PERF_SEL_CM_MC_WRITE_REQUEST          = 0x00000074,
13520CB_PERF_SEL_FC_MC_WRITE_REQUEST          = 0x00000075,
13521CB_PERF_SEL_CC_MC_WRITE_REQUEST          = 0x00000076,
13522CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT  = 0x00000077,
13523CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT  = 0x00000078,
13524CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT  = 0x00000079,
13525CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY     = 0x0000007a,
13526CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB    = 0x0000007b,
13527CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY    = 0x0000007c,
13528CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB   = 0x0000007d,
13529CB_PERF_SEL_CM_MC_READ_REQUEST           = 0x0000007e,
13530CB_PERF_SEL_FC_MC_READ_REQUEST           = 0x0000007f,
13531CB_PERF_SEL_CC_MC_READ_REQUEST           = 0x00000080,
13532CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT  = 0x00000081,
13533CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT  = 0x00000082,
13534CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT  = 0x00000083,
13535CB_PERF_SEL_CM_TQ_FULL                   = 0x00000084,
13536CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL  = 0x00000085,
13537CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL      = 0x00000086,
13538CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL      = 0x00000087,
13539CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL  = 0x00000088,
13540CB_PERF_SEL_FOP_FMASK_RAW_STALL          = 0x00000089,
13541CB_PERF_SEL_FOP_FMASK_BYPASS_STALL       = 0x0000008a,
13542CB_PERF_SEL_CC_SF_FULL                   = 0x0000008b,
13543CB_PERF_SEL_CC_RB_FULL                   = 0x0000008c,
13544CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL  = 0x0000008d,
13545CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL  = 0x0000008e,
13546CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL     = 0x0000008f,
13547CB_PERF_SEL_EVENT                        = 0x00000090,
13548CB_PERF_SEL_EVENT_CACHE_FLUSH_TS         = 0x00000091,
13549CB_PERF_SEL_EVENT_CONTEXT_DONE           = 0x00000092,
13550CB_PERF_SEL_EVENT_CACHE_FLUSH            = 0x00000093,
13551CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT  = 0x00000094,
13552CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT  = 0x00000095,
13553CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS  = 0x00000096,
13554CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META  = 0x00000097,
13555CB_PERF_SEL_CC_SURFACE_SYNC              = 0x00000098,
13556CB_PERF_SEL_CMASK_READ_DATA_0xC          = 0x00000099,
13557CB_PERF_SEL_CMASK_READ_DATA_0xD          = 0x0000009a,
13558CB_PERF_SEL_CMASK_READ_DATA_0xE          = 0x0000009b,
13559CB_PERF_SEL_CMASK_READ_DATA_0xF          = 0x0000009c,
13560CB_PERF_SEL_CMASK_WRITE_DATA_0xC         = 0x0000009d,
13561CB_PERF_SEL_CMASK_WRITE_DATA_0xD         = 0x0000009e,
13562CB_PERF_SEL_CMASK_WRITE_DATA_0xE         = 0x0000009f,
13563CB_PERF_SEL_CMASK_WRITE_DATA_0xF         = 0x000000a0,
13564CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT      = 0x000000a1,
13565CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT  = 0x000000a2,
13566CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT  = 0x000000a3,
13567CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE  = 0x000000a4,
13568CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE  = 0x000000a5,
13569CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE  = 0x000000a6,
13570CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE  = 0x000000a7,
13571CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE  = 0x000000a8,
13572CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE  = 0x000000a9,
13573CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE  = 0x000000aa,
13574CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE  = 0x000000ab,
13575CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE  = 0x000000ac,
13576CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE  = 0x000000ad,
13577CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE  = 0x000000ae,
13578CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE  = 0x000000af,
13579CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE  = 0x000000b0,
13580CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE  = 0x000000b1,
13581CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE  = 0x000000b2,
13582CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE  = 0x000000b3,
13583CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT        = 0x000000b4,
13584CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS       = 0x000000b5,
13585CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS       = 0x000000b6,
13586CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS       = 0x000000b7,
13587CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS       = 0x000000b8,
13588CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS       = 0x000000b9,
13589CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS       = 0x000000ba,
13590CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT      = 0x000000bb,
13591CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS     = 0x000000bc,
13592CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS     = 0x000000bd,
13593CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS     = 0x000000be,
13594CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS     = 0x000000bf,
13595CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS     = 0x000000c0,
13596CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS     = 0x000000c1,
13597CB_PERF_SEL_QUAD_READS_FRAGMENT_0        = 0x000000c2,
13598CB_PERF_SEL_QUAD_READS_FRAGMENT_1        = 0x000000c3,
13599CB_PERF_SEL_QUAD_READS_FRAGMENT_2        = 0x000000c4,
13600CB_PERF_SEL_QUAD_READS_FRAGMENT_3        = 0x000000c5,
13601CB_PERF_SEL_QUAD_READS_FRAGMENT_4        = 0x000000c6,
13602CB_PERF_SEL_QUAD_READS_FRAGMENT_5        = 0x000000c7,
13603CB_PERF_SEL_QUAD_READS_FRAGMENT_6        = 0x000000c8,
13604CB_PERF_SEL_QUAD_READS_FRAGMENT_7        = 0x000000c9,
13605CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0       = 0x000000ca,
13606CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1       = 0x000000cb,
13607CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2       = 0x000000cc,
13608CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3       = 0x000000cd,
13609CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4       = 0x000000ce,
13610CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5       = 0x000000cf,
13611CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6       = 0x000000d0,
13612CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7       = 0x000000d1,
13613CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST  = 0x000000d2,
13614CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS  = 0x000000d3,
13615CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS  = 0x000000d4,
13616CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED  = 0x000000d5,
13617CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED  = 0x000000d6,
13618CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED  = 0x000000d7,
13619CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST  = 0x000000d8,
13620CB_PERF_SEL_DRAWN_BUSY                   = 0x000000d9,
13621CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY      = 0x000000da,
13622CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY       = 0x000000db,
13623CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY       = 0x000000dc,
13624CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY       = 0x000000dd,
13625CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED  = 0x000000de,
13626CB_PERF_SEL_FC_SEQUENCER_CLEAR           = 0x000000df,
13627CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR  = 0x000000e0,
13628CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS  = 0x000000e1,
13629CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE  = 0x000000e2,
13630CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL     = 0x000000e3,
13631CB_PERF_SEL_FC_DOC_IS_STALLED            = 0x000000e4,
13632CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED     = 0x000000e5,
13633CB_PERF_SEL_FC_DOC_MRTS_COMBINED         = 0x000000e6,
13634CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS        = 0x000000e7,
13635CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT         = 0x000000e8,
13636CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS        = 0x000000e9,
13637CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT         = 0x000000ea,
13638CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL  = 0x000000eb,
13639CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR    = 0x000000ec,
13640CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS   = 0x000000ed,
13641CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS   = 0x000000ee,
13642CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS   = 0x000000ef,
13643CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS  = 0x000000f0,
13644CB_PERF_SEL_FC_DCC_CACHE_HIT             = 0x000000f1,
13645CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS        = 0x000000f2,
13646CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS     = 0x000000f3,
13647CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL  = 0x000000f4,
13648CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL  = 0x000000f5,
13649CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL  = 0x000000f6,
13650CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL  = 0x000000f7,
13651CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL  = 0x000000f8,
13652CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL  = 0x000000f9,
13653CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL  = 0x000000fa,
13654CB_PERF_SEL_FC_DCC_CACHE_STALL           = 0x000000fb,
13655CB_PERF_SEL_FC_DCC_CACHE_FLUSH           = 0x000000fc,
13656CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED    = 0x000000fd,
13657CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED  = 0x000000fe,
13658CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED  = 0x000000ff,
13659CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT     = 0x00000100,
13660CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST      = 0x00000101,
13661CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT  = 0x00000102,
13662CB_PERF_SEL_FC_MC_DCC_READ_REQUEST       = 0x00000103,
13663CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT  = 0x00000104,
13664CB_PERF_SEL_CC_DCC_RDREQ_STALL           = 0x00000105,
13665CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN    = 0x00000106,
13666CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT   = 0x00000107,
13667CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN      = 0x00000108,
13668CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT     = 0x00000109,
13669CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR      = 0x0000010a,
13670CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1  = 0x0000010b,
13671CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2  = 0x0000010c,
13672CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1  = 0x0000010d,
13673CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1  = 0x0000010e,
13674CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1  = 0x0000010f,
13675CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2  = 0x00000110,
13676CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1  = 0x00000111,
13677CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2  = 0x00000112,
13678CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1  = 0x00000113,
13679CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1  = 0x00000114,
13680CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2  = 0x00000115,
13681CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2  = 0x00000116,
13682CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2  = 0x00000117,
13683CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2  = 0x00000118,
13684CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1  = 0x00000119,
13685CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1  = 0x0000011a,
13686CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2  = 0x0000011b,
13687CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3  = 0x0000011c,
13688CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4  = 0x0000011d,
13689CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1  = 0x0000011e,
13690CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2  = 0x0000011f,
13691CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3  = 0x00000120,
13692CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4  = 0x00000121,
13693CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1  = 0x00000122,
13694CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2  = 0x00000123,
13695CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3  = 0x00000124,
13696CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4  = 0x00000125,
13697CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1  = 0x00000126,
13698CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2  = 0x00000127,
13699CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3  = 0x00000128,
13700CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1  = 0x00000129,
13701CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2  = 0x0000012a,
13702CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3  = 0x0000012b,
13703CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4  = 0x0000012c,
13704CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1  = 0x0000012d,
13705CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2  = 0x0000012e,
13706CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3  = 0x0000012f,
13707CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4  = 0x00000130,
13708CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1  = 0x00000131,
13709CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2  = 0x00000132,
13710CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3  = 0x00000133,
13711CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4  = 0x00000134,
13712CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1  = 0x00000135,
13713CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2  = 0x00000136,
13714CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3  = 0x00000137,
13715CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1  = 0x00000138,
13716CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1  = 0x00000139,
13717CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1  = 0x0000013a,
13718CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1  = 0x0000013b,
13719CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1  = 0x0000013c,
13720CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1  = 0x0000013d,
13721CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1  = 0x0000013e,
13722CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1  = 0x0000013f,
13723CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2  = 0x00000140,
13724CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2  = 0x00000141,
13725CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2  = 0x00000142,
13726CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2  = 0x00000143,
13727CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2  = 0x00000144,
13728CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2  = 0x00000145,
13729CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2  = 0x00000146,
13730CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1  = 0x00000147,
13731CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1  = 0x00000148,
13732CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1  = 0x00000149,
13733CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1  = 0x0000014a,
13734CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2  = 0x0000014b,
13735CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2  = 0x0000014c,
13736CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2  = 0x0000014d,
13737CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2  = 0x0000014e,
13738CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2  = 0x0000014f,
13739CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2  = 0x00000150,
13740CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2  = 0x00000151,
13741CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1  = 0x00000152,
13742CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1  = 0x00000153,
13743CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1  = 0x00000154,
13744CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1  = 0x00000155,
13745CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1  = 0x00000156,
13746CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2  = 0x00000157,
13747CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3  = 0x00000158,
13748CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4  = 0x00000159,
13749CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5  = 0x0000015a,
13750CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6  = 0x0000015b,
13751CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0  = 0x0000015c,
13752CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1  = 0x0000015d,
13753CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1  = 0x0000015e,
13754CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2  = 0x0000015f,
13755CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3  = 0x00000160,
13756CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4  = 0x00000161,
13757CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5  = 0x00000162,
13758CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0  = 0x00000163,
13759CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1  = 0x00000164,
13760CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1  = 0x00000165,
13761CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1  = 0x00000166,
13762CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1  = 0x00000167,
13763CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1  = 0x00000168,
13764CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1  = 0x00000169,
13765CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1  = 0x0000016a,
13766CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1  = 0x0000016b,
13767CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1  = 0x0000016c,
13768CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2  = 0x0000016d,
13769CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2  = 0x0000016e,
13770CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2  = 0x0000016f,
13771CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2  = 0x00000170,
13772CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2  = 0x00000171,
13773CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2  = 0x00000172,
13774CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2  = 0x00000173,
13775CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1  = 0x00000174,
13776CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2  = 0x00000175,
13777CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3  = 0x00000176,
13778CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4  = 0x00000177,
13779CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5  = 0x00000178,
13780CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6  = 0x00000179,
13781CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7  = 0x0000017a,
13782CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED  = 0x0000017b,
13783CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1   = 0x0000017c,
13784CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1   = 0x0000017d,
13785CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2   = 0x0000017e,
13786CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3   = 0x0000017f,
13787CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1   = 0x00000180,
13788CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2   = 0x00000181,
13789CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3   = 0x00000182,
13790CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4   = 0x00000183,
13791CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5   = 0x00000184,
13792CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1   = 0x00000185,
13793CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2   = 0x00000186,
13794CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3   = 0x00000187,
13795CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4   = 0x00000188,
13796CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5   = 0x00000189,
13797CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6   = 0x0000018a,
13798CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7   = 0x0000018b,
13799CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH     = 0x0000018c,
13800CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT     = 0x0000018d,
13801CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT    = 0x0000018e,
13802CB_PERF_SEL_RBP_SPLIT_MICROTILE          = 0x0000018f,
13803CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK     = 0x00000190,
13804CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK  = 0x00000191,
13805CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING  = 0x00000192,
13806CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS  = 0x00000193,
13807CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD  = 0x00000194,
13808} CBPerfSel;
13809
13810/*
13811 * CBPerfOpFilterSel enum
13812 */
13813
13814typedef enum CBPerfOpFilterSel {
13815CB_PERF_OP_FILTER_SEL_WRITE_ONLY         = 0x00000000,
13816CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION  = 0x00000001,
13817CB_PERF_OP_FILTER_SEL_RESOLVE            = 0x00000002,
13818CB_PERF_OP_FILTER_SEL_DECOMPRESS         = 0x00000003,
13819CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS   = 0x00000004,
13820CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR  = 0x00000005,
13821} CBPerfOpFilterSel;
13822
13823/*
13824 * CBPerfClearFilterSel enum
13825 */
13826
13827typedef enum CBPerfClearFilterSel {
13828CB_PERF_CLEAR_FILTER_SEL_NONCLEAR        = 0x00000000,
13829CB_PERF_CLEAR_FILTER_SEL_CLEAR           = 0x00000001,
13830} CBPerfClearFilterSel;
13831
13832/*******************************************************
13833 * TC Enums
13834 *******************************************************/
13835
13836/*
13837 * TC_OP_MASKS enum
13838 */
13839
13840typedef enum TC_OP_MASKS {
13841TC_OP_MASK_FLUSH_DENROM                  = 0x00000008,
13842TC_OP_MASK_64                            = 0x00000020,
13843TC_OP_MASK_NO_RTN                        = 0x00000040,
13844} TC_OP_MASKS;
13845
13846/*
13847 * TC_OP enum
13848 */
13849
13850typedef enum TC_OP {
13851TC_OP_READ                               = 0x00000000,
13852TC_OP_ATOMIC_FCMPSWAP_RTN_32             = 0x00000001,
13853TC_OP_ATOMIC_FMIN_RTN_32                 = 0x00000002,
13854TC_OP_ATOMIC_FMAX_RTN_32                 = 0x00000003,
13855TC_OP_RESERVED_FOP_RTN_32_0              = 0x00000004,
13856TC_OP_RESERVED_FOP_RTN_32_1              = 0x00000005,
13857TC_OP_RESERVED_FOP_RTN_32_2              = 0x00000006,
13858TC_OP_ATOMIC_SWAP_RTN_32                 = 0x00000007,
13859TC_OP_ATOMIC_CMPSWAP_RTN_32              = 0x00000008,
13860TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32  = 0x00000009,
13861TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32    = 0x0000000a,
13862TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32    = 0x0000000b,
13863TC_OP_PROBE_FILTER                       = 0x0000000c,
13864TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1  = 0x0000000d,
13865TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2  = 0x0000000e,
13866TC_OP_ATOMIC_ADD_RTN_32                  = 0x0000000f,
13867TC_OP_ATOMIC_SUB_RTN_32                  = 0x00000010,
13868TC_OP_ATOMIC_SMIN_RTN_32                 = 0x00000011,
13869TC_OP_ATOMIC_UMIN_RTN_32                 = 0x00000012,
13870TC_OP_ATOMIC_SMAX_RTN_32                 = 0x00000013,
13871TC_OP_ATOMIC_UMAX_RTN_32                 = 0x00000014,
13872TC_OP_ATOMIC_AND_RTN_32                  = 0x00000015,
13873TC_OP_ATOMIC_OR_RTN_32                   = 0x00000016,
13874TC_OP_ATOMIC_XOR_RTN_32                  = 0x00000017,
13875TC_OP_ATOMIC_INC_RTN_32                  = 0x00000018,
13876TC_OP_ATOMIC_DEC_RTN_32                  = 0x00000019,
13877TC_OP_WBINVL1_VOL                        = 0x0000001a,
13878TC_OP_WBINVL1_SD                         = 0x0000001b,
13879TC_OP_RESERVED_NON_FLOAT_RTN_32_0        = 0x0000001c,
13880TC_OP_RESERVED_NON_FLOAT_RTN_32_1        = 0x0000001d,
13881TC_OP_RESERVED_NON_FLOAT_RTN_32_2        = 0x0000001e,
13882TC_OP_RESERVED_NON_FLOAT_RTN_32_3        = 0x0000001f,
13883TC_OP_WRITE                              = 0x00000020,
13884TC_OP_ATOMIC_FCMPSWAP_RTN_64             = 0x00000021,
13885TC_OP_ATOMIC_FMIN_RTN_64                 = 0x00000022,
13886TC_OP_ATOMIC_FMAX_RTN_64                 = 0x00000023,
13887TC_OP_RESERVED_FOP_RTN_64_0              = 0x00000024,
13888TC_OP_RESERVED_FOP_RTN_64_1              = 0x00000025,
13889TC_OP_RESERVED_FOP_RTN_64_2              = 0x00000026,
13890TC_OP_ATOMIC_SWAP_RTN_64                 = 0x00000027,
13891TC_OP_ATOMIC_CMPSWAP_RTN_64              = 0x00000028,
13892TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64  = 0x00000029,
13893TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64    = 0x0000002a,
13894TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64    = 0x0000002b,
13895TC_OP_WBINVL2_SD                         = 0x0000002c,
13896TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0  = 0x0000002d,
13897TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1  = 0x0000002e,
13898TC_OP_ATOMIC_ADD_RTN_64                  = 0x0000002f,
13899TC_OP_ATOMIC_SUB_RTN_64                  = 0x00000030,
13900TC_OP_ATOMIC_SMIN_RTN_64                 = 0x00000031,
13901TC_OP_ATOMIC_UMIN_RTN_64                 = 0x00000032,
13902TC_OP_ATOMIC_SMAX_RTN_64                 = 0x00000033,
13903TC_OP_ATOMIC_UMAX_RTN_64                 = 0x00000034,
13904TC_OP_ATOMIC_AND_RTN_64                  = 0x00000035,
13905TC_OP_ATOMIC_OR_RTN_64                   = 0x00000036,
13906TC_OP_ATOMIC_XOR_RTN_64                  = 0x00000037,
13907TC_OP_ATOMIC_INC_RTN_64                  = 0x00000038,
13908TC_OP_ATOMIC_DEC_RTN_64                  = 0x00000039,
13909TC_OP_WBL2_NC                            = 0x0000003a,
13910TC_OP_WBL2_WC                            = 0x0000003b,
13911TC_OP_RESERVED_NON_FLOAT_RTN_64_1        = 0x0000003c,
13912TC_OP_RESERVED_NON_FLOAT_RTN_64_2        = 0x0000003d,
13913TC_OP_RESERVED_NON_FLOAT_RTN_64_3        = 0x0000003e,
13914TC_OP_RESERVED_NON_FLOAT_RTN_64_4        = 0x0000003f,
13915TC_OP_WBINVL1                            = 0x00000040,
13916TC_OP_ATOMIC_FCMPSWAP_32                 = 0x00000041,
13917TC_OP_ATOMIC_FMIN_32                     = 0x00000042,
13918TC_OP_ATOMIC_FMAX_32                     = 0x00000043,
13919TC_OP_RESERVED_FOP_32_0                  = 0x00000044,
13920TC_OP_RESERVED_FOP_32_1                  = 0x00000045,
13921TC_OP_RESERVED_FOP_32_2                  = 0x00000046,
13922TC_OP_ATOMIC_SWAP_32                     = 0x00000047,
13923TC_OP_ATOMIC_CMPSWAP_32                  = 0x00000048,
13924TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32    = 0x00000049,
13925TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32        = 0x0000004a,
13926TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32        = 0x0000004b,
13927TC_OP_INV_METADATA                       = 0x0000004c,
13928TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1     = 0x0000004d,
13929TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2     = 0x0000004e,
13930TC_OP_ATOMIC_ADD_32                      = 0x0000004f,
13931TC_OP_ATOMIC_SUB_32                      = 0x00000050,
13932TC_OP_ATOMIC_SMIN_32                     = 0x00000051,
13933TC_OP_ATOMIC_UMIN_32                     = 0x00000052,
13934TC_OP_ATOMIC_SMAX_32                     = 0x00000053,
13935TC_OP_ATOMIC_UMAX_32                     = 0x00000054,
13936TC_OP_ATOMIC_AND_32                      = 0x00000055,
13937TC_OP_ATOMIC_OR_32                       = 0x00000056,
13938TC_OP_ATOMIC_XOR_32                      = 0x00000057,
13939TC_OP_ATOMIC_INC_32                      = 0x00000058,
13940TC_OP_ATOMIC_DEC_32                      = 0x00000059,
13941TC_OP_INVL2_NC                           = 0x0000005a,
13942TC_OP_NOP_RTN0                           = 0x0000005b,
13943TC_OP_RESERVED_NON_FLOAT_32_1            = 0x0000005c,
13944TC_OP_RESERVED_NON_FLOAT_32_2            = 0x0000005d,
13945TC_OP_RESERVED_NON_FLOAT_32_3            = 0x0000005e,
13946TC_OP_RESERVED_NON_FLOAT_32_4            = 0x0000005f,
13947TC_OP_WBINVL2                            = 0x00000060,
13948TC_OP_ATOMIC_FCMPSWAP_64                 = 0x00000061,
13949TC_OP_ATOMIC_FMIN_64                     = 0x00000062,
13950TC_OP_ATOMIC_FMAX_64                     = 0x00000063,
13951TC_OP_RESERVED_FOP_64_0                  = 0x00000064,
13952TC_OP_RESERVED_FOP_64_1                  = 0x00000065,
13953TC_OP_RESERVED_FOP_64_2                  = 0x00000066,
13954TC_OP_ATOMIC_SWAP_64                     = 0x00000067,
13955TC_OP_ATOMIC_CMPSWAP_64                  = 0x00000068,
13956TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64    = 0x00000069,
13957TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64        = 0x0000006a,
13958TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64        = 0x0000006b,
13959TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0     = 0x0000006c,
13960TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1     = 0x0000006d,
13961TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2     = 0x0000006e,
13962TC_OP_ATOMIC_ADD_64                      = 0x0000006f,
13963TC_OP_ATOMIC_SUB_64                      = 0x00000070,
13964TC_OP_ATOMIC_SMIN_64                     = 0x00000071,
13965TC_OP_ATOMIC_UMIN_64                     = 0x00000072,
13966TC_OP_ATOMIC_SMAX_64                     = 0x00000073,
13967TC_OP_ATOMIC_UMAX_64                     = 0x00000074,
13968TC_OP_ATOMIC_AND_64                      = 0x00000075,
13969TC_OP_ATOMIC_OR_64                       = 0x00000076,
13970TC_OP_ATOMIC_XOR_64                      = 0x00000077,
13971TC_OP_ATOMIC_INC_64                      = 0x00000078,
13972TC_OP_ATOMIC_DEC_64                      = 0x00000079,
13973TC_OP_WBINVL2_NC                         = 0x0000007a,
13974TC_OP_NOP_ACK                            = 0x0000007b,
13975TC_OP_RESERVED_NON_FLOAT_64_1            = 0x0000007c,
13976TC_OP_RESERVED_NON_FLOAT_64_2            = 0x0000007d,
13977TC_OP_RESERVED_NON_FLOAT_64_3            = 0x0000007e,
13978TC_OP_RESERVED_NON_FLOAT_64_4            = 0x0000007f,
13979} TC_OP;
13980
13981/*
13982 * TC_CHUB_REQ_CREDITS_ENUM enum
13983 */
13984
13985typedef enum TC_CHUB_REQ_CREDITS_ENUM {
13986TC_CHUB_REQ_CREDITS                      = 0x00000010,
13987} TC_CHUB_REQ_CREDITS_ENUM;
13988
13989/*
13990 * CHUB_TC_RET_CREDITS_ENUM enum
13991 */
13992
13993typedef enum CHUB_TC_RET_CREDITS_ENUM {
13994CHUB_TC_RET_CREDITS                      = 0x00000020,
13995} CHUB_TC_RET_CREDITS_ENUM;
13996
13997/*
13998 * TC_NACKS enum
13999 */
14000

14001typedef enum TC_NACKS {
14002TC_NACK_NO_FAULT                         = 0x00000000,
14003TC_NACK_PAGE_FAULT                       = 0x00000001,
14004TC_NACK_PROTECTION_FAULT                 = 0x00000002,
14005TC_NACK_DATA_ERROR                       = 0x00000003,
14006} TC_NACKS;
14007
14008/*
14009 * TC_EA_CID enum
14010 */
14011
14012typedef enum TC_EA_CID {
14013TC_EA_CID_RT                             = 0x00000000,
14014TC_EA_CID_FMASK                          = 0x00000001,
14015TC_EA_CID_DCC                            = 0x00000002,
14016TC_EA_CID_TCPMETA                        = 0x00000003,
14017TC_EA_CID_Z                              = 0x00000004,
14018TC_EA_CID_STENCIL                        = 0x00000005,
14019TC_EA_CID_HTILE                          = 0x00000006,
14020TC_EA_CID_MISC                           = 0x00000007,
14021TC_EA_CID_TCP                            = 0x00000008,
14022TC_EA_CID_SQC                            = 0x00000009,
14023TC_EA_CID_CPF                            = 0x0000000a,
14024TC_EA_CID_CPG                            = 0x0000000b,
14025TC_EA_CID_IA                             = 0x0000000c,
14026TC_EA_CID_WD                             = 0x0000000d,
14027TC_EA_CID_PA                             = 0x0000000e,
14028TC_EA_CID_UTCL2_TPI                      = 0x0000000f,
14029} TC_EA_CID;
14030
14031/*******************************************************
14032 * SPI Enums
14033 *******************************************************/
14034
14035/*
14036 * SPI_SAMPLE_CNTL enum
14037 */
14038
14039typedef enum SPI_SAMPLE_CNTL {
14040CENTROIDS_ONLY                           = 0x00000000,
14041CENTERS_ONLY                             = 0x00000001,
14042CENTROIDS_AND_CENTERS                    = 0x00000002,
14043UNDEF                                    = 0x00000003,
14044} SPI_SAMPLE_CNTL;
14045
14046/*
14047 * SPI_FOG_MODE enum
14048 */
14049
14050typedef enum SPI_FOG_MODE {
14051SPI_FOG_NONE                             = 0x00000000,
14052SPI_FOG_EXP                              = 0x00000001,
14053SPI_FOG_EXP2                             = 0x00000002,
14054SPI_FOG_LINEAR                           = 0x00000003,
14055} SPI_FOG_MODE;
14056
14057/*
14058 * SPI_PNT_SPRITE_OVERRIDE enum
14059 */
14060
14061typedef enum SPI_PNT_SPRITE_OVERRIDE {
14062SPI_PNT_SPRITE_SEL_0                     = 0x00000000,
14063SPI_PNT_SPRITE_SEL_1                     = 0x00000001,
14064SPI_PNT_SPRITE_SEL_S                     = 0x00000002,
14065SPI_PNT_SPRITE_SEL_T                     = 0x00000003,
14066SPI_PNT_SPRITE_SEL_NONE                  = 0x00000004,
14067} SPI_PNT_SPRITE_OVERRIDE;
14068
14069/*
14070 * SPI_PERFCNT_SEL enum
14071 */
14072
14073typedef enum SPI_PERFCNT_SEL {
14074SPI_PERF_VS_WINDOW_VALID                 = 0x00000000,
14075SPI_PERF_VS_BUSY                         = 0x00000001,
14076SPI_PERF_VS_FIRST_WAVE                   = 0x00000002,
14077SPI_PERF_VS_LAST_WAVE                    = 0x00000003,
14078SPI_PERF_VS_LSHS_DEALLOC                 = 0x00000004,
14079SPI_PERF_VS_PC_STALL                     = 0x00000005,
14080SPI_PERF_VS_POS0_STALL                   = 0x00000006,
14081SPI_PERF_VS_POS1_STALL                   = 0x00000007,
14082SPI_PERF_VS_CRAWLER_STALL                = 0x00000008,
14083SPI_PERF_VS_EVENT_WAVE                   = 0x00000009,
14084SPI_PERF_VS_WAVE                         = 0x0000000a,
14085SPI_PERF_VS_PERS_UPD_FULL0               = 0x0000000b,
14086SPI_PERF_VS_PERS_UPD_FULL1               = 0x0000000c,
14087SPI_PERF_VS_LATE_ALLOC_FULL              = 0x0000000d,
14088SPI_PERF_VS_FIRST_SUBGRP                 = 0x0000000e,
14089SPI_PERF_VS_LAST_SUBGRP                  = 0x0000000f,
14090SPI_PERF_GS_WINDOW_VALID                 = 0x00000010,
14091SPI_PERF_GS_BUSY                         = 0x00000011,
14092SPI_PERF_GS_CRAWLER_STALL                = 0x00000012,
14093SPI_PERF_GS_EVENT_WAVE                   = 0x00000013,
14094SPI_PERF_GS_WAVE                         = 0x00000014,
14095SPI_PERF_GS_PERS_UPD_FULL0               = 0x00000015,
14096SPI_PERF_GS_PERS_UPD_FULL1               = 0x00000016,
14097SPI_PERF_GS_FIRST_SUBGRP                 = 0x00000017,
14098SPI_PERF_GS_LAST_SUBGRP                  = 0x00000018,
14099SPI_PERF_ES_WINDOW_VALID                 = 0x00000019,
14100SPI_PERF_ES_BUSY                         = 0x0000001a,
14101SPI_PERF_ES_CRAWLER_STALL                = 0x0000001b,
14102SPI_PERF_ES_FIRST_WAVE                   = 0x0000001c,
14103SPI_PERF_ES_LAST_WAVE                    = 0x0000001d,
14104SPI_PERF_ES_LSHS_DEALLOC                 = 0x0000001e,
14105SPI_PERF_ES_EVENT_WAVE                   = 0x0000001f,
14106SPI_PERF_ES_WAVE                         = 0x00000020,
14107SPI_PERF_ES_PERS_UPD_FULL0               = 0x00000021,
14108SPI_PERF_ES_PERS_UPD_FULL1               = 0x00000022,
14109SPI_PERF_ES_FIRST_SUBGRP                 = 0x00000023,
14110SPI_PERF_ES_LAST_SUBGRP                  = 0x00000024,
14111SPI_PERF_HS_WINDOW_VALID                 = 0x00000025,
14112SPI_PERF_HS_BUSY                         = 0x00000026,
14113SPI_PERF_HS_CRAWLER_STALL                = 0x00000027,
14114SPI_PERF_HS_FIRST_WAVE                   = 0x00000028,
14115SPI_PERF_HS_LAST_WAVE                    = 0x00000029,
14116SPI_PERF_HS_LSHS_DEALLOC                 = 0x0000002a,
14117SPI_PERF_HS_EVENT_WAVE                   = 0x0000002b,
14118SPI_PERF_HS_WAVE                         = 0x0000002c,
14119SPI_PERF_HS_PERS_UPD_FULL0               = 0x0000002d,
14120SPI_PERF_HS_PERS_UPD_FULL1               = 0x0000002e,
14121SPI_PERF_LS_WINDOW_VALID                 = 0x0000002f,
14122SPI_PERF_LS_BUSY                         = 0x00000030,
14123SPI_PERF_LS_CRAWLER_STALL                = 0x00000031,
14124SPI_PERF_LS_FIRST_WAVE                   = 0x00000032,
14125SPI_PERF_LS_LAST_WAVE                    = 0x00000033,
14126SPI_PERF_OFFCHIP_LDS_STALL_LS            = 0x00000034,
14127SPI_PERF_LS_EVENT_WAVE                   = 0x00000035,
14128SPI_PERF_LS_WAVE                         = 0x00000036,
14129SPI_PERF_LS_PERS_UPD_FULL0               = 0x00000037,
14130SPI_PERF_LS_PERS_UPD_FULL1               = 0x00000038,
14131SPI_PERF_CSG_WINDOW_VALID                = 0x00000039,
14132SPI_PERF_CSG_BUSY                        = 0x0000003a,
14133SPI_PERF_CSG_NUM_THREADGROUPS            = 0x0000003b,
14134SPI_PERF_CSG_CRAWLER_STALL               = 0x0000003c,
14135SPI_PERF_CSG_EVENT_WAVE                  = 0x0000003d,
14136SPI_PERF_CSG_WAVE                        = 0x0000003e,
14137SPI_PERF_CSN_WINDOW_VALID                = 0x0000003f,
14138SPI_PERF_CSN_BUSY                        = 0x00000040,
14139SPI_PERF_CSN_NUM_THREADGROUPS            = 0x00000041,
14140SPI_PERF_CSN_CRAWLER_STALL               = 0x00000042,
14141SPI_PERF_CSN_EVENT_WAVE                  = 0x00000043,
14142SPI_PERF_CSN_WAVE                        = 0x00000044,
14143SPI_PERF_PS_CTL_WINDOW_VALID             = 0x00000045,
14144SPI_PERF_PS_CTL_BUSY                     = 0x00000046,
14145SPI_PERF_PS_CTL_ACTIVE                   = 0x00000047,
14146SPI_PERF_PS_CTL_DEALLOC_BIN0             = 0x00000048,
14147SPI_PERF_PS_CTL_FPOS_BIN1_STALL          = 0x00000049,
14148SPI_PERF_PS_CTL_EVENT_WAVE               = 0x0000004a,
14149SPI_PERF_PS_CTL_WAVE                     = 0x0000004b,
14150SPI_PERF_PS_CTL_OPT_WAVE                 = 0x0000004c,
14151SPI_PERF_PS_CTL_PASS_BIN0                = 0x0000004d,
14152SPI_PERF_PS_CTL_PASS_BIN1                = 0x0000004e,
14153SPI_PERF_PS_CTL_FPOS_BIN2                = 0x0000004f,
14154SPI_PERF_PS_CTL_PRIM_BIN0                = 0x00000050,
14155SPI_PERF_PS_CTL_PRIM_BIN1                = 0x00000051,
14156SPI_PERF_PS_CTL_CNF_BIN2                 = 0x00000052,
14157SPI_PERF_PS_CTL_CNF_BIN3                 = 0x00000053,
14158SPI_PERF_PS_CTL_CRAWLER_STALL            = 0x00000054,
14159SPI_PERF_PS_CTL_LDS_RES_FULL             = 0x00000055,
14160SPI_PERF_PS_PERS_UPD_FULL0               = 0x00000056,
14161SPI_PERF_PS_PERS_UPD_FULL1               = 0x00000057,
14162SPI_PERF_PIX_ALLOC_PEND_CNT              = 0x00000058,
14163SPI_PERF_PIX_ALLOC_SCB_STALL             = 0x00000059,
14164SPI_PERF_PIX_ALLOC_DB0_STALL             = 0x0000005a,
14165SPI_PERF_PIX_ALLOC_DB1_STALL             = 0x0000005b,
14166SPI_PERF_PIX_ALLOC_DB2_STALL             = 0x0000005c,
14167SPI_PERF_PIX_ALLOC_DB3_STALL             = 0x0000005d,
14168SPI_PERF_LDS0_PC_VALID                   = 0x0000005e,
14169SPI_PERF_LDS1_PC_VALID                   = 0x0000005f,
14170SPI_PERF_RA_PIPE_REQ_BIN2                = 0x00000060,
14171SPI_PERF_RA_TASK_REQ_BIN3                = 0x00000061,
14172SPI_PERF_RA_WR_CTL_FULL                  = 0x00000062,
14173SPI_PERF_RA_REQ_NO_ALLOC                 = 0x00000063,
14174SPI_PERF_RA_REQ_NO_ALLOC_PS              = 0x00000064,
14175SPI_PERF_RA_REQ_NO_ALLOC_VS              = 0x00000065,
14176SPI_PERF_RA_REQ_NO_ALLOC_GS              = 0x00000066,
14177SPI_PERF_RA_REQ_NO_ALLOC_ES              = 0x00000067,
14178SPI_PERF_RA_REQ_NO_ALLOC_HS              = 0x00000068,
14179SPI_PERF_RA_REQ_NO_ALLOC_LS              = 0x00000069,
14180SPI_PERF_RA_REQ_NO_ALLOC_CSG             = 0x0000006a,
14181SPI_PERF_RA_REQ_NO_ALLOC_CSN             = 0x0000006b,
14182SPI_PERF_RA_RES_STALL_PS                 = 0x0000006c,
14183SPI_PERF_RA_RES_STALL_VS                 = 0x0000006d,
14184SPI_PERF_RA_RES_STALL_GS                 = 0x0000006e,
14185SPI_PERF_RA_RES_STALL_ES                 = 0x0000006f,
14186SPI_PERF_RA_RES_STALL_HS                 = 0x00000070,
14187SPI_PERF_RA_RES_STALL_LS                 = 0x00000071,
14188SPI_PERF_RA_RES_STALL_CSG                = 0x00000072,
14189SPI_PERF_RA_RES_STALL_CSN                = 0x00000073,
14190SPI_PERF_RA_TMP_STALL_PS                 = 0x00000074,
14191SPI_PERF_RA_TMP_STALL_VS                 = 0x00000075,
14192SPI_PERF_RA_TMP_STALL_GS                 = 0x00000076,
14193SPI_PERF_RA_TMP_STALL_ES                 = 0x00000077,
14194SPI_PERF_RA_TMP_STALL_HS                 = 0x00000078,
14195SPI_PERF_RA_TMP_STALL_LS                 = 0x00000079,
14196SPI_PERF_RA_TMP_STALL_CSG                = 0x0000007a,
14197SPI_PERF_RA_TMP_STALL_CSN                = 0x0000007b,
14198SPI_PERF_RA_WAVE_SIMD_FULL_PS            = 0x0000007c,
14199SPI_PERF_RA_WAVE_SIMD_FULL_VS            = 0x0000007d,
14200SPI_PERF_RA_WAVE_SIMD_FULL_GS            = 0x0000007e,
14201SPI_PERF_RA_WAVE_SIMD_FULL_ES            = 0x0000007f,
14202SPI_PERF_RA_WAVE_SIMD_FULL_HS            = 0x00000080,
14203SPI_PERF_RA_WAVE_SIMD_FULL_LS            = 0x00000081,
14204SPI_PERF_RA_WAVE_SIMD_FULL_CSG           = 0x00000082,
14205SPI_PERF_RA_WAVE_SIMD_FULL_CSN           = 0x00000083,
14206SPI_PERF_RA_VGPR_SIMD_FULL_PS            = 0x00000084,
14207SPI_PERF_RA_VGPR_SIMD_FULL_VS            = 0x00000085,
14208SPI_PERF_RA_VGPR_SIMD_FULL_GS            = 0x00000086,
14209SPI_PERF_RA_VGPR_SIMD_FULL_ES            = 0x00000087,
14210SPI_PERF_RA_VGPR_SIMD_FULL_HS            = 0x00000088,
14211SPI_PERF_RA_VGPR_SIMD_FULL_LS            = 0x00000089,
14212SPI_PERF_RA_VGPR_SIMD_FULL_CSG           = 0x0000008a,
14213SPI_PERF_RA_VGPR_SIMD_FULL_CSN           = 0x0000008b,
14214SPI_PERF_RA_SGPR_SIMD_FULL_PS            = 0x0000008c,
14215SPI_PERF_RA_SGPR_SIMD_FULL_VS            = 0x0000008d,
14216SPI_PERF_RA_SGPR_SIMD_FULL_GS            = 0x0000008e,
14217SPI_PERF_RA_SGPR_SIMD_FULL_ES            = 0x0000008f,
14218SPI_PERF_RA_SGPR_SIMD_FULL_HS            = 0x00000090,
14219SPI_PERF_RA_SGPR_SIMD_FULL_LS            = 0x00000091,
14220SPI_PERF_RA_SGPR_SIMD_FULL_CSG           = 0x00000092,
14221SPI_PERF_RA_SGPR_SIMD_FULL_CSN           = 0x00000093,
14222SPI_PERF_RA_LDS_CU_FULL_PS               = 0x00000094,
14223SPI_PERF_RA_LDS_CU_FULL_LS               = 0x00000095,
14224SPI_PERF_RA_LDS_CU_FULL_ES               = 0x00000096,
14225SPI_PERF_RA_LDS_CU_FULL_CSG              = 0x00000097,
14226SPI_PERF_RA_LDS_CU_FULL_CSN              = 0x00000098,
14227SPI_PERF_RA_BAR_CU_FULL_HS               = 0x00000099,
14228SPI_PERF_RA_BAR_CU_FULL_CSG              = 0x0000009a,
14229SPI_PERF_RA_BAR_CU_FULL_CSN              = 0x0000009b,
14230SPI_PERF_RA_BULKY_CU_FULL_CSG            = 0x0000009c,
14231SPI_PERF_RA_BULKY_CU_FULL_CSN            = 0x0000009d,
14232SPI_PERF_RA_TGLIM_CU_FULL_CSG            = 0x0000009e,
14233SPI_PERF_RA_TGLIM_CU_FULL_CSN            = 0x0000009f,
14234SPI_PERF_RA_WVLIM_STALL_PS               = 0x000000a0,
14235SPI_PERF_RA_WVLIM_STALL_VS               = 0x000000a1,
14236SPI_PERF_RA_WVLIM_STALL_GS               = 0x000000a2,
14237SPI_PERF_RA_WVLIM_STALL_ES               = 0x000000a3,
14238SPI_PERF_RA_WVLIM_STALL_HS               = 0x000000a4,
14239SPI_PERF_RA_WVLIM_STALL_LS               = 0x000000a5,
14240SPI_PERF_RA_WVLIM_STALL_CSG              = 0x000000a6,
14241SPI_PERF_RA_WVLIM_STALL_CSN              = 0x000000a7,
14242SPI_PERF_RA_PS_LOCK_NA                   = 0x000000a8,
14243SPI_PERF_RA_VS_LOCK                      = 0x000000a9,
14244SPI_PERF_RA_GS_LOCK                      = 0x000000aa,
14245SPI_PERF_RA_ES_LOCK                      = 0x000000ab,
14246SPI_PERF_RA_HS_LOCK                      = 0x000000ac,
14247SPI_PERF_RA_LS_LOCK                      = 0x000000ad,
14248SPI_PERF_RA_CSG_LOCK                     = 0x000000ae,
14249SPI_PERF_RA_CSN_LOCK                     = 0x000000af,
14250SPI_PERF_RA_RSV_UPD                      = 0x000000b0,
14251SPI_PERF_EXP_ARB_COL_CNT                 = 0x000000b1,
14252SPI_PERF_EXP_ARB_PAR_CNT                 = 0x000000b2,
14253SPI_PERF_EXP_ARB_POS_CNT                 = 0x000000b3,
14254SPI_PERF_EXP_ARB_GDS_CNT                 = 0x000000b4,
14255SPI_PERF_CLKGATE_BUSY_STALL              = 0x000000b5,
14256SPI_PERF_CLKGATE_ACTIVE_STALL            = 0x000000b6,
14257SPI_PERF_CLKGATE_ALL_CLOCKS_ON           = 0x000000b7,
14258SPI_PERF_CLKGATE_CGTT_DYN_ON             = 0x000000b8,
14259SPI_PERF_CLKGATE_CGTT_REG_ON             = 0x000000b9,
14260SPI_PERF_NUM_VS_POS_EXPORTS              = 0x000000ba,
14261SPI_PERF_NUM_VS_PARAM_EXPORTS            = 0x000000bb,
14262SPI_PERF_NUM_PS_COL_EXPORTS              = 0x000000bc,
14263SPI_PERF_ES_GRP_FIFO_FULL                = 0x000000bd,
14264SPI_PERF_GS_GRP_FIFO_FULL                = 0x000000be,
14265SPI_PERF_HS_GRP_FIFO_FULL                = 0x000000bf,
14266SPI_PERF_LS_GRP_FIFO_FULL                = 0x000000c0,
14267SPI_PERF_VS_ALLOC_CNT                    = 0x000000c1,
14268SPI_PERF_VS_LATE_ALLOC_ACCUM             = 0x000000c2,
14269SPI_PERF_PC_ALLOC_CNT                    = 0x000000c3,
14270SPI_PERF_PC_ALLOC_ACCUM                  = 0x000000c4,
14271} SPI_PERFCNT_SEL;
14272
14273/*
14274 * SPI_SHADER_FORMAT enum
14275 */
14276
14277typedef enum SPI_SHADER_FORMAT {
14278SPI_SHADER_NONE                          = 0x00000000,
14279SPI_SHADER_1COMP                         = 0x00000001,
14280SPI_SHADER_2COMP                         = 0x00000002,
14281SPI_SHADER_4COMPRESS                     = 0x00000003,
14282SPI_SHADER_4COMP                         = 0x00000004,
14283} SPI_SHADER_FORMAT;
14284
14285/*
14286 * SPI_SHADER_EX_FORMAT enum
14287 */
14288
14289typedef enum SPI_SHADER_EX_FORMAT {
14290SPI_SHADER_ZERO                          = 0x00000000,
14291SPI_SHADER_32_R                          = 0x00000001,
14292SPI_SHADER_32_GR                         = 0x00000002,
14293SPI_SHADER_32_AR                         = 0x00000003,
14294SPI_SHADER_FP16_ABGR                     = 0x00000004,
14295SPI_SHADER_UNORM16_ABGR                  = 0x00000005,
14296SPI_SHADER_SNORM16_ABGR                  = 0x00000006,
14297SPI_SHADER_UINT16_ABGR                   = 0x00000007,
14298SPI_SHADER_SINT16_ABGR                   = 0x00000008,
14299SPI_SHADER_32_ABGR                       = 0x00000009,
14300} SPI_SHADER_EX_FORMAT;
14301
14302/*
14303 * CLKGATE_SM_MODE enum
14304 */
14305
14306typedef enum CLKGATE_SM_MODE {
14307ON_SEQ                                   = 0x00000000,
14308OFF_SEQ                                  = 0x00000001,
14309PROG_SEQ                                 = 0x00000002,
14310READ_SEQ                                 = 0x00000003,
14311SM_MODE_RESERVED                         = 0x00000004,
14312} CLKGATE_SM_MODE;
14313
14314/*
14315 * CLKGATE_BASE_MODE enum
14316 */
14317
14318typedef enum CLKGATE_BASE_MODE {
14319MULT_8                                   = 0x00000000,
14320MULT_16                                  = 0x00000001,
14321} CLKGATE_BASE_MODE;
14322
14323/*******************************************************
14324 * SQ Enums
14325 *******************************************************/
14326
14327/*
14328 * SQ_TEX_CLAMP enum
14329 */
14330
14331typedef enum SQ_TEX_CLAMP {
14332SQ_TEX_WRAP                              = 0x00000000,
14333SQ_TEX_MIRROR                            = 0x00000001,
14334SQ_TEX_CLAMP_LAST_TEXEL                  = 0x00000002,
14335SQ_TEX_MIRROR_ONCE_LAST_TEXEL            = 0x00000003,
14336SQ_TEX_CLAMP_HALF_BORDER                 = 0x00000004,
14337SQ_TEX_MIRROR_ONCE_HALF_BORDER           = 0x00000005,
14338SQ_TEX_CLAMP_BORDER                      = 0x00000006,
14339SQ_TEX_MIRROR_ONCE_BORDER                = 0x00000007,
14340} SQ_TEX_CLAMP;
14341
14342/*
14343 * SQ_TEX_XY_FILTER enum
14344 */
14345
14346typedef enum SQ_TEX_XY_FILTER {
14347SQ_TEX_XY_FILTER_POINT                   = 0x00000000,
14348SQ_TEX_XY_FILTER_BILINEAR                = 0x00000001,
14349SQ_TEX_XY_FILTER_ANISO_POINT             = 0x00000002,
14350SQ_TEX_XY_FILTER_ANISO_BILINEAR          = 0x00000003,
14351} SQ_TEX_XY_FILTER;
14352
14353/*
14354 * SQ_TEX_Z_FILTER enum
14355 */
14356
14357typedef enum SQ_TEX_Z_FILTER {
14358SQ_TEX_Z_FILTER_NONE                     = 0x00000000,
14359SQ_TEX_Z_FILTER_POINT                    = 0x00000001,
14360SQ_TEX_Z_FILTER_LINEAR                   = 0x00000002,
14361} SQ_TEX_Z_FILTER;
14362
14363/*
14364 * SQ_TEX_MIP_FILTER enum
14365 */
14366
14367typedef enum SQ_TEX_MIP_FILTER {
14368SQ_TEX_MIP_FILTER_NONE                   = 0x00000000,
14369SQ_TEX_MIP_FILTER_POINT                  = 0x00000001,
14370SQ_TEX_MIP_FILTER_LINEAR                 = 0x00000002,
14371SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ        = 0x00000003,
14372} SQ_TEX_MIP_FILTER;
14373
14374/*
14375 * SQ_TEX_ANISO_RATIO enum
14376 */
14377
14378typedef enum SQ_TEX_ANISO_RATIO {
14379SQ_TEX_ANISO_RATIO_1                     = 0x00000000,
14380SQ_TEX_ANISO_RATIO_2                     = 0x00000001,
14381SQ_TEX_ANISO_RATIO_4                     = 0x00000002,
14382SQ_TEX_ANISO_RATIO_8                     = 0x00000003,
14383SQ_TEX_ANISO_RATIO_16                    = 0x00000004,
14384} SQ_TEX_ANISO_RATIO;
14385
14386/*
14387 * SQ_TEX_DEPTH_COMPARE enum
14388 */
14389
14390typedef enum SQ_TEX_DEPTH_COMPARE {
14391SQ_TEX_DEPTH_COMPARE_NEVER               = 0x00000000,
14392SQ_TEX_DEPTH_COMPARE_LESS                = 0x00000001,
14393SQ_TEX_DEPTH_COMPARE_EQUAL               = 0x00000002,
14394SQ_TEX_DEPTH_COMPARE_LESSEQUAL           = 0x00000003,
14395SQ_TEX_DEPTH_COMPARE_GREATER             = 0x00000004,
14396SQ_TEX_DEPTH_COMPARE_NOTEQUAL            = 0x00000005,
14397SQ_TEX_DEPTH_COMPARE_GREATEREQUAL        = 0x00000006,
14398SQ_TEX_DEPTH_COMPARE_ALWAYS              = 0x00000007,
14399} SQ_TEX_DEPTH_COMPARE;
14400
14401/*
14402 * SQ_TEX_BORDER_COLOR enum
14403 */
14404
14405typedef enum SQ_TEX_BORDER_COLOR {
14406SQ_TEX_BORDER_COLOR_TRANS_BLACK          = 0x00000000,
14407SQ_TEX_BORDER_COLOR_OPAQUE_BLACK         = 0x00000001,
14408SQ_TEX_BORDER_COLOR_OPAQUE_WHITE         = 0x00000002,
14409SQ_TEX_BORDER_COLOR_REGISTER             = 0x00000003,
14410} SQ_TEX_BORDER_COLOR;
14411
14412/*
14413 * SQ_RSRC_BUF_TYPE enum
14414 */
14415
14416typedef enum SQ_RSRC_BUF_TYPE {
14417SQ_RSRC_BUF                              = 0x00000000,
14418SQ_RSRC_BUF_RSVD_1                       = 0x00000001,
14419SQ_RSRC_BUF_RSVD_2                       = 0x00000002,
14420SQ_RSRC_BUF_RSVD_3                       = 0x00000003,
14421} SQ_RSRC_BUF_TYPE;
14422
14423/*
14424 * SQ_RSRC_IMG_TYPE enum
14425 */
14426
14427typedef enum SQ_RSRC_IMG_TYPE {
14428SQ_RSRC_IMG_RSVD_0                       = 0x00000000,
14429SQ_RSRC_IMG_RSVD_1                       = 0x00000001,
14430SQ_RSRC_IMG_RSVD_2                       = 0x00000002,
14431SQ_RSRC_IMG_RSVD_3                       = 0x00000003,
14432SQ_RSRC_IMG_RSVD_4                       = 0x00000004,
14433SQ_RSRC_IMG_RSVD_5                       = 0x00000005,
14434SQ_RSRC_IMG_RSVD_6                       = 0x00000006,
14435SQ_RSRC_IMG_RSVD_7                       = 0x00000007,
14436SQ_RSRC_IMG_1D                           = 0x00000008,
14437SQ_RSRC_IMG_2D                           = 0x00000009,
14438SQ_RSRC_IMG_3D                           = 0x0000000a,
14439SQ_RSRC_IMG_CUBE                         = 0x0000000b,
14440SQ_RSRC_IMG_1D_ARRAY                     = 0x0000000c,
14441SQ_RSRC_IMG_2D_ARRAY                     = 0x0000000d,
14442SQ_RSRC_IMG_2D_MSAA                      = 0x0000000e,
14443SQ_RSRC_IMG_2D_MSAA_ARRAY                = 0x0000000f,
14444} SQ_RSRC_IMG_TYPE;
14445
14446/*
14447 * SQ_RSRC_FLAT_TYPE enum
14448 */
14449
14450typedef enum SQ_RSRC_FLAT_TYPE {
14451SQ_RSRC_FLAT_RSVD_0                      = 0x00000000,
14452SQ_RSRC_FLAT                             = 0x00000001,
14453SQ_RSRC_FLAT_RSVD_2                      = 0x00000002,
14454SQ_RSRC_FLAT_RSVD_3                      = 0x00000003,
14455} SQ_RSRC_FLAT_TYPE;
14456
14457/*
14458 * SQ_IMG_FILTER_TYPE enum
14459 */
14460
14461typedef enum SQ_IMG_FILTER_TYPE {
14462SQ_IMG_FILTER_MODE_BLEND                 = 0x00000000,
14463SQ_IMG_FILTER_MODE_MIN                   = 0x00000001,
14464SQ_IMG_FILTER_MODE_MAX                   = 0x00000002,
14465} SQ_IMG_FILTER_TYPE;
14466
14467/*
14468 * SQ_SEL_XYZW01 enum
14469 */
14470
14471typedef enum SQ_SEL_XYZW01 {
14472SQ_SEL_0                                 = 0x00000000,
14473SQ_SEL_1                                 = 0x00000001,
14474SQ_SEL_RESERVED_0                        = 0x00000002,
14475SQ_SEL_RESERVED_1                        = 0x00000003,
14476SQ_SEL_X                                 = 0x00000004,
14477SQ_SEL_Y                                 = 0x00000005,
14478SQ_SEL_Z                                 = 0x00000006,
14479SQ_SEL_W                                 = 0x00000007,
14480} SQ_SEL_XYZW01;
14481
14482/*
14483 * SQ_WAVE_TYPE enum
14484 */
14485
14486typedef enum SQ_WAVE_TYPE {
14487SQ_WAVE_TYPE_PS                          = 0x00000000,
14488SQ_WAVE_TYPE_VS                          = 0x00000001,
14489SQ_WAVE_TYPE_GS                          = 0x00000002,
14490SQ_WAVE_TYPE_ES                          = 0x00000003,
14491SQ_WAVE_TYPE_HS                          = 0x00000004,
14492SQ_WAVE_TYPE_LS                          = 0x00000005,
14493SQ_WAVE_TYPE_CS                          = 0x00000006,
14494SQ_WAVE_TYPE_PS1                         = 0x00000007,
14495} SQ_WAVE_TYPE;
14496
14497/*
14498 * SQ_THREAD_TRACE_TOKEN_TYPE enum
14499 */
14500
14501typedef enum SQ_THREAD_TRACE_TOKEN_TYPE {
14502SQ_THREAD_TRACE_TOKEN_MISC               = 0x00000000,
14503SQ_THREAD_TRACE_TOKEN_TIMESTAMP          = 0x00000001,
14504SQ_THREAD_TRACE_TOKEN_REG                = 0x00000002,
14505SQ_THREAD_TRACE_TOKEN_WAVE_START         = 0x00000003,
14506SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC         = 0x00000004,
14507SQ_THREAD_TRACE_TOKEN_REG_CSPRIV         = 0x00000005,
14508SQ_THREAD_TRACE_TOKEN_WAVE_END           = 0x00000006,
14509SQ_THREAD_TRACE_TOKEN_EVENT              = 0x00000007,
14510SQ_THREAD_TRACE_TOKEN_EVENT_CS           = 0x00000008,
14511SQ_THREAD_TRACE_TOKEN_EVENT_GFX1         = 0x00000009,
14512SQ_THREAD_TRACE_TOKEN_INST               = 0x0000000a,
14513SQ_THREAD_TRACE_TOKEN_INST_PC            = 0x0000000b,
14514SQ_THREAD_TRACE_TOKEN_INST_USERDATA      = 0x0000000c,
14515SQ_THREAD_TRACE_TOKEN_ISSUE              = 0x0000000d,
14516SQ_THREAD_TRACE_TOKEN_PERF               = 0x0000000e,
14517SQ_THREAD_TRACE_TOKEN_REG_CS             = 0x0000000f,
14518} SQ_THREAD_TRACE_TOKEN_TYPE;
14519
14520/*
14521 * SQ_THREAD_TRACE_MISC_TOKEN_TYPE enum
14522 */
14523
14524typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE {
14525SQ_THREAD_TRACE_MISC_TOKEN_TIME          = 0x00000000,
14526SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET    = 0x00000001,
14527SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST   = 0x00000002,
14528SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC     = 0x00000003,
14529SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN  = 0x00000004,
14530SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END  = 0x00000005,
14531SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX       = 0x00000006,
14532SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN    = 0x00000007,
14533} SQ_THREAD_TRACE_MISC_TOKEN_TYPE;
14534
14535/*
14536 * SQ_THREAD_TRACE_INST_TYPE enum
14537 */
14538
14539typedef enum SQ_THREAD_TRACE_INST_TYPE {
14540SQ_THREAD_TRACE_INST_TYPE_SMEM_RD        = 0x00000000,
14541SQ_THREAD_TRACE_INST_TYPE_SALU_32        = 0x00000001,
14542SQ_THREAD_TRACE_INST_TYPE_VMEM_RD        = 0x00000002,
14543SQ_THREAD_TRACE_INST_TYPE_VMEM_WR        = 0x00000003,
14544SQ_THREAD_TRACE_INST_TYPE_FLAT_WR        = 0x00000004,
14545SQ_THREAD_TRACE_INST_TYPE_VALU_32        = 0x00000005,
14546SQ_THREAD_TRACE_INST_TYPE_LDS            = 0x00000006,
14547SQ_THREAD_TRACE_INST_TYPE_PC             = 0x00000007,
14548SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS     = 0x00000008,
14549SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX     = 0x00000009,
14550SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL  = 0x0000000a,
14551SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS  = 0x0000000b,
14552SQ_THREAD_TRACE_INST_TYPE_JUMP           = 0x0000000c,
14553SQ_THREAD_TRACE_INST_TYPE_NEXT           = 0x0000000d,
14554SQ_THREAD_TRACE_INST_TYPE_FLAT_RD        = 0x0000000e,
14555SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG      = 0x0000000f,
14556SQ_THREAD_TRACE_INST_TYPE_SMEM_WR        = 0x00000010,
14557SQ_THREAD_TRACE_INST_TYPE_SALU_64        = 0x00000011,
14558SQ_THREAD_TRACE_INST_TYPE_VALU_64        = 0x00000012,
14559SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY  = 0x00000013,
14560SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY  = 0x00000014,
14561SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY  = 0x00000015,
14562SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY  = 0x00000016,
14563SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY  = 0x00000017,
14564SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY  = 0x00000018,
14565SQ_THREAD_TRACE_INST_TYPE_FATAL_HALT     = 0x00000019,
14566} SQ_THREAD_TRACE_INST_TYPE;
14567
14568/*
14569 * SQ_THREAD_TRACE_REG_TYPE enum
14570 */
14571
14572typedef enum SQ_THREAD_TRACE_REG_TYPE {
14573SQ_THREAD_TRACE_REG_TYPE_EVENT           = 0x00000000,
14574SQ_THREAD_TRACE_REG_TYPE_DRAW            = 0x00000001,
14575SQ_THREAD_TRACE_REG_TYPE_DISPATCH        = 0x00000002,
14576SQ_THREAD_TRACE_REG_TYPE_USERDATA        = 0x00000003,
14577SQ_THREAD_TRACE_REG_TYPE_MARKER          = 0x00000004,
14578SQ_THREAD_TRACE_REG_TYPE_GFXDEC          = 0x00000005,
14579SQ_THREAD_TRACE_REG_TYPE_SHDEC           = 0x00000006,
14580SQ_THREAD_TRACE_REG_TYPE_OTHER           = 0x00000007,
14581} SQ_THREAD_TRACE_REG_TYPE;
14582
14583/*
14584 * SQ_THREAD_TRACE_REG_OP enum
14585 */
14586
14587typedef enum SQ_THREAD_TRACE_REG_OP {
14588SQ_THREAD_TRACE_REG_OP_READ              = 0x00000000,
14589SQ_THREAD_TRACE_REG_OP_WRITE             = 0x00000001,
14590} SQ_THREAD_TRACE_REG_OP;
14591
14592/*
14593 * SQ_THREAD_TRACE_MODE_SEL enum
14594 */
14595
14596typedef enum SQ_THREAD_TRACE_MODE_SEL {
14597SQ_THREAD_TRACE_MODE_OFF                 = 0x00000000,
14598SQ_THREAD_TRACE_MODE_ON                  = 0x00000001,
14599} SQ_THREAD_TRACE_MODE_SEL;
14600
14601/*
14602 * SQ_THREAD_TRACE_CAPTURE_MODE enum
14603 */
14604
14605typedef enum SQ_THREAD_TRACE_CAPTURE_MODE {
14606SQ_THREAD_TRACE_CAPTURE_MODE_ALL         = 0x00000000,
14607SQ_THREAD_TRACE_CAPTURE_MODE_SELECT      = 0x00000001,
14608SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL  = 0x00000002,
14609} SQ_THREAD_TRACE_CAPTURE_MODE;
14610
14611/*
14612 * SQ_THREAD_TRACE_VM_ID_MASK enum
14613 */
14614
14615typedef enum SQ_THREAD_TRACE_VM_ID_MASK {
14616SQ_THREAD_TRACE_VM_ID_MASK_SINGLE        = 0x00000000,
14617SQ_THREAD_TRACE_VM_ID_MASK_ALL           = 0x00000001,
14618SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL  = 0x00000002,
14619} SQ_THREAD_TRACE_VM_ID_MASK;
14620
14621/*
14622 * SQ_THREAD_TRACE_WAVE_MASK enum
14623 */
14624
14625typedef enum SQ_THREAD_TRACE_WAVE_MASK {
14626SQ_THREAD_TRACE_WAVE_MASK_NONE           = 0x00000000,
14627SQ_THREAD_TRACE_WAVE_MASK_ALL            = 0x00000001,
14628} SQ_THREAD_TRACE_WAVE_MASK;
14629
14630/*
14631 * SQ_THREAD_TRACE_ISSUE enum
14632 */
14633
14634typedef enum SQ_THREAD_TRACE_ISSUE {
14635SQ_THREAD_TRACE_ISSUE_NULL               = 0x00000000,
14636SQ_THREAD_TRACE_ISSUE_STALL              = 0x00000001,
14637SQ_THREAD_TRACE_ISSUE_INST               = 0x00000002,
14638SQ_THREAD_TRACE_ISSUE_IMMED              = 0x00000003,
14639} SQ_THREAD_TRACE_ISSUE;
14640
14641/*
14642 * SQ_THREAD_TRACE_ISSUE_MASK enum
14643 */
14644
14645typedef enum SQ_THREAD_TRACE_ISSUE_MASK {
14646SQ_THREAD_TRACE_ISSUE_MASK_ALL           = 0x00000000,
14647SQ_THREAD_TRACE_ISSUE_MASK_STALLED       = 0x00000001,
14648SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED  = 0x00000002,
14649SQ_THREAD_TRACE_ISSUE_MASK_IMMED         = 0x00000003,
14650} SQ_THREAD_TRACE_ISSUE_MASK;
14651
14652/*
14653 * SQ_PERF_SEL enum
14654 */
14655
14656typedef enum SQ_PERF_SEL {
14657SQ_PERF_SEL_NONE                         = 0x00000000,
14658SQ_PERF_SEL_ACCUM_PREV                   = 0x00000001,
14659SQ_PERF_SEL_CYCLES                       = 0x00000002,
14660SQ_PERF_SEL_BUSY_CYCLES                  = 0x00000003,
14661SQ_PERF_SEL_WAVES                        = 0x00000004,
14662SQ_PERF_SEL_LEVEL_WAVES                  = 0x00000005,
14663SQ_PERF_SEL_WAVES_EQ_64                  = 0x00000006,
14664SQ_PERF_SEL_WAVES_LT_64                  = 0x00000007,
14665SQ_PERF_SEL_WAVES_LT_48                  = 0x00000008,
14666SQ_PERF_SEL_WAVES_LT_32                  = 0x00000009,
14667SQ_PERF_SEL_WAVES_LT_16                  = 0x0000000a,
14668SQ_PERF_SEL_WAVES_CU                     = 0x0000000b,
14669SQ_PERF_SEL_LEVEL_WAVES_CU               = 0x0000000c,
14670SQ_PERF_SEL_BUSY_CU_CYCLES               = 0x0000000d,
14671SQ_PERF_SEL_ITEMS                        = 0x0000000e,
14672SQ_PERF_SEL_QUADS                        = 0x0000000f,
14673SQ_PERF_SEL_EVENTS                       = 0x00000010,
14674SQ_PERF_SEL_SURF_SYNCS                   = 0x00000011,
14675SQ_PERF_SEL_TTRACE_REQS                  = 0x00000012,
14676SQ_PERF_SEL_TTRACE_INFLIGHT_REQS         = 0x00000013,
14677SQ_PERF_SEL_TTRACE_STALL                 = 0x00000014,
14678SQ_PERF_SEL_MSG_CNTR                     = 0x00000015,
14679SQ_PERF_SEL_MSG_PERF                     = 0x00000016,
14680SQ_PERF_SEL_MSG_GSCNT                    = 0x00000017,
14681SQ_PERF_SEL_MSG_INTERRUPT                = 0x00000018,
14682SQ_PERF_SEL_INSTS                        = 0x00000019,
14683SQ_PERF_SEL_INSTS_VALU                   = 0x0000001a,
14684SQ_PERF_SEL_INSTS_VMEM_WR                = 0x0000001b,
14685SQ_PERF_SEL_INSTS_VMEM_RD                = 0x0000001c,
14686SQ_PERF_SEL_INSTS_VMEM                   = 0x0000001d,
14687SQ_PERF_SEL_INSTS_SALU                   = 0x0000001e,
14688SQ_PERF_SEL_INSTS_SMEM                   = 0x0000001f,
14689SQ_PERF_SEL_INSTS_FLAT                   = 0x00000020,
14690SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY          = 0x00000021,
14691SQ_PERF_SEL_INSTS_LDS                    = 0x00000022,
14692SQ_PERF_SEL_INSTS_GDS                    = 0x00000023,
14693SQ_PERF_SEL_INSTS_EXP                    = 0x00000024,
14694SQ_PERF_SEL_INSTS_EXP_GDS                = 0x00000025,
14695SQ_PERF_SEL_INSTS_BRANCH                 = 0x00000026,
14696SQ_PERF_SEL_INSTS_SENDMSG                = 0x00000027,
14697SQ_PERF_SEL_INSTS_VSKIPPED               = 0x00000028,
14698SQ_PERF_SEL_INST_LEVEL_VMEM              = 0x00000029,
14699SQ_PERF_SEL_INST_LEVEL_SMEM              = 0x0000002a,
14700SQ_PERF_SEL_INST_LEVEL_LDS               = 0x0000002b,
14701SQ_PERF_SEL_INST_LEVEL_GDS               = 0x0000002c,
14702SQ_PERF_SEL_INST_LEVEL_EXP               = 0x0000002d,
14703SQ_PERF_SEL_WAVE_CYCLES                  = 0x0000002e,
14704SQ_PERF_SEL_WAVE_READY                   = 0x0000002f,
14705SQ_PERF_SEL_WAIT_CNT_VM                  = 0x00000030,
14706SQ_PERF_SEL_WAIT_CNT_LGKM                = 0x00000031,
14707SQ_PERF_SEL_WAIT_CNT_EXP                 = 0x00000032,
14708SQ_PERF_SEL_WAIT_CNT_ANY                 = 0x00000033,
14709SQ_PERF_SEL_WAIT_BARRIER                 = 0x00000034,
14710SQ_PERF_SEL_WAIT_EXP_ALLOC               = 0x00000035,
14711SQ_PERF_SEL_WAIT_SLEEP                   = 0x00000036,
14712SQ_PERF_SEL_WAIT_SLEEP_XNACK             = 0x00000037,
14713SQ_PERF_SEL_WAIT_OTHER                   = 0x00000038,
14714SQ_PERF_SEL_WAIT_ANY                     = 0x00000039,
14715SQ_PERF_SEL_WAIT_TTRACE                  = 0x0000003a,
14716SQ_PERF_SEL_WAIT_IFETCH                  = 0x0000003b,
14717SQ_PERF_SEL_WAIT_INST_ANY                = 0x0000003c,
14718SQ_PERF_SEL_WAIT_INST_VMEM               = 0x0000003d,
14719SQ_PERF_SEL_WAIT_INST_SCA                = 0x0000003e,
14720SQ_PERF_SEL_WAIT_INST_LDS                = 0x0000003f,
14721SQ_PERF_SEL_WAIT_INST_VALU               = 0x00000040,
14722SQ_PERF_SEL_WAIT_INST_EXP_GDS            = 0x00000041,
14723SQ_PERF_SEL_WAIT_INST_MISC               = 0x00000042,
14724SQ_PERF_SEL_WAIT_INST_FLAT               = 0x00000043,
14725SQ_PERF_SEL_ACTIVE_INST_ANY              = 0x00000044,
14726SQ_PERF_SEL_ACTIVE_INST_VMEM             = 0x00000045,
14727SQ_PERF_SEL_ACTIVE_INST_LDS              = 0x00000046,
14728SQ_PERF_SEL_ACTIVE_INST_VALU             = 0x00000047,
14729SQ_PERF_SEL_ACTIVE_INST_SCA              = 0x00000048,
14730SQ_PERF_SEL_ACTIVE_INST_EXP_GDS          = 0x00000049,
14731SQ_PERF_SEL_ACTIVE_INST_MISC             = 0x0000004a,
14732SQ_PERF_SEL_ACTIVE_INST_FLAT             = 0x0000004b,
14733SQ_PERF_SEL_INST_CYCLES_VMEM_WR          = 0x0000004c,
14734SQ_PERF_SEL_INST_CYCLES_VMEM_RD          = 0x0000004d,
14735SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR        = 0x0000004e,
14736SQ_PERF_SEL_INST_CYCLES_VMEM_DATA        = 0x0000004f,
14737SQ_PERF_SEL_INST_CYCLES_VMEM_CMD         = 0x00000050,
14738SQ_PERF_SEL_INST_CYCLES_EXP              = 0x00000051,
14739SQ_PERF_SEL_INST_CYCLES_GDS              = 0x00000052,
14740SQ_PERF_SEL_INST_CYCLES_SMEM             = 0x00000053,
14741SQ_PERF_SEL_INST_CYCLES_SALU             = 0x00000054,
14742SQ_PERF_SEL_THREAD_CYCLES_VALU           = 0x00000055,
14743SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX       = 0x00000056,
14744SQ_PERF_SEL_IFETCH                       = 0x00000057,
14745SQ_PERF_SEL_IFETCH_LEVEL                 = 0x00000058,
14746SQ_PERF_SEL_CBRANCH_FORK                 = 0x00000059,
14747SQ_PERF_SEL_CBRANCH_FORK_SPLIT           = 0x0000005a,
14748SQ_PERF_SEL_VALU_LDS_DIRECT_RD           = 0x0000005b,
14749SQ_PERF_SEL_VALU_LDS_INTERP_OP           = 0x0000005c,
14750SQ_PERF_SEL_LDS_BANK_CONFLICT            = 0x0000005d,
14751SQ_PERF_SEL_LDS_ADDR_CONFLICT            = 0x0000005e,
14752SQ_PERF_SEL_LDS_UNALIGNED_STALL          = 0x0000005f,
14753SQ_PERF_SEL_LDS_MEM_VIOLATIONS           = 0x00000060,
14754SQ_PERF_SEL_LDS_ATOMIC_RETURN            = 0x00000061,
14755SQ_PERF_SEL_LDS_IDX_ACTIVE               = 0x00000062,
14756SQ_PERF_SEL_VALU_DEP_STALL               = 0x00000063,
14757SQ_PERF_SEL_VALU_STARVE                  = 0x00000064,
14758SQ_PERF_SEL_EXP_REQ_FIFO_FULL            = 0x00000065,
14759SQ_PERF_SEL_LDS_DATA_FIFO_FULL           = 0x00000066,
14760SQ_PERF_SEL_LDS_CMD_FIFO_FULL            = 0x00000067,
14761SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL       = 0x00000068,
14762SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL        = 0x00000069,
14763SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY        = 0x0000006a,
14764SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL    = 0x0000006b,
14765SQ_PERF_SEL_VALU_SRC_C_CONFLICT          = 0x0000006c,
14766SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT      = 0x0000006d,
14767SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT      = 0x0000006e,
14768SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT         = 0x0000006f,
14769SQ_PERF_SEL_LDS_SRC_CD_CONFLICT          = 0x00000070,
14770SQ_PERF_SEL_SRC_CD_BUSY                  = 0x00000071,
14771SQ_PERF_SEL_PT_POWER_STALL               = 0x00000072,
14772SQ_PERF_SEL_USER0                        = 0x00000073,
14773SQ_PERF_SEL_USER1                        = 0x00000074,
14774SQ_PERF_SEL_USER2                        = 0x00000075,
14775SQ_PERF_SEL_USER3                        = 0x00000076,
14776SQ_PERF_SEL_USER4                        = 0x00000077,
14777SQ_PERF_SEL_USER5                        = 0x00000078,
14778SQ_PERF_SEL_USER6                        = 0x00000079,
14779SQ_PERF_SEL_USER7                        = 0x0000007a,
14780SQ_PERF_SEL_USER8                        = 0x0000007b,
14781SQ_PERF_SEL_USER9                        = 0x0000007c,
14782SQ_PERF_SEL_USER10                       = 0x0000007d,
14783SQ_PERF_SEL_USER11                       = 0x0000007e,
14784SQ_PERF_SEL_USER12                       = 0x0000007f,
14785SQ_PERF_SEL_USER13                       = 0x00000080,
14786SQ_PERF_SEL_USER14                       = 0x00000081,
14787SQ_PERF_SEL_USER15                       = 0x00000082,
14788SQ_PERF_SEL_USER_LEVEL0                  = 0x00000083,
14789SQ_PERF_SEL_USER_LEVEL1                  = 0x00000084,
14790SQ_PERF_SEL_USER_LEVEL2                  = 0x00000085,
14791SQ_PERF_SEL_USER_LEVEL3                  = 0x00000086,
14792SQ_PERF_SEL_USER_LEVEL4                  = 0x00000087,
14793SQ_PERF_SEL_USER_LEVEL5                  = 0x00000088,
14794SQ_PERF_SEL_USER_LEVEL6                  = 0x00000089,
14795SQ_PERF_SEL_USER_LEVEL7                  = 0x0000008a,
14796SQ_PERF_SEL_USER_LEVEL8                  = 0x0000008b,
14797SQ_PERF_SEL_USER_LEVEL9                  = 0x0000008c,
14798SQ_PERF_SEL_USER_LEVEL10                 = 0x0000008d,
14799SQ_PERF_SEL_USER_LEVEL11                 = 0x0000008e,
14800SQ_PERF_SEL_USER_LEVEL12                 = 0x0000008f,
14801SQ_PERF_SEL_USER_LEVEL13                 = 0x00000090,
14802SQ_PERF_SEL_USER_LEVEL14                 = 0x00000091,
14803SQ_PERF_SEL_USER_LEVEL15                 = 0x00000092,
14804SQ_PERF_SEL_POWER_VALU                   = 0x00000093,
14805SQ_PERF_SEL_POWER_VALU0                  = 0x00000094,
14806SQ_PERF_SEL_POWER_VALU1                  = 0x00000095,
14807SQ_PERF_SEL_POWER_VALU2                  = 0x00000096,
14808SQ_PERF_SEL_POWER_GPR_RD                 = 0x00000097,
14809SQ_PERF_SEL_POWER_GPR_WR                 = 0x00000098,
14810SQ_PERF_SEL_POWER_LDS_BUSY               = 0x00000099,
14811SQ_PERF_SEL_POWER_ALU_BUSY               = 0x0000009a,
14812SQ_PERF_SEL_POWER_TEX_BUSY               = 0x0000009b,
14813SQ_PERF_SEL_ACCUM_PREV_HIRES             = 0x0000009c,
14814SQ_PERF_SEL_WAVES_RESTORED               = 0x0000009d,
14815SQ_PERF_SEL_WAVES_SAVED                  = 0x0000009e,
14816SQ_PERF_SEL_INSTS_SMEM_NORM              = 0x0000009f,
14817SQ_PERF_SEL_ATC_INSTS_VMEM               = 0x000000a0,
14818SQ_PERF_SEL_ATC_INST_LEVEL_VMEM          = 0x000000a1,
14819SQ_PERF_SEL_ATC_XNACK_FIRST              = 0x000000a2,
14820SQ_PERF_SEL_ATC_XNACK_ALL                = 0x000000a3,
14821SQ_PERF_SEL_ATC_XNACK_FIFO_FULL          = 0x000000a4,
14822SQ_PERF_SEL_ATC_INSTS_SMEM               = 0x000000a5,
14823SQ_PERF_SEL_ATC_INST_LEVEL_SMEM          = 0x000000a6,
14824SQ_PERF_SEL_IFETCH_XNACK                 = 0x000000a7,
14825SQ_PERF_SEL_TLB_SHOOTDOWN                = 0x000000a8,
14826SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES         = 0x000000a9,
14827SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY         = 0x000000aa,
14828SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY         = 0x000000ab,
14829SQ_PERF_SEL_INSTS_VMEM_REPLAY            = 0x000000ac,
14830SQ_PERF_SEL_INSTS_SMEM_REPLAY            = 0x000000ad,
14831SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY       = 0x000000ae,
14832SQ_PERF_SEL_INSTS_FLAT_REPLAY            = 0x000000af,
14833SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY        = 0x000000b0,
14834SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY        = 0x000000b1,
14835SQ_PERF_SEL_UTCL1_TRANSLATION_MISS       = 0x000000b2,
14836SQ_PERF_SEL_UTCL1_PERMISSION_MISS        = 0x000000b3,
14837SQ_PERF_SEL_UTCL1_REQUEST                = 0x000000b4,
14838SQ_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL    = 0x000000b5,
14839SQ_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX     = 0x000000b6,
14840SQ_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT     = 0x000000b7,
14841SQ_PERF_SEL_UTCL1_LFIFO_FULL             = 0x000000b8,
14842SQ_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES    = 0x000000b9,
14843SQ_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS  = 0x000000ba,
14844SQ_PERF_SEL_DUMMY_END                    = 0x000000bb,
14845SQ_PERF_SEL_DUMMY_LAST                   = 0x000000ff,
14846SQC_PERF_SEL_ICACHE_INPUT_VALID_READY    = 0x00000100,
14847SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB   = 0x00000101,
14848SQC_PERF_SEL_ICACHE_INPUT_VALIDB         = 0x00000102,
14849SQC_PERF_SEL_DCACHE_INPUT_VALID_READY    = 0x00000103,
14850SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB   = 0x00000104,
14851SQC_PERF_SEL_DCACHE_INPUT_VALIDB         = 0x00000105,
14852SQC_PERF_SEL_TC_REQ                      = 0x00000106,
14853SQC_PERF_SEL_TC_INST_REQ                 = 0x00000107,
14854SQC_PERF_SEL_TC_DATA_READ_REQ            = 0x00000108,
14855SQC_PERF_SEL_TC_DATA_WRITE_REQ           = 0x00000109,
14856SQC_PERF_SEL_TC_DATA_ATOMIC_REQ          = 0x0000010a,
14857SQC_PERF_SEL_TC_STALL                    = 0x0000010b,
14858SQC_PERF_SEL_TC_STARVE                   = 0x0000010c,
14859SQC_PERF_SEL_ICACHE_BUSY_CYCLES          = 0x0000010d,
14860SQC_PERF_SEL_ICACHE_REQ                  = 0x0000010e,
14861SQC_PERF_SEL_ICACHE_HITS                 = 0x0000010f,
14862SQC_PERF_SEL_ICACHE_MISSES               = 0x00000110,
14863SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE     = 0x00000111,
14864SQC_PERF_SEL_ICACHE_INVAL_INST           = 0x00000112,
14865SQC_PERF_SEL_ICACHE_INVAL_ASYNC          = 0x00000113,
14866SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT  = 0x00000114,
14867SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB  = 0x00000115,
14868SQC_PERF_SEL_ICACHE_CACHE_STALLED        = 0x00000116,
14869SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO  = 0x00000117,
14870SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX  = 0x00000118,
14871SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT   = 0x00000119,
14872SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO  = 0x0000011a,
14873SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO  = 0x0000011b,
14874SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF  = 0x0000011c,
14875SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT  = 0x0000011d,
14876SQC_PERF_SEL_ICACHE_PREFETCH_1           = 0x0000011e,
14877SQC_PERF_SEL_ICACHE_PREFETCH_2           = 0x0000011f,
14878SQC_PERF_SEL_ICACHE_PREFETCH_FILTERED    = 0x00000120,
14879SQC_PERF_SEL_DCACHE_BUSY_CYCLES          = 0x00000121,
14880SQC_PERF_SEL_DCACHE_REQ                  = 0x00000122,
14881SQC_PERF_SEL_DCACHE_HITS                 = 0x00000123,
14882SQC_PERF_SEL_DCACHE_MISSES               = 0x00000124,
14883SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE     = 0x00000125,
14884SQC_PERF_SEL_DCACHE_HIT_LRU_READ         = 0x00000126,
14885SQC_PERF_SEL_DCACHE_MISS_EVICT_READ      = 0x00000127,
14886SQC_PERF_SEL_DCACHE_WC_LRU_WRITE         = 0x00000128,
14887SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE       = 0x00000129,
14888SQC_PERF_SEL_DCACHE_ATOMIC               = 0x0000012a,
14889SQC_PERF_SEL_DCACHE_VOLATILE             = 0x0000012b,
14890SQC_PERF_SEL_DCACHE_INVAL_INST           = 0x0000012c,
14891SQC_PERF_SEL_DCACHE_INVAL_ASYNC          = 0x0000012d,
14892SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST  = 0x0000012e,
14893SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC  = 0x0000012f,
14894SQC_PERF_SEL_DCACHE_WB_INST              = 0x00000130,
14895SQC_PERF_SEL_DCACHE_WB_ASYNC             = 0x00000131,
14896SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST     = 0x00000132,
14897SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC    = 0x00000133,
14898SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT  = 0x00000134,
14899SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB  = 0x00000135,
14900SQC_PERF_SEL_DCACHE_CACHE_STALLED        = 0x00000136,
14901SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX  = 0x00000137,
14902SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT   = 0x00000138,
14903SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT    = 0x00000139,
14904SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED  = 0x0000013a,
14905SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE  = 0x0000013b,
14906SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT  = 0x0000013c,
14907SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH  = 0x0000013d,
14908SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE  = 0x0000013e,
14909SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO  = 0x0000013f,
14910SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO  = 0x00000140,
14911SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF  = 0x00000141,
14912SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT  = 0x00000142,
14913SQC_PERF_SEL_DCACHE_REQ_READ_1           = 0x00000143,
14914SQC_PERF_SEL_DCACHE_REQ_READ_2           = 0x00000144,
14915SQC_PERF_SEL_DCACHE_REQ_READ_4           = 0x00000145,
14916SQC_PERF_SEL_DCACHE_REQ_READ_8           = 0x00000146,
14917SQC_PERF_SEL_DCACHE_REQ_READ_16          = 0x00000147,
14918SQC_PERF_SEL_DCACHE_REQ_TIME             = 0x00000148,
14919SQC_PERF_SEL_DCACHE_REQ_WRITE_1          = 0x00000149,
14920SQC_PERF_SEL_DCACHE_REQ_WRITE_2          = 0x0000014a,
14921SQC_PERF_SEL_DCACHE_REQ_WRITE_4          = 0x0000014b,
14922SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE        = 0x0000014c,
14923SQC_PERF_SEL_SQ_DCACHE_REQS              = 0x0000014d,
14924SQC_PERF_SEL_DCACHE_FLAT_REQ             = 0x0000014e,
14925SQC_PERF_SEL_DCACHE_NONFLAT_REQ          = 0x0000014f,
14926SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL       = 0x00000150,
14927SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL       = 0x00000151,
14928SQC_PERF_SEL_TC_INFLIGHT_LEVEL           = 0x00000152,
14929SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL    = 0x00000153,
14930SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL    = 0x00000154,
14931SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS  = 0x00000155,
14932SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS  = 0x00000156,
14933SQC_PERF_SEL_ICACHE_GATCL1_REQUEST       = 0x00000157,
14934SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX  = 0x00000158,
14935SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT  = 0x00000159,
14936SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL    = 0x0000015a,
14937SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES  = 0x0000015b,
14938SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS  = 0x0000015c,
14939SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT  = 0x0000015d,
14940SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL  = 0x0000015e,
14941SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS  = 0x0000015f,
14942SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS  = 0x00000160,
14943SQC_PERF_SEL_DCACHE_GATCL1_REQUEST       = 0x00000161,
14944SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX  = 0x00000162,
14945SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT  = 0x00000163,
14946SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL    = 0x00000164,
14947SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES  = 0x00000165,
14948SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS  = 0x00000166,
14949SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT  = 0x00000167,
14950SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL  = 0x00000168,
14951SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS  = 0x00000169,
14952SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL  = 0x0000016a,
14953SQC_PERF_SEL_DUMMY_LAST                  = 0x0000016b,
14954} SQ_PERF_SEL;
14955
14956/*
14957 * SQ_CAC_POWER_SEL enum
14958 */
14959
14960typedef enum SQ_CAC_POWER_SEL {
14961SQ_CAC_POWER_VALU                        = 0x00000000,
14962SQ_CAC_POWER_VALU0                       = 0x00000001,
14963SQ_CAC_POWER_VALU1                       = 0x00000002,
14964SQ_CAC_POWER_VALU2                       = 0x00000003,
14965SQ_CAC_POWER_GPR_RD                      = 0x00000004,
14966SQ_CAC_POWER_GPR_WR                      = 0x00000005,
14967SQ_CAC_POWER_LDS_BUSY                    = 0x00000006,
14968SQ_CAC_POWER_ALU_BUSY                    = 0x00000007,
14969SQ_CAC_POWER_TEX_BUSY                    = 0x00000008,
14970} SQ_CAC_POWER_SEL;
14971
14972/*
14973 * SQ_IND_CMD_CMD enum
14974 */
14975
14976typedef enum SQ_IND_CMD_CMD {
14977SQ_IND_CMD_CMD_NULL                      = 0x00000000,
14978SQ_IND_CMD_CMD_SETHALT                   = 0x00000001,
14979SQ_IND_CMD_CMD_SAVECTX                   = 0x00000002,
14980SQ_IND_CMD_CMD_KILL                      = 0x00000003,
14981SQ_IND_CMD_CMD_DEBUG                     = 0x00000004,
14982SQ_IND_CMD_CMD_TRAP                      = 0x00000005,
14983SQ_IND_CMD_CMD_SET_SPI_PRIO              = 0x00000006,
14984SQ_IND_CMD_CMD_SETFATALHALT              = 0x00000007,
14985} SQ_IND_CMD_CMD;
14986
14987/*
14988 * SQ_IND_CMD_MODE enum
14989 */
14990
14991typedef enum SQ_IND_CMD_MODE {
14992SQ_IND_CMD_MODE_SINGLE                   = 0x00000000,
14993SQ_IND_CMD_MODE_BROADCAST                = 0x00000001,
14994SQ_IND_CMD_MODE_BROADCAST_QUEUE          = 0x00000002,
14995SQ_IND_CMD_MODE_BROADCAST_PIPE           = 0x00000003,
14996SQ_IND_CMD_MODE_BROADCAST_ME             = 0x00000004,
14997} SQ_IND_CMD_MODE;
14998
14999/*
15000 * SQ_EDC_INFO_SOURCE enum

15001 */
15002
15003typedef enum SQ_EDC_INFO_SOURCE {
15004SQ_EDC_INFO_SOURCE_INVALID               = 0x00000000,
15005SQ_EDC_INFO_SOURCE_INST                  = 0x00000001,
15006SQ_EDC_INFO_SOURCE_SGPR                  = 0x00000002,
15007SQ_EDC_INFO_SOURCE_VGPR                  = 0x00000003,
15008SQ_EDC_INFO_SOURCE_LDS                   = 0x00000004,
15009SQ_EDC_INFO_SOURCE_GDS                   = 0x00000005,
15010SQ_EDC_INFO_SOURCE_TA                    = 0x00000006,
15011} SQ_EDC_INFO_SOURCE;
15012
15013/*
15014 * SQ_ROUND_MODE enum
15015 */
15016
15017typedef enum SQ_ROUND_MODE {
15018SQ_ROUND_NEAREST_EVEN                    = 0x00000000,
15019SQ_ROUND_PLUS_INFINITY                   = 0x00000001,
15020SQ_ROUND_MINUS_INFINITY                  = 0x00000002,
15021SQ_ROUND_TO_ZERO                         = 0x00000003,
15022} SQ_ROUND_MODE;
15023
15024/*
15025 * SQ_INTERRUPT_WORD_ENCODING enum
15026 */
15027
15028typedef enum SQ_INTERRUPT_WORD_ENCODING {
15029SQ_INTERRUPT_WORD_ENCODING_AUTO          = 0x00000000,
15030SQ_INTERRUPT_WORD_ENCODING_INST          = 0x00000001,
15031SQ_INTERRUPT_WORD_ENCODING_ERROR         = 0x00000002,
15032} SQ_INTERRUPT_WORD_ENCODING;
15033
15034/*
15035 * ENUM_SQ_EXPORT_RAT_INST enum
15036 */
15037
15038typedef enum ENUM_SQ_EXPORT_RAT_INST {
15039SQ_EXPORT_RAT_INST_NOP                   = 0x00000000,
15040SQ_EXPORT_RAT_INST_STORE_TYPED           = 0x00000001,
15041SQ_EXPORT_RAT_INST_STORE_RAW             = 0x00000002,
15042SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM     = 0x00000003,
15043SQ_EXPORT_RAT_INST_CMPXCHG_INT           = 0x00000004,
15044SQ_EXPORT_RAT_INST_CMPXCHG_FLT           = 0x00000005,
15045SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM       = 0x00000006,
15046SQ_EXPORT_RAT_INST_ADD                   = 0x00000007,
15047SQ_EXPORT_RAT_INST_SUB                   = 0x00000008,
15048SQ_EXPORT_RAT_INST_RSUB                  = 0x00000009,
15049SQ_EXPORT_RAT_INST_MIN_INT               = 0x0000000a,
15050SQ_EXPORT_RAT_INST_MIN_UINT              = 0x0000000b,
15051SQ_EXPORT_RAT_INST_MAX_INT               = 0x0000000c,
15052SQ_EXPORT_RAT_INST_MAX_UINT              = 0x0000000d,
15053SQ_EXPORT_RAT_INST_AND                   = 0x0000000e,
15054SQ_EXPORT_RAT_INST_OR                    = 0x0000000f,
15055SQ_EXPORT_RAT_INST_XOR                   = 0x00000010,
15056SQ_EXPORT_RAT_INST_MSKOR                 = 0x00000011,
15057SQ_EXPORT_RAT_INST_INC_UINT              = 0x00000012,
15058SQ_EXPORT_RAT_INST_DEC_UINT              = 0x00000013,
15059SQ_EXPORT_RAT_INST_STORE_DWORD           = 0x00000014,
15060SQ_EXPORT_RAT_INST_STORE_SHORT           = 0x00000015,
15061SQ_EXPORT_RAT_INST_STORE_BYTE            = 0x00000016,
15062SQ_EXPORT_RAT_INST_NOP_RTN               = 0x00000020,
15063SQ_EXPORT_RAT_INST_XCHG_RTN              = 0x00000022,
15064SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN      = 0x00000023,
15065SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN       = 0x00000024,
15066SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN       = 0x00000025,
15067SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN   = 0x00000026,
15068SQ_EXPORT_RAT_INST_ADD_RTN               = 0x00000027,
15069SQ_EXPORT_RAT_INST_SUB_RTN               = 0x00000028,
15070SQ_EXPORT_RAT_INST_RSUB_RTN              = 0x00000029,
15071SQ_EXPORT_RAT_INST_MIN_INT_RTN           = 0x0000002a,
15072SQ_EXPORT_RAT_INST_MIN_UINT_RTN          = 0x0000002b,
15073SQ_EXPORT_RAT_INST_MAX_INT_RTN           = 0x0000002c,
15074SQ_EXPORT_RAT_INST_MAX_UINT_RTN          = 0x0000002d,
15075SQ_EXPORT_RAT_INST_AND_RTN               = 0x0000002e,
15076SQ_EXPORT_RAT_INST_OR_RTN                = 0x0000002f,
15077SQ_EXPORT_RAT_INST_XOR_RTN               = 0x00000030,
15078SQ_EXPORT_RAT_INST_MSKOR_RTN             = 0x00000031,
15079SQ_EXPORT_RAT_INST_INC_UINT_RTN          = 0x00000032,
15080SQ_EXPORT_RAT_INST_DEC_UINT_RTN          = 0x00000033,
15081} ENUM_SQ_EXPORT_RAT_INST;
15082
15083/*
15084 * SQ_IBUF_ST enum
15085 */
15086
15087typedef enum SQ_IBUF_ST {
15088SQ_IBUF_IB_IDLE                          = 0x00000000,
15089SQ_IBUF_IB_INI_WAIT_GNT                  = 0x00000001,
15090SQ_IBUF_IB_INI_WAIT_DRET                 = 0x00000002,
15091SQ_IBUF_IB_LE_4DW                        = 0x00000003,
15092SQ_IBUF_IB_WAIT_DRET                     = 0x00000004,
15093SQ_IBUF_IB_EMPTY_WAIT_DRET               = 0x00000005,
15094SQ_IBUF_IB_DRET                          = 0x00000006,
15095SQ_IBUF_IB_EMPTY_WAIT_GNT                = 0x00000007,
15096} SQ_IBUF_ST;
15097
15098/*
15099 * SQ_INST_STR_ST enum
15100 */
15101
15102typedef enum SQ_INST_STR_ST {
15103SQ_INST_STR_IB_WAVE_NORML                = 0x00000000,
15104SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV    = 0x00000001,
15105SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV     = 0x00000002,
15106SQ_INST_STR_IB_WAVE_INST_SKIP_AV         = 0x00000003,
15107SQ_INST_STR_IB_WAVE_SETVSKIP_ST0         = 0x00000004,
15108SQ_INST_STR_IB_WAVE_SETVSKIP_ST1         = 0x00000005,
15109SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT       = 0x00000006,
15110SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT  = 0x00000007,
15111} SQ_INST_STR_ST;
15112
15113/*
15114 * SQ_WAVE_IB_ECC_ST enum
15115 */
15116
15117typedef enum SQ_WAVE_IB_ECC_ST {
15118SQ_WAVE_IB_ECC_CLEAN                     = 0x00000000,
15119SQ_WAVE_IB_ECC_ERR_CONTINUE              = 0x00000001,
15120SQ_WAVE_IB_ECC_ERR_HALT                  = 0x00000002,
15121SQ_WAVE_IB_ECC_WITH_ERR_MSG              = 0x00000003,
15122} SQ_WAVE_IB_ECC_ST;
15123
15124/*
15125 * SH_MEM_ADDRESS_MODE enum
15126 */
15127
15128typedef enum SH_MEM_ADDRESS_MODE {
15129SH_MEM_ADDRESS_MODE_64                   = 0x00000000,
15130SH_MEM_ADDRESS_MODE_32                   = 0x00000001,
15131} SH_MEM_ADDRESS_MODE;
15132
15133/*
15134 * SH_MEM_ALIGNMENT_MODE enum
15135 */
15136
15137typedef enum SH_MEM_ALIGNMENT_MODE {
15138SH_MEM_ALIGNMENT_MODE_DWORD              = 0x00000000,
15139SH_MEM_ALIGNMENT_MODE_DWORD_STRICT       = 0x00000001,
15140SH_MEM_ALIGNMENT_MODE_STRICT             = 0x00000002,
15141SH_MEM_ALIGNMENT_MODE_UNALIGNED          = 0x00000003,
15142} SH_MEM_ALIGNMENT_MODE;
15143
15144/*
15145 * SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX enum
15146 */
15147
15148typedef enum SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX {
15149SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC  = 0x00000018,
15150SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE  = 0x00000019,
15151} SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX;
15152
15153/*
15154 * SQ_LB_CTR_SEL_VALUES enum
15155 */
15156
15157typedef enum SQ_LB_CTR_SEL_VALUES {
15158SQ_LB_CTR_SEL_ALU_CYCLES                 = 0x00000000,
15159SQ_LB_CTR_SEL_ALU_STALLS                 = 0x00000001,
15160SQ_LB_CTR_SEL_TEX_CYCLES                 = 0x00000002,
15161SQ_LB_CTR_SEL_TEX_STALLS                 = 0x00000003,
15162SQ_LB_CTR_SEL_SALU_CYCLES                = 0x00000004,
15163SQ_LB_CTR_SEL_SCALAR_STALLS              = 0x00000005,
15164SQ_LB_CTR_SEL_SMEM_CYCLES                = 0x00000006,
15165SQ_LB_CTR_SEL_ICACHE_STALLS              = 0x00000007,
15166SQ_LB_CTR_SEL_DCACHE_STALLS              = 0x00000008,
15167SQ_LB_CTR_SEL_RESERVED0                  = 0x00000009,
15168SQ_LB_CTR_SEL_RESERVED1                  = 0x0000000a,
15169SQ_LB_CTR_SEL_RESERVED2                  = 0x0000000b,
15170SQ_LB_CTR_SEL_RESERVED3                  = 0x0000000c,
15171SQ_LB_CTR_SEL_RESERVED4                  = 0x0000000d,
15172SQ_LB_CTR_SEL_RESERVED5                  = 0x0000000e,
15173SQ_LB_CTR_SEL_RESERVED6                  = 0x0000000f,
15174} SQ_LB_CTR_SEL_VALUES;
15175
15176/*
15177 * SQ_WAVE_TYPE value
15178 */
15179
15180#define SQ_WAVE_TYPE_PS0               0x00000000
15181
15182/*
15183 * SQIND_PARTITIONS value
15184 */
15185
15186#define SQIND_GLOBAL_REGS_OFFSET       0x00000000
15187#define SQIND_GLOBAL_REGS_SIZE         0x00000008
15188#define SQIND_LOCAL_REGS_OFFSET        0x00000008
15189#define SQIND_LOCAL_REGS_SIZE          0x00000008
15190#define SQIND_WAVE_HWREGS_OFFSET       0x00000010
15191#define SQIND_WAVE_HWREGS_SIZE         0x000001f0
15192#define SQIND_WAVE_SGPRS_OFFSET        0x00000200
15193#define SQIND_WAVE_SGPRS_SIZE          0x00000200
15194#define SQIND_WAVE_VGPRS_OFFSET        0x00000400
15195#define SQIND_WAVE_VGPRS_SIZE          0x00000100
15196
15197/*
15198 * SQ_GFXDEC value
15199 */
15200
15201#define SQ_GFXDEC_BEGIN                0x0000a000
15202#define SQ_GFXDEC_END                  0x0000c000
15203#define SQ_GFXDEC_STATE_ID_SHIFT       0x0000000a
15204
15205/*
15206 * SQDEC value
15207 */
15208
15209#define SQDEC_BEGIN                    0x00002300
15210#define SQDEC_END                      0x000023ff
15211
15212/*
15213 * SQPERFSDEC value
15214 */
15215
15216#define SQPERFSDEC_BEGIN               0x0000d9c0
15217#define SQPERFSDEC_END                 0x0000da40
15218
15219/*
15220 * SQPERFDDEC value
15221 */
15222
15223#define SQPERFDDEC_BEGIN               0x0000d1c0
15224#define SQPERFDDEC_END                 0x0000d240
15225
15226/*
15227 * SQGFXUDEC value
15228 */
15229
15230#define SQGFXUDEC_BEGIN                0x0000c330
15231#define SQGFXUDEC_END                  0x0000c380
15232
15233/*
15234 * SQPWRDEC value
15235 */
15236
15237#define SQPWRDEC_BEGIN                 0x0000f08c
15238#define SQPWRDEC_END                   0x0000f094
15239
15240/*
15241 * SQ_DISPATCHER value
15242 */
15243
15244#define SQ_DISPATCHER_GFX_MIN          0x00000010
15245#define SQ_DISPATCHER_GFX_CNT_PER_RING 0x00000008
15246
15247/*
15248 * SQ_MAX value
15249 */
15250
15251#define SQ_MAX_PGM_SGPRS               0x00000068
15252#define SQ_MAX_PGM_VGPRS               0x00000100
15253
15254/*
15255 * SQ_THREAD_TRACE_TIME_UNIT value
15256 */
15257
15258#define SQ_THREAD_TRACE_TIME_UNIT      0x00000004
15259
15260/*
15261 * SQ_EXCP_BITS value
15262 */
15263
15264#define SQ_EX_MODE_EXCP_VALU_BASE      0x00000000
15265#define SQ_EX_MODE_EXCP_VALU_SIZE      0x00000007
15266#define SQ_EX_MODE_EXCP_INVALID        0x00000000
15267#define SQ_EX_MODE_EXCP_INPUT_DENORM   0x00000001
15268#define SQ_EX_MODE_EXCP_DIV0           0x00000002
15269#define SQ_EX_MODE_EXCP_OVERFLOW       0x00000003
15270#define SQ_EX_MODE_EXCP_UNDERFLOW      0x00000004
15271#define SQ_EX_MODE_EXCP_INEXACT        0x00000005
15272#define SQ_EX_MODE_EXCP_INT_DIV0       0x00000006
15273#define SQ_EX_MODE_EXCP_ADDR_WATCH0    0x00000007
15274#define SQ_EX_MODE_EXCP_MEM_VIOL       0x00000008
15275
15276/*
15277 * SQ_EXCP_HI_BITS value
15278 */
15279
15280#define SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 0x00000000
15281#define SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 0x00000001
15282#define SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 0x00000002
15283
15284/*
15285 * HW_INSERTED_INST_ID value
15286 */
15287
15288#define INST_ID_PRIV_START             0x80000000
15289#define INST_ID_ECC_INTERRUPT_MSG      0xfffffff0
15290#define INST_ID_TTRACE_NEW_PC_MSG      0xfffffff1
15291#define INST_ID_HW_TRAP                0xfffffff2
15292#define INST_ID_KILL_SEQ               0xfffffff3
15293#define INST_ID_SPI_WREXEC             0xfffffff4
15294#define INST_ID_HOST_REG_TRAP_MSG      0xfffffffe
15295
15296/*
15297 * SIMM16_WAITCNT_PARTITIONS value
15298 */
15299
15300#define SIMM16_WAITCNT_VM_CNT_START    0x00000000
15301#define SIMM16_WAITCNT_VM_CNT_SIZE     0x00000004
15302#define SIMM16_WAITCNT_EXP_CNT_START   0x00000004
15303#define SIMM16_WAITCNT_EXP_CNT_SIZE    0x00000003
15304#define SIMM16_WAITCNT_LGKM_CNT_START  0x00000008
15305#define SIMM16_WAITCNT_LGKM_CNT_SIZE   0x00000004
15306#define SIMM16_WAITCNT_VM_CNT_HI_START 0x0000000e
15307#define SIMM16_WAITCNT_VM_CNT_HI_SIZE  0x00000002
15308
15309/*
15310 * SQ_EDC_FUE_CNTL_BITS value
15311 */
15312
15313#define SQ_EDC_FUE_CNTL_SQ             0x00000000
15314#define SQ_EDC_FUE_CNTL_LDS            0x00000001
15315#define SQ_EDC_FUE_CNTL_SIMD0          0x00000002
15316#define SQ_EDC_FUE_CNTL_SIMD1          0x00000003
15317#define SQ_EDC_FUE_CNTL_SIMD2          0x00000004
15318#define SQ_EDC_FUE_CNTL_SIMD3          0x00000005
15319#define SQ_EDC_FUE_CNTL_TA             0x00000006
15320#define SQ_EDC_FUE_CNTL_TD             0x00000007
15321#define SQ_EDC_FUE_CNTL_TCP            0x00000008
15322
15323/*******************************************************
15324 * COMP Enums
15325 *******************************************************/
15326
15327/*
15328 * CSDATA_TYPE enum
15329 */
15330
15331typedef enum CSDATA_TYPE {
15332CSDATA_TYPE_TG                           = 0x00000000,
15333CSDATA_TYPE_STATE                        = 0x00000001,
15334CSDATA_TYPE_EVENT                        = 0x00000002,
15335CSDATA_TYPE_PRIVATE                      = 0x00000003,
15336} CSDATA_TYPE;
15337
15338/*
15339 * CSDATA_TYPE_WIDTH value
15340 */
15341
15342#define CSDATA_TYPE_WIDTH              0x00000002
15343
15344/*
15345 * CSDATA_ADDR_WIDTH value
15346 */
15347
15348#define CSDATA_ADDR_WIDTH              0x00000007
15349
15350/*
15351 * CSDATA_DATA_WIDTH value
15352 */
15353
15354#define CSDATA_DATA_WIDTH              0x00000020
15355
15356/*******************************************************
15357 * VGT Enums
15358 *******************************************************/
15359
15360/*
15361 * VGT_OUT_PRIM_TYPE enum
15362 */
15363
15364typedef enum VGT_OUT_PRIM_TYPE {
15365VGT_OUT_POINT                            = 0x00000000,
15366VGT_OUT_LINE                             = 0x00000001,
15367VGT_OUT_TRI                              = 0x00000002,
15368VGT_OUT_RECT_V0                          = 0x00000003,
15369VGT_OUT_RECT_V1                          = 0x00000004,
15370VGT_OUT_RECT_V2                          = 0x00000005,
15371VGT_OUT_RECT_V3                          = 0x00000006,
15372VGT_OUT_2D_RECT                          = 0x00000007,
15373VGT_TE_QUAD                              = 0x00000008,
15374VGT_TE_PRIM_INDEX_LINE                   = 0x00000009,
15375VGT_TE_PRIM_INDEX_TRI                    = 0x0000000a,
15376VGT_TE_PRIM_INDEX_QUAD                   = 0x0000000b,
15377VGT_OUT_LINE_ADJ                         = 0x0000000c,
15378VGT_OUT_TRI_ADJ                          = 0x0000000d,
15379VGT_OUT_PATCH                            = 0x0000000e,
15380} VGT_OUT_PRIM_TYPE;
15381
15382/*
15383 * VGT_DI_PRIM_TYPE enum
15384 */
15385
15386typedef enum VGT_DI_PRIM_TYPE {
15387DI_PT_NONE                               = 0x00000000,
15388DI_PT_POINTLIST                          = 0x00000001,
15389DI_PT_LINELIST                           = 0x00000002,
15390DI_PT_LINESTRIP                          = 0x00000003,
15391DI_PT_TRILIST                            = 0x00000004,
15392DI_PT_TRIFAN                             = 0x00000005,
15393DI_PT_TRISTRIP                           = 0x00000006,
15394DI_PT_2D_RECTANGLE                       = 0x00000007,
15395DI_PT_UNUSED_1                           = 0x00000008,
15396DI_PT_PATCH                              = 0x00000009,
15397DI_PT_LINELIST_ADJ                       = 0x0000000a,
15398DI_PT_LINESTRIP_ADJ                      = 0x0000000b,
15399DI_PT_TRILIST_ADJ                        = 0x0000000c,
15400DI_PT_TRISTRIP_ADJ                       = 0x0000000d,
15401DI_PT_UNUSED_3                           = 0x0000000e,
15402DI_PT_UNUSED_4                           = 0x0000000f,
15403DI_PT_TRI_WITH_WFLAGS                    = 0x00000010,
15404DI_PT_RECTLIST                           = 0x00000011,
15405DI_PT_LINELOOP                           = 0x00000012,
15406DI_PT_QUADLIST                           = 0x00000013,
15407DI_PT_QUADSTRIP                          = 0x00000014,
15408DI_PT_POLYGON                            = 0x00000015,
15409} VGT_DI_PRIM_TYPE;
15410
15411/*
15412 * VGT_DI_SOURCE_SELECT enum
15413 */
15414
15415typedef enum VGT_DI_SOURCE_SELECT {
15416DI_SRC_SEL_DMA                           = 0x00000000,
15417DI_SRC_SEL_IMMEDIATE                     = 0x00000001,
15418DI_SRC_SEL_AUTO_INDEX                    = 0x00000002,
15419DI_SRC_SEL_RESERVED                      = 0x00000003,
15420} VGT_DI_SOURCE_SELECT;
15421
15422/*
15423 * VGT_DI_MAJOR_MODE_SELECT enum
15424 */
15425
15426typedef enum VGT_DI_MAJOR_MODE_SELECT {
15427DI_MAJOR_MODE_0                          = 0x00000000,
15428DI_MAJOR_MODE_1                          = 0x00000001,
15429} VGT_DI_MAJOR_MODE_SELECT;
15430
15431/*
15432 * VGT_DI_INDEX_SIZE enum
15433 */
15434
15435typedef enum VGT_DI_INDEX_SIZE {
15436DI_INDEX_SIZE_16_BIT                     = 0x00000000,
15437DI_INDEX_SIZE_32_BIT                     = 0x00000001,
15438DI_INDEX_SIZE_8_BIT                      = 0x00000002,
15439} VGT_DI_INDEX_SIZE;
15440
15441/*
15442 * VGT_EVENT_TYPE enum
15443 */
15444
15445typedef enum VGT_EVENT_TYPE {
15446Reserved_0x00                            = 0x00000000,
15447SAMPLE_STREAMOUTSTATS1                   = 0x00000001,
15448SAMPLE_STREAMOUTSTATS2                   = 0x00000002,
15449SAMPLE_STREAMOUTSTATS3                   = 0x00000003,
15450CACHE_FLUSH_TS                           = 0x00000004,
15451CONTEXT_DONE                             = 0x00000005,
15452CACHE_FLUSH                              = 0x00000006,
15453CS_PARTIAL_FLUSH                         = 0x00000007,
15454VGT_STREAMOUT_SYNC                       = 0x00000008,
15455Reserved_0x09                            = 0x00000009,
15456VGT_STREAMOUT_RESET                      = 0x0000000a,
15457END_OF_PIPE_INCR_DE                      = 0x0000000b,
15458END_OF_PIPE_IB_END                       = 0x0000000c,
15459RST_PIX_CNT                              = 0x0000000d,
15460BREAK_BATCH                              = 0x0000000e,
15461VS_PARTIAL_FLUSH                         = 0x0000000f,
15462PS_PARTIAL_FLUSH                         = 0x00000010,
15463FLUSH_HS_OUTPUT                          = 0x00000011,
15464FLUSH_DFSM                               = 0x00000012,
15465RESET_TO_LOWEST_VGT                      = 0x00000013,
15466CACHE_FLUSH_AND_INV_TS_EVENT             = 0x00000014,
15467ZPASS_DONE                               = 0x00000015,
15468CACHE_FLUSH_AND_INV_EVENT                = 0x00000016,
15469PERFCOUNTER_START                        = 0x00000017,
15470PERFCOUNTER_STOP                         = 0x00000018,
15471PIPELINESTAT_START                       = 0x00000019,
15472PIPELINESTAT_STOP                        = 0x0000001a,
15473PERFCOUNTER_SAMPLE                       = 0x0000001b,
15474Available_0x1c                           = 0x0000001c,
15475Available_0x1d                           = 0x0000001d,
15476SAMPLE_PIPELINESTAT                      = 0x0000001e,
15477SO_VGTSTREAMOUT_FLUSH                    = 0x0000001f,
15478SAMPLE_STREAMOUTSTATS                    = 0x00000020,
15479RESET_VTX_CNT                            = 0x00000021,
15480BLOCK_CONTEXT_DONE                       = 0x00000022,
15481CS_CONTEXT_DONE                          = 0x00000023,
15482VGT_FLUSH                                = 0x00000024,
15483TGID_ROLLOVER                            = 0x00000025,
15484SQ_NON_EVENT                             = 0x00000026,
15485SC_SEND_DB_VPZ                           = 0x00000027,
15486BOTTOM_OF_PIPE_TS                        = 0x00000028,
15487FLUSH_SX_TS                              = 0x00000029,
15488DB_CACHE_FLUSH_AND_INV                   = 0x0000002a,
15489FLUSH_AND_INV_DB_DATA_TS                 = 0x0000002b,
15490FLUSH_AND_INV_DB_META                    = 0x0000002c,
15491FLUSH_AND_INV_CB_DATA_TS                 = 0x0000002d,
15492FLUSH_AND_INV_CB_META                    = 0x0000002e,
15493CS_DONE                                  = 0x0000002f,
15494PS_DONE                                  = 0x00000030,
15495FLUSH_AND_INV_CB_PIXEL_DATA              = 0x00000031,
15496SX_CB_RAT_ACK_REQUEST                    = 0x00000032,
15497THREAD_TRACE_START                       = 0x00000033,
15498THREAD_TRACE_STOP                        = 0x00000034,
15499THREAD_TRACE_MARKER                      = 0x00000035,
15500THREAD_TRACE_FLUSH                       = 0x00000036,
15501THREAD_TRACE_FINISH                      = 0x00000037,
15502PIXEL_PIPE_STAT_CONTROL                  = 0x00000038,
15503PIXEL_PIPE_STAT_DUMP                     = 0x00000039,
15504PIXEL_PIPE_STAT_RESET                    = 0x0000003a,
15505CONTEXT_SUSPEND                          = 0x0000003b,
15506OFFCHIP_HS_DEALLOC                       = 0x0000003c,
15507ENABLE_NGG_PIPELINE                      = 0x0000003d,
15508ENABLE_LEGACY_PIPELINE                   = 0x0000003e,
15509Reserved_0x3f                            = 0x0000003f,
15510} VGT_EVENT_TYPE;
15511
15512/*
15513 * VGT_DMA_SWAP_MODE enum
15514 */
15515
15516typedef enum VGT_DMA_SWAP_MODE {
15517VGT_DMA_SWAP_NONE                        = 0x00000000,
15518VGT_DMA_SWAP_16_BIT                      = 0x00000001,
15519VGT_DMA_SWAP_32_BIT                      = 0x00000002,
15520VGT_DMA_SWAP_WORD                        = 0x00000003,
15521} VGT_DMA_SWAP_MODE;
15522
15523/*
15524 * VGT_INDEX_TYPE_MODE enum
15525 */
15526
15527typedef enum VGT_INDEX_TYPE_MODE {
15528VGT_INDEX_16                             = 0x00000000,
15529VGT_INDEX_32                             = 0x00000001,
15530VGT_INDEX_8                              = 0x00000002,
15531} VGT_INDEX_TYPE_MODE;
15532
15533/*
15534 * VGT_DMA_BUF_TYPE enum
15535 */
15536
15537typedef enum VGT_DMA_BUF_TYPE {
15538VGT_DMA_BUF_MEM                          = 0x00000000,
15539VGT_DMA_BUF_RING                         = 0x00000001,
15540VGT_DMA_BUF_SETUP                        = 0x00000002,
15541VGT_DMA_PTR_UPDATE                       = 0x00000003,
15542} VGT_DMA_BUF_TYPE;
15543
15544/*
15545 * VGT_OUTPATH_SELECT enum
15546 */
15547
15548typedef enum VGT_OUTPATH_SELECT {
15549VGT_OUTPATH_VTX_REUSE                    = 0x00000000,
15550VGT_OUTPATH_TESS_EN                      = 0x00000001,
15551VGT_OUTPATH_PASSTHRU                     = 0x00000002,
15552VGT_OUTPATH_GS_BLOCK                     = 0x00000003,
15553VGT_OUTPATH_HS_BLOCK                     = 0x00000004,
15554VGT_OUTPATH_PRIM_GEN                     = 0x00000005,
15555} VGT_OUTPATH_SELECT;
15556
15557/*
15558 * VGT_GRP_PRIM_TYPE enum
15559 */
15560
15561typedef enum VGT_GRP_PRIM_TYPE {
15562VGT_GRP_3D_POINT                         = 0x00000000,
15563VGT_GRP_3D_LINE                          = 0x00000001,
15564VGT_GRP_3D_TRI                           = 0x00000002,
15565VGT_GRP_3D_RECT                          = 0x00000003,
15566VGT_GRP_3D_QUAD                          = 0x00000004,
15567VGT_GRP_2D_COPY_RECT_V0                  = 0x00000005,
15568VGT_GRP_2D_COPY_RECT_V1                  = 0x00000006,
15569VGT_GRP_2D_COPY_RECT_V2                  = 0x00000007,
15570VGT_GRP_2D_COPY_RECT_V3                  = 0x00000008,
15571VGT_GRP_2D_FILL_RECT                     = 0x00000009,
15572VGT_GRP_2D_LINE                          = 0x0000000a,
15573VGT_GRP_2D_TRI                           = 0x0000000b,
15574VGT_GRP_PRIM_INDEX_LINE                  = 0x0000000c,
15575VGT_GRP_PRIM_INDEX_TRI                   = 0x0000000d,
15576VGT_GRP_PRIM_INDEX_QUAD                  = 0x0000000e,
15577VGT_GRP_3D_LINE_ADJ                      = 0x0000000f,
15578VGT_GRP_3D_TRI_ADJ                       = 0x00000010,
15579VGT_GRP_3D_PATCH                         = 0x00000011,
15580VGT_GRP_2D_RECT                          = 0x00000012,
15581} VGT_GRP_PRIM_TYPE;
15582
15583/*
15584 * VGT_GRP_PRIM_ORDER enum
15585 */
15586
15587typedef enum VGT_GRP_PRIM_ORDER {
15588VGT_GRP_LIST                             = 0x00000000,
15589VGT_GRP_STRIP                            = 0x00000001,
15590VGT_GRP_FAN                              = 0x00000002,
15591VGT_GRP_LOOP                             = 0x00000003,
15592VGT_GRP_POLYGON                          = 0x00000004,
15593} VGT_GRP_PRIM_ORDER;
15594
15595/*
15596 * VGT_GROUP_CONV_SEL enum
15597 */
15598
15599typedef enum VGT_GROUP_CONV_SEL {
15600VGT_GRP_INDEX_16                         = 0x00000000,
15601VGT_GRP_INDEX_32                         = 0x00000001,
15602VGT_GRP_UINT_16                          = 0x00000002,
15603VGT_GRP_UINT_32                          = 0x00000003,
15604VGT_GRP_SINT_16                          = 0x00000004,
15605VGT_GRP_SINT_32                          = 0x00000005,
15606VGT_GRP_FLOAT_32                         = 0x00000006,
15607VGT_GRP_AUTO_PRIM                        = 0x00000007,
15608VGT_GRP_FIX_1_23_TO_FLOAT                = 0x00000008,
15609} VGT_GROUP_CONV_SEL;
15610
15611/*
15612 * VGT_GS_MODE_TYPE enum
15613 */
15614
15615typedef enum VGT_GS_MODE_TYPE {
15616GS_OFF                                   = 0x00000000,
15617GS_SCENARIO_A                            = 0x00000001,
15618GS_SCENARIO_B                            = 0x00000002,
15619GS_SCENARIO_G                            = 0x00000003,
15620GS_SCENARIO_C                            = 0x00000004,
15621SPRITE_EN                                = 0x00000005,
15622} VGT_GS_MODE_TYPE;
15623
15624/*
15625 * VGT_GS_CUT_MODE enum
15626 */
15627
15628typedef enum VGT_GS_CUT_MODE {
15629GS_CUT_1024                              = 0x00000000,
15630GS_CUT_512                               = 0x00000001,
15631GS_CUT_256                               = 0x00000002,
15632GS_CUT_128                               = 0x00000003,
15633} VGT_GS_CUT_MODE;
15634
15635/*
15636 * VGT_GS_OUTPRIM_TYPE enum
15637 */
15638
15639typedef enum VGT_GS_OUTPRIM_TYPE {
15640POINTLIST                                = 0x00000000,
15641LINESTRIP                                = 0x00000001,
15642TRISTRIP                                 = 0x00000002,
15643RECTLIST                                 = 0x00000003,
15644} VGT_GS_OUTPRIM_TYPE;
15645
15646/*
15647 * VGT_CACHE_INVALID_MODE enum
15648 */
15649
15650typedef enum VGT_CACHE_INVALID_MODE {
15651VC_ONLY                                  = 0x00000000,
15652TC_ONLY                                  = 0x00000001,
15653VC_AND_TC                                = 0x00000002,
15654} VGT_CACHE_INVALID_MODE;
15655
15656/*
15657 * VGT_TESS_TYPE enum
15658 */
15659
15660typedef enum VGT_TESS_TYPE {
15661TESS_ISOLINE                             = 0x00000000,
15662TESS_TRIANGLE                            = 0x00000001,
15663TESS_QUAD                                = 0x00000002,
15664} VGT_TESS_TYPE;
15665
15666/*
15667 * VGT_TESS_PARTITION enum
15668 */
15669
15670typedef enum VGT_TESS_PARTITION {
15671PART_INTEGER                             = 0x00000000,
15672PART_POW2                                = 0x00000001,
15673PART_FRAC_ODD                            = 0x00000002,
15674PART_FRAC_EVEN                           = 0x00000003,
15675} VGT_TESS_PARTITION;
15676
15677/*
15678 * VGT_TESS_TOPOLOGY enum
15679 */
15680
15681typedef enum VGT_TESS_TOPOLOGY {
15682OUTPUT_POINT                             = 0x00000000,
15683OUTPUT_LINE                              = 0x00000001,
15684OUTPUT_TRIANGLE_CW                       = 0x00000002,
15685OUTPUT_TRIANGLE_CCW                      = 0x00000003,
15686} VGT_TESS_TOPOLOGY;
15687
15688/*
15689 * VGT_RDREQ_POLICY enum
15690 */
15691
15692typedef enum VGT_RDREQ_POLICY {
15693VGT_POLICY_LRU                           = 0x00000000,
15694VGT_POLICY_STREAM                        = 0x00000001,
15695} VGT_RDREQ_POLICY;
15696
15697/*
15698 * VGT_DIST_MODE enum
15699 */
15700
15701typedef enum VGT_DIST_MODE {
15702NO_DIST                                  = 0x00000000,
15703PATCHES                                  = 0x00000001,
15704DONUTS                                   = 0x00000002,
15705TRAPEZOIDS                               = 0x00000003,
15706} VGT_DIST_MODE;
15707
15708/*
15709 * VGT_STAGES_LS_EN enum
15710 */
15711
15712typedef enum VGT_STAGES_LS_EN {
15713LS_STAGE_OFF                             = 0x00000000,
15714LS_STAGE_ON                              = 0x00000001,
15715CS_STAGE_ON                              = 0x00000002,
15716RESERVED_LS                              = 0x00000003,
15717} VGT_STAGES_LS_EN;
15718
15719/*
15720 * VGT_STAGES_HS_EN enum
15721 */
15722
15723typedef enum VGT_STAGES_HS_EN {
15724HS_STAGE_OFF                             = 0x00000000,
15725HS_STAGE_ON                              = 0x00000001,
15726} VGT_STAGES_HS_EN;
15727
15728/*
15729 * VGT_STAGES_ES_EN enum
15730 */
15731
15732typedef enum VGT_STAGES_ES_EN {
15733ES_STAGE_OFF                             = 0x00000000,
15734ES_STAGE_DS                              = 0x00000001,
15735ES_STAGE_REAL                            = 0x00000002,
15736RESERVED_ES                              = 0x00000003,
15737} VGT_STAGES_ES_EN;
15738
15739/*
15740 * VGT_STAGES_GS_EN enum
15741 */
15742
15743typedef enum VGT_STAGES_GS_EN {
15744GS_STAGE_OFF                             = 0x00000000,
15745GS_STAGE_ON                              = 0x00000001,
15746} VGT_STAGES_GS_EN;
15747
15748/*
15749 * VGT_STAGES_VS_EN enum
15750 */
15751
15752typedef enum VGT_STAGES_VS_EN {
15753VS_STAGE_REAL                            = 0x00000000,
15754VS_STAGE_DS                              = 0x00000001,
15755VS_STAGE_COPY_SHADER                     = 0x00000002,
15756RESERVED_VS                              = 0x00000003,
15757} VGT_STAGES_VS_EN;
15758
15759/*
15760 * VGT_PERFCOUNT_SELECT enum
15761 */
15762
15763typedef enum VGT_PERFCOUNT_SELECT {
15764vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE  = 0x00000000,
15765vgt_perf_VGT_SPI_ESVERT_VALID            = 0x00000001,
15766vgt_perf_VGT_SPI_ESVERT_EOV              = 0x00000002,
15767vgt_perf_VGT_SPI_ESVERT_STALLED          = 0x00000003,
15768vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY     = 0x00000004,
15769vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE     = 0x00000005,
15770vgt_perf_VGT_SPI_ESVERT_STATIC           = 0x00000006,
15771vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT       = 0x00000007,
15772vgt_perf_VGT_SPI_ESTHREAD_SEND           = 0x00000008,
15773vgt_perf_VGT_SPI_GSPRIM_VALID            = 0x00000009,
15774vgt_perf_VGT_SPI_GSPRIM_EOV              = 0x0000000a,
15775vgt_perf_VGT_SPI_GSPRIM_CONT             = 0x0000000b,
15776vgt_perf_VGT_SPI_GSPRIM_STALLED          = 0x0000000c,
15777vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY     = 0x0000000d,
15778vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE     = 0x0000000e,
15779vgt_perf_VGT_SPI_GSPRIM_STATIC           = 0x0000000f,
15780vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE  = 0x00000010,
15781vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT       = 0x00000011,
15782vgt_perf_VGT_SPI_GSTHREAD_SEND           = 0x00000012,
15783vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE  = 0x00000013,
15784vgt_perf_VGT_SPI_VSVERT_SEND             = 0x00000014,
15785vgt_perf_VGT_SPI_VSVERT_EOV              = 0x00000015,
15786vgt_perf_VGT_SPI_VSVERT_STALLED          = 0x00000016,
15787vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY     = 0x00000017,
15788vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE     = 0x00000018,
15789vgt_perf_VGT_SPI_VSVERT_STATIC           = 0x00000019,
15790vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT       = 0x0000001a,
15791vgt_perf_VGT_SPI_VSTHREAD_SEND           = 0x0000001b,
15792vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE      = 0x0000001c,
15793vgt_perf_VGT_PA_CLIPV_SEND               = 0x0000001d,
15794vgt_perf_VGT_PA_CLIPV_FIRSTVERT          = 0x0000001e,
15795vgt_perf_VGT_PA_CLIPV_STALLED            = 0x0000001f,
15796vgt_perf_VGT_PA_CLIPV_STARVED_BUSY       = 0x00000020,
15797vgt_perf_VGT_PA_CLIPV_STARVED_IDLE       = 0x00000021,
15798vgt_perf_VGT_PA_CLIPV_STATIC             = 0x00000022,
15799vgt_perf_VGT_PA_CLIPP_SEND               = 0x00000023,
15800vgt_perf_VGT_PA_CLIPP_EOP                = 0x00000024,
15801vgt_perf_VGT_PA_CLIPP_IS_EVENT           = 0x00000025,
15802vgt_perf_VGT_PA_CLIPP_NULL_PRIM          = 0x00000026,
15803vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT       = 0x00000027,
15804vgt_perf_VGT_PA_CLIPP_STALLED            = 0x00000028,
15805vgt_perf_VGT_PA_CLIPP_STARVED_BUSY       = 0x00000029,
15806vgt_perf_VGT_PA_CLIPP_STARVED_IDLE       = 0x0000002a,
15807vgt_perf_VGT_PA_CLIPP_STATIC             = 0x0000002b,
15808vgt_perf_VGT_PA_CLIPS_SEND               = 0x0000002c,
15809vgt_perf_VGT_PA_CLIPS_STALLED            = 0x0000002d,
15810vgt_perf_VGT_PA_CLIPS_STARVED_BUSY       = 0x0000002e,
15811vgt_perf_VGT_PA_CLIPS_STARVED_IDLE       = 0x0000002f,
15812vgt_perf_VGT_PA_CLIPS_STATIC             = 0x00000030,
15813vgt_perf_vsvert_ds_send                  = 0x00000031,
15814vgt_perf_vsvert_api_send                 = 0x00000032,
15815vgt_perf_hs_tif_stall                    = 0x00000033,
15816vgt_perf_hs_input_stall                  = 0x00000034,
15817vgt_perf_hs_interface_stall              = 0x00000035,
15818vgt_perf_hs_tfm_stall                    = 0x00000036,
15819vgt_perf_te11_starved                    = 0x00000037,
15820vgt_perf_gs_event_stall                  = 0x00000038,
15821vgt_perf_vgt_pa_clipp_send_not_event     = 0x00000039,
15822vgt_perf_vgt_pa_clipp_valid_prim         = 0x0000003a,
15823vgt_perf_reused_es_indices               = 0x0000003b,
15824vgt_perf_vs_cache_hits                   = 0x0000003c,
15825vgt_perf_gs_cache_hits                   = 0x0000003d,
15826vgt_perf_ds_cache_hits                   = 0x0000003e,
15827vgt_perf_total_cache_hits                = 0x0000003f,
15828vgt_perf_vgt_busy                        = 0x00000040,
15829vgt_perf_vgt_gs_busy                     = 0x00000041,
15830vgt_perf_esvert_stalled_es_tbl           = 0x00000042,
15831vgt_perf_esvert_stalled_gs_tbl           = 0x00000043,
15832vgt_perf_esvert_stalled_gs_event         = 0x00000044,
15833vgt_perf_esvert_stalled_gsprim           = 0x00000045,
15834vgt_perf_gsprim_stalled_es_tbl           = 0x00000046,
15835vgt_perf_gsprim_stalled_gs_tbl           = 0x00000047,
15836vgt_perf_gsprim_stalled_gs_event         = 0x00000048,
15837vgt_perf_gsprim_stalled_esvert           = 0x00000049,
15838vgt_perf_esthread_stalled_es_rb_full     = 0x0000004a,
15839vgt_perf_esthread_stalled_spi_bp         = 0x0000004b,
15840vgt_perf_counters_avail_stalled          = 0x0000004c,
15841vgt_perf_gs_rb_space_avail_stalled       = 0x0000004d,
15842vgt_perf_gs_issue_rtr_stalled            = 0x0000004e,
15843vgt_perf_gsthread_stalled                = 0x0000004f,
15844vgt_perf_strmout_stalled                 = 0x00000050,
15845vgt_perf_wait_for_es_done_stalled        = 0x00000051,
15846vgt_perf_cm_stalled_by_gog               = 0x00000052,
15847vgt_perf_cm_reading_stalled              = 0x00000053,
15848vgt_perf_cm_stalled_by_gsfetch_done      = 0x00000054,
15849vgt_perf_gog_vs_tbl_stalled              = 0x00000055,
15850vgt_perf_gog_out_indx_stalled            = 0x00000056,
15851vgt_perf_gog_out_prim_stalled            = 0x00000057,
15852vgt_perf_waveid_stalled                  = 0x00000058,
15853vgt_perf_gog_busy                        = 0x00000059,
15854vgt_perf_reused_vs_indices               = 0x0000005a,
15855vgt_perf_sclk_reg_vld_event              = 0x0000005b,
15856vgt_perf_vs_conflicting_indices          = 0x0000005c,
15857vgt_perf_sclk_core_vld_event             = 0x0000005d,
15858vgt_perf_hswave_stalled                  = 0x0000005e,
15859vgt_perf_sclk_gs_vld_event               = 0x0000005f,
15860vgt_perf_VGT_SPI_LSVERT_VALID            = 0x00000060,
15861vgt_perf_VGT_SPI_LSVERT_EOV              = 0x00000061,
15862vgt_perf_VGT_SPI_LSVERT_STALLED          = 0x00000062,
15863vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY     = 0x00000063,
15864vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE     = 0x00000064,
15865vgt_perf_VGT_SPI_LSVERT_STATIC           = 0x00000065,
15866vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE  = 0x00000066,
15867vgt_perf_VGT_SPI_LSWAVE_IS_EVENT         = 0x00000067,
15868vgt_perf_VGT_SPI_LSWAVE_SEND             = 0x00000068,
15869vgt_perf_VGT_SPI_HSVERT_VALID            = 0x00000069,
15870vgt_perf_VGT_SPI_HSVERT_EOV              = 0x0000006a,
15871vgt_perf_VGT_SPI_HSVERT_STALLED          = 0x0000006b,
15872vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY     = 0x0000006c,
15873vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE     = 0x0000006d,
15874vgt_perf_VGT_SPI_HSVERT_STATIC           = 0x0000006e,
15875vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE  = 0x0000006f,
15876vgt_perf_VGT_SPI_HSWAVE_IS_EVENT         = 0x00000070,
15877vgt_perf_VGT_SPI_HSWAVE_SEND             = 0x00000071,
15878vgt_perf_ds_prims                        = 0x00000072,
15879vgt_perf_ds_RESERVED                     = 0x00000073,
15880vgt_perf_ls_thread_groups                = 0x00000074,
15881vgt_perf_hs_thread_groups                = 0x00000075,
15882vgt_perf_es_thread_groups                = 0x00000076,
15883vgt_perf_vs_thread_groups                = 0x00000077,
15884vgt_perf_ls_done_latency                 = 0x00000078,
15885vgt_perf_hs_done_latency                 = 0x00000079,
15886vgt_perf_es_done_latency                 = 0x0000007a,
15887vgt_perf_gs_done_latency                 = 0x0000007b,
15888vgt_perf_vgt_hs_busy                     = 0x0000007c,
15889vgt_perf_vgt_te11_busy                   = 0x0000007d,
15890vgt_perf_ls_flush                        = 0x0000007e,
15891vgt_perf_hs_flush                        = 0x0000007f,
15892vgt_perf_es_flush                        = 0x00000080,
15893vgt_perf_vgt_pa_clipp_eopg               = 0x00000081,
15894vgt_perf_ls_done                         = 0x00000082,
15895vgt_perf_hs_done                         = 0x00000083,
15896vgt_perf_es_done                         = 0x00000084,
15897vgt_perf_gs_done                         = 0x00000085,
15898vgt_perf_vsfetch_done                    = 0x00000086,
15899vgt_perf_gs_done_received                = 0x00000087,
15900vgt_perf_es_ring_high_water_mark         = 0x00000088,
15901vgt_perf_gs_ring_high_water_mark         = 0x00000089,
15902vgt_perf_vs_table_high_water_mark        = 0x0000008a,
15903vgt_perf_hs_tgs_active_high_water_mark   = 0x0000008b,
15904vgt_perf_pa_clipp_dealloc                = 0x0000008c,
15905vgt_perf_cut_mem_flush_stalled           = 0x0000008d,
15906vgt_perf_vsvert_work_received            = 0x0000008e,
15907vgt_perf_vgt_pa_clipp_starved_after_work  = 0x0000008f,
15908vgt_perf_te11_con_starved_after_work     = 0x00000090,
15909vgt_perf_hs_waiting_on_ls_done_stall     = 0x00000091,
15910vgt_spi_vsvert_valid                     = 0x00000092,
15911} VGT_PERFCOUNT_SELECT;
15912
15913/*
15914 * IA_PERFCOUNT_SELECT enum
15915 */
15916
15917typedef enum IA_PERFCOUNT_SELECT {
15918ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE    = 0x00000000,
15919ia_perf_dma_data_fifo_full               = 0x00000001,
15920ia_perf_RESERVED1                        = 0x00000002,
15921ia_perf_RESERVED2                        = 0x00000003,
15922ia_perf_RESERVED3                        = 0x00000004,
15923ia_perf_RESERVED4                        = 0x00000005,
15924ia_perf_RESERVED5                        = 0x00000006,
15925ia_perf_MC_LAT_BIN_0                     = 0x00000007,
15926ia_perf_MC_LAT_BIN_1                     = 0x00000008,
15927ia_perf_MC_LAT_BIN_2                     = 0x00000009,
15928ia_perf_MC_LAT_BIN_3                     = 0x0000000a,
15929ia_perf_MC_LAT_BIN_4                     = 0x0000000b,
15930ia_perf_MC_LAT_BIN_5                     = 0x0000000c,
15931ia_perf_MC_LAT_BIN_6                     = 0x0000000d,
15932ia_perf_MC_LAT_BIN_7                     = 0x0000000e,
15933ia_perf_ia_busy                          = 0x0000000f,
15934ia_perf_ia_sclk_reg_vld_event            = 0x00000010,
15935ia_perf_RESERVED6                        = 0x00000011,
15936ia_perf_ia_sclk_core_vld_event           = 0x00000012,
15937ia_perf_RESERVED7                        = 0x00000013,
15938ia_perf_ia_dma_return                    = 0x00000014,
15939ia_perf_ia_stalled                       = 0x00000015,
15940ia_perf_shift_starved_pipe0_event        = 0x00000016,
15941ia_perf_shift_starved_pipe1_event        = 0x00000017,
15942} IA_PERFCOUNT_SELECT;
15943
15944/*
15945 * WD_PERFCOUNT_SELECT enum
15946 */
15947
15948typedef enum WD_PERFCOUNT_SELECT {
15949wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE   = 0x00000000,
15950wd_perf_RBIU_DR_FIFO_STARVED             = 0x00000001,
15951wd_perf_RBIU_DR_FIFO_STALLED             = 0x00000002,
15952wd_perf_RBIU_DI_FIFO_STARVED             = 0x00000003,
15953wd_perf_RBIU_DI_FIFO_STALLED             = 0x00000004,
15954wd_perf_wd_busy                          = 0x00000005,
15955wd_perf_wd_sclk_reg_vld_event            = 0x00000006,
15956wd_perf_wd_sclk_input_vld_event          = 0x00000007,
15957wd_perf_wd_sclk_core_vld_event           = 0x00000008,
15958wd_perf_wd_stalled                       = 0x00000009,
15959wd_perf_inside_tf_bin_0                  = 0x0000000a,
15960wd_perf_inside_tf_bin_1                  = 0x0000000b,
15961wd_perf_inside_tf_bin_2                  = 0x0000000c,
15962wd_perf_inside_tf_bin_3                  = 0x0000000d,
15963wd_perf_inside_tf_bin_4                  = 0x0000000e,
15964wd_perf_inside_tf_bin_5                  = 0x0000000f,
15965wd_perf_inside_tf_bin_6                  = 0x00000010,
15966wd_perf_inside_tf_bin_7                  = 0x00000011,
15967wd_perf_inside_tf_bin_8                  = 0x00000012,
15968wd_perf_tfreq_lat_bin_0                  = 0x00000013,
15969wd_perf_tfreq_lat_bin_1                  = 0x00000014,
15970wd_perf_tfreq_lat_bin_2                  = 0x00000015,
15971wd_perf_tfreq_lat_bin_3                  = 0x00000016,
15972wd_perf_tfreq_lat_bin_4                  = 0x00000017,
15973wd_perf_tfreq_lat_bin_5                  = 0x00000018,
15974wd_perf_tfreq_lat_bin_6                  = 0x00000019,
15975wd_perf_tfreq_lat_bin_7                  = 0x0000001a,
15976wd_starved_on_hs_done                    = 0x0000001b,
15977wd_perf_se0_hs_done_latency              = 0x0000001c,
15978wd_perf_se1_hs_done_latency              = 0x0000001d,
15979wd_perf_se2_hs_done_latency              = 0x0000001e,
15980wd_perf_se3_hs_done_latency              = 0x0000001f,
15981wd_perf_hs_done_se0                      = 0x00000020,
15982wd_perf_hs_done_se1                      = 0x00000021,
15983wd_perf_hs_done_se2                      = 0x00000022,
15984wd_perf_hs_done_se3                      = 0x00000023,
15985wd_perf_null_patches                     = 0x00000024,
15986} WD_PERFCOUNT_SELECT;
15987
15988/*
15989 * WD_IA_DRAW_TYPE enum
15990 */
15991
15992typedef enum WD_IA_DRAW_TYPE {
15993WD_IA_DRAW_TYPE_DI_MM0                   = 0x00000000,
15994WD_IA_DRAW_TYPE_REG_XFER                 = 0x00000001,
15995WD_IA_DRAW_TYPE_EVENT_INIT               = 0x00000002,
15996WD_IA_DRAW_TYPE_EVENT_ADDR               = 0x00000003,
15997WD_IA_DRAW_TYPE_MIN_INDX                 = 0x00000004,
15998WD_IA_DRAW_TYPE_MAX_INDX                 = 0x00000005,
15999WD_IA_DRAW_TYPE_INDX_OFF                 = 0x00000006,
16000WD_IA_DRAW_TYPE_IMM_DATA                 = 0x00000007,

16001} WD_IA_DRAW_TYPE;
16002
16003/*
16004 * WD_IA_DRAW_REG_XFER enum
16005 */
16006
16007typedef enum WD_IA_DRAW_REG_XFER {
16008WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM   = 0x00000000,
16009WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 0x00000001,
16010} WD_IA_DRAW_REG_XFER;
16011
16012/*
16013 * WD_IA_DRAW_SOURCE enum
16014 */
16015
16016typedef enum WD_IA_DRAW_SOURCE {
16017WD_IA_DRAW_SOURCE_DMA                    = 0x00000000,
16018WD_IA_DRAW_SOURCE_IMMD                   = 0x00000001,
16019WD_IA_DRAW_SOURCE_AUTO                   = 0x00000002,
16020WD_IA_DRAW_SOURCE_OPAQ                   = 0x00000003,
16021} WD_IA_DRAW_SOURCE;
16022
16023/*
16024 * GS_THREADID_SIZE value
16025 */
16026
16027#define GSTHREADID_SIZE                0x00000002
16028
16029/*******************************************************
16030 * GB Enums
16031 *******************************************************/
16032
16033/*
16034 * GB_EDC_DED_MODE enum
16035 */
16036
16037typedef enum GB_EDC_DED_MODE {
16038GB_EDC_DED_MODE_LOG                      = 0x00000000,
16039GB_EDC_DED_MODE_HALT                     = 0x00000001,
16040GB_EDC_DED_MODE_INT_HALT                 = 0x00000002,
16041} GB_EDC_DED_MODE;
16042
16043/*
16044 * VALUE_GB_TILING_CONFIG_TABLE_SIZE value
16045 */
16046
16047#define GB_TILING_CONFIG_TABLE_SIZE    0x00000020
16048
16049/*
16050 * VALUE_GB_TILING_CONFIG_MACROTABLE_SIZE value
16051 */
16052
16053#define GB_TILING_CONFIG_MACROTABLE_SIZE 0x00000010
16054
16055/*******************************************************
16056 * TP Enums
16057 *******************************************************/
16058
16059/*
16060 * TA_TC_ADDR_MODES enum
16061 */
16062
16063typedef enum TA_TC_ADDR_MODES {
16064TA_TC_ADDR_MODE_DEFAULT                  = 0x00000000,
16065TA_TC_ADDR_MODE_COMP0                    = 0x00000001,
16066TA_TC_ADDR_MODE_COMP1                    = 0x00000002,
16067TA_TC_ADDR_MODE_COMP2                    = 0x00000003,
16068TA_TC_ADDR_MODE_COMP3                    = 0x00000004,
16069TA_TC_ADDR_MODE_UNALIGNED                = 0x00000005,
16070TA_TC_ADDR_MODE_BORDER_COLOR             = 0x00000006,
16071} TA_TC_ADDR_MODES;
16072
16073/*
16074 * TA_PERFCOUNT_SEL enum
16075 */
16076
16077typedef enum TA_PERFCOUNT_SEL {
16078TA_PERF_SEL_NULL                         = 0x00000000,
16079TA_PERF_SEL_sh_fifo_busy                 = 0x00000001,
16080TA_PERF_SEL_sh_fifo_cmd_busy             = 0x00000002,
16081TA_PERF_SEL_sh_fifo_addr_busy            = 0x00000003,
16082TA_PERF_SEL_sh_fifo_data_busy            = 0x00000004,
16083TA_PERF_SEL_sh_fifo_data_sfifo_busy      = 0x00000005,
16084TA_PERF_SEL_sh_fifo_data_tfifo_busy      = 0x00000006,
16085TA_PERF_SEL_gradient_busy                = 0x00000007,
16086TA_PERF_SEL_gradient_fifo_busy           = 0x00000008,
16087TA_PERF_SEL_lod_busy                     = 0x00000009,
16088TA_PERF_SEL_lod_fifo_busy                = 0x0000000a,
16089TA_PERF_SEL_addresser_busy               = 0x0000000b,
16090TA_PERF_SEL_addresser_fifo_busy          = 0x0000000c,
16091TA_PERF_SEL_aligner_busy                 = 0x0000000d,
16092TA_PERF_SEL_write_path_busy              = 0x0000000e,
16093TA_PERF_SEL_ta_busy                      = 0x0000000f,
16094TA_PERF_SEL_sq_ta_cmd_cycles             = 0x00000010,
16095TA_PERF_SEL_sp_ta_addr_cycles            = 0x00000011,
16096TA_PERF_SEL_sp_ta_data_cycles            = 0x00000012,
16097TA_PERF_SEL_ta_fa_data_state_cycles      = 0x00000013,
16098TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles  = 0x00000014,
16099TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles  = 0x00000015,
16100TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles  = 0x00000016,
16101TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles  = 0x00000017,
16102TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles  = 0x00000018,
16103TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles  = 0x00000019,
16104TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles  = 0x0000001a,
16105TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles  = 0x0000001b,
16106TA_PERF_SEL_RESERVED_28                  = 0x0000001c,
16107TA_PERF_SEL_RESERVED_29                  = 0x0000001d,
16108TA_PERF_SEL_sh_fifo_addr_cycles          = 0x0000001e,
16109TA_PERF_SEL_sh_fifo_data_cycles          = 0x0000001f,
16110TA_PERF_SEL_total_wavefronts             = 0x00000020,
16111TA_PERF_SEL_gradient_cycles              = 0x00000021,
16112TA_PERF_SEL_walker_cycles                = 0x00000022,
16113TA_PERF_SEL_aligner_cycles               = 0x00000023,
16114TA_PERF_SEL_image_wavefronts             = 0x00000024,
16115TA_PERF_SEL_image_read_wavefronts        = 0x00000025,
16116TA_PERF_SEL_image_write_wavefronts       = 0x00000026,
16117TA_PERF_SEL_image_atomic_wavefronts      = 0x00000027,
16118TA_PERF_SEL_image_total_cycles           = 0x00000028,
16119TA_PERF_SEL_RESERVED_41                  = 0x00000029,
16120TA_PERF_SEL_RESERVED_42                  = 0x0000002a,
16121TA_PERF_SEL_RESERVED_43                  = 0x0000002b,
16122TA_PERF_SEL_buffer_wavefronts            = 0x0000002c,
16123TA_PERF_SEL_buffer_read_wavefronts       = 0x0000002d,
16124TA_PERF_SEL_buffer_write_wavefronts      = 0x0000002e,
16125TA_PERF_SEL_buffer_atomic_wavefronts     = 0x0000002f,
16126TA_PERF_SEL_buffer_coalescable_wavefronts  = 0x00000030,
16127TA_PERF_SEL_buffer_total_cycles          = 0x00000031,
16128TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles  = 0x00000032,
16129TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles  = 0x00000033,
16130TA_PERF_SEL_buffer_coalesced_read_cycles  = 0x00000034,
16131TA_PERF_SEL_buffer_coalesced_write_cycles  = 0x00000035,
16132TA_PERF_SEL_addr_stalled_by_tc_cycles    = 0x00000036,
16133TA_PERF_SEL_addr_stalled_by_td_cycles    = 0x00000037,
16134TA_PERF_SEL_data_stalled_by_tc_cycles    = 0x00000038,
16135TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles  = 0x00000039,
16136TA_PERF_SEL_addresser_stalled_cycles     = 0x0000003a,
16137TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles  = 0x0000003b,
16138TA_PERF_SEL_aniso_stalled_cycles         = 0x0000003c,
16139TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles  = 0x0000003d,
16140TA_PERF_SEL_deriv_stalled_cycles         = 0x0000003e,
16141TA_PERF_SEL_aniso_gt1_cycle_quads        = 0x0000003f,
16142TA_PERF_SEL_color_1_cycle_pixels         = 0x00000040,
16143TA_PERF_SEL_color_2_cycle_pixels         = 0x00000041,
16144TA_PERF_SEL_color_3_cycle_pixels         = 0x00000042,
16145TA_PERF_SEL_color_4_cycle_pixels         = 0x00000043,
16146TA_PERF_SEL_mip_1_cycle_pixels           = 0x00000044,
16147TA_PERF_SEL_mip_2_cycle_pixels           = 0x00000045,
16148TA_PERF_SEL_vol_1_cycle_pixels           = 0x00000046,
16149TA_PERF_SEL_vol_2_cycle_pixels           = 0x00000047,
16150TA_PERF_SEL_bilin_point_1_cycle_pixels   = 0x00000048,
16151TA_PERF_SEL_mipmap_lod_0_samples         = 0x00000049,
16152TA_PERF_SEL_mipmap_lod_1_samples         = 0x0000004a,
16153TA_PERF_SEL_mipmap_lod_2_samples         = 0x0000004b,
16154TA_PERF_SEL_mipmap_lod_3_samples         = 0x0000004c,
16155TA_PERF_SEL_mipmap_lod_4_samples         = 0x0000004d,
16156TA_PERF_SEL_mipmap_lod_5_samples         = 0x0000004e,
16157TA_PERF_SEL_mipmap_lod_6_samples         = 0x0000004f,
16158TA_PERF_SEL_mipmap_lod_7_samples         = 0x00000050,
16159TA_PERF_SEL_mipmap_lod_8_samples         = 0x00000051,
16160TA_PERF_SEL_mipmap_lod_9_samples         = 0x00000052,
16161TA_PERF_SEL_mipmap_lod_10_samples        = 0x00000053,
16162TA_PERF_SEL_mipmap_lod_11_samples        = 0x00000054,
16163TA_PERF_SEL_mipmap_lod_12_samples        = 0x00000055,
16164TA_PERF_SEL_mipmap_lod_13_samples        = 0x00000056,
16165TA_PERF_SEL_mipmap_lod_14_samples        = 0x00000057,
16166TA_PERF_SEL_mipmap_invalid_samples       = 0x00000058,
16167TA_PERF_SEL_aniso_1_cycle_quads          = 0x00000059,
16168TA_PERF_SEL_aniso_2_cycle_quads          = 0x0000005a,
16169TA_PERF_SEL_aniso_4_cycle_quads          = 0x0000005b,
16170TA_PERF_SEL_aniso_6_cycle_quads          = 0x0000005c,
16171TA_PERF_SEL_aniso_8_cycle_quads          = 0x0000005d,
16172TA_PERF_SEL_aniso_10_cycle_quads         = 0x0000005e,
16173TA_PERF_SEL_aniso_12_cycle_quads         = 0x0000005f,
16174TA_PERF_SEL_aniso_14_cycle_quads         = 0x00000060,
16175TA_PERF_SEL_aniso_16_cycle_quads         = 0x00000061,
16176TA_PERF_SEL_write_path_input_cycles      = 0x00000062,
16177TA_PERF_SEL_write_path_output_cycles     = 0x00000063,
16178TA_PERF_SEL_flat_wavefronts              = 0x00000064,
16179TA_PERF_SEL_flat_read_wavefronts         = 0x00000065,
16180TA_PERF_SEL_flat_write_wavefronts        = 0x00000066,
16181TA_PERF_SEL_flat_atomic_wavefronts       = 0x00000067,
16182TA_PERF_SEL_flat_coalesceable_wavefronts  = 0x00000068,
16183TA_PERF_SEL_reg_sclk_vld                 = 0x00000069,
16184TA_PERF_SEL_local_cg_dyn_sclk_grp0_en    = 0x0000006a,
16185TA_PERF_SEL_local_cg_dyn_sclk_grp1_en    = 0x0000006b,
16186TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en  = 0x0000006c,
16187TA_PERF_SEL_local_cg_dyn_sclk_grp4_en    = 0x0000006d,
16188TA_PERF_SEL_local_cg_dyn_sclk_grp5_en    = 0x0000006e,
16189TA_PERF_SEL_xnack_on_phase0              = 0x0000006f,
16190TA_PERF_SEL_xnack_on_phase1              = 0x00000070,
16191TA_PERF_SEL_xnack_on_phase2              = 0x00000071,
16192TA_PERF_SEL_xnack_on_phase3              = 0x00000072,
16193TA_PERF_SEL_first_xnack_on_phase0        = 0x00000073,
16194TA_PERF_SEL_first_xnack_on_phase1        = 0x00000074,
16195TA_PERF_SEL_first_xnack_on_phase2        = 0x00000075,
16196TA_PERF_SEL_first_xnack_on_phase3        = 0x00000076,
16197} TA_PERFCOUNT_SEL;
16198
16199/*
16200 * TD_PERFCOUNT_SEL enum
16201 */
16202
16203typedef enum TD_PERFCOUNT_SEL {
16204TD_PERF_SEL_none                         = 0x00000000,
16205TD_PERF_SEL_td_busy                      = 0x00000001,
16206TD_PERF_SEL_input_busy                   = 0x00000002,
16207TD_PERF_SEL_output_busy                  = 0x00000003,
16208TD_PERF_SEL_lerp_busy                    = 0x00000004,
16209TD_PERF_SEL_reg_sclk_vld                 = 0x00000005,
16210TD_PERF_SEL_local_cg_dyn_sclk_grp0_en    = 0x00000006,
16211TD_PERF_SEL_local_cg_dyn_sclk_grp1_en    = 0x00000007,
16212TD_PERF_SEL_local_cg_dyn_sclk_grp4_en    = 0x00000008,
16213TD_PERF_SEL_local_cg_dyn_sclk_grp5_en    = 0x00000009,
16214TD_PERF_SEL_tc_td_fifo_full              = 0x0000000a,
16215TD_PERF_SEL_constant_state_full          = 0x0000000b,
16216TD_PERF_SEL_sample_state_full            = 0x0000000c,
16217TD_PERF_SEL_output_fifo_full             = 0x0000000d,
16218TD_PERF_SEL_RESERVED_14                  = 0x0000000e,
16219TD_PERF_SEL_tc_stall                     = 0x0000000f,
16220TD_PERF_SEL_pc_stall                     = 0x00000010,
16221TD_PERF_SEL_gds_stall                    = 0x00000011,
16222TD_PERF_SEL_RESERVED_18                  = 0x00000012,
16223TD_PERF_SEL_RESERVED_19                  = 0x00000013,
16224TD_PERF_SEL_gather4_wavefront            = 0x00000014,
16225TD_PERF_SEL_gather4h_wavefront           = 0x00000015,
16226TD_PERF_SEL_gather4h_packed_wavefront    = 0x00000016,
16227TD_PERF_SEL_gather8h_packed_wavefront    = 0x00000017,
16228TD_PERF_SEL_sample_c_wavefront           = 0x00000018,
16229TD_PERF_SEL_load_wavefront               = 0x00000019,
16230TD_PERF_SEL_atomic_wavefront             = 0x0000001a,
16231TD_PERF_SEL_store_wavefront              = 0x0000001b,
16232TD_PERF_SEL_ldfptr_wavefront             = 0x0000001c,
16233TD_PERF_SEL_d16_en_wavefront             = 0x0000001d,
16234TD_PERF_SEL_bypass_filter_wavefront      = 0x0000001e,
16235TD_PERF_SEL_min_max_filter_wavefront     = 0x0000001f,
16236TD_PERF_SEL_coalescable_wavefront        = 0x00000020,
16237TD_PERF_SEL_coalesced_phase              = 0x00000021,
16238TD_PERF_SEL_four_phase_wavefront         = 0x00000022,
16239TD_PERF_SEL_eight_phase_wavefront        = 0x00000023,
16240TD_PERF_SEL_sixteen_phase_wavefront      = 0x00000024,
16241TD_PERF_SEL_four_phase_forward_wavefront  = 0x00000025,
16242TD_PERF_SEL_write_ack_wavefront          = 0x00000026,
16243TD_PERF_SEL_RESERVED_39                  = 0x00000027,
16244TD_PERF_SEL_user_defined_border          = 0x00000028,
16245TD_PERF_SEL_white_border                 = 0x00000029,
16246TD_PERF_SEL_opaque_black_border          = 0x0000002a,
16247TD_PERF_SEL_RESERVED_43                  = 0x0000002b,
16248TD_PERF_SEL_RESERVED_44                  = 0x0000002c,
16249TD_PERF_SEL_nack                         = 0x0000002d,
16250TD_PERF_SEL_td_sp_traffic                = 0x0000002e,
16251TD_PERF_SEL_consume_gds_traffic          = 0x0000002f,
16252TD_PERF_SEL_addresscmd_poison            = 0x00000030,
16253TD_PERF_SEL_data_poison                  = 0x00000031,
16254TD_PERF_SEL_start_cycle_0                = 0x00000032,
16255TD_PERF_SEL_start_cycle_1                = 0x00000033,
16256TD_PERF_SEL_start_cycle_2                = 0x00000034,
16257TD_PERF_SEL_start_cycle_3                = 0x00000035,
16258TD_PERF_SEL_null_cycle_output            = 0x00000036,
16259TD_PERF_SEL_d16_data_packed              = 0x00000037,
16260TD_PERF_SEL_texels_zeroed_out_by_blend_zero_prt  = 0x00000038,
16261} TD_PERFCOUNT_SEL;
16262
16263/*
16264 * TCP_PERFCOUNT_SELECT enum
16265 */
16266
16267typedef enum TCP_PERFCOUNT_SELECT {
16268TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES   = 0x00000000,
16269TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES   = 0x00000001,
16270TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES    = 0x00000002,
16271TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES    = 0x00000003,
16272TCP_PERF_SEL_TD_TCP_STALL_CYCLES         = 0x00000004,
16273TCP_PERF_SEL_TCR_TCP_STALL_CYCLES        = 0x00000005,
16274TCP_PERF_SEL_LOD_STALL_CYCLES            = 0x00000006,
16275TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES  = 0x00000007,
16276TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES  = 0x00000008,
16277TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES  = 0x00000009,
16278TCP_PERF_SEL_ALLOC_STALL_CYCLES          = 0x0000000a,
16279TCP_PERF_SEL_LFIFO_STALL_CYCLES          = 0x0000000b,
16280TCP_PERF_SEL_RFIFO_STALL_CYCLES          = 0x0000000c,
16281TCP_PERF_SEL_TCR_RDRET_STALL             = 0x0000000d,
16282TCP_PERF_SEL_WRITE_CONFLICT_STALL        = 0x0000000e,
16283TCP_PERF_SEL_HOLE_READ_STALL             = 0x0000000f,
16284TCP_PERF_SEL_READCONFLICT_STALL_CYCLES   = 0x00000010,
16285TCP_PERF_SEL_PENDING_STALL_CYCLES        = 0x00000011,
16286TCP_PERF_SEL_READFIFO_STALL_CYCLES       = 0x00000012,
16287TCP_PERF_SEL_TCP_LATENCY                 = 0x00000013,
16288TCP_PERF_SEL_TCC_READ_REQ_LATENCY        = 0x00000014,
16289TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY       = 0x00000015,
16290TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY  = 0x00000016,
16291TCP_PERF_SEL_TCC_READ_REQ                = 0x00000017,
16292TCP_PERF_SEL_TCC_WRITE_REQ               = 0x00000018,
16293TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ     = 0x00000019,
16294TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ  = 0x0000001a,
16295TCP_PERF_SEL_TOTAL_LOCAL_READ            = 0x0000001b,
16296TCP_PERF_SEL_TOTAL_GLOBAL_READ           = 0x0000001c,
16297TCP_PERF_SEL_TOTAL_LOCAL_WRITE           = 0x0000001d,
16298TCP_PERF_SEL_TOTAL_GLOBAL_WRITE          = 0x0000001e,
16299TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET       = 0x0000001f,
16300TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET    = 0x00000020,
16301TCP_PERF_SEL_TOTAL_WBINVL1               = 0x00000021,
16302TCP_PERF_SEL_IMG_READ_FMT_1              = 0x00000022,
16303TCP_PERF_SEL_IMG_READ_FMT_8              = 0x00000023,
16304TCP_PERF_SEL_IMG_READ_FMT_16             = 0x00000024,
16305TCP_PERF_SEL_IMG_READ_FMT_32             = 0x00000025,
16306TCP_PERF_SEL_IMG_READ_FMT_32_AS_8        = 0x00000026,
16307TCP_PERF_SEL_IMG_READ_FMT_32_AS_16       = 0x00000027,
16308TCP_PERF_SEL_IMG_READ_FMT_32_AS_128      = 0x00000028,
16309TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE     = 0x00000029,
16310TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE     = 0x0000002a,
16311TCP_PERF_SEL_IMG_READ_FMT_96             = 0x0000002b,
16312TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE    = 0x0000002c,
16313TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE    = 0x0000002d,
16314TCP_PERF_SEL_IMG_READ_FMT_BC1            = 0x0000002e,
16315TCP_PERF_SEL_IMG_READ_FMT_BC2            = 0x0000002f,
16316TCP_PERF_SEL_IMG_READ_FMT_BC3            = 0x00000030,
16317TCP_PERF_SEL_IMG_READ_FMT_BC4            = 0x00000031,
16318TCP_PERF_SEL_IMG_READ_FMT_BC5            = 0x00000032,
16319TCP_PERF_SEL_IMG_READ_FMT_BC6            = 0x00000033,
16320TCP_PERF_SEL_IMG_READ_FMT_BC7            = 0x00000034,
16321TCP_PERF_SEL_IMG_READ_FMT_I8             = 0x00000035,
16322TCP_PERF_SEL_IMG_READ_FMT_I16            = 0x00000036,
16323TCP_PERF_SEL_IMG_READ_FMT_I32            = 0x00000037,
16324TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8       = 0x00000038,
16325TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16      = 0x00000039,
16326TCP_PERF_SEL_IMG_READ_FMT_D8             = 0x0000003a,
16327TCP_PERF_SEL_IMG_READ_FMT_D16            = 0x0000003b,
16328TCP_PERF_SEL_IMG_READ_FMT_D32            = 0x0000003c,
16329TCP_PERF_SEL_IMG_WRITE_FMT_8             = 0x0000003d,
16330TCP_PERF_SEL_IMG_WRITE_FMT_16            = 0x0000003e,
16331TCP_PERF_SEL_IMG_WRITE_FMT_32            = 0x0000003f,
16332TCP_PERF_SEL_IMG_WRITE_FMT_64            = 0x00000040,
16333TCP_PERF_SEL_IMG_WRITE_FMT_128           = 0x00000041,
16334TCP_PERF_SEL_IMG_WRITE_FMT_D8            = 0x00000042,
16335TCP_PERF_SEL_IMG_WRITE_FMT_D16           = 0x00000043,
16336TCP_PERF_SEL_IMG_WRITE_FMT_D32           = 0x00000044,
16337TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32  = 0x00000045,
16338TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32  = 0x00000046,
16339TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64  = 0x00000047,
16340TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64  = 0x00000048,
16341TCP_PERF_SEL_BUF_READ_FMT_8              = 0x00000049,
16342TCP_PERF_SEL_BUF_READ_FMT_16             = 0x0000004a,
16343TCP_PERF_SEL_BUF_READ_FMT_32             = 0x0000004b,
16344TCP_PERF_SEL_BUF_WRITE_FMT_8             = 0x0000004c,
16345TCP_PERF_SEL_BUF_WRITE_FMT_16            = 0x0000004d,
16346TCP_PERF_SEL_BUF_WRITE_FMT_32            = 0x0000004e,
16347TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32  = 0x0000004f,
16348TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32  = 0x00000050,
16349TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64  = 0x00000051,
16350TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64  = 0x00000052,
16351TCP_PERF_SEL_ARR_LINEAR_GENERAL          = 0x00000053,
16352TCP_PERF_SEL_ARR_LINEAR_ALIGNED          = 0x00000054,
16353TCP_PERF_SEL_ARR_1D_THIN1                = 0x00000055,
16354TCP_PERF_SEL_ARR_1D_THICK                = 0x00000056,
16355TCP_PERF_SEL_ARR_2D_THIN1                = 0x00000057,
16356TCP_PERF_SEL_ARR_2D_THICK                = 0x00000058,
16357TCP_PERF_SEL_ARR_2D_XTHICK               = 0x00000059,
16358TCP_PERF_SEL_ARR_3D_THIN1                = 0x0000005a,
16359TCP_PERF_SEL_ARR_3D_THICK                = 0x0000005b,
16360TCP_PERF_SEL_ARR_3D_XTHICK               = 0x0000005c,
16361TCP_PERF_SEL_DIM_1D                      = 0x0000005d,
16362TCP_PERF_SEL_DIM_2D                      = 0x0000005e,
16363TCP_PERF_SEL_DIM_3D                      = 0x0000005f,
16364TCP_PERF_SEL_DIM_1D_ARRAY                = 0x00000060,
16365TCP_PERF_SEL_DIM_2D_ARRAY                = 0x00000061,
16366TCP_PERF_SEL_DIM_2D_MSAA                 = 0x00000062,
16367TCP_PERF_SEL_DIM_2D_ARRAY_MSAA           = 0x00000063,
16368TCP_PERF_SEL_DIM_CUBE_ARRAY              = 0x00000064,
16369TCP_PERF_SEL_CP_TCP_INVALIDATE           = 0x00000065,
16370TCP_PERF_SEL_TA_TCP_STATE_READ           = 0x00000066,
16371TCP_PERF_SEL_TAGRAM0_REQ                 = 0x00000067,
16372TCP_PERF_SEL_TAGRAM1_REQ                 = 0x00000068,
16373TCP_PERF_SEL_TAGRAM2_REQ                 = 0x00000069,
16374TCP_PERF_SEL_TAGRAM3_REQ                 = 0x0000006a,
16375TCP_PERF_SEL_GATE_EN1                    = 0x0000006b,
16376TCP_PERF_SEL_GATE_EN2                    = 0x0000006c,
16377TCP_PERF_SEL_CORE_REG_SCLK_VLD           = 0x0000006d,
16378TCP_PERF_SEL_TCC_REQ                     = 0x0000006e,
16379TCP_PERF_SEL_TCC_NON_READ_REQ            = 0x0000006f,
16380TCP_PERF_SEL_TCC_BYPASS_READ_REQ         = 0x00000070,
16381TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ     = 0x00000071,
16382TCP_PERF_SEL_TCC_VOLATILE_READ_REQ       = 0x00000072,
16383TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ  = 0x00000073,
16384TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ  = 0x00000074,
16385TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ        = 0x00000075,
16386TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ    = 0x00000076,
16387TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ  = 0x00000077,
16388TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ      = 0x00000078,
16389TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ  = 0x00000079,
16390TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ       = 0x0000007a,
16391TCP_PERF_SEL_TCC_ATOMIC_REQ              = 0x0000007b,
16392TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ     = 0x0000007c,
16393TCP_PERF_SEL_TCC_DATA_BUS_BUSY           = 0x0000007d,
16394TCP_PERF_SEL_TOTAL_ACCESSES              = 0x0000007e,
16395TCP_PERF_SEL_TOTAL_READ                  = 0x0000007f,
16396TCP_PERF_SEL_TOTAL_HIT_LRU_READ          = 0x00000080,
16397TCP_PERF_SEL_TOTAL_HIT_EVICT_READ        = 0x00000081,
16398TCP_PERF_SEL_TOTAL_MISS_LRU_READ         = 0x00000082,
16399TCP_PERF_SEL_TOTAL_MISS_EVICT_READ       = 0x00000083,
16400TCP_PERF_SEL_TOTAL_NON_READ              = 0x00000084,
16401TCP_PERF_SEL_TOTAL_WRITE                 = 0x00000085,
16402TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE        = 0x00000086,
16403TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE      = 0x00000087,
16404TCP_PERF_SEL_TOTAL_WBINVL1_VOL           = 0x00000088,
16405TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES  = 0x00000089,
16406TCP_PERF_SEL_DISPLAY_MICROTILING         = 0x0000008a,
16407TCP_PERF_SEL_THIN_MICROTILING            = 0x0000008b,
16408TCP_PERF_SEL_DEPTH_MICROTILING           = 0x0000008c,
16409TCP_PERF_SEL_ARR_PRT_THIN1               = 0x0000008d,
16410TCP_PERF_SEL_ARR_PRT_2D_THIN1            = 0x0000008e,
16411TCP_PERF_SEL_ARR_PRT_3D_THIN1            = 0x0000008f,
16412TCP_PERF_SEL_ARR_PRT_THICK               = 0x00000090,
16413TCP_PERF_SEL_ARR_PRT_2D_THICK            = 0x00000091,
16414TCP_PERF_SEL_ARR_PRT_3D_THICK            = 0x00000092,
16415TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL       = 0x00000093,
16416TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL       = 0x00000094,
16417TCP_PERF_SEL_UNALIGNED                   = 0x00000095,
16418TCP_PERF_SEL_ROTATED_MICROTILING         = 0x00000096,
16419TCP_PERF_SEL_THICK_MICROTILING           = 0x00000097,
16420TCP_PERF_SEL_ATC                         = 0x00000098,
16421TCP_PERF_SEL_POWER_STALL                 = 0x00000099,
16422TCP_PERF_SEL_RESERVED_154                = 0x0000009a,
16423TCP_PERF_SEL_TCC_LRU_REQ                 = 0x0000009b,
16424TCP_PERF_SEL_TCC_STREAM_REQ              = 0x0000009c,
16425TCP_PERF_SEL_TCC_NC_READ_REQ             = 0x0000009d,
16426TCP_PERF_SEL_TCC_NC_WRITE_REQ            = 0x0000009e,
16427TCP_PERF_SEL_TCC_NC_ATOMIC_REQ           = 0x0000009f,
16428TCP_PERF_SEL_TCC_UC_READ_REQ             = 0x000000a0,
16429TCP_PERF_SEL_TCC_UC_WRITE_REQ            = 0x000000a1,
16430TCP_PERF_SEL_TCC_UC_ATOMIC_REQ           = 0x000000a2,
16431TCP_PERF_SEL_TCC_CC_READ_REQ             = 0x000000a3,
16432TCP_PERF_SEL_TCC_CC_WRITE_REQ            = 0x000000a4,
16433TCP_PERF_SEL_TCC_CC_ATOMIC_REQ           = 0x000000a5,
16434TCP_PERF_SEL_TCC_DCC_REQ                 = 0x000000a6,
16435TCP_PERF_SEL_TCC_PHYSICAL_REQ            = 0x000000a7,
16436TCP_PERF_SEL_UNORDERED_MTYPE_STALL       = 0x000000a8,
16437TCP_PERF_SEL_VOLATILE                    = 0x000000a9,
16438TCP_PERF_SEL_TC_TA_XNACK_STALL           = 0x000000aa,
16439TCP_PERF_SEL_UTCL1_SERIALIZATION_STALL   = 0x000000ab,
16440TCP_PERF_SEL_SHOOTDOWN                   = 0x000000ac,
16441TCP_PERF_SEL_UTCL1_TRANSLATION_MISS      = 0x000000ad,
16442TCP_PERF_SEL_UTCL1_PERMISSION_MISS       = 0x000000ae,
16443TCP_PERF_SEL_UTCL1_REQUEST               = 0x000000af,
16444TCP_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX    = 0x000000b0,
16445TCP_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT    = 0x000000b1,
16446TCP_PERF_SEL_UTCL1_LFIFO_FULL            = 0x000000b2,
16447TCP_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES   = 0x000000b3,
16448TCP_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS  = 0x000000b4,
16449TCP_PERF_SEL_UTCL1_UTCL2_INFLIGHT        = 0x000000b5,
16450TCP_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL   = 0x000000b6,
16451TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGB       = 0x000000b7,
16452TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA      = 0x000000b8,
16453TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA1     = 0x000000b9,
16454TCP_PERF_SEL_IMG_READ_FMT_ETC2_R         = 0x000000ba,
16455TCP_PERF_SEL_IMG_READ_FMT_ETC2_RG        = 0x000000bb,
16456TCP_PERF_SEL_IMG_READ_FMT_8_AS_32        = 0x000000bc,
16457TCP_PERF_SEL_IMG_READ_FMT_8_AS_64        = 0x000000bd,
16458TCP_PERF_SEL_IMG_READ_FMT_16_AS_64       = 0x000000be,
16459TCP_PERF_SEL_IMG_READ_FMT_16_AS_128      = 0x000000bf,
16460TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_32       = 0x000000c0,
16461TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_64       = 0x000000c1,
16462TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_64      = 0x000000c2,
16463TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_128     = 0x000000c3,
16464} TCP_PERFCOUNT_SELECT;
16465
16466/*
16467 * TCP_CACHE_POLICIES enum
16468 */
16469
16470typedef enum TCP_CACHE_POLICIES {
16471TCP_CACHE_POLICY_MISS_LRU                = 0x00000000,
16472TCP_CACHE_POLICY_MISS_EVICT              = 0x00000001,
16473TCP_CACHE_POLICY_HIT_LRU                 = 0x00000002,
16474TCP_CACHE_POLICY_HIT_EVICT               = 0x00000003,
16475} TCP_CACHE_POLICIES;
16476
16477/*
16478 * TCP_CACHE_STORE_POLICIES enum
16479 */
16480
16481typedef enum TCP_CACHE_STORE_POLICIES {
16482TCP_CACHE_STORE_POLICY_WT_LRU            = 0x00000000,
16483TCP_CACHE_STORE_POLICY_WT_EVICT          = 0x00000001,
16484} TCP_CACHE_STORE_POLICIES;
16485
16486/*
16487 * TCP_WATCH_MODES enum
16488 */
16489
16490typedef enum TCP_WATCH_MODES {
16491TCP_WATCH_MODE_READ                      = 0x00000000,
16492TCP_WATCH_MODE_NONREAD                   = 0x00000001,
16493TCP_WATCH_MODE_ATOMIC                    = 0x00000002,
16494TCP_WATCH_MODE_ALL                       = 0x00000003,
16495} TCP_WATCH_MODES;
16496
16497/*
16498 * TCP_DSM_DATA_SEL enum
16499 */
16500
16501typedef enum TCP_DSM_DATA_SEL {
16502TCP_DSM_DISABLE                          = 0x00000000,
16503TCP_DSM_SEL0                             = 0x00000001,
16504TCP_DSM_SEL1                             = 0x00000002,
16505TCP_DSM_SEL_BOTH                         = 0x00000003,
16506} TCP_DSM_DATA_SEL;
16507
16508/*
16509 * TCP_DSM_SINGLE_WRITE enum
16510 */
16511
16512typedef enum TCP_DSM_SINGLE_WRITE {
16513TCP_DSM_SINGLE_WRITE_DIS                 = 0x00000000,
16514TCP_DSM_SINGLE_WRITE_EN                  = 0x00000001,
16515} TCP_DSM_SINGLE_WRITE;
16516
16517/*
16518 * TCP_DSM_INJECT_SEL enum
16519 */
16520
16521typedef enum TCP_DSM_INJECT_SEL {
16522TCP_DSM_INJECT_SEL0                      = 0x00000000,
16523TCP_DSM_INJECT_SEL1                      = 0x00000001,
16524TCP_DSM_INJECT_SEL2                      = 0x00000002,
16525TCP_DSM_INJECT_SEL3                      = 0x00000003,
16526} TCP_DSM_INJECT_SEL;
16527
16528/*******************************************************
16529 * TCC Enums
16530 *******************************************************/
16531
16532/*
16533 * TCC_PERF_SEL enum
16534 */
16535
16536typedef enum TCC_PERF_SEL {
16537TCC_PERF_SEL_NONE                        = 0x00000000,
16538TCC_PERF_SEL_CYCLE                       = 0x00000001,
16539TCC_PERF_SEL_BUSY                        = 0x00000002,
16540TCC_PERF_SEL_REQ                         = 0x00000003,
16541TCC_PERF_SEL_STREAMING_REQ               = 0x00000004,
16542TCC_PERF_SEL_EXE_REQ                     = 0x00000005,
16543TCC_PERF_SEL_COMPRESSED_REQ              = 0x00000006,
16544TCC_PERF_SEL_COMPRESSED_0_REQ            = 0x00000007,
16545TCC_PERF_SEL_METADATA_REQ                = 0x00000008,
16546TCC_PERF_SEL_NC_VIRTUAL_REQ              = 0x00000009,
16547TCC_PERF_SEL_UC_VIRTUAL_REQ              = 0x0000000a,
16548TCC_PERF_SEL_CC_PHYSICAL_REQ             = 0x0000000b,
16549TCC_PERF_SEL_PROBE                       = 0x0000000c,
16550TCC_PERF_SEL_PROBE_ALL                   = 0x0000000d,
16551TCC_PERF_SEL_READ                        = 0x0000000e,
16552TCC_PERF_SEL_WRITE                       = 0x0000000f,
16553TCC_PERF_SEL_ATOMIC                      = 0x00000010,
16554TCC_PERF_SEL_HIT                         = 0x00000011,
16555TCC_PERF_SEL_SECTOR_HIT                  = 0x00000012,
16556TCC_PERF_SEL_MISS                        = 0x00000013,
16557TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT        = 0x00000014,
16558TCC_PERF_SEL_FULLY_WRITTEN_HIT           = 0x00000015,
16559TCC_PERF_SEL_WRITEBACK                   = 0x00000016,
16560TCC_PERF_SEL_LATENCY_FIFO_FULL           = 0x00000017,
16561TCC_PERF_SEL_SRC_FIFO_FULL               = 0x00000018,
16562TCC_PERF_SEL_HOLE_FIFO_FULL              = 0x00000019,
16563TCC_PERF_SEL_EA_WRREQ                    = 0x0000001a,
16564TCC_PERF_SEL_EA_WRREQ_64B                = 0x0000001b,
16565TCC_PERF_SEL_EA_WRREQ_PROBE_COMMAND      = 0x0000001c,
16566TCC_PERF_SEL_EA_WR_UNCACHED_32B          = 0x0000001d,
16567TCC_PERF_SEL_EA_WRREQ_STALL              = 0x0000001e,
16568TCC_PERF_SEL_EA_WRREQ_CREDIT_STALL       = 0x0000001f,
16569TCC_PERF_SEL_TOO_MANY_EA_WRREQS_STALL    = 0x00000020,
16570TCC_PERF_SEL_EA_WRREQ_LEVEL              = 0x00000021,
16571TCC_PERF_SEL_EA_ATOMIC                   = 0x00000022,
16572TCC_PERF_SEL_EA_ATOMIC_LEVEL             = 0x00000023,
16573TCC_PERF_SEL_EA_RDREQ                    = 0x00000024,
16574TCC_PERF_SEL_EA_RDREQ_32B                = 0x00000025,
16575TCC_PERF_SEL_EA_RD_UNCACHED_32B          = 0x00000026,
16576TCC_PERF_SEL_EA_RD_MDC_32B               = 0x00000027,
16577TCC_PERF_SEL_EA_RD_COMPRESSED_32B        = 0x00000028,
16578TCC_PERF_SEL_EA_RDREQ_CREDIT_STALL       = 0x00000029,
16579TCC_PERF_SEL_EA_RDREQ_LEVEL              = 0x0000002a,
16580TCC_PERF_SEL_TAG_STALL                   = 0x0000002b,
16581TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL  = 0x0000002c,
16582TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL  = 0x0000002d,
16583TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL  = 0x0000002e,
16584TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL  = 0x0000002f,
16585TCC_PERF_SEL_TAG_PROBE_STALL             = 0x00000030,
16586TCC_PERF_SEL_TAG_PROBE_FILTER_STALL      = 0x00000031,
16587TCC_PERF_SEL_READ_RETURN_TIMEOUT         = 0x00000032,
16588TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT      = 0x00000033,
16589TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE     = 0x00000034,
16590TCC_PERF_SEL_BUBBLE                      = 0x00000035,
16591TCC_PERF_SEL_RETURN_ACK                  = 0x00000036,
16592TCC_PERF_SEL_RETURN_DATA                 = 0x00000037,
16593TCC_PERF_SEL_RETURN_HOLE                 = 0x00000038,
16594TCC_PERF_SEL_RETURN_ACK_HOLE             = 0x00000039,
16595TCC_PERF_SEL_IB_REQ                      = 0x0000003a,
16596TCC_PERF_SEL_IB_STALL                    = 0x0000003b,
16597TCC_PERF_SEL_IB_TAG_STALL                = 0x0000003c,
16598TCC_PERF_SEL_IB_MDC_STALL                = 0x0000003d,
16599TCC_PERF_SEL_TCA_LEVEL                   = 0x0000003e,
16600TCC_PERF_SEL_HOLE_LEVEL                  = 0x0000003f,
16601TCC_PERF_SEL_NORMAL_WRITEBACK            = 0x00000040,
16602TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK     = 0x00000041,
16603TCC_PERF_SEL_TC_OP_WBL2_WC_WRITEBACK     = 0x00000042,
16604TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK     = 0x00000043,
16605TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK  = 0x00000044,
16606TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK  = 0x00000045,
16607TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK      = 0x00000046,
16608TCC_PERF_SEL_NORMAL_EVICT                = 0x00000047,
16609TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT         = 0x00000048,
16610TCC_PERF_SEL_TC_OP_WBL2_WC_EVICT         = 0x00000049,
16611TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT        = 0x0000004a,
16612TCC_PERF_SEL_TC_OP_WBINVL2_EVICT         = 0x0000004b,
16613TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT      = 0x0000004c,
16614TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT      = 0x0000004d,
16615TCC_PERF_SEL_ALL_TC_OP_INV_EVICT         = 0x0000004e,
16616TCC_PERF_SEL_PROBE_EVICT                 = 0x0000004f,
16617TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE         = 0x00000050,
16618TCC_PERF_SEL_TC_OP_WBL2_WC_CYCLE         = 0x00000051,
16619TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE        = 0x00000052,
16620TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE         = 0x00000053,
16621TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE      = 0x00000054,
16622TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE      = 0x00000055,
16623TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE   = 0x00000056,
16624TCC_PERF_SEL_TC_OP_WBL2_NC_START         = 0x00000057,
16625TCC_PERF_SEL_TC_OP_WBL2_WC_START         = 0x00000058,
16626TCC_PERF_SEL_TC_OP_INVL2_NC_START        = 0x00000059,
16627TCC_PERF_SEL_TC_OP_WBINVL2_START         = 0x0000005a,
16628TCC_PERF_SEL_TC_OP_WBINVL2_NC_START      = 0x0000005b,
16629TCC_PERF_SEL_TC_OP_WBINVL2_SD_START      = 0x0000005c,
16630TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START   = 0x0000005d,
16631TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH        = 0x0000005e,
16632TCC_PERF_SEL_TC_OP_WBL2_WC_FINISH        = 0x0000005f,
16633TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH       = 0x00000060,
16634TCC_PERF_SEL_TC_OP_WBINVL2_FINISH        = 0x00000061,
16635TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH     = 0x00000062,
16636TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH     = 0x00000063,
16637TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH  = 0x00000064,
16638TCC_PERF_SEL_MDC_REQ                     = 0x00000065,
16639TCC_PERF_SEL_MDC_LEVEL                   = 0x00000066,
16640TCC_PERF_SEL_MDC_TAG_HIT                 = 0x00000067,
16641TCC_PERF_SEL_MDC_SECTOR_HIT              = 0x00000068,
16642TCC_PERF_SEL_MDC_SECTOR_MISS             = 0x00000069,
16643TCC_PERF_SEL_MDC_TAG_STALL               = 0x0000006a,
16644TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL  = 0x0000006b,
16645TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL  = 0x0000006c,
16646TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL  = 0x0000006d,
16647TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION  = 0x0000006e,
16648TCC_PERF_SEL_PROBE_FILTER_DISABLED       = 0x0000006f,
16649TCC_PERF_SEL_CLIENT0_REQ                 = 0x00000080,
16650TCC_PERF_SEL_CLIENT1_REQ                 = 0x00000081,
16651TCC_PERF_SEL_CLIENT2_REQ                 = 0x00000082,
16652TCC_PERF_SEL_CLIENT3_REQ                 = 0x00000083,
16653TCC_PERF_SEL_CLIENT4_REQ                 = 0x00000084,
16654TCC_PERF_SEL_CLIENT5_REQ                 = 0x00000085,
16655TCC_PERF_SEL_CLIENT6_REQ                 = 0x00000086,
16656TCC_PERF_SEL_CLIENT7_REQ                 = 0x00000087,
16657TCC_PERF_SEL_CLIENT8_REQ                 = 0x00000088,
16658TCC_PERF_SEL_CLIENT9_REQ                 = 0x00000089,
16659TCC_PERF_SEL_CLIENT10_REQ                = 0x0000008a,
16660TCC_PERF_SEL_CLIENT11_REQ                = 0x0000008b,
16661TCC_PERF_SEL_CLIENT12_REQ                = 0x0000008c,
16662TCC_PERF_SEL_CLIENT13_REQ                = 0x0000008d,
16663TCC_PERF_SEL_CLIENT14_REQ                = 0x0000008e,
16664TCC_PERF_SEL_CLIENT15_REQ                = 0x0000008f,
16665TCC_PERF_SEL_CLIENT16_REQ                = 0x00000090,
16666TCC_PERF_SEL_CLIENT17_REQ                = 0x00000091,
16667TCC_PERF_SEL_CLIENT18_REQ                = 0x00000092,
16668TCC_PERF_SEL_CLIENT19_REQ                = 0x00000093,
16669TCC_PERF_SEL_CLIENT20_REQ                = 0x00000094,
16670TCC_PERF_SEL_CLIENT21_REQ                = 0x00000095,
16671TCC_PERF_SEL_CLIENT22_REQ                = 0x00000096,
16672TCC_PERF_SEL_CLIENT23_REQ                = 0x00000097,
16673TCC_PERF_SEL_CLIENT24_REQ                = 0x00000098,
16674TCC_PERF_SEL_CLIENT25_REQ                = 0x00000099,
16675TCC_PERF_SEL_CLIENT26_REQ                = 0x0000009a,
16676TCC_PERF_SEL_CLIENT27_REQ                = 0x0000009b,
16677TCC_PERF_SEL_CLIENT28_REQ                = 0x0000009c,
16678TCC_PERF_SEL_CLIENT29_REQ                = 0x0000009d,
16679TCC_PERF_SEL_CLIENT30_REQ                = 0x0000009e,
16680TCC_PERF_SEL_CLIENT31_REQ                = 0x0000009f,
16681TCC_PERF_SEL_CLIENT32_REQ                = 0x000000a0,
16682TCC_PERF_SEL_CLIENT33_REQ                = 0x000000a1,
16683TCC_PERF_SEL_CLIENT34_REQ                = 0x000000a2,
16684TCC_PERF_SEL_CLIENT35_REQ                = 0x000000a3,
16685TCC_PERF_SEL_CLIENT36_REQ                = 0x000000a4,
16686TCC_PERF_SEL_CLIENT37_REQ                = 0x000000a5,
16687TCC_PERF_SEL_CLIENT38_REQ                = 0x000000a6,
16688TCC_PERF_SEL_CLIENT39_REQ                = 0x000000a7,
16689TCC_PERF_SEL_CLIENT40_REQ                = 0x000000a8,
16690TCC_PERF_SEL_CLIENT41_REQ                = 0x000000a9,
16691TCC_PERF_SEL_CLIENT42_REQ                = 0x000000aa,
16692TCC_PERF_SEL_CLIENT43_REQ                = 0x000000ab,
16693TCC_PERF_SEL_CLIENT44_REQ                = 0x000000ac,
16694TCC_PERF_SEL_CLIENT45_REQ                = 0x000000ad,
16695TCC_PERF_SEL_CLIENT46_REQ                = 0x000000ae,
16696TCC_PERF_SEL_CLIENT47_REQ                = 0x000000af,
16697TCC_PERF_SEL_CLIENT48_REQ                = 0x000000b0,
16698TCC_PERF_SEL_CLIENT49_REQ                = 0x000000b1,
16699TCC_PERF_SEL_CLIENT50_REQ                = 0x000000b2,
16700TCC_PERF_SEL_CLIENT51_REQ                = 0x000000b3,
16701TCC_PERF_SEL_CLIENT52_REQ                = 0x000000b4,
16702TCC_PERF_SEL_CLIENT53_REQ                = 0x000000b5,
16703TCC_PERF_SEL_CLIENT54_REQ                = 0x000000b6,
16704TCC_PERF_SEL_CLIENT55_REQ                = 0x000000b7,
16705TCC_PERF_SEL_CLIENT56_REQ                = 0x000000b8,
16706TCC_PERF_SEL_CLIENT57_REQ                = 0x000000b9,
16707TCC_PERF_SEL_CLIENT58_REQ                = 0x000000ba,
16708TCC_PERF_SEL_CLIENT59_REQ                = 0x000000bb,
16709TCC_PERF_SEL_CLIENT60_REQ                = 0x000000bc,
16710TCC_PERF_SEL_CLIENT61_REQ                = 0x000000bd,
16711TCC_PERF_SEL_CLIENT62_REQ                = 0x000000be,
16712TCC_PERF_SEL_CLIENT63_REQ                = 0x000000bf,
16713TCC_PERF_SEL_CLIENT64_REQ                = 0x000000c0,
16714TCC_PERF_SEL_CLIENT65_REQ                = 0x000000c1,
16715TCC_PERF_SEL_CLIENT66_REQ                = 0x000000c2,
16716TCC_PERF_SEL_CLIENT67_REQ                = 0x000000c3,
16717TCC_PERF_SEL_CLIENT68_REQ                = 0x000000c4,
16718TCC_PERF_SEL_CLIENT69_REQ                = 0x000000c5,
16719TCC_PERF_SEL_CLIENT70_REQ                = 0x000000c6,
16720TCC_PERF_SEL_CLIENT71_REQ                = 0x000000c7,
16721TCC_PERF_SEL_CLIENT72_REQ                = 0x000000c8,
16722TCC_PERF_SEL_CLIENT73_REQ                = 0x000000c9,
16723TCC_PERF_SEL_CLIENT74_REQ                = 0x000000ca,
16724TCC_PERF_SEL_CLIENT75_REQ                = 0x000000cb,
16725TCC_PERF_SEL_CLIENT76_REQ                = 0x000000cc,
16726TCC_PERF_SEL_CLIENT77_REQ                = 0x000000cd,
16727TCC_PERF_SEL_CLIENT78_REQ                = 0x000000ce,
16728TCC_PERF_SEL_CLIENT79_REQ                = 0x000000cf,
16729TCC_PERF_SEL_CLIENT80_REQ                = 0x000000d0,
16730TCC_PERF_SEL_CLIENT81_REQ                = 0x000000d1,
16731TCC_PERF_SEL_CLIENT82_REQ                = 0x000000d2,
16732TCC_PERF_SEL_CLIENT83_REQ                = 0x000000d3,
16733TCC_PERF_SEL_CLIENT84_REQ                = 0x000000d4,
16734TCC_PERF_SEL_CLIENT85_REQ                = 0x000000d5,
16735TCC_PERF_SEL_CLIENT86_REQ                = 0x000000d6,
16736TCC_PERF_SEL_CLIENT87_REQ                = 0x000000d7,
16737TCC_PERF_SEL_CLIENT88_REQ                = 0x000000d8,
16738TCC_PERF_SEL_CLIENT89_REQ                = 0x000000d9,
16739TCC_PERF_SEL_CLIENT90_REQ                = 0x000000da,
16740TCC_PERF_SEL_CLIENT91_REQ                = 0x000000db,
16741TCC_PERF_SEL_CLIENT92_REQ                = 0x000000dc,
16742TCC_PERF_SEL_CLIENT93_REQ                = 0x000000dd,
16743TCC_PERF_SEL_CLIENT94_REQ                = 0x000000de,
16744TCC_PERF_SEL_CLIENT95_REQ                = 0x000000df,
16745TCC_PERF_SEL_CLIENT96_REQ                = 0x000000e0,
16746TCC_PERF_SEL_CLIENT97_REQ                = 0x000000e1,
16747TCC_PERF_SEL_CLIENT98_REQ                = 0x000000e2,
16748TCC_PERF_SEL_CLIENT99_REQ                = 0x000000e3,
16749TCC_PERF_SEL_CLIENT100_REQ               = 0x000000e4,
16750TCC_PERF_SEL_CLIENT101_REQ               = 0x000000e5,
16751TCC_PERF_SEL_CLIENT102_REQ               = 0x000000e6,
16752TCC_PERF_SEL_CLIENT103_REQ               = 0x000000e7,
16753TCC_PERF_SEL_CLIENT104_REQ               = 0x000000e8,
16754TCC_PERF_SEL_CLIENT105_REQ               = 0x000000e9,
16755TCC_PERF_SEL_CLIENT106_REQ               = 0x000000ea,
16756TCC_PERF_SEL_CLIENT107_REQ               = 0x000000eb,
16757TCC_PERF_SEL_CLIENT108_REQ               = 0x000000ec,
16758TCC_PERF_SEL_CLIENT109_REQ               = 0x000000ed,
16759TCC_PERF_SEL_CLIENT110_REQ               = 0x000000ee,
16760TCC_PERF_SEL_CLIENT111_REQ               = 0x000000ef,
16761TCC_PERF_SEL_CLIENT112_REQ               = 0x000000f0,
16762TCC_PERF_SEL_CLIENT113_REQ               = 0x000000f1,
16763TCC_PERF_SEL_CLIENT114_REQ               = 0x000000f2,
16764TCC_PERF_SEL_CLIENT115_REQ               = 0x000000f3,
16765TCC_PERF_SEL_CLIENT116_REQ               = 0x000000f4,
16766TCC_PERF_SEL_CLIENT117_REQ               = 0x000000f5,
16767TCC_PERF_SEL_CLIENT118_REQ               = 0x000000f6,
16768TCC_PERF_SEL_CLIENT119_REQ               = 0x000000f7,
16769TCC_PERF_SEL_CLIENT120_REQ               = 0x000000f8,
16770TCC_PERF_SEL_CLIENT121_REQ               = 0x000000f9,
16771TCC_PERF_SEL_CLIENT122_REQ               = 0x000000fa,
16772TCC_PERF_SEL_CLIENT123_REQ               = 0x000000fb,
16773TCC_PERF_SEL_CLIENT124_REQ               = 0x000000fc,
16774TCC_PERF_SEL_CLIENT125_REQ               = 0x000000fd,
16775TCC_PERF_SEL_CLIENT126_REQ               = 0x000000fe,
16776TCC_PERF_SEL_CLIENT127_REQ               = 0x000000ff,
16777} TCC_PERF_SEL;
16778
16779/*
16780 * TCA_PERF_SEL enum
16781 */
16782
16783typedef enum TCA_PERF_SEL {
16784TCA_PERF_SEL_NONE                        = 0x00000000,
16785TCA_PERF_SEL_CYCLE                       = 0x00000001,
16786TCA_PERF_SEL_BUSY                        = 0x00000002,
16787TCA_PERF_SEL_FORCED_HOLE_TCC0            = 0x00000003,
16788TCA_PERF_SEL_FORCED_HOLE_TCC1            = 0x00000004,
16789TCA_PERF_SEL_FORCED_HOLE_TCC2            = 0x00000005,
16790TCA_PERF_SEL_FORCED_HOLE_TCC3            = 0x00000006,
16791TCA_PERF_SEL_FORCED_HOLE_TCC4            = 0x00000007,
16792TCA_PERF_SEL_FORCED_HOLE_TCC5            = 0x00000008,
16793TCA_PERF_SEL_FORCED_HOLE_TCC6            = 0x00000009,
16794TCA_PERF_SEL_FORCED_HOLE_TCC7            = 0x0000000a,
16795TCA_PERF_SEL_REQ_TCC0                    = 0x0000000b,
16796TCA_PERF_SEL_REQ_TCC1                    = 0x0000000c,
16797TCA_PERF_SEL_REQ_TCC2                    = 0x0000000d,
16798TCA_PERF_SEL_REQ_TCC3                    = 0x0000000e,
16799TCA_PERF_SEL_REQ_TCC4                    = 0x0000000f,
16800TCA_PERF_SEL_REQ_TCC5                    = 0x00000010,
16801TCA_PERF_SEL_REQ_TCC6                    = 0x00000011,
16802TCA_PERF_SEL_REQ_TCC7                    = 0x00000012,
16803TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0    = 0x00000013,
16804TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1    = 0x00000014,
16805TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2    = 0x00000015,
16806TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3    = 0x00000016,
16807TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4    = 0x00000017,
16808TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5    = 0x00000018,
16809TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6    = 0x00000019,
16810TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7    = 0x0000001a,
16811TCA_PERF_SEL_CROSSBAR_STALL_TCC0         = 0x0000001b,
16812TCA_PERF_SEL_CROSSBAR_STALL_TCC1         = 0x0000001c,
16813TCA_PERF_SEL_CROSSBAR_STALL_TCC2         = 0x0000001d,
16814TCA_PERF_SEL_CROSSBAR_STALL_TCC3         = 0x0000001e,
16815TCA_PERF_SEL_CROSSBAR_STALL_TCC4         = 0x0000001f,
16816TCA_PERF_SEL_CROSSBAR_STALL_TCC5         = 0x00000020,
16817TCA_PERF_SEL_CROSSBAR_STALL_TCC6         = 0x00000021,
16818TCA_PERF_SEL_CROSSBAR_STALL_TCC7         = 0x00000022,
16819} TCA_PERF_SEL;
16820
16821/*******************************************************
16822 * GRBM Enums
16823 *******************************************************/
16824
16825/*
16826 * GRBM_PERF_SEL enum
16827 */
16828
16829typedef enum GRBM_PERF_SEL {
16830GRBM_PERF_SEL_COUNT                      = 0x00000000,
16831GRBM_PERF_SEL_USER_DEFINED               = 0x00000001,
16832GRBM_PERF_SEL_GUI_ACTIVE                 = 0x00000002,
16833GRBM_PERF_SEL_CP_BUSY                    = 0x00000003,
16834GRBM_PERF_SEL_CP_COHER_BUSY              = 0x00000004,
16835GRBM_PERF_SEL_CP_DMA_BUSY                = 0x00000005,
16836GRBM_PERF_SEL_CB_BUSY                    = 0x00000006,
16837GRBM_PERF_SEL_DB_BUSY                    = 0x00000007,
16838GRBM_PERF_SEL_PA_BUSY                    = 0x00000008,
16839GRBM_PERF_SEL_SC_BUSY                    = 0x00000009,
16840GRBM_PERF_SEL_RESERVED_6                 = 0x0000000a,
16841GRBM_PERF_SEL_SPI_BUSY                   = 0x0000000b,
16842GRBM_PERF_SEL_SX_BUSY                    = 0x0000000c,
16843GRBM_PERF_SEL_TA_BUSY                    = 0x0000000d,
16844GRBM_PERF_SEL_CB_CLEAN                   = 0x0000000e,
16845GRBM_PERF_SEL_DB_CLEAN                   = 0x0000000f,
16846GRBM_PERF_SEL_RESERVED_5                 = 0x00000010,
16847GRBM_PERF_SEL_VGT_BUSY                   = 0x00000011,
16848GRBM_PERF_SEL_RESERVED_4                 = 0x00000012,
16849GRBM_PERF_SEL_RESERVED_3                 = 0x00000013,
16850GRBM_PERF_SEL_RESERVED_2                 = 0x00000014,
16851GRBM_PERF_SEL_RESERVED_1                 = 0x00000015,
16852GRBM_PERF_SEL_RESERVED_0                 = 0x00000016,
16853GRBM_PERF_SEL_IA_BUSY                    = 0x00000017,
16854GRBM_PERF_SEL_IA_NO_DMA_BUSY             = 0x00000018,
16855GRBM_PERF_SEL_GDS_BUSY                   = 0x00000019,
16856GRBM_PERF_SEL_BCI_BUSY                   = 0x0000001a,
16857GRBM_PERF_SEL_RLC_BUSY                   = 0x0000001b,
16858GRBM_PERF_SEL_TC_BUSY                    = 0x0000001c,
16859GRBM_PERF_SEL_CPG_BUSY                   = 0x0000001d,
16860GRBM_PERF_SEL_CPC_BUSY                   = 0x0000001e,
16861GRBM_PERF_SEL_CPF_BUSY                   = 0x0000001f,
16862GRBM_PERF_SEL_WD_BUSY                    = 0x00000020,
16863GRBM_PERF_SEL_WD_NO_DMA_BUSY             = 0x00000021,
16864GRBM_PERF_SEL_UTCL2_BUSY                 = 0x00000022,
16865GRBM_PERF_SEL_EA_BUSY                    = 0x00000023,
16866GRBM_PERF_SEL_RMI_BUSY                   = 0x00000024,
16867GRBM_PERF_SEL_CPAXI_BUSY                 = 0x00000025,
16868} GRBM_PERF_SEL;
16869
16870/*
16871 * GRBM_SE0_PERF_SEL enum
16872 */
16873
16874typedef enum GRBM_SE0_PERF_SEL {
16875GRBM_SE0_PERF_SEL_COUNT                  = 0x00000000,
16876GRBM_SE0_PERF_SEL_USER_DEFINED           = 0x00000001,
16877GRBM_SE0_PERF_SEL_CB_BUSY                = 0x00000002,
16878GRBM_SE0_PERF_SEL_DB_BUSY                = 0x00000003,
16879GRBM_SE0_PERF_SEL_SC_BUSY                = 0x00000004,
16880GRBM_SE0_PERF_SEL_RESERVED_1             = 0x00000005,
16881GRBM_SE0_PERF_SEL_SPI_BUSY               = 0x00000006,
16882GRBM_SE0_PERF_SEL_SX_BUSY                = 0x00000007,
16883GRBM_SE0_PERF_SEL_TA_BUSY                = 0x00000008,
16884GRBM_SE0_PERF_SEL_CB_CLEAN               = 0x00000009,
16885GRBM_SE0_PERF_SEL_DB_CLEAN               = 0x0000000a,
16886GRBM_SE0_PERF_SEL_RESERVED_0             = 0x0000000b,
16887GRBM_SE0_PERF_SEL_PA_BUSY                = 0x0000000c,
16888GRBM_SE0_PERF_SEL_VGT_BUSY               = 0x0000000d,
16889GRBM_SE0_PERF_SEL_BCI_BUSY               = 0x0000000e,
16890GRBM_SE0_PERF_SEL_RMI_BUSY               = 0x0000000f,
16891} GRBM_SE0_PERF_SEL;
16892
16893/*
16894 * GRBM_SE1_PERF_SEL enum
16895 */
16896
16897typedef enum GRBM_SE1_PERF_SEL {
16898GRBM_SE1_PERF_SEL_COUNT                  = 0x00000000,
16899GRBM_SE1_PERF_SEL_USER_DEFINED           = 0x00000001,
16900GRBM_SE1_PERF_SEL_CB_BUSY                = 0x00000002,
16901GRBM_SE1_PERF_SEL_DB_BUSY                = 0x00000003,
16902GRBM_SE1_PERF_SEL_SC_BUSY                = 0x00000004,
16903GRBM_SE1_PERF_SEL_RESERVED_1             = 0x00000005,
16904GRBM_SE1_PERF_SEL_SPI_BUSY               = 0x00000006,
16905GRBM_SE1_PERF_SEL_SX_BUSY                = 0x00000007,
16906GRBM_SE1_PERF_SEL_TA_BUSY                = 0x00000008,
16907GRBM_SE1_PERF_SEL_CB_CLEAN               = 0x00000009,
16908GRBM_SE1_PERF_SEL_DB_CLEAN               = 0x0000000a,
16909GRBM_SE1_PERF_SEL_RESERVED_0             = 0x0000000b,
16910GRBM_SE1_PERF_SEL_PA_BUSY                = 0x0000000c,
16911GRBM_SE1_PERF_SEL_VGT_BUSY               = 0x0000000d,
16912GRBM_SE1_PERF_SEL_BCI_BUSY               = 0x0000000e,
16913GRBM_SE1_PERF_SEL_RMI_BUSY               = 0x0000000f,
16914} GRBM_SE1_PERF_SEL;
16915
16916/*
16917 * GRBM_SE2_PERF_SEL enum
16918 */
16919
16920typedef enum GRBM_SE2_PERF_SEL {
16921GRBM_SE2_PERF_SEL_COUNT                  = 0x00000000,
16922GRBM_SE2_PERF_SEL_USER_DEFINED           = 0x00000001,
16923GRBM_SE2_PERF_SEL_CB_BUSY                = 0x00000002,
16924GRBM_SE2_PERF_SEL_DB_BUSY                = 0x00000003,
16925GRBM_SE2_PERF_SEL_SC_BUSY                = 0x00000004,
16926GRBM_SE2_PERF_SEL_RESERVED_1             = 0x00000005,
16927GRBM_SE2_PERF_SEL_SPI_BUSY               = 0x00000006,
16928GRBM_SE2_PERF_SEL_SX_BUSY                = 0x00000007,
16929GRBM_SE2_PERF_SEL_TA_BUSY                = 0x00000008,
16930GRBM_SE2_PERF_SEL_CB_CLEAN               = 0x00000009,
16931GRBM_SE2_PERF_SEL_DB_CLEAN               = 0x0000000a,
16932GRBM_SE2_PERF_SEL_RESERVED_0             = 0x0000000b,
16933GRBM_SE2_PERF_SEL_PA_BUSY                = 0x0000000c,
16934GRBM_SE2_PERF_SEL_VGT_BUSY               = 0x0000000d,
16935GRBM_SE2_PERF_SEL_BCI_BUSY               = 0x0000000e,
16936GRBM_SE2_PERF_SEL_RMI_BUSY               = 0x0000000f,
16937} GRBM_SE2_PERF_SEL;
16938
16939/*
16940 * GRBM_SE3_PERF_SEL enum
16941 */
16942
16943typedef enum GRBM_SE3_PERF_SEL {
16944GRBM_SE3_PERF_SEL_COUNT                  = 0x00000000,
16945GRBM_SE3_PERF_SEL_USER_DEFINED           = 0x00000001,
16946GRBM_SE3_PERF_SEL_CB_BUSY                = 0x00000002,
16947GRBM_SE3_PERF_SEL_DB_BUSY                = 0x00000003,
16948GRBM_SE3_PERF_SEL_SC_BUSY                = 0x00000004,
16949GRBM_SE3_PERF_SEL_RESERVED_1             = 0x00000005,
16950GRBM_SE3_PERF_SEL_SPI_BUSY               = 0x00000006,
16951GRBM_SE3_PERF_SEL_SX_BUSY                = 0x00000007,
16952GRBM_SE3_PERF_SEL_TA_BUSY                = 0x00000008,
16953GRBM_SE3_PERF_SEL_CB_CLEAN               = 0x00000009,
16954GRBM_SE3_PERF_SEL_DB_CLEAN               = 0x0000000a,
16955GRBM_SE3_PERF_SEL_RESERVED_0             = 0x0000000b,
16956GRBM_SE3_PERF_SEL_PA_BUSY                = 0x0000000c,
16957GRBM_SE3_PERF_SEL_VGT_BUSY               = 0x0000000d,
16958GRBM_SE3_PERF_SEL_BCI_BUSY               = 0x0000000e,
16959GRBM_SE3_PERF_SEL_RMI_BUSY               = 0x0000000f,
16960} GRBM_SE3_PERF_SEL;
16961
16962/*******************************************************
16963 * CP Enums
16964 *******************************************************/
16965
16966/*
16967 * CP_RING_ID enum
16968 */
16969
16970typedef enum CP_RING_ID {
16971RINGID0                                  = 0x00000000,
16972RINGID1                                  = 0x00000001,
16973RINGID2                                  = 0x00000002,
16974RINGID3                                  = 0x00000003,
16975} CP_RING_ID;
16976
16977/*
16978 * CP_PIPE_ID enum
16979 */
16980
16981typedef enum CP_PIPE_ID {
16982PIPE_ID0                                 = 0x00000000,
16983PIPE_ID1                                 = 0x00000001,
16984PIPE_ID2                                 = 0x00000002,
16985PIPE_ID3                                 = 0x00000003,
16986} CP_PIPE_ID;
16987
16988/*
16989 * CP_ME_ID enum
16990 */
16991
16992typedef enum CP_ME_ID {
16993ME_ID0                                   = 0x00000000,
16994ME_ID1                                   = 0x00000001,
16995ME_ID2                                   = 0x00000002,
16996ME_ID3                                   = 0x00000003,
16997} CP_ME_ID;
16998
16999/*
17000 * SPM_PERFMON_STATE enum

17001 */
17002
17003typedef enum SPM_PERFMON_STATE {
17004STRM_PERFMON_STATE_DISABLE_AND_RESET     = 0x00000000,
17005STRM_PERFMON_STATE_START_COUNTING        = 0x00000001,
17006STRM_PERFMON_STATE_STOP_COUNTING         = 0x00000002,
17007STRM_PERFMON_STATE_RESERVED_3            = 0x00000003,
17008STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM  = 0x00000004,
17009STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM  = 0x00000005,
17010} SPM_PERFMON_STATE;
17011
17012/*
17013 * CP_PERFMON_STATE enum
17014 */
17015
17016typedef enum CP_PERFMON_STATE {
17017CP_PERFMON_STATE_DISABLE_AND_RESET       = 0x00000000,
17018CP_PERFMON_STATE_START_COUNTING          = 0x00000001,
17019CP_PERFMON_STATE_STOP_COUNTING           = 0x00000002,
17020CP_PERFMON_STATE_RESERVED_3              = 0x00000003,
17021CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM  = 0x00000004,
17022CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM  = 0x00000005,
17023} CP_PERFMON_STATE;
17024
17025/*
17026 * CP_PERFMON_ENABLE_MODE enum
17027 */
17028
17029typedef enum CP_PERFMON_ENABLE_MODE {
17030CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT      = 0x00000000,
17031CP_PERFMON_ENABLE_MODE_RESERVED_1        = 0x00000001,
17032CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE  = 0x00000002,
17033CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE  = 0x00000003,
17034} CP_PERFMON_ENABLE_MODE;
17035
17036/*
17037 * CPG_PERFCOUNT_SEL enum
17038 */
17039
17040typedef enum CPG_PERFCOUNT_SEL {
17041CPG_PERF_SEL_ALWAYS_COUNT                = 0x00000000,
17042CPG_PERF_SEL_RBIU_FIFO_FULL              = 0x00000001,
17043CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR     = 0x00000002,
17044CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL  = 0x00000003,
17045CPG_PERF_SEL_CP_GRBM_DWORDS_SENT         = 0x00000004,
17046CPG_PERF_SEL_ME_PARSER_BUSY              = 0x00000005,
17047CPG_PERF_SEL_COUNT_TYPE0_PACKETS         = 0x00000006,
17048CPG_PERF_SEL_COUNT_TYPE3_PACKETS         = 0x00000007,
17049CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS    = 0x00000008,
17050CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS      = 0x00000009,
17051CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS  = 0x0000000a,
17052CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS  = 0x0000000b,
17053CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ     = 0x0000000c,
17054CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ    = 0x0000000d,
17055CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX  = 0x0000000e,
17056CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS  = 0x0000000f,
17057CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE  = 0x00000010,
17058CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM  = 0x00000011,
17059CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY    = 0x00000012,
17060CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY    = 0x00000013,
17061CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY   = 0x00000014,
17062CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ  = 0x00000015,
17063CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP  = 0x00000016,
17064CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ  = 0x00000017,
17065CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX  = 0x00000018,
17066CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU  = 0x00000019,
17067CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS  = 0x0000001a,
17068CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH  = 0x0000001b,
17069CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER       = 0x0000001c,
17070CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER     = 0x0000001d,
17071CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS  = 0x0000001e,
17072CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY  = 0x0000001f,
17073CPG_PERF_SEL_DYNAMIC_CLK_VALID           = 0x00000020,
17074CPG_PERF_SEL_REGISTER_CLK_VALID          = 0x00000021,
17075CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT      = 0x00000022,
17076CPG_PERF_SEL_MIU_READ_REQUEST_SENT       = 0x00000023,
17077CPG_PERF_SEL_CE_STALL_RAM_DUMP           = 0x00000024,
17078CPG_PERF_SEL_CE_STALL_RAM_WRITE          = 0x00000025,
17079CPG_PERF_SEL_CE_STALL_ON_INC_FIFO        = 0x00000026,
17080CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO     = 0x00000027,
17081CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU   = 0x00000028,
17082CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ   = 0x00000029,
17083CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG  = 0x0000002a,
17084CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER      = 0x0000002b,
17085CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE     = 0x0000002c,
17086CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS     = 0x0000002d,
17087CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE  = 0x0000002e,
17088CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS  = 0x0000002f,
17089CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION  = 0x00000030,
17090} CPG_PERFCOUNT_SEL;
17091
17092/*
17093 * CPF_PERFCOUNT_SEL enum
17094 */
17095
17096typedef enum CPF_PERFCOUNT_SEL {
17097CPF_PERF_SEL_ALWAYS_COUNT                = 0x00000000,
17098CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE  = 0x00000001,
17099CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE  = 0x00000002,
17100CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS  = 0x00000003,
17101CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING  = 0x00000004,
17102CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1   = 0x00000005,
17103CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2   = 0x00000006,
17104CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE  = 0x00000007,
17105CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS  = 0x00000008,
17106CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR         = 0x00000009,
17107CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR      = 0x0000000a,
17108CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS    = 0x0000000b,
17109CPF_PERF_SEL_GRBM_DWORDS_SENT            = 0x0000000c,
17110CPF_PERF_SEL_DYNAMIC_CLOCK_VALID         = 0x0000000d,
17111CPF_PERF_SEL_REGISTER_CLOCK_VALID        = 0x0000000e,
17112CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND      = 0x0000000f,
17113CPF_PERF_SEL_MIU_READ_REQUEST_SEND       = 0x00000010,
17114CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE  = 0x00000011,
17115CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS  = 0x00000012,
17116CPF_PERF_SEL_UTCL1_STALL_ON_TRANSLATION  = 0x00000013,
17117CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE     = 0x00000014,
17118} CPF_PERFCOUNT_SEL;
17119
17120/*
17121 * CPC_PERFCOUNT_SEL enum
17122 */
17123
17124typedef enum CPC_PERFCOUNT_SEL {
17125CPC_PERF_SEL_ALWAYS_COUNT                = 0x00000000,
17126CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE     = 0x00000001,
17127CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION   = 0x00000002,
17128CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE     = 0x00000003,
17129CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE     = 0x00000004,
17130CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE     = 0x00000005,
17131CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY  = 0x00000006,
17132CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF  = 0x00000007,
17133CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ  = 0x00000008,
17134CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ  = 0x00000009,
17135CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE  = 0x0000000a,
17136CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ  = 0x0000000b,
17137CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF  = 0x0000000c,
17138CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE  = 0x0000000d,
17139CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY  = 0x0000000e,
17140CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF  = 0x0000000f,
17141CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ  = 0x00000010,
17142CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ  = 0x00000011,
17143CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE  = 0x00000012,
17144CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ  = 0x00000013,
17145CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF  = 0x00000014,
17146CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE  = 0x00000015,
17147CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE  = 0x00000016,
17148CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS  = 0x00000017,
17149CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION  = 0x00000018,
17150} CPC_PERFCOUNT_SEL;
17151
17152/*
17153 * CP_ALPHA_TAG_RAM_SEL enum
17154 */
17155
17156typedef enum CP_ALPHA_TAG_RAM_SEL {
17157CPG_TAG_RAM                              = 0x00000000,
17158CPC_TAG_RAM                              = 0x00000001,
17159CPF_TAG_RAM                              = 0x00000002,
17160RSV_TAG_RAM                              = 0x00000003,
17161} CP_ALPHA_TAG_RAM_SEL;
17162
17163/*
17164 * SEM_RESPONSE value
17165 */
17166
17167#define SEM_ECC_ERROR                  0x00000000
17168#define SEM_TRANS_ERROR                0x00000001
17169#define SEM_FAILED                     0x00000002
17170#define SEM_PASSED                     0x00000003
17171
17172/*
17173 * IQ_RETRY_TYPE value
17174 */
17175
17176#define IQ_QUEUE_SLEEP                 0x00000000
17177#define IQ_OFFLOAD_RETRY               0x00000001
17178#define IQ_SCH_WAVE_MSG                0x00000002
17179#define IQ_SEM_REARM                   0x00000003
17180#define IQ_DEQUEUE_RETRY               0x00000004
17181
17182/*
17183 * IQ_INTR_TYPE value
17184 */
17185
17186#define IQ_INTR_TYPE_PQ                0x00000000
17187#define IQ_INTR_TYPE_IB                0x00000001
17188#define IQ_INTR_TYPE_MQD               0x00000002
17189
17190/*
17191 * VMID_SIZE value
17192 */
17193
17194#define VMID_SZ                        0x00000004
17195
17196/*
17197 * CONFIG_SPACE value
17198 */
17199
17200#define CONFIG_SPACE_START             0x00002000
17201#define CONFIG_SPACE_END               0x00009fff
17202
17203/*
17204 * CONFIG_SPACE1 value
17205 */
17206
17207#define CONFIG_SPACE1_START            0x00002000
17208#define CONFIG_SPACE1_END              0x00002bff
17209
17210/*
17211 * CONFIG_SPACE2 value
17212 */
17213
17214#define CONFIG_SPACE2_START            0x00003000
17215#define CONFIG_SPACE2_END              0x00009fff
17216
17217/*
17218 * UCONFIG_SPACE value
17219 */
17220
17221#define UCONFIG_SPACE_START            0x0000c000
17222#define UCONFIG_SPACE_END              0x0000ffff
17223
17224/*
17225 * PERSISTENT_SPACE value
17226 */
17227
17228#define PERSISTENT_SPACE_START         0x00002c00
17229#define PERSISTENT_SPACE_END           0x00002fff
17230
17231/*
17232 * CONTEXT_SPACE value
17233 */
17234
17235#define CONTEXT_SPACE_START            0x0000a000
17236#define CONTEXT_SPACE_END              0x0000bfff
17237
17238/*******************************************************
17239 * SQ_UC Enums
17240 *******************************************************/
17241
17242/*
17243 * VALUE_SQ_ENC_SOP1 value
17244 */
17245
17246#define SQ_ENC_SOP1_BITS               0xbe800000
17247#define SQ_ENC_SOP1_MASK               0xff800000
17248#define SQ_ENC_SOP1_FIELD              0x0000017d
17249
17250/*
17251 * VALUE_SQ_ENC_SOPC value
17252 */
17253
17254#define SQ_ENC_SOPC_BITS               0xbf000000
17255#define SQ_ENC_SOPC_MASK               0xff800000
17256#define SQ_ENC_SOPC_FIELD              0x0000017e
17257
17258/*
17259 * VALUE_SQ_ENC_SOPP value
17260 */
17261
17262#define SQ_ENC_SOPP_BITS               0xbf800000
17263#define SQ_ENC_SOPP_MASK               0xff800000
17264#define SQ_ENC_SOPP_FIELD              0x0000017f
17265
17266/*
17267 * VALUE_SQ_ENC_SOPK value
17268 */
17269
17270#define SQ_ENC_SOPK_BITS               0xb0000000
17271#define SQ_ENC_SOPK_MASK               0xf0000000
17272#define SQ_ENC_SOPK_FIELD              0x0000000b
17273
17274/*
17275 * VALUE_SQ_ENC_SOP2 value
17276 */
17277
17278#define SQ_ENC_SOP2_BITS               0x80000000
17279#define SQ_ENC_SOP2_MASK               0xc0000000
17280#define SQ_ENC_SOP2_FIELD              0x00000002
17281
17282/*
17283 * VALUE_SQ_ENC_SMEM value
17284 */
17285
17286#define SQ_ENC_SMEM_BITS               0xc0000000
17287#define SQ_ENC_SMEM_MASK               0xfc000000
17288#define SQ_ENC_SMEM_FIELD              0x00000030
17289
17290/*
17291 * VALUE_SQ_ENC_VOP1 value
17292 */
17293
17294#define SQ_ENC_VOP1_BITS               0x7e000000
17295#define SQ_ENC_VOP1_MASK               0xfe000000
17296#define SQ_ENC_VOP1_FIELD              0x0000003f
17297
17298/*
17299 * VALUE_SQ_ENC_VOPC value
17300 */
17301
17302#define SQ_ENC_VOPC_BITS               0x7c000000
17303#define SQ_ENC_VOPC_MASK               0xfe000000
17304#define SQ_ENC_VOPC_FIELD              0x0000003e
17305
17306/*
17307 * VALUE_SQ_ENC_VOP2 value
17308 */
17309
17310#define SQ_ENC_VOP2_BITS               0x00000000
17311#define SQ_ENC_VOP2_MASK               0x80000000
17312#define SQ_ENC_VOP2_FIELD              0x00000000
17313
17314/*
17315 * VALUE_SQ_ENC_VINTRP value
17316 */
17317
17318#define SQ_ENC_VINTRP_BITS             0xd4000000
17319#define SQ_ENC_VINTRP_MASK             0xfc000000
17320#define SQ_ENC_VINTRP_FIELD            0x00000035
17321
17322/*
17323 * VALUE_SQ_ENC_VOP3P value
17324 */
17325
17326#define SQ_ENC_VOP3P_BITS              0xd3800000
17327#define SQ_ENC_VOP3P_MASK              0xff800000
17328#define SQ_ENC_VOP3P_FIELD             0x000001a7
17329
17330/*
17331 * VALUE_SQ_ENC_VOP3 value
17332 */
17333
17334#define SQ_ENC_VOP3_BITS               0xd0000000
17335#define SQ_ENC_VOP3_MASK               0xfc000000
17336#define SQ_ENC_VOP3_FIELD              0x00000034
17337
17338/*
17339 * VALUE_SQ_ENC_DS value
17340 */
17341
17342#define SQ_ENC_DS_BITS                 0xd8000000
17343#define SQ_ENC_DS_MASK                 0xfc000000
17344#define SQ_ENC_DS_FIELD                0x00000036
17345
17346/*
17347 * VALUE_SQ_ENC_MUBUF value
17348 */
17349
17350#define SQ_ENC_MUBUF_BITS              0xe0000000
17351#define SQ_ENC_MUBUF_MASK              0xfc000000
17352#define SQ_ENC_MUBUF_FIELD             0x00000038
17353
17354/*
17355 * VALUE_SQ_ENC_MTBUF value
17356 */
17357
17358#define SQ_ENC_MTBUF_BITS              0xe8000000
17359#define SQ_ENC_MTBUF_MASK              0xfc000000
17360#define SQ_ENC_MTBUF_FIELD             0x0000003a
17361
17362/*
17363 * VALUE_SQ_ENC_MIMG value
17364 */
17365
17366#define SQ_ENC_MIMG_BITS               0xf0000000
17367#define SQ_ENC_MIMG_MASK               0xfc000000
17368#define SQ_ENC_MIMG_FIELD              0x0000003c
17369
17370/*
17371 * VALUE_SQ_ENC_EXP value
17372 */
17373
17374#define SQ_ENC_EXP_BITS                0xc4000000
17375#define SQ_ENC_EXP_MASK                0xfc000000
17376#define SQ_ENC_EXP_FIELD               0x00000031
17377
17378/*
17379 * VALUE_SQ_ENC_FLAT value
17380 */
17381
17382#define SQ_ENC_FLAT_BITS               0xdc000000
17383#define SQ_ENC_FLAT_MASK               0xfc000000
17384#define SQ_ENC_FLAT_FIELD              0x00000037
17385
17386/*
17387 * VALUE_SQ_V_OP3_INTRP_COUNT value
17388 */
17389
17390#define SQ_V_OP3_INTRP_COUNT           0x0000000c
17391
17392/*
17393 * VALUE_SQ_SENDMSG_SYSTEM_SIZE value
17394 */
17395
17396#define SQ_SENDMSG_SYSTEM_SIZE         0x00000003
17397
17398/*
17399 * VALUE_SQ_HWREG_ID_SIZE value
17400 */
17401
17402#define SQ_HWREG_ID_SIZE               0x00000006
17403
17404/*
17405 * VALUE_SQ_V_OPC_COUNT value
17406 */
17407
17408#define SQ_V_OPC_COUNT                 0x00000100
17409
17410/*
17411 * VALUE_SQ_NUM_VGPR value
17412 */
17413
17414#define SQ_NUM_VGPR                    0x00000100
17415
17416/*
17417 * VALUE_SQ_WAITCNT_LGKM_SHIFT value
17418 */
17419
17420#define SQ_WAITCNT_LGKM_SHIFT          0x00000008
17421
17422/*
17423 * VALUE_SQ_HWREG_ID_SHIFT value
17424 */
17425
17426#define SQ_HWREG_ID_SHIFT              0x00000000
17427
17428/*
17429 * VALUE_SQ_EXP_NUM_POS value
17430 */
17431
17432#define SQ_EXP_NUM_POS                 0x00000004
17433
17434/*
17435 * VALUE_SQ_XLATE_VOP3_TO_VOPC_OFFSET value
17436 */
17437
17438#define SQ_XLATE_VOP3_TO_VOPC_OFFSET   0x00000000
17439
17440/*
17441 * VALUE_SQ_V_OP3_2IN_OFFSET value
17442 */
17443
17444#define SQ_V_OP3_2IN_OFFSET            0x00000280
17445
17446/*
17447 * VALUE_SQ_XLATE_VOP3_TO_VOP2_OFFSET value
17448 */
17449
17450#define SQ_XLATE_VOP3_TO_VOP2_OFFSET   0x00000100
17451
17452/*
17453 * VALUE_SQ_EXP_NUM_MRT value
17454 */
17455
17456#define SQ_EXP_NUM_MRT                 0x00000008
17457
17458/*
17459 * VALUE_SQ_NUM_TTMP value
17460 */
17461
17462#define SQ_NUM_TTMP                    0x00000010
17463
17464/*
17465 * VALUE_SQ_SENDMSG_STREAMID_SHIFT value
17466 */
17467
17468#define SQ_SENDMSG_STREAMID_SHIFT      0x00000008
17469
17470/*
17471 * VALUE_SQ_V_OP1_COUNT value
17472 */
17473
17474#define SQ_V_OP1_COUNT                 0x00000080
17475
17476/*
17477 * VALUE_SQ_WAITCNT_LGKM_SIZE value
17478 */
17479
17480#define SQ_WAITCNT_LGKM_SIZE           0x00000004
17481
17482/*
17483 * VALUE_SQ_XLATE_VOP3_TO_VOPC_COUNT value
17484 */
17485
17486#define SQ_XLATE_VOP3_TO_VOPC_COUNT    0x00000100
17487
17488/*
17489 * VALUE_SQ_SENDMSG_MSG_SHIFT value
17490 */
17491
17492#define SQ_SENDMSG_MSG_SHIFT           0x00000000
17493
17494/*
17495 * VALUE_SQ_V_OP3_3IN_OFFSET value
17496 */
17497
17498#define SQ_V_OP3_3IN_OFFSET            0x000001c0
17499
17500/*
17501 * VALUE_SQ_HWREG_OFFSET_SHIFT value
17502 */
17503
17504#define SQ_HWREG_OFFSET_SHIFT          0x00000006
17505
17506/*
17507 * VALUE_SQ_HWREG_SIZE_SHIFT value
17508 */
17509
17510#define SQ_HWREG_SIZE_SHIFT            0x0000000b
17511
17512/*
17513 * VALUE_SQ_HWREG_OFFSET_SIZE value
17514 */
17515
17516#define SQ_HWREG_OFFSET_SIZE           0x00000005
17517
17518/*
17519 * VALUE_SQ_V_OP3_3IN_COUNT value
17520 */
17521
17522#define SQ_V_OP3_3IN_COUNT             0x000000b0
17523
17524/*
17525 * VALUE_SQ_SENDMSG_MSG_SIZE value
17526 */
17527
17528#define SQ_SENDMSG_MSG_SIZE            0x00000004
17529
17530/*
17531 * VALUE_SQ_XLATE_VOP3_TO_VOP1_COUNT value
17532 */
17533
17534#define SQ_XLATE_VOP3_TO_VOP1_COUNT    0x00000080
17535
17536/*
17537 * VALUE_SQ_EXP_NUM_GDS value
17538 */
17539
17540#define SQ_EXP_NUM_GDS                 0x00000005
17541
17542/*
17543 * VALUE_SQ_V_OP2_COUNT value
17544 */
17545
17546#define SQ_V_OP2_COUNT                 0x00000040
17547
17548/*
17549 * VALUE_SQ_SENDMSG_GSOP_SIZE value
17550 */
17551
17552#define SQ_SENDMSG_GSOP_SIZE           0x00000002
17553
17554/*
17555 * VALUE_SQ_WAITCNT_VM_SHIFT value
17556 */
17557
17558#define SQ_WAITCNT_VM_SHIFT            0x00000000
17559
17560/*
17561 * VALUE_SQ_XLATE_VOP3_TO_VOP3P_COUNT value
17562 */
17563
17564#define SQ_XLATE_VOP3_TO_VOP3P_COUNT   0x00000080
17565
17566/*
17567 * VALUE_SQ_V_OP3_2IN_COUNT value
17568 */
17569
17570#define SQ_V_OP3_2IN_COUNT             0x00000080
17571
17572/*
17573 * VALUE_SQ_SENDMSG_SYSTEM_SHIFT value
17574 */
17575
17576#define SQ_SENDMSG_SYSTEM_SHIFT        0x00000004
17577
17578/*
17579 * VALUE_SQ_WAITCNT_VM_SIZE value
17580 */
17581
17582#define SQ_WAITCNT_VM_SIZE             0x00000004
17583
17584/*
17585 * VALUE_SQ_XLATE_VOP3_TO_VOP3P_OFFSET value
17586 */
17587
17588#define SQ_XLATE_VOP3_TO_VOP3P_OFFSET  0x00000380
17589
17590/*
17591 * VALUE_SQ_WAITCNT_EXP_SHIFT value
17592 */
17593
17594#define SQ_WAITCNT_EXP_SHIFT           0x00000004
17595
17596/*
17597 * VALUE_SQ_XLATE_VOP3_TO_VOP2_COUNT value
17598 */
17599
17600#define SQ_XLATE_VOP3_TO_VOP2_COUNT    0x00000040
17601
17602/*
17603 * VALUE_SQ_EXP_NUM_PARAM value
17604 */
17605
17606#define SQ_EXP_NUM_PARAM               0x00000020
17607
17608/*
17609 * VALUE_SQ_HWREG_SIZE_SIZE value
17610 */
17611
17612#define SQ_HWREG_SIZE_SIZE             0x00000005
17613
17614/*
17615 * VALUE_SQ_WAITCNT_EXP_SIZE value
17616 */
17617
17618#define SQ_WAITCNT_EXP_SIZE            0x00000003
17619
17620/*
17621 * VALUE_SQ_V_OP3_INTRP_OFFSET value
17622 */
17623
17624#define SQ_V_OP3_INTRP_OFFSET          0x00000274
17625
17626/*
17627 * VALUE_SQ_SENDMSG_GSOP_SHIFT value
17628 */
17629
17630#define SQ_SENDMSG_GSOP_SHIFT          0x00000004
17631
17632/*
17633 * VALUE_SQ_XLATE_VOP3_TO_VINTRP_OFFSET value
17634 */
17635
17636#define SQ_XLATE_VOP3_TO_VINTRP_OFFSET 0x00000270
17637
17638/*
17639 * VALUE_SQ_NUM_ATTR value
17640 */
17641
17642#define SQ_NUM_ATTR                    0x00000021
17643
17644/*
17645 * VALUE_SQ_NUM_SGPR value
17646 */
17647
17648#define SQ_NUM_SGPR                    0x00000066
17649
17650/*
17651 * VALUE_SQ_SRC_VGPR_BIT value
17652 */
17653
17654#define SQ_SRC_VGPR_BIT                0x00000100
17655
17656/*
17657 * VALUE_SQ_V_INTRP_COUNT value
17658 */
17659
17660#define SQ_V_INTRP_COUNT               0x00000004
17661
17662/*
17663 * VALUE_SQ_SENDMSG_STREAMID_SIZE value
17664 */
17665
17666#define SQ_SENDMSG_STREAMID_SIZE       0x00000002
17667
17668/*
17669 * VALUE_SQ_V_OP3P_COUNT value
17670 */
17671
17672#define SQ_V_OP3P_COUNT                0x00000080
17673
17674/*
17675 * VALUE_SQ_XLATE_VOP3_TO_VOP1_OFFSET value
17676 */
17677
17678#define SQ_XLATE_VOP3_TO_VOP1_OFFSET   0x00000140
17679
17680/*
17681 * VALUE_SQ_XLATE_VOP3_TO_VINTRP_COUNT value
17682 */
17683
17684#define SQ_XLATE_VOP3_TO_VINTRP_COUNT  0x00000004
17685
17686/*
17687 * VALUE_SQ_SSRC_SPECIAL_DPP value
17688 */
17689
17690#define SQ_SRC_DPP                     0x000000fa
17691
17692/*
17693 * VALUE_SQ_OP_MTBUF value
17694 */
17695
17696#define SQ_TBUFFER_LOAD_FORMAT_X       0x00000000
17697#define SQ_TBUFFER_LOAD_FORMAT_XY      0x00000001
17698#define SQ_TBUFFER_LOAD_FORMAT_XYZ     0x00000002
17699#define SQ_TBUFFER_LOAD_FORMAT_XYZW    0x00000003
17700#define SQ_TBUFFER_STORE_FORMAT_X      0x00000004
17701#define SQ_TBUFFER_STORE_FORMAT_XY     0x00000005
17702#define SQ_TBUFFER_STORE_FORMAT_XYZ    0x00000006
17703#define SQ_TBUFFER_STORE_FORMAT_XYZW   0x00000007
17704#define SQ_TBUFFER_LOAD_FORMAT_D16_X   0x00000008
17705#define SQ_TBUFFER_LOAD_FORMAT_D16_XY  0x00000009
17706#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZ 0x0000000a
17707#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZW 0x0000000b
17708#define SQ_TBUFFER_STORE_FORMAT_D16_X  0x0000000c
17709#define SQ_TBUFFER_STORE_FORMAT_D16_XY 0x0000000d
17710#define SQ_TBUFFER_STORE_FORMAT_D16_XYZ 0x0000000e
17711#define SQ_TBUFFER_STORE_FORMAT_D16_XYZW 0x0000000f
17712
17713/*
17714 * VALUE_SQ_OP_FLAT_GLBL value
17715 */
17716
17717#define SQ_GLOBAL_LOAD_UBYTE           0x00000010
17718#define SQ_GLOBAL_LOAD_SBYTE           0x00000011
17719#define SQ_GLOBAL_LOAD_USHORT          0x00000012
17720#define SQ_GLOBAL_LOAD_SSHORT          0x00000013
17721#define SQ_GLOBAL_LOAD_DWORD           0x00000014
17722#define SQ_GLOBAL_LOAD_DWORDX2         0x00000015
17723#define SQ_GLOBAL_LOAD_DWORDX3         0x00000016
17724#define SQ_GLOBAL_LOAD_DWORDX4         0x00000017
17725#define SQ_GLOBAL_STORE_BYTE           0x00000018
17726#define SQ_GLOBAL_STORE_SHORT          0x0000001a
17727#define SQ_GLOBAL_STORE_DWORD          0x0000001c
17728#define SQ_GLOBAL_STORE_DWORDX2        0x0000001d
17729#define SQ_GLOBAL_STORE_DWORDX3        0x0000001e
17730#define SQ_GLOBAL_STORE_DWORDX4        0x0000001f
17731#define SQ_GLOBAL_ATOMIC_SWAP          0x00000040
17732#define SQ_GLOBAL_ATOMIC_CMPSWAP       0x00000041
17733#define SQ_GLOBAL_ATOMIC_ADD           0x00000042
17734#define SQ_GLOBAL_ATOMIC_SUB           0x00000043
17735#define SQ_GLOBAL_ATOMIC_SMIN          0x00000044
17736#define SQ_GLOBAL_ATOMIC_UMIN          0x00000045
17737#define SQ_GLOBAL_ATOMIC_SMAX          0x00000046
17738#define SQ_GLOBAL_ATOMIC_UMAX          0x00000047
17739#define SQ_GLOBAL_ATOMIC_AND           0x00000048
17740#define SQ_GLOBAL_ATOMIC_OR            0x00000049
17741#define SQ_GLOBAL_ATOMIC_XOR           0x0000004a
17742#define SQ_GLOBAL_ATOMIC_INC           0x0000004b
17743#define SQ_GLOBAL_ATOMIC_DEC           0x0000004c
17744#define SQ_GLOBAL_ATOMIC_SWAP_X2       0x00000060
17745#define SQ_GLOBAL_ATOMIC_CMPSWAP_X2    0x00000061
17746#define SQ_GLOBAL_ATOMIC_ADD_X2        0x00000062
17747#define SQ_GLOBAL_ATOMIC_SUB_X2        0x00000063
17748#define SQ_GLOBAL_ATOMIC_SMIN_X2       0x00000064
17749#define SQ_GLOBAL_ATOMIC_UMIN_X2       0x00000065
17750#define SQ_GLOBAL_ATOMIC_SMAX_X2       0x00000066
17751#define SQ_GLOBAL_ATOMIC_UMAX_X2       0x00000067
17752#define SQ_GLOBAL_ATOMIC_AND_X2        0x00000068
17753#define SQ_GLOBAL_ATOMIC_OR_X2         0x00000069
17754#define SQ_GLOBAL_ATOMIC_XOR_X2        0x0000006a
17755#define SQ_GLOBAL_ATOMIC_INC_X2        0x0000006b
17756#define SQ_GLOBAL_ATOMIC_DEC_X2        0x0000006c
17757
17758/*
17759 * VALUE_SQ_VGPR value
17760 */
17761
17762#define SQ_VGPR0                       0x00000000
17763
17764/*
17765 * VALUE_SQ_OP_FLAT_SCRATCH value
17766 */
17767
17768#define SQ_SCRATCH_LOAD_UBYTE          0x00000010
17769#define SQ_SCRATCH_LOAD_SBYTE          0x00000011
17770#define SQ_SCRATCH_LOAD_USHORT         0x00000012
17771#define SQ_SCRATCH_LOAD_SSHORT         0x00000013
17772#define SQ_SCRATCH_LOAD_DWORD          0x00000014
17773#define SQ_SCRATCH_LOAD_DWORDX2        0x00000015
17774#define SQ_SCRATCH_LOAD_DWORDX3        0x00000016
17775#define SQ_SCRATCH_LOAD_DWORDX4        0x00000017
17776#define SQ_SCRATCH_STORE_BYTE          0x00000018
17777#define SQ_SCRATCH_STORE_SHORT         0x0000001a
17778#define SQ_SCRATCH_STORE_DWORD         0x0000001c
17779#define SQ_SCRATCH_STORE_DWORDX2       0x0000001d
17780#define SQ_SCRATCH_STORE_DWORDX3       0x0000001e
17781#define SQ_SCRATCH_STORE_DWORDX4       0x0000001f
17782
17783/*
17784 * VALUE_SQ_VCC value
17785 */
17786
17787#define SQ_VCC_ALL                     0x00000000
17788
17789/*
17790 * VALUE_SQ_SSRC_0_63_INLINES value
17791 */
17792
17793#define SQ_SRC_0                       0x00000080
17794#define SQ_SRC_1_INT                   0x00000081
17795#define SQ_SRC_2_INT                   0x00000082
17796#define SQ_SRC_3_INT                   0x00000083
17797#define SQ_SRC_4_INT                   0x00000084
17798#define SQ_SRC_5_INT                   0x00000085
17799#define SQ_SRC_6_INT                   0x00000086
17800#define SQ_SRC_7_INT                   0x00000087
17801#define SQ_SRC_8_INT                   0x00000088
17802#define SQ_SRC_9_INT                   0x00000089
17803#define SQ_SRC_10_INT                  0x0000008a
17804#define SQ_SRC_11_INT                  0x0000008b
17805#define SQ_SRC_12_INT                  0x0000008c
17806#define SQ_SRC_13_INT                  0x0000008d
17807#define SQ_SRC_14_INT                  0x0000008e
17808#define SQ_SRC_15_INT                  0x0000008f
17809#define SQ_SRC_16_INT                  0x00000090
17810#define SQ_SRC_17_INT                  0x00000091
17811#define SQ_SRC_18_INT                  0x00000092
17812#define SQ_SRC_19_INT                  0x00000093
17813#define SQ_SRC_20_INT                  0x00000094
17814#define SQ_SRC_21_INT                  0x00000095
17815#define SQ_SRC_22_INT                  0x00000096
17816#define SQ_SRC_23_INT                  0x00000097
17817#define SQ_SRC_24_INT                  0x00000098
17818#define SQ_SRC_25_INT                  0x00000099
17819#define SQ_SRC_26_INT                  0x0000009a
17820#define SQ_SRC_27_INT                  0x0000009b
17821#define SQ_SRC_28_INT                  0x0000009c
17822#define SQ_SRC_29_INT                  0x0000009d
17823#define SQ_SRC_30_INT                  0x0000009e
17824#define SQ_SRC_31_INT                  0x0000009f
17825#define SQ_SRC_32_INT                  0x000000a0
17826#define SQ_SRC_33_INT                  0x000000a1
17827#define SQ_SRC_34_INT                  0x000000a2
17828#define SQ_SRC_35_INT                  0x000000a3
17829#define SQ_SRC_36_INT                  0x000000a4
17830#define SQ_SRC_37_INT                  0x000000a5
17831#define SQ_SRC_38_INT                  0x000000a6
17832#define SQ_SRC_39_INT                  0x000000a7
17833#define SQ_SRC_40_INT                  0x000000a8
17834#define SQ_SRC_41_INT                  0x000000a9
17835#define SQ_SRC_42_INT                  0x000000aa
17836#define SQ_SRC_43_INT                  0x000000ab
17837#define SQ_SRC_44_INT                  0x000000ac
17838#define SQ_SRC_45_INT                  0x000000ad
17839#define SQ_SRC_46_INT                  0x000000ae
17840#define SQ_SRC_47_INT                  0x000000af
17841#define SQ_SRC_48_INT                  0x000000b0
17842#define SQ_SRC_49_INT                  0x000000b1
17843#define SQ_SRC_50_INT                  0x000000b2
17844#define SQ_SRC_51_INT                  0x000000b3
17845#define SQ_SRC_52_INT                  0x000000b4
17846#define SQ_SRC_53_INT                  0x000000b5
17847#define SQ_SRC_54_INT                  0x000000b6
17848#define SQ_SRC_55_INT                  0x000000b7
17849#define SQ_SRC_56_INT                  0x000000b8
17850#define SQ_SRC_57_INT                  0x000000b9
17851#define SQ_SRC_58_INT                  0x000000ba
17852#define SQ_SRC_59_INT                  0x000000bb
17853#define SQ_SRC_60_INT                  0x000000bc
17854#define SQ_SRC_61_INT                  0x000000bd
17855#define SQ_SRC_62_INT                  0x000000be
17856#define SQ_SRC_63_INT                  0x000000bf
17857
17858/*
17859 * VALUE_SQ_OP_MIMG value
17860 */
17861
17862#define SQ_IMAGE_LOAD                  0x00000000
17863#define SQ_IMAGE_LOAD_MIP              0x00000001
17864#define SQ_IMAGE_LOAD_PCK              0x00000002
17865#define SQ_IMAGE_LOAD_PCK_SGN          0x00000003
17866#define SQ_IMAGE_LOAD_MIP_PCK          0x00000004
17867#define SQ_IMAGE_LOAD_MIP_PCK_SGN      0x00000005
17868#define SQ_IMAGE_STORE                 0x00000008
17869#define SQ_IMAGE_STORE_MIP             0x00000009
17870#define SQ_IMAGE_STORE_PCK             0x0000000a
17871#define SQ_IMAGE_STORE_MIP_PCK         0x0000000b
17872#define SQ_IMAGE_GET_RESINFO           0x0000000e
17873#define SQ_IMAGE_ATOMIC_SWAP           0x00000010
17874#define SQ_IMAGE_ATOMIC_CMPSWAP        0x00000011
17875#define SQ_IMAGE_ATOMIC_ADD            0x00000012
17876#define SQ_IMAGE_ATOMIC_SUB            0x00000013
17877#define SQ_IMAGE_ATOMIC_SMIN           0x00000014
17878#define SQ_IMAGE_ATOMIC_UMIN           0x00000015
17879#define SQ_IMAGE_ATOMIC_SMAX           0x00000016
17880#define SQ_IMAGE_ATOMIC_UMAX           0x00000017
17881#define SQ_IMAGE_ATOMIC_AND            0x00000018
17882#define SQ_IMAGE_ATOMIC_OR             0x00000019
17883#define SQ_IMAGE_ATOMIC_XOR            0x0000001a
17884#define SQ_IMAGE_ATOMIC_INC            0x0000001b
17885#define SQ_IMAGE_ATOMIC_DEC            0x0000001c
17886#define SQ_IMAGE_SAMPLE                0x00000020
17887#define SQ_IMAGE_SAMPLE_CL             0x00000021
17888#define SQ_IMAGE_SAMPLE_D              0x00000022
17889#define SQ_IMAGE_SAMPLE_D_CL           0x00000023
17890#define SQ_IMAGE_SAMPLE_L              0x00000024
17891#define SQ_IMAGE_SAMPLE_B              0x00000025
17892#define SQ_IMAGE_SAMPLE_B_CL           0x00000026
17893#define SQ_IMAGE_SAMPLE_LZ             0x00000027
17894#define SQ_IMAGE_SAMPLE_C              0x00000028
17895#define SQ_IMAGE_SAMPLE_C_CL           0x00000029
17896#define SQ_IMAGE_SAMPLE_C_D            0x0000002a
17897#define SQ_IMAGE_SAMPLE_C_D_CL         0x0000002b
17898#define SQ_IMAGE_SAMPLE_C_L            0x0000002c
17899#define SQ_IMAGE_SAMPLE_C_B            0x0000002d
17900#define SQ_IMAGE_SAMPLE_C_B_CL         0x0000002e
17901#define SQ_IMAGE_SAMPLE_C_LZ           0x0000002f
17902#define SQ_IMAGE_SAMPLE_O              0x00000030
17903#define SQ_IMAGE_SAMPLE_CL_O           0x00000031
17904#define SQ_IMAGE_SAMPLE_D_O            0x00000032
17905#define SQ_IMAGE_SAMPLE_D_CL_O         0x00000033
17906#define SQ_IMAGE_SAMPLE_L_O            0x00000034
17907#define SQ_IMAGE_SAMPLE_B_O            0x00000035
17908#define SQ_IMAGE_SAMPLE_B_CL_O         0x00000036
17909#define SQ_IMAGE_SAMPLE_LZ_O           0x00000037
17910#define SQ_IMAGE_SAMPLE_C_O            0x00000038
17911#define SQ_IMAGE_SAMPLE_C_CL_O         0x00000039
17912#define SQ_IMAGE_SAMPLE_C_D_O          0x0000003a
17913#define SQ_IMAGE_SAMPLE_C_D_CL_O       0x0000003b
17914#define SQ_IMAGE_SAMPLE_C_L_O          0x0000003c
17915#define SQ_IMAGE_SAMPLE_C_B_O          0x0000003d
17916#define SQ_IMAGE_SAMPLE_C_B_CL_O       0x0000003e
17917#define SQ_IMAGE_SAMPLE_C_LZ_O         0x0000003f
17918#define SQ_IMAGE_GATHER4               0x00000040
17919#define SQ_IMAGE_GATHER4_CL            0x00000041
17920#define SQ_IMAGE_GATHER4H              0x00000042
17921#define SQ_IMAGE_GATHER4_L             0x00000044
17922#define SQ_IMAGE_GATHER4_B             0x00000045
17923#define SQ_IMAGE_GATHER4_B_CL          0x00000046
17924#define SQ_IMAGE_GATHER4_LZ            0x00000047
17925#define SQ_IMAGE_GATHER4_C             0x00000048
17926#define SQ_IMAGE_GATHER4_C_CL          0x00000049
17927#define SQ_IMAGE_GATHER4H_PCK          0x0000004a
17928#define SQ_IMAGE_GATHER8H_PCK          0x0000004b
17929#define SQ_IMAGE_GATHER4_C_L           0x0000004c
17930#define SQ_IMAGE_GATHER4_C_B           0x0000004d
17931#define SQ_IMAGE_GATHER4_C_B_CL        0x0000004e
17932#define SQ_IMAGE_GATHER4_C_LZ          0x0000004f
17933#define SQ_IMAGE_GATHER4_O             0x00000050
17934#define SQ_IMAGE_GATHER4_CL_O          0x00000051
17935#define SQ_IMAGE_GATHER4_L_O           0x00000054
17936#define SQ_IMAGE_GATHER4_B_O           0x00000055
17937#define SQ_IMAGE_GATHER4_B_CL_O        0x00000056
17938#define SQ_IMAGE_GATHER4_LZ_O          0x00000057
17939#define SQ_IMAGE_GATHER4_C_O           0x00000058
17940#define SQ_IMAGE_GATHER4_C_CL_O        0x00000059
17941#define SQ_IMAGE_GATHER4_C_L_O         0x0000005c
17942#define SQ_IMAGE_GATHER4_C_B_O         0x0000005d
17943#define SQ_IMAGE_GATHER4_C_B_CL_O      0x0000005e
17944#define SQ_IMAGE_GATHER4_C_LZ_O        0x0000005f
17945#define SQ_IMAGE_GET_LOD               0x00000060
17946#define SQ_IMAGE_SAMPLE_CD             0x00000068
17947#define SQ_IMAGE_SAMPLE_CD_CL          0x00000069
17948#define SQ_IMAGE_SAMPLE_C_CD           0x0000006a
17949#define SQ_IMAGE_SAMPLE_C_CD_CL        0x0000006b
17950#define SQ_IMAGE_SAMPLE_CD_O           0x0000006c
17951#define SQ_IMAGE_SAMPLE_CD_CL_O        0x0000006d
17952#define SQ_IMAGE_SAMPLE_C_CD_O         0x0000006e
17953#define SQ_IMAGE_SAMPLE_C_CD_CL_O      0x0000006f
17954#define SQ_IMAGE_RSRC256               0x0000007e
17955#define SQ_IMAGE_SAMPLER               0x0000007f
17956
17957/*
17958 * VALUE_SQ_HW_REG value
17959 */
17960
17961#define SQ_HW_REG_MODE                 0x00000001
17962#define SQ_HW_REG_STATUS               0x00000002
17963#define SQ_HW_REG_TRAPSTS              0x00000003
17964#define SQ_HW_REG_HW_ID                0x00000004
17965#define SQ_HW_REG_GPR_ALLOC            0x00000005
17966#define SQ_HW_REG_LDS_ALLOC            0x00000006
17967#define SQ_HW_REG_IB_STS               0x00000007
17968#define SQ_HW_REG_PC_LO                0x00000008
17969#define SQ_HW_REG_PC_HI                0x00000009
17970#define SQ_HW_REG_INST_DW0             0x0000000a
17971#define SQ_HW_REG_INST_DW1             0x0000000b
17972#define SQ_HW_REG_IB_DBG0              0x0000000c
17973#define SQ_HW_REG_IB_DBG1              0x0000000d
17974#define SQ_HW_REG_FLUSH_IB             0x0000000e
17975#define SQ_HW_REG_SH_MEM_BASES         0x0000000f
17976#define SQ_HW_REG_SQ_SHADER_TBA_LO     0x00000010
17977#define SQ_HW_REG_SQ_SHADER_TBA_HI     0x00000011
17978#define SQ_HW_REG_SQ_SHADER_TMA_LO     0x00000012
17979#define SQ_HW_REG_SQ_SHADER_TMA_HI     0x00000013
17980
17981/*
17982 * VALUE_SQ_OP_SOP1 value
17983 */
17984
17985#define SQ_S_MOV_B32                   0x00000000
17986#define SQ_S_MOV_B64                   0x00000001
17987#define SQ_S_CMOV_B32                  0x00000002
17988#define SQ_S_CMOV_B64                  0x00000003
17989#define SQ_S_NOT_B32                   0x00000004
17990#define SQ_S_NOT_B64                   0x00000005
17991#define SQ_S_WQM_B32                   0x00000006
17992#define SQ_S_WQM_B64                   0x00000007
17993#define SQ_S_BREV_B32                  0x00000008
17994#define SQ_S_BREV_B64                  0x00000009
17995#define SQ_S_BCNT0_I32_B32             0x0000000a
17996#define SQ_S_BCNT0_I32_B64             0x0000000b
17997#define SQ_S_BCNT1_I32_B32             0x0000000c
17998#define SQ_S_BCNT1_I32_B64             0x0000000d
17999#define SQ_S_FF0_I32_B32               0x0000000e
18000#define SQ_S_FF0_I32_B64               0x0000000f

18001#define SQ_S_FF1_I32_B32               0x00000010
18002#define SQ_S_FF1_I32_B64               0x00000011
18003#define SQ_S_FLBIT_I32_B32             0x00000012
18004#define SQ_S_FLBIT_I32_B64             0x00000013
18005#define SQ_S_FLBIT_I32                 0x00000014
18006#define SQ_S_FLBIT_I32_I64             0x00000015
18007#define SQ_S_SEXT_I32_I8               0x00000016
18008#define SQ_S_SEXT_I32_I16              0x00000017
18009#define SQ_S_BITSET0_B32               0x00000018
18010#define SQ_S_BITSET0_B64               0x00000019
18011#define SQ_S_BITSET1_B32               0x0000001a
18012#define SQ_S_BITSET1_B64               0x0000001b
18013#define SQ_S_GETPC_B64                 0x0000001c
18014#define SQ_S_SETPC_B64                 0x0000001d
18015#define SQ_S_SWAPPC_B64                0x0000001e
18016#define SQ_S_RFE_B64                   0x0000001f
18017#define SQ_S_AND_SAVEEXEC_B64          0x00000020
18018#define SQ_S_OR_SAVEEXEC_B64           0x00000021
18019#define SQ_S_XOR_SAVEEXEC_B64          0x00000022
18020#define SQ_S_ANDN2_SAVEEXEC_B64        0x00000023
18021#define SQ_S_ORN2_SAVEEXEC_B64         0x00000024
18022#define SQ_S_NAND_SAVEEXEC_B64         0x00000025
18023#define SQ_S_NOR_SAVEEXEC_B64          0x00000026
18024#define SQ_S_XNOR_SAVEEXEC_B64         0x00000027
18025#define SQ_S_QUADMASK_B32              0x00000028
18026#define SQ_S_QUADMASK_B64              0x00000029
18027#define SQ_S_MOVRELS_B32               0x0000002a
18028#define SQ_S_MOVRELS_B64               0x0000002b
18029#define SQ_S_MOVRELD_B32               0x0000002c
18030#define SQ_S_MOVRELD_B64               0x0000002d
18031#define SQ_S_CBRANCH_JOIN              0x0000002e
18032#define SQ_S_MOV_REGRD_B32             0x0000002f
18033#define SQ_S_ABS_I32                   0x00000030
18034#define SQ_S_MOV_FED_B32               0x00000031
18035#define SQ_S_SET_GPR_IDX_IDX           0x00000032
18036#define SQ_S_ANDN1_SAVEEXEC_B64        0x00000033
18037#define SQ_S_ORN1_SAVEEXEC_B64         0x00000034
18038#define SQ_S_ANDN1_WREXEC_B64          0x00000035
18039#define SQ_S_ANDN2_WREXEC_B64          0x00000036
18040#define SQ_S_BITREPLICATE_B64_B32      0x00000037
18041
18042/*
18043 * VALUE_SQ_CNT value
18044 */
18045
18046#define SQ_CNT1                        0x00000000
18047#define SQ_CNT2                        0x00000001
18048#define SQ_CNT3                        0x00000002
18049#define SQ_CNT4                        0x00000003
18050
18051/*
18052 * VALUE_SQ_OP_VOP3 value
18053 */
18054
18055#define SQ_V_MAD_LEGACY_F32            0x000001c0
18056#define SQ_V_MAD_F32                   0x000001c1
18057#define SQ_V_MAD_I32_I24               0x000001c2
18058#define SQ_V_MAD_U32_U24               0x000001c3
18059#define SQ_V_CUBEID_F32                0x000001c4
18060#define SQ_V_CUBESC_F32                0x000001c5
18061#define SQ_V_CUBETC_F32                0x000001c6
18062#define SQ_V_CUBEMA_F32                0x000001c7
18063#define SQ_V_BFE_U32                   0x000001c8
18064#define SQ_V_BFE_I32                   0x000001c9
18065#define SQ_V_BFI_B32                   0x000001ca
18066#define SQ_V_FMA_F32                   0x000001cb
18067#define SQ_V_FMA_F64                   0x000001cc
18068#define SQ_V_LERP_U8                   0x000001cd
18069#define SQ_V_ALIGNBIT_B32              0x000001ce
18070#define SQ_V_ALIGNBYTE_B32             0x000001cf
18071#define SQ_V_MIN3_F32                  0x000001d0
18072#define SQ_V_MIN3_I32                  0x000001d1
18073#define SQ_V_MIN3_U32                  0x000001d2
18074#define SQ_V_MAX3_F32                  0x000001d3
18075#define SQ_V_MAX3_I32                  0x000001d4
18076#define SQ_V_MAX3_U32                  0x000001d5
18077#define SQ_V_MED3_F32                  0x000001d6
18078#define SQ_V_MED3_I32                  0x000001d7
18079#define SQ_V_MED3_U32                  0x000001d8
18080#define SQ_V_SAD_U8                    0x000001d9
18081#define SQ_V_SAD_HI_U8                 0x000001da
18082#define SQ_V_SAD_U16                   0x000001db
18083#define SQ_V_SAD_U32                   0x000001dc
18084#define SQ_V_CVT_PK_U8_F32             0x000001dd
18085#define SQ_V_DIV_FIXUP_F32             0x000001de
18086#define SQ_V_DIV_FIXUP_F64             0x000001df
18087#define SQ_V_DIV_SCALE_F32             0x000001e0
18088#define SQ_V_DIV_SCALE_F64             0x000001e1
18089#define SQ_V_DIV_FMAS_F32              0x000001e2
18090#define SQ_V_DIV_FMAS_F64              0x000001e3
18091#define SQ_V_MSAD_U8                   0x000001e4
18092#define SQ_V_QSAD_PK_U16_U8            0x000001e5
18093#define SQ_V_MQSAD_PK_U16_U8           0x000001e6
18094#define SQ_V_MQSAD_U32_U8              0x000001e7
18095#define SQ_V_MAD_U64_U32               0x000001e8
18096#define SQ_V_MAD_I64_I32               0x000001e9
18097#define SQ_V_MAD_LEGACY_F16            0x000001ea
18098#define SQ_V_MAD_LEGACY_U16            0x000001eb
18099#define SQ_V_MAD_LEGACY_I16            0x000001ec
18100#define SQ_V_PERM_B32                  0x000001ed
18101#define SQ_V_FMA_LEGACY_F16            0x000001ee
18102#define SQ_V_DIV_FIXUP_LEGACY_F16      0x000001ef
18103#define SQ_V_CVT_PKACCUM_U8_F32        0x000001f0
18104#define SQ_V_MAD_U32_U16               0x000001f1
18105#define SQ_V_MAD_I32_I16               0x000001f2
18106#define SQ_V_XAD_U32                   0x000001f3
18107#define SQ_V_MIN3_F16                  0x000001f4
18108#define SQ_V_MIN3_I16                  0x000001f5
18109#define SQ_V_MIN3_U16                  0x000001f6
18110#define SQ_V_MAX3_F16                  0x000001f7
18111#define SQ_V_MAX3_I16                  0x000001f8
18112#define SQ_V_MAX3_U16                  0x000001f9
18113#define SQ_V_MED3_F16                  0x000001fa
18114#define SQ_V_MED3_I16                  0x000001fb
18115#define SQ_V_MED3_U16                  0x000001fc
18116#define SQ_V_LSHL_ADD_U32              0x000001fd
18117#define SQ_V_ADD_LSHL_U32              0x000001fe
18118#define SQ_V_ADD3_U32                  0x000001ff
18119#define SQ_V_LSHL_OR_B32               0x00000200
18120#define SQ_V_AND_OR_B32                0x00000201
18121#define SQ_V_OR3_B32                   0x00000202
18122#define SQ_V_MAD_F16                   0x00000203
18123#define SQ_V_MAD_U16                   0x00000204
18124#define SQ_V_MAD_I16                   0x00000205
18125#define SQ_V_FMA_F16                   0x00000206
18126#define SQ_V_DIV_FIXUP_F16             0x00000207
18127#define SQ_V_INTERP_P1LL_F16           0x00000274
18128#define SQ_V_INTERP_P1LV_F16           0x00000275
18129#define SQ_V_INTERP_P2_LEGACY_F16      0x00000276
18130#define SQ_V_INTERP_P2_F16             0x00000277
18131#define SQ_V_ADD_F64                   0x00000280
18132#define SQ_V_MUL_F64                   0x00000281
18133#define SQ_V_MIN_F64                   0x00000282
18134#define SQ_V_MAX_F64                   0x00000283
18135#define SQ_V_LDEXP_F64                 0x00000284
18136#define SQ_V_MUL_LO_U32                0x00000285
18137#define SQ_V_MUL_HI_U32                0x00000286
18138#define SQ_V_MUL_HI_I32                0x00000287
18139#define SQ_V_LDEXP_F32                 0x00000288
18140#define SQ_V_READLANE_B32              0x00000289
18141#define SQ_V_WRITELANE_B32             0x0000028a
18142#define SQ_V_BCNT_U32_B32              0x0000028b
18143#define SQ_V_MBCNT_LO_U32_B32          0x0000028c
18144#define SQ_V_MBCNT_HI_U32_B32          0x0000028d
18145#define SQ_V_MAC_LEGACY_F32            0x0000028e
18146#define SQ_V_LSHLREV_B64               0x0000028f
18147#define SQ_V_LSHRREV_B64               0x00000290
18148#define SQ_V_ASHRREV_I64               0x00000291
18149#define SQ_V_TRIG_PREOP_F64            0x00000292
18150#define SQ_V_BFM_B32                   0x00000293
18151#define SQ_V_CVT_PKNORM_I16_F32        0x00000294
18152#define SQ_V_CVT_PKNORM_U16_F32        0x00000295
18153#define SQ_V_CVT_PKRTZ_F16_F32         0x00000296
18154#define SQ_V_CVT_PK_U16_U32            0x00000297
18155#define SQ_V_CVT_PK_I16_I32            0x00000298
18156#define SQ_V_CVT_PKNORM_I16_F16        0x00000299
18157#define SQ_V_CVT_PKNORM_U16_F16        0x0000029a
18158#define SQ_V_READLANE_REGRD_B32        0x0000029b
18159#define SQ_V_ADD_I32                   0x0000029c
18160#define SQ_V_SUB_I32                   0x0000029d
18161#define SQ_V_ADD_I16                   0x0000029e
18162#define SQ_V_SUB_I16                   0x0000029f
18163#define SQ_V_PACK_B32_F16              0x000002a0
18164
18165/*
18166 * VALUE_SQ_SSRC_SPECIAL_LIT value
18167 */
18168
18169#define SQ_SRC_LITERAL                 0x000000ff
18170
18171/*
18172 * VALUE_SQ_DPP_CTRL value
18173 */
18174
18175#define SQ_DPP_QUAD_PERM               0x00000000
18176#define SQ_DPP_ROW_SL1                 0x00000101
18177#define SQ_DPP_ROW_SL2                 0x00000102
18178#define SQ_DPP_ROW_SL3                 0x00000103
18179#define SQ_DPP_ROW_SL4                 0x00000104
18180#define SQ_DPP_ROW_SL5                 0x00000105
18181#define SQ_DPP_ROW_SL6                 0x00000106
18182#define SQ_DPP_ROW_SL7                 0x00000107
18183#define SQ_DPP_ROW_SL8                 0x00000108
18184#define SQ_DPP_ROW_SL9                 0x00000109
18185#define SQ_DPP_ROW_SL10                0x0000010a
18186#define SQ_DPP_ROW_SL11                0x0000010b
18187#define SQ_DPP_ROW_SL12                0x0000010c
18188#define SQ_DPP_ROW_SL13                0x0000010d
18189#define SQ_DPP_ROW_SL14                0x0000010e
18190#define SQ_DPP_ROW_SL15                0x0000010f
18191#define SQ_DPP_ROW_SR1                 0x00000111
18192#define SQ_DPP_ROW_SR2                 0x00000112
18193#define SQ_DPP_ROW_SR3                 0x00000113
18194#define SQ_DPP_ROW_SR4                 0x00000114
18195#define SQ_DPP_ROW_SR5                 0x00000115
18196#define SQ_DPP_ROW_SR6                 0x00000116
18197#define SQ_DPP_ROW_SR7                 0x00000117
18198#define SQ_DPP_ROW_SR8                 0x00000118
18199#define SQ_DPP_ROW_SR9                 0x00000119
18200#define SQ_DPP_ROW_SR10                0x0000011a
18201#define SQ_DPP_ROW_SR11                0x0000011b
18202#define SQ_DPP_ROW_SR12                0x0000011c
18203#define SQ_DPP_ROW_SR13                0x0000011d
18204#define SQ_DPP_ROW_SR14                0x0000011e
18205#define SQ_DPP_ROW_SR15                0x0000011f
18206#define SQ_DPP_ROW_RR1                 0x00000121
18207#define SQ_DPP_ROW_RR2                 0x00000122
18208#define SQ_DPP_ROW_RR3                 0x00000123
18209#define SQ_DPP_ROW_RR4                 0x00000124
18210#define SQ_DPP_ROW_RR5                 0x00000125
18211#define SQ_DPP_ROW_RR6                 0x00000126
18212#define SQ_DPP_ROW_RR7                 0x00000127
18213#define SQ_DPP_ROW_RR8                 0x00000128
18214#define SQ_DPP_ROW_RR9                 0x00000129
18215#define SQ_DPP_ROW_RR10                0x0000012a
18216#define SQ_DPP_ROW_RR11                0x0000012b
18217#define SQ_DPP_ROW_RR12                0x0000012c
18218#define SQ_DPP_ROW_RR13                0x0000012d
18219#define SQ_DPP_ROW_RR14                0x0000012e
18220#define SQ_DPP_ROW_RR15                0x0000012f
18221#define SQ_DPP_WF_SL1                  0x00000130
18222#define SQ_DPP_WF_RL1                  0x00000134
18223#define SQ_DPP_WF_SR1                  0x00000138
18224#define SQ_DPP_WF_RR1                  0x0000013c
18225#define SQ_DPP_ROW_MIRROR              0x00000140
18226#define SQ_DPP_ROW_HALF_MIRROR         0x00000141
18227#define SQ_DPP_ROW_BCAST15             0x00000142
18228#define SQ_DPP_ROW_BCAST31             0x00000143
18229
18230/*
18231 * VALUE_SQ_FLAT_SCRATCH_LOHI value
18232 */
18233
18234#define SQ_FLAT_SCRATCH_LO             0x00000066
18235#define SQ_FLAT_SCRATCH_HI             0x00000067
18236
18237/*
18238 * VALUE_SQ_OP_VOP1 value
18239 */
18240
18241#define SQ_V_NOP                       0x00000000
18242#define SQ_V_MOV_B32                   0x00000001
18243#define SQ_V_READFIRSTLANE_B32         0x00000002
18244#define SQ_V_CVT_I32_F64               0x00000003
18245#define SQ_V_CVT_F64_I32               0x00000004
18246#define SQ_V_CVT_F32_I32               0x00000005
18247#define SQ_V_CVT_F32_U32               0x00000006
18248#define SQ_V_CVT_U32_F32               0x00000007
18249#define SQ_V_CVT_I32_F32               0x00000008
18250#define SQ_V_MOV_FED_B32               0x00000009
18251#define SQ_V_CVT_F16_F32               0x0000000a
18252#define SQ_V_CVT_F32_F16               0x0000000b
18253#define SQ_V_CVT_RPI_I32_F32           0x0000000c
18254#define SQ_V_CVT_FLR_I32_F32           0x0000000d
18255#define SQ_V_CVT_OFF_F32_I4            0x0000000e
18256#define SQ_V_CVT_F32_F64               0x0000000f
18257#define SQ_V_CVT_F64_F32               0x00000010
18258#define SQ_V_CVT_F32_UBYTE0            0x00000011
18259#define SQ_V_CVT_F32_UBYTE1            0x00000012
18260#define SQ_V_CVT_F32_UBYTE2            0x00000013
18261#define SQ_V_CVT_F32_UBYTE3            0x00000014
18262#define SQ_V_CVT_U32_F64               0x00000015
18263#define SQ_V_CVT_F64_U32               0x00000016
18264#define SQ_V_TRUNC_F64                 0x00000017
18265#define SQ_V_CEIL_F64                  0x00000018
18266#define SQ_V_RNDNE_F64                 0x00000019
18267#define SQ_V_FLOOR_F64                 0x0000001a
18268#define SQ_V_FRACT_F32                 0x0000001b
18269#define SQ_V_TRUNC_F32                 0x0000001c
18270#define SQ_V_CEIL_F32                  0x0000001d
18271#define SQ_V_RNDNE_F32                 0x0000001e
18272#define SQ_V_FLOOR_F32                 0x0000001f
18273#define SQ_V_EXP_F32                   0x00000020
18274#define SQ_V_LOG_F32                   0x00000021
18275#define SQ_V_RCP_F32                   0x00000022
18276#define SQ_V_RCP_IFLAG_F32             0x00000023
18277#define SQ_V_RSQ_F32                   0x00000024
18278#define SQ_V_RCP_F64                   0x00000025
18279#define SQ_V_RSQ_F64                   0x00000026
18280#define SQ_V_SQRT_F32                  0x00000027
18281#define SQ_V_SQRT_F64                  0x00000028
18282#define SQ_V_SIN_F32                   0x00000029
18283#define SQ_V_COS_F32                   0x0000002a
18284#define SQ_V_NOT_B32                   0x0000002b
18285#define SQ_V_BFREV_B32                 0x0000002c
18286#define SQ_V_FFBH_U32                  0x0000002d
18287#define SQ_V_FFBL_B32                  0x0000002e
18288#define SQ_V_FFBH_I32                  0x0000002f
18289#define SQ_V_FREXP_EXP_I32_F64         0x00000030
18290#define SQ_V_FREXP_MANT_F64            0x00000031
18291#define SQ_V_FRACT_F64                 0x00000032
18292#define SQ_V_FREXP_EXP_I32_F32         0x00000033
18293#define SQ_V_FREXP_MANT_F32            0x00000034
18294#define SQ_V_CLREXCP                   0x00000035
18295#define SQ_V_MOV_PRSV_B32              0x00000036
18296#define SQ_V_CVT_F16_U16               0x00000039
18297#define SQ_V_CVT_F16_I16               0x0000003a
18298#define SQ_V_CVT_U16_F16               0x0000003b
18299#define SQ_V_CVT_I16_F16               0x0000003c
18300#define SQ_V_RCP_F16                   0x0000003d
18301#define SQ_V_SQRT_F16                  0x0000003e
18302#define SQ_V_RSQ_F16                   0x0000003f
18303#define SQ_V_LOG_F16                   0x00000040
18304#define SQ_V_EXP_F16                   0x00000041
18305#define SQ_V_FREXP_MANT_F16            0x00000042
18306#define SQ_V_FREXP_EXP_I16_F16         0x00000043
18307#define SQ_V_FLOOR_F16                 0x00000044
18308#define SQ_V_CEIL_F16                  0x00000045
18309#define SQ_V_TRUNC_F16                 0x00000046
18310#define SQ_V_RNDNE_F16                 0x00000047
18311#define SQ_V_FRACT_F16                 0x00000048
18312#define SQ_V_SIN_F16                   0x00000049
18313#define SQ_V_COS_F16                   0x0000004a
18314#define SQ_V_EXP_LEGACY_F32            0x0000004b
18315#define SQ_V_LOG_LEGACY_F32            0x0000004c
18316#define SQ_V_CVT_NORM_I16_F16          0x0000004d
18317#define SQ_V_CVT_NORM_U16_F16          0x0000004e
18318#define SQ_V_SAT_PK_U8_I16             0x0000004f
18319#define SQ_V_WRITELANE_IMM32           0x00000050
18320#define SQ_V_SWAP_B32                  0x00000051
18321
18322/*
18323 * VALUE_SQ_OP_FLAT value
18324 */
18325
18326#define SQ_FLAT_LOAD_UBYTE             0x00000010
18327#define SQ_FLAT_LOAD_SBYTE             0x00000011
18328#define SQ_FLAT_LOAD_USHORT            0x00000012
18329#define SQ_FLAT_LOAD_SSHORT            0x00000013
18330#define SQ_FLAT_LOAD_DWORD             0x00000014
18331#define SQ_FLAT_LOAD_DWORDX2           0x00000015
18332#define SQ_FLAT_LOAD_DWORDX3           0x00000016
18333#define SQ_FLAT_LOAD_DWORDX4           0x00000017
18334#define SQ_FLAT_STORE_BYTE             0x00000018
18335#define SQ_FLAT_STORE_SHORT            0x0000001a
18336#define SQ_FLAT_STORE_DWORD            0x0000001c
18337#define SQ_FLAT_STORE_DWORDX2          0x0000001d
18338#define SQ_FLAT_STORE_DWORDX3          0x0000001e
18339#define SQ_FLAT_STORE_DWORDX4          0x0000001f
18340#define SQ_FLAT_ATOMIC_SWAP            0x00000040
18341#define SQ_FLAT_ATOMIC_CMPSWAP         0x00000041
18342#define SQ_FLAT_ATOMIC_ADD             0x00000042
18343#define SQ_FLAT_ATOMIC_SUB             0x00000043
18344#define SQ_FLAT_ATOMIC_SMIN            0x00000044
18345#define SQ_FLAT_ATOMIC_UMIN            0x00000045
18346#define SQ_FLAT_ATOMIC_SMAX            0x00000046
18347#define SQ_FLAT_ATOMIC_UMAX            0x00000047
18348#define SQ_FLAT_ATOMIC_AND             0x00000048
18349#define SQ_FLAT_ATOMIC_OR              0x00000049
18350#define SQ_FLAT_ATOMIC_XOR             0x0000004a
18351#define SQ_FLAT_ATOMIC_INC             0x0000004b
18352#define SQ_FLAT_ATOMIC_DEC             0x0000004c
18353#define SQ_FLAT_ATOMIC_SWAP_X2         0x00000060
18354#define SQ_FLAT_ATOMIC_CMPSWAP_X2      0x00000061
18355#define SQ_FLAT_ATOMIC_ADD_X2          0x00000062
18356#define SQ_FLAT_ATOMIC_SUB_X2          0x00000063
18357#define SQ_FLAT_ATOMIC_SMIN_X2         0x00000064
18358#define SQ_FLAT_ATOMIC_UMIN_X2         0x00000065
18359#define SQ_FLAT_ATOMIC_SMAX_X2         0x00000066
18360#define SQ_FLAT_ATOMIC_UMAX_X2         0x00000067
18361#define SQ_FLAT_ATOMIC_AND_X2          0x00000068
18362#define SQ_FLAT_ATOMIC_OR_X2           0x00000069
18363#define SQ_FLAT_ATOMIC_XOR_X2          0x0000006a
18364#define SQ_FLAT_ATOMIC_INC_X2          0x0000006b
18365#define SQ_FLAT_ATOMIC_DEC_X2          0x0000006c
18366
18367/*
18368 * VALUE_SQ_OP_DS value
18369 */
18370
18371#define SQ_DS_ADD_U32                  0x00000000
18372#define SQ_DS_SUB_U32                  0x00000001
18373#define SQ_DS_RSUB_U32                 0x00000002
18374#define SQ_DS_INC_U32                  0x00000003
18375#define SQ_DS_DEC_U32                  0x00000004
18376#define SQ_DS_MIN_I32                  0x00000005
18377#define SQ_DS_MAX_I32                  0x00000006
18378#define SQ_DS_MIN_U32                  0x00000007
18379#define SQ_DS_MAX_U32                  0x00000008
18380#define SQ_DS_AND_B32                  0x00000009
18381#define SQ_DS_OR_B32                   0x0000000a
18382#define SQ_DS_XOR_B32                  0x0000000b
18383#define SQ_DS_MSKOR_B32                0x0000000c
18384#define SQ_DS_WRITE_B32                0x0000000d
18385#define SQ_DS_WRITE2_B32               0x0000000e
18386#define SQ_DS_WRITE2ST64_B32           0x0000000f
18387#define SQ_DS_CMPST_B32                0x00000010
18388#define SQ_DS_CMPST_F32                0x00000011
18389#define SQ_DS_MIN_F32                  0x00000012
18390#define SQ_DS_MAX_F32                  0x00000013
18391#define SQ_DS_NOP                      0x00000014
18392#define SQ_DS_ADD_F32                  0x00000015
18393#define SQ_DS_WRITE_ADDTID_B32         0x0000001d
18394#define SQ_DS_WRITE_B8                 0x0000001e
18395#define SQ_DS_WRITE_B16                0x0000001f
18396#define SQ_DS_ADD_RTN_U32              0x00000020
18397#define SQ_DS_SUB_RTN_U32              0x00000021
18398#define SQ_DS_RSUB_RTN_U32             0x00000022
18399#define SQ_DS_INC_RTN_U32              0x00000023
18400#define SQ_DS_DEC_RTN_U32              0x00000024
18401#define SQ_DS_MIN_RTN_I32              0x00000025
18402#define SQ_DS_MAX_RTN_I32              0x00000026
18403#define SQ_DS_MIN_RTN_U32              0x00000027
18404#define SQ_DS_MAX_RTN_U32              0x00000028
18405#define SQ_DS_AND_RTN_B32              0x00000029
18406#define SQ_DS_OR_RTN_B32               0x0000002a
18407#define SQ_DS_XOR_RTN_B32              0x0000002b
18408#define SQ_DS_MSKOR_RTN_B32            0x0000002c
18409#define SQ_DS_WRXCHG_RTN_B32           0x0000002d
18410#define SQ_DS_WRXCHG2_RTN_B32          0x0000002e
18411#define SQ_DS_WRXCHG2ST64_RTN_B32      0x0000002f
18412#define SQ_DS_CMPST_RTN_B32            0x00000030
18413#define SQ_DS_CMPST_RTN_F32            0x00000031
18414#define SQ_DS_MIN_RTN_F32              0x00000032
18415#define SQ_DS_MAX_RTN_F32              0x00000033
18416#define SQ_DS_WRAP_RTN_B32             0x00000034
18417#define SQ_DS_ADD_RTN_F32              0x00000035
18418#define SQ_DS_READ_B32                 0x00000036
18419#define SQ_DS_READ2_B32                0x00000037
18420#define SQ_DS_READ2ST64_B32            0x00000038
18421#define SQ_DS_READ_I8                  0x00000039
18422#define SQ_DS_READ_U8                  0x0000003a
18423#define SQ_DS_READ_I16                 0x0000003b
18424#define SQ_DS_READ_U16                 0x0000003c
18425#define SQ_DS_SWIZZLE_B32              0x0000003d
18426#define SQ_DS_PERMUTE_B32              0x0000003e
18427#define SQ_DS_BPERMUTE_B32             0x0000003f
18428#define SQ_DS_ADD_U64                  0x00000040
18429#define SQ_DS_SUB_U64                  0x00000041
18430#define SQ_DS_RSUB_U64                 0x00000042
18431#define SQ_DS_INC_U64                  0x00000043
18432#define SQ_DS_DEC_U64                  0x00000044
18433#define SQ_DS_MIN_I64                  0x00000045
18434#define SQ_DS_MAX_I64                  0x00000046
18435#define SQ_DS_MIN_U64                  0x00000047
18436#define SQ_DS_MAX_U64                  0x00000048
18437#define SQ_DS_AND_B64                  0x00000049
18438#define SQ_DS_OR_B64                   0x0000004a
18439#define SQ_DS_XOR_B64                  0x0000004b
18440#define SQ_DS_MSKOR_B64                0x0000004c
18441#define SQ_DS_WRITE_B64                0x0000004d
18442#define SQ_DS_WRITE2_B64               0x0000004e
18443#define SQ_DS_WRITE2ST64_B64           0x0000004f
18444#define SQ_DS_CMPST_B64                0x00000050
18445#define SQ_DS_CMPST_F64                0x00000051
18446#define SQ_DS_MIN_F64                  0x00000052
18447#define SQ_DS_MAX_F64                  0x00000053
18448#define SQ_DS_ADD_RTN_U64              0x00000060
18449#define SQ_DS_SUB_RTN_U64              0x00000061
18450#define SQ_DS_RSUB_RTN_U64             0x00000062
18451#define SQ_DS_INC_RTN_U64              0x00000063
18452#define SQ_DS_DEC_RTN_U64              0x00000064
18453#define SQ_DS_MIN_RTN_I64              0x00000065
18454#define SQ_DS_MAX_RTN_I64              0x00000066
18455#define SQ_DS_MIN_RTN_U64              0x00000067
18456#define SQ_DS_MAX_RTN_U64              0x00000068
18457#define SQ_DS_AND_RTN_B64              0x00000069
18458#define SQ_DS_OR_RTN_B64               0x0000006a
18459#define SQ_DS_XOR_RTN_B64              0x0000006b
18460#define SQ_DS_MSKOR_RTN_B64            0x0000006c
18461#define SQ_DS_WRXCHG_RTN_B64           0x0000006d
18462#define SQ_DS_WRXCHG2_RTN_B64          0x0000006e
18463#define SQ_DS_WRXCHG2ST64_RTN_B64      0x0000006f
18464#define SQ_DS_CMPST_RTN_B64            0x00000070
18465#define SQ_DS_CMPST_RTN_F64            0x00000071
18466#define SQ_DS_MIN_RTN_F64              0x00000072
18467#define SQ_DS_MAX_RTN_F64              0x00000073
18468#define SQ_DS_READ_B64                 0x00000076
18469#define SQ_DS_READ2_B64                0x00000077
18470#define SQ_DS_READ2ST64_B64            0x00000078
18471#define SQ_DS_CONDXCHG32_RTN_B64       0x0000007e
18472#define SQ_DS_ADD_SRC2_U32             0x00000080
18473#define SQ_DS_SUB_SRC2_U32             0x00000081
18474#define SQ_DS_RSUB_SRC2_U32            0x00000082
18475#define SQ_DS_INC_SRC2_U32             0x00000083
18476#define SQ_DS_DEC_SRC2_U32             0x00000084
18477#define SQ_DS_MIN_SRC2_I32             0x00000085
18478#define SQ_DS_MAX_SRC2_I32             0x00000086
18479#define SQ_DS_MIN_SRC2_U32             0x00000087
18480#define SQ_DS_MAX_SRC2_U32             0x00000088
18481#define SQ_DS_AND_SRC2_B32             0x00000089
18482#define SQ_DS_OR_SRC2_B32              0x0000008a
18483#define SQ_DS_XOR_SRC2_B32             0x0000008b
18484#define SQ_DS_WRITE_SRC2_B32           0x0000008d
18485#define SQ_DS_MIN_SRC2_F32             0x00000092
18486#define SQ_DS_MAX_SRC2_F32             0x00000093
18487#define SQ_DS_ADD_SRC2_F32             0x00000095
18488#define SQ_DS_GWS_SEMA_RELEASE_ALL     0x00000098
18489#define SQ_DS_GWS_INIT                 0x00000099
18490#define SQ_DS_GWS_SEMA_V               0x0000009a
18491#define SQ_DS_GWS_SEMA_BR              0x0000009b
18492#define SQ_DS_GWS_SEMA_P               0x0000009c
18493#define SQ_DS_GWS_BARRIER              0x0000009d
18494#define SQ_DS_READ_ADDTID_B32          0x000000b6
18495#define SQ_DS_CONSUME                  0x000000bd
18496#define SQ_DS_APPEND                   0x000000be
18497#define SQ_DS_ORDERED_COUNT            0x000000bf
18498#define SQ_DS_ADD_SRC2_U64             0x000000c0
18499#define SQ_DS_SUB_SRC2_U64             0x000000c1
18500#define SQ_DS_RSUB_SRC2_U64            0x000000c2
18501#define SQ_DS_INC_SRC2_U64             0x000000c3
18502#define SQ_DS_DEC_SRC2_U64             0x000000c4
18503#define SQ_DS_MIN_SRC2_I64             0x000000c5
18504#define SQ_DS_MAX_SRC2_I64             0x000000c6
18505#define SQ_DS_MIN_SRC2_U64             0x000000c7
18506#define SQ_DS_MAX_SRC2_U64             0x000000c8
18507#define SQ_DS_AND_SRC2_B64             0x000000c9
18508#define SQ_DS_OR_SRC2_B64              0x000000ca
18509#define SQ_DS_XOR_SRC2_B64             0x000000cb
18510#define SQ_DS_WRITE_SRC2_B64           0x000000cd
18511#define SQ_DS_MIN_SRC2_F64             0x000000d2
18512#define SQ_DS_MAX_SRC2_F64             0x000000d3
18513#define SQ_DS_WRITE_B96                0x000000de
18514#define SQ_DS_WRITE_B128               0x000000df
18515#define SQ_DS_CONDXCHG32_RTN_B128      0x000000fd
18516#define SQ_DS_READ_B96                 0x000000fe
18517#define SQ_DS_READ_B128                0x000000ff
18518
18519/*
18520 * VALUE_SQ_OP_SMEM value
18521 */
18522
18523#define SQ_S_LOAD_DWORD                0x00000000
18524#define SQ_S_LOAD_DWORDX2              0x00000001
18525#define SQ_S_LOAD_DWORDX4              0x00000002
18526#define SQ_S_LOAD_DWORDX8              0x00000003
18527#define SQ_S_LOAD_DWORDX16             0x00000004
18528#define SQ_S_SCRATCH_LOAD_DWORD        0x00000005
18529#define SQ_S_SCRATCH_LOAD_DWORDX2      0x00000006
18530#define SQ_S_SCRATCH_LOAD_DWORDX4      0x00000007
18531#define SQ_S_BUFFER_LOAD_DWORD         0x00000008
18532#define SQ_S_BUFFER_LOAD_DWORDX2       0x00000009
18533#define SQ_S_BUFFER_LOAD_DWORDX4       0x0000000a
18534#define SQ_S_BUFFER_LOAD_DWORDX8       0x0000000b
18535#define SQ_S_BUFFER_LOAD_DWORDX16      0x0000000c
18536#define SQ_S_STORE_DWORD               0x00000010
18537#define SQ_S_STORE_DWORDX2             0x00000011
18538#define SQ_S_STORE_DWORDX4             0x00000012
18539#define SQ_S_SCRATCH_STORE_DWORD       0x00000015
18540#define SQ_S_SCRATCH_STORE_DWORDX2     0x00000016
18541#define SQ_S_SCRATCH_STORE_DWORDX4     0x00000017
18542#define SQ_S_BUFFER_STORE_DWORD        0x00000018
18543#define SQ_S_BUFFER_STORE_DWORDX2      0x00000019
18544#define SQ_S_BUFFER_STORE_DWORDX4      0x0000001a
18545#define SQ_S_DCACHE_INV                0x00000020
18546#define SQ_S_DCACHE_WB                 0x00000021
18547#define SQ_S_DCACHE_INV_VOL            0x00000022
18548#define SQ_S_DCACHE_WB_VOL             0x00000023
18549#define SQ_S_MEMTIME                   0x00000024
18550#define SQ_S_MEMREALTIME               0x00000025
18551#define SQ_S_ATC_PROBE                 0x00000026
18552#define SQ_S_ATC_PROBE_BUFFER          0x00000027
18553#define SQ_S_BUFFER_ATOMIC_SWAP        0x00000040
18554#define SQ_S_BUFFER_ATOMIC_CMPSWAP     0x00000041
18555#define SQ_S_BUFFER_ATOMIC_ADD         0x00000042
18556#define SQ_S_BUFFER_ATOMIC_SUB         0x00000043
18557#define SQ_S_BUFFER_ATOMIC_SMIN        0x00000044
18558#define SQ_S_BUFFER_ATOMIC_UMIN        0x00000045
18559#define SQ_S_BUFFER_ATOMIC_SMAX        0x00000046
18560#define SQ_S_BUFFER_ATOMIC_UMAX        0x00000047
18561#define SQ_S_BUFFER_ATOMIC_AND         0x00000048
18562#define SQ_S_BUFFER_ATOMIC_OR          0x00000049
18563#define SQ_S_BUFFER_ATOMIC_XOR         0x0000004a
18564#define SQ_S_BUFFER_ATOMIC_INC         0x0000004b
18565#define SQ_S_BUFFER_ATOMIC_DEC         0x0000004c
18566#define SQ_S_BUFFER_ATOMIC_SWAP_X2     0x00000060
18567#define SQ_S_BUFFER_ATOMIC_CMPSWAP_X2  0x00000061
18568#define SQ_S_BUFFER_ATOMIC_ADD_X2      0x00000062
18569#define SQ_S_BUFFER_ATOMIC_SUB_X2      0x00000063
18570#define SQ_S_BUFFER_ATOMIC_SMIN_X2     0x00000064
18571#define SQ_S_BUFFER_ATOMIC_UMIN_X2     0x00000065
18572#define SQ_S_BUFFER_ATOMIC_SMAX_X2     0x00000066
18573#define SQ_S_BUFFER_ATOMIC_UMAX_X2     0x00000067
18574#define SQ_S_BUFFER_ATOMIC_AND_X2      0x00000068
18575#define SQ_S_BUFFER_ATOMIC_OR_X2       0x00000069
18576#define SQ_S_BUFFER_ATOMIC_XOR_X2      0x0000006a
18577#define SQ_S_BUFFER_ATOMIC_INC_X2      0x0000006b
18578#define SQ_S_BUFFER_ATOMIC_DEC_X2      0x0000006c
18579#define SQ_S_ATOMIC_SWAP               0x00000080
18580#define SQ_S_ATOMIC_CMPSWAP            0x00000081
18581#define SQ_S_ATOMIC_ADD                0x00000082
18582#define SQ_S_ATOMIC_SUB                0x00000083
18583#define SQ_S_ATOMIC_SMIN               0x00000084
18584#define SQ_S_ATOMIC_UMIN               0x00000085
18585#define SQ_S_ATOMIC_SMAX               0x00000086
18586#define SQ_S_ATOMIC_UMAX               0x00000087
18587#define SQ_S_ATOMIC_AND                0x00000088
18588#define SQ_S_ATOMIC_OR                 0x00000089
18589#define SQ_S_ATOMIC_XOR                0x0000008a
18590#define SQ_S_ATOMIC_INC                0x0000008b
18591#define SQ_S_ATOMIC_DEC                0x0000008c
18592#define SQ_S_ATOMIC_SWAP_X2            0x000000a0
18593#define SQ_S_ATOMIC_CMPSWAP_X2         0x000000a1
18594#define SQ_S_ATOMIC_ADD_X2             0x000000a2
18595#define SQ_S_ATOMIC_SUB_X2             0x000000a3
18596#define SQ_S_ATOMIC_SMIN_X2            0x000000a4
18597#define SQ_S_ATOMIC_UMIN_X2            0x000000a5
18598#define SQ_S_ATOMIC_SMAX_X2            0x000000a6
18599#define SQ_S_ATOMIC_UMAX_X2            0x000000a7
18600#define SQ_S_ATOMIC_AND_X2             0x000000a8
18601#define SQ_S_ATOMIC_OR_X2              0x000000a9
18602#define SQ_S_ATOMIC_XOR_X2             0x000000aa
18603#define SQ_S_ATOMIC_INC_X2             0x000000ab
18604#define SQ_S_ATOMIC_DEC_X2             0x000000ac
18605
18606/*
18607 * VALUE_SQ_OP_VOP2 value
18608 */
18609
18610#define SQ_V_CNDMASK_B32               0x00000000
18611#define SQ_V_ADD_F32                   0x00000001
18612#define SQ_V_SUB_F32                   0x00000002
18613#define SQ_V_SUBREV_F32                0x00000003
18614#define SQ_V_MUL_LEGACY_F32            0x00000004
18615#define SQ_V_MUL_F32                   0x00000005
18616#define SQ_V_MUL_I32_I24               0x00000006
18617#define SQ_V_MUL_HI_I32_I24            0x00000007
18618#define SQ_V_MUL_U32_U24               0x00000008
18619#define SQ_V_MUL_HI_U32_U24            0x00000009
18620#define SQ_V_MIN_F32                   0x0000000a
18621#define SQ_V_MAX_F32                   0x0000000b
18622#define SQ_V_MIN_I32                   0x0000000c
18623#define SQ_V_MAX_I32                   0x0000000d
18624#define SQ_V_MIN_U32                   0x0000000e
18625#define SQ_V_MAX_U32                   0x0000000f
18626#define SQ_V_LSHRREV_B32               0x00000010
18627#define SQ_V_ASHRREV_I32               0x00000011
18628#define SQ_V_LSHLREV_B32               0x00000012
18629#define SQ_V_AND_B32                   0x00000013
18630#define SQ_V_OR_B32                    0x00000014
18631#define SQ_V_XOR_B32                   0x00000015
18632#define SQ_V_MAC_F32                   0x00000016
18633#define SQ_V_MADMK_F32                 0x00000017
18634#define SQ_V_MADAK_F32                 0x00000018
18635#define SQ_V_ADD_CO_U32                0x00000019
18636#define SQ_V_SUB_CO_U32                0x0000001a
18637#define SQ_V_SUBREV_CO_U32             0x0000001b
18638#define SQ_V_ADDC_CO_U32               0x0000001c
18639#define SQ_V_SUBB_CO_U32               0x0000001d
18640#define SQ_V_SUBBREV_CO_U32            0x0000001e
18641#define SQ_V_ADD_F16                   0x0000001f
18642#define SQ_V_SUB_F16                   0x00000020
18643#define SQ_V_SUBREV_F16                0x00000021
18644#define SQ_V_MUL_F16                   0x00000022
18645#define SQ_V_MAC_F16                   0x00000023
18646#define SQ_V_MADMK_F16                 0x00000024
18647#define SQ_V_MADAK_F16                 0x00000025
18648#define SQ_V_ADD_U16                   0x00000026
18649#define SQ_V_SUB_U16                   0x00000027
18650#define SQ_V_SUBREV_U16                0x00000028
18651#define SQ_V_MUL_LO_U16                0x00000029
18652#define SQ_V_LSHLREV_B16               0x0000002a
18653#define SQ_V_LSHRREV_B16               0x0000002b
18654#define SQ_V_ASHRREV_I16               0x0000002c
18655#define SQ_V_MAX_F16                   0x0000002d
18656#define SQ_V_MIN_F16                   0x0000002e
18657#define SQ_V_MAX_U16                   0x0000002f
18658#define SQ_V_MAX_I16                   0x00000030
18659#define SQ_V_MIN_U16                   0x00000031
18660#define SQ_V_MIN_I16                   0x00000032
18661#define SQ_V_LDEXP_F16                 0x00000033
18662#define SQ_V_ADD_U32                   0x00000034
18663#define SQ_V_SUB_U32                   0x00000035
18664#define SQ_V_SUBREV_U32                0x00000036
18665
18666/*
18667 * VALUE_SQ_SYSMSG_OP value
18668 */
18669
18670#define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT 0x00000001
18671#define SQ_SYSMSG_OP_REG_RD            0x00000002
18672#define SQ_SYSMSG_OP_HOST_TRAP_ACK     0x00000003
18673#define SQ_SYSMSG_OP_TTRACE_PC         0x00000004
18674#define SQ_SYSMSG_OP_ILLEGAL_INST_INTERRUPT 0x00000005
18675#define SQ_SYSMSG_OP_MEMVIOL_INTERRUPT 0x00000006
18676
18677/*
18678 * VALUE_SQ_SSRC_SPECIAL_VCCZ value
18679 */
18680
18681#define SQ_SRC_VCCZ                    0x000000fb
18682
18683/*
18684 * VALUE_SQ_CHAN value
18685 */
18686
18687#define SQ_CHAN_X                      0x00000000
18688#define SQ_CHAN_Y                      0x00000001
18689#define SQ_CHAN_Z                      0x00000002
18690#define SQ_CHAN_W                      0x00000003
18691
18692/*
18693 * VALUE_SQ_OP_SOPK value
18694 */
18695
18696#define SQ_S_MOVK_I32                  0x00000000
18697#define SQ_S_CMOVK_I32                 0x00000001
18698#define SQ_S_CMPK_EQ_I32               0x00000002
18699#define SQ_S_CMPK_LG_I32               0x00000003
18700#define SQ_S_CMPK_GT_I32               0x00000004
18701#define SQ_S_CMPK_GE_I32               0x00000005
18702#define SQ_S_CMPK_LT_I32               0x00000006
18703#define SQ_S_CMPK_LE_I32               0x00000007
18704#define SQ_S_CMPK_EQ_U32               0x00000008
18705#define SQ_S_CMPK_LG_U32               0x00000009
18706#define SQ_S_CMPK_GT_U32               0x0000000a
18707#define SQ_S_CMPK_GE_U32               0x0000000b
18708#define SQ_S_CMPK_LT_U32               0x0000000c
18709#define SQ_S_CMPK_LE_U32               0x0000000d
18710#define SQ_S_ADDK_I32                  0x0000000e
18711#define SQ_S_MULK_I32                  0x0000000f
18712#define SQ_S_CBRANCH_I_FORK            0x00000010
18713#define SQ_S_GETREG_B32                0x00000011
18714#define SQ_S_SETREG_B32                0x00000012
18715#define SQ_S_GETREG_REGRD_B32          0x00000013
18716#define SQ_S_SETREG_IMM32_B32          0x00000014
18717#define SQ_S_CALL_B64                  0x00000015
18718
18719/*
18720 * VALUE_SQ_DPP_CTRL_L_1_15 value
18721 */
18722
18723#define SQ_L1                          0x00000001
18724#define SQ_L2                          0x00000002
18725#define SQ_L3                          0x00000003
18726#define SQ_L4                          0x00000004
18727#define SQ_L5                          0x00000005
18728#define SQ_L6                          0x00000006
18729#define SQ_L7                          0x00000007
18730#define SQ_L8                          0x00000008
18731#define SQ_L9                          0x00000009
18732#define SQ_L10                         0x0000000a
18733#define SQ_L11                         0x0000000b
18734#define SQ_L12                         0x0000000c
18735#define SQ_L13                         0x0000000d
18736#define SQ_L14                         0x0000000e
18737#define SQ_L15                         0x0000000f
18738
18739/*
18740 * VALUE_SQ_SGPR value
18741 */
18742
18743#define SQ_SGPR0                       0x00000000
18744
18745/*
18746 * VALUE_SQ_OP_VOP3P value
18747 */
18748
18749#define SQ_V_PK_MAD_I16                0x00000000
18750#define SQ_V_PK_MUL_LO_U16             0x00000001
18751#define SQ_V_PK_ADD_I16                0x00000002
18752#define SQ_V_PK_SUB_I16                0x00000003
18753#define SQ_V_PK_LSHLREV_B16            0x00000004
18754#define SQ_V_PK_LSHRREV_B16            0x00000005
18755#define SQ_V_PK_ASHRREV_I16            0x00000006
18756#define SQ_V_PK_MAX_I16                0x00000007
18757#define SQ_V_PK_MIN_I16                0x00000008
18758#define SQ_V_PK_MAD_U16                0x00000009
18759#define SQ_V_PK_ADD_U16                0x0000000a
18760#define SQ_V_PK_SUB_U16                0x0000000b
18761#define SQ_V_PK_MAX_U16                0x0000000c
18762#define SQ_V_PK_MIN_U16                0x0000000d
18763#define SQ_V_PK_MAD_F16                0x0000000e
18764#define SQ_V_PK_ADD_F16                0x0000000f
18765#define SQ_V_PK_MUL_F16                0x00000010
18766#define SQ_V_PK_MIN_F16                0x00000011
18767#define SQ_V_PK_MAX_F16                0x00000012
18768#define SQ_V_MAD_MIX_F32               0x00000020
18769#define SQ_V_MAD_MIXLO_F16             0x00000021
18770#define SQ_V_MAD_MIXHI_F16             0x00000022
18771
18772/*
18773 * VALUE_SQ_OP_VINTRP value
18774 */
18775
18776#define SQ_V_INTERP_P1_F32             0x00000000
18777#define SQ_V_INTERP_P2_F32             0x00000001
18778#define SQ_V_INTERP_MOV_F32            0x00000002
18779
18780/*
18781 * VALUE_SQ_DPP_CTRL_R_1_15 value
18782 */
18783
18784#define SQ_R1                          0x00000001
18785#define SQ_R2                          0x00000002
18786#define SQ_R3                          0x00000003
18787#define SQ_R4                          0x00000004
18788#define SQ_R5                          0x00000005
18789#define SQ_R6                          0x00000006
18790#define SQ_R7                          0x00000007
18791#define SQ_R8                          0x00000008
18792#define SQ_R9                          0x00000009
18793#define SQ_R10                         0x0000000a
18794#define SQ_R11                         0x0000000b
18795#define SQ_R12                         0x0000000c
18796#define SQ_R13                         0x0000000d
18797#define SQ_R14                         0x0000000e
18798#define SQ_R15                         0x0000000f
18799
18800/*
18801 * VALUE_SQ_OP_SOP2 value
18802 */
18803
18804#define SQ_S_ADD_U32                   0x00000000
18805#define SQ_S_SUB_U32                   0x00000001
18806#define SQ_S_ADD_I32                   0x00000002
18807#define SQ_S_SUB_I32                   0x00000003
18808#define SQ_S_ADDC_U32                  0x00000004
18809#define SQ_S_SUBB_U32                  0x00000005
18810#define SQ_S_MIN_I32                   0x00000006
18811#define SQ_S_MIN_U32                   0x00000007
18812#define SQ_S_MAX_I32                   0x00000008
18813#define SQ_S_MAX_U32                   0x00000009
18814#define SQ_S_CSELECT_B32               0x0000000a
18815#define SQ_S_CSELECT_B64               0x0000000b
18816#define SQ_S_AND_B32                   0x0000000c
18817#define SQ_S_AND_B64                   0x0000000d
18818#define SQ_S_OR_B32                    0x0000000e
18819#define SQ_S_OR_B64                    0x0000000f
18820#define SQ_S_XOR_B32                   0x00000010
18821#define SQ_S_XOR_B64                   0x00000011
18822#define SQ_S_ANDN2_B32                 0x00000012
18823#define SQ_S_ANDN2_B64                 0x00000013
18824#define SQ_S_ORN2_B32                  0x00000014
18825#define SQ_S_ORN2_B64                  0x00000015
18826#define SQ_S_NAND_B32                  0x00000016
18827#define SQ_S_NAND_B64                  0x00000017
18828#define SQ_S_NOR_B32                   0x00000018
18829#define SQ_S_NOR_B64                   0x00000019
18830#define SQ_S_XNOR_B32                  0x0000001a
18831#define SQ_S_XNOR_B64                  0x0000001b
18832#define SQ_S_LSHL_B32                  0x0000001c
18833#define SQ_S_LSHL_B64                  0x0000001d
18834#define SQ_S_LSHR_B32                  0x0000001e
18835#define SQ_S_LSHR_B64                  0x0000001f
18836#define SQ_S_ASHR_I32                  0x00000020
18837#define SQ_S_ASHR_I64                  0x00000021
18838#define SQ_S_BFM_B32                   0x00000022
18839#define SQ_S_BFM_B64                   0x00000023
18840#define SQ_S_MUL_I32                   0x00000024
18841#define SQ_S_BFE_U32                   0x00000025
18842#define SQ_S_BFE_I32                   0x00000026
18843#define SQ_S_BFE_U64                   0x00000027
18844#define SQ_S_BFE_I64                   0x00000028
18845#define SQ_S_CBRANCH_G_FORK            0x00000029
18846#define SQ_S_ABSDIFF_I32               0x0000002a
18847#define SQ_S_RFE_RESTORE_B64           0x0000002b
18848#define SQ_S_MUL_HI_U32                0x0000002c
18849#define SQ_S_MUL_HI_I32                0x0000002d
18850#define SQ_S_LSHL1_ADD_U32             0x0000002e
18851#define SQ_S_LSHL2_ADD_U32             0x0000002f
18852#define SQ_S_LSHL3_ADD_U32             0x00000030
18853#define SQ_S_LSHL4_ADD_U32             0x00000031
18854#define SQ_S_PACK_LL_B32_B16           0x00000032
18855#define SQ_S_PACK_LH_B32_B16           0x00000033
18856#define SQ_S_PACK_HH_B32_B16           0x00000034
18857
18858/*
18859 * VALUE_SQ_SEG value
18860 */
18861
18862#define SQ_FLAT                        0x00000000
18863#define SQ_SCRATCH                     0x00000001
18864#define SQ_GLOBAL                      0x00000002
18865
18866/*
18867 * VALUE_SQ_SDST_EXEC value
18868 */
18869
18870#define SQ_EXEC_LO                     0x0000007e
18871#define SQ_EXEC_HI                     0x0000007f
18872
18873/*
18874 * VALUE_SQ_SSRC_SPECIAL_NOLIT value
18875 */
18876
18877#define SQ_SRC_64_INT                  0x000000c0
18878#define SQ_SRC_M_1_INT                 0x000000c1
18879#define SQ_SRC_M_2_INT                 0x000000c2
18880#define SQ_SRC_M_3_INT                 0x000000c3
18881#define SQ_SRC_M_4_INT                 0x000000c4
18882#define SQ_SRC_M_5_INT                 0x000000c5
18883#define SQ_SRC_M_6_INT                 0x000000c6
18884#define SQ_SRC_M_7_INT                 0x000000c7
18885#define SQ_SRC_M_8_INT                 0x000000c8
18886#define SQ_SRC_M_9_INT                 0x000000c9
18887#define SQ_SRC_M_10_INT                0x000000ca
18888#define SQ_SRC_M_11_INT                0x000000cb
18889#define SQ_SRC_M_12_INT                0x000000cc
18890#define SQ_SRC_M_13_INT                0x000000cd
18891#define SQ_SRC_M_14_INT                0x000000ce
18892#define SQ_SRC_M_15_INT                0x000000cf
18893#define SQ_SRC_M_16_INT                0x000000d0
18894#define SQ_SRC_0_5                     0x000000f0
18895#define SQ_SRC_M_0_5                   0x000000f1
18896#define SQ_SRC_1                       0x000000f2
18897#define SQ_SRC_M_1                     0x000000f3
18898#define SQ_SRC_2                       0x000000f4
18899#define SQ_SRC_M_2                     0x000000f5
18900#define SQ_SRC_4                       0x000000f6
18901#define SQ_SRC_M_4                     0x000000f7
18902#define SQ_SRC_INV_2PI                 0x000000f8
18903
18904/*
18905 * VALUE_SQ_VCC_LOHI value
18906 */
18907
18908#define SQ_VCC_LO                      0x0000006a
18909#define SQ_VCC_HI                      0x0000006b
18910
18911/*
18912 * VALUE_SQ_TGT value
18913 */
18914
18915#define SQ_EXP_MRT0                    0x00000000
18916#define SQ_EXP_MRTZ                    0x00000008
18917#define SQ_EXP_NULL                    0x00000009
18918#define SQ_EXP_POS0                    0x0000000c
18919#define SQ_EXP_PARAM0                  0x00000020
18920
18921/*
18922 * VALUE_SQ_OP_SOPP value
18923 */
18924
18925#define SQ_S_NOP                       0x00000000
18926#define SQ_S_ENDPGM                    0x00000001
18927#define SQ_S_BRANCH                    0x00000002
18928#define SQ_S_WAKEUP                    0x00000003
18929#define SQ_S_CBRANCH_SCC0              0x00000004
18930#define SQ_S_CBRANCH_SCC1              0x00000005
18931#define SQ_S_CBRANCH_VCCZ              0x00000006
18932#define SQ_S_CBRANCH_VCCNZ             0x00000007
18933#define SQ_S_CBRANCH_EXECZ             0x00000008
18934#define SQ_S_CBRANCH_EXECNZ            0x00000009
18935#define SQ_S_BARRIER                   0x0000000a
18936#define SQ_S_SETKILL                   0x0000000b
18937#define SQ_S_WAITCNT                   0x0000000c
18938#define SQ_S_SETHALT                   0x0000000d
18939#define SQ_S_SLEEP                     0x0000000e
18940#define SQ_S_SETPRIO                   0x0000000f
18941#define SQ_S_SENDMSG                   0x00000010
18942#define SQ_S_SENDMSGHALT               0x00000011
18943#define SQ_S_TRAP                      0x00000012
18944#define SQ_S_ICACHE_INV                0x00000013
18945#define SQ_S_INCPERFLEVEL              0x00000014
18946#define SQ_S_DECPERFLEVEL              0x00000015
18947#define SQ_S_TTRACEDATA                0x00000016
18948#define SQ_S_CBRANCH_CDBGSYS           0x00000017
18949#define SQ_S_CBRANCH_CDBGUSER          0x00000018
18950#define SQ_S_CBRANCH_CDBGSYS_OR_USER   0x00000019
18951#define SQ_S_CBRANCH_CDBGSYS_AND_USER  0x0000001a
18952#define SQ_S_ENDPGM_SAVED              0x0000001b
18953#define SQ_S_SET_GPR_IDX_OFF           0x0000001c
18954#define SQ_S_SET_GPR_IDX_MODE          0x0000001d
18955#define SQ_S_ENDPGM_ORDERED_PS_DONE    0x0000001e
18956
18957/*
18958 * VALUE_SQ_OP_EXP value
18959 */
18960
18961#define SQ_EXP                         0x00000000
18962
18963/*
18964 * VALUE_SQ_SSRC_SPECIAL_POPS_EXITING_WAVE_ID value
18965 */
18966
18967#define SQ_SRC_POPS_EXITING_WAVE_ID    0x000000ef
18968
18969/*
18970 * VALUE_SQ_XNACK_MASK_LOHI value
18971 */
18972
18973#define SQ_XNACK_MASK_LO               0x00000068
18974#define SQ_XNACK_MASK_HI               0x00000069
18975
18976/*
18977 * VALUE_SQ_OMOD value
18978 */
18979
18980#define SQ_OMOD_OFF                    0x00000000
18981#define SQ_OMOD_M2                     0x00000001
18982#define SQ_OMOD_M4                     0x00000002
18983#define SQ_OMOD_D2                     0x00000003
18984
18985/*
18986 * VALUE_SQ_SSRC_SPECIAL_EXECZ value
18987 */
18988
18989#define SQ_SRC_EXECZ                   0x000000fc
18990
18991/*
18992 * VALUE_SQ_COMPI value
18993 */
18994
18995#define SQ_F                           0x00000000
18996#define SQ_LT                          0x00000001
18997#define SQ_EQ                          0x00000002
18998#define SQ_LE                          0x00000003
18999#define SQ_GT                          0x00000004
19000#define SQ_NE                          0x00000005

19001#define SQ_GE                          0x00000006
19002#define SQ_T                           0x00000007
19003
19004/*
19005 * VALUE_SQ_DPP_BOUND_CTRL value
19006 */
19007
19008#define SQ_DPP_BOUND_OFF               0x00000000
19009#define SQ_DPP_BOUND_ZERO              0x00000001
19010
19011/*
19012 * VALUE_SQ_SDST_M0 value
19013 */
19014
19015#define SQ_M0                          0x0000007c
19016
19017/*
19018 * VALUE_SQ_MSG value
19019 */
19020
19021#define SQ_MSG_INTERRUPT               0x00000001
19022#define SQ_MSG_GS                      0x00000002
19023#define SQ_MSG_GS_DONE                 0x00000003
19024#define SQ_MSG_SAVEWAVE                0x00000004
19025#define SQ_MSG_STALL_WAVE_GEN          0x00000005
19026#define SQ_MSG_HALT_WAVES              0x00000006
19027#define SQ_MSG_ORDERED_PS_DONE         0x00000007
19028#define SQ_MSG_EARLY_PRIM_DEALLOC      0x00000008
19029#define SQ_MSG_GS_ALLOC_REQ            0x00000009
19030#define SQ_MSG_SYSMSG                  0x0000000f
19031
19032/*
19033 * VALUE_SQ_PARAM value
19034 */
19035
19036#define SQ_PARAM_P10                   0x00000000
19037#define SQ_PARAM_P20                   0x00000001
19038#define SQ_PARAM_P0                    0x00000002
19039
19040/*
19041 * VALUE_SQ_OPU_VOP3 value
19042 */
19043
19044#define SQ_V_OPC_OFFSET                0x00000000
19045#define SQ_V_OP2_OFFSET                0x00000100
19046#define SQ_V_OP1_OFFSET                0x00000140
19047#define SQ_V_INTRP_OFFSET              0x00000270
19048#define SQ_V_OP3P_OFFSET               0x00000380
19049
19050/*
19051 * VALUE_SQ_SSRC_SPECIAL_SDWA value
19052 */
19053
19054#define SQ_SRC_SDWA                    0x000000f9
19055
19056/*
19057 * VALUE_SQ_SSRC_SPECIAL_APERTURE value
19058 */
19059
19060#define SQ_SRC_SHARED_BASE             0x000000eb
19061#define SQ_SRC_SHARED_LIMIT            0x000000ec
19062#define SQ_SRC_PRIVATE_BASE            0x000000ed
19063#define SQ_SRC_PRIVATE_LIMIT           0x000000ee
19064
19065/*
19066 * VALUE_SQ_COMPF value
19067 */
19068
19069#define SQ_F                           0x00000000
19070#define SQ_LT                          0x00000001
19071#define SQ_EQ                          0x00000002
19072#define SQ_LE                          0x00000003
19073#define SQ_GT                          0x00000004
19074#define SQ_LG                          0x00000005
19075#define SQ_GE                          0x00000006
19076#define SQ_O                           0x00000007
19077#define SQ_U                           0x00000008
19078#define SQ_NGE                         0x00000009
19079#define SQ_NLG                         0x0000000a
19080#define SQ_NGT                         0x0000000b
19081#define SQ_NLE                         0x0000000c
19082#define SQ_NEQ                         0x0000000d
19083#define SQ_NLT                         0x0000000e
19084#define SQ_TRU                         0x0000000f
19085
19086/*
19087 * VALUE_SQ_SDWA_UNUSED value
19088 */
19089
19090#define SQ_SDWA_UNUSED_PAD             0x00000000
19091#define SQ_SDWA_UNUSED_SEXT            0x00000001
19092#define SQ_SDWA_UNUSED_PRESERVE        0x00000002
19093
19094/*
19095 * VALUE_SQ_SSRC_SPECIAL_SCC value
19096 */
19097
19098#define SQ_SRC_SCC                     0x000000fd
19099
19100/*
19101 * VALUE_SQ_OP_VOPC value
19102 */
19103
19104#define SQ_V_CMP_CLASS_F32             0x00000010
19105#define SQ_V_CMPX_CLASS_F32            0x00000011
19106#define SQ_V_CMP_CLASS_F64             0x00000012
19107#define SQ_V_CMPX_CLASS_F64            0x00000013
19108#define SQ_V_CMP_CLASS_F16             0x00000014
19109#define SQ_V_CMPX_CLASS_F16            0x00000015
19110#define SQ_V_CMP_F_F16                 0x00000020
19111#define SQ_V_CMP_LT_F16                0x00000021
19112#define SQ_V_CMP_EQ_F16                0x00000022
19113#define SQ_V_CMP_LE_F16                0x00000023
19114#define SQ_V_CMP_GT_F16                0x00000024
19115#define SQ_V_CMP_LG_F16                0x00000025
19116#define SQ_V_CMP_GE_F16                0x00000026
19117#define SQ_V_CMP_O_F16                 0x00000027
19118#define SQ_V_CMP_U_F16                 0x00000028
19119#define SQ_V_CMP_NGE_F16               0x00000029
19120#define SQ_V_CMP_NLG_F16               0x0000002a
19121#define SQ_V_CMP_NGT_F16               0x0000002b
19122#define SQ_V_CMP_NLE_F16               0x0000002c
19123#define SQ_V_CMP_NEQ_F16               0x0000002d
19124#define SQ_V_CMP_NLT_F16               0x0000002e
19125#define SQ_V_CMP_TRU_F16               0x0000002f
19126#define SQ_V_CMPX_F_F16                0x00000030
19127#define SQ_V_CMPX_LT_F16               0x00000031
19128#define SQ_V_CMPX_EQ_F16               0x00000032
19129#define SQ_V_CMPX_LE_F16               0x00000033
19130#define SQ_V_CMPX_GT_F16               0x00000034
19131#define SQ_V_CMPX_LG_F16               0x00000035
19132#define SQ_V_CMPX_GE_F16               0x00000036
19133#define SQ_V_CMPX_O_F16                0x00000037
19134#define SQ_V_CMPX_U_F16                0x00000038
19135#define SQ_V_CMPX_NGE_F16              0x00000039
19136#define SQ_V_CMPX_NLG_F16              0x0000003a
19137#define SQ_V_CMPX_NGT_F16              0x0000003b
19138#define SQ_V_CMPX_NLE_F16              0x0000003c
19139#define SQ_V_CMPX_NEQ_F16              0x0000003d
19140#define SQ_V_CMPX_NLT_F16              0x0000003e
19141#define SQ_V_CMPX_TRU_F16              0x0000003f
19142#define SQ_V_CMP_F_F32                 0x00000040
19143#define SQ_V_CMP_LT_F32                0x00000041
19144#define SQ_V_CMP_EQ_F32                0x00000042
19145#define SQ_V_CMP_LE_F32                0x00000043
19146#define SQ_V_CMP_GT_F32                0x00000044
19147#define SQ_V_CMP_LG_F32                0x00000045
19148#define SQ_V_CMP_GE_F32                0x00000046
19149#define SQ_V_CMP_O_F32                 0x00000047
19150#define SQ_V_CMP_U_F32                 0x00000048
19151#define SQ_V_CMP_NGE_F32               0x00000049
19152#define SQ_V_CMP_NLG_F32               0x0000004a
19153#define SQ_V_CMP_NGT_F32               0x0000004b
19154#define SQ_V_CMP_NLE_F32               0x0000004c
19155#define SQ_V_CMP_NEQ_F32               0x0000004d
19156#define SQ_V_CMP_NLT_F32               0x0000004e
19157#define SQ_V_CMP_TRU_F32               0x0000004f
19158#define SQ_V_CMPX_F_F32                0x00000050
19159#define SQ_V_CMPX_LT_F32               0x00000051
19160#define SQ_V_CMPX_EQ_F32               0x00000052
19161#define SQ_V_CMPX_LE_F32               0x00000053
19162#define SQ_V_CMPX_GT_F32               0x00000054
19163#define SQ_V_CMPX_LG_F32               0x00000055
19164#define SQ_V_CMPX_GE_F32               0x00000056
19165#define SQ_V_CMPX_O_F32                0x00000057
19166#define SQ_V_CMPX_U_F32                0x00000058
19167#define SQ_V_CMPX_NGE_F32              0x00000059
19168#define SQ_V_CMPX_NLG_F32              0x0000005a
19169#define SQ_V_CMPX_NGT_F32              0x0000005b
19170#define SQ_V_CMPX_NLE_F32              0x0000005c
19171#define SQ_V_CMPX_NEQ_F32              0x0000005d
19172#define SQ_V_CMPX_NLT_F32              0x0000005e
19173#define SQ_V_CMPX_TRU_F32              0x0000005f
19174#define SQ_V_CMP_F_F64                 0x00000060
19175#define SQ_V_CMP_LT_F64                0x00000061
19176#define SQ_V_CMP_EQ_F64                0x00000062
19177#define SQ_V_CMP_LE_F64                0x00000063
19178#define SQ_V_CMP_GT_F64                0x00000064
19179#define SQ_V_CMP_LG_F64                0x00000065
19180#define SQ_V_CMP_GE_F64                0x00000066
19181#define SQ_V_CMP_O_F64                 0x00000067
19182#define SQ_V_CMP_U_F64                 0x00000068
19183#define SQ_V_CMP_NGE_F64               0x00000069
19184#define SQ_V_CMP_NLG_F64               0x0000006a
19185#define SQ_V_CMP_NGT_F64               0x0000006b
19186#define SQ_V_CMP_NLE_F64               0x0000006c
19187#define SQ_V_CMP_NEQ_F64               0x0000006d
19188#define SQ_V_CMP_NLT_F64               0x0000006e
19189#define SQ_V_CMP_TRU_F64               0x0000006f
19190#define SQ_V_CMPX_F_F64                0x00000070
19191#define SQ_V_CMPX_LT_F64               0x00000071
19192#define SQ_V_CMPX_EQ_F64               0x00000072
19193#define SQ_V_CMPX_LE_F64               0x00000073
19194#define SQ_V_CMPX_GT_F64               0x00000074
19195#define SQ_V_CMPX_LG_F64               0x00000075
19196#define SQ_V_CMPX_GE_F64               0x00000076
19197#define SQ_V_CMPX_O_F64                0x00000077
19198#define SQ_V_CMPX_U_F64                0x00000078
19199#define SQ_V_CMPX_NGE_F64              0x00000079
19200#define SQ_V_CMPX_NLG_F64              0x0000007a
19201#define SQ_V_CMPX_NGT_F64              0x0000007b
19202#define SQ_V_CMPX_NLE_F64              0x0000007c
19203#define SQ_V_CMPX_NEQ_F64              0x0000007d
19204#define SQ_V_CMPX_NLT_F64              0x0000007e
19205#define SQ_V_CMPX_TRU_F64              0x0000007f
19206#define SQ_V_CMP_F_I16                 0x000000a0
19207#define SQ_V_CMP_LT_I16                0x000000a1
19208#define SQ_V_CMP_EQ_I16                0x000000a2
19209#define SQ_V_CMP_LE_I16                0x000000a3
19210#define SQ_V_CMP_GT_I16                0x000000a4
19211#define SQ_V_CMP_NE_I16                0x000000a5
19212#define SQ_V_CMP_GE_I16                0x000000a6
19213#define SQ_V_CMP_T_I16                 0x000000a7
19214#define SQ_V_CMP_F_U16                 0x000000a8
19215#define SQ_V_CMP_LT_U16                0x000000a9
19216#define SQ_V_CMP_EQ_U16                0x000000aa
19217#define SQ_V_CMP_LE_U16                0x000000ab
19218#define SQ_V_CMP_GT_U16                0x000000ac
19219#define SQ_V_CMP_NE_U16                0x000000ad
19220#define SQ_V_CMP_GE_U16                0x000000ae
19221#define SQ_V_CMP_T_U16                 0x000000af
19222#define SQ_V_CMPX_F_I16                0x000000b0
19223#define SQ_V_CMPX_LT_I16               0x000000b1
19224#define SQ_V_CMPX_EQ_I16               0x000000b2
19225#define SQ_V_CMPX_LE_I16               0x000000b3
19226#define SQ_V_CMPX_GT_I16               0x000000b4
19227#define SQ_V_CMPX_NE_I16               0x000000b5
19228#define SQ_V_CMPX_GE_I16               0x000000b6
19229#define SQ_V_CMPX_T_I16                0x000000b7
19230#define SQ_V_CMPX_F_U16                0x000000b8
19231#define SQ_V_CMPX_LT_U16               0x000000b9
19232#define SQ_V_CMPX_EQ_U16               0x000000ba
19233#define SQ_V_CMPX_LE_U16               0x000000bb
19234#define SQ_V_CMPX_GT_U16               0x000000bc
19235#define SQ_V_CMPX_NE_U16               0x000000bd
19236#define SQ_V_CMPX_GE_U16               0x000000be
19237#define SQ_V_CMPX_T_U16                0x000000bf
19238#define SQ_V_CMP_F_I32                 0x000000c0
19239#define SQ_V_CMP_LT_I32                0x000000c1
19240#define SQ_V_CMP_EQ_I32                0x000000c2
19241#define SQ_V_CMP_LE_I32                0x000000c3
19242#define SQ_V_CMP_GT_I32                0x000000c4
19243#define SQ_V_CMP_NE_I32                0x000000c5
19244#define SQ_V_CMP_GE_I32                0x000000c6
19245#define SQ_V_CMP_T_I32                 0x000000c7
19246#define SQ_V_CMP_F_U32                 0x000000c8
19247#define SQ_V_CMP_LT_U32                0x000000c9
19248#define SQ_V_CMP_EQ_U32                0x000000ca
19249#define SQ_V_CMP_LE_U32                0x000000cb
19250#define SQ_V_CMP_GT_U32                0x000000cc
19251#define SQ_V_CMP_NE_U32                0x000000cd
19252#define SQ_V_CMP_GE_U32                0x000000ce
19253#define SQ_V_CMP_T_U32                 0x000000cf
19254#define SQ_V_CMPX_F_I32                0x000000d0
19255#define SQ_V_CMPX_LT_I32               0x000000d1
19256#define SQ_V_CMPX_EQ_I32               0x000000d2
19257#define SQ_V_CMPX_LE_I32               0x000000d3
19258#define SQ_V_CMPX_GT_I32               0x000000d4
19259#define SQ_V_CMPX_NE_I32               0x000000d5
19260#define SQ_V_CMPX_GE_I32               0x000000d6
19261#define SQ_V_CMPX_T_I32                0x000000d7
19262#define SQ_V_CMPX_F_U32                0x000000d8
19263#define SQ_V_CMPX_LT_U32               0x000000d9
19264#define SQ_V_CMPX_EQ_U32               0x000000da
19265#define SQ_V_CMPX_LE_U32               0x000000db
19266#define SQ_V_CMPX_GT_U32               0x000000dc
19267#define SQ_V_CMPX_NE_U32               0x000000dd
19268#define SQ_V_CMPX_GE_U32               0x000000de
19269#define SQ_V_CMPX_T_U32                0x000000df
19270#define SQ_V_CMP_F_I64                 0x000000e0
19271#define SQ_V_CMP_LT_I64                0x000000e1
19272#define SQ_V_CMP_EQ_I64                0x000000e2
19273#define SQ_V_CMP_LE_I64                0x000000e3
19274#define SQ_V_CMP_GT_I64                0x000000e4
19275#define SQ_V_CMP_NE_I64                0x000000e5
19276#define SQ_V_CMP_GE_I64                0x000000e6
19277#define SQ_V_CMP_T_I64                 0x000000e7
19278#define SQ_V_CMP_F_U64                 0x000000e8
19279#define SQ_V_CMP_LT_U64                0x000000e9
19280#define SQ_V_CMP_EQ_U64                0x000000ea
19281#define SQ_V_CMP_LE_U64                0x000000eb
19282#define SQ_V_CMP_GT_U64                0x000000ec
19283#define SQ_V_CMP_NE_U64                0x000000ed
19284#define SQ_V_CMP_GE_U64                0x000000ee
19285#define SQ_V_CMP_T_U64                 0x000000ef
19286#define SQ_V_CMPX_F_I64                0x000000f0
19287#define SQ_V_CMPX_LT_I64               0x000000f1
19288#define SQ_V_CMPX_EQ_I64               0x000000f2
19289#define SQ_V_CMPX_LE_I64               0x000000f3
19290#define SQ_V_CMPX_GT_I64               0x000000f4
19291#define SQ_V_CMPX_NE_I64               0x000000f5
19292#define SQ_V_CMPX_GE_I64               0x000000f6
19293#define SQ_V_CMPX_T_I64                0x000000f7
19294#define SQ_V_CMPX_F_U64                0x000000f8
19295#define SQ_V_CMPX_LT_U64               0x000000f9
19296#define SQ_V_CMPX_EQ_U64               0x000000fa
19297#define SQ_V_CMPX_LE_U64               0x000000fb
19298#define SQ_V_CMPX_GT_U64               0x000000fc
19299#define SQ_V_CMPX_NE_U64               0x000000fd
19300#define SQ_V_CMPX_GE_U64               0x000000fe
19301#define SQ_V_CMPX_T_U64                0x000000ff
19302
19303/*
19304 * VALUE_SQ_GS_OP value
19305 */
19306
19307#define SQ_GS_OP_NOP                   0x00000000
19308#define SQ_GS_OP_CUT                   0x00000001
19309#define SQ_GS_OP_EMIT                  0x00000002
19310#define SQ_GS_OP_EMIT_CUT              0x00000003
19311
19312/*
19313 * VALUE_SQ_SSRC_SPECIAL_LDS value
19314 */
19315
19316#define SQ_SRC_LDS_DIRECT              0x000000fe
19317
19318/*
19319 * VALUE_SQ_ATTR value
19320 */
19321
19322#define SQ_ATTR0                       0x00000000
19323
19324/*
19325 * VALUE_SQ_TGT_INTERNAL value
19326 */
19327
19328#define SQ_EXP_GDS0                    0x00000018
19329
19330/*
19331 * VALUE_SQ_OP_SOPC value
19332 */
19333
19334#define SQ_S_CMP_EQ_I32                0x00000000
19335#define SQ_S_CMP_LG_I32                0x00000001
19336#define SQ_S_CMP_GT_I32                0x00000002
19337#define SQ_S_CMP_GE_I32                0x00000003
19338#define SQ_S_CMP_LT_I32                0x00000004
19339#define SQ_S_CMP_LE_I32                0x00000005
19340#define SQ_S_CMP_EQ_U32                0x00000006
19341#define SQ_S_CMP_LG_U32                0x00000007
19342#define SQ_S_CMP_GT_U32                0x00000008
19343#define SQ_S_CMP_GE_U32                0x00000009
19344#define SQ_S_CMP_LT_U32                0x0000000a
19345#define SQ_S_CMP_LE_U32                0x0000000b
19346#define SQ_S_BITCMP0_B32               0x0000000c
19347#define SQ_S_BITCMP1_B32               0x0000000d
19348#define SQ_S_BITCMP0_B64               0x0000000e
19349#define SQ_S_BITCMP1_B64               0x0000000f
19350#define SQ_S_SETVSKIP                  0x00000010
19351#define SQ_S_SET_GPR_IDX_ON            0x00000011
19352#define SQ_S_CMP_EQ_U64                0x00000012
19353#define SQ_S_CMP_LG_U64                0x00000013
19354
19355/*
19356 * VALUE_SQ_TRAP value
19357 */
19358
19359#define SQ_TTMP0                       0x0000006c
19360#define SQ_TTMP1                       0x0000006d
19361#define SQ_TTMP2                       0x0000006e
19362#define SQ_TTMP3                       0x0000006f
19363#define SQ_TTMP4                       0x00000070
19364#define SQ_TTMP5                       0x00000071
19365#define SQ_TTMP6                       0x00000072
19366#define SQ_TTMP7                       0x00000073
19367#define SQ_TTMP8                       0x00000074
19368#define SQ_TTMP9                       0x00000075
19369#define SQ_TTMP10                      0x00000076
19370#define SQ_TTMP11                      0x00000077
19371#define SQ_TTMP12                      0x00000078
19372#define SQ_TTMP13                      0x00000079
19373#define SQ_TTMP14                      0x0000007a
19374#define SQ_TTMP15                      0x0000007b
19375
19376/*
19377 * VALUE_SQ_SRC_VGPR value
19378 */
19379
19380#define SQ_SRC_VGPR0                   0x00000100
19381
19382/*
19383 * VALUE_SQ_OP_MUBUF value
19384 */
19385
19386#define SQ_BUFFER_LOAD_FORMAT_X        0x00000000
19387#define SQ_BUFFER_LOAD_FORMAT_XY       0x00000001
19388#define SQ_BUFFER_LOAD_FORMAT_XYZ      0x00000002
19389#define SQ_BUFFER_LOAD_FORMAT_XYZW     0x00000003
19390#define SQ_BUFFER_STORE_FORMAT_X       0x00000004
19391#define SQ_BUFFER_STORE_FORMAT_XY      0x00000005
19392#define SQ_BUFFER_STORE_FORMAT_XYZ     0x00000006
19393#define SQ_BUFFER_STORE_FORMAT_XYZW    0x00000007
19394#define SQ_BUFFER_LOAD_FORMAT_D16_X    0x00000008
19395#define SQ_BUFFER_LOAD_FORMAT_D16_XY   0x00000009
19396#define SQ_BUFFER_LOAD_FORMAT_D16_XYZ  0x0000000a
19397#define SQ_BUFFER_LOAD_FORMAT_D16_XYZW 0x0000000b
19398#define SQ_BUFFER_STORE_FORMAT_D16_X   0x0000000c
19399#define SQ_BUFFER_STORE_FORMAT_D16_XY  0x0000000d
19400#define SQ_BUFFER_STORE_FORMAT_D16_XYZ 0x0000000e
19401#define SQ_BUFFER_STORE_FORMAT_D16_XYZW 0x0000000f
19402#define SQ_BUFFER_LOAD_UBYTE           0x00000010
19403#define SQ_BUFFER_LOAD_SBYTE           0x00000011
19404#define SQ_BUFFER_LOAD_USHORT          0x00000012
19405#define SQ_BUFFER_LOAD_SSHORT          0x00000013
19406#define SQ_BUFFER_LOAD_DWORD           0x00000014
19407#define SQ_BUFFER_LOAD_DWORDX2         0x00000015
19408#define SQ_BUFFER_LOAD_DWORDX3         0x00000016
19409#define SQ_BUFFER_LOAD_DWORDX4         0x00000017
19410#define SQ_BUFFER_STORE_BYTE           0x00000018
19411#define SQ_BUFFER_STORE_SHORT          0x0000001a
19412#define SQ_BUFFER_STORE_DWORD          0x0000001c
19413#define SQ_BUFFER_STORE_DWORDX2        0x0000001d
19414#define SQ_BUFFER_STORE_DWORDX3        0x0000001e
19415#define SQ_BUFFER_STORE_DWORDX4        0x0000001f
19416#define SQ_BUFFER_STORE_LDS_DWORD      0x0000003d
19417#define SQ_BUFFER_WBINVL1              0x0000003e
19418#define SQ_BUFFER_WBINVL1_VOL          0x0000003f
19419#define SQ_BUFFER_ATOMIC_SWAP          0x00000040
19420#define SQ_BUFFER_ATOMIC_CMPSWAP       0x00000041
19421#define SQ_BUFFER_ATOMIC_ADD           0x00000042
19422#define SQ_BUFFER_ATOMIC_SUB           0x00000043
19423#define SQ_BUFFER_ATOMIC_SMIN          0x00000044
19424#define SQ_BUFFER_ATOMIC_UMIN          0x00000045
19425#define SQ_BUFFER_ATOMIC_SMAX          0x00000046
19426#define SQ_BUFFER_ATOMIC_UMAX          0x00000047
19427#define SQ_BUFFER_ATOMIC_AND           0x00000048
19428#define SQ_BUFFER_ATOMIC_OR            0x00000049
19429#define SQ_BUFFER_ATOMIC_XOR           0x0000004a
19430#define SQ_BUFFER_ATOMIC_INC           0x0000004b
19431#define SQ_BUFFER_ATOMIC_DEC           0x0000004c
19432#define SQ_BUFFER_ATOMIC_SWAP_X2       0x00000060
19433#define SQ_BUFFER_ATOMIC_CMPSWAP_X2    0x00000061
19434#define SQ_BUFFER_ATOMIC_ADD_X2        0x00000062
19435#define SQ_BUFFER_ATOMIC_SUB_X2        0x00000063
19436#define SQ_BUFFER_ATOMIC_SMIN_X2       0x00000064
19437#define SQ_BUFFER_ATOMIC_UMIN_X2       0x00000065
19438#define SQ_BUFFER_ATOMIC_SMAX_X2       0x00000066
19439#define SQ_BUFFER_ATOMIC_UMAX_X2       0x00000067
19440#define SQ_BUFFER_ATOMIC_AND_X2        0x00000068
19441#define SQ_BUFFER_ATOMIC_OR_X2         0x00000069
19442#define SQ_BUFFER_ATOMIC_XOR_X2        0x0000006a
19443#define SQ_BUFFER_ATOMIC_INC_X2        0x0000006b
19444#define SQ_BUFFER_ATOMIC_DEC_X2        0x0000006c
19445
19446/*
19447 * VALUE_SQ_SDWA_SEL value
19448 */
19449
19450#define SQ_SDWA_BYTE_0                 0x00000000
19451#define SQ_SDWA_BYTE_1                 0x00000001
19452#define SQ_SDWA_BYTE_2                 0x00000002
19453#define SQ_SDWA_BYTE_3                 0x00000003
19454#define SQ_SDWA_WORD_0                 0x00000004
19455#define SQ_SDWA_WORD_1                 0x00000005
19456#define SQ_SDWA_DWORD                  0x00000006
19457
19458/*******************************************************
19459 * SX Enums
19460 *******************************************************/
19461
19462/*
19463 * SX_BLEND_OPT enum
19464 */
19465
19466typedef enum SX_BLEND_OPT {
19467BLEND_OPT_PRESERVE_NONE_IGNORE_ALL       = 0x00000000,
19468BLEND_OPT_PRESERVE_ALL_IGNORE_NONE       = 0x00000001,
19469BLEND_OPT_PRESERVE_C1_IGNORE_C0          = 0x00000002,
19470BLEND_OPT_PRESERVE_C0_IGNORE_C1          = 0x00000003,
19471BLEND_OPT_PRESERVE_A1_IGNORE_A0          = 0x00000004,
19472BLEND_OPT_PRESERVE_A0_IGNORE_A1          = 0x00000005,
19473BLEND_OPT_PRESERVE_NONE_IGNORE_A0        = 0x00000006,
19474BLEND_OPT_PRESERVE_NONE_IGNORE_NONE      = 0x00000007,
19475} SX_BLEND_OPT;
19476
19477/*
19478 * SX_OPT_COMB_FCN enum
19479 */
19480
19481typedef enum SX_OPT_COMB_FCN {
19482OPT_COMB_NONE                            = 0x00000000,
19483OPT_COMB_ADD                             = 0x00000001,
19484OPT_COMB_SUBTRACT                        = 0x00000002,
19485OPT_COMB_MIN                             = 0x00000003,
19486OPT_COMB_MAX                             = 0x00000004,
19487OPT_COMB_REVSUBTRACT                     = 0x00000005,
19488OPT_COMB_BLEND_DISABLED                  = 0x00000006,
19489OPT_COMB_SAFE_ADD                        = 0x00000007,
19490} SX_OPT_COMB_FCN;
19491
19492/*
19493 * SX_DOWNCONVERT_FORMAT enum
19494 */
19495
19496typedef enum SX_DOWNCONVERT_FORMAT {
19497SX_RT_EXPORT_NO_CONVERSION               = 0x00000000,
19498SX_RT_EXPORT_32_R                        = 0x00000001,
19499SX_RT_EXPORT_32_A                        = 0x00000002,
19500SX_RT_EXPORT_10_11_11                    = 0x00000003,
19501SX_RT_EXPORT_2_10_10_10                  = 0x00000004,
19502SX_RT_EXPORT_8_8_8_8                     = 0x00000005,
19503SX_RT_EXPORT_5_6_5                       = 0x00000006,
19504SX_RT_EXPORT_1_5_5_5                     = 0x00000007,
19505SX_RT_EXPORT_4_4_4_4                     = 0x00000008,
19506SX_RT_EXPORT_16_16_GR                    = 0x00000009,
19507SX_RT_EXPORT_16_16_AR                    = 0x0000000a,
19508} SX_DOWNCONVERT_FORMAT;
19509
19510/*
19511 * SX_PERFCOUNTER_VALS enum
19512 */
19513
19514typedef enum SX_PERFCOUNTER_VALS {
19515SX_PERF_SEL_PA_IDLE_CYCLES               = 0x00000000,
19516SX_PERF_SEL_PA_REQ                       = 0x00000001,
19517SX_PERF_SEL_PA_POS                       = 0x00000002,
19518SX_PERF_SEL_CLOCK                        = 0x00000003,
19519SX_PERF_SEL_GATE_EN1                     = 0x00000004,
19520SX_PERF_SEL_GATE_EN2                     = 0x00000005,
19521SX_PERF_SEL_GATE_EN3                     = 0x00000006,
19522SX_PERF_SEL_GATE_EN4                     = 0x00000007,
19523SX_PERF_SEL_SH_POS_STARVE                = 0x00000008,
19524SX_PERF_SEL_SH_COLOR_STARVE              = 0x00000009,
19525SX_PERF_SEL_SH_POS_STALL                 = 0x0000000a,
19526SX_PERF_SEL_SH_COLOR_STALL               = 0x0000000b,
19527SX_PERF_SEL_DB0_PIXELS                   = 0x0000000c,
19528SX_PERF_SEL_DB0_HALF_QUADS               = 0x0000000d,
19529SX_PERF_SEL_DB0_PIXEL_STALL              = 0x0000000e,
19530SX_PERF_SEL_DB0_PIXEL_IDLE               = 0x0000000f,
19531SX_PERF_SEL_DB0_PRED_PIXELS              = 0x00000010,
19532SX_PERF_SEL_DB1_PIXELS                   = 0x00000011,
19533SX_PERF_SEL_DB1_HALF_QUADS               = 0x00000012,
19534SX_PERF_SEL_DB1_PIXEL_STALL              = 0x00000013,
19535SX_PERF_SEL_DB1_PIXEL_IDLE               = 0x00000014,
19536SX_PERF_SEL_DB1_PRED_PIXELS              = 0x00000015,
19537SX_PERF_SEL_DB2_PIXELS                   = 0x00000016,
19538SX_PERF_SEL_DB2_HALF_QUADS               = 0x00000017,
19539SX_PERF_SEL_DB2_PIXEL_STALL              = 0x00000018,
19540SX_PERF_SEL_DB2_PIXEL_IDLE               = 0x00000019,
19541SX_PERF_SEL_DB2_PRED_PIXELS              = 0x0000001a,
19542SX_PERF_SEL_DB3_PIXELS                   = 0x0000001b,
19543SX_PERF_SEL_DB3_HALF_QUADS               = 0x0000001c,
19544SX_PERF_SEL_DB3_PIXEL_STALL              = 0x0000001d,
19545SX_PERF_SEL_DB3_PIXEL_IDLE               = 0x0000001e,
19546SX_PERF_SEL_DB3_PRED_PIXELS              = 0x0000001f,
19547SX_PERF_SEL_COL_BUSY                     = 0x00000020,
19548SX_PERF_SEL_POS_BUSY                     = 0x00000021,
19549SX_PERF_SEL_DB0_A2M_DISCARD_QUADS        = 0x00000022,
19550SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS        = 0x00000023,
19551SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST        = 0x00000024,
19552SX_PERF_SEL_DB0_MRT0_DISCARD_SRC         = 0x00000025,
19553SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS        = 0x00000026,
19554SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS        = 0x00000027,
19555SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS        = 0x00000028,
19556SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST        = 0x00000029,
19557SX_PERF_SEL_DB0_MRT1_DISCARD_SRC         = 0x0000002a,
19558SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS        = 0x0000002b,
19559SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS        = 0x0000002c,
19560SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS        = 0x0000002d,
19561SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST        = 0x0000002e,
19562SX_PERF_SEL_DB0_MRT2_DISCARD_SRC         = 0x0000002f,
19563SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS        = 0x00000030,
19564SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS        = 0x00000031,
19565SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS        = 0x00000032,
19566SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST        = 0x00000033,
19567SX_PERF_SEL_DB0_MRT3_DISCARD_SRC         = 0x00000034,
19568SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS        = 0x00000035,
19569SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS        = 0x00000036,
19570SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS        = 0x00000037,
19571SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST        = 0x00000038,
19572SX_PERF_SEL_DB0_MRT4_DISCARD_SRC         = 0x00000039,
19573SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS        = 0x0000003a,
19574SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS        = 0x0000003b,
19575SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS        = 0x0000003c,
19576SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST        = 0x0000003d,
19577SX_PERF_SEL_DB0_MRT5_DISCARD_SRC         = 0x0000003e,
19578SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS        = 0x0000003f,
19579SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS        = 0x00000040,
19580SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS        = 0x00000041,
19581SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST        = 0x00000042,
19582SX_PERF_SEL_DB0_MRT6_DISCARD_SRC         = 0x00000043,
19583SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS        = 0x00000044,
19584SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS        = 0x00000045,
19585SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS        = 0x00000046,
19586SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST        = 0x00000047,
19587SX_PERF_SEL_DB0_MRT7_DISCARD_SRC         = 0x00000048,
19588SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS        = 0x00000049,
19589SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS        = 0x0000004a,
19590SX_PERF_SEL_DB1_A2M_DISCARD_QUADS        = 0x0000004b,
19591SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS        = 0x0000004c,
19592SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST        = 0x0000004d,
19593SX_PERF_SEL_DB1_MRT0_DISCARD_SRC         = 0x0000004e,
19594SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS        = 0x0000004f,
19595SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS        = 0x00000050,
19596SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS        = 0x00000051,
19597SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST        = 0x00000052,
19598SX_PERF_SEL_DB1_MRT1_DISCARD_SRC         = 0x00000053,
19599SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS        = 0x00000054,
19600SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS        = 0x00000055,
19601SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS        = 0x00000056,
19602SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST        = 0x00000057,
19603SX_PERF_SEL_DB1_MRT2_DISCARD_SRC         = 0x00000058,
19604SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS        = 0x00000059,
19605SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS        = 0x0000005a,
19606SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS        = 0x0000005b,
19607SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST        = 0x0000005c,
19608SX_PERF_SEL_DB1_MRT3_DISCARD_SRC         = 0x0000005d,
19609SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS        = 0x0000005e,
19610SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS        = 0x0000005f,
19611SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS        = 0x00000060,
19612SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST        = 0x00000061,
19613SX_PERF_SEL_DB1_MRT4_DISCARD_SRC         = 0x00000062,
19614SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS        = 0x00000063,
19615SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS        = 0x00000064,
19616SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS        = 0x00000065,
19617SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST        = 0x00000066,
19618SX_PERF_SEL_DB1_MRT5_DISCARD_SRC         = 0x00000067,
19619SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS        = 0x00000068,
19620SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS        = 0x00000069,
19621SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS        = 0x0000006a,
19622SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST        = 0x0000006b,
19623SX_PERF_SEL_DB1_MRT6_DISCARD_SRC         = 0x0000006c,
19624SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS        = 0x0000006d,
19625SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS        = 0x0000006e,
19626SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS        = 0x0000006f,
19627SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST        = 0x00000070,
19628SX_PERF_SEL_DB1_MRT7_DISCARD_SRC         = 0x00000071,
19629SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS        = 0x00000072,
19630SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS        = 0x00000073,
19631SX_PERF_SEL_DB2_A2M_DISCARD_QUADS        = 0x00000074,
19632SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS        = 0x00000075,
19633SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST        = 0x00000076,
19634SX_PERF_SEL_DB2_MRT0_DISCARD_SRC         = 0x00000077,
19635SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS        = 0x00000078,
19636SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS        = 0x00000079,
19637SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS        = 0x0000007a,
19638SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST        = 0x0000007b,
19639SX_PERF_SEL_DB2_MRT1_DISCARD_SRC         = 0x0000007c,
19640SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS        = 0x0000007d,
19641SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS        = 0x0000007e,
19642SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS        = 0x0000007f,
19643SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST        = 0x00000080,
19644SX_PERF_SEL_DB2_MRT2_DISCARD_SRC         = 0x00000081,
19645SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS        = 0x00000082,
19646SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS        = 0x00000083,
19647SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS        = 0x00000084,
19648SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST        = 0x00000085,
19649SX_PERF_SEL_DB2_MRT3_DISCARD_SRC         = 0x00000086,
19650SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS        = 0x00000087,
19651SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS        = 0x00000088,
19652SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS        = 0x00000089,
19653SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST        = 0x0000008a,
19654SX_PERF_SEL_DB2_MRT4_DISCARD_SRC         = 0x0000008b,
19655SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS        = 0x0000008c,
19656SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS        = 0x0000008d,
19657SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS        = 0x0000008e,
19658SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST        = 0x0000008f,
19659SX_PERF_SEL_DB2_MRT5_DISCARD_SRC         = 0x00000090,
19660SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS        = 0x00000091,
19661SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS        = 0x00000092,
19662SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS        = 0x00000093,
19663SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST        = 0x00000094,
19664SX_PERF_SEL_DB2_MRT6_DISCARD_SRC         = 0x00000095,
19665SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS        = 0x00000096,
19666SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS        = 0x00000097,
19667SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS        = 0x00000098,
19668SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST        = 0x00000099,
19669SX_PERF_SEL_DB2_MRT7_DISCARD_SRC         = 0x0000009a,
19670SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS        = 0x0000009b,
19671SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS        = 0x0000009c,
19672SX_PERF_SEL_DB3_A2M_DISCARD_QUADS        = 0x0000009d,
19673SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS        = 0x0000009e,
19674SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST        = 0x0000009f,
19675SX_PERF_SEL_DB3_MRT0_DISCARD_SRC         = 0x000000a0,
19676SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS        = 0x000000a1,
19677SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS        = 0x000000a2,
19678SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS        = 0x000000a3,
19679SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST        = 0x000000a4,
19680SX_PERF_SEL_DB3_MRT1_DISCARD_SRC         = 0x000000a5,
19681SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS        = 0x000000a6,
19682SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS        = 0x000000a7,
19683SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS        = 0x000000a8,
19684SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST        = 0x000000a9,
19685SX_PERF_SEL_DB3_MRT2_DISCARD_SRC         = 0x000000aa,
19686SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS        = 0x000000ab,
19687SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS        = 0x000000ac,
19688SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS        = 0x000000ad,
19689SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST        = 0x000000ae,
19690SX_PERF_SEL_DB3_MRT3_DISCARD_SRC         = 0x000000af,
19691SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS        = 0x000000b0,
19692SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS        = 0x000000b1,
19693SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS        = 0x000000b2,
19694SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST        = 0x000000b3,
19695SX_PERF_SEL_DB3_MRT4_DISCARD_SRC         = 0x000000b4,
19696SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS        = 0x000000b5,
19697SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS        = 0x000000b6,
19698SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS        = 0x000000b7,
19699SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST        = 0x000000b8,
19700SX_PERF_SEL_DB3_MRT5_DISCARD_SRC         = 0x000000b9,
19701SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS        = 0x000000ba,
19702SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS        = 0x000000bb,
19703SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS        = 0x000000bc,
19704SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST        = 0x000000bd,
19705SX_PERF_SEL_DB3_MRT6_DISCARD_SRC         = 0x000000be,
19706SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS        = 0x000000bf,
19707SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS        = 0x000000c0,
19708SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS        = 0x000000c1,
19709SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST        = 0x000000c2,
19710SX_PERF_SEL_DB3_MRT7_DISCARD_SRC         = 0x000000c3,
19711SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS        = 0x000000c4,
19712SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS        = 0x000000c5,
19713} SX_PERFCOUNTER_VALS;
19714
19715/*******************************************************
19716 * DB Enums
19717 *******************************************************/
19718
19719/*
19720 * ForceControl enum
19721 */
19722
19723typedef enum ForceControl {
19724FORCE_OFF                                = 0x00000000,
19725FORCE_ENABLE                             = 0x00000001,
19726FORCE_DISABLE                            = 0x00000002,
19727FORCE_RESERVED                           = 0x00000003,
19728} ForceControl;
19729
19730/*
19731 * ZSamplePosition enum
19732 */
19733
19734typedef enum ZSamplePosition {
19735Z_SAMPLE_CENTER                          = 0x00000000,
19736Z_SAMPLE_CENTROID                        = 0x00000001,
19737} ZSamplePosition;
19738
19739/*
19740 * ZOrder enum
19741 */
19742
19743typedef enum ZOrder {
19744LATE_Z                                   = 0x00000000,
19745EARLY_Z_THEN_LATE_Z                      = 0x00000001,
19746RE_Z                                     = 0x00000002,
19747EARLY_Z_THEN_RE_Z                        = 0x00000003,
19748} ZOrder;
19749
19750/*
19751 * ZpassControl enum
19752 */
19753
19754typedef enum ZpassControl {
19755ZPASS_DISABLE                            = 0x00000000,
19756ZPASS_SAMPLES                            = 0x00000001,
19757ZPASS_PIXELS                             = 0x00000002,
19758} ZpassControl;
19759
19760/*
19761 * ZModeForce enum
19762 */
19763
19764typedef enum ZModeForce {
19765NO_FORCE                                 = 0x00000000,
19766FORCE_EARLY_Z                            = 0x00000001,
19767FORCE_LATE_Z                             = 0x00000002,
19768FORCE_RE_Z                               = 0x00000003,
19769} ZModeForce;
19770
19771/*
19772 * ZLimitSumm enum
19773 */
19774
19775typedef enum ZLimitSumm {
19776FORCE_SUMM_OFF                           = 0x00000000,
19777FORCE_SUMM_MINZ                          = 0x00000001,
19778FORCE_SUMM_MAXZ                          = 0x00000002,
19779FORCE_SUMM_BOTH                          = 0x00000003,
19780} ZLimitSumm;
19781
19782/*
19783 * CompareFrag enum
19784 */
19785
19786typedef enum CompareFrag {
19787FRAG_NEVER                               = 0x00000000,
19788FRAG_LESS                                = 0x00000001,
19789FRAG_EQUAL                               = 0x00000002,
19790FRAG_LEQUAL                              = 0x00000003,
19791FRAG_GREATER                             = 0x00000004,
19792FRAG_NOTEQUAL                            = 0x00000005,
19793FRAG_GEQUAL                              = 0x00000006,
19794FRAG_ALWAYS                              = 0x00000007,
19795} CompareFrag;
19796
19797/*
19798 * StencilOp enum
19799 */
19800
19801typedef enum StencilOp {
19802STENCIL_KEEP                             = 0x00000000,
19803STENCIL_ZERO                             = 0x00000001,
19804STENCIL_ONES                             = 0x00000002,
19805STENCIL_REPLACE_TEST                     = 0x00000003,
19806STENCIL_REPLACE_OP                       = 0x00000004,
19807STENCIL_ADD_CLAMP                        = 0x00000005,
19808STENCIL_SUB_CLAMP                        = 0x00000006,
19809STENCIL_INVERT                           = 0x00000007,
19810STENCIL_ADD_WRAP                         = 0x00000008,
19811STENCIL_SUB_WRAP                         = 0x00000009,
19812STENCIL_AND                              = 0x0000000a,
19813STENCIL_OR                               = 0x0000000b,
19814STENCIL_XOR                              = 0x0000000c,
19815STENCIL_NAND                             = 0x0000000d,
19816STENCIL_NOR                              = 0x0000000e,
19817STENCIL_XNOR                             = 0x0000000f,
19818} StencilOp;
19819
19820/*
19821 * ConservativeZExport enum
19822 */
19823
19824typedef enum ConservativeZExport {
19825EXPORT_ANY_Z                             = 0x00000000,
19826EXPORT_LESS_THAN_Z                       = 0x00000001,
19827EXPORT_GREATER_THAN_Z                    = 0x00000002,
19828EXPORT_RESERVED                          = 0x00000003,
19829} ConservativeZExport;
19830
19831/*
19832 * DbPSLControl enum
19833 */
19834
19835typedef enum DbPSLControl {
19836PSLC_AUTO                                = 0x00000000,
19837PSLC_ON_HANG_ONLY                        = 0x00000001,
19838PSLC_ASAP                                = 0x00000002,
19839PSLC_COUNTDOWN                           = 0x00000003,
19840} DbPSLControl;
19841
19842/*
19843 * DbPRTFaultBehavior enum
19844 */
19845
19846typedef enum DbPRTFaultBehavior {
19847FAULT_ZERO                               = 0x00000000,
19848FAULT_ONE                                = 0x00000001,
19849FAULT_FAIL                               = 0x00000002,
19850FAULT_PASS                               = 0x00000003,
19851} DbPRTFaultBehavior;
19852
19853/*
19854 * PerfCounter_Vals enum
19855 */
19856
19857typedef enum PerfCounter_Vals {
19858DB_PERF_SEL_SC_DB_tile_sends             = 0x00000000,
19859DB_PERF_SEL_SC_DB_tile_busy              = 0x00000001,
19860DB_PERF_SEL_SC_DB_tile_stalls            = 0x00000002,
19861DB_PERF_SEL_SC_DB_tile_events            = 0x00000003,
19862DB_PERF_SEL_SC_DB_tile_tiles             = 0x00000004,
19863DB_PERF_SEL_SC_DB_tile_covered           = 0x00000005,
19864DB_PERF_SEL_hiz_tc_read_starved          = 0x00000006,
19865DB_PERF_SEL_hiz_tc_write_stall           = 0x00000007,
19866DB_PERF_SEL_hiz_qtiles_culled            = 0x00000008,
19867DB_PERF_SEL_his_qtiles_culled            = 0x00000009,
19868DB_PERF_SEL_DB_SC_tile_sends             = 0x0000000a,
19869DB_PERF_SEL_DB_SC_tile_busy              = 0x0000000b,
19870DB_PERF_SEL_DB_SC_tile_stalls            = 0x0000000c,
19871DB_PERF_SEL_DB_SC_tile_df_stalls         = 0x0000000d,
19872DB_PERF_SEL_DB_SC_tile_tiles             = 0x0000000e,
19873DB_PERF_SEL_DB_SC_tile_culled            = 0x0000000f,
19874DB_PERF_SEL_DB_SC_tile_hier_kill         = 0x00000010,
19875DB_PERF_SEL_DB_SC_tile_fast_ops          = 0x00000011,
19876DB_PERF_SEL_DB_SC_tile_no_ops            = 0x00000012,
19877DB_PERF_SEL_DB_SC_tile_tile_rate         = 0x00000013,
19878DB_PERF_SEL_DB_SC_tile_ssaa_kill         = 0x00000014,
19879DB_PERF_SEL_DB_SC_tile_fast_z_ops        = 0x00000015,
19880DB_PERF_SEL_DB_SC_tile_fast_stencil_ops  = 0x00000016,
19881DB_PERF_SEL_SC_DB_quad_sends             = 0x00000017,
19882DB_PERF_SEL_SC_DB_quad_busy              = 0x00000018,
19883DB_PERF_SEL_SC_DB_quad_squads            = 0x00000019,
19884DB_PERF_SEL_SC_DB_quad_tiles             = 0x0000001a,
19885DB_PERF_SEL_SC_DB_quad_pixels            = 0x0000001b,
19886DB_PERF_SEL_SC_DB_quad_killed_tiles      = 0x0000001c,
19887DB_PERF_SEL_DB_SC_quad_sends             = 0x0000001d,
19888DB_PERF_SEL_DB_SC_quad_busy              = 0x0000001e,
19889DB_PERF_SEL_DB_SC_quad_stalls            = 0x0000001f,
19890DB_PERF_SEL_DB_SC_quad_tiles             = 0x00000020,
19891DB_PERF_SEL_DB_SC_quad_lit_quad          = 0x00000021,
19892DB_PERF_SEL_DB_CB_tile_sends             = 0x00000022,
19893DB_PERF_SEL_DB_CB_tile_busy              = 0x00000023,
19894DB_PERF_SEL_DB_CB_tile_stalls            = 0x00000024,
19895DB_PERF_SEL_SX_DB_quad_sends             = 0x00000025,
19896DB_PERF_SEL_SX_DB_quad_busy              = 0x00000026,
19897DB_PERF_SEL_SX_DB_quad_stalls            = 0x00000027,
19898DB_PERF_SEL_SX_DB_quad_quads             = 0x00000028,
19899DB_PERF_SEL_SX_DB_quad_pixels            = 0x00000029,
19900DB_PERF_SEL_SX_DB_quad_exports           = 0x0000002a,
19901DB_PERF_SEL_SH_quads_outstanding_sum     = 0x0000002b,
19902DB_PERF_SEL_DB_CB_lquad_sends            = 0x0000002c,
19903DB_PERF_SEL_DB_CB_lquad_busy             = 0x0000002d,
19904DB_PERF_SEL_DB_CB_lquad_stalls           = 0x0000002e,
19905DB_PERF_SEL_DB_CB_lquad_quads            = 0x0000002f,
19906DB_PERF_SEL_tile_rd_sends                = 0x00000030,
19907DB_PERF_SEL_mi_tile_rd_outstanding_sum   = 0x00000031,
19908DB_PERF_SEL_quad_rd_sends                = 0x00000032,
19909DB_PERF_SEL_quad_rd_busy                 = 0x00000033,
19910DB_PERF_SEL_quad_rd_mi_stall             = 0x00000034,
19911DB_PERF_SEL_quad_rd_rw_collision         = 0x00000035,
19912DB_PERF_SEL_quad_rd_tag_stall            = 0x00000036,
19913DB_PERF_SEL_quad_rd_32byte_reqs          = 0x00000037,
19914DB_PERF_SEL_quad_rd_panic                = 0x00000038,
19915DB_PERF_SEL_mi_quad_rd_outstanding_sum   = 0x00000039,
19916DB_PERF_SEL_quad_rdret_sends             = 0x0000003a,
19917DB_PERF_SEL_quad_rdret_busy              = 0x0000003b,
19918DB_PERF_SEL_tile_wr_sends                = 0x0000003c,
19919DB_PERF_SEL_tile_wr_acks                 = 0x0000003d,
19920DB_PERF_SEL_mi_tile_wr_outstanding_sum   = 0x0000003e,
19921DB_PERF_SEL_quad_wr_sends                = 0x0000003f,
19922DB_PERF_SEL_quad_wr_busy                 = 0x00000040,
19923DB_PERF_SEL_quad_wr_mi_stall             = 0x00000041,
19924DB_PERF_SEL_quad_wr_coherency_stall      = 0x00000042,
19925DB_PERF_SEL_quad_wr_acks                 = 0x00000043,
19926DB_PERF_SEL_mi_quad_wr_outstanding_sum   = 0x00000044,
19927DB_PERF_SEL_Tile_Cache_misses            = 0x00000045,
19928DB_PERF_SEL_Tile_Cache_hits              = 0x00000046,
19929DB_PERF_SEL_Tile_Cache_flushes           = 0x00000047,
19930DB_PERF_SEL_Tile_Cache_surface_stall     = 0x00000048,
19931DB_PERF_SEL_Tile_Cache_starves           = 0x00000049,
19932DB_PERF_SEL_Tile_Cache_mem_return_starve  = 0x0000004a,
19933DB_PERF_SEL_tcp_dispatcher_reads         = 0x0000004b,
19934DB_PERF_SEL_tcp_prefetcher_reads         = 0x0000004c,
19935DB_PERF_SEL_tcp_preloader_reads          = 0x0000004d,
19936DB_PERF_SEL_tcp_dispatcher_flushes       = 0x0000004e,
19937DB_PERF_SEL_tcp_prefetcher_flushes       = 0x0000004f,
19938DB_PERF_SEL_tcp_preloader_flushes        = 0x00000050,
19939DB_PERF_SEL_Depth_Tile_Cache_sends       = 0x00000051,
19940DB_PERF_SEL_Depth_Tile_Cache_busy        = 0x00000052,
19941DB_PERF_SEL_Depth_Tile_Cache_starves     = 0x00000053,
19942DB_PERF_SEL_Depth_Tile_Cache_dtile_locked  = 0x00000054,
19943DB_PERF_SEL_Depth_Tile_Cache_alloc_stall  = 0x00000055,
19944DB_PERF_SEL_Depth_Tile_Cache_misses      = 0x00000056,
19945DB_PERF_SEL_Depth_Tile_Cache_hits        = 0x00000057,
19946DB_PERF_SEL_Depth_Tile_Cache_flushes     = 0x00000058,
19947DB_PERF_SEL_Depth_Tile_Cache_noop_tile   = 0x00000059,
19948DB_PERF_SEL_Depth_Tile_Cache_detailed_noop  = 0x0000005a,
19949DB_PERF_SEL_Depth_Tile_Cache_event       = 0x0000005b,
19950DB_PERF_SEL_Depth_Tile_Cache_tile_frees  = 0x0000005c,
19951DB_PERF_SEL_Depth_Tile_Cache_data_frees  = 0x0000005d,
19952DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve  = 0x0000005e,
19953DB_PERF_SEL_Stencil_Cache_misses         = 0x0000005f,
19954DB_PERF_SEL_Stencil_Cache_hits           = 0x00000060,
19955DB_PERF_SEL_Stencil_Cache_flushes        = 0x00000061,
19956DB_PERF_SEL_Stencil_Cache_starves        = 0x00000062,
19957DB_PERF_SEL_Stencil_Cache_frees          = 0x00000063,
19958DB_PERF_SEL_Z_Cache_separate_Z_misses    = 0x00000064,
19959DB_PERF_SEL_Z_Cache_separate_Z_hits      = 0x00000065,
19960DB_PERF_SEL_Z_Cache_separate_Z_flushes   = 0x00000066,
19961DB_PERF_SEL_Z_Cache_separate_Z_starves   = 0x00000067,
19962DB_PERF_SEL_Z_Cache_pmask_misses         = 0x00000068,
19963DB_PERF_SEL_Z_Cache_pmask_hits           = 0x00000069,
19964DB_PERF_SEL_Z_Cache_pmask_flushes        = 0x0000006a,
19965DB_PERF_SEL_Z_Cache_pmask_starves        = 0x0000006b,
19966DB_PERF_SEL_Z_Cache_frees                = 0x0000006c,
19967DB_PERF_SEL_Plane_Cache_misses           = 0x0000006d,
19968DB_PERF_SEL_Plane_Cache_hits             = 0x0000006e,
19969DB_PERF_SEL_Plane_Cache_flushes          = 0x0000006f,
19970DB_PERF_SEL_Plane_Cache_starves          = 0x00000070,
19971DB_PERF_SEL_Plane_Cache_frees            = 0x00000071,
19972DB_PERF_SEL_flush_expanded_stencil       = 0x00000072,
19973DB_PERF_SEL_flush_compressed_stencil     = 0x00000073,
19974DB_PERF_SEL_flush_single_stencil         = 0x00000074,
19975DB_PERF_SEL_planes_flushed               = 0x00000075,
19976DB_PERF_SEL_flush_1plane                 = 0x00000076,
19977DB_PERF_SEL_flush_2plane                 = 0x00000077,
19978DB_PERF_SEL_flush_3plane                 = 0x00000078,
19979DB_PERF_SEL_flush_4plane                 = 0x00000079,
19980DB_PERF_SEL_flush_5plane                 = 0x0000007a,
19981DB_PERF_SEL_flush_6plane                 = 0x0000007b,
19982DB_PERF_SEL_flush_7plane                 = 0x0000007c,
19983DB_PERF_SEL_flush_8plane                 = 0x0000007d,
19984DB_PERF_SEL_flush_9plane                 = 0x0000007e,
19985DB_PERF_SEL_flush_10plane                = 0x0000007f,
19986DB_PERF_SEL_flush_11plane                = 0x00000080,
19987DB_PERF_SEL_flush_12plane                = 0x00000081,
19988DB_PERF_SEL_flush_13plane                = 0x00000082,
19989DB_PERF_SEL_flush_14plane                = 0x00000083,
19990DB_PERF_SEL_flush_15plane                = 0x00000084,
19991DB_PERF_SEL_flush_16plane                = 0x00000085,
19992DB_PERF_SEL_flush_expanded_z             = 0x00000086,
19993DB_PERF_SEL_earlyZ_waiting_for_postZ_done  = 0x00000087,
19994DB_PERF_SEL_reZ_waiting_for_postZ_done   = 0x00000088,
19995DB_PERF_SEL_dk_tile_sends                = 0x00000089,
19996DB_PERF_SEL_dk_tile_busy                 = 0x0000008a,
19997DB_PERF_SEL_dk_tile_quad_starves         = 0x0000008b,
19998DB_PERF_SEL_dk_tile_stalls               = 0x0000008c,
19999DB_PERF_SEL_dk_squad_sends               = 0x0000008d,
20000DB_PERF_SEL_dk_squad_busy                = 0x0000008e,

20001DB_PERF_SEL_dk_squad_stalls              = 0x0000008f,
20002DB_PERF_SEL_Op_Pipe_Busy                 = 0x00000090,
20003DB_PERF_SEL_Op_Pipe_MC_Read_stall        = 0x00000091,
20004DB_PERF_SEL_qc_busy                      = 0x00000092,
20005DB_PERF_SEL_qc_xfc                       = 0x00000093,
20006DB_PERF_SEL_qc_conflicts                 = 0x00000094,
20007DB_PERF_SEL_qc_full_stall                = 0x00000095,
20008DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ  = 0x00000096,
20009DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ  = 0x00000097,
20010DB_PERF_SEL_tsc_insert_summarize_stall   = 0x00000098,
20011DB_PERF_SEL_tl_busy                      = 0x00000099,
20012DB_PERF_SEL_tl_dtc_read_starved          = 0x0000009a,
20013DB_PERF_SEL_tl_z_fetch_stall             = 0x0000009b,
20014DB_PERF_SEL_tl_stencil_stall             = 0x0000009c,
20015DB_PERF_SEL_tl_z_decompress_stall        = 0x0000009d,
20016DB_PERF_SEL_tl_stencil_locked_stall      = 0x0000009e,
20017DB_PERF_SEL_tl_events                    = 0x0000009f,
20018DB_PERF_SEL_tl_summarize_squads          = 0x000000a0,
20019DB_PERF_SEL_tl_flush_expand_squads       = 0x000000a1,
20020DB_PERF_SEL_tl_expand_squads             = 0x000000a2,
20021DB_PERF_SEL_tl_preZ_squads               = 0x000000a3,
20022DB_PERF_SEL_tl_postZ_squads              = 0x000000a4,
20023DB_PERF_SEL_tl_preZ_noop_squads          = 0x000000a5,
20024DB_PERF_SEL_tl_postZ_noop_squads         = 0x000000a6,
20025DB_PERF_SEL_tl_tile_ops                  = 0x000000a7,
20026DB_PERF_SEL_tl_in_xfc                    = 0x000000a8,
20027DB_PERF_SEL_tl_in_single_stencil_expand_stall  = 0x000000a9,
20028DB_PERF_SEL_tl_in_fast_z_stall           = 0x000000aa,
20029DB_PERF_SEL_tl_out_xfc                   = 0x000000ab,
20030DB_PERF_SEL_tl_out_squads                = 0x000000ac,
20031DB_PERF_SEL_zf_plane_multicycle          = 0x000000ad,
20032DB_PERF_SEL_PostZ_Samples_passing_Z      = 0x000000ae,
20033DB_PERF_SEL_PostZ_Samples_failing_Z      = 0x000000af,
20034DB_PERF_SEL_PostZ_Samples_failing_S      = 0x000000b0,
20035DB_PERF_SEL_PreZ_Samples_passing_Z       = 0x000000b1,
20036DB_PERF_SEL_PreZ_Samples_failing_Z       = 0x000000b2,
20037DB_PERF_SEL_PreZ_Samples_failing_S       = 0x000000b3,
20038DB_PERF_SEL_ts_tc_update_stall           = 0x000000b4,
20039DB_PERF_SEL_sc_kick_start                = 0x000000b5,
20040DB_PERF_SEL_sc_kick_end                  = 0x000000b6,
20041DB_PERF_SEL_clock_reg_active             = 0x000000b7,
20042DB_PERF_SEL_clock_main_active            = 0x000000b8,
20043DB_PERF_SEL_clock_mem_export_active      = 0x000000b9,
20044DB_PERF_SEL_esr_ps_out_busy              = 0x000000ba,
20045DB_PERF_SEL_esr_ps_lqf_busy              = 0x000000bb,
20046DB_PERF_SEL_esr_ps_lqf_stall             = 0x000000bc,
20047DB_PERF_SEL_etr_out_send                 = 0x000000bd,
20048DB_PERF_SEL_etr_out_busy                 = 0x000000be,
20049DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall  = 0x000000bf,
20050DB_PERF_SEL_etr_out_cb_tile_stall        = 0x000000c0,
20051DB_PERF_SEL_etr_out_esr_stall            = 0x000000c1,
20052DB_PERF_SEL_esr_ps_sqq_busy              = 0x000000c2,
20053DB_PERF_SEL_esr_ps_sqq_stall             = 0x000000c3,
20054DB_PERF_SEL_esr_eot_fwd_busy             = 0x000000c4,
20055DB_PERF_SEL_esr_eot_fwd_holding_squad    = 0x000000c5,
20056DB_PERF_SEL_esr_eot_fwd_forward          = 0x000000c6,
20057DB_PERF_SEL_esr_sqq_zi_busy              = 0x000000c7,
20058DB_PERF_SEL_esr_sqq_zi_stall             = 0x000000c8,
20059DB_PERF_SEL_postzl_sq_pt_busy            = 0x000000c9,
20060DB_PERF_SEL_postzl_sq_pt_stall           = 0x000000ca,
20061DB_PERF_SEL_postzl_se_busy               = 0x000000cb,
20062DB_PERF_SEL_postzl_se_stall              = 0x000000cc,
20063DB_PERF_SEL_postzl_partial_launch        = 0x000000cd,
20064DB_PERF_SEL_postzl_full_launch           = 0x000000ce,
20065DB_PERF_SEL_postzl_partial_waiting       = 0x000000cf,
20066DB_PERF_SEL_postzl_tile_mem_stall        = 0x000000d0,
20067DB_PERF_SEL_postzl_tile_init_stall       = 0x000000d1,
20068DB_PEFF_SEL_prezl_tile_mem_stall         = 0x000000d2,
20069DB_PERF_SEL_prezl_tile_init_stall        = 0x000000d3,
20070DB_PERF_SEL_dtt_sm_clash_stall           = 0x000000d4,
20071DB_PERF_SEL_dtt_sm_slot_stall            = 0x000000d5,
20072DB_PERF_SEL_dtt_sm_miss_stall            = 0x000000d6,
20073DB_PERF_SEL_mi_rdreq_busy                = 0x000000d7,
20074DB_PERF_SEL_mi_rdreq_stall               = 0x000000d8,
20075DB_PERF_SEL_mi_wrreq_busy                = 0x000000d9,
20076DB_PERF_SEL_mi_wrreq_stall               = 0x000000da,
20077DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop  = 0x000000db,
20078DB_PERF_SEL_dkg_tile_rate_tile           = 0x000000dc,
20079DB_PERF_SEL_prezl_src_in_sends           = 0x000000dd,
20080DB_PERF_SEL_prezl_src_in_stall           = 0x000000de,
20081DB_PERF_SEL_prezl_src_in_squads          = 0x000000df,
20082DB_PERF_SEL_prezl_src_in_squads_unrolled  = 0x000000e0,
20083DB_PERF_SEL_prezl_src_in_tile_rate       = 0x000000e1,
20084DB_PERF_SEL_prezl_src_in_tile_rate_unrolled  = 0x000000e2,
20085DB_PERF_SEL_prezl_src_out_stall          = 0x000000e3,
20086DB_PERF_SEL_postzl_src_in_sends          = 0x000000e4,
20087DB_PERF_SEL_postzl_src_in_stall          = 0x000000e5,
20088DB_PERF_SEL_postzl_src_in_squads         = 0x000000e6,
20089DB_PERF_SEL_postzl_src_in_squads_unrolled  = 0x000000e7,
20090DB_PERF_SEL_postzl_src_in_tile_rate      = 0x000000e8,
20091DB_PERF_SEL_postzl_src_in_tile_rate_unrolled  = 0x000000e9,
20092DB_PERF_SEL_postzl_src_out_stall         = 0x000000ea,
20093DB_PERF_SEL_esr_ps_src_in_sends          = 0x000000eb,
20094DB_PERF_SEL_esr_ps_src_in_stall          = 0x000000ec,
20095DB_PERF_SEL_esr_ps_src_in_squads         = 0x000000ed,
20096DB_PERF_SEL_esr_ps_src_in_squads_unrolled  = 0x000000ee,
20097DB_PERF_SEL_esr_ps_src_in_tile_rate      = 0x000000ef,
20098DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled  = 0x000000f0,
20099DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate  = 0x000000f1,
20100DB_PERF_SEL_esr_ps_src_out_stall         = 0x000000f2,
20101DB_PERF_SEL_depth_bounds_qtiles_culled   = 0x000000f3,
20102DB_PERF_SEL_PreZ_Samples_failing_DB      = 0x000000f4,
20103DB_PERF_SEL_PostZ_Samples_failing_DB     = 0x000000f5,
20104DB_PERF_SEL_flush_compressed             = 0x000000f6,
20105DB_PERF_SEL_flush_plane_le4              = 0x000000f7,
20106DB_PERF_SEL_tiles_z_fully_summarized     = 0x000000f8,
20107DB_PERF_SEL_tiles_stencil_fully_summarized  = 0x000000f9,
20108DB_PERF_SEL_tiles_z_clear_on_expclear    = 0x000000fa,
20109DB_PERF_SEL_tiles_s_clear_on_expclear    = 0x000000fb,
20110DB_PERF_SEL_tiles_decomp_on_expclear     = 0x000000fc,
20111DB_PERF_SEL_tiles_compressed_to_decompressed  = 0x000000fd,
20112DB_PERF_SEL_Op_Pipe_Prez_Busy            = 0x000000fe,
20113DB_PERF_SEL_Op_Pipe_Postz_Busy           = 0x000000ff,
20114DB_PERF_SEL_di_dt_stall                  = 0x00000100,
20115DB_PERF_SEL_DB_SC_quad_double_quad       = 0x00000101,
20116DB_PERF_SEL_SX_DB_quad_export_quads      = 0x00000102,
20117DB_PERF_SEL_SX_DB_quad_double_format     = 0x00000103,
20118DB_PERF_SEL_SX_DB_quad_fast_format       = 0x00000104,
20119DB_PERF_SEL_SX_DB_quad_slow_format       = 0x00000105,
20120DB_PERF_SEL_DB_CB_lquad_export_quads     = 0x00000106,
20121DB_PERF_SEL_DB_CB_lquad_double_format    = 0x00000107,
20122DB_PERF_SEL_DB_CB_lquad_fast_format      = 0x00000108,
20123DB_PERF_SEL_DB_CB_lquad_slow_format      = 0x00000109,
20124DB_PERF_SEL_CB_DB_rdreq_sends            = 0x0000010a,
20125DB_PERF_SEL_CB_DB_rdreq_prt_sends        = 0x0000010b,
20126DB_PERF_SEL_CB_DB_wrreq_sends            = 0x0000010c,
20127DB_PERF_SEL_CB_DB_wrreq_prt_sends        = 0x0000010d,
20128DB_PERF_SEL_DB_CB_rdret_ack              = 0x0000010e,
20129DB_PERF_SEL_DB_CB_rdret_nack             = 0x0000010f,
20130DB_PERF_SEL_DB_CB_wrret_ack              = 0x00000110,
20131DB_PERF_SEL_DB_CB_wrret_nack             = 0x00000111,
20132DB_PERF_SEL_DFSM_squads_in               = 0x00000112,
20133DB_PERF_SEL_DFSM_full_cleared_squads_out  = 0x00000113,
20134DB_PERF_SEL_DFSM_quads_in                = 0x00000114,
20135DB_PERF_SEL_DFSM_fully_cleared_quads_out  = 0x00000115,
20136DB_PERF_SEL_DFSM_lit_pixels_in           = 0x00000116,
20137DB_PERF_SEL_DFSM_fully_cleared_pixels_out  = 0x00000117,
20138DB_PERF_SEL_DFSM_lit_samples_in          = 0x00000118,
20139DB_PERF_SEL_DFSM_lit_samples_out         = 0x00000119,
20140DB_PERF_SEL_DFSM_cycles_above_watermark  = 0x0000011a,
20141DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream  = 0x0000011b,
20142DB_PERF_SEL_DFSM_stalled_by_downstream   = 0x0000011c,
20143DB_PERF_SEL_DFSM_evicted_squads_above_watermark  = 0x0000011d,
20144DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow  = 0x0000011e,
20145DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO  = 0x0000011f,
20146DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark  = 0x00000120,
20147} PerfCounter_Vals;
20148
20149/*
20150 * RingCounterControl enum
20151 */
20152
20153typedef enum RingCounterControl {
20154COUNTER_RING_SPLIT                       = 0x00000000,
20155COUNTER_RING_0                           = 0x00000001,
20156COUNTER_RING_1                           = 0x00000002,
20157} RingCounterControl;
20158
20159/*
20160 * DbMemArbWatermarks enum
20161 */
20162
20163typedef enum DbMemArbWatermarks {
20164TRANSFERRED_64_BYTES                     = 0x00000000,
20165TRANSFERRED_128_BYTES                    = 0x00000001,
20166TRANSFERRED_256_BYTES                    = 0x00000002,
20167TRANSFERRED_512_BYTES                    = 0x00000003,
20168TRANSFERRED_1024_BYTES                   = 0x00000004,
20169TRANSFERRED_2048_BYTES                   = 0x00000005,
20170TRANSFERRED_4096_BYTES                   = 0x00000006,
20171TRANSFERRED_8192_BYTES                   = 0x00000007,
20172} DbMemArbWatermarks;
20173
20174/*
20175 * DFSMFlushEvents enum
20176 */
20177
20178typedef enum DFSMFlushEvents {
20179DB_FLUSH_AND_INV_DB_DATA_TS              = 0x00000000,
20180DB_FLUSH_AND_INV_DB_META                 = 0x00000001,
20181DB_CACHE_FLUSH                           = 0x00000002,
20182DB_CACHE_FLUSH_TS                        = 0x00000003,
20183DB_CACHE_FLUSH_AND_INV_EVENT             = 0x00000004,
20184DB_CACHE_FLUSH_AND_INV_TS_EVENT          = 0x00000005,
20185} DFSMFlushEvents;
20186
20187/*
20188 * PixelPipeCounterId enum
20189 */
20190
20191typedef enum PixelPipeCounterId {
20192PIXEL_PIPE_OCCLUSION_COUNT_0             = 0x00000000,
20193PIXEL_PIPE_OCCLUSION_COUNT_1             = 0x00000001,
20194PIXEL_PIPE_OCCLUSION_COUNT_2             = 0x00000002,
20195PIXEL_PIPE_OCCLUSION_COUNT_3             = 0x00000003,
20196PIXEL_PIPE_SCREEN_MIN_EXTENTS_0          = 0x00000004,
20197PIXEL_PIPE_SCREEN_MAX_EXTENTS_0          = 0x00000005,
20198PIXEL_PIPE_SCREEN_MIN_EXTENTS_1          = 0x00000006,
20199PIXEL_PIPE_SCREEN_MAX_EXTENTS_1          = 0x00000007,
20200} PixelPipeCounterId;
20201
20202/*
20203 * PixelPipeStride enum
20204 */
20205
20206typedef enum PixelPipeStride {
20207PIXEL_PIPE_STRIDE_32_BITS                = 0x00000000,
20208PIXEL_PIPE_STRIDE_64_BITS                = 0x00000001,
20209PIXEL_PIPE_STRIDE_128_BITS               = 0x00000002,
20210PIXEL_PIPE_STRIDE_256_BITS               = 0x00000003,
20211} PixelPipeStride;
20212
20213/*******************************************************
20214 * TA Enums
20215 *******************************************************/
20216
20217/*
20218 * TEX_BORDER_COLOR_TYPE enum
20219 */
20220
20221typedef enum TEX_BORDER_COLOR_TYPE {
20222TEX_BorderColor_TransparentBlack         = 0x00000000,
20223TEX_BorderColor_OpaqueBlack              = 0x00000001,
20224TEX_BorderColor_OpaqueWhite              = 0x00000002,
20225TEX_BorderColor_Register                 = 0x00000003,
20226} TEX_BORDER_COLOR_TYPE;
20227
20228/*
20229 * TEX_CHROMA_KEY enum
20230 */
20231
20232typedef enum TEX_CHROMA_KEY {
20233TEX_ChromaKey_Disabled                   = 0x00000000,
20234TEX_ChromaKey_Kill                       = 0x00000001,
20235TEX_ChromaKey_Blend                      = 0x00000002,
20236TEX_ChromaKey_RESERVED_3                 = 0x00000003,
20237} TEX_CHROMA_KEY;
20238
20239/*
20240 * TEX_CLAMP enum
20241 */
20242
20243typedef enum TEX_CLAMP {
20244TEX_Clamp_Repeat                         = 0x00000000,
20245TEX_Clamp_Mirror                         = 0x00000001,
20246TEX_Clamp_ClampToLast                    = 0x00000002,
20247TEX_Clamp_MirrorOnceToLast               = 0x00000003,
20248TEX_Clamp_ClampHalfToBorder              = 0x00000004,
20249TEX_Clamp_MirrorOnceHalfToBorder         = 0x00000005,
20250TEX_Clamp_ClampToBorder                  = 0x00000006,
20251TEX_Clamp_MirrorOnceToBorder             = 0x00000007,
20252} TEX_CLAMP;
20253
20254/*
20255 * TEX_COORD_TYPE enum
20256 */
20257
20258typedef enum TEX_COORD_TYPE {
20259TEX_CoordType_Unnormalized               = 0x00000000,
20260TEX_CoordType_Normalized                 = 0x00000001,
20261} TEX_COORD_TYPE;
20262
20263/*
20264 * TEX_DEPTH_COMPARE_FUNCTION enum
20265 */
20266
20267typedef enum TEX_DEPTH_COMPARE_FUNCTION {
20268TEX_DepthCompareFunction_Never           = 0x00000000,
20269TEX_DepthCompareFunction_Less            = 0x00000001,
20270TEX_DepthCompareFunction_Equal           = 0x00000002,
20271TEX_DepthCompareFunction_LessEqual       = 0x00000003,
20272TEX_DepthCompareFunction_Greater         = 0x00000004,
20273TEX_DepthCompareFunction_NotEqual        = 0x00000005,
20274TEX_DepthCompareFunction_GreaterEqual    = 0x00000006,
20275TEX_DepthCompareFunction_Always          = 0x00000007,
20276} TEX_DEPTH_COMPARE_FUNCTION;
20277
20278/*
20279 * TEX_DIM enum
20280 */
20281
20282typedef enum TEX_DIM {
20283TEX_Dim_1D                               = 0x00000000,
20284TEX_Dim_2D                               = 0x00000001,
20285TEX_Dim_3D                               = 0x00000002,
20286TEX_Dim_CubeMap                          = 0x00000003,
20287TEX_Dim_1DArray                          = 0x00000004,
20288TEX_Dim_2DArray                          = 0x00000005,
20289TEX_Dim_2D_MSAA                          = 0x00000006,
20290TEX_Dim_2DArray_MSAA                     = 0x00000007,
20291} TEX_DIM;
20292
20293/*
20294 * TEX_FORMAT_COMP enum
20295 */
20296
20297typedef enum TEX_FORMAT_COMP {
20298TEX_FormatComp_Unsigned                  = 0x00000000,
20299TEX_FormatComp_Signed                    = 0x00000001,
20300TEX_FormatComp_UnsignedBiased            = 0x00000002,
20301TEX_FormatComp_RESERVED_3                = 0x00000003,
20302} TEX_FORMAT_COMP;
20303
20304/*
20305 * TEX_MAX_ANISO_RATIO enum
20306 */
20307
20308typedef enum TEX_MAX_ANISO_RATIO {
20309TEX_MaxAnisoRatio_1to1                   = 0x00000000,
20310TEX_MaxAnisoRatio_2to1                   = 0x00000001,
20311TEX_MaxAnisoRatio_4to1                   = 0x00000002,
20312TEX_MaxAnisoRatio_8to1                   = 0x00000003,
20313TEX_MaxAnisoRatio_16to1                  = 0x00000004,
20314TEX_MaxAnisoRatio_RESERVED_5             = 0x00000005,
20315TEX_MaxAnisoRatio_RESERVED_6             = 0x00000006,
20316TEX_MaxAnisoRatio_RESERVED_7             = 0x00000007,
20317} TEX_MAX_ANISO_RATIO;
20318
20319/*
20320 * TEX_MIP_FILTER enum
20321 */
20322
20323typedef enum TEX_MIP_FILTER {
20324TEX_MipFilter_None                       = 0x00000000,
20325TEX_MipFilter_Point                      = 0x00000001,
20326TEX_MipFilter_Linear                     = 0x00000002,
20327TEX_MipFilter_Point_Aniso_Adj            = 0x00000003,
20328} TEX_MIP_FILTER;
20329
20330/*
20331 * TEX_REQUEST_SIZE enum
20332 */
20333
20334typedef enum TEX_REQUEST_SIZE {
20335TEX_RequestSize_32B                      = 0x00000000,
20336TEX_RequestSize_64B                      = 0x00000001,
20337TEX_RequestSize_128B                     = 0x00000002,
20338TEX_RequestSize_2X64B                    = 0x00000003,
20339} TEX_REQUEST_SIZE;
20340
20341/*
20342 * TEX_SAMPLER_TYPE enum
20343 */
20344
20345typedef enum TEX_SAMPLER_TYPE {
20346TEX_SamplerType_Invalid                  = 0x00000000,
20347TEX_SamplerType_Valid                    = 0x00000001,
20348} TEX_SAMPLER_TYPE;
20349
20350/*
20351 * TEX_XY_FILTER enum
20352 */
20353
20354typedef enum TEX_XY_FILTER {
20355TEX_XYFilter_Point                       = 0x00000000,
20356TEX_XYFilter_Linear                      = 0x00000001,
20357TEX_XYFilter_AnisoPoint                  = 0x00000002,
20358TEX_XYFilter_AnisoLinear                 = 0x00000003,
20359} TEX_XY_FILTER;
20360
20361/*
20362 * TEX_Z_FILTER enum
20363 */
20364
20365typedef enum TEX_Z_FILTER {
20366TEX_ZFilter_None                         = 0x00000000,
20367TEX_ZFilter_Point                        = 0x00000001,
20368TEX_ZFilter_Linear                       = 0x00000002,
20369TEX_ZFilter_RESERVED_3                   = 0x00000003,
20370} TEX_Z_FILTER;
20371
20372/*
20373 * VTX_CLAMP enum
20374 */
20375
20376typedef enum VTX_CLAMP {
20377VTX_Clamp_ClampToZero                    = 0x00000000,
20378VTX_Clamp_ClampToNAN                     = 0x00000001,
20379} VTX_CLAMP;
20380
20381/*
20382 * VTX_FETCH_TYPE enum
20383 */
20384
20385typedef enum VTX_FETCH_TYPE {
20386VTX_FetchType_VertexData                 = 0x00000000,
20387VTX_FetchType_InstanceData               = 0x00000001,
20388VTX_FetchType_NoIndexOffset              = 0x00000002,
20389VTX_FetchType_RESERVED_3                 = 0x00000003,
20390} VTX_FETCH_TYPE;
20391
20392/*
20393 * VTX_FORMAT_COMP_ALL enum
20394 */
20395
20396typedef enum VTX_FORMAT_COMP_ALL {
20397VTX_FormatCompAll_Unsigned               = 0x00000000,
20398VTX_FormatCompAll_Signed                 = 0x00000001,
20399} VTX_FORMAT_COMP_ALL;
20400
20401/*
20402 * VTX_MEM_REQUEST_SIZE enum
20403 */
20404
20405typedef enum VTX_MEM_REQUEST_SIZE {
20406VTX_MemRequestSize_32B                   = 0x00000000,
20407VTX_MemRequestSize_64B                   = 0x00000001,
20408} VTX_MEM_REQUEST_SIZE;
20409
20410/*
20411 * TVX_DATA_FORMAT enum
20412 */
20413
20414typedef enum TVX_DATA_FORMAT {
20415TVX_FMT_INVALID                          = 0x00000000,
20416TVX_FMT_8                                = 0x00000001,
20417TVX_FMT_4_4                              = 0x00000002,
20418TVX_FMT_3_3_2                            = 0x00000003,
20419TVX_FMT_RESERVED_4                       = 0x00000004,
20420TVX_FMT_16                               = 0x00000005,
20421TVX_FMT_16_FLOAT                         = 0x00000006,
20422TVX_FMT_8_8                              = 0x00000007,
20423TVX_FMT_5_6_5                            = 0x00000008,
20424TVX_FMT_6_5_5                            = 0x00000009,
20425TVX_FMT_1_5_5_5                          = 0x0000000a,
20426TVX_FMT_4_4_4_4                          = 0x0000000b,
20427TVX_FMT_5_5_5_1                          = 0x0000000c,
20428TVX_FMT_32                               = 0x0000000d,
20429TVX_FMT_32_FLOAT                         = 0x0000000e,
20430TVX_FMT_16_16                            = 0x0000000f,
20431TVX_FMT_16_16_FLOAT                      = 0x00000010,
20432TVX_FMT_8_24                             = 0x00000011,
20433TVX_FMT_8_24_FLOAT                       = 0x00000012,
20434TVX_FMT_24_8                             = 0x00000013,
20435TVX_FMT_24_8_FLOAT                       = 0x00000014,
20436TVX_FMT_10_11_11                         = 0x00000015,
20437TVX_FMT_10_11_11_FLOAT                   = 0x00000016,
20438TVX_FMT_11_11_10                         = 0x00000017,
20439TVX_FMT_11_11_10_FLOAT                   = 0x00000018,
20440TVX_FMT_2_10_10_10                       = 0x00000019,
20441TVX_FMT_8_8_8_8                          = 0x0000001a,
20442TVX_FMT_10_10_10_2                       = 0x0000001b,
20443TVX_FMT_X24_8_32_FLOAT                   = 0x0000001c,
20444TVX_FMT_32_32                            = 0x0000001d,
20445TVX_FMT_32_32_FLOAT                      = 0x0000001e,
20446TVX_FMT_16_16_16_16                      = 0x0000001f,
20447TVX_FMT_16_16_16_16_FLOAT                = 0x00000020,
20448TVX_FMT_RESERVED_33                      = 0x00000021,
20449TVX_FMT_32_32_32_32                      = 0x00000022,
20450TVX_FMT_32_32_32_32_FLOAT                = 0x00000023,
20451TVX_FMT_RESERVED_36                      = 0x00000024,
20452TVX_FMT_1                                = 0x00000025,
20453TVX_FMT_1_REVERSED                       = 0x00000026,
20454TVX_FMT_GB_GR                            = 0x00000027,
20455TVX_FMT_BG_RG                            = 0x00000028,
20456TVX_FMT_32_AS_8                          = 0x00000029,
20457TVX_FMT_32_AS_8_8                        = 0x0000002a,
20458TVX_FMT_5_9_9_9_SHAREDEXP                = 0x0000002b,
20459TVX_FMT_8_8_8                            = 0x0000002c,
20460TVX_FMT_16_16_16                         = 0x0000002d,
20461TVX_FMT_16_16_16_FLOAT                   = 0x0000002e,
20462TVX_FMT_32_32_32                         = 0x0000002f,
20463TVX_FMT_32_32_32_FLOAT                   = 0x00000030,
20464TVX_FMT_BC1                              = 0x00000031,
20465TVX_FMT_BC2                              = 0x00000032,
20466TVX_FMT_BC3                              = 0x00000033,
20467TVX_FMT_BC4                              = 0x00000034,
20468TVX_FMT_BC5                              = 0x00000035,
20469TVX_FMT_APC0                             = 0x00000036,
20470TVX_FMT_APC1                             = 0x00000037,
20471TVX_FMT_APC2                             = 0x00000038,
20472TVX_FMT_APC3                             = 0x00000039,
20473TVX_FMT_APC4                             = 0x0000003a,
20474TVX_FMT_APC5                             = 0x0000003b,
20475TVX_FMT_APC6                             = 0x0000003c,
20476TVX_FMT_APC7                             = 0x0000003d,
20477TVX_FMT_CTX1                             = 0x0000003e,
20478TVX_FMT_RESERVED_63                      = 0x0000003f,
20479} TVX_DATA_FORMAT;
20480
20481/*
20482 * TVX_DST_SEL enum
20483 */
20484
20485typedef enum TVX_DST_SEL {
20486TVX_DstSel_X                             = 0x00000000,
20487TVX_DstSel_Y                             = 0x00000001,
20488TVX_DstSel_Z                             = 0x00000002,
20489TVX_DstSel_W                             = 0x00000003,
20490TVX_DstSel_0f                            = 0x00000004,
20491TVX_DstSel_1f                            = 0x00000005,
20492TVX_DstSel_RESERVED_6                    = 0x00000006,
20493TVX_DstSel_Mask                          = 0x00000007,
20494} TVX_DST_SEL;
20495
20496/*
20497 * TVX_ENDIAN_SWAP enum
20498 */
20499
20500typedef enum TVX_ENDIAN_SWAP {
20501TVX_EndianSwap_None                      = 0x00000000,
20502TVX_EndianSwap_8in16                     = 0x00000001,
20503TVX_EndianSwap_8in32                     = 0x00000002,
20504TVX_EndianSwap_8in64                     = 0x00000003,
20505} TVX_ENDIAN_SWAP;
20506
20507/*
20508 * TVX_INST enum
20509 */
20510
20511typedef enum TVX_INST {
20512TVX_Inst_NormalVertexFetch               = 0x00000000,
20513TVX_Inst_SemanticVertexFetch             = 0x00000001,
20514TVX_Inst_RESERVED_2                      = 0x00000002,
20515TVX_Inst_LD                              = 0x00000003,
20516TVX_Inst_GetTextureResInfo               = 0x00000004,
20517TVX_Inst_GetNumberOfSamples              = 0x00000005,
20518TVX_Inst_GetLOD                          = 0x00000006,
20519TVX_Inst_GetGradientsH                   = 0x00000007,
20520TVX_Inst_GetGradientsV                   = 0x00000008,
20521TVX_Inst_SetTextureOffsets               = 0x00000009,
20522TVX_Inst_KeepGradients                   = 0x0000000a,
20523TVX_Inst_SetGradientsH                   = 0x0000000b,
20524TVX_Inst_SetGradientsV                   = 0x0000000c,
20525TVX_Inst_Pass                            = 0x0000000d,
20526TVX_Inst_GetBufferResInfo                = 0x0000000e,
20527TVX_Inst_RESERVED_15                     = 0x0000000f,
20528TVX_Inst_Sample                          = 0x00000010,
20529TVX_Inst_Sample_L                        = 0x00000011,
20530TVX_Inst_Sample_LB                       = 0x00000012,
20531TVX_Inst_Sample_LZ                       = 0x00000013,
20532TVX_Inst_Sample_G                        = 0x00000014,
20533TVX_Inst_Gather4                         = 0x00000015,
20534TVX_Inst_Sample_G_LB                     = 0x00000016,
20535TVX_Inst_Gather4_O                       = 0x00000017,
20536TVX_Inst_Sample_C                        = 0x00000018,
20537TVX_Inst_Sample_C_L                      = 0x00000019,
20538TVX_Inst_Sample_C_LB                     = 0x0000001a,
20539TVX_Inst_Sample_C_LZ                     = 0x0000001b,
20540TVX_Inst_Sample_C_G                      = 0x0000001c,
20541TVX_Inst_Gather4_C                       = 0x0000001d,
20542TVX_Inst_Sample_C_G_LB                   = 0x0000001e,
20543TVX_Inst_Gather4_C_O                     = 0x0000001f,
20544} TVX_INST;
20545
20546/*
20547 * TVX_NUM_FORMAT_ALL enum
20548 */
20549
20550typedef enum TVX_NUM_FORMAT_ALL {
20551TVX_NumFormatAll_Norm                    = 0x00000000,
20552TVX_NumFormatAll_Int                     = 0x00000001,
20553TVX_NumFormatAll_Scaled                  = 0x00000002,
20554TVX_NumFormatAll_RESERVED_3              = 0x00000003,
20555} TVX_NUM_FORMAT_ALL;
20556
20557/*
20558 * TVX_SRC_SEL enum
20559 */
20560
20561typedef enum TVX_SRC_SEL {
20562TVX_SrcSel_X                             = 0x00000000,
20563TVX_SrcSel_Y                             = 0x00000001,
20564TVX_SrcSel_Z                             = 0x00000002,
20565TVX_SrcSel_W                             = 0x00000003,
20566TVX_SrcSel_0f                            = 0x00000004,
20567TVX_SrcSel_1f                            = 0x00000005,
20568} TVX_SRC_SEL;
20569
20570/*
20571 * TVX_SRF_MODE_ALL enum
20572 */
20573
20574typedef enum TVX_SRF_MODE_ALL {
20575TVX_SRFModeAll_ZCMO                      = 0x00000000,
20576TVX_SRFModeAll_NZ                        = 0x00000001,
20577} TVX_SRF_MODE_ALL;
20578
20579/*
20580 * TVX_TYPE enum
20581 */
20582
20583typedef enum TVX_TYPE {
20584TVX_Type_InvalidTextureResource          = 0x00000000,
20585TVX_Type_InvalidVertexBuffer             = 0x00000001,
20586TVX_Type_ValidTextureResource            = 0x00000002,
20587TVX_Type_ValidVertexBuffer               = 0x00000003,
20588} TVX_TYPE;
20589
20590/*******************************************************
20591 * PA Enums
20592 *******************************************************/
20593
20594/*
20595 * SU_PERFCNT_SEL enum
20596 */
20597
20598typedef enum SU_PERFCNT_SEL {
20599PERF_PAPC_PASX_REQ                       = 0x00000000,
20600PERF_PAPC_PASX_DISABLE_PIPE              = 0x00000001,
20601PERF_PAPC_PASX_FIRST_VECTOR              = 0x00000002,
20602PERF_PAPC_PASX_SECOND_VECTOR             = 0x00000003,
20603PERF_PAPC_PASX_FIRST_DEAD                = 0x00000004,
20604PERF_PAPC_PASX_SECOND_DEAD               = 0x00000005,
20605PERF_PAPC_PASX_VTX_KILL_DISCARD          = 0x00000006,
20606PERF_PAPC_PASX_VTX_NAN_DISCARD           = 0x00000007,
20607PERF_PAPC_PA_INPUT_PRIM                  = 0x00000008,
20608PERF_PAPC_PA_INPUT_NULL_PRIM             = 0x00000009,
20609PERF_PAPC_PA_INPUT_EVENT_FLAG            = 0x0000000a,
20610PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT       = 0x0000000b,
20611PERF_PAPC_PA_INPUT_END_OF_PACKET         = 0x0000000c,
20612PERF_PAPC_PA_INPUT_EXTENDED_EVENT        = 0x0000000d,
20613PERF_PAPC_CLPR_CULL_PRIM                 = 0x0000000e,
20614PERF_PAPC_CLPR_VVUCP_CULL_PRIM           = 0x0000000f,
20615PERF_PAPC_CLPR_VV_CULL_PRIM              = 0x00000010,
20616PERF_PAPC_CLPR_UCP_CULL_PRIM             = 0x00000011,
20617PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM        = 0x00000012,
20618PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM         = 0x00000013,
20619PERF_PAPC_CLPR_CULL_TO_NULL_PRIM         = 0x00000014,
20620PERF_PAPC_CLPR_VVUCP_CLIP_PRIM           = 0x00000015,
20621PERF_PAPC_CLPR_VV_CLIP_PRIM              = 0x00000016,
20622PERF_PAPC_CLPR_UCP_CLIP_PRIM             = 0x00000017,
20623PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE      = 0x00000018,
20624PERF_PAPC_CLPR_CLIP_PLANE_CNT_1          = 0x00000019,
20625PERF_PAPC_CLPR_CLIP_PLANE_CNT_2          = 0x0000001a,
20626PERF_PAPC_CLPR_CLIP_PLANE_CNT_3          = 0x0000001b,
20627PERF_PAPC_CLPR_CLIP_PLANE_CNT_4          = 0x0000001c,
20628PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8        = 0x0000001d,
20629PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12       = 0x0000001e,
20630PERF_PAPC_CLPR_CLIP_PLANE_NEAR           = 0x0000001f,
20631PERF_PAPC_CLPR_CLIP_PLANE_FAR            = 0x00000020,
20632PERF_PAPC_CLPR_CLIP_PLANE_LEFT           = 0x00000021,
20633PERF_PAPC_CLPR_CLIP_PLANE_RIGHT          = 0x00000022,
20634PERF_PAPC_CLPR_CLIP_PLANE_TOP            = 0x00000023,
20635PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM         = 0x00000024,
20636PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM        = 0x00000025,
20637PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM     = 0x00000026,
20638PERF_PAPC_CLSM_NULL_PRIM                 = 0x00000027,
20639PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM      = 0x00000028,
20640PERF_PAPC_CLSM_CULL_TO_NULL_PRIM         = 0x00000029,
20641PERF_PAPC_CLSM_OUT_PRIM_CNT_1            = 0x0000002a,
20642PERF_PAPC_CLSM_OUT_PRIM_CNT_2            = 0x0000002b,
20643PERF_PAPC_CLSM_OUT_PRIM_CNT_3            = 0x0000002c,
20644PERF_PAPC_CLSM_OUT_PRIM_CNT_4            = 0x0000002d,
20645PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8          = 0x0000002e,
20646PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13         = 0x0000002f,
20647PERF_PAPC_CLIPGA_VTE_KILL_PRIM           = 0x00000030,
20648PERF_PAPC_SU_INPUT_PRIM                  = 0x00000031,
20649PERF_PAPC_SU_INPUT_CLIP_PRIM             = 0x00000032,
20650PERF_PAPC_SU_INPUT_NULL_PRIM             = 0x00000033,
20651PERF_PAPC_SU_INPUT_PRIM_DUAL             = 0x00000034,
20652PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL        = 0x00000035,
20653PERF_PAPC_SU_ZERO_AREA_CULL_PRIM         = 0x00000036,
20654PERF_PAPC_SU_BACK_FACE_CULL_PRIM         = 0x00000037,
20655PERF_PAPC_SU_FRONT_FACE_CULL_PRIM        = 0x00000038,
20656PERF_PAPC_SU_POLYMODE_FACE_CULL          = 0x00000039,
20657PERF_PAPC_SU_POLYMODE_BACK_CULL          = 0x0000003a,
20658PERF_PAPC_SU_POLYMODE_FRONT_CULL         = 0x0000003b,
20659PERF_PAPC_SU_POLYMODE_INVALID_FILL       = 0x0000003c,
20660PERF_PAPC_SU_OUTPUT_PRIM                 = 0x0000003d,
20661PERF_PAPC_SU_OUTPUT_CLIP_PRIM            = 0x0000003e,
20662PERF_PAPC_SU_OUTPUT_NULL_PRIM            = 0x0000003f,
20663PERF_PAPC_SU_OUTPUT_EVENT_FLAG           = 0x00000040,
20664PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT      = 0x00000041,
20665PERF_PAPC_SU_OUTPUT_END_OF_PACKET        = 0x00000042,
20666PERF_PAPC_SU_OUTPUT_POLYMODE_FACE        = 0x00000043,
20667PERF_PAPC_SU_OUTPUT_POLYMODE_BACK        = 0x00000044,
20668PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT       = 0x00000045,
20669PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE      = 0x00000046,
20670PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK      = 0x00000047,
20671PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT     = 0x00000048,
20672PERF_PAPC_SU_OUTPUT_PRIM_DUAL            = 0x00000049,
20673PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL       = 0x0000004a,
20674PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL        = 0x0000004b,
20675PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL   = 0x0000004c,
20676PERF_PAPC_PASX_REQ_IDLE                  = 0x0000004d,
20677PERF_PAPC_PASX_REQ_BUSY                  = 0x0000004e,
20678PERF_PAPC_PASX_REQ_STALLED               = 0x0000004f,
20679PERF_PAPC_PASX_REC_IDLE                  = 0x00000050,
20680PERF_PAPC_PASX_REC_BUSY                  = 0x00000051,
20681PERF_PAPC_PASX_REC_STARVED_SX            = 0x00000052,
20682PERF_PAPC_PASX_REC_STALLED               = 0x00000053,
20683PERF_PAPC_PASX_REC_STALLED_POS_MEM       = 0x00000054,
20684PERF_PAPC_PASX_REC_STALLED_CCGSM_IN      = 0x00000055,
20685PERF_PAPC_CCGSM_IDLE                     = 0x00000056,
20686PERF_PAPC_CCGSM_BUSY                     = 0x00000057,
20687PERF_PAPC_CCGSM_STALLED                  = 0x00000058,
20688PERF_PAPC_CLPRIM_IDLE                    = 0x00000059,
20689PERF_PAPC_CLPRIM_BUSY                    = 0x0000005a,
20690PERF_PAPC_CLPRIM_STALLED                 = 0x0000005b,
20691PERF_PAPC_CLPRIM_STARVED_CCGSM           = 0x0000005c,
20692PERF_PAPC_CLIPSM_IDLE                    = 0x0000005d,
20693PERF_PAPC_CLIPSM_BUSY                    = 0x0000005e,
20694PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH     = 0x0000005f,
20695PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ       = 0x00000060,
20696PERF_PAPC_CLIPSM_WAIT_CLIPGA             = 0x00000061,
20697PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP     = 0x00000062,
20698PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM         = 0x00000063,
20699PERF_PAPC_CLIPGA_IDLE                    = 0x00000064,
20700PERF_PAPC_CLIPGA_BUSY                    = 0x00000065,
20701PERF_PAPC_CLIPGA_STARVED_VTE_CLIP        = 0x00000066,
20702PERF_PAPC_CLIPGA_STALLED                 = 0x00000067,
20703PERF_PAPC_CLIP_IDLE                      = 0x00000068,
20704PERF_PAPC_CLIP_BUSY                      = 0x00000069,
20705PERF_PAPC_SU_IDLE                        = 0x0000006a,
20706PERF_PAPC_SU_BUSY                        = 0x0000006b,
20707PERF_PAPC_SU_STARVED_CLIP                = 0x0000006c,
20708PERF_PAPC_SU_STALLED_SC                  = 0x0000006d,
20709PERF_PAPC_CL_DYN_SCLK_VLD                = 0x0000006e,
20710PERF_PAPC_SU_DYN_SCLK_VLD                = 0x0000006f,
20711PERF_PAPC_PA_REG_SCLK_VLD                = 0x00000070,
20712PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL  = 0x00000071,
20713PERF_PAPC_PASX_SE0_REQ                   = 0x00000072,
20714PERF_PAPC_PASX_SE1_REQ                   = 0x00000073,
20715PERF_PAPC_PASX_SE0_FIRST_VECTOR          = 0x00000074,
20716PERF_PAPC_PASX_SE0_SECOND_VECTOR         = 0x00000075,
20717PERF_PAPC_PASX_SE1_FIRST_VECTOR          = 0x00000076,
20718PERF_PAPC_PASX_SE1_SECOND_VECTOR         = 0x00000077,
20719PERF_PAPC_SU_SE0_PRIM_FILTER_CULL        = 0x00000078,
20720PERF_PAPC_SU_SE1_PRIM_FILTER_CULL        = 0x00000079,
20721PERF_PAPC_SU_SE01_PRIM_FILTER_CULL       = 0x0000007a,
20722PERF_PAPC_SU_SE0_OUTPUT_PRIM             = 0x0000007b,
20723PERF_PAPC_SU_SE1_OUTPUT_PRIM             = 0x0000007c,
20724PERF_PAPC_SU_SE01_OUTPUT_PRIM            = 0x0000007d,
20725PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM        = 0x0000007e,
20726PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM        = 0x0000007f,
20727PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM       = 0x00000080,
20728PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT  = 0x00000081,
20729PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT  = 0x00000082,
20730PERF_PAPC_SU_SE0_STALLED_SC              = 0x00000083,
20731PERF_PAPC_SU_SE1_STALLED_SC              = 0x00000084,
20732PERF_PAPC_SU_SE01_STALLED_SC             = 0x00000085,
20733PERF_PAPC_CLSM_CLIPPING_PRIM             = 0x00000086,
20734PERF_PAPC_SU_CULLED_PRIM                 = 0x00000087,
20735PERF_PAPC_SU_OUTPUT_EOPG                 = 0x00000088,
20736PERF_PAPC_SU_SE2_PRIM_FILTER_CULL        = 0x00000089,
20737PERF_PAPC_SU_SE3_PRIM_FILTER_CULL        = 0x0000008a,
20738PERF_PAPC_SU_SE2_OUTPUT_PRIM             = 0x0000008b,
20739PERF_PAPC_SU_SE3_OUTPUT_PRIM             = 0x0000008c,
20740PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM        = 0x0000008d,
20741PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM        = 0x0000008e,
20742PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET    = 0x0000008f,
20743PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET    = 0x00000090,
20744PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET    = 0x00000091,
20745PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET    = 0x00000092,
20746PERF_PAPC_SU_SE0_OUTPUT_EOPG             = 0x00000093,
20747PERF_PAPC_SU_SE1_OUTPUT_EOPG             = 0x00000094,
20748PERF_PAPC_SU_SE2_OUTPUT_EOPG             = 0x00000095,
20749PERF_PAPC_SU_SE3_OUTPUT_EOPG             = 0x00000096,
20750PERF_PAPC_SU_SE2_STALLED_SC              = 0x00000097,
20751PERF_PAPC_SU_SE3_STALLED_SC              = 0x00000098,
20752} SU_PERFCNT_SEL;
20753
20754/*
20755 * SC_PERFCNT_SEL enum
20756 */
20757
20758typedef enum SC_PERFCNT_SEL {
20759SC_SRPS_WINDOW_VALID                     = 0x00000000,
20760SC_PSSW_WINDOW_VALID                     = 0x00000001,
20761SC_TPQZ_WINDOW_VALID                     = 0x00000002,
20762SC_QZQP_WINDOW_VALID                     = 0x00000003,
20763SC_TRPK_WINDOW_VALID                     = 0x00000004,
20764SC_SRPS_WINDOW_VALID_BUSY                = 0x00000005,
20765SC_PSSW_WINDOW_VALID_BUSY                = 0x00000006,
20766SC_TPQZ_WINDOW_VALID_BUSY                = 0x00000007,
20767SC_QZQP_WINDOW_VALID_BUSY                = 0x00000008,
20768SC_TRPK_WINDOW_VALID_BUSY                = 0x00000009,
20769SC_STARVED_BY_PA                         = 0x0000000a,
20770SC_STALLED_BY_PRIMFIFO                   = 0x0000000b,
20771SC_STALLED_BY_DB_TILE                    = 0x0000000c,
20772SC_STARVED_BY_DB_TILE                    = 0x0000000d,
20773SC_STALLED_BY_TILEORDERFIFO              = 0x0000000e,
20774SC_STALLED_BY_TILEFIFO                   = 0x0000000f,
20775SC_STALLED_BY_DB_QUAD                    = 0x00000010,
20776SC_STARVED_BY_DB_QUAD                    = 0x00000011,
20777SC_STALLED_BY_QUADFIFO                   = 0x00000012,
20778SC_STALLED_BY_BCI                        = 0x00000013,
20779SC_STALLED_BY_SPI                        = 0x00000014,
20780SC_SCISSOR_DISCARD                       = 0x00000015,
20781SC_BB_DISCARD                            = 0x00000016,
20782SC_SUPERTILE_COUNT                       = 0x00000017,
20783SC_SUPERTILE_PER_PRIM_H0                 = 0x00000018,
20784SC_SUPERTILE_PER_PRIM_H1                 = 0x00000019,
20785SC_SUPERTILE_PER_PRIM_H2                 = 0x0000001a,
20786SC_SUPERTILE_PER_PRIM_H3                 = 0x0000001b,
20787SC_SUPERTILE_PER_PRIM_H4                 = 0x0000001c,
20788SC_SUPERTILE_PER_PRIM_H5                 = 0x0000001d,
20789SC_SUPERTILE_PER_PRIM_H6                 = 0x0000001e,
20790SC_SUPERTILE_PER_PRIM_H7                 = 0x0000001f,
20791SC_SUPERTILE_PER_PRIM_H8                 = 0x00000020,
20792SC_SUPERTILE_PER_PRIM_H9                 = 0x00000021,
20793SC_SUPERTILE_PER_PRIM_H10                = 0x00000022,
20794SC_SUPERTILE_PER_PRIM_H11                = 0x00000023,
20795SC_SUPERTILE_PER_PRIM_H12                = 0x00000024,
20796SC_SUPERTILE_PER_PRIM_H13                = 0x00000025,
20797SC_SUPERTILE_PER_PRIM_H14                = 0x00000026,
20798SC_SUPERTILE_PER_PRIM_H15                = 0x00000027,
20799SC_SUPERTILE_PER_PRIM_H16                = 0x00000028,
20800SC_TILE_PER_PRIM_H0                      = 0x00000029,
20801SC_TILE_PER_PRIM_H1                      = 0x0000002a,
20802SC_TILE_PER_PRIM_H2                      = 0x0000002b,
20803SC_TILE_PER_PRIM_H3                      = 0x0000002c,
20804SC_TILE_PER_PRIM_H4                      = 0x0000002d,
20805SC_TILE_PER_PRIM_H5                      = 0x0000002e,
20806SC_TILE_PER_PRIM_H6                      = 0x0000002f,
20807SC_TILE_PER_PRIM_H7                      = 0x00000030,
20808SC_TILE_PER_PRIM_H8                      = 0x00000031,
20809SC_TILE_PER_PRIM_H9                      = 0x00000032,
20810SC_TILE_PER_PRIM_H10                     = 0x00000033,
20811SC_TILE_PER_PRIM_H11                     = 0x00000034,
20812SC_TILE_PER_PRIM_H12                     = 0x00000035,
20813SC_TILE_PER_PRIM_H13                     = 0x00000036,
20814SC_TILE_PER_PRIM_H14                     = 0x00000037,
20815SC_TILE_PER_PRIM_H15                     = 0x00000038,
20816SC_TILE_PER_PRIM_H16                     = 0x00000039,
20817SC_TILE_PER_SUPERTILE_H0                 = 0x0000003a,
20818SC_TILE_PER_SUPERTILE_H1                 = 0x0000003b,
20819SC_TILE_PER_SUPERTILE_H2                 = 0x0000003c,
20820SC_TILE_PER_SUPERTILE_H3                 = 0x0000003d,
20821SC_TILE_PER_SUPERTILE_H4                 = 0x0000003e,
20822SC_TILE_PER_SUPERTILE_H5                 = 0x0000003f,
20823SC_TILE_PER_SUPERTILE_H6                 = 0x00000040,
20824SC_TILE_PER_SUPERTILE_H7                 = 0x00000041,
20825SC_TILE_PER_SUPERTILE_H8                 = 0x00000042,
20826SC_TILE_PER_SUPERTILE_H9                 = 0x00000043,
20827SC_TILE_PER_SUPERTILE_H10                = 0x00000044,
20828SC_TILE_PER_SUPERTILE_H11                = 0x00000045,
20829SC_TILE_PER_SUPERTILE_H12                = 0x00000046,
20830SC_TILE_PER_SUPERTILE_H13                = 0x00000047,
20831SC_TILE_PER_SUPERTILE_H14                = 0x00000048,
20832SC_TILE_PER_SUPERTILE_H15                = 0x00000049,
20833SC_TILE_PER_SUPERTILE_H16                = 0x0000004a,
20834SC_TILE_PICKED_H1                        = 0x0000004b,
20835SC_TILE_PICKED_H2                        = 0x0000004c,
20836SC_TILE_PICKED_H3                        = 0x0000004d,
20837SC_TILE_PICKED_H4                        = 0x0000004e,
20838SC_QZ0_MULTI_GPU_TILE_DISCARD            = 0x0000004f,
20839SC_QZ1_MULTI_GPU_TILE_DISCARD            = 0x00000050,
20840SC_QZ2_MULTI_GPU_TILE_DISCARD            = 0x00000051,
20841SC_QZ3_MULTI_GPU_TILE_DISCARD            = 0x00000052,
20842SC_QZ0_TILE_COUNT                        = 0x00000053,
20843SC_QZ1_TILE_COUNT                        = 0x00000054,
20844SC_QZ2_TILE_COUNT                        = 0x00000055,
20845SC_QZ3_TILE_COUNT                        = 0x00000056,
20846SC_QZ0_TILE_COVERED_COUNT                = 0x00000057,
20847SC_QZ1_TILE_COVERED_COUNT                = 0x00000058,
20848SC_QZ2_TILE_COVERED_COUNT                = 0x00000059,
20849SC_QZ3_TILE_COVERED_COUNT                = 0x0000005a,
20850SC_QZ0_TILE_NOT_COVERED_COUNT            = 0x0000005b,
20851SC_QZ1_TILE_NOT_COVERED_COUNT            = 0x0000005c,
20852SC_QZ2_TILE_NOT_COVERED_COUNT            = 0x0000005d,
20853SC_QZ3_TILE_NOT_COVERED_COUNT            = 0x0000005e,
20854SC_QZ0_QUAD_PER_TILE_H0                  = 0x0000005f,
20855SC_QZ0_QUAD_PER_TILE_H1                  = 0x00000060,
20856SC_QZ0_QUAD_PER_TILE_H2                  = 0x00000061,
20857SC_QZ0_QUAD_PER_TILE_H3                  = 0x00000062,
20858SC_QZ0_QUAD_PER_TILE_H4                  = 0x00000063,
20859SC_QZ0_QUAD_PER_TILE_H5                  = 0x00000064,
20860SC_QZ0_QUAD_PER_TILE_H6                  = 0x00000065,
20861SC_QZ0_QUAD_PER_TILE_H7                  = 0x00000066,
20862SC_QZ0_QUAD_PER_TILE_H8                  = 0x00000067,
20863SC_QZ0_QUAD_PER_TILE_H9                  = 0x00000068,
20864SC_QZ0_QUAD_PER_TILE_H10                 = 0x00000069,
20865SC_QZ0_QUAD_PER_TILE_H11                 = 0x0000006a,
20866SC_QZ0_QUAD_PER_TILE_H12                 = 0x0000006b,
20867SC_QZ0_QUAD_PER_TILE_H13                 = 0x0000006c,
20868SC_QZ0_QUAD_PER_TILE_H14                 = 0x0000006d,
20869SC_QZ0_QUAD_PER_TILE_H15                 = 0x0000006e,
20870SC_QZ0_QUAD_PER_TILE_H16                 = 0x0000006f,
20871SC_QZ1_QUAD_PER_TILE_H0                  = 0x00000070,
20872SC_QZ1_QUAD_PER_TILE_H1                  = 0x00000071,
20873SC_QZ1_QUAD_PER_TILE_H2                  = 0x00000072,
20874SC_QZ1_QUAD_PER_TILE_H3                  = 0x00000073,
20875SC_QZ1_QUAD_PER_TILE_H4                  = 0x00000074,
20876SC_QZ1_QUAD_PER_TILE_H5                  = 0x00000075,
20877SC_QZ1_QUAD_PER_TILE_H6                  = 0x00000076,
20878SC_QZ1_QUAD_PER_TILE_H7                  = 0x00000077,
20879SC_QZ1_QUAD_PER_TILE_H8                  = 0x00000078,
20880SC_QZ1_QUAD_PER_TILE_H9                  = 0x00000079,
20881SC_QZ1_QUAD_PER_TILE_H10                 = 0x0000007a,
20882SC_QZ1_QUAD_PER_TILE_H11                 = 0x0000007b,
20883SC_QZ1_QUAD_PER_TILE_H12                 = 0x0000007c,
20884SC_QZ1_QUAD_PER_TILE_H13                 = 0x0000007d,
20885SC_QZ1_QUAD_PER_TILE_H14                 = 0x0000007e,
20886SC_QZ1_QUAD_PER_TILE_H15                 = 0x0000007f,
20887SC_QZ1_QUAD_PER_TILE_H16                 = 0x00000080,
20888SC_QZ2_QUAD_PER_TILE_H0                  = 0x00000081,
20889SC_QZ2_QUAD_PER_TILE_H1                  = 0x00000082,
20890SC_QZ2_QUAD_PER_TILE_H2                  = 0x00000083,
20891SC_QZ2_QUAD_PER_TILE_H3                  = 0x00000084,
20892SC_QZ2_QUAD_PER_TILE_H4                  = 0x00000085,
20893SC_QZ2_QUAD_PER_TILE_H5                  = 0x00000086,
20894SC_QZ2_QUAD_PER_TILE_H6                  = 0x00000087,
20895SC_QZ2_QUAD_PER_TILE_H7                  = 0x00000088,
20896SC_QZ2_QUAD_PER_TILE_H8                  = 0x00000089,
20897SC_QZ2_QUAD_PER_TILE_H9                  = 0x0000008a,
20898SC_QZ2_QUAD_PER_TILE_H10                 = 0x0000008b,
20899SC_QZ2_QUAD_PER_TILE_H11                 = 0x0000008c,
20900SC_QZ2_QUAD_PER_TILE_H12                 = 0x0000008d,
20901SC_QZ2_QUAD_PER_TILE_H13                 = 0x0000008e,
20902SC_QZ2_QUAD_PER_TILE_H14                 = 0x0000008f,
20903SC_QZ2_QUAD_PER_TILE_H15                 = 0x00000090,
20904SC_QZ2_QUAD_PER_TILE_H16                 = 0x00000091,
20905SC_QZ3_QUAD_PER_TILE_H0                  = 0x00000092,
20906SC_QZ3_QUAD_PER_TILE_H1                  = 0x00000093,
20907SC_QZ3_QUAD_PER_TILE_H2                  = 0x00000094,
20908SC_QZ3_QUAD_PER_TILE_H3                  = 0x00000095,
20909SC_QZ3_QUAD_PER_TILE_H4                  = 0x00000096,
20910SC_QZ3_QUAD_PER_TILE_H5                  = 0x00000097,
20911SC_QZ3_QUAD_PER_TILE_H6                  = 0x00000098,
20912SC_QZ3_QUAD_PER_TILE_H7                  = 0x00000099,
20913SC_QZ3_QUAD_PER_TILE_H8                  = 0x0000009a,
20914SC_QZ3_QUAD_PER_TILE_H9                  = 0x0000009b,
20915SC_QZ3_QUAD_PER_TILE_H10                 = 0x0000009c,
20916SC_QZ3_QUAD_PER_TILE_H11                 = 0x0000009d,
20917SC_QZ3_QUAD_PER_TILE_H12                 = 0x0000009e,
20918SC_QZ3_QUAD_PER_TILE_H13                 = 0x0000009f,
20919SC_QZ3_QUAD_PER_TILE_H14                 = 0x000000a0,
20920SC_QZ3_QUAD_PER_TILE_H15                 = 0x000000a1,
20921SC_QZ3_QUAD_PER_TILE_H16                 = 0x000000a2,
20922SC_QZ0_QUAD_COUNT                        = 0x000000a3,
20923SC_QZ1_QUAD_COUNT                        = 0x000000a4,
20924SC_QZ2_QUAD_COUNT                        = 0x000000a5,
20925SC_QZ3_QUAD_COUNT                        = 0x000000a6,
20926SC_P0_HIZ_TILE_COUNT                     = 0x000000a7,
20927SC_P1_HIZ_TILE_COUNT                     = 0x000000a8,
20928SC_P2_HIZ_TILE_COUNT                     = 0x000000a9,
20929SC_P3_HIZ_TILE_COUNT                     = 0x000000aa,
20930SC_P0_HIZ_QUAD_PER_TILE_H0               = 0x000000ab,
20931SC_P0_HIZ_QUAD_PER_TILE_H1               = 0x000000ac,
20932SC_P0_HIZ_QUAD_PER_TILE_H2               = 0x000000ad,
20933SC_P0_HIZ_QUAD_PER_TILE_H3               = 0x000000ae,
20934SC_P0_HIZ_QUAD_PER_TILE_H4               = 0x000000af,
20935SC_P0_HIZ_QUAD_PER_TILE_H5               = 0x000000b0,
20936SC_P0_HIZ_QUAD_PER_TILE_H6               = 0x000000b1,
20937SC_P0_HIZ_QUAD_PER_TILE_H7               = 0x000000b2,
20938SC_P0_HIZ_QUAD_PER_TILE_H8               = 0x000000b3,
20939SC_P0_HIZ_QUAD_PER_TILE_H9               = 0x000000b4,
20940SC_P0_HIZ_QUAD_PER_TILE_H10              = 0x000000b5,
20941SC_P0_HIZ_QUAD_PER_TILE_H11              = 0x000000b6,
20942SC_P0_HIZ_QUAD_PER_TILE_H12              = 0x000000b7,
20943SC_P0_HIZ_QUAD_PER_TILE_H13              = 0x000000b8,
20944SC_P0_HIZ_QUAD_PER_TILE_H14              = 0x000000b9,
20945SC_P0_HIZ_QUAD_PER_TILE_H15              = 0x000000ba,
20946SC_P0_HIZ_QUAD_PER_TILE_H16              = 0x000000bb,
20947SC_P1_HIZ_QUAD_PER_TILE_H0               = 0x000000bc,
20948SC_P1_HIZ_QUAD_PER_TILE_H1               = 0x000000bd,
20949SC_P1_HIZ_QUAD_PER_TILE_H2               = 0x000000be,
20950SC_P1_HIZ_QUAD_PER_TILE_H3               = 0x000000bf,
20951SC_P1_HIZ_QUAD_PER_TILE_H4               = 0x000000c0,
20952SC_P1_HIZ_QUAD_PER_TILE_H5               = 0x000000c1,
20953SC_P1_HIZ_QUAD_PER_TILE_H6               = 0x000000c2,
20954SC_P1_HIZ_QUAD_PER_TILE_H7               = 0x000000c3,
20955SC_P1_HIZ_QUAD_PER_TILE_H8               = 0x000000c4,
20956SC_P1_HIZ_QUAD_PER_TILE_H9               = 0x000000c5,
20957SC_P1_HIZ_QUAD_PER_TILE_H10              = 0x000000c6,
20958SC_P1_HIZ_QUAD_PER_TILE_H11              = 0x000000c7,
20959SC_P1_HIZ_QUAD_PER_TILE_H12              = 0x000000c8,
20960SC_P1_HIZ_QUAD_PER_TILE_H13              = 0x000000c9,
20961SC_P1_HIZ_QUAD_PER_TILE_H14              = 0x000000ca,
20962SC_P1_HIZ_QUAD_PER_TILE_H15              = 0x000000cb,
20963SC_P1_HIZ_QUAD_PER_TILE_H16              = 0x000000cc,
20964SC_P2_HIZ_QUAD_PER_TILE_H0               = 0x000000cd,
20965SC_P2_HIZ_QUAD_PER_TILE_H1               = 0x000000ce,
20966SC_P2_HIZ_QUAD_PER_TILE_H2               = 0x000000cf,
20967SC_P2_HIZ_QUAD_PER_TILE_H3               = 0x000000d0,
20968SC_P2_HIZ_QUAD_PER_TILE_H4               = 0x000000d1,
20969SC_P2_HIZ_QUAD_PER_TILE_H5               = 0x000000d2,
20970SC_P2_HIZ_QUAD_PER_TILE_H6               = 0x000000d3,
20971SC_P2_HIZ_QUAD_PER_TILE_H7               = 0x000000d4,
20972SC_P2_HIZ_QUAD_PER_TILE_H8               = 0x000000d5,
20973SC_P2_HIZ_QUAD_PER_TILE_H9               = 0x000000d6,
20974SC_P2_HIZ_QUAD_PER_TILE_H10              = 0x000000d7,
20975SC_P2_HIZ_QUAD_PER_TILE_H11              = 0x000000d8,
20976SC_P2_HIZ_QUAD_PER_TILE_H12              = 0x000000d9,
20977SC_P2_HIZ_QUAD_PER_TILE_H13              = 0x000000da,
20978SC_P2_HIZ_QUAD_PER_TILE_H14              = 0x000000db,
20979SC_P2_HIZ_QUAD_PER_TILE_H15              = 0x000000dc,
20980SC_P2_HIZ_QUAD_PER_TILE_H16              = 0x000000dd,
20981SC_P3_HIZ_QUAD_PER_TILE_H0               = 0x000000de,
20982SC_P3_HIZ_QUAD_PER_TILE_H1               = 0x000000df,
20983SC_P3_HIZ_QUAD_PER_TILE_H2               = 0x000000e0,
20984SC_P3_HIZ_QUAD_PER_TILE_H3               = 0x000000e1,
20985SC_P3_HIZ_QUAD_PER_TILE_H4               = 0x000000e2,
20986SC_P3_HIZ_QUAD_PER_TILE_H5               = 0x000000e3,
20987SC_P3_HIZ_QUAD_PER_TILE_H6               = 0x000000e4,
20988SC_P3_HIZ_QUAD_PER_TILE_H7               = 0x000000e5,
20989SC_P3_HIZ_QUAD_PER_TILE_H8               = 0x000000e6,
20990SC_P3_HIZ_QUAD_PER_TILE_H9               = 0x000000e7,
20991SC_P3_HIZ_QUAD_PER_TILE_H10              = 0x000000e8,
20992SC_P3_HIZ_QUAD_PER_TILE_H11              = 0x000000e9,
20993SC_P3_HIZ_QUAD_PER_TILE_H12              = 0x000000ea,
20994SC_P3_HIZ_QUAD_PER_TILE_H13              = 0x000000eb,
20995SC_P3_HIZ_QUAD_PER_TILE_H14              = 0x000000ec,
20996SC_P3_HIZ_QUAD_PER_TILE_H15              = 0x000000ed,
20997SC_P3_HIZ_QUAD_PER_TILE_H16              = 0x000000ee,
20998SC_P0_HIZ_QUAD_COUNT                     = 0x000000ef,
20999SC_P1_HIZ_QUAD_COUNT                     = 0x000000f0,
21000SC_P2_HIZ_QUAD_COUNT                     = 0x000000f1,

21001SC_P3_HIZ_QUAD_COUNT                     = 0x000000f2,
21002SC_P0_DETAIL_QUAD_COUNT                  = 0x000000f3,
21003SC_P1_DETAIL_QUAD_COUNT                  = 0x000000f4,
21004SC_P2_DETAIL_QUAD_COUNT                  = 0x000000f5,
21005SC_P3_DETAIL_QUAD_COUNT                  = 0x000000f6,
21006SC_P0_DETAIL_QUAD_WITH_1_PIX             = 0x000000f7,
21007SC_P0_DETAIL_QUAD_WITH_2_PIX             = 0x000000f8,
21008SC_P0_DETAIL_QUAD_WITH_3_PIX             = 0x000000f9,
21009SC_P0_DETAIL_QUAD_WITH_4_PIX             = 0x000000fa,
21010SC_P1_DETAIL_QUAD_WITH_1_PIX             = 0x000000fb,
21011SC_P1_DETAIL_QUAD_WITH_2_PIX             = 0x000000fc,
21012SC_P1_DETAIL_QUAD_WITH_3_PIX             = 0x000000fd,
21013SC_P1_DETAIL_QUAD_WITH_4_PIX             = 0x000000fe,
21014SC_P2_DETAIL_QUAD_WITH_1_PIX             = 0x000000ff,
21015SC_P2_DETAIL_QUAD_WITH_2_PIX             = 0x00000100,
21016SC_P2_DETAIL_QUAD_WITH_3_PIX             = 0x00000101,
21017SC_P2_DETAIL_QUAD_WITH_4_PIX             = 0x00000102,
21018SC_P3_DETAIL_QUAD_WITH_1_PIX             = 0x00000103,
21019SC_P3_DETAIL_QUAD_WITH_2_PIX             = 0x00000104,
21020SC_P3_DETAIL_QUAD_WITH_3_PIX             = 0x00000105,
21021SC_P3_DETAIL_QUAD_WITH_4_PIX             = 0x00000106,
21022SC_EARLYZ_QUAD_COUNT                     = 0x00000107,
21023SC_EARLYZ_QUAD_WITH_1_PIX                = 0x00000108,
21024SC_EARLYZ_QUAD_WITH_2_PIX                = 0x00000109,
21025SC_EARLYZ_QUAD_WITH_3_PIX                = 0x0000010a,
21026SC_EARLYZ_QUAD_WITH_4_PIX                = 0x0000010b,
21027SC_PKR_QUAD_PER_ROW_H1                   = 0x0000010c,
21028SC_PKR_QUAD_PER_ROW_H2                   = 0x0000010d,
21029SC_PKR_4X2_QUAD_SPLIT                    = 0x0000010e,
21030SC_PKR_4X2_FILL_QUAD                     = 0x0000010f,
21031SC_PKR_END_OF_VECTOR                     = 0x00000110,
21032SC_PKR_CONTROL_XFER                      = 0x00000111,
21033SC_PKR_DBHANG_FORCE_EOV                  = 0x00000112,
21034SC_REG_SCLK_BUSY                         = 0x00000113,
21035SC_GRP0_DYN_SCLK_BUSY                    = 0x00000114,
21036SC_GRP1_DYN_SCLK_BUSY                    = 0x00000115,
21037SC_GRP2_DYN_SCLK_BUSY                    = 0x00000116,
21038SC_GRP3_DYN_SCLK_BUSY                    = 0x00000117,
21039SC_GRP4_DYN_SCLK_BUSY                    = 0x00000118,
21040SC_PA0_SC_DATA_FIFO_RD                   = 0x00000119,
21041SC_PA0_SC_DATA_FIFO_WE                   = 0x0000011a,
21042SC_PA1_SC_DATA_FIFO_RD                   = 0x0000011b,
21043SC_PA1_SC_DATA_FIFO_WE                   = 0x0000011c,
21044SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES   = 0x0000011d,
21045SC_PS_ARB_XFC_ONLY_PRIM_CYCLES           = 0x0000011e,
21046SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM      = 0x0000011f,
21047SC_PS_ARB_STALLED_FROM_BELOW             = 0x00000120,
21048SC_PS_ARB_STARVED_FROM_ABOVE             = 0x00000121,
21049SC_PS_ARB_SC_BUSY                        = 0x00000122,
21050SC_PS_ARB_PA_SC_BUSY                     = 0x00000123,
21051SC_PA2_SC_DATA_FIFO_RD                   = 0x00000124,
21052SC_PA2_SC_DATA_FIFO_WE                   = 0x00000125,
21053SC_PA3_SC_DATA_FIFO_RD                   = 0x00000126,
21054SC_PA3_SC_DATA_FIFO_WE                   = 0x00000127,
21055SC_PA_SC_DEALLOC_0_0_WE                  = 0x00000128,
21056SC_PA_SC_DEALLOC_0_1_WE                  = 0x00000129,
21057SC_PA_SC_DEALLOC_1_0_WE                  = 0x0000012a,
21058SC_PA_SC_DEALLOC_1_1_WE                  = 0x0000012b,
21059SC_PA_SC_DEALLOC_2_0_WE                  = 0x0000012c,
21060SC_PA_SC_DEALLOC_2_1_WE                  = 0x0000012d,
21061SC_PA_SC_DEALLOC_3_0_WE                  = 0x0000012e,
21062SC_PA_SC_DEALLOC_3_1_WE                  = 0x0000012f,
21063SC_PA0_SC_EOP_WE                         = 0x00000130,
21064SC_PA0_SC_EOPG_WE                        = 0x00000131,
21065SC_PA0_SC_EVENT_WE                       = 0x00000132,
21066SC_PA1_SC_EOP_WE                         = 0x00000133,
21067SC_PA1_SC_EOPG_WE                        = 0x00000134,
21068SC_PA1_SC_EVENT_WE                       = 0x00000135,
21069SC_PA2_SC_EOP_WE                         = 0x00000136,
21070SC_PA2_SC_EOPG_WE                        = 0x00000137,
21071SC_PA2_SC_EVENT_WE                       = 0x00000138,
21072SC_PA3_SC_EOP_WE                         = 0x00000139,
21073SC_PA3_SC_EOPG_WE                        = 0x0000013a,
21074SC_PA3_SC_EVENT_WE                       = 0x0000013b,
21075SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO  = 0x0000013c,
21076SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH          = 0x0000013d,
21077SC_PS_ARB_NULL_PRIM_BUBBLE_POP           = 0x0000013e,
21078SC_PS_ARB_EOP_POP_SYNC_POP               = 0x0000013f,
21079SC_PS_ARB_EVENT_SYNC_POP                 = 0x00000140,
21080SC_SC_PS_ENG_MULTICYCLE_BUBBLE           = 0x00000141,
21081SC_PA0_SC_FPOV_WE                        = 0x00000142,
21082SC_PA1_SC_FPOV_WE                        = 0x00000143,
21083SC_PA2_SC_FPOV_WE                        = 0x00000144,
21084SC_PA3_SC_FPOV_WE                        = 0x00000145,
21085SC_PA0_SC_LPOV_WE                        = 0x00000146,
21086SC_PA1_SC_LPOV_WE                        = 0x00000147,
21087SC_PA2_SC_LPOV_WE                        = 0x00000148,
21088SC_PA3_SC_LPOV_WE                        = 0x00000149,
21089SC_SC_SPI_DEALLOC_0_0                    = 0x0000014a,
21090SC_SC_SPI_DEALLOC_0_1                    = 0x0000014b,
21091SC_SC_SPI_DEALLOC_0_2                    = 0x0000014c,
21092SC_SC_SPI_DEALLOC_1_0                    = 0x0000014d,
21093SC_SC_SPI_DEALLOC_1_1                    = 0x0000014e,
21094SC_SC_SPI_DEALLOC_1_2                    = 0x0000014f,
21095SC_SC_SPI_DEALLOC_2_0                    = 0x00000150,
21096SC_SC_SPI_DEALLOC_2_1                    = 0x00000151,
21097SC_SC_SPI_DEALLOC_2_2                    = 0x00000152,
21098SC_SC_SPI_DEALLOC_3_0                    = 0x00000153,
21099SC_SC_SPI_DEALLOC_3_1                    = 0x00000154,
21100SC_SC_SPI_DEALLOC_3_2                    = 0x00000155,
21101SC_SC_SPI_FPOV_0                         = 0x00000156,
21102SC_SC_SPI_FPOV_1                         = 0x00000157,
21103SC_SC_SPI_FPOV_2                         = 0x00000158,
21104SC_SC_SPI_FPOV_3                         = 0x00000159,
21105SC_SC_SPI_EVENT                          = 0x0000015a,
21106SC_PS_TS_EVENT_FIFO_PUSH                 = 0x0000015b,
21107SC_PS_TS_EVENT_FIFO_POP                  = 0x0000015c,
21108SC_PS_CTX_DONE_FIFO_PUSH                 = 0x0000015d,
21109SC_PS_CTX_DONE_FIFO_POP                  = 0x0000015e,
21110SC_MULTICYCLE_BUBBLE_FREEZE              = 0x0000015f,
21111SC_EOP_SYNC_WINDOW                       = 0x00000160,
21112SC_PA0_SC_NULL_WE                        = 0x00000161,
21113SC_PA0_SC_NULL_DEALLOC_WE                = 0x00000162,
21114SC_PA0_SC_DATA_FIFO_EOPG_RD              = 0x00000163,
21115SC_PA0_SC_DATA_FIFO_EOP_RD               = 0x00000164,
21116SC_PA0_SC_DEALLOC_0_RD                   = 0x00000165,
21117SC_PA0_SC_DEALLOC_1_RD                   = 0x00000166,
21118SC_PA1_SC_DATA_FIFO_EOPG_RD              = 0x00000167,
21119SC_PA1_SC_DATA_FIFO_EOP_RD               = 0x00000168,
21120SC_PA1_SC_DEALLOC_0_RD                   = 0x00000169,
21121SC_PA1_SC_DEALLOC_1_RD                   = 0x0000016a,
21122SC_PA1_SC_NULL_WE                        = 0x0000016b,
21123SC_PA1_SC_NULL_DEALLOC_WE                = 0x0000016c,
21124SC_PA2_SC_DATA_FIFO_EOPG_RD              = 0x0000016d,
21125SC_PA2_SC_DATA_FIFO_EOP_RD               = 0x0000016e,
21126SC_PA2_SC_DEALLOC_0_RD                   = 0x0000016f,
21127SC_PA2_SC_DEALLOC_1_RD                   = 0x00000170,
21128SC_PA2_SC_NULL_WE                        = 0x00000171,
21129SC_PA2_SC_NULL_DEALLOC_WE                = 0x00000172,
21130SC_PA3_SC_DATA_FIFO_EOPG_RD              = 0x00000173,
21131SC_PA3_SC_DATA_FIFO_EOP_RD               = 0x00000174,
21132SC_PA3_SC_DEALLOC_0_RD                   = 0x00000175,
21133SC_PA3_SC_DEALLOC_1_RD                   = 0x00000176,
21134SC_PA3_SC_NULL_WE                        = 0x00000177,
21135SC_PA3_SC_NULL_DEALLOC_WE                = 0x00000178,
21136SC_PS_PA0_SC_FIFO_EMPTY                  = 0x00000179,
21137SC_PS_PA0_SC_FIFO_FULL                   = 0x0000017a,
21138SC_PA0_PS_DATA_SEND                      = 0x0000017b,
21139SC_PS_PA1_SC_FIFO_EMPTY                  = 0x0000017c,
21140SC_PS_PA1_SC_FIFO_FULL                   = 0x0000017d,
21141SC_PA1_PS_DATA_SEND                      = 0x0000017e,
21142SC_PS_PA2_SC_FIFO_EMPTY                  = 0x0000017f,
21143SC_PS_PA2_SC_FIFO_FULL                   = 0x00000180,
21144SC_PA2_PS_DATA_SEND                      = 0x00000181,
21145SC_PS_PA3_SC_FIFO_EMPTY                  = 0x00000182,
21146SC_PS_PA3_SC_FIFO_FULL                   = 0x00000183,
21147SC_PA3_PS_DATA_SEND                      = 0x00000184,
21148SC_BUSY_PROCESSING_MULTICYCLE_PRIM       = 0x00000185,
21149SC_BUSY_CNT_NOT_ZERO                     = 0x00000186,
21150SC_BM_BUSY                               = 0x00000187,
21151SC_BACKEND_BUSY                          = 0x00000188,
21152SC_SCF_SCB_INTERFACE_BUSY                = 0x00000189,
21153SC_SCB_BUSY                              = 0x0000018a,
21154SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY  = 0x0000018b,
21155SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL  = 0x0000018c,
21156SC_PBB_BIN_HIST_NUM_PRIMS                = 0x0000018d,
21157SC_PBB_BATCH_HIST_NUM_PRIMS              = 0x0000018e,
21158SC_PBB_BIN_HIST_NUM_CONTEXTS             = 0x0000018f,
21159SC_PBB_BATCH_HIST_NUM_CONTEXTS           = 0x00000190,
21160SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES    = 0x00000191,
21161SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES  = 0x00000192,
21162SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS     = 0x00000193,
21163SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS  = 0x00000194,
21164SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM      = 0x00000195,
21165SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW    = 0x00000196,
21166SC_PBB_BUSY                              = 0x00000197,
21167SC_PBB_BUSY_AND_RTR                      = 0x00000198,
21168SC_PBB_STALLS_PA_DUE_TO_NO_TILES         = 0x00000199,
21169SC_PBB_NUM_BINS                          = 0x0000019a,
21170SC_PBB_END_OF_BIN                        = 0x0000019b,
21171SC_PBB_END_OF_BATCH                      = 0x0000019c,
21172SC_PBB_PRIMBIN_PROCESSED                 = 0x0000019d,
21173SC_PBB_PRIM_ADDED_TO_BATCH               = 0x0000019e,
21174SC_PBB_NONBINNED_PRIM                    = 0x0000019f,
21175SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB       = 0x000001a0,
21176SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB       = 0x000001a1,
21177SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION  = 0x000001a2,
21178SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW  = 0x000001a3,
21179SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN  = 0x000001a4,
21180SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE  = 0x000001a5,
21181SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE  = 0x000001a6,
21182SC_PBB_BATCH_BREAK_DUE_TO_PRIM           = 0x000001a7,
21183SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE     = 0x000001a8,
21184SC_PBB_BATCH_BREAK_DUE_TO_EVENT          = 0x000001a9,
21185SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT     = 0x000001aa,
21186SC_POPS_INTRA_WAVE_OVERLAPS              = 0x000001ab,
21187SC_POPS_FORCE_EOV                        = 0x000001ac,
21188SC_PKR_QUAD_OVERLAP_NOT_FOUND_IN_WAVE_TABLE  = 0x000001ad,
21189SC_PKR_QUAD_OVERLAP_FOUND_IN_WAVE_TABLE  = 0x000001ae,
21190} SC_PERFCNT_SEL;
21191
21192/*
21193 * SePairXsel enum
21194 */
21195
21196typedef enum SePairXsel {
21197RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE   = 0x00000000,
21198RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE  = 0x00000001,
21199RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE  = 0x00000002,
21200RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE  = 0x00000003,
21201RASTER_CONFIG_SE_PAIR_XSEL_128_WIDE_TILE  = 0x00000004,
21202} SePairXsel;
21203
21204/*
21205 * SePairYsel enum
21206 */
21207
21208typedef enum SePairYsel {
21209RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE   = 0x00000000,
21210RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE  = 0x00000001,
21211RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE  = 0x00000002,
21212RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE  = 0x00000003,
21213RASTER_CONFIG_SE_PAIR_YSEL_128_WIDE_TILE  = 0x00000004,
21214} SePairYsel;
21215
21216/*
21217 * SePairMap enum
21218 */
21219
21220typedef enum SePairMap {
21221RASTER_CONFIG_SE_PAIR_MAP_0              = 0x00000000,
21222RASTER_CONFIG_SE_PAIR_MAP_1              = 0x00000001,
21223RASTER_CONFIG_SE_PAIR_MAP_2              = 0x00000002,
21224RASTER_CONFIG_SE_PAIR_MAP_3              = 0x00000003,
21225} SePairMap;
21226
21227/*
21228 * SeXsel enum
21229 */
21230
21231typedef enum SeXsel {
21232RASTER_CONFIG_SE_XSEL_8_WIDE_TILE        = 0x00000000,
21233RASTER_CONFIG_SE_XSEL_16_WIDE_TILE       = 0x00000001,
21234RASTER_CONFIG_SE_XSEL_32_WIDE_TILE       = 0x00000002,
21235RASTER_CONFIG_SE_XSEL_64_WIDE_TILE       = 0x00000003,
21236RASTER_CONFIG_SE_XSEL_128_WIDE_TILE      = 0x00000004,
21237} SeXsel;
21238
21239/*
21240 * SeYsel enum
21241 */
21242
21243typedef enum SeYsel {
21244RASTER_CONFIG_SE_YSEL_8_WIDE_TILE        = 0x00000000,
21245RASTER_CONFIG_SE_YSEL_16_WIDE_TILE       = 0x00000001,
21246RASTER_CONFIG_SE_YSEL_32_WIDE_TILE       = 0x00000002,
21247RASTER_CONFIG_SE_YSEL_64_WIDE_TILE       = 0x00000003,
21248RASTER_CONFIG_SE_YSEL_128_WIDE_TILE      = 0x00000004,
21249} SeYsel;
21250
21251/*
21252 * SeMap enum
21253 */
21254
21255typedef enum SeMap {
21256RASTER_CONFIG_SE_MAP_0                   = 0x00000000,
21257RASTER_CONFIG_SE_MAP_1                   = 0x00000001,
21258RASTER_CONFIG_SE_MAP_2                   = 0x00000002,
21259RASTER_CONFIG_SE_MAP_3                   = 0x00000003,
21260} SeMap;
21261
21262/*
21263 * ScXsel enum
21264 */
21265
21266typedef enum ScXsel {
21267RASTER_CONFIG_SC_XSEL_8_WIDE_TILE        = 0x00000000,
21268RASTER_CONFIG_SC_XSEL_16_WIDE_TILE       = 0x00000001,
21269RASTER_CONFIG_SC_XSEL_32_WIDE_TILE       = 0x00000002,
21270RASTER_CONFIG_SC_XSEL_64_WIDE_TILE       = 0x00000003,
21271} ScXsel;
21272
21273/*
21274 * ScYsel enum
21275 */
21276
21277typedef enum ScYsel {
21278RASTER_CONFIG_SC_YSEL_8_WIDE_TILE        = 0x00000000,
21279RASTER_CONFIG_SC_YSEL_16_WIDE_TILE       = 0x00000001,
21280RASTER_CONFIG_SC_YSEL_32_WIDE_TILE       = 0x00000002,
21281RASTER_CONFIG_SC_YSEL_64_WIDE_TILE       = 0x00000003,
21282} ScYsel;
21283
21284/*
21285 * ScMap enum
21286 */
21287
21288typedef enum ScMap {
21289RASTER_CONFIG_SC_MAP_0                   = 0x00000000,
21290RASTER_CONFIG_SC_MAP_1                   = 0x00000001,
21291RASTER_CONFIG_SC_MAP_2                   = 0x00000002,
21292RASTER_CONFIG_SC_MAP_3                   = 0x00000003,
21293} ScMap;
21294
21295/*
21296 * PkrXsel2 enum
21297 */
21298
21299typedef enum PkrXsel2 {
21300RASTER_CONFIG_PKR_XSEL2_0                = 0x00000000,
21301RASTER_CONFIG_PKR_XSEL2_1                = 0x00000001,
21302RASTER_CONFIG_PKR_XSEL2_2                = 0x00000002,
21303RASTER_CONFIG_PKR_XSEL2_3                = 0x00000003,
21304} PkrXsel2;
21305
21306/*
21307 * PkrXsel enum
21308 */
21309
21310typedef enum PkrXsel {
21311RASTER_CONFIG_PKR_XSEL_0                 = 0x00000000,
21312RASTER_CONFIG_PKR_XSEL_1                 = 0x00000001,
21313RASTER_CONFIG_PKR_XSEL_2                 = 0x00000002,
21314RASTER_CONFIG_PKR_XSEL_3                 = 0x00000003,
21315} PkrXsel;
21316
21317/*
21318 * PkrYsel enum
21319 */
21320
21321typedef enum PkrYsel {
21322RASTER_CONFIG_PKR_YSEL_0                 = 0x00000000,
21323RASTER_CONFIG_PKR_YSEL_1                 = 0x00000001,
21324RASTER_CONFIG_PKR_YSEL_2                 = 0x00000002,
21325RASTER_CONFIG_PKR_YSEL_3                 = 0x00000003,
21326} PkrYsel;
21327
21328/*
21329 * PkrMap enum
21330 */
21331
21332typedef enum PkrMap {
21333RASTER_CONFIG_PKR_MAP_0                  = 0x00000000,
21334RASTER_CONFIG_PKR_MAP_1                  = 0x00000001,
21335RASTER_CONFIG_PKR_MAP_2                  = 0x00000002,
21336RASTER_CONFIG_PKR_MAP_3                  = 0x00000003,
21337} PkrMap;
21338
21339/*
21340 * RbXsel enum
21341 */
21342
21343typedef enum RbXsel {
21344RASTER_CONFIG_RB_XSEL_0                  = 0x00000000,
21345RASTER_CONFIG_RB_XSEL_1                  = 0x00000001,
21346} RbXsel;
21347
21348/*
21349 * RbYsel enum
21350 */
21351
21352typedef enum RbYsel {
21353RASTER_CONFIG_RB_YSEL_0                  = 0x00000000,
21354RASTER_CONFIG_RB_YSEL_1                  = 0x00000001,
21355} RbYsel;
21356
21357/*
21358 * RbXsel2 enum
21359 */
21360
21361typedef enum RbXsel2 {
21362RASTER_CONFIG_RB_XSEL2_0                 = 0x00000000,
21363RASTER_CONFIG_RB_XSEL2_1                 = 0x00000001,
21364RASTER_CONFIG_RB_XSEL2_2                 = 0x00000002,
21365RASTER_CONFIG_RB_XSEL2_3                 = 0x00000003,
21366} RbXsel2;
21367
21368/*
21369 * RbMap enum
21370 */
21371
21372typedef enum RbMap {
21373RASTER_CONFIG_RB_MAP_0                   = 0x00000000,
21374RASTER_CONFIG_RB_MAP_1                   = 0x00000001,
21375RASTER_CONFIG_RB_MAP_2                   = 0x00000002,
21376RASTER_CONFIG_RB_MAP_3                   = 0x00000003,
21377} RbMap;
21378
21379/*
21380 * BinningMode enum
21381 */
21382
21383typedef enum BinningMode {
21384BINNING_ALLOWED                          = 0x00000000,
21385FORCE_BINNING_ON                         = 0x00000001,
21386DISABLE_BINNING_USE_NEW_SC               = 0x00000002,
21387DISABLE_BINNING_USE_LEGACY_SC            = 0x00000003,
21388} BinningMode;
21389
21390/*
21391 * BinEventCntl enum
21392 */
21393
21394typedef enum BinEventCntl {
21395BINNER_BREAK_BATCH                       = 0x00000000,
21396BINNER_PIPELINE                          = 0x00000001,
21397BINNER_DROP_ASSERT                       = 0x00000002,
21398} BinEventCntl;
21399
21400/*
21401 * CovToShaderSel enum
21402 */
21403
21404typedef enum CovToShaderSel {
21405INPUT_COVERAGE                           = 0x00000000,
21406INPUT_INNER_COVERAGE                     = 0x00000001,
21407INPUT_DEPTH_COVERAGE                     = 0x00000002,
21408RAW                                      = 0x00000003,
21409} CovToShaderSel;
21410
21411/*******************************************************
21412 * RMI Enums
21413 *******************************************************/
21414
21415/*
21416 * RMIPerfSel enum
21417 */
21418
21419typedef enum RMIPerfSel {
21420RMI_PERF_SEL_NONE                        = 0x00000000,
21421RMI_PERF_SEL_BUSY                        = 0x00000001,
21422RMI_PERF_SEL_REG_CLK_VLD                 = 0x00000002,
21423RMI_PERF_SEL_DYN_CLK_CMN_VLD             = 0x00000003,
21424RMI_PERF_SEL_DYN_CLK_RB_VLD              = 0x00000004,
21425RMI_PERF_SEL_DYN_CLK_PERF_VLD            = 0x00000005,
21426RMI_PERF_SEL_PERF_WINDOW                 = 0x00000006,
21427RMI_PERF_SEL_EVENT_SEND                  = 0x00000007,
21428RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0 = 0x00000008,
21429RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1 = 0x00000009,
21430RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2 = 0x0000000a,
21431RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3 = 0x0000000b,
21432RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4 = 0x0000000c,
21433RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5 = 0x0000000d,
21434RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6 = 0x0000000e,
21435RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7 = 0x0000000f,
21436RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8 = 0x00000010,
21437RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9 = 0x00000011,
21438RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10 = 0x00000012,
21439RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11 = 0x00000013,
21440RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12 = 0x00000014,
21441RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13 = 0x00000015,
21442RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14 = 0x00000016,
21443RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15 = 0x00000017,
21444RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL = 0x00000018,
21445RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0 = 0x00000019,
21446RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1 = 0x0000001a,
21447RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2 = 0x0000001b,
21448RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3 = 0x0000001c,
21449RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4 = 0x0000001d,
21450RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5 = 0x0000001e,
21451RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6 = 0x0000001f,
21452RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7 = 0x00000020,
21453RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8 = 0x00000021,
21454RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9 = 0x00000022,
21455RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10 = 0x00000023,
21456RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11 = 0x00000024,
21457RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12 = 0x00000025,
21458RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13 = 0x00000026,
21459RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14 = 0x00000027,
21460RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15 = 0x00000028,
21461RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL = 0x00000029,
21462RMI_PERF_SEL_UTCL1_TRANSLATION_MISS      = 0x0000002a,
21463RMI_PERF_SEL_UTCL1_PERMISSION_MISS       = 0x0000002b,
21464RMI_PERF_SEL_UTCL1_REQUEST               = 0x0000002c,
21465RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX    = 0x0000002d,
21466RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT    = 0x0000002e,
21467RMI_PERF_SEL_UTCL1_LFIFO_FULL            = 0x0000002f,
21468RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES   = 0x00000030,
21469RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS  = 0x00000031,
21470RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL   = 0x00000032,
21471RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL         = 0x00000033,
21472RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS      = 0x00000034,
21473RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID        = 0x00000035,
21474RMI_PERF_SEL_RB_RMI_WRREQ_BUSY           = 0x00000036,
21475RMI_PERF_SEL_RB_RMI_WRREQ_CID0           = 0x00000037,
21476RMI_PERF_SEL_RB_RMI_WRREQ_CID1           = 0x00000038,
21477RMI_PERF_SEL_RB_RMI_WRREQ_CID2           = 0x00000039,
21478RMI_PERF_SEL_RB_RMI_WRREQ_CID3           = 0x0000003a,
21479RMI_PERF_SEL_RB_RMI_WRREQ_CID4           = 0x0000003b,
21480RMI_PERF_SEL_RB_RMI_WRREQ_CID5           = 0x0000003c,
21481RMI_PERF_SEL_RB_RMI_WRREQ_CID6           = 0x0000003d,
21482RMI_PERF_SEL_RB_RMI_WRREQ_CID7           = 0x0000003e,
21483RMI_PERF_SEL_RB_RMI_WRREQ_INFLIGHT_ALL_ORONE_CID = 0x0000003f,
21484RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID = 0x00000040,
21485RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID = 0x00000041,
21486RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY      = 0x00000042,
21487RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID  = 0x00000043,
21488RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0     = 0x00000044,
21489RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1     = 0x00000045,
21490RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2     = 0x00000046,
21491RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3     = 0x00000047,
21492RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4     = 0x00000048,
21493RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5     = 0x00000049,
21494RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6     = 0x0000004a,
21495RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7     = 0x0000004b,
21496RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0    = 0x0000004c,
21497RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1    = 0x0000004d,
21498RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2    = 0x0000004e,
21499RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3    = 0x0000004f,
21500RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID     = 0x00000050,
21501RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID        = 0x00000051,
21502RMI_PERF_SEL_RB_RMI_RDREQ_BUSY           = 0x00000052,
21503RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0        = 0x00000053,
21504RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1        = 0x00000054,
21505RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2        = 0x00000055,
21506RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3        = 0x00000056,
21507RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4        = 0x00000057,
21508RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5        = 0x00000058,
21509RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6        = 0x00000059,
21510RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7        = 0x0000005a,
21511RMI_PERF_SEL_RB_RMI_RDREQ_CID0           = 0x0000005b,
21512RMI_PERF_SEL_RB_RMI_RDREQ_CID1           = 0x0000005c,
21513RMI_PERF_SEL_RB_RMI_RDREQ_CID2           = 0x0000005d,
21514RMI_PERF_SEL_RB_RMI_RDREQ_CID3           = 0x0000005e,
21515RMI_PERF_SEL_RB_RMI_RDREQ_CID4           = 0x0000005f,
21516RMI_PERF_SEL_RB_RMI_RDREQ_CID5           = 0x00000060,
21517RMI_PERF_SEL_RB_RMI_RDREQ_CID6           = 0x00000061,
21518RMI_PERF_SEL_RB_RMI_RDREQ_CID7           = 0x00000062,
21519RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID = 0x00000063,
21520RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID = 0x00000064,
21521RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID = 0x00000065,
21522RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY      = 0x00000066,
21523RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID = 0x00000067,
21524RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0  = 0x00000068,
21525RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1  = 0x00000069,
21526RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2  = 0x0000006a,
21527RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3  = 0x0000006b,
21528RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4  = 0x0000006c,
21529RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5  = 0x0000006d,
21530RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6  = 0x0000006e,
21531RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7  = 0x0000006f,
21532RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0 = 0x00000070,
21533RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1 = 0x00000071,
21534RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2 = 0x00000072,
21535RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3 = 0x00000073,
21536RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID        = 0x00000074,
21537RMI_PERF_SEL_RMI_TC_REQ_BUSY             = 0x00000075,
21538RMI_PERF_SEL_RMI_TC_WRREQ_CID0           = 0x00000076,
21539RMI_PERF_SEL_RMI_TC_WRREQ_CID1           = 0x00000077,
21540RMI_PERF_SEL_RMI_TC_WRREQ_CID2           = 0x00000078,
21541RMI_PERF_SEL_RMI_TC_WRREQ_CID3           = 0x00000079,
21542RMI_PERF_SEL_RMI_TC_WRREQ_CID4           = 0x0000007a,
21543RMI_PERF_SEL_RMI_TC_WRREQ_CID5           = 0x0000007b,
21544RMI_PERF_SEL_RMI_TC_WRREQ_CID6           = 0x0000007c,
21545RMI_PERF_SEL_RMI_TC_WRREQ_CID7           = 0x0000007d,
21546RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID = 0x0000007e,
21547RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID  = 0x0000007f,
21548RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID        = 0x00000080,
21549RMI_PERF_SEL_RMI_TC_RDREQ_CID0           = 0x00000081,
21550RMI_PERF_SEL_RMI_TC_RDREQ_CID1           = 0x00000082,
21551RMI_PERF_SEL_RMI_TC_RDREQ_CID2           = 0x00000083,
21552RMI_PERF_SEL_RMI_TC_RDREQ_CID3           = 0x00000084,
21553RMI_PERF_SEL_RMI_TC_RDREQ_CID4           = 0x00000085,
21554RMI_PERF_SEL_RMI_TC_RDREQ_CID5           = 0x00000086,
21555RMI_PERF_SEL_RMI_TC_RDREQ_CID6           = 0x00000087,
21556RMI_PERF_SEL_RMI_TC_RDREQ_CID7           = 0x00000088,
21557RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID = 0x00000089,
21558RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID  = 0x0000008a,
21559RMI_PERF_SEL_UTCL1_BUSY                  = 0x0000008b,
21560RMI_PERF_SEL_RMI_UTC_REQ                 = 0x0000008c,
21561RMI_PERF_SEL_RMI_UTC_BUSY                = 0x0000008d,
21562RMI_PERF_SEL_UTCL1_UTCL2_REQ             = 0x0000008e,
21563RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY     = 0x0000008f,
21564RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT       = 0x00000090,
21565RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT       = 0x00000091,
21566RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT = 0x00000092,
21567RMI_PERF_SEL_XNACK_FIFO_NUM_USED         = 0x00000093,
21568RMI_PERF_SEL_LAT_FIFO_NUM_USED           = 0x00000094,
21569RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ       = 0x00000095,
21570RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ    = 0x00000096,
21571RMI_PERF_SEL_XNACK_FIFO_FULL             = 0x00000097,
21572RMI_PERF_SEL_XNACK_FIFO_BUSY             = 0x00000098,
21573RMI_PERF_SEL_LAT_FIFO_FULL               = 0x00000099,
21574RMI_PERF_SEL_SKID_FIFO_DEPTH             = 0x0000009a,
21575RMI_PERF_SEL_TCIW_INFLIGHT_COUNT         = 0x0000009b,
21576RMI_PERF_SEL_PRT_FIFO_NUM_USED           = 0x0000009c,
21577RMI_PERF_SEL_PRT_FIFO_REQ                = 0x0000009d,
21578RMI_PERF_SEL_PRT_FIFO_BUSY               = 0x0000009e,
21579RMI_PERF_SEL_TCIW_REQ                    = 0x0000009f,
21580RMI_PERF_SEL_TCIW_BUSY                   = 0x000000a0,
21581RMI_PERF_SEL_SKID_FIFO_REQ               = 0x000000a1,
21582RMI_PERF_SEL_SKID_FIFO_BUSY              = 0x000000a2,
21583RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0  = 0x000000a3,
21584RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1  = 0x000000a4,
21585RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2  = 0x000000a5,
21586RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3  = 0x000000a6,
21587RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR       = 0x000000a7,
21588RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR      = 0x000000a8,
21589RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB      = 0x000000a9,
21590RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB     = 0x000000aa,
21591RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR = 0x000000ab,
21592RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR = 0x000000ac,
21593RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB = 0x000000ad,
21594RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB = 0x000000ae,
21595RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR = 0x000000af,
21596RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR = 0x000000b0,
21597RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB = 0x000000b1,
21598RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB = 0x000000b2,
21599RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR = 0x000000b3,
21600RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR = 0x000000b4,
21601RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB = 0x000000b5,
21602RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB = 0x000000b6,
21603RMI_PERF_SEL_POP_DEMUX_RTS_RTR           = 0x000000b7,
21604RMI_PERF_SEL_POP_DEMUX_RTSB_RTR          = 0x000000b8,
21605RMI_PERF_SEL_POP_DEMUX_RTS_RTRB          = 0x000000b9,
21606RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB         = 0x000000ba,
21607RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR        = 0x000000bb,
21608RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR       = 0x000000bc,
21609RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB       = 0x000000bd,
21610RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB      = 0x000000be,
21611RMI_PERF_SEL_UTC_POP_RTS_RTR             = 0x000000bf,
21612RMI_PERF_SEL_UTC_POP_RTSB_RTR            = 0x000000c0,
21613RMI_PERF_SEL_UTC_POP_RTS_RTRB            = 0x000000c1,
21614RMI_PERF_SEL_UTC_POP_RTSB_RTRB           = 0x000000c2,
21615RMI_PERF_SEL_POP_XNACK_RTS_RTR           = 0x000000c3,
21616RMI_PERF_SEL_POP_XNACK_RTSB_RTR          = 0x000000c4,
21617RMI_PERF_SEL_POP_XNACK_RTS_RTRB          = 0x000000c5,
21618RMI_PERF_SEL_POP_XNACK_RTSB_RTRB         = 0x000000c6,
21619RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR      = 0x000000c7,
21620RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR     = 0x000000c8,
21621RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB     = 0x000000c9,
21622RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB    = 0x000000ca,
21623RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR = 0x000000cb,
21624RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR = 0x000000cc,
21625RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB = 0x000000cd,
21626RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB = 0x000000ce,
21627RMI_PERF_SEL_SKID_FIFO_IN_RTS            = 0x000000cf,
21628RMI_PERF_SEL_SKID_FIFO_IN_RTSB           = 0x000000d0,
21629RMI_PERF_SEL_SKID_FIFO_OUT_RTS           = 0x000000d1,
21630RMI_PERF_SEL_SKID_FIFO_OUT_RTSB          = 0x000000d2,
21631RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR  = 0x000000d3,
21632RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR = 0x000000d4,
21633RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR   = 0x000000d5,
21634RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR   = 0x000000d6,
21635RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR    = 0x000000d7,
21636RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR    = 0x000000d8,
21637RMI_PERF_SEL_REORDER_FIFO_REQ            = 0x000000d9,
21638RMI_PERF_SEL_REORDER_FIFO_BUSY           = 0x000000da,
21639RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID  = 0x000000db,
21640RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0     = 0x000000dc,
21641RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1     = 0x000000dd,
21642RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2     = 0x000000de,
21643RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3     = 0x000000df,
21644RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4     = 0x000000e0,
21645RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5     = 0x000000e1,
21646RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6     = 0x000000e2,
21647RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7     = 0x000000e3,
21648RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0    = 0x000000e4,
21649RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1    = 0x000000e5,
21650RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2    = 0x000000e6,
21651RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3    = 0x000000e7,
21652} RMIPerfSel;
21653
21654/*******************************************************
21655 * IH Enums
21656 *******************************************************/
21657
21658/*
21659 * IH_PERF_SEL enum
21660 */
21661
21662typedef enum IH_PERF_SEL {
21663IH_PERF_SEL_CYCLE                        = 0x00000000,
21664IH_PERF_SEL_IDLE                         = 0x00000001,
21665IH_PERF_SEL_INPUT_IDLE                   = 0x00000002,
21666IH_PERF_SEL_BUFFER_IDLE                  = 0x00000003,
21667IH_PERF_SEL_RB0_FULL                     = 0x00000004,
21668IH_PERF_SEL_RB0_OVERFLOW                 = 0x00000005,
21669IH_PERF_SEL_RB0_WPTR_WRITEBACK           = 0x00000006,
21670IH_PERF_SEL_RB0_WPTR_WRAP                = 0x00000007,
21671IH_PERF_SEL_RB0_RPTR_WRAP                = 0x00000008,
21672IH_PERF_SEL_MC_WR_IDLE                   = 0x00000009,
21673IH_PERF_SEL_MC_WR_COUNT                  = 0x0000000a,
21674IH_PERF_SEL_MC_WR_STALL                  = 0x0000000b,
21675IH_PERF_SEL_MC_WR_CLEAN_PENDING          = 0x0000000c,
21676IH_PERF_SEL_MC_WR_CLEAN_STALL            = 0x0000000d,
21677IH_PERF_SEL_BIF_LINE0_RISING             = 0x0000000e,
21678IH_PERF_SEL_BIF_LINE0_FALLING            = 0x0000000f,
21679IH_PERF_SEL_RB1_FULL                     = 0x00000010,
21680IH_PERF_SEL_RB1_OVERFLOW                 = 0x00000011,
21681Reserved18                               = 0x00000012,
21682IH_PERF_SEL_RB1_WPTR_WRAP                = 0x00000013,
21683IH_PERF_SEL_RB1_RPTR_WRAP                = 0x00000014,
21684IH_PERF_SEL_RB2_FULL                     = 0x00000015,
21685IH_PERF_SEL_RB2_OVERFLOW                 = 0x00000016,
21686Reserved23                               = 0x00000017,
21687IH_PERF_SEL_RB2_WPTR_WRAP                = 0x00000018,
21688IH_PERF_SEL_RB2_RPTR_WRAP                = 0x00000019,
21689Reserved26                               = 0x0000001a,
21690Reserved27                               = 0x0000001b,
21691Reserved28                               = 0x0000001c,
21692Reserved29                               = 0x0000001d,
21693IH_PERF_SEL_RB0_FULL_VF0                 = 0x0000001e,
21694IH_PERF_SEL_RB0_FULL_VF1                 = 0x0000001f,
21695IH_PERF_SEL_RB0_FULL_VF2                 = 0x00000020,
21696IH_PERF_SEL_RB0_FULL_VF3                 = 0x00000021,
21697IH_PERF_SEL_RB0_FULL_VF4                 = 0x00000022,
21698IH_PERF_SEL_RB0_FULL_VF5                 = 0x00000023,
21699IH_PERF_SEL_RB0_FULL_VF6                 = 0x00000024,
21700IH_PERF_SEL_RB0_FULL_VF7                 = 0x00000025,
21701IH_PERF_SEL_RB0_FULL_VF8                 = 0x00000026,
21702IH_PERF_SEL_RB0_FULL_VF9                 = 0x00000027,
21703IH_PERF_SEL_RB0_FULL_VF10                = 0x00000028,
21704IH_PERF_SEL_RB0_FULL_VF11                = 0x00000029,
21705IH_PERF_SEL_RB0_FULL_VF12                = 0x0000002a,
21706IH_PERF_SEL_RB0_FULL_VF13                = 0x0000002b,
21707IH_PERF_SEL_RB0_FULL_VF14                = 0x0000002c,
21708IH_PERF_SEL_RB0_FULL_VF15                = 0x0000002d,
21709IH_PERF_SEL_RB0_OVERFLOW_VF0             = 0x0000002e,
21710IH_PERF_SEL_RB0_OVERFLOW_VF1             = 0x0000002f,
21711IH_PERF_SEL_RB0_OVERFLOW_VF2             = 0x00000030,
21712IH_PERF_SEL_RB0_OVERFLOW_VF3             = 0x00000031,
21713IH_PERF_SEL_RB0_OVERFLOW_VF4             = 0x00000032,
21714IH_PERF_SEL_RB0_OVERFLOW_VF5             = 0x00000033,
21715IH_PERF_SEL_RB0_OVERFLOW_VF6             = 0x00000034,
21716IH_PERF_SEL_RB0_OVERFLOW_VF7             = 0x00000035,
21717IH_PERF_SEL_RB0_OVERFLOW_VF8             = 0x00000036,
21718IH_PERF_SEL_RB0_OVERFLOW_VF9             = 0x00000037,
21719IH_PERF_SEL_RB0_OVERFLOW_VF10            = 0x00000038,
21720IH_PERF_SEL_RB0_OVERFLOW_VF11            = 0x00000039,
21721IH_PERF_SEL_RB0_OVERFLOW_VF12            = 0x0000003a,
21722IH_PERF_SEL_RB0_OVERFLOW_VF13            = 0x0000003b,
21723IH_PERF_SEL_RB0_OVERFLOW_VF14            = 0x0000003c,
21724IH_PERF_SEL_RB0_OVERFLOW_VF15            = 0x0000003d,
21725IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0       = 0x0000003e,
21726IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1       = 0x0000003f,
21727IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2       = 0x00000040,
21728IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3       = 0x00000041,
21729IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4       = 0x00000042,
21730IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5       = 0x00000043,
21731IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6       = 0x00000044,
21732IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7       = 0x00000045,
21733IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8       = 0x00000046,
21734IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9       = 0x00000047,
21735IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10      = 0x00000048,
21736IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11      = 0x00000049,
21737IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12      = 0x0000004a,
21738IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13      = 0x0000004b,
21739IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14      = 0x0000004c,
21740IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15      = 0x0000004d,
21741IH_PERF_SEL_RB0_WPTR_WRAP_VF0            = 0x0000004e,
21742IH_PERF_SEL_RB0_WPTR_WRAP_VF1            = 0x0000004f,
21743IH_PERF_SEL_RB0_WPTR_WRAP_VF2            = 0x00000050,
21744IH_PERF_SEL_RB0_WPTR_WRAP_VF3            = 0x00000051,
21745IH_PERF_SEL_RB0_WPTR_WRAP_VF4            = 0x00000052,
21746IH_PERF_SEL_RB0_WPTR_WRAP_VF5            = 0x00000053,
21747IH_PERF_SEL_RB0_WPTR_WRAP_VF6            = 0x00000054,
21748IH_PERF_SEL_RB0_WPTR_WRAP_VF7            = 0x00000055,
21749IH_PERF_SEL_RB0_WPTR_WRAP_VF8            = 0x00000056,
21750IH_PERF_SEL_RB0_WPTR_WRAP_VF9            = 0x00000057,
21751IH_PERF_SEL_RB0_WPTR_WRAP_VF10           = 0x00000058,
21752IH_PERF_SEL_RB0_WPTR_WRAP_VF11           = 0x00000059,
21753IH_PERF_SEL_RB0_WPTR_WRAP_VF12           = 0x0000005a,
21754IH_PERF_SEL_RB0_WPTR_WRAP_VF13           = 0x0000005b,
21755IH_PERF_SEL_RB0_WPTR_WRAP_VF14           = 0x0000005c,
21756IH_PERF_SEL_RB0_WPTR_WRAP_VF15           = 0x0000005d,
21757IH_PERF_SEL_RB0_RPTR_WRAP_VF0            = 0x0000005e,
21758IH_PERF_SEL_RB0_RPTR_WRAP_VF1            = 0x0000005f,
21759IH_PERF_SEL_RB0_RPTR_WRAP_VF2            = 0x00000060,
21760IH_PERF_SEL_RB0_RPTR_WRAP_VF3            = 0x00000061,
21761IH_PERF_SEL_RB0_RPTR_WRAP_VF4            = 0x00000062,
21762IH_PERF_SEL_RB0_RPTR_WRAP_VF5            = 0x00000063,
21763IH_PERF_SEL_RB0_RPTR_WRAP_VF6            = 0x00000064,
21764IH_PERF_SEL_RB0_RPTR_WRAP_VF7            = 0x00000065,
21765IH_PERF_SEL_RB0_RPTR_WRAP_VF8            = 0x00000066,
21766IH_PERF_SEL_RB0_RPTR_WRAP_VF9            = 0x00000067,
21767IH_PERF_SEL_RB0_RPTR_WRAP_VF10           = 0x00000068,
21768IH_PERF_SEL_RB0_RPTR_WRAP_VF11           = 0x00000069,
21769IH_PERF_SEL_RB0_RPTR_WRAP_VF12           = 0x0000006a,
21770IH_PERF_SEL_RB0_RPTR_WRAP_VF13           = 0x0000006b,
21771IH_PERF_SEL_RB0_RPTR_WRAP_VF14           = 0x0000006c,
21772IH_PERF_SEL_RB0_RPTR_WRAP_VF15           = 0x0000006d,
21773IH_PERF_SEL_BIF_LINE0_RISING_VF0         = 0x0000006e,
21774IH_PERF_SEL_BIF_LINE0_RISING_VF1         = 0x0000006f,
21775IH_PERF_SEL_BIF_LINE0_RISING_VF2         = 0x00000070,
21776IH_PERF_SEL_BIF_LINE0_RISING_VF3         = 0x00000071,
21777IH_PERF_SEL_BIF_LINE0_RISING_VF4         = 0x00000072,
21778IH_PERF_SEL_BIF_LINE0_RISING_VF5         = 0x00000073,
21779IH_PERF_SEL_BIF_LINE0_RISING_VF6         = 0x00000074,
21780IH_PERF_SEL_BIF_LINE0_RISING_VF7         = 0x00000075,
21781IH_PERF_SEL_BIF_LINE0_RISING_VF8         = 0x00000076,
21782IH_PERF_SEL_BIF_LINE0_RISING_VF9         = 0x00000077,
21783IH_PERF_SEL_BIF_LINE0_RISING_VF10        = 0x00000078,
21784IH_PERF_SEL_BIF_LINE0_RISING_VF11        = 0x00000079,
21785IH_PERF_SEL_BIF_LINE0_RISING_VF12        = 0x0000007a,
21786IH_PERF_SEL_BIF_LINE0_RISING_VF13        = 0x0000007b,
21787IH_PERF_SEL_BIF_LINE0_RISING_VF14        = 0x0000007c,
21788IH_PERF_SEL_BIF_LINE0_RISING_VF15        = 0x0000007d,
21789IH_PERF_SEL_BIF_LINE0_FALLING_VF0        = 0x0000007e,
21790IH_PERF_SEL_BIF_LINE0_FALLING_VF1        = 0x0000007f,
21791IH_PERF_SEL_BIF_LINE0_FALLING_VF2        = 0x00000080,
21792IH_PERF_SEL_BIF_LINE0_FALLING_VF3        = 0x00000081,
21793IH_PERF_SEL_BIF_LINE0_FALLING_VF4        = 0x00000082,
21794IH_PERF_SEL_BIF_LINE0_FALLING_VF5        = 0x00000083,
21795IH_PERF_SEL_BIF_LINE0_FALLING_VF6        = 0x00000084,
21796IH_PERF_SEL_BIF_LINE0_FALLING_VF7        = 0x00000085,
21797IH_PERF_SEL_BIF_LINE0_FALLING_VF8        = 0x00000086,
21798IH_PERF_SEL_BIF_LINE0_FALLING_VF9        = 0x00000087,
21799IH_PERF_SEL_BIF_LINE0_FALLING_VF10       = 0x00000088,
21800IH_PERF_SEL_BIF_LINE0_FALLING_VF11       = 0x00000089,
21801IH_PERF_SEL_BIF_LINE0_FALLING_VF12       = 0x0000008a,
21802IH_PERF_SEL_BIF_LINE0_FALLING_VF13       = 0x0000008b,
21803IH_PERF_SEL_BIF_LINE0_FALLING_VF14       = 0x0000008c,
21804IH_PERF_SEL_BIF_LINE0_FALLING_VF15       = 0x0000008d,
21805Reserved142                              = 0x0000008e,
21806Reserved143                              = 0x0000008f,
21807Reserved144                              = 0x00000090,
21808Reserved145                              = 0x00000091,
21809Reserved146                              = 0x00000092,
21810Reserved147                              = 0x00000093,
21811Reserved148                              = 0x00000094,
21812Reserved149                              = 0x00000095,
21813IH_PERF_SEL_CLIENT0_INT                  = 0x00000096,
21814IH_PERF_SEL_CLIENT1_INT                  = 0x00000097,
21815IH_PERF_SEL_CLIENT2_INT                  = 0x00000098,
21816IH_PERF_SEL_CLIENT3_INT                  = 0x00000099,
21817IH_PERF_SEL_CLIENT4_INT                  = 0x0000009a,
21818IH_PERF_SEL_CLIENT5_INT                  = 0x0000009b,
21819IH_PERF_SEL_CLIENT6_INT                  = 0x0000009c,
21820IH_PERF_SEL_CLIENT7_INT                  = 0x0000009d,
21821IH_PERF_SEL_CLIENT8_INT                  = 0x0000009e,
21822IH_PERF_SEL_CLIENT9_INT                  = 0x0000009f,
21823IH_PERF_SEL_CLIENT10_INT                 = 0x000000a0,
21824IH_PERF_SEL_CLIENT11_INT                 = 0x000000a1,
21825IH_PERF_SEL_CLIENT12_INT                 = 0x000000a2,
21826IH_PERF_SEL_CLIENT13_INT                 = 0x000000a3,
21827IH_PERF_SEL_CLIENT14_INT                 = 0x000000a4,
21828IH_PERF_SEL_CLIENT15_INT                 = 0x000000a5,
21829IH_PERF_SEL_CLIENT16_INT                 = 0x000000a6,
21830IH_PERF_SEL_CLIENT17_INT                 = 0x000000a7,
21831IH_PERF_SEL_CLIENT18_INT                 = 0x000000a8,
21832IH_PERF_SEL_CLIENT19_INT                 = 0x000000a9,
21833IH_PERF_SEL_CLIENT20_INT                 = 0x000000aa,
21834IH_PERF_SEL_CLIENT21_INT                 = 0x000000ab,
21835IH_PERF_SEL_CLIENT22_INT                 = 0x000000ac,
21836IH_PERF_SEL_CLIENT23_INT                 = 0x000000ad,
21837IH_PERF_SEL_CLIENT24_INT                 = 0x000000ae,
21838IH_PERF_SEL_CLIENT25_INT                 = 0x000000af,
21839IH_PERF_SEL_CLIENT26_INT                 = 0x000000b0,
21840IH_PERF_SEL_CLIENT27_INT                 = 0x000000b1,
21841IH_PERF_SEL_CLIENT28_INT                 = 0x000000b2,
21842IH_PERF_SEL_CLIENT29_INT                 = 0x000000b3,
21843IH_PERF_SEL_CLIENT30_INT                 = 0x000000b4,
21844IH_PERF_SEL_CLIENT31_INT                 = 0x000000b5,
21845Reserved182                              = 0x000000b6,
21846Reserved183                              = 0x000000b7,
21847Reserved184                              = 0x000000b8,
21848Reserved185                              = 0x000000b9,
21849Reserved186                              = 0x000000ba,
21850Reserved187                              = 0x000000bb,
21851Reserved188                              = 0x000000bc,
21852Reserved189                              = 0x000000bd,
21853Reserved190                              = 0x000000be,
21854Reserved191                              = 0x000000bf,
21855Reserved192                              = 0x000000c0,
21856Reserved193                              = 0x000000c1,
21857Reserved194                              = 0x000000c2,
21858Reserved195                              = 0x000000c3,
21859Reserved196                              = 0x000000c4,
21860Reserved197                              = 0x000000c5,
21861Reserved198                              = 0x000000c6,
21862Reserved199                              = 0x000000c7,
21863Reserved200                              = 0x000000c8,
21864Reserved201                              = 0x000000c9,
21865Reserved202                              = 0x000000ca,
21866Reserved203                              = 0x000000cb,
21867Reserved204                              = 0x000000cc,
21868Reserved205                              = 0x000000cd,
21869Reserved206                              = 0x000000ce,
21870Reserved207                              = 0x000000cf,
21871Reserved208                              = 0x000000d0,
21872Reserved209                              = 0x000000d1,
21873Reserved210                              = 0x000000d2,
21874Reserved211                              = 0x000000d3,
21875Reserved212                              = 0x000000d4,
21876Reserved213                              = 0x000000d5,
21877Reserved214                              = 0x000000d6,
21878Reserved215                              = 0x000000d7,
21879Reserved216                              = 0x000000d8,
21880Reserved217                              = 0x000000d9,
21881Reserved218                              = 0x000000da,
21882Reserved219                              = 0x000000db,
21883IH_PERF_SEL_RB1_FULL_VF0                 = 0x000000dc,
21884IH_PERF_SEL_RB1_FULL_VF1                 = 0x000000dd,
21885IH_PERF_SEL_RB1_FULL_VF2                 = 0x000000de,
21886IH_PERF_SEL_RB1_FULL_VF3                 = 0x000000df,
21887IH_PERF_SEL_RB1_FULL_VF4                 = 0x000000e0,
21888IH_PERF_SEL_RB1_FULL_VF5                 = 0x000000e1,
21889IH_PERF_SEL_RB1_FULL_VF6                 = 0x000000e2,
21890IH_PERF_SEL_RB1_FULL_VF7                 = 0x000000e3,
21891IH_PERF_SEL_RB1_FULL_VF8                 = 0x000000e4,
21892IH_PERF_SEL_RB1_FULL_VF9                 = 0x000000e5,
21893IH_PERF_SEL_RB1_FULL_VF10                = 0x000000e6,
21894IH_PERF_SEL_RB1_FULL_VF11                = 0x000000e7,
21895IH_PERF_SEL_RB1_FULL_VF12                = 0x000000e8,
21896IH_PERF_SEL_RB1_FULL_VF13                = 0x000000e9,
21897IH_PERF_SEL_RB1_FULL_VF14                = 0x000000ea,
21898IH_PERF_SEL_RB1_FULL_VF15                = 0x000000eb,
21899IH_PERF_SEL_RB1_OVERFLOW_VF0             = 0x000000ec,
21900IH_PERF_SEL_RB1_OVERFLOW_VF1             = 0x000000ed,
21901IH_PERF_SEL_RB1_OVERFLOW_VF2             = 0x000000ee,
21902IH_PERF_SEL_RB1_OVERFLOW_VF3             = 0x000000ef,
21903IH_PERF_SEL_RB1_OVERFLOW_VF4             = 0x000000f0,
21904IH_PERF_SEL_RB1_OVERFLOW_VF5             = 0x000000f1,
21905IH_PERF_SEL_RB1_OVERFLOW_VF6             = 0x000000f2,
21906IH_PERF_SEL_RB1_OVERFLOW_VF7             = 0x000000f3,
21907IH_PERF_SEL_RB1_OVERFLOW_VF8             = 0x000000f4,
21908IH_PERF_SEL_RB1_OVERFLOW_VF9             = 0x000000f5,
21909IH_PERF_SEL_RB1_OVERFLOW_VF10            = 0x000000f6,
21910IH_PERF_SEL_RB1_OVERFLOW_VF11            = 0x000000f7,
21911IH_PERF_SEL_RB1_OVERFLOW_VF12            = 0x000000f8,
21912IH_PERF_SEL_RB1_OVERFLOW_VF13            = 0x000000f9,
21913IH_PERF_SEL_RB1_OVERFLOW_VF14            = 0x000000fa,
21914IH_PERF_SEL_RB1_OVERFLOW_VF15            = 0x000000fb,
21915Reserved252                              = 0x000000fc,
21916Reserved253                              = 0x000000fd,
21917Reserved254                              = 0x000000fe,
21918Reserved255                              = 0x000000ff,
21919Reserved256                              = 0x00000100,
21920Reserved257                              = 0x00000101,
21921Reserved258                              = 0x00000102,
21922Reserved259                              = 0x00000103,
21923Reserved260                              = 0x00000104,
21924Reserved261                              = 0x00000105,
21925Reserved262                              = 0x00000106,
21926Reserved263                              = 0x00000107,
21927Reserved264                              = 0x00000108,
21928Reserved265                              = 0x00000109,
21929Reserved266                              = 0x0000010a,
21930Reserved267                              = 0x0000010b,
21931IH_PERF_SEL_RB1_WPTR_WRAP_VF0            = 0x0000010c,
21932IH_PERF_SEL_RB1_WPTR_WRAP_VF1            = 0x0000010d,
21933IH_PERF_SEL_RB1_WPTR_WRAP_VF2            = 0x0000010e,
21934IH_PERF_SEL_RB1_WPTR_WRAP_VF3            = 0x0000010f,
21935IH_PERF_SEL_RB1_WPTR_WRAP_VF4            = 0x00000110,
21936IH_PERF_SEL_RB1_WPTR_WRAP_VF5            = 0x00000111,
21937IH_PERF_SEL_RB1_WPTR_WRAP_VF6            = 0x00000112,
21938IH_PERF_SEL_RB1_WPTR_WRAP_VF7            = 0x00000113,
21939IH_PERF_SEL_RB1_WPTR_WRAP_VF8            = 0x00000114,
21940IH_PERF_SEL_RB1_WPTR_WRAP_VF9            = 0x00000115,
21941IH_PERF_SEL_RB1_WPTR_WRAP_VF10           = 0x00000116,
21942IH_PERF_SEL_RB1_WPTR_WRAP_VF11           = 0x00000117,
21943IH_PERF_SEL_RB1_WPTR_WRAP_VF12           = 0x00000118,
21944IH_PERF_SEL_RB1_WPTR_WRAP_VF13           = 0x00000119,
21945IH_PERF_SEL_RB1_WPTR_WRAP_VF14           = 0x0000011a,
21946IH_PERF_SEL_RB1_WPTR_WRAP_VF15           = 0x0000011b,
21947IH_PERF_SEL_RB1_RPTR_WRAP_VF0            = 0x0000011c,
21948IH_PERF_SEL_RB1_RPTR_WRAP_VF1            = 0x0000011d,
21949IH_PERF_SEL_RB1_RPTR_WRAP_VF2            = 0x0000011e,
21950IH_PERF_SEL_RB1_RPTR_WRAP_VF3            = 0x0000011f,
21951IH_PERF_SEL_RB1_RPTR_WRAP_VF4            = 0x00000120,
21952IH_PERF_SEL_RB1_RPTR_WRAP_VF5            = 0x00000121,
21953IH_PERF_SEL_RB1_RPTR_WRAP_VF6            = 0x00000122,
21954IH_PERF_SEL_RB1_RPTR_WRAP_VF7            = 0x00000123,
21955IH_PERF_SEL_RB1_RPTR_WRAP_VF8            = 0x00000124,
21956IH_PERF_SEL_RB1_RPTR_WRAP_VF9            = 0x00000125,
21957IH_PERF_SEL_RB1_RPTR_WRAP_VF10           = 0x00000126,
21958IH_PERF_SEL_RB1_RPTR_WRAP_VF11           = 0x00000127,
21959IH_PERF_SEL_RB1_RPTR_WRAP_VF12           = 0x00000128,
21960IH_PERF_SEL_RB1_RPTR_WRAP_VF13           = 0x00000129,
21961IH_PERF_SEL_RB1_RPTR_WRAP_VF14           = 0x0000012a,
21962IH_PERF_SEL_RB1_RPTR_WRAP_VF15           = 0x0000012b,
21963Reserved300                              = 0x0000012c,
21964Reserved301                              = 0x0000012d,
21965Reserved302                              = 0x0000012e,
21966Reserved303                              = 0x0000012f,
21967Reserved304                              = 0x00000130,
21968Reserved305                              = 0x00000131,
21969Reserved306                              = 0x00000132,
21970Reserved307                              = 0x00000133,
21971Reserved308                              = 0x00000134,
21972Reserved309                              = 0x00000135,
21973Reserved310                              = 0x00000136,
21974Reserved311                              = 0x00000137,
21975Reserved312                              = 0x00000138,
21976Reserved313                              = 0x00000139,
21977Reserved314                              = 0x0000013a,
21978Reserved315                              = 0x0000013b,
21979Reserved316                              = 0x0000013c,
21980Reserved317                              = 0x0000013d,
21981Reserved318                              = 0x0000013e,
21982Reserved319                              = 0x0000013f,
21983Reserved320                              = 0x00000140,
21984Reserved321                              = 0x00000141,
21985Reserved322                              = 0x00000142,
21986Reserved323                              = 0x00000143,
21987Reserved324                              = 0x00000144,
21988Reserved325                              = 0x00000145,
21989Reserved326                              = 0x00000146,
21990Reserved327                              = 0x00000147,
21991Reserved328                              = 0x00000148,
21992Reserved329                              = 0x00000149,
21993Reserved330                              = 0x0000014a,
21994Reserved331                              = 0x0000014b,
21995IH_PERF_SEL_RB2_FULL_VF0                 = 0x0000014c,
21996IH_PERF_SEL_RB2_FULL_VF1                 = 0x0000014d,
21997IH_PERF_SEL_RB2_FULL_VF2                 = 0x0000014e,
21998IH_PERF_SEL_RB2_FULL_VF3                 = 0x0000014f,
21999IH_PERF_SEL_RB2_FULL_VF4                 = 0x00000150,
22000IH_PERF_SEL_RB2_FULL_VF5                 = 0x00000151,

22001IH_PERF_SEL_RB2_FULL_VF6                 = 0x00000152,
22002IH_PERF_SEL_RB2_FULL_VF7                 = 0x00000153,
22003IH_PERF_SEL_RB2_FULL_VF8                 = 0x00000154,
22004IH_PERF_SEL_RB2_FULL_VF9                 = 0x00000155,
22005IH_PERF_SEL_RB2_FULL_VF10                = 0x00000156,
22006IH_PERF_SEL_RB2_FULL_VF11                = 0x00000157,
22007IH_PERF_SEL_RB2_FULL_VF12                = 0x00000158,
22008IH_PERF_SEL_RB2_FULL_VF13                = 0x00000159,
22009IH_PERF_SEL_RB2_FULL_VF14                = 0x0000015a,
22010IH_PERF_SEL_RB2_FULL_VF15                = 0x0000015b,
22011IH_PERF_SEL_RB2_OVERFLOW_VF0             = 0x0000015c,
22012IH_PERF_SEL_RB2_OVERFLOW_VF1             = 0x0000015d,
22013IH_PERF_SEL_RB2_OVERFLOW_VF2             = 0x0000015e,
22014IH_PERF_SEL_RB2_OVERFLOW_VF3             = 0x0000015f,
22015IH_PERF_SEL_RB2_OVERFLOW_VF4             = 0x00000160,
22016IH_PERF_SEL_RB2_OVERFLOW_VF5             = 0x00000161,
22017IH_PERF_SEL_RB2_OVERFLOW_VF6             = 0x00000162,
22018IH_PERF_SEL_RB2_OVERFLOW_VF7             = 0x00000163,
22019IH_PERF_SEL_RB2_OVERFLOW_VF8             = 0x00000164,
22020IH_PERF_SEL_RB2_OVERFLOW_VF9             = 0x00000165,
22021IH_PERF_SEL_RB2_OVERFLOW_VF10            = 0x00000166,
22022IH_PERF_SEL_RB2_OVERFLOW_VF11            = 0x00000167,
22023IH_PERF_SEL_RB2_OVERFLOW_VF12            = 0x00000168,
22024IH_PERF_SEL_RB2_OVERFLOW_VF13            = 0x00000169,
22025IH_PERF_SEL_RB2_OVERFLOW_VF14            = 0x0000016a,
22026IH_PERF_SEL_RB2_OVERFLOW_VF15            = 0x0000016b,
22027Reserved364                              = 0x0000016c,
22028Reserved365                              = 0x0000016d,
22029Reserved366                              = 0x0000016e,
22030Reserved367                              = 0x0000016f,
22031Reserved368                              = 0x00000170,
22032Reserved369                              = 0x00000171,
22033Reserved370                              = 0x00000172,
22034Reserved371                              = 0x00000173,
22035Reserved372                              = 0x00000174,
22036Reserved373                              = 0x00000175,
22037Reserved374                              = 0x00000176,
22038Reserved375                              = 0x00000177,
22039Reserved376                              = 0x00000178,
22040Reserved377                              = 0x00000179,
22041Reserved378                              = 0x0000017a,
22042Reserved379                              = 0x0000017b,
22043IH_PERF_SEL_RB2_WPTR_WRAP_VF0            = 0x0000017c,
22044IH_PERF_SEL_RB2_WPTR_WRAP_VF1            = 0x0000017d,
22045IH_PERF_SEL_RB2_WPTR_WRAP_VF2            = 0x0000017e,
22046IH_PERF_SEL_RB2_WPTR_WRAP_VF3            = 0x0000017f,
22047IH_PERF_SEL_RB2_WPTR_WRAP_VF4            = 0x00000180,
22048IH_PERF_SEL_RB2_WPTR_WRAP_VF5            = 0x00000181,
22049IH_PERF_SEL_RB2_WPTR_WRAP_VF6            = 0x00000182,
22050IH_PERF_SEL_RB2_WPTR_WRAP_VF7            = 0x00000183,
22051IH_PERF_SEL_RB2_WPTR_WRAP_VF8            = 0x00000184,
22052IH_PERF_SEL_RB2_WPTR_WRAP_VF9            = 0x00000185,
22053IH_PERF_SEL_RB2_WPTR_WRAP_VF10           = 0x00000186,
22054IH_PERF_SEL_RB2_WPTR_WRAP_VF11           = 0x00000187,
22055IH_PERF_SEL_RB2_WPTR_WRAP_VF12           = 0x00000188,
22056IH_PERF_SEL_RB2_WPTR_WRAP_VF13           = 0x00000189,
22057IH_PERF_SEL_RB2_WPTR_WRAP_VF14           = 0x0000018a,
22058IH_PERF_SEL_RB2_WPTR_WRAP_VF15           = 0x0000018b,
22059IH_PERF_SEL_RB2_RPTR_WRAP_VF0            = 0x0000018c,
22060IH_PERF_SEL_RB2_RPTR_WRAP_VF1            = 0x0000018d,
22061IH_PERF_SEL_RB2_RPTR_WRAP_VF2            = 0x0000018e,
22062IH_PERF_SEL_RB2_RPTR_WRAP_VF3            = 0x0000018f,
22063IH_PERF_SEL_RB2_RPTR_WRAP_VF4            = 0x00000190,
22064IH_PERF_SEL_RB2_RPTR_WRAP_VF5            = 0x00000191,
22065IH_PERF_SEL_RB2_RPTR_WRAP_VF6            = 0x00000192,
22066IH_PERF_SEL_RB2_RPTR_WRAP_VF7            = 0x00000193,
22067IH_PERF_SEL_RB2_RPTR_WRAP_VF8            = 0x00000194,
22068IH_PERF_SEL_RB2_RPTR_WRAP_VF9            = 0x00000195,
22069IH_PERF_SEL_RB2_RPTR_WRAP_VF10           = 0x00000196,
22070IH_PERF_SEL_RB2_RPTR_WRAP_VF11           = 0x00000197,
22071IH_PERF_SEL_RB2_RPTR_WRAP_VF12           = 0x00000198,
22072IH_PERF_SEL_RB2_RPTR_WRAP_VF13           = 0x00000199,
22073IH_PERF_SEL_RB2_RPTR_WRAP_VF14           = 0x0000019a,
22074IH_PERF_SEL_RB2_RPTR_WRAP_VF15           = 0x0000019b,
22075Reserved412                              = 0x0000019c,
22076Reserved413                              = 0x0000019d,
22077Reserved414                              = 0x0000019e,
22078Reserved415                              = 0x0000019f,
22079Reserved416                              = 0x000001a0,
22080Reserved417                              = 0x000001a1,
22081Reserved418                              = 0x000001a2,
22082Reserved419                              = 0x000001a3,
22083Reserved420                              = 0x000001a4,
22084Reserved421                              = 0x000001a5,
22085Reserved422                              = 0x000001a6,
22086Reserved423                              = 0x000001a7,
22087Reserved424                              = 0x000001a8,
22088Reserved425                              = 0x000001a9,
22089Reserved426                              = 0x000001aa,
22090Reserved427                              = 0x000001ab,
22091Reserved428                              = 0x000001ac,
22092Reserved429                              = 0x000001ad,
22093Reserved430                              = 0x000001ae,
22094Reserved431                              = 0x000001af,
22095Reserved432                              = 0x000001b0,
22096Reserved433                              = 0x000001b1,
22097Reserved434                              = 0x000001b2,
22098Reserved435                              = 0x000001b3,
22099Reserved436                              = 0x000001b4,
22100Reserved437                              = 0x000001b5,
22101Reserved438                              = 0x000001b6,
22102Reserved439                              = 0x000001b7,
22103Reserved440                              = 0x000001b8,
22104Reserved441                              = 0x000001b9,
22105Reserved442                              = 0x000001ba,
22106Reserved443                              = 0x000001bb,
22107Reserved444                              = 0x000001bc,
22108Reserved445                              = 0x000001bd,
22109Reserved446                              = 0x000001be,
22110Reserved447                              = 0x000001bf,
22111Reserved448                              = 0x000001c0,
22112Reserved449                              = 0x000001c1,
22113Reserved450                              = 0x000001c2,
22114Reserved451                              = 0x000001c3,
22115Reserved452                              = 0x000001c4,
22116Reserved453                              = 0x000001c5,
22117Reserved454                              = 0x000001c6,
22118Reserved455                              = 0x000001c7,
22119Reserved456                              = 0x000001c8,
22120Reserved457                              = 0x000001c9,
22121Reserved458                              = 0x000001ca,
22122Reserved459                              = 0x000001cb,
22123Reserved460                              = 0x000001cc,
22124Reserved461                              = 0x000001cd,
22125Reserved462                              = 0x000001ce,
22126Reserved463                              = 0x000001cf,
22127Reserved464                              = 0x000001d0,
22128Reserved465                              = 0x000001d1,
22129Reserved466                              = 0x000001d2,
22130Reserved467                              = 0x000001d3,
22131Reserved468                              = 0x000001d4,
22132Reserved469                              = 0x000001d5,
22133Reserved470                              = 0x000001d6,
22134Reserved471                              = 0x000001d7,
22135Reserved472                              = 0x000001d8,
22136Reserved473                              = 0x000001d9,
22137Reserved474                              = 0x000001da,
22138Reserved475                              = 0x000001db,
22139Reserved476                              = 0x000001dc,
22140Reserved477                              = 0x000001dd,
22141Reserved478                              = 0x000001de,
22142Reserved479                              = 0x000001df,
22143Reserved480                              = 0x000001e0,
22144Reserved481                              = 0x000001e1,
22145Reserved482                              = 0x000001e2,
22146Reserved483                              = 0x000001e3,
22147Reserved484                              = 0x000001e4,
22148Reserved485                              = 0x000001e5,
22149Reserved486                              = 0x000001e6,
22150Reserved487                              = 0x000001e7,
22151Reserved488                              = 0x000001e8,
22152Reserved489                              = 0x000001e9,
22153Reserved490                              = 0x000001ea,
22154Reserved491                              = 0x000001eb,
22155Reserved492                              = 0x000001ec,
22156Reserved493                              = 0x000001ed,
22157Reserved494                              = 0x000001ee,
22158Reserved495                              = 0x000001ef,
22159Reserved496                              = 0x000001f0,
22160Reserved497                              = 0x000001f1,
22161Reserved498                              = 0x000001f2,
22162Reserved499                              = 0x000001f3,
22163Reserved500                              = 0x000001f4,
22164Reserved501                              = 0x000001f5,
22165Reserved502                              = 0x000001f6,
22166Reserved503                              = 0x000001f7,
22167Reserved504                              = 0x000001f8,
22168Reserved505                              = 0x000001f9,
22169Reserved506                              = 0x000001fa,
22170Reserved507                              = 0x000001fb,
22171Reserved508                              = 0x000001fc,
22172Reserved509                              = 0x000001fd,
22173Reserved510                              = 0x000001fe,
22174Reserved511                              = 0x000001ff,
22175} IH_PERF_SEL;
22176
22177/*******************************************************
22178 * SEM Enums
22179 *******************************************************/
22180
22181/*
22182 * SEM_PERF_SEL enum
22183 */
22184
22185typedef enum SEM_PERF_SEL {
22186SEM_PERF_SEL_CYCLE                       = 0x00000000,
22187SEM_PERF_SEL_IDLE                        = 0x00000001,
22188SEM_PERF_SEL_SDMA0_REQ_SIGNAL            = 0x00000002,
22189SEM_PERF_SEL_SDMA1_REQ_SIGNAL            = 0x00000003,
22190SEM_PERF_SEL_UVD_REQ_SIGNAL              = 0x00000004,
22191SEM_PERF_SEL_VCE0_REQ_SIGNAL             = 0x00000005,
22192SEM_PERF_SEL_ACP_REQ_SIGNAL              = 0x00000006,
22193SEM_PERF_SEL_ISP_REQ_SIGNAL              = 0x00000007,
22194SEM_PERF_SEL_VCE1_REQ_SIGNAL             = 0x00000008,
22195SEM_PERF_SEL_VP8_REQ_SIGNAL              = 0x00000009,
22196SEM_PERF_SEL_CPG_E0_REQ_SIGNAL           = 0x0000000a,
22197SEM_PERF_SEL_CPG_E1_REQ_SIGNAL           = 0x0000000b,
22198SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL     = 0x0000000c,
22199SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL     = 0x0000000d,
22200SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL     = 0x0000000e,
22201SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL     = 0x0000000f,
22202SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL     = 0x00000010,
22203SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL     = 0x00000011,
22204SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL     = 0x00000012,
22205SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL     = 0x00000013,
22206SEM_PERF_SEL_SDMA0_REQ_WAIT              = 0x00000014,
22207SEM_PERF_SEL_SDMA1_REQ_WAIT              = 0x00000015,
22208SEM_PERF_SEL_UVD_REQ_WAIT                = 0x00000016,
22209SEM_PERF_SEL_VCE0_REQ_WAIT               = 0x00000017,
22210SEM_PERF_SEL_ACP_REQ_WAIT                = 0x00000018,
22211SEM_PERF_SEL_ISP_REQ_WAIT                = 0x00000019,
22212SEM_PERF_SEL_VCE1_REQ_WAIT               = 0x0000001a,
22213SEM_PERF_SEL_VP8_REQ_WAIT                = 0x0000001b,
22214SEM_PERF_SEL_CPG_E0_REQ_WAIT             = 0x0000001c,
22215SEM_PERF_SEL_CPG_E1_REQ_WAIT             = 0x0000001d,
22216SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT       = 0x0000001e,
22217SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT       = 0x0000001f,
22218SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT       = 0x00000020,
22219SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT       = 0x00000021,
22220SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT       = 0x00000022,
22221SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT       = 0x00000023,
22222SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT       = 0x00000024,
22223SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT       = 0x00000025,
22224SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT       = 0x00000026,
22225SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT       = 0x00000027,
22226SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT       = 0x00000028,
22227SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT       = 0x00000029,
22228SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT       = 0x0000002a,
22229SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT       = 0x0000002b,
22230SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT       = 0x0000002c,
22231SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT       = 0x0000002d,
22232SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT       = 0x0000002e,
22233SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT       = 0x0000002f,
22234SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT      = 0x00000030,
22235SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT      = 0x00000031,
22236SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT      = 0x00000032,
22237SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT      = 0x00000033,
22238SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT      = 0x00000034,
22239SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT      = 0x00000035,
22240SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT      = 0x00000036,
22241SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT      = 0x00000037,
22242SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT      = 0x00000038,
22243SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT      = 0x00000039,
22244SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT      = 0x0000003a,
22245SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT      = 0x0000003b,
22246SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT      = 0x0000003c,
22247SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT      = 0x0000003d,
22248SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT      = 0x0000003e,
22249SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT      = 0x0000003f,
22250SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT      = 0x00000040,
22251SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT      = 0x00000041,
22252SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT      = 0x00000042,
22253SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT      = 0x00000043,
22254SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT      = 0x00000044,
22255SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT      = 0x00000045,
22256SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT       = 0x00000046,
22257SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT       = 0x00000047,
22258SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT       = 0x00000048,
22259SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT       = 0x00000049,
22260SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT       = 0x0000004a,
22261SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT       = 0x0000004b,
22262SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT       = 0x0000004c,
22263SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT       = 0x0000004d,
22264SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT       = 0x0000004e,
22265SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT       = 0x0000004f,
22266SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT      = 0x00000050,
22267SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT      = 0x00000051,
22268SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT      = 0x00000052,
22269SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT      = 0x00000053,
22270SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT      = 0x00000054,
22271SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT      = 0x00000055,
22272SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT      = 0x00000056,
22273SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT      = 0x00000057,
22274SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT      = 0x00000058,
22275SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT      = 0x00000059,
22276SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT      = 0x0000005a,
22277SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT      = 0x0000005b,
22278SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT      = 0x0000005c,
22279SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT      = 0x0000005d,
22280SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT      = 0x0000005e,
22281SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT      = 0x0000005f,
22282SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT      = 0x00000060,
22283SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT      = 0x00000061,
22284SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT      = 0x00000062,
22285SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT      = 0x00000063,
22286SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT      = 0x00000064,
22287SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT      = 0x00000065,
22288SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT      = 0x00000066,
22289SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT      = 0x00000067,
22290SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT      = 0x00000068,
22291SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT      = 0x00000069,
22292SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT      = 0x0000006a,
22293SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT      = 0x0000006b,
22294SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT      = 0x0000006c,
22295SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT      = 0x0000006d,
22296SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT      = 0x0000006e,
22297SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT      = 0x0000006f,
22298SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT     = 0x00000070,
22299SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT     = 0x00000071,
22300SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT     = 0x00000072,
22301SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT     = 0x00000073,
22302SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT     = 0x00000074,
22303SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT     = 0x00000075,
22304SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT     = 0x00000076,
22305SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT     = 0x00000077,
22306SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT     = 0x00000078,
22307SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT     = 0x00000079,
22308SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT     = 0x0000007a,
22309SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT     = 0x0000007b,
22310SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT     = 0x0000007c,
22311SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT     = 0x0000007d,
22312SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT     = 0x0000007e,
22313SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT     = 0x0000007f,
22314SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT     = 0x00000080,
22315SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT     = 0x00000081,
22316SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT     = 0x00000082,
22317SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT     = 0x00000083,
22318SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT     = 0x00000084,
22319SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT     = 0x00000085,
22320SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT      = 0x00000086,
22321SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT      = 0x00000087,
22322SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT      = 0x00000088,
22323SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT      = 0x00000089,
22324SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT      = 0x0000008a,
22325SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT      = 0x0000008b,
22326SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT      = 0x0000008c,
22327SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT      = 0x0000008d,
22328SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT      = 0x0000008e,
22329SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT      = 0x0000008f,
22330SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT     = 0x00000090,
22331SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT     = 0x00000091,
22332SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT     = 0x00000092,
22333SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT     = 0x00000093,
22334SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT     = 0x00000094,
22335SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT     = 0x00000095,
22336SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT     = 0x00000096,
22337SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT     = 0x00000097,
22338SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT     = 0x00000098,
22339SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT     = 0x00000099,
22340SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT     = 0x0000009a,
22341SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT     = 0x0000009b,
22342SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT     = 0x0000009c,
22343SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT     = 0x0000009d,
22344SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT     = 0x0000009e,
22345SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT     = 0x0000009f,
22346SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT     = 0x000000a0,
22347SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT     = 0x000000a1,
22348SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT     = 0x000000a2,
22349SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT     = 0x000000a3,
22350SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT     = 0x000000a4,
22351SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT     = 0x000000a5,
22352SEM_PERF_SEL_MC_RD_REQ                   = 0x000000a6,
22353SEM_PERF_SEL_MC_RD_RET                   = 0x000000a7,
22354SEM_PERF_SEL_MC_WR_REQ                   = 0x000000a8,
22355SEM_PERF_SEL_MC_WR_RET                   = 0x000000a9,
22356SEM_PERF_SEL_ATC_REQ                     = 0x000000aa,
22357SEM_PERF_SEL_ATC_RET                     = 0x000000ab,
22358SEM_PERF_SEL_ATC_XNACK                   = 0x000000ac,
22359SEM_PERF_SEL_ATC_INVALIDATION            = 0x000000ad,
22360} SEM_PERF_SEL;
22361
22362/*******************************************************
22363 * SDMA Enums
22364 *******************************************************/
22365
22366/*
22367 * SDMA_PERF_SEL enum
22368 */
22369
22370typedef enum SDMA_PERF_SEL {
22371SDMA_PERF_SEL_CYCLE                      = 0x00000000,
22372SDMA_PERF_SEL_IDLE                       = 0x00000001,
22373SDMA_PERF_SEL_REG_IDLE                   = 0x00000002,
22374SDMA_PERF_SEL_RB_EMPTY                   = 0x00000003,
22375SDMA_PERF_SEL_RB_FULL                    = 0x00000004,
22376SDMA_PERF_SEL_RB_WPTR_WRAP               = 0x00000005,
22377SDMA_PERF_SEL_RB_RPTR_WRAP               = 0x00000006,
22378SDMA_PERF_SEL_RB_WPTR_POLL_READ          = 0x00000007,
22379SDMA_PERF_SEL_RB_RPTR_WB                 = 0x00000008,
22380SDMA_PERF_SEL_RB_CMD_IDLE                = 0x00000009,
22381SDMA_PERF_SEL_RB_CMD_FULL                = 0x0000000a,
22382SDMA_PERF_SEL_IB_CMD_IDLE                = 0x0000000b,
22383SDMA_PERF_SEL_IB_CMD_FULL                = 0x0000000c,
22384SDMA_PERF_SEL_EX_IDLE                    = 0x0000000d,
22385SDMA_PERF_SEL_SRBM_REG_SEND              = 0x0000000e,
22386SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE  = 0x0000000f,
22387SDMA_PERF_SEL_MC_WR_IDLE                 = 0x00000010,
22388SDMA_PERF_SEL_MC_WR_COUNT                = 0x00000011,
22389SDMA_PERF_SEL_MC_RD_IDLE                 = 0x00000012,
22390SDMA_PERF_SEL_MC_RD_COUNT                = 0x00000013,
22391SDMA_PERF_SEL_MC_RD_RET_STALL            = 0x00000014,
22392SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE         = 0x00000015,
22393SDMA_PERF_SEL_SEM_IDLE                   = 0x00000018,
22394SDMA_PERF_SEL_SEM_REQ_STALL              = 0x00000019,
22395SDMA_PERF_SEL_SEM_REQ_COUNT              = 0x0000001a,
22396SDMA_PERF_SEL_SEM_RESP_INCOMPLETE        = 0x0000001b,
22397SDMA_PERF_SEL_SEM_RESP_FAIL              = 0x0000001c,
22398SDMA_PERF_SEL_SEM_RESP_PASS              = 0x0000001d,
22399SDMA_PERF_SEL_INT_IDLE                   = 0x0000001e,
22400SDMA_PERF_SEL_INT_REQ_STALL              = 0x0000001f,
22401SDMA_PERF_SEL_INT_REQ_COUNT              = 0x00000020,
22402SDMA_PERF_SEL_INT_RESP_ACCEPTED          = 0x00000021,
22403SDMA_PERF_SEL_INT_RESP_RETRY             = 0x00000022,
22404SDMA_PERF_SEL_NUM_PACKET                 = 0x00000023,
22405SDMA_PERF_SEL_CE_WREQ_IDLE               = 0x00000025,
22406SDMA_PERF_SEL_CE_WR_IDLE                 = 0x00000026,
22407SDMA_PERF_SEL_CE_SPLIT_IDLE              = 0x00000027,
22408SDMA_PERF_SEL_CE_RREQ_IDLE               = 0x00000028,
22409SDMA_PERF_SEL_CE_OUT_IDLE                = 0x00000029,
22410SDMA_PERF_SEL_CE_IN_IDLE                 = 0x0000002a,
22411SDMA_PERF_SEL_CE_DST_IDLE                = 0x0000002b,
22412SDMA_PERF_SEL_CE_AFIFO_FULL              = 0x0000002e,
22413SDMA_PERF_SEL_CE_INFO_FULL               = 0x00000031,
22414SDMA_PERF_SEL_CE_INFO1_FULL              = 0x00000032,
22415SDMA_PERF_SEL_CE_RD_STALL                = 0x00000033,
22416SDMA_PERF_SEL_CE_WR_STALL                = 0x00000034,
22417SDMA_PERF_SEL_GFX_SELECT                 = 0x00000035,
22418SDMA_PERF_SEL_RLC0_SELECT                = 0x00000036,
22419SDMA_PERF_SEL_RLC1_SELECT                = 0x00000037,
22420SDMA_PERF_SEL_PAGE_SELECT                = 0x00000038,
22421SDMA_PERF_SEL_CTX_CHANGE                 = 0x00000039,
22422SDMA_PERF_SEL_CTX_CHANGE_EXPIRED         = 0x0000003a,
22423SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION       = 0x0000003b,
22424SDMA_PERF_SEL_DOORBELL                   = 0x0000003c,
22425SDMA_PERF_SEL_RD_BA_RTR                  = 0x0000003d,
22426SDMA_PERF_SEL_WR_BA_RTR                  = 0x0000003e,
22427SDMA_PERF_SEL_F32_L1_WR_VLD              = 0x0000003f,
22428SDMA_PERF_SEL_CE_L1_WR_VLD               = 0x00000040,
22429SDMA_PERF_SEL_CE_L1_STALL                = 0x00000041,
22430SDMA_PERF_SEL_SDMA_INVACK_NFLUSH         = 0x00000042,
22431SDMA_PERF_SEL_SDMA_INVACK_FLUSH          = 0x00000043,
22432SDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH        = 0x00000044,
22433SDMA_PERF_SEL_ATCL2_INVREQ_FLUSH         = 0x00000045,
22434SDMA_PERF_SEL_ATCL2_RET_XNACK            = 0x00000046,
22435SDMA_PERF_SEL_ATCL2_RET_ACK              = 0x00000047,
22436SDMA_PERF_SEL_ATCL2_FREE                 = 0x00000048,
22437SDMA_PERF_SEL_SDMA_ATCL2_SEND            = 0x00000049,
22438SDMA_PERF_SEL_DMA_L1_WR_SEND             = 0x0000004a,
22439SDMA_PERF_SEL_DMA_L1_RD_SEND             = 0x0000004b,
22440SDMA_PERF_SEL_DMA_MC_WR_SEND             = 0x0000004c,
22441SDMA_PERF_SEL_DMA_MC_RD_SEND             = 0x0000004d,
22442SDMA_PERF_SEL_L1_WR_FIFO_IDLE            = 0x0000004e,
22443SDMA_PERF_SEL_L1_RD_FIFO_IDLE            = 0x0000004f,
22444SDMA_PERF_SEL_L1_WRL2_IDLE               = 0x00000050,
22445SDMA_PERF_SEL_L1_RDL2_IDLE               = 0x00000051,
22446SDMA_PERF_SEL_L1_WRMC_IDLE               = 0x00000052,
22447SDMA_PERF_SEL_L1_RDMC_IDLE               = 0x00000053,
22448SDMA_PERF_SEL_L1_WR_INV_IDLE             = 0x00000054,
22449SDMA_PERF_SEL_L1_RD_INV_IDLE             = 0x00000055,
22450SDMA_PERF_SEL_L1_WR_INV_EN               = 0x00000056,
22451SDMA_PERF_SEL_L1_RD_INV_EN               = 0x00000057,
22452SDMA_PERF_SEL_L1_WR_WAIT_INVADR          = 0x00000058,
22453SDMA_PERF_SEL_L1_RD_WAIT_INVADR          = 0x00000059,
22454SDMA_PERF_SEL_IS_INVREQ_ADDR_WR          = 0x0000005a,
22455SDMA_PERF_SEL_IS_INVREQ_ADDR_RD          = 0x0000005b,
22456SDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT        = 0x0000005c,
22457SDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT        = 0x0000005d,
22458SDMA_PERF_SEL_L1_INV_MIDDLE              = 0x0000005e,
22459SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER    = 0x000000fe,
22460SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER    = 0x000000ff,
22461} SDMA_PERF_SEL;
22462
22463/*******************************************************
22464 * SMUIO Enums
22465 *******************************************************/
22466
22467/*
22468 * ROM_SIGNATURE value
22469 */
22470
22471#define ROM_SIGNATURE                  0x0000aa55
22472
22473/*******************************************************
22474 * XDMA_CMN Enums
22475 *******************************************************/
22476
22477/*
22478 * ENUM_XDMA_LOCAL_SW_MODE enum
22479 */
22480
22481typedef enum ENUM_XDMA_LOCAL_SW_MODE {
22482XDMA_LOCAL_SW_MODE_SW_256B_D             = 0x00000002,
22483XDMA_LOCAL_SW_MODE_SW_64KB_D             = 0x0000000a,
22484XDMA_LOCAL_SW_MODE_SW_64KB_D_X           = 0x0000001a,
22485} ENUM_XDMA_LOCAL_SW_MODE;
22486
22487/*******************************************************
22488 * XDMA_SLV Enums
22489 *******************************************************/
22490
22491/*
22492 * ENUM_XDMA_SLV_ALPHA_POSITION enum
22493 */
22494
22495typedef enum ENUM_XDMA_SLV_ALPHA_POSITION {
22496XDMA_SLV_ALPHA_POSITION_7_0              = 0x00000000,
22497XDMA_SLV_ALPHA_POSITION_15_8             = 0x00000001,
22498XDMA_SLV_ALPHA_POSITION_23_16            = 0x00000002,
22499XDMA_SLV_ALPHA_POSITION_31_24            = 0x00000003,
22500} ENUM_XDMA_SLV_ALPHA_POSITION;
22501
22502/*******************************************************
22503 * XDMA_MSTR Enums
22504 *******************************************************/
22505
22506/*
22507 * ENUM_XDMA_MSTR_ALPHA_POSITION enum
22508 */
22509
22510typedef enum ENUM_XDMA_MSTR_ALPHA_POSITION {
22511XDMA_MSTR_ALPHA_POSITION_7_0             = 0x00000000,
22512XDMA_MSTR_ALPHA_POSITION_15_8            = 0x00000001,
22513XDMA_MSTR_ALPHA_POSITION_23_16           = 0x00000002,
22514XDMA_MSTR_ALPHA_POSITION_31_24           = 0x00000003,
22515} ENUM_XDMA_MSTR_ALPHA_POSITION;
22516
22517/*
22518 * ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL enum
22519 */
22520
22521typedef enum ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL {
22522XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE0      = 0x00000000,
22523XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE1      = 0x00000001,
22524XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE2      = 0x00000002,
22525XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE3      = 0x00000003,
22526XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE4      = 0x00000004,
22527XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE5      = 0x00000005,
22528} ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL;
22529
22530
22531#endif /*_vega10_ENUM_HEADER*/
22532
22533