linux/drivers/gpu/drm/amd/include/vega10_enum.h
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   1/*
   2 * Copyright (C) 2017  Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included
  12 * in all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20 */
  21#if !defined (_vega10_ENUM_HEADER)
  22#define _vega10_ENUM_HEADER
  23
  24#ifndef _DRIVER_BUILD
  25#ifndef GL_ZERO
  26#define GL__ZERO                      BLEND_ZERO
  27#define GL__ONE                       BLEND_ONE
  28#define GL__SRC_COLOR                 BLEND_SRC_COLOR
  29#define GL__ONE_MINUS_SRC_COLOR       BLEND_ONE_MINUS_SRC_COLOR
  30#define GL__DST_COLOR                 BLEND_DST_COLOR
  31#define GL__ONE_MINUS_DST_COLOR       BLEND_ONE_MINUS_DST_COLOR
  32#define GL__SRC_ALPHA                 BLEND_SRC_ALPHA
  33#define GL__ONE_MINUS_SRC_ALPHA       BLEND_ONE_MINUS_SRC_ALPHA
  34#define GL__DST_ALPHA                 BLEND_DST_ALPHA
  35#define GL__ONE_MINUS_DST_ALPHA       BLEND_ONE_MINUS_DST_ALPHA
  36#define GL__SRC_ALPHA_SATURATE        BLEND_SRC_ALPHA_SATURATE
  37#define GL__CONSTANT_COLOR            BLEND_CONSTANT_COLOR
  38#define GL__ONE_MINUS_CONSTANT_COLOR  BLEND_ONE_MINUS_CONSTANT_COLOR
  39#define GL__CONSTANT_ALPHA            BLEND_CONSTANT_ALPHA
  40#define GL__ONE_MINUS_CONSTANT_ALPHA  BLEND_ONE_MINUS_CONSTANT_ALPHA
  41#endif
  42#endif
  43
  44/*******************************************************
  45 * GDS DATA_TYPE Enums
  46 *******************************************************/
  47
  48#ifndef ENUMS_GDS_PERFCOUNT_SELECT_H
  49#define ENUMS_GDS_PERFCOUNT_SELECT_H
  50typedef enum GDS_PERFCOUNT_SELECT {
  51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
  52 GDS_PERF_SEL_DS_BANK_CONFL = 1,
  53 GDS_PERF_SEL_WBUF_FLUSH = 2,
  54 GDS_PERF_SEL_WR_COMP = 3,
  55 GDS_PERF_SEL_WBUF_WR = 4,
  56 GDS_PERF_SEL_RBUF_HIT = 5,
  57 GDS_PERF_SEL_RBUF_MISS = 6,
  58 GDS_PERF_SEL_SE0_SH0_NORET = 7,
  59 GDS_PERF_SEL_SE0_SH0_RET = 8,
  60 GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9,
  61 GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10,
  62 GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11,
  63 GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12,
  64 GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13,
  65 GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14,
  66 GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15,
  67 GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16,
  68 GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17,
  69 GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18,
  70 GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19,
  71 GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20,
  72 GDS_PERF_SEL_SE0_SH1_NORET = 21,
  73 GDS_PERF_SEL_SE0_SH1_RET = 22,
  74 GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23,
  75 GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24,
  76 GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25,
  77 GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26,
  78 GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27,
  79 GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28,
  80 GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29,
  81 GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30,
  82 GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31,
  83 GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32,
  84 GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33,
  85 GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34,
  86 GDS_PERF_SEL_SE1_SH0_NORET = 35,
  87 GDS_PERF_SEL_SE1_SH0_RET = 36,
  88 GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37,
  89 GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38,
  90 GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39,
  91 GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40,
  92 GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41,
  93 GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42,
  94 GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43,
  95 GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44,
  96 GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45,
  97 GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46,
  98 GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47,
  99 GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48,
 100 GDS_PERF_SEL_SE1_SH1_NORET = 49,
 101 GDS_PERF_SEL_SE1_SH1_RET = 50,
 102 GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51,
 103 GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52,
 104 GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53,
 105 GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54,
 106 GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55,
 107 GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56,
 108 GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57,
 109 GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58,
 110 GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59,
 111 GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP = 60,
 112 GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP = 61,
 113 GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP = 62,
 114 GDS_PERF_SEL_SE2_SH0_NORET = 63,
 115 GDS_PERF_SEL_SE2_SH0_RET = 64,
 116 GDS_PERF_SEL_SE2_SH0_ORD_CNT = 65,
 117 GDS_PERF_SEL_SE2_SH0_2COMP_REQ = 66,
 118 GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID = 67,
 119 GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID = 68,
 120 GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD = 69,
 121 GDS_PERF_SEL_SE2_SH0_GDS_WR_OP = 70,
 122 GDS_PERF_SEL_SE2_SH0_GDS_RD_OP = 71,
 123 GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP = 72,
 124 GDS_PERF_SEL_SE2_SH0_GDS_REL_OP = 73,
 125 GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP = 74,
 126 GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP = 75,
 127 GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP = 76,
 128 GDS_PERF_SEL_SE2_SH1_NORET = 77,
 129 GDS_PERF_SEL_SE2_SH1_RET = 78,
 130 GDS_PERF_SEL_SE2_SH1_ORD_CNT = 79,
 131 GDS_PERF_SEL_SE2_SH1_2COMP_REQ = 80,
 132 GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID = 81,
 133 GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID = 82,
 134 GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD = 83,
 135 GDS_PERF_SEL_SE2_SH1_GDS_WR_OP = 84,
 136 GDS_PERF_SEL_SE2_SH1_GDS_RD_OP = 85,
 137 GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP = 86,
 138 GDS_PERF_SEL_SE2_SH1_GDS_REL_OP = 87,
 139 GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP = 88,
 140 GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP = 89,
 141 GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP = 90,
 142 GDS_PERF_SEL_SE3_SH0_NORET = 91,
 143 GDS_PERF_SEL_SE3_SH0_RET = 92,
 144 GDS_PERF_SEL_SE3_SH0_ORD_CNT = 93,
 145 GDS_PERF_SEL_SE3_SH0_2COMP_REQ = 94,
 146 GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID = 95,
 147 GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID = 96,
 148 GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD = 97,
 149 GDS_PERF_SEL_SE3_SH0_GDS_WR_OP = 98,
 150 GDS_PERF_SEL_SE3_SH0_GDS_RD_OP = 99,
 151 GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP = 100,
 152 GDS_PERF_SEL_SE3_SH0_GDS_REL_OP = 101,
 153 GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP = 102,
 154 GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP = 103,
 155 GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP = 104,
 156 GDS_PERF_SEL_SE3_SH1_NORET = 105,
 157 GDS_PERF_SEL_SE3_SH1_RET = 106,
 158 GDS_PERF_SEL_SE3_SH1_ORD_CNT = 107,
 159 GDS_PERF_SEL_SE3_SH1_2COMP_REQ = 108,
 160 GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID = 109,
 161 GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID = 110,
 162 GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD = 111,
 163 GDS_PERF_SEL_SE3_SH1_GDS_WR_OP = 112,
 164 GDS_PERF_SEL_SE3_SH1_GDS_RD_OP = 113,
 165 GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP = 114,
 166 GDS_PERF_SEL_SE3_SH1_GDS_REL_OP = 115,
 167 GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP = 116,
 168 GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP = 117,
 169 GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP = 118,
 170 GDS_PERF_SEL_GWS_RELEASED = 119,
 171 GDS_PERF_SEL_GWS_BYPASS = 120,
 172} GDS_PERFCOUNT_SELECT;
 173#endif /*ENUMS_GDS_PERFCOUNT_SELECT_H*/
 174
 175/*******************************************************
 176 * Chip Enums
 177 *******************************************************/
 178
 179/*
 180 * MEM_PWR_FORCE_CTRL enum
 181 */
 182
 183typedef enum MEM_PWR_FORCE_CTRL {
 184NO_FORCE_REQUEST                         = 0x00000000,
 185FORCE_LIGHT_SLEEP_REQUEST                = 0x00000001,
 186FORCE_DEEP_SLEEP_REQUEST                 = 0x00000002,
 187FORCE_SHUT_DOWN_REQUEST                  = 0x00000003,
 188} MEM_PWR_FORCE_CTRL;
 189
 190/*
 191 * MEM_PWR_FORCE_CTRL2 enum
 192 */
 193
 194typedef enum MEM_PWR_FORCE_CTRL2 {
 195NO_FORCE_REQ                             = 0x00000000,
 196FORCE_LIGHT_SLEEP_REQ                    = 0x00000001,
 197} MEM_PWR_FORCE_CTRL2;
 198
 199/*
 200 * MEM_PWR_DIS_CTRL enum
 201 */
 202
 203typedef enum MEM_PWR_DIS_CTRL {
 204ENABLE_MEM_PWR_CTRL                      = 0x00000000,
 205DISABLE_MEM_PWR_CTRL                     = 0x00000001,
 206} MEM_PWR_DIS_CTRL;
 207
 208/*
 209 * MEM_PWR_SEL_CTRL enum
 210 */
 211
 212typedef enum MEM_PWR_SEL_CTRL {
 213DYNAMIC_SHUT_DOWN_ENABLE                 = 0x00000000,
 214DYNAMIC_DEEP_SLEEP_ENABLE                = 0x00000001,
 215DYNAMIC_LIGHT_SLEEP_ENABLE               = 0x00000002,
 216} MEM_PWR_SEL_CTRL;
 217
 218/*
 219 * MEM_PWR_SEL_CTRL2 enum
 220 */
 221
 222typedef enum MEM_PWR_SEL_CTRL2 {
 223DYNAMIC_DEEP_SLEEP_EN                    = 0x00000000,
 224DYNAMIC_LIGHT_SLEEP_EN                   = 0x00000001,
 225} MEM_PWR_SEL_CTRL2;
 226
 227/*
 228 * RowSize enum
 229 */
 230
 231typedef enum RowSize {
 232ADDR_CONFIG_1KB_ROW                      = 0x00000000,
 233ADDR_CONFIG_2KB_ROW                      = 0x00000001,
 234ADDR_CONFIG_4KB_ROW                      = 0x00000002,
 235} RowSize;
 236
 237/*
 238 * SurfaceEndian enum
 239 */
 240
 241typedef enum SurfaceEndian {
 242ENDIAN_NONE                              = 0x00000000,
 243ENDIAN_8IN16                             = 0x00000001,
 244ENDIAN_8IN32                             = 0x00000002,
 245ENDIAN_8IN64                             = 0x00000003,
 246} SurfaceEndian;
 247
 248/*
 249 * ArrayMode enum
 250 */
 251
 252typedef enum ArrayMode {
 253ARRAY_LINEAR_GENERAL                     = 0x00000000,
 254ARRAY_LINEAR_ALIGNED                     = 0x00000001,
 255ARRAY_1D_TILED_THIN1                     = 0x00000002,
 256ARRAY_1D_TILED_THICK                     = 0x00000003,
 257ARRAY_2D_TILED_THIN1                     = 0x00000004,
 258ARRAY_PRT_TILED_THIN1                    = 0x00000005,
 259ARRAY_PRT_2D_TILED_THIN1                 = 0x00000006,
 260ARRAY_2D_TILED_THICK                     = 0x00000007,
 261ARRAY_2D_TILED_XTHICK                    = 0x00000008,
 262ARRAY_PRT_TILED_THICK                    = 0x00000009,
 263ARRAY_PRT_2D_TILED_THICK                 = 0x0000000a,
 264ARRAY_PRT_3D_TILED_THIN1                 = 0x0000000b,
 265ARRAY_3D_TILED_THIN1                     = 0x0000000c,
 266ARRAY_3D_TILED_THICK                     = 0x0000000d,
 267ARRAY_3D_TILED_XTHICK                    = 0x0000000e,
 268ARRAY_PRT_3D_TILED_THICK                 = 0x0000000f,
 269} ArrayMode;
 270
 271/*
 272 * NumPipes enum
 273 */
 274
 275typedef enum NumPipes {
 276ADDR_CONFIG_1_PIPE                       = 0x00000000,
 277ADDR_CONFIG_2_PIPE                       = 0x00000001,
 278ADDR_CONFIG_4_PIPE                       = 0x00000002,
 279ADDR_CONFIG_8_PIPE                       = 0x00000003,
 280ADDR_CONFIG_16_PIPE                      = 0x00000004,
 281ADDR_CONFIG_32_PIPE                      = 0x00000005,
 282} NumPipes;
 283
 284/*
 285 * NumBanksConfig enum
 286 */
 287
 288typedef enum NumBanksConfig {
 289ADDR_CONFIG_1_BANK                       = 0x00000000,
 290ADDR_CONFIG_2_BANK                       = 0x00000001,
 291ADDR_CONFIG_4_BANK                       = 0x00000002,
 292ADDR_CONFIG_8_BANK                       = 0x00000003,
 293ADDR_CONFIG_16_BANK                      = 0x00000004,
 294} NumBanksConfig;
 295
 296/*
 297 * PipeInterleaveSize enum
 298 */
 299
 300typedef enum PipeInterleaveSize {
 301ADDR_CONFIG_PIPE_INTERLEAVE_256B         = 0x00000000,
 302ADDR_CONFIG_PIPE_INTERLEAVE_512B         = 0x00000001,
 303ADDR_CONFIG_PIPE_INTERLEAVE_1KB          = 0x00000002,
 304ADDR_CONFIG_PIPE_INTERLEAVE_2KB          = 0x00000003,
 305} PipeInterleaveSize;
 306
 307/*
 308 * BankInterleaveSize enum
 309 */
 310
 311typedef enum BankInterleaveSize {
 312ADDR_CONFIG_BANK_INTERLEAVE_1            = 0x00000000,
 313ADDR_CONFIG_BANK_INTERLEAVE_2            = 0x00000001,
 314ADDR_CONFIG_BANK_INTERLEAVE_4            = 0x00000002,
 315ADDR_CONFIG_BANK_INTERLEAVE_8            = 0x00000003,
 316} BankInterleaveSize;
 317
 318/*
 319 * NumShaderEngines enum
 320 */
 321
 322typedef enum NumShaderEngines {
 323ADDR_CONFIG_1_SHADER_ENGINE              = 0x00000000,
 324ADDR_CONFIG_2_SHADER_ENGINE              = 0x00000001,
 325ADDR_CONFIG_4_SHADER_ENGINE              = 0x00000002,
 326ADDR_CONFIG_8_SHADER_ENGINE              = 0x00000003,
 327} NumShaderEngines;
 328
 329/*
 330 * NumRbPerShaderEngine enum
 331 */
 332
 333typedef enum NumRbPerShaderEngine {
 334ADDR_CONFIG_1_RB_PER_SHADER_ENGINE       = 0x00000000,
 335ADDR_CONFIG_2_RB_PER_SHADER_ENGINE       = 0x00000001,
 336ADDR_CONFIG_4_RB_PER_SHADER_ENGINE       = 0x00000002,
 337} NumRbPerShaderEngine;
 338
 339/*
 340 * NumGPUs enum
 341 */
 342
 343typedef enum NumGPUs {
 344ADDR_CONFIG_1_GPU                        = 0x00000000,
 345ADDR_CONFIG_2_GPU                        = 0x00000001,
 346ADDR_CONFIG_4_GPU                        = 0x00000002,
 347ADDR_CONFIG_8_GPU                        = 0x00000003,
 348} NumGPUs;
 349
 350/*
 351 * NumMaxCompressedFragments enum
 352 */
 353
 354typedef enum NumMaxCompressedFragments {
 355ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS   = 0x00000000,
 356ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS   = 0x00000001,
 357ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS   = 0x00000002,
 358ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS   = 0x00000003,
 359} NumMaxCompressedFragments;
 360
 361/*
 362 * ShaderEngineTileSize enum
 363 */
 364
 365typedef enum ShaderEngineTileSize {
 366ADDR_CONFIG_SE_TILE_16                   = 0x00000000,
 367ADDR_CONFIG_SE_TILE_32                   = 0x00000001,
 368} ShaderEngineTileSize;
 369
 370/*
 371 * MultiGPUTileSize enum
 372 */
 373
 374typedef enum MultiGPUTileSize {
 375ADDR_CONFIG_GPU_TILE_16                  = 0x00000000,
 376ADDR_CONFIG_GPU_TILE_32                  = 0x00000001,
 377ADDR_CONFIG_GPU_TILE_64                  = 0x00000002,
 378ADDR_CONFIG_GPU_TILE_128                 = 0x00000003,
 379} MultiGPUTileSize;
 380
 381/*
 382 * NumLowerPipes enum
 383 */
 384
 385typedef enum NumLowerPipes {
 386ADDR_CONFIG_1_LOWER_PIPES                = 0x00000000,
 387ADDR_CONFIG_2_LOWER_PIPES                = 0x00000001,
 388} NumLowerPipes;
 389
 390/*
 391 * ColorTransform enum
 392 */
 393
 394typedef enum ColorTransform {
 395DCC_CT_AUTO                              = 0x00000000,
 396DCC_CT_NONE                              = 0x00000001,
 397ABGR_TO_A_BG_G_RB                        = 0x00000002,
 398BGRA_TO_BG_G_RB_A                        = 0x00000003,
 399} ColorTransform;
 400
 401/*
 402 * CompareRef enum
 403 */
 404
 405typedef enum CompareRef {
 406REF_NEVER                                = 0x00000000,
 407REF_LESS                                 = 0x00000001,
 408REF_EQUAL                                = 0x00000002,
 409REF_LEQUAL                               = 0x00000003,
 410REF_GREATER                              = 0x00000004,
 411REF_NOTEQUAL                             = 0x00000005,
 412REF_GEQUAL                               = 0x00000006,
 413REF_ALWAYS                               = 0x00000007,
 414} CompareRef;
 415
 416/*
 417 * ReadSize enum
 418 */
 419
 420typedef enum ReadSize {
 421READ_256_BITS                            = 0x00000000,
 422READ_512_BITS                            = 0x00000001,
 423} ReadSize;
 424
 425/*
 426 * DepthFormat enum
 427 */
 428
 429typedef enum DepthFormat {
 430DEPTH_INVALID                            = 0x00000000,
 431DEPTH_16                                 = 0x00000001,
 432DEPTH_X8_24                              = 0x00000002,
 433DEPTH_8_24                               = 0x00000003,
 434DEPTH_X8_24_FLOAT                        = 0x00000004,
 435DEPTH_8_24_FLOAT                         = 0x00000005,
 436DEPTH_32_FLOAT                           = 0x00000006,
 437DEPTH_X24_8_32_FLOAT                     = 0x00000007,
 438} DepthFormat;
 439
 440/*
 441 * ZFormat enum
 442 */
 443
 444typedef enum ZFormat {
 445Z_INVALID                                = 0x00000000,
 446Z_16                                     = 0x00000001,
 447Z_24                                     = 0x00000002,
 448Z_32_FLOAT                               = 0x00000003,
 449} ZFormat;
 450
 451/*
 452 * StencilFormat enum
 453 */
 454
 455typedef enum StencilFormat {
 456STENCIL_INVALID                          = 0x00000000,
 457STENCIL_8                                = 0x00000001,
 458} StencilFormat;
 459
 460/*
 461 * CmaskMode enum
 462 */
 463
 464typedef enum CmaskMode {
 465CMASK_CLEAR_NONE                         = 0x00000000,
 466CMASK_CLEAR_ONE                          = 0x00000001,
 467CMASK_CLEAR_ALL                          = 0x00000002,
 468CMASK_ANY_EXPANDED                       = 0x00000003,
 469CMASK_ALPHA0_FRAG1                       = 0x00000004,
 470CMASK_ALPHA0_FRAG2                       = 0x00000005,
 471CMASK_ALPHA0_FRAG4                       = 0x00000006,
 472CMASK_ALPHA0_FRAGS                       = 0x00000007,
 473CMASK_ALPHA1_FRAG1                       = 0x00000008,
 474CMASK_ALPHA1_FRAG2                       = 0x00000009,
 475CMASK_ALPHA1_FRAG4                       = 0x0000000a,
 476CMASK_ALPHA1_FRAGS                       = 0x0000000b,
 477CMASK_ALPHAX_FRAG1                       = 0x0000000c,
 478CMASK_ALPHAX_FRAG2                       = 0x0000000d,
 479CMASK_ALPHAX_FRAG4                       = 0x0000000e,
 480CMASK_ALPHAX_FRAGS                       = 0x0000000f,
 481} CmaskMode;
 482
 483/*
 484 * QuadExportFormat enum
 485 */
 486
 487typedef enum QuadExportFormat {
 488EXPORT_UNUSED                            = 0x00000000,
 489EXPORT_32_R                              = 0x00000001,
 490EXPORT_32_GR                             = 0x00000002,
 491EXPORT_32_AR                             = 0x00000003,
 492EXPORT_FP16_ABGR                         = 0x00000004,
 493EXPORT_UNSIGNED16_ABGR                   = 0x00000005,
 494EXPORT_SIGNED16_ABGR                     = 0x00000006,
 495EXPORT_32_ABGR                           = 0x00000007,
 496EXPORT_32BPP_8PIX                        = 0x00000008,
 497EXPORT_16_16_UNSIGNED_8PIX               = 0x00000009,
 498EXPORT_16_16_SIGNED_8PIX                 = 0x0000000a,
 499EXPORT_16_16_FLOAT_8PIX                  = 0x0000000b,
 500} QuadExportFormat;
 501
 502/*
 503 * QuadExportFormatOld enum
 504 */
 505
 506typedef enum QuadExportFormatOld {
 507EXPORT_4P_32BPC_ABGR                     = 0x00000000,
 508EXPORT_4P_16BPC_ABGR                     = 0x00000001,
 509EXPORT_4P_32BPC_GR                       = 0x00000002,
 510EXPORT_4P_32BPC_AR                       = 0x00000003,
 511EXPORT_2P_32BPC_ABGR                     = 0x00000004,
 512EXPORT_8P_32BPC_R                        = 0x00000005,
 513} QuadExportFormatOld;
 514
 515/*
 516 * ColorFormat enum
 517 */
 518
 519typedef enum ColorFormat {
 520COLOR_INVALID                            = 0x00000000,
 521COLOR_8                                  = 0x00000001,
 522COLOR_16                                 = 0x00000002,
 523COLOR_8_8                                = 0x00000003,
 524COLOR_32                                 = 0x00000004,
 525COLOR_16_16                              = 0x00000005,
 526COLOR_10_11_11                           = 0x00000006,
 527COLOR_11_11_10                           = 0x00000007,
 528COLOR_10_10_10_2                         = 0x00000008,
 529COLOR_2_10_10_10                         = 0x00000009,
 530COLOR_8_8_8_8                            = 0x0000000a,
 531COLOR_32_32                              = 0x0000000b,
 532COLOR_16_16_16_16                        = 0x0000000c,
 533COLOR_RESERVED_13                        = 0x0000000d,
 534COLOR_32_32_32_32                        = 0x0000000e,
 535COLOR_RESERVED_15                        = 0x0000000f,
 536COLOR_5_6_5                              = 0x00000010,
 537COLOR_1_5_5_5                            = 0x00000011,
 538COLOR_5_5_5_1                            = 0x00000012,
 539COLOR_4_4_4_4                            = 0x00000013,
 540COLOR_8_24                               = 0x00000014,
 541COLOR_24_8                               = 0x00000015,
 542COLOR_X24_8_32_FLOAT                     = 0x00000016,
 543COLOR_RESERVED_23                        = 0x00000017,
 544COLOR_RESERVED_24                        = 0x00000018,
 545COLOR_RESERVED_25                        = 0x00000019,
 546COLOR_RESERVED_26                        = 0x0000001a,
 547COLOR_RESERVED_27                        = 0x0000001b,
 548COLOR_RESERVED_28                        = 0x0000001c,
 549COLOR_RESERVED_29                        = 0x0000001d,
 550COLOR_RESERVED_30                        = 0x0000001e,
 551COLOR_2_10_10_10_6E4                     = 0x0000001f,
 552} ColorFormat;
 553
 554/*
 555 * SurfaceFormat enum
 556 */
 557
 558typedef enum SurfaceFormat {
 559FMT_INVALID                              = 0x00000000,
 560FMT_8                                    = 0x00000001,
 561FMT_16                                   = 0x00000002,
 562FMT_8_8                                  = 0x00000003,
 563FMT_32                                   = 0x00000004,
 564FMT_16_16                                = 0x00000005,
 565FMT_10_11_11                             = 0x00000006,
 566FMT_11_11_10                             = 0x00000007,
 567FMT_10_10_10_2                           = 0x00000008,
 568FMT_2_10_10_10                           = 0x00000009,
 569FMT_8_8_8_8                              = 0x0000000a,
 570FMT_32_32                                = 0x0000000b,
 571FMT_16_16_16_16                          = 0x0000000c,
 572FMT_32_32_32                             = 0x0000000d,
 573FMT_32_32_32_32                          = 0x0000000e,
 574FMT_RESERVED_4                           = 0x0000000f,
 575FMT_5_6_5                                = 0x00000010,
 576FMT_1_5_5_5                              = 0x00000011,
 577FMT_5_5_5_1                              = 0x00000012,
 578FMT_4_4_4_4                              = 0x00000013,
 579FMT_8_24                                 = 0x00000014,
 580FMT_24_8                                 = 0x00000015,
 581FMT_X24_8_32_FLOAT                       = 0x00000016,
 582FMT_RESERVED_33                          = 0x00000017,
 583FMT_11_11_10_FLOAT                       = 0x00000018,
 584FMT_16_FLOAT                             = 0x00000019,
 585FMT_32_FLOAT                             = 0x0000001a,
 586FMT_16_16_FLOAT                          = 0x0000001b,
 587FMT_8_24_FLOAT                           = 0x0000001c,
 588FMT_24_8_FLOAT                           = 0x0000001d,
 589FMT_32_32_FLOAT                          = 0x0000001e,
 590FMT_10_11_11_FLOAT                       = 0x0000001f,
 591FMT_16_16_16_16_FLOAT                    = 0x00000020,
 592FMT_3_3_2                                = 0x00000021,
 593FMT_6_5_5                                = 0x00000022,
 594FMT_32_32_32_32_FLOAT                    = 0x00000023,
 595FMT_RESERVED_36                          = 0x00000024,
 596FMT_1                                    = 0x00000025,
 597FMT_1_REVERSED                           = 0x00000026,
 598FMT_GB_GR                                = 0x00000027,
 599FMT_BG_RG                                = 0x00000028,
 600FMT_32_AS_8                              = 0x00000029,
 601FMT_32_AS_8_8                            = 0x0000002a,
 602FMT_5_9_9_9_SHAREDEXP                    = 0x0000002b,
 603FMT_8_8_8                                = 0x0000002c,
 604FMT_16_16_16                             = 0x0000002d,
 605FMT_16_16_16_FLOAT                       = 0x0000002e,
 606FMT_4_4                                  = 0x0000002f,
 607FMT_32_32_32_FLOAT                       = 0x00000030,
 608FMT_BC1                                  = 0x00000031,
 609FMT_BC2                                  = 0x00000032,
 610FMT_BC3                                  = 0x00000033,
 611FMT_BC4                                  = 0x00000034,
 612FMT_BC5                                  = 0x00000035,
 613FMT_BC6                                  = 0x00000036,
 614FMT_BC7                                  = 0x00000037,
 615FMT_32_AS_32_32_32_32                    = 0x00000038,
 616FMT_APC3                                 = 0x00000039,
 617FMT_APC4                                 = 0x0000003a,
 618FMT_APC5                                 = 0x0000003b,
 619FMT_APC6                                 = 0x0000003c,
 620FMT_APC7                                 = 0x0000003d,
 621FMT_CTX1                                 = 0x0000003e,
 622FMT_RESERVED_63                          = 0x0000003f,
 623} SurfaceFormat;
 624
 625/*
 626 * BUF_DATA_FORMAT enum
 627 */
 628
 629typedef enum BUF_DATA_FORMAT {
 630BUF_DATA_FORMAT_INVALID                  = 0x00000000,
 631BUF_DATA_FORMAT_8                        = 0x00000001,
 632BUF_DATA_FORMAT_16                       = 0x00000002,
 633BUF_DATA_FORMAT_8_8                      = 0x00000003,
 634BUF_DATA_FORMAT_32                       = 0x00000004,
 635BUF_DATA_FORMAT_16_16                    = 0x00000005,
 636BUF_DATA_FORMAT_10_11_11                 = 0x00000006,
 637BUF_DATA_FORMAT_11_11_10                 = 0x00000007,
 638BUF_DATA_FORMAT_10_10_10_2               = 0x00000008,
 639BUF_DATA_FORMAT_2_10_10_10               = 0x00000009,
 640BUF_DATA_FORMAT_8_8_8_8                  = 0x0000000a,
 641BUF_DATA_FORMAT_32_32                    = 0x0000000b,
 642BUF_DATA_FORMAT_16_16_16_16              = 0x0000000c,
 643BUF_DATA_FORMAT_32_32_32                 = 0x0000000d,
 644BUF_DATA_FORMAT_32_32_32_32              = 0x0000000e,
 645BUF_DATA_FORMAT_RESERVED_15              = 0x0000000f,
 646} BUF_DATA_FORMAT;
 647
 648/*
 649 * IMG_DATA_FORMAT enum
 650 */
 651
 652typedef enum IMG_DATA_FORMAT {
 653IMG_DATA_FORMAT_INVALID                  = 0x00000000,
 654IMG_DATA_FORMAT_8                        = 0x00000001,
 655IMG_DATA_FORMAT_16                       = 0x00000002,
 656IMG_DATA_FORMAT_8_8                      = 0x00000003,
 657IMG_DATA_FORMAT_32                       = 0x00000004,
 658IMG_DATA_FORMAT_16_16                    = 0x00000005,
 659IMG_DATA_FORMAT_10_11_11                 = 0x00000006,
 660IMG_DATA_FORMAT_11_11_10                 = 0x00000007,
 661IMG_DATA_FORMAT_10_10_10_2               = 0x00000008,
 662IMG_DATA_FORMAT_2_10_10_10               = 0x00000009,
 663IMG_DATA_FORMAT_8_8_8_8                  = 0x0000000a,
 664IMG_DATA_FORMAT_32_32                    = 0x0000000b,
 665IMG_DATA_FORMAT_16_16_16_16              = 0x0000000c,
 666IMG_DATA_FORMAT_32_32_32                 = 0x0000000d,
 667IMG_DATA_FORMAT_32_32_32_32              = 0x0000000e,
 668IMG_DATA_FORMAT_RESERVED_15              = 0x0000000f,
 669IMG_DATA_FORMAT_5_6_5                    = 0x00000010,
 670IMG_DATA_FORMAT_1_5_5_5                  = 0x00000011,
 671IMG_DATA_FORMAT_5_5_5_1                  = 0x00000012,
 672IMG_DATA_FORMAT_4_4_4_4                  = 0x00000013,
 673IMG_DATA_FORMAT_8_24                     = 0x00000014,
 674IMG_DATA_FORMAT_24_8                     = 0x00000015,
 675IMG_DATA_FORMAT_X24_8_32                 = 0x00000016,
 676IMG_DATA_FORMAT_8_AS_8_8_8_8             = 0x00000017,
 677IMG_DATA_FORMAT_ETC2_RGB                 = 0x00000018,
 678IMG_DATA_FORMAT_ETC2_RGBA                = 0x00000019,
 679IMG_DATA_FORMAT_ETC2_R                   = 0x0000001a,
 680IMG_DATA_FORMAT_ETC2_RG                  = 0x0000001b,
 681IMG_DATA_FORMAT_ETC2_RGBA1               = 0x0000001c,
 682IMG_DATA_FORMAT_RESERVED_29              = 0x0000001d,
 683IMG_DATA_FORMAT_RESERVED_30              = 0x0000001e,
 684IMG_DATA_FORMAT_6E4                      = 0x0000001f,
 685IMG_DATA_FORMAT_GB_GR                    = 0x00000020,
 686IMG_DATA_FORMAT_BG_RG                    = 0x00000021,
 687IMG_DATA_FORMAT_5_9_9_9                  = 0x00000022,
 688IMG_DATA_FORMAT_BC1                      = 0x00000023,
 689IMG_DATA_FORMAT_BC2                      = 0x00000024,
 690IMG_DATA_FORMAT_BC3                      = 0x00000025,
 691IMG_DATA_FORMAT_BC4                      = 0x00000026,
 692IMG_DATA_FORMAT_BC5                      = 0x00000027,
 693IMG_DATA_FORMAT_BC6                      = 0x00000028,
 694IMG_DATA_FORMAT_BC7                      = 0x00000029,
 695IMG_DATA_FORMAT_16_AS_32_32              = 0x0000002a,
 696IMG_DATA_FORMAT_16_AS_16_16_16_16        = 0x0000002b,
 697IMG_DATA_FORMAT_16_AS_32_32_32_32        = 0x0000002c,
 698IMG_DATA_FORMAT_FMASK                    = 0x0000002d,
 699IMG_DATA_FORMAT_ASTC_2D_LDR              = 0x0000002e,
 700IMG_DATA_FORMAT_ASTC_2D_HDR              = 0x0000002f,
 701IMG_DATA_FORMAT_ASTC_2D_LDR_SRGB         = 0x00000030,
 702IMG_DATA_FORMAT_ASTC_3D_LDR              = 0x00000031,
 703IMG_DATA_FORMAT_ASTC_3D_HDR              = 0x00000032,
 704IMG_DATA_FORMAT_ASTC_3D_LDR_SRGB         = 0x00000033,
 705IMG_DATA_FORMAT_N_IN_16                  = 0x00000034,
 706IMG_DATA_FORMAT_N_IN_16_16               = 0x00000035,
 707IMG_DATA_FORMAT_N_IN_16_16_16_16         = 0x00000036,
 708IMG_DATA_FORMAT_N_IN_16_AS_16_16_16_16   = 0x00000037,
 709IMG_DATA_FORMAT_RESERVED_56              = 0x00000038,
 710IMG_DATA_FORMAT_4_4                      = 0x00000039,
 711IMG_DATA_FORMAT_6_5_5                    = 0x0000003a,
 712IMG_DATA_FORMAT_RESERVED_59              = 0x0000003b,
 713IMG_DATA_FORMAT_RESERVED_60              = 0x0000003c,
 714IMG_DATA_FORMAT_8_AS_32                  = 0x0000003d,
 715IMG_DATA_FORMAT_8_AS_32_32               = 0x0000003e,
 716IMG_DATA_FORMAT_32_AS_32_32_32_32        = 0x0000003f,
 717} IMG_DATA_FORMAT;
 718
 719/*
 720 * BUF_NUM_FORMAT enum
 721 */
 722
 723typedef enum BUF_NUM_FORMAT {
 724BUF_NUM_FORMAT_UNORM                     = 0x00000000,
 725BUF_NUM_FORMAT_SNORM                     = 0x00000001,
 726BUF_NUM_FORMAT_USCALED                   = 0x00000002,
 727BUF_NUM_FORMAT_SSCALED                   = 0x00000003,
 728BUF_NUM_FORMAT_UINT                      = 0x00000004,
 729BUF_NUM_FORMAT_SINT                      = 0x00000005,
 730BUF_NUM_FORMAT_UNORM_UINT                = 0x00000006,
 731BUF_NUM_FORMAT_FLOAT                     = 0x00000007,
 732} BUF_NUM_FORMAT;
 733
 734/*
 735 * IMG_NUM_FORMAT enum
 736 */
 737
 738typedef enum IMG_NUM_FORMAT {
 739IMG_NUM_FORMAT_UNORM                     = 0x00000000,
 740IMG_NUM_FORMAT_SNORM                     = 0x00000001,
 741IMG_NUM_FORMAT_USCALED                   = 0x00000002,
 742IMG_NUM_FORMAT_SSCALED                   = 0x00000003,
 743IMG_NUM_FORMAT_UINT                      = 0x00000004,
 744IMG_NUM_FORMAT_SINT                      = 0x00000005,
 745IMG_NUM_FORMAT_UNORM_UINT                = 0x00000006,
 746IMG_NUM_FORMAT_FLOAT                     = 0x00000007,
 747IMG_NUM_FORMAT_RESERVED_8                = 0x00000008,
 748IMG_NUM_FORMAT_SRGB                      = 0x00000009,
 749IMG_NUM_FORMAT_RESERVED_10               = 0x0000000a,
 750IMG_NUM_FORMAT_RESERVED_11               = 0x0000000b,
 751IMG_NUM_FORMAT_RESERVED_12               = 0x0000000c,
 752IMG_NUM_FORMAT_RESERVED_13               = 0x0000000d,
 753IMG_NUM_FORMAT_RESERVED_14               = 0x0000000e,
 754IMG_NUM_FORMAT_RESERVED_15               = 0x0000000f,
 755} IMG_NUM_FORMAT;
 756
 757/*
 758 * IMG_NUM_FORMAT_FMASK enum
 759 */
 760
 761typedef enum IMG_NUM_FORMAT_FMASK {
 762IMG_NUM_FORMAT_FMASK_8_2_1               = 0x00000000,
 763IMG_NUM_FORMAT_FMASK_8_4_1               = 0x00000001,
 764IMG_NUM_FORMAT_FMASK_8_8_1               = 0x00000002,
 765IMG_NUM_FORMAT_FMASK_8_2_2               = 0x00000003,
 766IMG_NUM_FORMAT_FMASK_8_4_2               = 0x00000004,
 767IMG_NUM_FORMAT_FMASK_8_4_4               = 0x00000005,
 768IMG_NUM_FORMAT_FMASK_16_16_1             = 0x00000006,
 769IMG_NUM_FORMAT_FMASK_16_8_2              = 0x00000007,
 770IMG_NUM_FORMAT_FMASK_32_16_2             = 0x00000008,
 771IMG_NUM_FORMAT_FMASK_32_8_4              = 0x00000009,
 772IMG_NUM_FORMAT_FMASK_32_8_8              = 0x0000000a,
 773IMG_NUM_FORMAT_FMASK_64_16_4             = 0x0000000b,
 774IMG_NUM_FORMAT_FMASK_64_16_8             = 0x0000000c,
 775IMG_NUM_FORMAT_FMASK_RESERVED_13         = 0x0000000d,
 776IMG_NUM_FORMAT_FMASK_RESERVED_14         = 0x0000000e,
 777IMG_NUM_FORMAT_FMASK_RESERVED_15         = 0x0000000f,
 778} IMG_NUM_FORMAT_FMASK;
 779
 780/*
 781 * IMG_NUM_FORMAT_N_IN_16 enum
 782 */
 783
 784typedef enum IMG_NUM_FORMAT_N_IN_16 {
 785IMG_NUM_FORMAT_N_IN_16_RESERVED_0        = 0x00000000,
 786IMG_NUM_FORMAT_N_IN_16_UNORM_10          = 0x00000001,
 787IMG_NUM_FORMAT_N_IN_16_UNORM_9           = 0x00000002,
 788IMG_NUM_FORMAT_N_IN_16_RESERVED_3        = 0x00000003,
 789IMG_NUM_FORMAT_N_IN_16_UINT_10           = 0x00000004,
 790IMG_NUM_FORMAT_N_IN_16_UINT_9            = 0x00000005,
 791IMG_NUM_FORMAT_N_IN_16_RESERVED_6        = 0x00000006,
 792IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10     = 0x00000007,
 793IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9      = 0x00000008,
 794IMG_NUM_FORMAT_N_IN_16_RESERVED_9        = 0x00000009,
 795IMG_NUM_FORMAT_N_IN_16_RESERVED_10       = 0x0000000a,
 796IMG_NUM_FORMAT_N_IN_16_RESERVED_11       = 0x0000000b,
 797IMG_NUM_FORMAT_N_IN_16_RESERVED_12       = 0x0000000c,
 798IMG_NUM_FORMAT_N_IN_16_RESERVED_13       = 0x0000000d,
 799IMG_NUM_FORMAT_N_IN_16_RESERVED_14       = 0x0000000e,
 800IMG_NUM_FORMAT_N_IN_16_RESERVED_15       = 0x0000000f,
 801} IMG_NUM_FORMAT_N_IN_16;
 802
 803/*
 804 * IMG_NUM_FORMAT_ASTC_2D enum
 805 */
 806
 807typedef enum IMG_NUM_FORMAT_ASTC_2D {
 808IMG_NUM_FORMAT_ASTC_2D_4x4               = 0x00000000,
 809IMG_NUM_FORMAT_ASTC_2D_5x4               = 0x00000001,
 810IMG_NUM_FORMAT_ASTC_2D_5x5               = 0x00000002,
 811IMG_NUM_FORMAT_ASTC_2D_6x5               = 0x00000003,
 812IMG_NUM_FORMAT_ASTC_2D_6x6               = 0x00000004,
 813IMG_NUM_FORMAT_ASTC_2D_8x5               = 0x00000005,
 814IMG_NUM_FORMAT_ASTC_2D_8x6               = 0x00000006,
 815IMG_NUM_FORMAT_ASTC_2D_8x8               = 0x00000007,
 816IMG_NUM_FORMAT_ASTC_2D_10x5              = 0x00000008,
 817IMG_NUM_FORMAT_ASTC_2D_10x6              = 0x00000009,
 818IMG_NUM_FORMAT_ASTC_2D_10x8              = 0x0000000a,
 819IMG_NUM_FORMAT_ASTC_2D_10x10             = 0x0000000b,
 820IMG_NUM_FORMAT_ASTC_2D_12x10             = 0x0000000c,
 821IMG_NUM_FORMAT_ASTC_2D_12x12             = 0x0000000d,
 822IMG_NUM_FORMAT_ASTC_2D_RESERVED_14       = 0x0000000e,
 823IMG_NUM_FORMAT_ASTC_2D_RESERVED_15       = 0x0000000f,
 824} IMG_NUM_FORMAT_ASTC_2D;
 825
 826/*
 827 * IMG_NUM_FORMAT_ASTC_3D enum
 828 */
 829
 830typedef enum IMG_NUM_FORMAT_ASTC_3D {
 831IMG_NUM_FORMAT_ASTC_3D_3x3x3             = 0x00000000,
 832IMG_NUM_FORMAT_ASTC_3D_4x3x3             = 0x00000001,
 833IMG_NUM_FORMAT_ASTC_3D_4x4x3             = 0x00000002,
 834IMG_NUM_FORMAT_ASTC_3D_4x4x4             = 0x00000003,
 835IMG_NUM_FORMAT_ASTC_3D_5x4x4             = 0x00000004,
 836IMG_NUM_FORMAT_ASTC_3D_5x5x4             = 0x00000005,
 837IMG_NUM_FORMAT_ASTC_3D_5x5x5             = 0x00000006,
 838IMG_NUM_FORMAT_ASTC_3D_6x5x5             = 0x00000007,
 839IMG_NUM_FORMAT_ASTC_3D_6x6x5             = 0x00000008,
 840IMG_NUM_FORMAT_ASTC_3D_6x6x6             = 0x00000009,
 841IMG_NUM_FORMAT_ASTC_3D_RESERVED_10       = 0x0000000a,
 842IMG_NUM_FORMAT_ASTC_3D_RESERVED_11       = 0x0000000b,
 843IMG_NUM_FORMAT_ASTC_3D_RESERVED_12       = 0x0000000c,
 844IMG_NUM_FORMAT_ASTC_3D_RESERVED_13       = 0x0000000d,
 845IMG_NUM_FORMAT_ASTC_3D_RESERVED_14       = 0x0000000e,
 846IMG_NUM_FORMAT_ASTC_3D_RESERVED_15       = 0x0000000f,
 847} IMG_NUM_FORMAT_ASTC_3D;
 848
 849/*
 850 * TileType enum
 851 */
 852
 853typedef enum TileType {
 854ARRAY_COLOR_TILE                         = 0x00000000,
 855ARRAY_DEPTH_TILE                         = 0x00000001,
 856} TileType;
 857
 858/*
 859 * NonDispTilingOrder enum
 860 */
 861
 862typedef enum NonDispTilingOrder {
 863ADDR_SURF_MICRO_TILING_DISPLAY           = 0x00000000,
 864ADDR_SURF_MICRO_TILING_NON_DISPLAY       = 0x00000001,
 865} NonDispTilingOrder;
 866
 867/*
 868 * MicroTileMode enum
 869 */
 870
 871typedef enum MicroTileMode {
 872ADDR_SURF_DISPLAY_MICRO_TILING           = 0x00000000,
 873ADDR_SURF_THIN_MICRO_TILING              = 0x00000001,
 874ADDR_SURF_DEPTH_MICRO_TILING             = 0x00000002,
 875ADDR_SURF_ROTATED_MICRO_TILING           = 0x00000003,
 876ADDR_SURF_THICK_MICRO_TILING             = 0x00000004,
 877} MicroTileMode;
 878
 879/*
 880 * TileSplit enum
 881 */
 882
 883typedef enum TileSplit {
 884ADDR_SURF_TILE_SPLIT_64B                 = 0x00000000,
 885ADDR_SURF_TILE_SPLIT_128B                = 0x00000001,
 886ADDR_SURF_TILE_SPLIT_256B                = 0x00000002,
 887ADDR_SURF_TILE_SPLIT_512B                = 0x00000003,
 888ADDR_SURF_TILE_SPLIT_1KB                 = 0x00000004,
 889ADDR_SURF_TILE_SPLIT_2KB                 = 0x00000005,
 890ADDR_SURF_TILE_SPLIT_4KB                 = 0x00000006,
 891} TileSplit;
 892
 893/*
 894 * SampleSplit enum
 895 */
 896
 897typedef enum SampleSplit {
 898ADDR_SURF_SAMPLE_SPLIT_1                 = 0x00000000,
 899ADDR_SURF_SAMPLE_SPLIT_2                 = 0x00000001,
 900ADDR_SURF_SAMPLE_SPLIT_4                 = 0x00000002,
 901ADDR_SURF_SAMPLE_SPLIT_8                 = 0x00000003,
 902} SampleSplit;
 903
 904/*
 905 * PipeConfig enum
 906 */
 907
 908typedef enum PipeConfig {
 909ADDR_SURF_P2                             = 0x00000000,
 910ADDR_SURF_P2_RESERVED0                   = 0x00000001,
 911ADDR_SURF_P2_RESERVED1                   = 0x00000002,
 912ADDR_SURF_P2_RESERVED2                   = 0x00000003,
 913ADDR_SURF_P4_8x16                        = 0x00000004,
 914ADDR_SURF_P4_16x16                       = 0x00000005,
 915ADDR_SURF_P4_16x32                       = 0x00000006,
 916ADDR_SURF_P4_32x32                       = 0x00000007,
 917ADDR_SURF_P8_16x16_8x16                  = 0x00000008,
 918ADDR_SURF_P8_16x32_8x16                  = 0x00000009,
 919ADDR_SURF_P8_32x32_8x16                  = 0x0000000a,
 920ADDR_SURF_P8_16x32_16x16                 = 0x0000000b,
 921ADDR_SURF_P8_32x32_16x16                 = 0x0000000c,
 922ADDR_SURF_P8_32x32_16x32                 = 0x0000000d,
 923ADDR_SURF_P8_32x64_32x32                 = 0x0000000e,
 924ADDR_SURF_P8_RESERVED0                   = 0x0000000f,
 925ADDR_SURF_P16_32x32_8x16                 = 0x00000010,
 926ADDR_SURF_P16_32x32_16x16                = 0x00000011,
 927} PipeConfig;
 928
 929/*
 930 * SeEnable enum
 931 */
 932
 933typedef enum SeEnable {
 934ADDR_CONFIG_DISABLE_SE                   = 0x00000000,
 935ADDR_CONFIG_ENABLE_SE                    = 0x00000001,
 936} SeEnable;
 937
 938/*
 939 * NumBanks enum
 940 */
 941
 942typedef enum NumBanks {
 943ADDR_SURF_2_BANK                         = 0x00000000,
 944ADDR_SURF_4_BANK                         = 0x00000001,
 945ADDR_SURF_8_BANK                         = 0x00000002,
 946ADDR_SURF_16_BANK                        = 0x00000003,
 947} NumBanks;
 948
 949/*
 950 * BankWidth enum
 951 */
 952
 953typedef enum BankWidth {
 954ADDR_SURF_BANK_WIDTH_1                   = 0x00000000,
 955ADDR_SURF_BANK_WIDTH_2                   = 0x00000001,
 956ADDR_SURF_BANK_WIDTH_4                   = 0x00000002,
 957ADDR_SURF_BANK_WIDTH_8                   = 0x00000003,
 958} BankWidth;
 959
 960/*
 961 * BankHeight enum
 962 */
 963
 964typedef enum BankHeight {
 965ADDR_SURF_BANK_HEIGHT_1                  = 0x00000000,
 966ADDR_SURF_BANK_HEIGHT_2                  = 0x00000001,
 967ADDR_SURF_BANK_HEIGHT_4                  = 0x00000002,
 968ADDR_SURF_BANK_HEIGHT_8                  = 0x00000003,
 969} BankHeight;
 970
 971/*
 972 * BankWidthHeight enum
 973 */
 974
 975typedef enum BankWidthHeight {
 976ADDR_SURF_BANK_WH_1                      = 0x00000000,
 977ADDR_SURF_BANK_WH_2                      = 0x00000001,
 978ADDR_SURF_BANK_WH_4                      = 0x00000002,
 979ADDR_SURF_BANK_WH_8                      = 0x00000003,
 980} BankWidthHeight;
 981
 982/*
 983 * MacroTileAspect enum
 984 */
 985
 986typedef enum MacroTileAspect {
 987ADDR_SURF_MACRO_ASPECT_1                 = 0x00000000,
 988ADDR_SURF_MACRO_ASPECT_2                 = 0x00000001,
 989ADDR_SURF_MACRO_ASPECT_4                 = 0x00000002,
 990ADDR_SURF_MACRO_ASPECT_8                 = 0x00000003,
 991} MacroTileAspect;
 992
 993/*
 994 * GATCL1RequestType enum
 995 */
 996
 997typedef enum GATCL1RequestType {
 998GATCL1_TYPE_NORMAL                       = 0x00000000,
 999GATCL1_TYPE_SHOOTDOWN                    = 0x00000001,
1000GATCL1_TYPE_BYPASS                       = 0x00000002,
1001} GATCL1RequestType;
1002
1003/*
1004 * UTCL1RequestType enum
1005 */
1006
1007typedef enum UTCL1RequestType {
1008UTCL1_TYPE_NORMAL                        = 0x00000000,
1009UTCL1_TYPE_SHOOTDOWN                     = 0x00000001,
1010UTCL1_TYPE_BYPASS                        = 0x00000002,
1011} UTCL1RequestType;
1012
1013/*
1014 * UTCL1FaultType enum
1015 */
1016
1017typedef enum UTCL1FaultType {
1018UTCL1_XNACK_SUCCESS                      = 0x00000000,
1019UTCL1_XNACK_RETRY                        = 0x00000001,
1020UTCL1_XNACK_PRT                          = 0x00000002,
1021UTCL1_XNACK_NO_RETRY                     = 0x00000003,
1022} UTCL1FaultType;
1023
1024/*
1025 * TCC_CACHE_POLICIES enum
1026 */
1027
1028typedef enum TCC_CACHE_POLICIES {
1029TCC_CACHE_POLICY_LRU                     = 0x00000000,
1030TCC_CACHE_POLICY_STREAM                  = 0x00000001,
1031} TCC_CACHE_POLICIES;
1032
1033/*
1034 * MTYPE enum
1035 */
1036
1037typedef enum MTYPE {
1038MTYPE_NC                                 = 0x00000000,
1039MTYPE_WC                                 = 0x00000001,
1040MTYPE_RW                                 = 0x00000001,
1041MTYPE_CC                                 = 0x00000002,
1042MTYPE_UC                                 = 0x00000003,
1043} MTYPE;
1044
1045/*
1046 * RMI_CID enum
1047 */
1048
1049typedef enum RMI_CID {
1050RMI_CID_CC                               = 0x00000000,
1051RMI_CID_FC                               = 0x00000001,
1052RMI_CID_CM                               = 0x00000002,
1053RMI_CID_DC                               = 0x00000003,
1054RMI_CID_Z                                = 0x00000004,
1055RMI_CID_S                                = 0x00000005,
1056RMI_CID_TILE                             = 0x00000006,
1057RMI_CID_ZPCPSD                           = 0x00000007,
1058} RMI_CID;
1059
1060/*
1061 * PERFMON_COUNTER_MODE enum
1062 */
1063
1064typedef enum PERFMON_COUNTER_MODE {
1065PERFMON_COUNTER_MODE_ACCUM               = 0x00000000,
1066PERFMON_COUNTER_MODE_ACTIVE_CYCLES       = 0x00000001,
1067PERFMON_COUNTER_MODE_MAX                 = 0x00000002,
1068PERFMON_COUNTER_MODE_DIRTY               = 0x00000003,
1069PERFMON_COUNTER_MODE_SAMPLE              = 0x00000004,
1070PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT  = 0x00000005,
1071PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT  = 0x00000006,
1072PERFMON_COUNTER_MODE_CYCLES_GE_HI        = 0x00000007,
1073PERFMON_COUNTER_MODE_CYCLES_EQ_HI        = 0x00000008,
1074PERFMON_COUNTER_MODE_INACTIVE_CYCLES     = 0x00000009,
1075PERFMON_COUNTER_MODE_RESERVED            = 0x0000000f,
1076} PERFMON_COUNTER_MODE;
1077
1078/*
1079 * PERFMON_SPM_MODE enum
1080 */
1081
1082typedef enum PERFMON_SPM_MODE {
1083PERFMON_SPM_MODE_OFF                     = 0x00000000,
1084PERFMON_SPM_MODE_16BIT_CLAMP             = 0x00000001,
1085PERFMON_SPM_MODE_16BIT_NO_CLAMP          = 0x00000002,
1086PERFMON_SPM_MODE_32BIT_CLAMP             = 0x00000003,
1087PERFMON_SPM_MODE_32BIT_NO_CLAMP          = 0x00000004,
1088PERFMON_SPM_MODE_RESERVED_5              = 0x00000005,
1089PERFMON_SPM_MODE_RESERVED_6              = 0x00000006,
1090PERFMON_SPM_MODE_RESERVED_7              = 0x00000007,
1091PERFMON_SPM_MODE_TEST_MODE_0             = 0x00000008,
1092PERFMON_SPM_MODE_TEST_MODE_1             = 0x00000009,
1093PERFMON_SPM_MODE_TEST_MODE_2             = 0x0000000a,
1094} PERFMON_SPM_MODE;
1095
1096/*
1097 * SurfaceTiling enum
1098 */
1099
1100typedef enum SurfaceTiling {
1101ARRAY_LINEAR                             = 0x00000000,
1102ARRAY_TILED                              = 0x00000001,
1103} SurfaceTiling;
1104
1105/*
1106 * SurfaceArray enum
1107 */
1108
1109typedef enum SurfaceArray {
1110ARRAY_1D                                 = 0x00000000,
1111ARRAY_2D                                 = 0x00000001,
1112ARRAY_3D                                 = 0x00000002,
1113ARRAY_3D_SLICE                           = 0x00000003,
1114} SurfaceArray;
1115
1116/*
1117 * ColorArray enum
1118 */
1119
1120typedef enum ColorArray {
1121ARRAY_2D_ALT_COLOR                       = 0x00000000,
1122ARRAY_2D_COLOR                           = 0x00000001,
1123ARRAY_3D_SLICE_COLOR                     = 0x00000003,
1124} ColorArray;
1125
1126/*
1127 * DepthArray enum
1128 */
1129
1130typedef enum DepthArray {
1131ARRAY_2D_ALT_DEPTH                       = 0x00000000,
1132ARRAY_2D_DEPTH                           = 0x00000001,
1133} DepthArray;
1134
1135/*
1136 * ENUM_NUM_SIMD_PER_CU enum
1137 */
1138
1139typedef enum ENUM_NUM_SIMD_PER_CU {
1140NUM_SIMD_PER_CU                          = 0x00000004,
1141} ENUM_NUM_SIMD_PER_CU;
1142
1143/*
1144 * DSM_ENABLE_ERROR_INJECT enum
1145 */
1146
1147typedef enum DSM_ENABLE_ERROR_INJECT {
1148DSM_ENABLE_ERROR_INJECT_FED_IN           = 0x00000000,
1149DSM_ENABLE_ERROR_INJECT_SINGLE           = 0x00000001,
1150DSM_ENABLE_ERROR_INJECT_DOUBLE           = 0x00000002,
1151DSM_ENABLE_ERROR_INJECT_DOUBLE_LIMITED   = 0x00000003,
1152} DSM_ENABLE_ERROR_INJECT;
1153
1154/*
1155 * DSM_SELECT_INJECT_DELAY enum
1156 */
1157
1158typedef enum DSM_SELECT_INJECT_DELAY {
1159DSM_SELECT_INJECT_DELAY_NO_DELAY         = 0x00000000,
1160DSM_SELECT_INJECT_DELAY_DELAY_ERROR      = 0x00000001,
1161} DSM_SELECT_INJECT_DELAY;
1162
1163/*
1164 * SWIZZLE_TYPE_ENUM enum
1165 */
1166
1167typedef enum SWIZZLE_TYPE_ENUM {
1168SW_Z                                     = 0x00000000,
1169SW_S                                     = 0x00000001,
1170SW_D                                     = 0x00000002,
1171SW_R                                     = 0x00000003,
1172SW_L                                     = 0x00000004,
1173} SWIZZLE_TYPE_ENUM;
1174
1175/*
1176 * TC_MICRO_TILE_MODE enum
1177 */
1178
1179typedef enum TC_MICRO_TILE_MODE {
1180MICRO_TILE_MODE_LINEAR                   = 0x00000000,
1181MICRO_TILE_MODE_ROTATED                  = 0x00000001,
1182MICRO_TILE_MODE_STD_2D                   = 0x00000002,
1183MICRO_TILE_MODE_STD_3D                   = 0x00000003,
1184MICRO_TILE_MODE_DISPLAY_2D               = 0x00000004,
1185MICRO_TILE_MODE_DISPLAY_3D               = 0x00000005,
1186MICRO_TILE_MODE_Z_2D                     = 0x00000006,
1187MICRO_TILE_MODE_Z_3D                     = 0x00000007,
1188} TC_MICRO_TILE_MODE;
1189
1190/*
1191 * SWIZZLE_MODE_ENUM enum
1192 */
1193
1194typedef enum SWIZZLE_MODE_ENUM {
1195SW_LINEAR                                = 0x00000000,
1196SW_256B_S                                = 0x00000001,
1197SW_256B_D                                = 0x00000002,
1198SW_256B_R                                = 0x00000003,
1199SW_4KB_Z                                 = 0x00000004,
1200SW_4KB_S                                 = 0x00000005,
1201SW_4KB_D                                 = 0x00000006,
1202SW_4KB_R                                 = 0x00000007,
1203SW_64KB_Z                                = 0x00000008,
1204SW_64KB_S                                = 0x00000009,
1205SW_64KB_D                                = 0x0000000a,
1206SW_64KB_R                                = 0x0000000b,
1207SW_VAR_Z                                 = 0x0000000c,
1208SW_VAR_S                                 = 0x0000000d,
1209SW_VAR_D                                 = 0x0000000e,
1210SW_VAR_R                                 = 0x0000000f,
1211SW_RESERVED_16                           = 0x00000010,
1212SW_RESERVED_17                           = 0x00000011,
1213SW_RESERVED_18                           = 0x00000012,
1214SW_RESERVED_19                           = 0x00000013,
1215SW_4KB_Z_X                               = 0x00000014,
1216SW_4KB_S_X                               = 0x00000015,
1217SW_4KB_D_X                               = 0x00000016,
1218SW_4KB_R_X                               = 0x00000017,
1219SW_64KB_Z_X                              = 0x00000018,
1220SW_64KB_S_X                              = 0x00000019,
1221SW_64KB_D_X                              = 0x0000001a,
1222SW_64KB_R_X                              = 0x0000001b,
1223SW_VAR_Z_X                               = 0x0000001c,
1224SW_VAR_S_X                               = 0x0000001d,
1225SW_VAR_D_X                               = 0x0000001e,
1226SW_VAR_R_X                               = 0x0000001f,
1227SW_RESERVED_12                           = 0x00000020,
1228SW_RESERVED_13                           = 0x00000021,
1229SW_RESERVED_14                           = 0x00000022,
1230SW_RESERVED_15                           = 0x00000023,
1231} SWIZZLE_MODE_ENUM;
1232
1233/*
1234 * PipeTiling enum
1235 */
1236
1237typedef enum PipeTiling {
1238CONFIG_1_PIPE                            = 0x00000000,
1239CONFIG_2_PIPE                            = 0x00000001,
1240CONFIG_4_PIPE                            = 0x00000002,
1241CONFIG_8_PIPE                            = 0x00000003,
1242} PipeTiling;
1243
1244/*
1245 * BankTiling enum
1246 */
1247
1248typedef enum BankTiling {
1249CONFIG_4_BANK                            = 0x00000000,
1250CONFIG_8_BANK                            = 0x00000001,
1251} BankTiling;
1252
1253/*
1254 * GroupInterleave enum
1255 */
1256
1257typedef enum GroupInterleave {
1258CONFIG_256B_GROUP                        = 0x00000000,
1259CONFIG_512B_GROUP                        = 0x00000001,
1260} GroupInterleave;
1261
1262/*
1263 * RowTiling enum
1264 */
1265
1266typedef enum RowTiling {
1267CONFIG_1KB_ROW                           = 0x00000000,
1268CONFIG_2KB_ROW                           = 0x00000001,
1269CONFIG_4KB_ROW                           = 0x00000002,
1270CONFIG_8KB_ROW                           = 0x00000003,
1271CONFIG_1KB_ROW_OPT                       = 0x00000004,
1272CONFIG_2KB_ROW_OPT                       = 0x00000005,
1273CONFIG_4KB_ROW_OPT                       = 0x00000006,
1274CONFIG_8KB_ROW_OPT                       = 0x00000007,
1275} RowTiling;
1276
1277/*
1278 * BankSwapBytes enum
1279 */
1280
1281typedef enum BankSwapBytes {
1282CONFIG_128B_SWAPS                        = 0x00000000,
1283CONFIG_256B_SWAPS                        = 0x00000001,
1284CONFIG_512B_SWAPS                        = 0x00000002,
1285CONFIG_1KB_SWAPS                         = 0x00000003,
1286} BankSwapBytes;
1287
1288/*
1289 * SampleSplitBytes enum
1290 */
1291
1292typedef enum SampleSplitBytes {
1293CONFIG_1KB_SPLIT                         = 0x00000000,
1294CONFIG_2KB_SPLIT                         = 0x00000001,
1295CONFIG_4KB_SPLIT                         = 0x00000002,
1296CONFIG_8KB_SPLIT                         = 0x00000003,
1297} SampleSplitBytes;
1298
1299/*******************************************************
1300 * AZSTREAM Enums
1301 *******************************************************/
1302
1303/*
1304 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR enum
1305 */
1306
1307typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR {
1308OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET  = 0x00000000,
1309OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET  = 0x00000001,
1310} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR;
1311
1312/*
1313 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR enum
1314 */
1315
1316typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR {
1317OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET  = 0x00000000,
1318OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET  = 0x00000001,
1319} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR;
1320
1321/*
1322 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS enum
1323 */
1324
1325typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS {
1326OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET  = 0x00000000,
1327OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET  = 0x00000001,
1328} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS;
1329
1330/*
1331 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY enum
1332 */
1333
1334typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY {
1335OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY  = 0x00000000,
1336OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY  = 0x00000001,
1337} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY;
1338
1339/*
1340 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE enum
1341 */
1342
1343typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE {
1344OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED  = 0x00000000,
1345OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED  = 0x00000001,
1346} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE;
1347
1348/*
1349 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE enum
1350 */
1351
1352typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE {
1353OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED  = 0x00000000,
1354OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED  = 0x00000001,
1355} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE;
1356
1357/*
1358 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE enum
1359 */
1360
1361typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE {
1362OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED  = 0x00000000,
1363OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED  = 0x00000001,
1364} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE;
1365
1366/*
1367 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN enum
1368 */
1369
1370typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN {
1371OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN  = 0x00000000,
1372OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN  = 0x00000001,
1373} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN;
1374
1375/*
1376 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET enum
1377 */
1378
1379typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET {
1380OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET  = 0x00000000,
1381OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET  = 0x00000001,
1382} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET;
1383
1384/*
1385 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE enum
1386 */
1387
1388typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE {
1389OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ  = 0x00000000,
1390OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ  = 0x00000001,
1391} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE;
1392
1393/*
1394 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE enum
1395 */
1396
1397typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE {
1398OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1  = 0x00000000,
1399OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2  = 0x00000001,
1400OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED  = 0x00000002,
1401OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4  = 0x00000003,
1402OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED  = 0x00000004,
1403} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE;
1404
1405/*
1406 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR enum
1407 */
1408
1409typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR {
1410OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1  = 0x00000000,
1411OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED  = 0x00000001,
1412OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3  = 0x00000002,
1413OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED  = 0x00000003,
1414OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED  = 0x00000004,
1415OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED  = 0x00000005,
1416OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED  = 0x00000006,
1417OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED  = 0x00000007,
1418} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR;
1419
1420/*
1421 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE enum
1422 */
1423
1424typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE {
1425OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED  = 0x00000000,
1426OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16  = 0x00000001,
1427OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20  = 0x00000002,
1428OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24  = 0x00000003,
1429OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED  = 0x00000004,
1430OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED  = 0x00000005,
1431} OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE;
1432
1433/*
1434 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS enum
1435 */
1436
1437typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS {
1438OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1  = 0x00000000,
1439OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2  = 0x00000001,
1440OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3  = 0x00000002,
1441OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4  = 0x00000003,
1442OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5  = 0x00000004,
1443OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6  = 0x00000005,
1444OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7  = 0x00000006,
1445OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8  = 0x00000007,
1446OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED  = 0x00000008,
1447OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED  = 0x00000009,
1448OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED  = 0x0000000a,
1449OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED  = 0x0000000b,
1450OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED  = 0x0000000c,
1451OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED  = 0x0000000d,
1452OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED  = 0x0000000e,
1453OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED  = 0x0000000f,
1454} OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS;
1455
1456/*******************************************************
1457 * BLNDV Enums
1458 *******************************************************/
1459
1460/*
1461 * BLNDV_CONTROL_BLND_MODE enum
1462 */
1463
1464typedef enum BLNDV_CONTROL_BLND_MODE {
1465BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x00000000,
1466BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY  = 0x00000001,
1467BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x00000002,
1468BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x00000003,
1469} BLNDV_CONTROL_BLND_MODE;
1470
1471/*
1472 * BLNDV_CONTROL_BLND_STEREO_TYPE enum
1473 */
1474
1475typedef enum BLNDV_CONTROL_BLND_STEREO_TYPE {
1476BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO = 0x00000000,
1477BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO = 0x00000001,
1478BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO = 0x00000002,
1479BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED    = 0x00000003,
1480} BLNDV_CONTROL_BLND_STEREO_TYPE;
1481
1482/*
1483 * BLNDV_CONTROL_BLND_STEREO_POLARITY enum
1484 */
1485
1486typedef enum BLNDV_CONTROL_BLND_STEREO_POLARITY {
1487BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW   = 0x00000000,
1488BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH  = 0x00000001,
1489} BLNDV_CONTROL_BLND_STEREO_POLARITY;
1490
1491/*
1492 * BLNDV_CONTROL_BLND_FEEDTHROUGH_EN enum
1493 */
1494
1495typedef enum BLNDV_CONTROL_BLND_FEEDTHROUGH_EN {
1496BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE  = 0x00000000,
1497BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE   = 0x00000001,
1498} BLNDV_CONTROL_BLND_FEEDTHROUGH_EN;
1499
1500/*
1501 * BLNDV_CONTROL_BLND_ALPHA_MODE enum
1502 */
1503
1504typedef enum BLNDV_CONTROL_BLND_ALPHA_MODE {
1505BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0x00000000,
1506BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 0x00000001,
1507BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x00000002,
1508BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED     = 0x00000003,
1509} BLNDV_CONTROL_BLND_ALPHA_MODE;
1510
1511/*
1512 * BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY enum
1513 */
1514
1515typedef enum BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY {
1516BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_FALSE  = 0x00000000,
1517BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_TRUE  = 0x00000001,
1518} BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY;
1519
1520/*
1521 * BLNDV_CONTROL_BLND_MULTIPLIED_MODE enum
1522 */
1523
1524typedef enum BLNDV_CONTROL_BLND_MULTIPLIED_MODE {
1525BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0x00000000,
1526BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE  = 0x00000001,
1527} BLNDV_CONTROL_BLND_MULTIPLIED_MODE;
1528
1529/*
1530 * BLNDV_SM_CONTROL2_SM_MODE enum
1531 */
1532
1533typedef enum BLNDV_SM_CONTROL2_SM_MODE {
1534BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE   = 0x00000000,
1535BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x00000002,
1536BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x00000004,
1537BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING = 0x00000006,
1538} BLNDV_SM_CONTROL2_SM_MODE;
1539
1540/*
1541 * BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE enum
1542 */
1543
1544typedef enum BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE {
1545BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x00000000,
1546BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x00000001,
1547} BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE;
1548
1549/*
1550 * BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE enum
1551 */
1552
1553typedef enum BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE {
1554BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x00000000,
1555BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x00000001,
1556} BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE;
1557
1558/*
1559 * BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL enum
1560 */
1561
1562typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
1563BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0x00000000,
1564BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED = 0x00000001,
1565BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 0x00000002,
1566BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 0x00000003,
1567} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;
1568
1569/*
1570 * BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL enum
1571 */
1572
1573typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
1574BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x00000000,
1575BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x00000001,
1576BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x00000002,
1577BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 0x00000003,
1578} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;
1579
1580/*
1581 * BLNDV_CONTROL2_PTI_ENABLE enum
1582 */
1583
1584typedef enum BLNDV_CONTROL2_PTI_ENABLE {
1585BLNDV_CONTROL2_PTI_ENABLE_FALSE          = 0x00000000,
1586BLNDV_CONTROL2_PTI_ENABLE_TRUE           = 0x00000001,
1587} BLNDV_CONTROL2_PTI_ENABLE;
1588
1589/*
1590 * BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN enum
1591 */
1592
1593typedef enum BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
1594BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x00000000,
1595BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x00000001,
1596} BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;
1597
1598/*
1599 * BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN enum
1600 */
1601
1602typedef enum BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
1603BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x00000000,
1604BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x00000001,
1605} BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN;
1606
1607/*
1608 * BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK enum
1609 */
1610
1611typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
1612BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE = 0x00000000,
1613BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE = 0x00000001,
1614} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;
1615
1616/*
1617 * BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK enum
1618 */
1619
1620typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
1621BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE = 0x00000000,
1622BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE = 0x00000001,
1623} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;
1624
1625/*
1626 * BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK enum
1627 */
1628
1629typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
1630BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE = 0x00000000,
1631BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE = 0x00000001,
1632} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;
1633
1634/*
1635 * BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK enum
1636 */
1637
1638typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
1639BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE = 0x00000000,
1640BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE = 0x00000001,
1641} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;
1642
1643/*
1644 * BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK enum
1645 */
1646
1647typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
1648BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE = 0x00000000,
1649BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE = 0x00000001,
1650} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;
1651
1652/*
1653 * BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK enum
1654 */
1655
1656typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
1657BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE = 0x00000000,
1658BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE = 0x00000001,
1659} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;
1660
1661/*
1662 * BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK enum
1663 */
1664
1665typedef enum BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
1666BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x00000000,
1667BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x00000001,
1668} BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;
1669
1670/*
1671 * BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK enum
1672 */
1673
1674typedef enum BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
1675BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0x00000000,
1676BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x00000001,
1677} BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;
1678
1679/*
1680 * BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE enum
1681 */
1682
1683typedef enum BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
1684BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0x00000000,
1685BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x00000001,
1686} BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;
1687
1688/*
1689 * BLNDV_DEBUG_BLND_CNV_MUX_SELECT enum
1690 */
1691
1692typedef enum BLNDV_DEBUG_BLND_CNV_MUX_SELECT {
1693BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW      = 0x00000000,
1694BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH     = 0x00000001,
1695} BLNDV_DEBUG_BLND_CNV_MUX_SELECT;
1696
1697/*
1698 * BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN enum
1699 */
1700
1701typedef enum BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
1702BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
1703BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
1704} BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;
1705
1706/*******************************************************
1707 * LBV Enums
1708 *******************************************************/
1709
1710/*
1711 * LBV_PIXEL_DEPTH enum
1712 */
1713
1714typedef enum LBV_PIXEL_DEPTH {
1715PIXEL_DEPTH_30BPP                        = 0x00000000,
1716PIXEL_DEPTH_24BPP                        = 0x00000001,
1717PIXEL_DEPTH_18BPP                        = 0x00000002,
1718PIXEL_DEPTH_38BPP                        = 0x00000003,
1719} LBV_PIXEL_DEPTH;
1720
1721/*
1722 * LBV_PIXEL_EXPAN_MODE enum
1723 */
1724
1725typedef enum LBV_PIXEL_EXPAN_MODE {
1726PIXEL_EXPAN_MODE_ZERO_EXP                = 0x00000000,
1727PIXEL_EXPAN_MODE_DYN_EXP                 = 0x00000001,
1728} LBV_PIXEL_EXPAN_MODE;
1729
1730/*
1731 * LBV_INTERLEAVE_EN enum
1732 */
1733
1734typedef enum LBV_INTERLEAVE_EN {
1735INTERLEAVE_DIS                           = 0x00000000,
1736INTERLEAVE_EN                            = 0x00000001,
1737} LBV_INTERLEAVE_EN;
1738
1739/*
1740 * LBV_PIXEL_REDUCE_MODE enum
1741 */
1742
1743typedef enum LBV_PIXEL_REDUCE_MODE {
1744PIXEL_REDUCE_MODE_TRUNCATION             = 0x00000000,
1745PIXEL_REDUCE_MODE_ROUNDING               = 0x00000001,
1746} LBV_PIXEL_REDUCE_MODE;
1747
1748/*
1749 * LBV_DYNAMIC_PIXEL_DEPTH enum
1750 */
1751
1752typedef enum LBV_DYNAMIC_PIXEL_DEPTH {
1753DYNAMIC_PIXEL_DEPTH_36BPP                = 0x00000000,
1754DYNAMIC_PIXEL_DEPTH_30BPP                = 0x00000001,
1755} LBV_DYNAMIC_PIXEL_DEPTH;
1756
1757/*
1758 * LBV_DITHER_EN enum
1759 */
1760
1761typedef enum LBV_DITHER_EN {
1762DITHER_DIS                               = 0x00000000,
1763DITHER_EN                                = 0x00000001,
1764} LBV_DITHER_EN;
1765
1766/*
1767 * LBV_DOWNSCALE_PREFETCH_EN enum
1768 */
1769
1770typedef enum LBV_DOWNSCALE_PREFETCH_EN {
1771DOWNSCALE_PREFETCH_DIS                   = 0x00000000,
1772DOWNSCALE_PREFETCH_EN                    = 0x00000001,
1773} LBV_DOWNSCALE_PREFETCH_EN;
1774
1775/*
1776 * LBV_MEMORY_CONFIG enum
1777 */
1778
1779typedef enum LBV_MEMORY_CONFIG {
1780MEMORY_CONFIG_0                          = 0x00000000,
1781MEMORY_CONFIG_1                          = 0x00000001,
1782MEMORY_CONFIG_2                          = 0x00000002,
1783MEMORY_CONFIG_3                          = 0x00000003,
1784} LBV_MEMORY_CONFIG;
1785
1786/*
1787 * LBV_SYNC_RESET_SEL2 enum
1788 */
1789
1790typedef enum LBV_SYNC_RESET_SEL2 {
1791SYNC_RESET_SEL2_VBLANK                   = 0x00000000,
1792SYNC_RESET_SEL2_VSYNC                    = 0x00000001,
1793} LBV_SYNC_RESET_SEL2;
1794
1795/*
1796 * LBV_SYNC_DURATION enum
1797 */
1798
1799typedef enum LBV_SYNC_DURATION {
1800SYNC_DURATION_16                         = 0x00000000,
1801SYNC_DURATION_32                         = 0x00000001,
1802SYNC_DURATION_64                         = 0x00000002,
1803SYNC_DURATION_128                        = 0x00000003,
1804} LBV_SYNC_DURATION;
1805
1806/*******************************************************
1807 * CRTC Enums
1808 *******************************************************/
1809
1810/*
1811 * CRTC_CONTROL_CRTC_START_POINT_CNTL enum
1812 */
1813
1814typedef enum CRTC_CONTROL_CRTC_START_POINT_CNTL {
1815CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL = 0x00000000,
1816CRTC_CONTROL_CRTC_START_POINT_CNTL_DP    = 0x00000001,
1817} CRTC_CONTROL_CRTC_START_POINT_CNTL;
1818
1819/*
1820 * CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL enum
1821 */
1822
1823typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL {
1824CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL = 0x00000000,
1825CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP   = 0x00000001,
1826} CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL;
1827
1828/*
1829 * CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL enum
1830 */
1831
1832typedef enum CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL {
1833CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE  = 0x00000000,
1834CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT  = 0x00000001,
1835CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED  = 0x00000002,
1836CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST  = 0x00000003,
1837} CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL;
1838
1839/*
1840 * CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY enum
1841 */
1842
1843typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY {
1844CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE  = 0x00000000,
1845CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE  = 0x00000001,
1846} CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY;
1847
1848/*
1849 * CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE enum
1850 */
1851
1852typedef enum CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE {
1853CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE  = 0x00000000,
1854CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE  = 0x00000001,
1855} CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE;
1856
1857/*
1858 * CRTC_CONTROL_CRTC_SOF_PULL_EN enum
1859 */
1860
1861typedef enum CRTC_CONTROL_CRTC_SOF_PULL_EN {
1862CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE      = 0x00000000,
1863CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE       = 0x00000001,
1864} CRTC_CONTROL_CRTC_SOF_PULL_EN;
1865
1866/*
1867 * CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL enum
1868 */
1869
1870typedef enum CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL {
1871CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE  = 0x00000000,
1872CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE  = 0x00000001,
1873} CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL;
1874
1875/*
1876 * CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL enum
1877 */
1878
1879typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL {
1880CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE  = 0x00000000,
1881CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE  = 0x00000001,
1882} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL;
1883
1884/*
1885 * CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL enum
1886 */
1887
1888typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL {
1889CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE  = 0x00000000,
1890CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE  = 0x00000001,
1891} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL;
1892
1893/*
1894 * CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN enum
1895 */
1896
1897typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN {
1898CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE  = 0x00000000,
1899CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE  = 0x00000001,
1900} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN;
1901
1902/*
1903 * CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC enum
1904 */
1905
1906typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC {
1907CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0x00000000,
1908CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE  = 0x00000001,
1909} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC;
1910
1911/*
1912 * CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT enum
1913 */
1914
1915typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT {
1916CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE = 0x00000000,
1917CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE  = 0x00000001,
1918} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT;
1919
1920/*
1921 * CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK enum
1922 */
1923
1924typedef enum CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK {
1925CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE = 0x00000000,
1926CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE  = 0x00000001,
1927} CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK;
1928
1929/*
1930 * CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR enum
1931 */
1932
1933typedef enum CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR {
1934CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE = 0x00000000,
1935CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE  = 0x00000001,
1936} CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR;
1937
1938/*
1939 * CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL enum
1940 */
1941
1942typedef enum CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL {
1943CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE  = 0x00000000,
1944CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE  = 0x00000001,
1945} CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL;
1946
1947/*
1948 * CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN enum
1949 */
1950
1951typedef enum CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN {
1952CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE  = 0x00000000,
1953CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE  = 0x00000001,
1954} CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN;
1955
1956/*
1957 * CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT enum
1958 */
1959
1960typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT {
1961CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER  = 0x00000001,
1962CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER  = 0x00000002,
1963CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF  = 0x00000005,
1964CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE  = 0x00000006,
1965CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA  = 0x00000007,
1966CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA  = 0x00000008,
1967CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB  = 0x00000009,
1968CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB  = 0x0000000a,
1969CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1  = 0x0000000b,
1970CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2  = 0x0000000c,
1971CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD  = 0x0000000d,
1972CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC  = 0x0000000e,
1973CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0  = 0x00000010,
1974CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1  = 0x00000011,
1975CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2  = 0x00000012,
1976CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON  = 0x00000013,
1977CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA  = 0x00000014,
1978CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB  = 0x00000015,
1979CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW  = 0x00000016,
1980CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW  = 0x00000017,
1981} CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT;
1982
1983/*
1984 * CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT enum
1985 */
1986
1987typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT {
1988CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE  = 0x00000001,
1989CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA  = 0x00000002,
1990CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB  = 0x00000003,
1991CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA  = 0x00000004,
1992CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB  = 0x00000005,
1993CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO  = 0x00000006,
1994CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC  = 0x00000007,
1995} CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT;
1996
1997/*
1998 * CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN enum
1999 */
2000
2001typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN {
2002CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE  = 0x00000000,
2003CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE  = 0x00000001,
2004} CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN;
2005
2006/*
2007 * CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR enum
2008 */
2009
2010typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR {
2011CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE   = 0x00000000,
2012CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE    = 0x00000001,
2013} CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR;
2014
2015/*
2016 * CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT enum
2017 */
2018
2019typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT {
2020CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER  = 0x00000001,
2021CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER  = 0x00000002,
2022CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF  = 0x00000005,
2023CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE  = 0x00000006,
2024CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA  = 0x00000007,
2025CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA  = 0x00000008,
2026CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB  = 0x00000009,
2027CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB  = 0x0000000a,
2028CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1  = 0x0000000b,
2029CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2  = 0x0000000c,
2030CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD  = 0x0000000d,
2031CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC  = 0x0000000e,
2032CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0  = 0x00000010,
2033CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1  = 0x00000011,
2034CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2  = 0x00000012,
2035CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON  = 0x00000013,
2036CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA  = 0x00000014,
2037CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB  = 0x00000015,
2038CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW  = 0x00000016,
2039CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW  = 0x00000017,
2040} CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT;
2041
2042/*
2043 * CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT enum
2044 */
2045
2046typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT {
2047CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE  = 0x00000001,
2048CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA  = 0x00000002,
2049CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB  = 0x00000003,
2050CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA  = 0x00000004,
2051CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB  = 0x00000005,
2052CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO  = 0x00000006,
2053CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC  = 0x00000007,
2054} CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT;
2055
2056/*
2057 * CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN enum
2058 */
2059
2060typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN {
2061CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE  = 0x00000000,
2062CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE  = 0x00000001,
2063} CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN;
2064
2065/*
2066 * CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR enum
2067 */
2068
2069typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR {
2070CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE   = 0x00000000,
2071CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE    = 0x00000001,
2072} CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR;
2073
2074/*
2075 * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE enum
2076 */
2077
2078typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE {
2079CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE  = 0x00000000,
2080CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT  = 0x00000001,
2081CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT  = 0x00000002,
2082CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED  = 0x00000003,
2083} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE;
2084
2085/*
2086 * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK enum
2087 */
2088
2089typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK {
2090CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE  = 0x00000000,
2091CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE  = 0x00000001,
2092} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK;
2093
2094/*
2095 * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL enum
2096 */
2097
2098typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL {
2099CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE  = 0x00000000,
2100CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE  = 0x00000001,
2101} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL;
2102
2103/*
2104 * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR enum
2105 */
2106
2107typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR {
2108CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE = 0x00000000,
2109CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE  = 0x00000001,
2110} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR;
2111
2112/*
2113 * CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT enum
2114 */
2115
2116typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT {
2117CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0  = 0x00000000,
2118CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF  = 0x00000001,
2119CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE  = 0x00000002,
2120CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1  = 0x00000003,
2121CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2  = 0x00000004,
2122CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA  = 0x00000005,
2123CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK  = 0x00000006,
2124CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA  = 0x00000007,
2125CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK  = 0x00000008,
2126CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK  = 0x00000009,
2127CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL  = 0x0000000a,
2128CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1  = 0x0000000b,
2129CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB  = 0x0000000c,
2130CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA  = 0x0000000d,
2131CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD  = 0x0000000e,
2132CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC  = 0x0000000f,
2133} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT;
2134
2135/*
2136 * CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY enum
2137 */
2138
2139typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY {
2140CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE  = 0x00000000,
2141CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE  = 0x00000001,
2142} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY;
2143
2144/*
2145 * CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY enum
2146 */
2147
2148typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY {
2149CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE  = 0x00000000,
2150CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE  = 0x00000001,
2151} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY;
2152
2153/*
2154 * CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE enum
2155 */
2156
2157typedef enum CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE {
2158CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO  = 0x00000000,
2159CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT  = 0x00000001,
2160CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT  = 0x00000002,
2161CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED  = 0x00000003,
2162} CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE;
2163
2164/*
2165 * CRTC_CONTROL_CRTC_MASTER_EN enum
2166 */
2167
2168typedef enum CRTC_CONTROL_CRTC_MASTER_EN {
2169CRTC_CONTROL_CRTC_MASTER_EN_FALSE        = 0x00000000,
2170CRTC_CONTROL_CRTC_MASTER_EN_TRUE         = 0x00000001,
2171} CRTC_CONTROL_CRTC_MASTER_EN;
2172
2173/*
2174 * CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN enum
2175 */
2176
2177typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN {
2178CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE  = 0x00000000,
2179CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE  = 0x00000001,
2180} CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN;
2181
2182/*
2183 * CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE enum
2184 */
2185
2186typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE {
2187CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE  = 0x00000000,
2188CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE  = 0x00000001,
2189} CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE;
2190
2191/*
2192 * CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE enum
2193 */
2194
2195typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE {
2196CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE  = 0x00000000,
2197CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE  = 0x00000001,
2198} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE;
2199
2200/*
2201 * CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD enum
2202 */
2203
2204typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD {
2205CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT  = 0x00000000,
2206CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD  = 0x00000001,
2207CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN  = 0x00000002,
2208CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2  = 0x00000003,
2209} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD;
2210
2211/*
2212 * CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY enum
2213 */
2214
2215typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY {
2216CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE  = 0x00000000,
2217CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE  = 0x00000001,
2218} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY;
2219
2220/*
2221 * CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT enum
2222 */
2223
2224typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT {
2225CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE  = 0x00000000,
2226CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE  = 0x00000001,
2227} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT;
2228
2229/*
2230 * CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN enum
2231 */
2232
2233typedef enum CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN {
2234CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE  = 0x00000000,
2235CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE  = 0x00000001,
2236} CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN;
2237
2238/*
2239 * CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE enum
2240 */
2241
2242typedef enum CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE {
2243CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0x00000000,
2244CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE  = 0x00000001,
2245} CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE;
2246
2247/*
2248 * CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR enum
2249 */
2250
2251typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR {
2252CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0x00000000,
2253CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE  = 0x00000001,
2254} CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR;
2255
2256/*
2257 * CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE enum
2258 */
2259
2260typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE {
2261CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE  = 0x00000000,
2262CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA  = 0x00000001,
2263CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB  = 0x00000002,
2264CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED  = 0x00000003,
2265} CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE;
2266
2267/*
2268 * CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY enum
2269 */
2270
2271typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY {
2272CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE  = 0x00000000,
2273CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE  = 0x00000001,
2274} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY;
2275
2276/*
2277 * CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY enum
2278 */
2279
2280typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY {
2281CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE  = 0x00000000,
2282CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE  = 0x00000001,
2283} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY;
2284
2285/*
2286 * CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY enum
2287 */
2288
2289typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY {
2290CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE  = 0x00000000,
2291CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE  = 0x00000001,
2292} CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY;
2293
2294/*
2295 * CRTC_STEREO_CONTROL_CRTC_STEREO_EN enum
2296 */
2297
2298typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EN {
2299CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE  = 0x00000000,
2300CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE  = 0x00000001,
2301} CRTC_STEREO_CONTROL_CRTC_STEREO_EN;
2302
2303/*
2304 * CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR enum
2305 */
2306
2307typedef enum CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR {
2308CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE = 0x00000000,
2309CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE  = 0x00000001,
2310} CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR;
2311
2312/*
2313 * CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL enum
2314 */
2315
2316typedef enum CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL {
2317CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE  = 0x00000000,
2318CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA  = 0x00000001,
2319CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB  = 0x00000002,
2320CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED  = 0x00000003,
2321} CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL;
2322
2323/*
2324 * CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY enum
2325 */
2326
2327typedef enum CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY {
2328CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE = 0x00000000,
2329CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE  = 0x00000001,
2330} CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY;
2331
2332/*
2333 * CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY enum
2334 */
2335
2336typedef enum CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY {
2337CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE = 0x00000000,
2338CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE  = 0x00000001,
2339} CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY;
2340
2341/*
2342 * CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN enum
2343 */
2344
2345typedef enum CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN {
2346CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE  = 0x00000000,
2347CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE  = 0x00000001,
2348} CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN;
2349
2350/*
2351 * CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN enum
2352 */
2353
2354typedef enum CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN {
2355CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE  = 0x00000000,
2356CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE  = 0x00000001,
2357} CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN;
2358
2359/*
2360 * CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK enum
2361 */
2362
2363typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK {
2364CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE  = 0x00000000,
2365CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE  = 0x00000001,
2366} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK;
2367
2368/*
2369 * CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE enum
2370 */
2371
2372typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE {
2373CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE  = 0x00000000,
2374CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE  = 0x00000001,
2375} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE;
2376
2377/*
2378 * CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK enum
2379 */
2380
2381typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK {
2382CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE  = 0x00000000,
2383CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE  = 0x00000001,
2384} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK;
2385
2386/*
2387 * CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE enum
2388 */
2389
2390typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE {
2391CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE  = 0x00000000,
2392CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE  = 0x00000001,
2393} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE;
2394
2395/*
2396 * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK enum
2397 */
2398
2399typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK {
2400CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE  = 0x00000000,
2401CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE  = 0x00000001,
2402} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK;
2403
2404/*
2405 * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE enum
2406 */
2407
2408typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE {
2409CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE  = 0x00000000,
2410CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE  = 0x00000001,
2411} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE;
2412
2413/*
2414 * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK enum
2415 */
2416
2417typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK {
2418CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE  = 0x00000000,
2419CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE  = 0x00000001,
2420} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK;
2421
2422/*
2423 * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE enum
2424 */
2425
2426typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE {
2427CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE  = 0x00000000,
2428CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE  = 0x00000001,
2429} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE;
2430
2431/*
2432 * CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK enum
2433 */
2434
2435typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK {
2436CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE  = 0x00000000,
2437CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE  = 0x00000001,
2438} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK;
2439
2440/*
2441 * CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE enum
2442 */
2443
2444typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE {
2445CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE  = 0x00000000,
2446CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE  = 0x00000001,
2447} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE;
2448
2449/*
2450 * CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK enum
2451 */
2452
2453typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK {
2454CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE  = 0x00000000,
2455CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE  = 0x00000001,
2456} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK;
2457
2458/*
2459 * CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE enum
2460 */
2461
2462typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE {
2463CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE  = 0x00000000,
2464CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE  = 0x00000001,
2465} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE;
2466
2467/*
2468 * CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK enum
2469 */
2470
2471typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK {
2472CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE  = 0x00000000,
2473CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE  = 0x00000001,
2474} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK;
2475
2476/*
2477 * CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE enum
2478 */
2479
2480typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE {
2481CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE  = 0x00000000,
2482CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE  = 0x00000001,
2483} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE;
2484
2485/*
2486 * CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK enum
2487 */
2488
2489typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK {
2490CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE  = 0x00000000,
2491CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE  = 0x00000001,
2492} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK;
2493
2494/*
2495 * CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE enum
2496 */
2497
2498typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE {
2499CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE  = 0x00000000,
2500CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE  = 0x00000001,
2501} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE;
2502
2503/*
2504 * CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK enum
2505 */
2506
2507typedef enum CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK {
2508CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE  = 0x00000000,
2509CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE   = 0x00000001,
2510} CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK;
2511
2512/*
2513 * CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY enum
2514 */
2515
2516typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY {
2517CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE  = 0x00000000,
2518CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE  = 0x00000001,
2519} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY;
2520
2521/*
2522 * CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN enum
2523 */
2524
2525typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN {
2526CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE  = 0x00000000,
2527CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE  = 0x00000001,
2528} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN;
2529
2530/*
2531 * CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE enum
2532 */
2533
2534typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE {
2535CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_0  = 0x00000000,
2536CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_1  = 0x00000001,
2537} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE;
2538
2539/*
2540 * CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE enum
2541 */
2542
2543typedef enum CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE {
2544CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE  = 0x00000000,
2545CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE  = 0x00000001,
2546} CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE;
2547
2548/*
2549 * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN enum
2550 */
2551
2552typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN {
2553CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE  = 0x00000000,
2554CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE  = 0x00000001,
2555} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN;
2556
2557/*
2558 * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE enum
2559 */
2560
2561typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE {
2562CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB  = 0x00000000,
2563CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601  = 0x00000001,
2564CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709  = 0x00000002,
2565CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS  = 0x00000003,
2566CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS  = 0x00000004,
2567CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB  = 0x00000005,
2568CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB  = 0x00000006,
2569CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS  = 0x00000007,
2570} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE;
2571
2572/*
2573 * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE enum
2574 */
2575
2576typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE {
2577CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE  = 0x00000000,
2578CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE  = 0x00000001,
2579} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE;
2580
2581/*
2582 * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT enum
2583 */
2584
2585typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT {
2586CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC  = 0x00000000,
2587CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC  = 0x00000001,
2588CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC  = 0x00000002,
2589CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED  = 0x00000003,
2590} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT;
2591
2592/*
2593 * MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK enum
2594 */
2595
2596typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {
2597MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE  = 0x00000000,
2598MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE  = 0x00000001,
2599} MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK;
2600
2601/*
2602 * MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK enum
2603 */
2604
2605typedef enum MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK {
2606MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE  = 0x00000000,
2607MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE  = 0x00000001,
2608} MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK;
2609
2610/*
2611 * MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK enum
2612 */
2613
2614typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK {
2615MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE  = 0x00000000,
2616MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE  = 0x00000001,
2617} MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK;
2618
2619/*
2620 * MASTER_UPDATE_MODE_MASTER_UPDATE_MODE enum
2621 */
2622
2623typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_MODE {
2624MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN  = 0x00000000,
2625MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA  = 0x00000001,
2626MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA  = 0x00000002,
2627MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE  = 0x00000003,
2628} MASTER_UPDATE_MODE_MASTER_UPDATE_MODE;
2629
2630/*
2631 * MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE enum
2632 */
2633
2634typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {
2635MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH  = 0x00000000,
2636MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN  = 0x00000001,
2637MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD  = 0x00000002,
2638MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED  = 0x00000003,
2639} MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE;
2640
2641/*
2642 * CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE enum
2643 */
2644
2645typedef enum CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE {
2646CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE  = 0x00000000,
2647CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG  = 0x00000001,
2648CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL  = 0x00000002,
2649} CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE;
2650
2651/*
2652 * CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR enum
2653 */
2654
2655typedef enum CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR {
2656CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE = 0x00000000,
2657CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE  = 0x00000001,
2658} CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR;
2659
2660/*
2661 * CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR enum
2662 */
2663
2664typedef enum CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR {
2665CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE = 0x00000000,
2666CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE  = 0x00000001,
2667} CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR;
2668
2669/*
2670 * CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR enum
2671 */
2672
2673typedef enum CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR {
2674CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE = 0x00000000,
2675CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE  = 0x00000001,
2676} CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR;
2677
2678/*
2679 * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY enum
2680 */
2681
2682typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {
2683CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE  = 0x00000000,
2684CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE  = 0x00000001,
2685} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY;
2686
2687/*
2688 * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE enum
2689 */
2690
2691typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE {
2692CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0x00000000,
2693CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE  = 0x00000001,
2694} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE;
2695
2696/*
2697 * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR enum
2698 */
2699
2700typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR {
2701CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0x00000000,
2702CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE  = 0x00000001,
2703} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR;
2704
2705/*
2706 * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE enum
2707 */
2708
2709typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE {
2710CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE  = 0x00000000,
2711CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE  = 0x00000001,
2712} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE;
2713
2714/*
2715 * CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR enum
2716 */
2717
2718typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR {
2719CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0x00000000,
2720CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE  = 0x00000001,
2721} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR;
2722
2723/*
2724 * CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE enum
2725 */
2726
2727typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE {
2728CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0x00000000,
2729CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE  = 0x00000001,
2730} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE;
2731
2732/*
2733 * CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE enum
2734 */
2735
2736typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE {
2737CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE  = 0x00000000,
2738CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE  = 0x00000001,
2739} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE;
2740
2741/*
2742 * CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR enum
2743 */
2744
2745typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR {
2746CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0x00000000,
2747CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE  = 0x00000001,
2748} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR;
2749
2750/*
2751 * CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE enum
2752 */
2753
2754typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE {
2755CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0x00000000,
2756CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE  = 0x00000001,
2757} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE;
2758
2759/*
2760 * CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE enum
2761 */
2762
2763typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE {
2764CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE  = 0x00000000,
2765CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE  = 0x00000001,
2766} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE;
2767
2768/*
2769 * CRTC_CRC_CNTL_CRTC_CRC_EN enum
2770 */
2771
2772typedef enum CRTC_CRC_CNTL_CRTC_CRC_EN {
2773CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE          = 0x00000000,
2774CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE           = 0x00000001,
2775} CRTC_CRC_CNTL_CRTC_CRC_EN;
2776
2777/*
2778 * CRTC_CRC_CNTL_CRTC_CRC_CONT_EN enum
2779 */
2780
2781typedef enum CRTC_CRC_CNTL_CRTC_CRC_CONT_EN {
2782CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE     = 0x00000000,
2783CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE      = 0x00000001,
2784} CRTC_CRC_CNTL_CRTC_CRC_CONT_EN;
2785
2786/*
2787 * CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE enum
2788 */
2789
2790typedef enum CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE {
2791CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT  = 0x00000000,
2792CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT  = 0x00000001,
2793CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES  = 0x00000002,
2794CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS  = 0x00000003,
2795} CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE;
2796
2797/*
2798 * CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE enum
2799 */
2800
2801typedef enum CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE {
2802CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP  = 0x00000000,
2803CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM  = 0x00000001,
2804CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM  = 0x00000002,
2805CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD  = 0x00000003,
2806} CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE;
2807
2808/*
2809 * CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS enum
2810 */
2811
2812typedef enum CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS {
2813CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0x00000000,
2814CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE  = 0x00000001,
2815} CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS;
2816
2817/*
2818 * CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT enum
2819 */
2820
2821typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT {
2822CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB  = 0x00000000,
2823CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B  = 0x00000001,
2824CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB  = 0x00000002,
2825CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B  = 0x00000003,
2826CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB  = 0x00000004,
2827CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B  = 0x00000005,
2828CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB  = 0x00000006,
2829CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B  = 0x00000007,
2830} CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT;
2831
2832/*
2833 * CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT enum
2834 */
2835
2836typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT {
2837CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB  = 0x00000000,
2838CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B  = 0x00000001,
2839CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB  = 0x00000002,
2840CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B  = 0x00000003,
2841CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB  = 0x00000004,
2842CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B  = 0x00000005,
2843CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB  = 0x00000006,
2844CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B  = 0x00000007,
2845} CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT;
2846
2847/*
2848 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE enum
2849 */
2850
2851typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE {
2852CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_DISABLE  = 0x00000000,
2853CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_ONESHOT  = 0x00000001,
2854CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_CONTINUOUS  = 0x00000002,
2855CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_RESERVED  = 0x00000003,
2856} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE;
2857
2858/*
2859 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE enum
2860 */
2861
2862typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE {
2863CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE  = 0x00000000,
2864CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE  = 0x00000001,
2865} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE;
2866
2867/*
2868 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE enum
2869 */
2870
2871typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE {
2872CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE  = 0x00000000,
2873CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE  = 0x00000001,
2874} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE;
2875
2876/*
2877 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW enum
2878 */
2879
2880typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW {
2881CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel  = 0x00000000,
2882CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel  = 0x00000001,
2883CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel  = 0x00000002,
2884CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel  = 0x00000003,
2885} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW;
2886
2887/*
2888 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE enum
2889 */
2890
2891typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE {
2892CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE  = 0x00000000,
2893CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE  = 0x00000001,
2894} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE;
2895
2896/*
2897 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE enum
2898 */
2899
2900typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE {
2901CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE = 0x00000000,
2902CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE  = 0x00000001,
2903} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE;
2904
2905/*
2906 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY enum
2907 */
2908
2909typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY {
2910CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE  = 0x00000000,
2911CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE  = 0x00000001,
2912} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY;
2913
2914/*
2915 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY enum
2916 */
2917
2918typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY {
2919CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE  = 0x00000000,
2920CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE  = 0x00000001,
2921} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY;
2922
2923/*
2924 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE enum
2925 */
2926
2927typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE {
2928CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE  = 0x00000000,
2929CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE  = 0x00000001,
2930} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE;
2931
2932/*
2933 * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE enum
2934 */
2935
2936typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE {
2937CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE  = 0x00000000,
2938CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE  = 0x00000001,
2939} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE;
2940
2941/*
2942 * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR enum
2943 */
2944
2945typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR {
2946CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE = 0x00000000,
2947CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE  = 0x00000001,
2948} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR;
2949
2950/*
2951 * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE enum
2952 */
2953
2954typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE {
2955CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE  = 0x00000000,
2956CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE  = 0x00000001,
2957} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE;
2958
2959/*
2960 * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT enum
2961 */
2962
2963typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT {
2964CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME  = 0x00000000,
2965CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME  = 0x00000001,
2966CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME  = 0x00000002,
2967CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME  = 0x00000003,
2968CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME  = 0x00000004,
2969CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME  = 0x00000005,
2970CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME  = 0x00000006,
2971CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME  = 0x00000007,
2972} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT;
2973
2974/*
2975 * CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE enum
2976 */
2977
2978typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE {
2979CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_FALSE  = 0x00000000,
2980CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_TRUE  = 0x00000001,
2981} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE;
2982
2983/*
2984 * CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR enum
2985 */
2986
2987typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR {
2988CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_FALSE = 0x00000000,
2989CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_TRUE  = 0x00000001,
2990} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR;
2991
2992/*
2993 * CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE enum
2994 */
2995
2996typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE {
2997CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_FALSE  = 0x00000000,
2998CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_TRUE  = 0x00000001,
2999} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE;
3000
3001/*
3002 * CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE enum
3003 */
3004
3005typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE {
3006CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE  = 0x00000000,
3007CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE  = 0x00000001,
3008} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE;
3009
3010/*
3011 * CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR enum
3012 */
3013
3014typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR {
3015CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE = 0x00000000,
3016CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE  = 0x00000001,
3017} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR;
3018
3019/*
3020 * CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE enum
3021 */
3022
3023typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE {
3024CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE  = 0x00000000,
3025CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE  = 0x00000001,
3026} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE;
3027
3028/*
3029 * CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE enum
3030 */
3031
3032typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE {
3033CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE  = 0x00000000,
3034CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE  = 0x00000001,
3035} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE;
3036
3037/*
3038 * CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR enum
3039 */
3040
3041typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR {
3042CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE = 0x00000000,
3043CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE  = 0x00000001,
3044} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR;
3045
3046/*
3047 * CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE enum
3048 */
3049
3050typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE {
3051CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE  = 0x00000000,
3052CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE  = 0x00000001,
3053} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE;
3054
3055/*
3056 * CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE enum
3057 */
3058
3059typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE {
3060CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_FALSE  = 0x00000000,
3061CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_TRUE  = 0x00000001,
3062} CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE;
3063
3064/*
3065 * CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE enum
3066 */
3067
3068typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE {
3069CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_OFF  = 0x00000000,
3070CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_ON  = 0x00000001,
3071} CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE;
3072
3073/*
3074 * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN enum
3075 */
3076
3077typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN {
3078CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE  = 0x00000000,
3079CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE  = 0x00000001,
3080} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN;
3081
3082/*
3083 * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB enum
3084 */
3085
3086typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB {
3087CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE  = 0x00000000,
3088CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE  = 0x00000001,
3089} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB;
3090
3091/*
3092 * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE enum
3093 */
3094
3095typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE {
3096CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH  = 0x00000000,
3097CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE  = 0x00000001,
3098CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE  = 0x00000002,
3099CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED  = 0x00000003,
3100} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE;
3101
3102/*
3103 * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR enum
3104 */
3105
3106typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR {
3107CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE  = 0x00000000,
3108CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE  = 0x00000001,
3109} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR;
3110
3111/*
3112 * CRTC_V_SYNC_A_POL enum
3113 */
3114
3115typedef enum CRTC_V_SYNC_A_POL {
3116CRTC_V_SYNC_A_POL_HIGH                   = 0x00000000,
3117CRTC_V_SYNC_A_POL_LOW                    = 0x00000001,
3118} CRTC_V_SYNC_A_POL;
3119
3120/*
3121 * CRTC_H_SYNC_A_POL enum
3122 */
3123
3124typedef enum CRTC_H_SYNC_A_POL {
3125CRTC_H_SYNC_A_POL_HIGH                   = 0x00000000,
3126CRTC_H_SYNC_A_POL_LOW                    = 0x00000001,
3127} CRTC_H_SYNC_A_POL;
3128
3129/*
3130 * CRTC_HORZ_REPETITION_COUNT enum
3131 */
3132
3133typedef enum CRTC_HORZ_REPETITION_COUNT {
3134CRTC_HORZ_REPETITION_COUNT_0             = 0x00000000,
3135CRTC_HORZ_REPETITION_COUNT_1             = 0x00000001,
3136CRTC_HORZ_REPETITION_COUNT_2             = 0x00000002,
3137CRTC_HORZ_REPETITION_COUNT_3             = 0x00000003,
3138CRTC_HORZ_REPETITION_COUNT_4             = 0x00000004,
3139CRTC_HORZ_REPETITION_COUNT_5             = 0x00000005,
3140CRTC_HORZ_REPETITION_COUNT_6             = 0x00000006,
3141CRTC_HORZ_REPETITION_COUNT_7             = 0x00000007,
3142CRTC_HORZ_REPETITION_COUNT_8             = 0x00000008,
3143CRTC_HORZ_REPETITION_COUNT_9             = 0x00000009,
3144CRTC_HORZ_REPETITION_COUNT_10            = 0x0000000a,
3145CRTC_HORZ_REPETITION_COUNT_11            = 0x0000000b,
3146CRTC_HORZ_REPETITION_COUNT_12            = 0x0000000c,
3147CRTC_HORZ_REPETITION_COUNT_13            = 0x0000000d,
3148CRTC_HORZ_REPETITION_COUNT_14            = 0x0000000e,
3149CRTC_HORZ_REPETITION_COUNT_15            = 0x0000000f,
3150} CRTC_HORZ_REPETITION_COUNT;
3151
3152/*
3153 * CRTC_DRR_MODE_DBUF_UPDATE_MODE enum
3154 */
3155
3156typedef enum CRTC_DRR_MODE_DBUF_UPDATE_MODE {
3157CRTC_DRR_MODE_DBUF_UPDATE_MODE_00_IMMEDIATE  = 0x00000000,
3158CRTC_DRR_MODE_DBUF_UPDATE_MODE_01_MANUAL  = 0x00000001,
3159CRTC_DRR_MODE_DBUF_UPDATE_MODE_10_DBUF   = 0x00000002,
3160CRTC_DRR_MODE_DBUF_UPDATE_MODE_11_SYNCED_DBUF  = 0x00000003,
3161} CRTC_DRR_MODE_DBUF_UPDATE_MODE;
3162
3163/*******************************************************
3164 * FMT Enums
3165 *******************************************************/
3166
3167/*
3168 * FMT_CONTROL_PIXEL_ENCODING enum
3169 */
3170
3171typedef enum FMT_CONTROL_PIXEL_ENCODING {
3172FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444  = 0x00000000,
3173FMT_CONTROL_PIXEL_ENCODING_YCBCR422      = 0x00000001,
3174FMT_CONTROL_PIXEL_ENCODING_YCBCR420      = 0x00000002,
3175FMT_CONTROL_PIXEL_ENCODING_RESERVED      = 0x00000003,
3176} FMT_CONTROL_PIXEL_ENCODING;
3177
3178/*
3179 * FMT_CONTROL_SUBSAMPLING_MODE enum
3180 */
3181
3182typedef enum FMT_CONTROL_SUBSAMPLING_MODE {
3183FMT_CONTROL_SUBSAMPLING_MODE_DROP        = 0x00000000,
3184FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE     = 0x00000001,
3185FMT_CONTROL_SUBSAMPLING_MOME_3_TAP       = 0x00000002,
3186FMT_CONTROL_SUBSAMPLING_MOME_RESERVED    = 0x00000003,
3187} FMT_CONTROL_SUBSAMPLING_MODE;
3188
3189/*
3190 * FMT_CONTROL_SUBSAMPLING_ORDER enum
3191 */
3192
3193typedef enum FMT_CONTROL_SUBSAMPLING_ORDER {
3194FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR  = 0x00000000,
3195FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB  = 0x00000001,
3196} FMT_CONTROL_SUBSAMPLING_ORDER;
3197
3198/*
3199 * FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS enum
3200 */
3201
3202typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS {
3203FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE  = 0x00000000,
3204FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE  = 0x00000001,
3205} FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS;
3206
3207/*
3208 * FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE enum
3209 */
3210
3211typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE {
3212FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION  = 0x00000000,
3213FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING  = 0x00000001,
3214} FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE;
3215
3216/*
3217 * FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH enum
3218 */
3219
3220typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH {
3221FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP  = 0x00000000,
3222FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP  = 0x00000001,
3223FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP  = 0x00000002,
3224} FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH;
3225
3226/*
3227 * FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH enum
3228 */
3229
3230typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH {
3231FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP  = 0x00000000,
3232FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP  = 0x00000001,
3233FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP  = 0x00000002,
3234} FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH;
3235
3236/*
3237 * FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH enum
3238 */
3239
3240typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH {
3241FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP  = 0x00000000,
3242FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP  = 0x00000001,
3243FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP  = 0x00000002,
3244} FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH;
3245
3246/*
3247 * FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL enum
3248 */
3249
3250typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL {
3251FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2  = 0x00000000,
3252FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4  = 0x00000001,
3253} FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL;
3254
3255/*
3256 * FMT_BIT_DEPTH_CONTROL_25FRC_SEL enum
3257 */
3258
3259typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL {
3260FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei       = 0x00000000,
3261FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi       = 0x00000001,
3262FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi       = 0x00000002,
3263FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED  = 0x00000003,
3264} FMT_BIT_DEPTH_CONTROL_25FRC_SEL;
3265
3266/*
3267 * FMT_BIT_DEPTH_CONTROL_50FRC_SEL enum
3268 */
3269
3270typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL {
3271FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A        = 0x00000000,
3272FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B        = 0x00000001,
3273FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C        = 0x00000002,
3274FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D        = 0x00000003,
3275} FMT_BIT_DEPTH_CONTROL_50FRC_SEL;
3276
3277/*
3278 * FMT_BIT_DEPTH_CONTROL_75FRC_SEL enum
3279 */
3280
3281typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL {
3282FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E        = 0x00000000,
3283FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F        = 0x00000001,
3284FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G        = 0x00000002,
3285FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED  = 0x00000003,
3286} FMT_BIT_DEPTH_CONTROL_75FRC_SEL;
3287
3288/*
3289 * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT enum
3290 */
3291
3292typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT {
3293FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN  = 0x00000000,
3294FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN  = 0x00000001,
3295} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT;
3296
3297/*
3298 * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 enum
3299 */
3300
3301typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 {
3302FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR  = 0x00000000,
3303FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB  = 0x00000001,
3304} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0;
3305
3306/*
3307 * FMT_CLAMP_CNTL_COLOR_FORMAT enum
3308 */
3309
3310typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT {
3311FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC         = 0x00000000,
3312FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC         = 0x00000001,
3313FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC        = 0x00000002,
3314FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC        = 0x00000003,
3315FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1    = 0x00000004,
3316FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2    = 0x00000005,
3317FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3    = 0x00000006,
3318FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE  = 0x00000007,
3319} FMT_CLAMP_CNTL_COLOR_FORMAT;
3320
3321/*
3322 * FMT_CRC_CNTL_CONT_EN enum
3323 */
3324
3325typedef enum FMT_CRC_CNTL_CONT_EN {
3326FMT_CRC_CNTL_CONT_EN_ONE_SHOT            = 0x00000000,
3327FMT_CRC_CNTL_CONT_EN_CONT                = 0x00000001,
3328} FMT_CRC_CNTL_CONT_EN;
3329
3330/*
3331 * FMT_CRC_CNTL_INCLUDE_OVERSCAN enum
3332 */
3333
3334typedef enum FMT_CRC_CNTL_INCLUDE_OVERSCAN {
3335FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE  = 0x00000000,
3336FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE    = 0x00000001,
3337} FMT_CRC_CNTL_INCLUDE_OVERSCAN;
3338
3339/*
3340 * FMT_CRC_CNTL_ONLY_BLANKB enum
3341 */
3342
3343typedef enum FMT_CRC_CNTL_ONLY_BLANKB {
3344FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD    = 0x00000000,
3345FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK       = 0x00000001,
3346} FMT_CRC_CNTL_ONLY_BLANKB;
3347
3348/*
3349 * FMT_CRC_CNTL_PSR_MODE_ENABLE enum
3350 */
3351
3352typedef enum FMT_CRC_CNTL_PSR_MODE_ENABLE {
3353FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL      = 0x00000000,
3354FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC  = 0x00000001,
3355} FMT_CRC_CNTL_PSR_MODE_ENABLE;
3356
3357/*
3358 * FMT_CRC_CNTL_INTERLACE_MODE enum
3359 */
3360
3361typedef enum FMT_CRC_CNTL_INTERLACE_MODE {
3362FMT_CRC_CNTL_INTERLACE_MODE_TOP          = 0x00000000,
3363FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM       = 0x00000001,
3364FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM  = 0x00000002,
3365FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH    = 0x00000003,
3366} FMT_CRC_CNTL_INTERLACE_MODE;
3367
3368/*
3369 * FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE enum
3370 */
3371
3372typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE {
3373FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL     = 0x00000000,
3374FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN  = 0x00000001,
3375} FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE;
3376
3377/*
3378 * FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT enum
3379 */
3380
3381typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT {
3382FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN    = 0x00000000,
3383FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD     = 0x00000001,
3384} FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT;
3385
3386/*
3387 * FMT_DEBUG_CNTL_COLOR_SELECT enum
3388 */
3389
3390typedef enum FMT_DEBUG_CNTL_COLOR_SELECT {
3391FMT_DEBUG_CNTL_COLOR_SELECT_BLUE         = 0x00000000,
3392FMT_DEBUG_CNTL_COLOR_SELECT_GREEN        = 0x00000001,
3393FMT_DEBUG_CNTL_COLOR_SELECT_RED1         = 0x00000002,
3394FMT_DEBUG_CNTL_COLOR_SELECT_RED2         = 0x00000003,
3395} FMT_DEBUG_CNTL_COLOR_SELECT;
3396
3397/*
3398 * FMT_SPATIAL_DITHER_MODE enum
3399 */
3400
3401typedef enum FMT_SPATIAL_DITHER_MODE {
3402FMT_SPATIAL_DITHER_MODE_0                = 0x00000000,
3403FMT_SPATIAL_DITHER_MODE_1                = 0x00000001,
3404FMT_SPATIAL_DITHER_MODE_2                = 0x00000002,
3405FMT_SPATIAL_DITHER_MODE_3                = 0x00000003,
3406} FMT_SPATIAL_DITHER_MODE;
3407
3408/*
3409 * FMT_STEREOSYNC_OVR_POL enum
3410 */
3411
3412typedef enum FMT_STEREOSYNC_OVR_POL {
3413FMT_STEREOSYNC_OVR_POL_INVERTED          = 0x00000000,
3414FMT_STEREOSYNC_OVR_POL_NOT_INVERTED      = 0x00000001,
3415} FMT_STEREOSYNC_OVR_POL;
3416
3417/*
3418 * FMT_DYNAMIC_EXP_MODE enum
3419 */
3420
3421typedef enum FMT_DYNAMIC_EXP_MODE {
3422FMT_DYNAMIC_EXP_MODE_10to12              = 0x00000000,
3423FMT_DYNAMIC_EXP_MODE_8to12               = 0x00000001,
3424} FMT_DYNAMIC_EXP_MODE;
3425
3426/*******************************************************
3427 * HPD Enums
3428 *******************************************************/
3429
3430/*
3431 * HPD_INT_CONTROL_ACK enum
3432 */
3433
3434typedef enum HPD_INT_CONTROL_ACK {
3435HPD_INT_CONTROL_ACK_0                    = 0x00000000,
3436HPD_INT_CONTROL_ACK_1                    = 0x00000001,
3437} HPD_INT_CONTROL_ACK;
3438
3439/*
3440 * HPD_INT_CONTROL_POLARITY enum
3441 */
3442
3443typedef enum HPD_INT_CONTROL_POLARITY {
3444HPD_INT_CONTROL_GEN_INT_ON_DISCON        = 0x00000000,
3445HPD_INT_CONTROL_GEN_INT_ON_CON           = 0x00000001,
3446} HPD_INT_CONTROL_POLARITY;
3447
3448/*
3449 * HPD_INT_CONTROL_RX_INT_ACK enum
3450 */
3451
3452typedef enum HPD_INT_CONTROL_RX_INT_ACK {
3453HPD_INT_CONTROL_RX_INT_ACK_0             = 0x00000000,
3454HPD_INT_CONTROL_RX_INT_ACK_1             = 0x00000001,
3455} HPD_INT_CONTROL_RX_INT_ACK;
3456
3457/*******************************************************
3458 * LB Enums
3459 *******************************************************/
3460
3461/*
3462 * LB_DATA_FORMAT_PIXEL_DEPTH enum
3463 */
3464
3465typedef enum LB_DATA_FORMAT_PIXEL_DEPTH {
3466LB_DATA_FORMAT_PIXEL_DEPTH_30BPP         = 0x00000000,
3467LB_DATA_FORMAT_PIXEL_DEPTH_24BPP         = 0x00000001,
3468LB_DATA_FORMAT_PIXEL_DEPTH_18BPP         = 0x00000002,
3469LB_DATA_FORMAT_PIXEL_DEPTH_36BPP         = 0x00000003,
3470} LB_DATA_FORMAT_PIXEL_DEPTH;
3471
3472/*
3473 * LB_DATA_FORMAT_PIXEL_EXPAN_MODE enum
3474 */
3475
3476typedef enum LB_DATA_FORMAT_PIXEL_EXPAN_MODE {
3477LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION = 0x00000000,
3478LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION = 0x00000001,
3479} LB_DATA_FORMAT_PIXEL_EXPAN_MODE;
3480
3481/*
3482 * LB_DATA_FORMAT_PIXEL_REDUCE_MODE enum
3483 */
3484
3485typedef enum LB_DATA_FORMAT_PIXEL_REDUCE_MODE {
3486LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION = 0x00000000,
3487LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING = 0x00000001,
3488} LB_DATA_FORMAT_PIXEL_REDUCE_MODE;
3489
3490/*
3491 * LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH enum
3492 */
3493
3494typedef enum LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH {
3495LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP = 0x00000000,
3496LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP = 0x00000001,
3497} LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH;
3498
3499/*
3500 * LB_DATA_FORMAT_INTERLEAVE_EN enum
3501 */
3502
3503typedef enum LB_DATA_FORMAT_INTERLEAVE_EN {
3504LB_DATA_FORMAT_INTERLEAVE_DISABLE        = 0x00000000,
3505LB_DATA_FORMAT_INTERLEAVE_ENABLE         = 0x00000001,
3506} LB_DATA_FORMAT_INTERLEAVE_EN;
3507
3508/*
3509 * LB_DATA_FORMAT_REQUEST_MODE enum
3510 */
3511
3512typedef enum LB_DATA_FORMAT_REQUEST_MODE {
3513LB_DATA_FORMAT_REQUEST_MODE_NORMAL       = 0x00000000,
3514LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE  = 0x00000001,
3515} LB_DATA_FORMAT_REQUEST_MODE;
3516
3517/*
3518 * LB_DATA_FORMAT_ALPHA_EN enum
3519 */
3520
3521typedef enum LB_DATA_FORMAT_ALPHA_EN {
3522LB_DATA_FORMAT_ALPHA_DISABLE             = 0x00000000,
3523LB_DATA_FORMAT_ALPHA_ENABLE              = 0x00000001,
3524} LB_DATA_FORMAT_ALPHA_EN;
3525
3526/*
3527 * LB_VLINE_START_END_VLINE_INV enum
3528 */
3529
3530typedef enum LB_VLINE_START_END_VLINE_INV {
3531LB_VLINE_START_END_VLINE_NORMAL          = 0x00000000,
3532LB_VLINE_START_END_VLINE_INVERSE         = 0x00000001,
3533} LB_VLINE_START_END_VLINE_INV;
3534
3535/*
3536 * LB_VLINE2_START_END_VLINE2_INV enum
3537 */
3538
3539typedef enum LB_VLINE2_START_END_VLINE2_INV {
3540LB_VLINE2_START_END_VLINE2_NORMAL        = 0x00000000,
3541LB_VLINE2_START_END_VLINE2_INVERSE       = 0x00000001,
3542} LB_VLINE2_START_END_VLINE2_INV;
3543
3544/*
3545 * LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK enum
3546 */
3547
3548typedef enum LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK {
3549LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE = 0x00000000,
3550LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE = 0x00000001,
3551} LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK;
3552
3553/*
3554 * LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK enum
3555 */
3556
3557typedef enum LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK {
3558LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE = 0x00000000,
3559LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE = 0x00000001,
3560} LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK;
3561
3562/*
3563 * LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK enum
3564 */
3565
3566typedef enum LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK {
3567LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE = 0x00000000,
3568LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE = 0x00000001,
3569} LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK;
3570
3571/*
3572 * LB_VLINE_STATUS_VLINE_ACK enum
3573 */
3574
3575typedef enum LB_VLINE_STATUS_VLINE_ACK {
3576LB_VLINE_STATUS_VLINE_NORMAL             = 0x00000000,
3577LB_VLINE_STATUS_VLINE_CLEAR              = 0x00000001,
3578} LB_VLINE_STATUS_VLINE_ACK;
3579
3580/*
3581 * LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE enum
3582 */
3583
3584typedef enum LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE {
3585LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED  = 0x00000000,
3586LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED  = 0x00000001,
3587} LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE;
3588
3589/*
3590 * LB_VLINE2_STATUS_VLINE2_ACK enum
3591 */
3592
3593typedef enum LB_VLINE2_STATUS_VLINE2_ACK {
3594LB_VLINE2_STATUS_VLINE2_NORMAL           = 0x00000000,
3595LB_VLINE2_STATUS_VLINE2_CLEAR            = 0x00000001,
3596} LB_VLINE2_STATUS_VLINE2_ACK;
3597
3598/*
3599 * LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE enum
3600 */
3601
3602typedef enum LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE {
3603LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED  = 0x00000000,
3604LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED  = 0x00000001,
3605} LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE;
3606
3607/*
3608 * LB_VBLANK_STATUS_VBLANK_ACK enum
3609 */
3610
3611typedef enum LB_VBLANK_STATUS_VBLANK_ACK {
3612LB_VBLANK_STATUS_VBLANK_NORMAL           = 0x00000000,
3613LB_VBLANK_STATUS_VBLANK_CLEAR            = 0x00000001,
3614} LB_VBLANK_STATUS_VBLANK_ACK;
3615
3616/*
3617 * LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE enum
3618 */
3619
3620typedef enum LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE {
3621LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED  = 0x00000000,
3622LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED  = 0x00000001,
3623} LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE;
3624
3625/*
3626 * LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL enum
3627 */
3628
3629typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL {
3630LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE  = 0x00000000,
3631LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK  = 0x00000001,
3632LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET  = 0x00000002,
3633LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET  = 0x00000003,
3634} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL;
3635
3636/*
3637 * LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 enum
3638 */
3639
3640typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 {
3641LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK  = 0x00000000,
3642LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC  = 0x00000001,
3643} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2;
3644
3645/*
3646 * LB_SYNC_RESET_SEL_LB_SYNC_DURATION enum
3647 */
3648
3649typedef enum LB_SYNC_RESET_SEL_LB_SYNC_DURATION {
3650LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS = 0x00000000,
3651LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS = 0x00000001,
3652LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS = 0x00000002,
3653LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS = 0x00000003,
3654} LB_SYNC_RESET_SEL_LB_SYNC_DURATION;
3655
3656/*
3657 * LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN enum
3658 */
3659
3660typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN {
3661LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE = 0x00000000,
3662LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE = 0x00000001,
3663} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN;
3664
3665/*
3666 * LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN enum
3667 */
3668
3669typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN {
3670LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE = 0x00000000,
3671LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE = 0x00000001,
3672} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN;
3673
3674/*
3675 * LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK enum
3676 */
3677
3678typedef enum LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK {
3679LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL  = 0x00000000,
3680LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET   = 0x00000001,
3681} LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK;
3682
3683/*
3684 * LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK enum
3685 */
3686
3687typedef enum LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK {
3688LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL   = 0x00000000,
3689LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET    = 0x00000001,
3690} LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK;
3691
3692/*
3693 * LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE enum
3694 */
3695
3696typedef enum LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE {
3697LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP  = 0x00000002,
3698LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP  = 0x00000003,
3699} LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE;
3700
3701/*
3702 * LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET enum
3703 */
3704
3705typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET {
3706LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL = 0x00000000,
3707LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE  = 0x00000001,
3708} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET;
3709
3710/*
3711 * LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK enum
3712 */
3713
3714typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK {
3715LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0 = 0x00000000,
3716LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1 = 0x00000001,
3717} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK;
3718
3719/*
3720 * LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE enum
3721 */
3722
3723typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE {
3724LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT  = 0x00000000,
3725LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG  = 0x00000001,
3726LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE  = 0x00000002,
3727} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE;
3728
3729/*
3730 * LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE enum
3731 */
3732
3733typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE {
3734LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE  = 0x00000000,
3735LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN  = 0x00000001,
3736} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE;
3737
3738/*
3739 * LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE enum
3740 */
3741
3742typedef enum LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE {
3743ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER  = 0x00000001,
3744ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE  = 0x00000002,
3745} LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE;
3746
3747/*
3748 * LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL enum
3749 */
3750
3751typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL {
3752LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0 = 0x00000000,
3753LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1 = 0x00000001,
3754} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL;
3755
3756/*
3757 * LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE enum
3758 */
3759
3760typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE {
3761LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE = 0x00000000,
3762LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE  = 0x00000001,
3763} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE;
3764
3765/*
3766 * LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO enum
3767 */
3768
3769typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO {
3770LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO = 0x00000000,
3771LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO  = 0x00000001,
3772} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO;
3773
3774/*
3775 * LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN enum
3776 */
3777
3778typedef enum LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN {
3779LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0 = 0x00000000,
3780LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1 = 0x00000001,
3781} LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN;
3782
3783/*******************************************************
3784 * DIG Enums
3785 *******************************************************/
3786
3787/*
3788 * HDMI_KEEPOUT_MODE enum
3789 */
3790
3791typedef enum HDMI_KEEPOUT_MODE {
3792HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC        = 0x00000000,
3793HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC      = 0x00000001,
3794} HDMI_KEEPOUT_MODE;
3795
3796/*
3797 * HDMI_DATA_SCRAMBLE_EN enum
3798 */
3799
3800typedef enum HDMI_DATA_SCRAMBLE_EN {
3801HDMI_DATA_SCRAMBLE_DISABLE               = 0x00000000,
3802HDMI_DATA_SCRAMBLE_ENABLE                = 0x00000001,
3803} HDMI_DATA_SCRAMBLE_EN;
3804
3805/*
3806 * HDMI_CLOCK_CHANNEL_RATE enum
3807 */
3808
3809typedef enum HDMI_CLOCK_CHANNEL_RATE {
3810HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE  = 0x00000000,
3811HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE  = 0x00000001,
3812} HDMI_CLOCK_CHANNEL_RATE;
3813
3814/*
3815 * HDMI_NO_EXTRA_NULL_PACKET_FILLED enum
3816 */
3817
3818typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED {
3819HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE     = 0x00000000,
3820HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE    = 0x00000001,
3821} HDMI_NO_EXTRA_NULL_PACKET_FILLED;
3822
3823/*
3824 * HDMI_PACKET_GEN_VERSION enum
3825 */
3826
3827typedef enum HDMI_PACKET_GEN_VERSION {
3828HDMI_PACKET_GEN_VERSION_OLD              = 0x00000000,
3829HDMI_PACKET_GEN_VERSION_NEW              = 0x00000001,
3830} HDMI_PACKET_GEN_VERSION;
3831
3832/*
3833 * HDMI_ERROR_ACK enum
3834 */
3835
3836typedef enum HDMI_ERROR_ACK {
3837HDMI_ERROR_ACK_INT                       = 0x00000000,
3838HDMI_ERROR_NOT_ACK                       = 0x00000001,
3839} HDMI_ERROR_ACK;
3840
3841/*
3842 * HDMI_ERROR_MASK enum
3843 */
3844
3845typedef enum HDMI_ERROR_MASK {
3846HDMI_ERROR_MASK_INT                      = 0x00000000,
3847HDMI_ERROR_NOT_MASK                      = 0x00000001,
3848} HDMI_ERROR_MASK;
3849
3850/*
3851 * HDMI_DEEP_COLOR_DEPTH enum
3852 */
3853
3854typedef enum HDMI_DEEP_COLOR_DEPTH {
3855HDMI_DEEP_COLOR_DEPTH_24BPP              = 0x00000000,
3856HDMI_DEEP_COLOR_DEPTH_30BPP              = 0x00000001,
3857HDMI_DEEP_COLOR_DEPTH_36BPP              = 0x00000002,
3858HDMI_DEEP_COLOR_DEPTH_RESERVED           = 0x00000003,
3859} HDMI_DEEP_COLOR_DEPTH;
3860
3861/*
3862 * HDMI_AUDIO_DELAY_EN enum
3863 */
3864
3865typedef enum HDMI_AUDIO_DELAY_EN {
3866HDMI_AUDIO_DELAY_DISABLE                 = 0x00000000,
3867HDMI_AUDIO_DELAY_58CLK                   = 0x00000001,
3868HDMI_AUDIO_DELAY_56CLK                   = 0x00000002,
3869HDMI_AUDIO_DELAY_RESERVED                = 0x00000003,
3870} HDMI_AUDIO_DELAY_EN;
3871
3872/*
3873 * HDMI_AUDIO_SEND_MAX_PACKETS enum
3874 */
3875
3876typedef enum HDMI_AUDIO_SEND_MAX_PACKETS {
3877HDMI_NOT_SEND_MAX_AUDIO_PACKETS          = 0x00000000,
3878HDMI_SEND_MAX_AUDIO_PACKETS              = 0x00000001,
3879} HDMI_AUDIO_SEND_MAX_PACKETS;
3880
3881/*
3882 * HDMI_ACR_SEND enum
3883 */
3884
3885typedef enum HDMI_ACR_SEND {
3886HDMI_ACR_NOT_SEND                        = 0x00000000,
3887HDMI_ACR_PKT_SEND                        = 0x00000001,
3888} HDMI_ACR_SEND;
3889
3890/*
3891 * HDMI_ACR_CONT enum
3892 */
3893
3894typedef enum HDMI_ACR_CONT {
3895HDMI_ACR_CONT_DISABLE                    = 0x00000000,
3896HDMI_ACR_CONT_ENABLE                     = 0x00000001,
3897} HDMI_ACR_CONT;
3898
3899/*
3900 * HDMI_ACR_SELECT enum
3901 */
3902
3903typedef enum HDMI_ACR_SELECT {
3904HDMI_ACR_SELECT_HW                       = 0x00000000,
3905HDMI_ACR_SELECT_32K                      = 0x00000001,
3906HDMI_ACR_SELECT_44K                      = 0x00000002,
3907HDMI_ACR_SELECT_48K                      = 0x00000003,
3908} HDMI_ACR_SELECT;
3909
3910/*
3911 * HDMI_ACR_SOURCE enum
3912 */
3913
3914typedef enum HDMI_ACR_SOURCE {
3915HDMI_ACR_SOURCE_HW                       = 0x00000000,
3916HDMI_ACR_SOURCE_SW                       = 0x00000001,
3917} HDMI_ACR_SOURCE;
3918
3919/*
3920 * HDMI_ACR_N_MULTIPLE enum
3921 */
3922
3923typedef enum HDMI_ACR_N_MULTIPLE {
3924HDMI_ACR_0_MULTIPLE_RESERVED             = 0x00000000,
3925HDMI_ACR_1_MULTIPLE                      = 0x00000001,
3926HDMI_ACR_2_MULTIPLE                      = 0x00000002,
3927HDMI_ACR_3_MULTIPLE_RESERVED             = 0x00000003,
3928HDMI_ACR_4_MULTIPLE                      = 0x00000004,
3929HDMI_ACR_5_MULTIPLE_RESERVED             = 0x00000005,
3930HDMI_ACR_6_MULTIPLE_RESERVED             = 0x00000006,
3931HDMI_ACR_7_MULTIPLE_RESERVED             = 0x00000007,
3932} HDMI_ACR_N_MULTIPLE;
3933
3934/*
3935 * HDMI_ACR_AUDIO_PRIORITY enum
3936 */
3937
3938typedef enum HDMI_ACR_AUDIO_PRIORITY {
3939HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE  = 0x00000000,
3940HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT  = 0x00000001,
3941} HDMI_ACR_AUDIO_PRIORITY;
3942
3943/*
3944 * HDMI_NULL_SEND enum
3945 */
3946
3947typedef enum HDMI_NULL_SEND {
3948HDMI_NULL_NOT_SEND                       = 0x00000000,
3949HDMI_NULL_PKT_SEND                       = 0x00000001,
3950} HDMI_NULL_SEND;
3951
3952/*
3953 * HDMI_GC_SEND enum
3954 */
3955
3956typedef enum HDMI_GC_SEND {
3957HDMI_GC_NOT_SEND                         = 0x00000000,
3958HDMI_GC_PKT_SEND                         = 0x00000001,
3959} HDMI_GC_SEND;
3960
3961/*
3962 * HDMI_GC_CONT enum
3963 */
3964
3965typedef enum HDMI_GC_CONT {
3966HDMI_GC_CONT_DISABLE                     = 0x00000000,
3967HDMI_GC_CONT_ENABLE                      = 0x00000001,
3968} HDMI_GC_CONT;
3969
3970/*
3971 * HDMI_ISRC_SEND enum
3972 */
3973
3974typedef enum HDMI_ISRC_SEND {
3975HDMI_ISRC_NOT_SEND                       = 0x00000000,
3976HDMI_ISRC_PKT_SEND                       = 0x00000001,
3977} HDMI_ISRC_SEND;
3978
3979/*
3980 * HDMI_ISRC_CONT enum
3981 */
3982
3983typedef enum HDMI_ISRC_CONT {
3984HDMI_ISRC_CONT_DISABLE                   = 0x00000000,
3985HDMI_ISRC_CONT_ENABLE                    = 0x00000001,
3986} HDMI_ISRC_CONT;
3987
3988/*
3989 * HDMI_AVI_INFO_SEND enum
3990 */
3991
3992typedef enum HDMI_AVI_INFO_SEND {
3993HDMI_AVI_INFO_NOT_SEND                   = 0x00000000,
3994HDMI_AVI_INFO_PKT_SEND                   = 0x00000001,
3995} HDMI_AVI_INFO_SEND;
3996
3997/*
3998 * HDMI_AVI_INFO_CONT enum
3999 */
4000
4001typedef enum HDMI_AVI_INFO_CONT {
4002HDMI_AVI_INFO_CONT_DISABLE               = 0x00000000,
4003HDMI_AVI_INFO_CONT_ENABLE                = 0x00000001,
4004} HDMI_AVI_INFO_CONT;
4005
4006/*
4007 * HDMI_AUDIO_INFO_SEND enum
4008 */
4009
4010typedef enum HDMI_AUDIO_INFO_SEND {
4011HDMI_AUDIO_INFO_NOT_SEND                 = 0x00000000,
4012HDMI_AUDIO_INFO_PKT_SEND                 = 0x00000001,
4013} HDMI_AUDIO_INFO_SEND;
4014
4015/*
4016 * HDMI_AUDIO_INFO_CONT enum
4017 */
4018
4019typedef enum HDMI_AUDIO_INFO_CONT {
4020HDMI_AUDIO_INFO_CONT_DISABLE             = 0x00000000,
4021HDMI_AUDIO_INFO_CONT_ENABLE              = 0x00000001,
4022} HDMI_AUDIO_INFO_CONT;
4023
4024/*
4025 * HDMI_MPEG_INFO_SEND enum
4026 */
4027
4028typedef enum HDMI_MPEG_INFO_SEND {
4029HDMI_MPEG_INFO_NOT_SEND                  = 0x00000000,
4030HDMI_MPEG_INFO_PKT_SEND                  = 0x00000001,
4031} HDMI_MPEG_INFO_SEND;
4032
4033/*
4034 * HDMI_MPEG_INFO_CONT enum
4035 */
4036
4037typedef enum HDMI_MPEG_INFO_CONT {
4038HDMI_MPEG_INFO_CONT_DISABLE              = 0x00000000,
4039HDMI_MPEG_INFO_CONT_ENABLE               = 0x00000001,
4040} HDMI_MPEG_INFO_CONT;
4041
4042/*
4043 * HDMI_GENERIC0_SEND enum
4044 */
4045
4046typedef enum HDMI_GENERIC0_SEND {
4047HDMI_GENERIC0_NOT_SEND                   = 0x00000000,
4048HDMI_GENERIC0_PKT_SEND                   = 0x00000001,
4049} HDMI_GENERIC0_SEND;
4050
4051/*
4052 * HDMI_GENERIC0_CONT enum
4053 */
4054
4055typedef enum HDMI_GENERIC0_CONT {
4056HDMI_GENERIC0_CONT_DISABLE               = 0x00000000,
4057HDMI_GENERIC0_CONT_ENABLE                = 0x00000001,
4058} HDMI_GENERIC0_CONT;
4059
4060/*
4061 * HDMI_GENERIC1_SEND enum
4062 */
4063
4064typedef enum HDMI_GENERIC1_SEND {
4065HDMI_GENERIC1_NOT_SEND                   = 0x00000000,
4066HDMI_GENERIC1_PKT_SEND                   = 0x00000001,
4067} HDMI_GENERIC1_SEND;
4068
4069/*
4070 * HDMI_GENERIC1_CONT enum
4071 */
4072
4073typedef enum HDMI_GENERIC1_CONT {
4074HDMI_GENERIC1_CONT_DISABLE               = 0x00000000,
4075HDMI_GENERIC1_CONT_ENABLE                = 0x00000001,
4076} HDMI_GENERIC1_CONT;
4077
4078/*
4079 * HDMI_GC_AVMUTE_CONT enum
4080 */
4081
4082typedef enum HDMI_GC_AVMUTE_CONT {
4083HDMI_GC_AVMUTE_CONT_DISABLE              = 0x00000000,
4084HDMI_GC_AVMUTE_CONT_ENABLE               = 0x00000001,
4085} HDMI_GC_AVMUTE_CONT;
4086
4087/*
4088 * HDMI_PACKING_PHASE_OVERRIDE enum
4089 */
4090
4091typedef enum HDMI_PACKING_PHASE_OVERRIDE {
4092HDMI_PACKING_PHASE_SET_BY_HW             = 0x00000000,
4093HDMI_PACKING_PHASE_SET_BY_SW             = 0x00000001,
4094} HDMI_PACKING_PHASE_OVERRIDE;
4095
4096/*
4097 * HDMI_GENERIC2_SEND enum
4098 */
4099
4100typedef enum HDMI_GENERIC2_SEND {
4101HDMI_GENERIC2_NOT_SEND                   = 0x00000000,
4102HDMI_GENERIC2_PKT_SEND                   = 0x00000001,
4103} HDMI_GENERIC2_SEND;
4104
4105/*
4106 * HDMI_GENERIC2_CONT enum
4107 */
4108
4109typedef enum HDMI_GENERIC2_CONT {
4110HDMI_GENERIC2_CONT_DISABLE               = 0x00000000,
4111HDMI_GENERIC2_CONT_ENABLE                = 0x00000001,
4112} HDMI_GENERIC2_CONT;
4113
4114/*
4115 * HDMI_GENERIC3_SEND enum
4116 */
4117
4118typedef enum HDMI_GENERIC3_SEND {
4119HDMI_GENERIC3_NOT_SEND                   = 0x00000000,
4120HDMI_GENERIC3_PKT_SEND                   = 0x00000001,
4121} HDMI_GENERIC3_SEND;
4122
4123/*
4124 * HDMI_GENERIC3_CONT enum
4125 */
4126
4127typedef enum HDMI_GENERIC3_CONT {
4128HDMI_GENERIC3_CONT_DISABLE               = 0x00000000,
4129HDMI_GENERIC3_CONT_ENABLE                = 0x00000001,
4130} HDMI_GENERIC3_CONT;
4131
4132/*
4133 * TMDS_PIXEL_ENCODING enum
4134 */
4135
4136typedef enum TMDS_PIXEL_ENCODING {
4137TMDS_PIXEL_ENCODING_444_OR_420           = 0x00000000,
4138TMDS_PIXEL_ENCODING_422                  = 0x00000001,
4139} TMDS_PIXEL_ENCODING;
4140
4141/*
4142 * TMDS_COLOR_FORMAT enum
4143 */
4144
4145typedef enum TMDS_COLOR_FORMAT {
4146TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP  = 0x00000000,
4147TMDS_COLOR_FORMAT_TWIN30BPP_LSB          = 0x00000001,
4148TMDS_COLOR_FORMAT_DUAL30BPP              = 0x00000002,
4149TMDS_COLOR_FORMAT_RESERVED               = 0x00000003,
4150} TMDS_COLOR_FORMAT;
4151
4152/*
4153 * TMDS_STEREOSYNC_CTL_SEL_REG enum
4154 */
4155
4156typedef enum TMDS_STEREOSYNC_CTL_SEL_REG {
4157TMDS_STEREOSYNC_CTL0                     = 0x00000000,
4158TMDS_STEREOSYNC_CTL1                     = 0x00000001,
4159TMDS_STEREOSYNC_CTL2                     = 0x00000002,
4160TMDS_STEREOSYNC_CTL3                     = 0x00000003,
4161} TMDS_STEREOSYNC_CTL_SEL_REG;
4162
4163/*
4164 * TMDS_CTL0_DATA_SEL enum
4165 */
4166
4167typedef enum TMDS_CTL0_DATA_SEL {
4168TMDS_CTL0_DATA_SEL0_RESERVED             = 0x00000000,
4169TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE       = 0x00000001,
4170TMDS_CTL0_DATA_SEL2_VSYNC                = 0x00000002,
4171TMDS_CTL0_DATA_SEL3_RESERVED             = 0x00000003,
4172TMDS_CTL0_DATA_SEL4_HSYNC                = 0x00000004,
4173TMDS_CTL0_DATA_SEL5_SEL7_RESERVED        = 0x00000005,
4174TMDS_CTL0_DATA_SEL8_RANDOM_DATA          = 0x00000006,
4175TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA    = 0x00000007,
4176} TMDS_CTL0_DATA_SEL;
4177
4178/*
4179 * TMDS_CTL0_DATA_INVERT enum
4180 */
4181
4182typedef enum TMDS_CTL0_DATA_INVERT {
4183TMDS_CTL0_DATA_NORMAL                    = 0x00000000,
4184TMDS_CTL0_DATA_INVERT_EN                 = 0x00000001,
4185} TMDS_CTL0_DATA_INVERT;
4186
4187/*
4188 * TMDS_CTL0_DATA_MODULATION enum
4189 */
4190
4191typedef enum TMDS_CTL0_DATA_MODULATION {
4192TMDS_CTL0_DATA_MODULATION_DISABLE        = 0x00000000,
4193TMDS_CTL0_DATA_MODULATION_BIT0           = 0x00000001,
4194TMDS_CTL0_DATA_MODULATION_BIT1           = 0x00000002,
4195TMDS_CTL0_DATA_MODULATION_BIT2           = 0x00000003,
4196} TMDS_CTL0_DATA_MODULATION;
4197
4198/*
4199 * TMDS_CTL0_PATTERN_OUT_EN enum
4200 */
4201
4202typedef enum TMDS_CTL0_PATTERN_OUT_EN {
4203TMDS_CTL0_PATTERN_OUT_DISABLE            = 0x00000000,
4204TMDS_CTL0_PATTERN_OUT_ENABLE             = 0x00000001,
4205} TMDS_CTL0_PATTERN_OUT_EN;
4206
4207/*
4208 * TMDS_CTL1_DATA_SEL enum
4209 */
4210
4211typedef enum TMDS_CTL1_DATA_SEL {
4212TMDS_CTL1_DATA_SEL0_RESERVED             = 0x00000000,
4213TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE       = 0x00000001,
4214TMDS_CTL1_DATA_SEL2_VSYNC                = 0x00000002,
4215TMDS_CTL1_DATA_SEL3_RESERVED             = 0x00000003,
4216TMDS_CTL1_DATA_SEL4_HSYNC                = 0x00000004,
4217TMDS_CTL1_DATA_SEL5_SEL7_RESERVED        = 0x00000005,
4218TMDS_CTL1_DATA_SEL8_BLANK_TIME           = 0x00000006,
4219TMDS_CTL1_DATA_SEL9_SEL15_RESERVED       = 0x00000007,
4220} TMDS_CTL1_DATA_SEL;
4221
4222/*
4223 * TMDS_CTL1_DATA_INVERT enum
4224 */
4225
4226typedef enum TMDS_CTL1_DATA_INVERT {
4227TMDS_CTL1_DATA_NORMAL                    = 0x00000000,
4228TMDS_CTL1_DATA_INVERT_EN                 = 0x00000001,
4229} TMDS_CTL1_DATA_INVERT;
4230
4231/*
4232 * TMDS_CTL1_DATA_MODULATION enum
4233 */
4234
4235typedef enum TMDS_CTL1_DATA_MODULATION {
4236TMDS_CTL1_DATA_MODULATION_DISABLE        = 0x00000000,
4237TMDS_CTL1_DATA_MODULATION_BIT0           = 0x00000001,
4238TMDS_CTL1_DATA_MODULATION_BIT1           = 0x00000002,
4239TMDS_CTL1_DATA_MODULATION_BIT2           = 0x00000003,
4240} TMDS_CTL1_DATA_MODULATION;
4241
4242/*
4243 * TMDS_CTL1_PATTERN_OUT_EN enum
4244 */
4245
4246typedef enum TMDS_CTL1_PATTERN_OUT_EN {
4247TMDS_CTL1_PATTERN_OUT_DISABLE            = 0x00000000,
4248TMDS_CTL1_PATTERN_OUT_ENABLE             = 0x00000001,
4249} TMDS_CTL1_PATTERN_OUT_EN;
4250
4251/*
4252 * TMDS_CTL2_DATA_SEL enum
4253 */
4254
4255typedef enum TMDS_CTL2_DATA_SEL {
4256TMDS_CTL2_DATA_SEL0_RESERVED             = 0x00000000,
4257TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE       = 0x00000001,
4258TMDS_CTL2_DATA_SEL2_VSYNC                = 0x00000002,
4259TMDS_CTL2_DATA_SEL3_RESERVED             = 0x00000003,
4260TMDS_CTL2_DATA_SEL4_HSYNC                = 0x00000004,
4261TMDS_CTL2_DATA_SEL5_SEL7_RESERVED        = 0x00000005,
4262TMDS_CTL2_DATA_SEL8_BLANK_TIME           = 0x00000006,
4263TMDS_CTL2_DATA_SEL9_SEL15_RESERVED       = 0x00000007,
4264} TMDS_CTL2_DATA_SEL;
4265
4266/*
4267 * TMDS_CTL2_DATA_INVERT enum
4268 */
4269
4270typedef enum TMDS_CTL2_DATA_INVERT {
4271TMDS_CTL2_DATA_NORMAL                    = 0x00000000,
4272TMDS_CTL2_DATA_INVERT_EN                 = 0x00000001,
4273} TMDS_CTL2_DATA_INVERT;
4274
4275/*
4276 * TMDS_CTL2_DATA_MODULATION enum
4277 */
4278
4279typedef enum TMDS_CTL2_DATA_MODULATION {
4280TMDS_CTL2_DATA_MODULATION_DISABLE        = 0x00000000,
4281TMDS_CTL2_DATA_MODULATION_BIT0           = 0x00000001,
4282TMDS_CTL2_DATA_MODULATION_BIT1           = 0x00000002,
4283TMDS_CTL2_DATA_MODULATION_BIT2           = 0x00000003,
4284} TMDS_CTL2_DATA_MODULATION;
4285
4286/*
4287 * TMDS_CTL2_PATTERN_OUT_EN enum
4288 */
4289
4290typedef enum TMDS_CTL2_PATTERN_OUT_EN {
4291TMDS_CTL2_PATTERN_OUT_DISABLE            = 0x00000000,
4292TMDS_CTL2_PATTERN_OUT_ENABLE             = 0x00000001,
4293} TMDS_CTL2_PATTERN_OUT_EN;
4294
4295/*
4296 * TMDS_CTL3_DATA_INVERT enum
4297 */
4298
4299typedef enum TMDS_CTL3_DATA_INVERT {
4300TMDS_CTL3_DATA_NORMAL                    = 0x00000000,
4301TMDS_CTL3_DATA_INVERT_EN                 = 0x00000001,
4302} TMDS_CTL3_DATA_INVERT;
4303
4304/*
4305 * TMDS_CTL3_DATA_MODULATION enum
4306 */
4307
4308typedef enum TMDS_CTL3_DATA_MODULATION {
4309TMDS_CTL3_DATA_MODULATION_DISABLE        = 0x00000000,
4310TMDS_CTL3_DATA_MODULATION_BIT0           = 0x00000001,
4311TMDS_CTL3_DATA_MODULATION_BIT1           = 0x00000002,
4312TMDS_CTL3_DATA_MODULATION_BIT2           = 0x00000003,
4313} TMDS_CTL3_DATA_MODULATION;
4314
4315/*
4316 * TMDS_CTL3_PATTERN_OUT_EN enum
4317 */
4318
4319typedef enum TMDS_CTL3_PATTERN_OUT_EN {
4320TMDS_CTL3_PATTERN_OUT_DISABLE            = 0x00000000,
4321TMDS_CTL3_PATTERN_OUT_ENABLE             = 0x00000001,
4322} TMDS_CTL3_PATTERN_OUT_EN;
4323
4324/*
4325 * TMDS_CTL3_DATA_SEL enum
4326 */
4327
4328typedef enum TMDS_CTL3_DATA_SEL {
4329TMDS_CTL3_DATA_SEL0_RESERVED             = 0x00000000,
4330TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE       = 0x00000001,
4331TMDS_CTL3_DATA_SEL2_VSYNC                = 0x00000002,
4332TMDS_CTL3_DATA_SEL3_RESERVED             = 0x00000003,
4333TMDS_CTL3_DATA_SEL4_HSYNC                = 0x00000004,
4334TMDS_CTL3_DATA_SEL5_SEL7_RESERVED        = 0x00000005,
4335TMDS_CTL3_DATA_SEL8_BLANK_TIME           = 0x00000006,
4336TMDS_CTL3_DATA_SEL9_SEL15_RESERVED       = 0x00000007,
4337} TMDS_CTL3_DATA_SEL;
4338
4339/*
4340 * DIG_FE_CNTL_SOURCE_SELECT enum
4341 */
4342
4343typedef enum DIG_FE_CNTL_SOURCE_SELECT {
4344DIG_FE_SOURCE_FROM_FMT0                  = 0x00000000,
4345DIG_FE_SOURCE_FROM_FMT1                  = 0x00000001,
4346DIG_FE_SOURCE_FROM_FMT2                  = 0x00000002,
4347DIG_FE_SOURCE_FROM_FMT3                  = 0x00000003,
4348DIG_FE_SOURCE_FROM_FMT4                  = 0x00000004,
4349DIG_FE_SOURCE_FROM_FMT5                  = 0x00000005,
4350} DIG_FE_CNTL_SOURCE_SELECT;
4351
4352/*
4353 * DIG_FE_CNTL_STEREOSYNC_SELECT enum
4354 */
4355
4356typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT {
4357DIG_FE_STEREOSYNC_FROM_FMT0              = 0x00000000,
4358DIG_FE_STEREOSYNC_FROM_FMT1              = 0x00000001,
4359DIG_FE_STEREOSYNC_FROM_FMT2              = 0x00000002,
4360DIG_FE_STEREOSYNC_FROM_FMT3              = 0x00000003,
4361DIG_FE_STEREOSYNC_FROM_FMT4              = 0x00000004,
4362DIG_FE_STEREOSYNC_FROM_FMT5              = 0x00000005,
4363} DIG_FE_CNTL_STEREOSYNC_SELECT;
4364
4365/*
4366 * DIG_FIFO_READ_CLOCK_SRC enum
4367 */
4368
4369typedef enum DIG_FIFO_READ_CLOCK_SRC {
4370DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG        = 0x00000000,
4371DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE  = 0x00000001,
4372} DIG_FIFO_READ_CLOCK_SRC;
4373
4374/*
4375 * DIG_OUTPUT_CRC_CNTL_LINK_SEL enum
4376 */
4377
4378typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL {
4379DIG_OUTPUT_CRC_ON_LINK0                  = 0x00000000,
4380DIG_OUTPUT_CRC_ON_LINK1                  = 0x00000001,
4381} DIG_OUTPUT_CRC_CNTL_LINK_SEL;
4382
4383/*
4384 * DIG_OUTPUT_CRC_DATA_SEL enum
4385 */
4386
4387typedef enum DIG_OUTPUT_CRC_DATA_SEL {
4388DIG_OUTPUT_CRC_FOR_FULLFRAME             = 0x00000000,
4389DIG_OUTPUT_CRC_FOR_ACTIVEONLY            = 0x00000001,
4390DIG_OUTPUT_CRC_FOR_VBI                   = 0x00000002,
4391DIG_OUTPUT_CRC_FOR_AUDIO                 = 0x00000003,
4392} DIG_OUTPUT_CRC_DATA_SEL;
4393
4394/*
4395 * DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN enum
4396 */
4397
4398typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN {
4399DIG_IN_NORMAL_OPERATION                  = 0x00000000,
4400DIG_IN_DEBUG_MODE                        = 0x00000001,
4401} DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN;
4402
4403/*
4404 * DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL enum
4405 */
4406
4407typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL {
4408DIG_10BIT_TEST_PATTERN                   = 0x00000000,
4409DIG_ALTERNATING_TEST_PATTERN             = 0x00000001,
4410} DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL;
4411
4412/*
4413 * DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN enum
4414 */
4415
4416typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN {
4417DIG_TEST_PATTERN_NORMAL                  = 0x00000000,
4418DIG_TEST_PATTERN_RANDOM                  = 0x00000001,
4419} DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN;
4420
4421/*
4422 * DIG_TEST_PATTERN_RANDOM_PATTERN_RESET enum
4423 */
4424
4425typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET {
4426DIG_RANDOM_PATTERN_ENABLED               = 0x00000000,
4427DIG_RANDOM_PATTERN_RESETED               = 0x00000001,
4428} DIG_TEST_PATTERN_RANDOM_PATTERN_RESET;
4429
4430/*
4431 * DIG_TEST_PATTERN_EXTERNAL_RESET_EN enum
4432 */
4433
4434typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN {
4435DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE   = 0x00000000,
4436DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG  = 0x00000001,
4437} DIG_TEST_PATTERN_EXTERNAL_RESET_EN;
4438
4439/*
4440 * DIG_RANDOM_PATTERN_SEED_RAN_PAT enum
4441 */
4442
4443typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT {
4444DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS  = 0x00000000,
4445DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH  = 0x00000001,
4446} DIG_RANDOM_PATTERN_SEED_RAN_PAT;
4447
4448/*
4449 * DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL enum
4450 */
4451
4452typedef enum DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL {
4453DIG_FIFO_USE_OVERWRITE_LEVEL             = 0x00000000,
4454DIG_FIFO_USE_CAL_AVERAGE_LEVEL           = 0x00000001,
4455} DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL;
4456
4457/*
4458 * DIG_FIFO_ERROR_ACK enum
4459 */
4460
4461typedef enum DIG_FIFO_ERROR_ACK {
4462DIG_FIFO_ERROR_ACK_INT                   = 0x00000000,
4463DIG_FIFO_ERROR_NOT_ACK                   = 0x00000001,
4464} DIG_FIFO_ERROR_ACK;
4465
4466/*
4467 * DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE enum
4468 */
4469
4470typedef enum DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE {
4471DIG_FIFO_NOT_FORCE_RECAL_AVERAGE         = 0x00000000,
4472DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL       = 0x00000001,
4473} DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE;
4474
4475/*
4476 * DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX enum
4477 */
4478
4479typedef enum DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX {
4480DIG_FIFO_NOT_FORCE_RECOMP_MINMAX         = 0x00000000,
4481DIG_FIFO_FORCE_RECOMP_MINMAX             = 0x00000001,
4482} DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX;
4483
4484/*
4485 * AFMT_INTERRUPT_STATUS_CHG_MASK enum
4486 */
4487
4488typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK {
4489AFMT_INTERRUPT_DISABLE                   = 0x00000000,
4490AFMT_INTERRUPT_ENABLE                    = 0x00000001,
4491} AFMT_INTERRUPT_STATUS_CHG_MASK;
4492
4493/*
4494 * HDMI_GC_AVMUTE enum
4495 */
4496
4497typedef enum HDMI_GC_AVMUTE {
4498HDMI_GC_AVMUTE_SET                       = 0x00000000,
4499HDMI_GC_AVMUTE_UNSET                     = 0x00000001,
4500} HDMI_GC_AVMUTE;
4501
4502/*
4503 * HDMI_DEFAULT_PAHSE enum
4504 */
4505
4506typedef enum HDMI_DEFAULT_PAHSE {
4507HDMI_DEFAULT_PHASE_IS_0                  = 0x00000000,
4508HDMI_DEFAULT_PHASE_IS_1                  = 0x00000001,
4509} HDMI_DEFAULT_PAHSE;
4510
4511/*
4512 * AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD enum
4513 */
4514
4515typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD {
4516AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS  = 0x00000000,
4517AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER       = 0x00000001,
4518} AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD;
4519
4520/*
4521 * AUDIO_LAYOUT_SELECT enum
4522 */
4523
4524typedef enum AUDIO_LAYOUT_SELECT {
4525AUDIO_LAYOUT_0                           = 0x00000000,
4526AUDIO_LAYOUT_1                           = 0x00000001,
4527} AUDIO_LAYOUT_SELECT;
4528
4529/*
4530 * AFMT_AUDIO_CRC_CONTROL_CONT enum
4531 */
4532
4533typedef enum AFMT_AUDIO_CRC_CONTROL_CONT {
4534AFMT_AUDIO_CRC_ONESHOT                   = 0x00000000,
4535AFMT_AUDIO_CRC_AUTO_RESTART              = 0x00000001,
4536} AFMT_AUDIO_CRC_CONTROL_CONT;
4537
4538/*
4539 * AFMT_AUDIO_CRC_CONTROL_SOURCE enum
4540 */
4541
4542typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE {
4543AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT    = 0x00000000,
4544AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT   = 0x00000001,
4545} AFMT_AUDIO_CRC_CONTROL_SOURCE;
4546
4547/*
4548 * AFMT_AUDIO_CRC_CONTROL_CH_SEL enum
4549 */
4550
4551typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL {
4552AFMT_AUDIO_CRC_CH0_SIG                   = 0x00000000,
4553AFMT_AUDIO_CRC_CH1_SIG                   = 0x00000001,
4554AFMT_AUDIO_CRC_CH2_SIG                   = 0x00000002,
4555AFMT_AUDIO_CRC_CH3_SIG                   = 0x00000003,
4556AFMT_AUDIO_CRC_CH4_SIG                   = 0x00000004,
4557AFMT_AUDIO_CRC_CH5_SIG                   = 0x00000005,
4558AFMT_AUDIO_CRC_CH6_SIG                   = 0x00000006,
4559AFMT_AUDIO_CRC_CH7_SIG                   = 0x00000007,
4560AFMT_AUDIO_CRC_RESERVED_8                = 0x00000008,
4561AFMT_AUDIO_CRC_RESERVED_9                = 0x00000009,
4562AFMT_AUDIO_CRC_RESERVED_10               = 0x0000000a,
4563AFMT_AUDIO_CRC_RESERVED_11               = 0x0000000b,
4564AFMT_AUDIO_CRC_RESERVED_12               = 0x0000000c,
4565AFMT_AUDIO_CRC_RESERVED_13               = 0x0000000d,
4566AFMT_AUDIO_CRC_RESERVED_14               = 0x0000000e,
4567AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT        = 0x0000000f,
4568} AFMT_AUDIO_CRC_CONTROL_CH_SEL;
4569
4570/*
4571 * AFMT_RAMP_CONTROL0_SIGN enum
4572 */
4573
4574typedef enum AFMT_RAMP_CONTROL0_SIGN {
4575AFMT_RAMP_SIGNED                         = 0x00000000,
4576AFMT_RAMP_UNSIGNED                       = 0x00000001,
4577} AFMT_RAMP_CONTROL0_SIGN;
4578
4579/*
4580 * AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND enum
4581 */
4582
4583typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND {
4584AFMT_AUDIO_PACKET_SENT_DISABLED          = 0x00000000,
4585AFMT_AUDIO_PACKET_SENT_ENABLED           = 0x00000001,
4586} AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND;
4587
4588/*
4589 * AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS enum
4590 */
4591
4592typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS {
4593AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED  = 0x00000000,
4594AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED  = 0x00000001,
4595} AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS;
4596
4597/*
4598 * AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE enum
4599 */
4600
4601typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE {
4602AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK  = 0x00000000,
4603AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS  = 0x00000001,
4604} AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE;
4605
4606/*
4607 * AFMT_AUDIO_SRC_CONTROL_SELECT enum
4608 */
4609
4610typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT {
4611AFMT_AUDIO_SRC_FROM_AZ_STREAM0           = 0x00000000,
4612AFMT_AUDIO_SRC_FROM_AZ_STREAM1           = 0x00000001,
4613AFMT_AUDIO_SRC_FROM_AZ_STREAM2           = 0x00000002,
4614AFMT_AUDIO_SRC_FROM_AZ_STREAM3           = 0x00000003,
4615AFMT_AUDIO_SRC_FROM_AZ_STREAM4           = 0x00000004,
4616AFMT_AUDIO_SRC_FROM_AZ_STREAM5           = 0x00000005,
4617AFMT_AUDIO_SRC_RESERVED                  = 0x00000006,
4618} AFMT_AUDIO_SRC_CONTROL_SELECT;
4619
4620/*
4621 * DIG_BE_CNTL_MODE enum
4622 */
4623
4624typedef enum DIG_BE_CNTL_MODE {
4625DIG_BE_DP_SST_MODE                       = 0x00000000,
4626DIG_BE_RESERVED1                         = 0x00000001,
4627DIG_BE_TMDS_DVI_MODE                     = 0x00000002,
4628DIG_BE_TMDS_HDMI_MODE                    = 0x00000003,
4629DIG_BE_SDVO_RESERVED                     = 0x00000004,
4630DIG_BE_DP_MST_MODE                       = 0x00000005,
4631DIG_BE_RESERVED2                         = 0x00000006,
4632DIG_BE_RESERVED3                         = 0x00000007,
4633} DIG_BE_CNTL_MODE;
4634
4635/*
4636 * DIG_BE_CNTL_HPD_SELECT enum
4637 */
4638
4639typedef enum DIG_BE_CNTL_HPD_SELECT {
4640DIG_BE_CNTL_HPD1                         = 0x00000000,
4641DIG_BE_CNTL_HPD2                         = 0x00000001,
4642DIG_BE_CNTL_HPD3                         = 0x00000002,
4643DIG_BE_CNTL_HPD4                         = 0x00000003,
4644DIG_BE_CNTL_HPD5                         = 0x00000004,
4645DIG_BE_CNTL_HPD6                         = 0x00000005,
4646} DIG_BE_CNTL_HPD_SELECT;
4647
4648/*
4649 * LVTMA_RANDOM_PATTERN_SEED_RAN_PAT enum
4650 */
4651
4652typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT {
4653LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS     = 0x00000000,
4654LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH   = 0x00000001,
4655} LVTMA_RANDOM_PATTERN_SEED_RAN_PAT;
4656
4657/*
4658 * TMDS_SYNC_PHASE enum
4659 */
4660
4661typedef enum TMDS_SYNC_PHASE {
4662TMDS_NOT_SYNC_PHASE_ON_FRAME_START       = 0x00000000,
4663TMDS_SYNC_PHASE_ON_FRAME_START           = 0x00000001,
4664} TMDS_SYNC_PHASE;
4665
4666/*
4667 * TMDS_DATA_SYNCHRONIZATION_DSINTSEL enum
4668 */
4669
4670typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL {
4671TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS  = 0x00000000,
4672TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL  = 0x00000001,
4673} TMDS_DATA_SYNCHRONIZATION_DSINTSEL;
4674
4675/*
4676 * TMDS_TRANSMITTER_ENABLE_HPD_MASK enum
4677 */
4678
4679typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK {
4680TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE   = 0x00000000,
4681TMDS_TRANSMITTER_HPD_MASK_OVERRIDE       = 0x00000001,
4682} TMDS_TRANSMITTER_ENABLE_HPD_MASK;
4683
4684/*
4685 * TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK enum
4686 */
4687
4688typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK {
4689TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE  = 0x00000000,
4690TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE  = 0x00000001,
4691} TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK;
4692
4693/*
4694 * TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK enum
4695 */
4696
4697typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK {
4698TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE  = 0x00000000,
4699TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE  = 0x00000001,
4700} TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK;
4701
4702/*
4703 * TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK enum
4704 */
4705
4706typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK {
4707TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE  = 0x00000000,
4708TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON  = 0x00000001,
4709TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON  = 0x00000002,
4710TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE  = 0x00000003,
4711} TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK;
4712
4713/*
4714 * TMDS_TRANSMITTER_CONTROL_IDSCKSELA enum
4715 */
4716
4717typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA {
4718TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK   = 0x00000000,
4719TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK     = 0x00000001,
4720} TMDS_TRANSMITTER_CONTROL_IDSCKSELA;
4721
4722/*
4723 * TMDS_TRANSMITTER_CONTROL_IDSCKSELB enum
4724 */
4725
4726typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB {
4727TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK   = 0x00000000,
4728TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK     = 0x00000001,
4729} TMDS_TRANSMITTER_CONTROL_IDSCKSELB;
4730
4731/*
4732 * TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN enum
4733 */
4734
4735typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN {
4736TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE   = 0x00000000,
4737TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE    = 0x00000001,
4738} TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN;
4739
4740/*
4741 * TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK enum
4742 */
4743
4744typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK {
4745TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD      = 0x00000000,
4746TMDS_TRANSMITTER_PLL_RST_ON_HPD          = 0x00000001,
4747} TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK;
4748
4749/*
4750 * TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS enum
4751 */
4752
4753typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS {
4754TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK   = 0x00000000,
4755TMDS_TRANSMITTER_TMCLK_FROM_PADS         = 0x00000001,
4756} TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS;
4757
4758/*
4759 * TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS enum
4760 */
4761
4762typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS {
4763TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK   = 0x00000000,
4764TMDS_TRANSMITTER_TDCLK_FROM_PADS         = 0x00000001,
4765} TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS;
4766
4767/*
4768 * TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN enum
4769 */
4770
4771typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN {
4772TMDS_TRANSMITTER_PLLSEL_BY_HW            = 0x00000000,
4773TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW  = 0x00000001,
4774} TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN;
4775
4776/*
4777 * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA enum
4778 */
4779
4780typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA {
4781TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT    = 0x00000000,
4782TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT  = 0x00000001,
4783} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA;
4784
4785/*
4786 * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB enum
4787 */
4788
4789typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB {
4790TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT    = 0x00000000,
4791TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT  = 0x00000001,
4792} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB;
4793
4794/*
4795 * TMDS_REG_TEST_OUTPUTA_CNTLA enum
4796 */
4797
4798typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA {
4799TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0      = 0x00000000,
4800TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1      = 0x00000001,
4801TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2      = 0x00000002,
4802TMDS_REG_TEST_OUTPUTA_CNTLA_NA           = 0x00000003,
4803} TMDS_REG_TEST_OUTPUTA_CNTLA;
4804
4805/*
4806 * TMDS_REG_TEST_OUTPUTB_CNTLB enum
4807 */
4808
4809typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB {
4810TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0      = 0x00000000,
4811TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1      = 0x00000001,
4812TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2      = 0x00000002,
4813TMDS_REG_TEST_OUTPUTB_CNTLB_NA           = 0x00000003,
4814} TMDS_REG_TEST_OUTPUTB_CNTLB;
4815
4816/*******************************************************
4817 * DCP Enums
4818 *******************************************************/
4819
4820/*
4821 * DCP_GRPH_ENABLE enum
4822 */
4823
4824typedef enum DCP_GRPH_ENABLE {
4825DCP_GRPH_ENABLE_FALSE                    = 0x00000000,
4826DCP_GRPH_ENABLE_TRUE                     = 0x00000001,
4827} DCP_GRPH_ENABLE;
4828
4829/*
4830 * DCP_GRPH_KEYER_ALPHA_SEL enum
4831 */
4832
4833typedef enum DCP_GRPH_KEYER_ALPHA_SEL {
4834DCP_GRPH_KEYER_ALPHA_SEL_FALSE           = 0x00000000,
4835DCP_GRPH_KEYER_ALPHA_SEL_TRUE            = 0x00000001,
4836} DCP_GRPH_KEYER_ALPHA_SEL;
4837
4838/*
4839 * DCP_GRPH_DEPTH enum
4840 */
4841
4842typedef enum DCP_GRPH_DEPTH {
4843DCP_GRPH_DEPTH_8BPP                      = 0x00000000,
4844DCP_GRPH_DEPTH_16BPP                     = 0x00000001,
4845DCP_GRPH_DEPTH_32BPP                     = 0x00000002,
4846DCP_GRPH_DEPTH_64BPP                     = 0x00000003,
4847} DCP_GRPH_DEPTH;
4848
4849/*
4850 * DCP_GRPH_NUM_BANKS enum
4851 */
4852
4853typedef enum DCP_GRPH_NUM_BANKS {
4854DCP_GRPH_NUM_BANKS_1BANK                 = 0x00000000,
4855DCP_GRPH_NUM_BANKS_2BANK                 = 0x00000001,
4856DCP_GRPH_NUM_BANKS_4BANK                 = 0x00000002,
4857DCP_GRPH_NUM_BANKS_8BANK                 = 0x00000003,
4858DCP_GRPH_NUM_BANKS_16BANK                = 0x00000004,
4859} DCP_GRPH_NUM_BANKS;
4860
4861/*
4862 * DCP_GRPH_NUM_PIPES enum
4863 */
4864
4865typedef enum DCP_GRPH_NUM_PIPES {
4866DCP_GRPH_NUM_PIPES_1PIPE                 = 0x00000000,
4867DCP_GRPH_NUM_PIPES_2PIPE                 = 0x00000001,
4868DCP_GRPH_NUM_PIPES_4PIPE                 = 0x00000002,
4869DCP_GRPH_NUM_PIPES_8PIPE                 = 0x00000003,
4870} DCP_GRPH_NUM_PIPES;
4871
4872/*
4873 * DCP_GRPH_FORMAT enum
4874 */
4875
4876typedef enum DCP_GRPH_FORMAT {
4877DCP_GRPH_FORMAT_8BPP                     = 0x00000000,
4878DCP_GRPH_FORMAT_16BPP                    = 0x00000001,
4879DCP_GRPH_FORMAT_32BPP                    = 0x00000002,
4880DCP_GRPH_FORMAT_64BPP                    = 0x00000003,
4881} DCP_GRPH_FORMAT;
4882
4883/*
4884 * DCP_GRPH_ADDRESS_TRANSLATION_ENABLE enum
4885 */
4886
4887typedef enum DCP_GRPH_ADDRESS_TRANSLATION_ENABLE {
4888DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE  = 0x00000000,
4889DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE  = 0x00000001,
4890} DCP_GRPH_ADDRESS_TRANSLATION_ENABLE;
4891
4892/*
4893 * DCP_GRPH_SW_MODE enum
4894 */
4895
4896typedef enum DCP_GRPH_SW_MODE {
4897DCP_GRPH_SW_MODE_0                       = 0x00000000,
4898DCP_GRPH_SW_MODE_2                       = 0x00000002,
4899DCP_GRPH_SW_MODE_3                       = 0x00000003,
4900DCP_GRPH_SW_MODE_22                      = 0x00000016,
4901DCP_GRPH_SW_MODE_23                      = 0x00000017,
4902DCP_GRPH_SW_MODE_26                      = 0x0000001a,
4903DCP_GRPH_SW_MODE_27                      = 0x0000001b,
4904DCP_GRPH_SW_MODE_30                      = 0x0000001e,
4905DCP_GRPH_SW_MODE_31                      = 0x0000001f,
4906} DCP_GRPH_SW_MODE;
4907
4908/*
4909 * DCP_GRPH_COLOR_EXPANSION_MODE enum
4910 */
4911
4912typedef enum DCP_GRPH_COLOR_EXPANSION_MODE {
4913DCP_GRPH_COLOR_EXPANSION_MODE_DEXP       = 0x00000000,
4914DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP       = 0x00000001,
4915} DCP_GRPH_COLOR_EXPANSION_MODE;
4916
4917/*
4918 * DCP_GRPH_LUT_10BIT_BYPASS_EN enum
4919 */
4920
4921typedef enum DCP_GRPH_LUT_10BIT_BYPASS_EN {
4922DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE       = 0x00000000,
4923DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE        = 0x00000001,
4924} DCP_GRPH_LUT_10BIT_BYPASS_EN;
4925
4926/*
4927 * DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN enum
4928 */
4929
4930typedef enum DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN {
4931DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE  = 0x00000000,
4932DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE  = 0x00000001,
4933} DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN;
4934
4935/*
4936 * DCP_GRPH_ENDIAN_SWAP enum
4937 */
4938
4939typedef enum DCP_GRPH_ENDIAN_SWAP {
4940DCP_GRPH_ENDIAN_SWAP_NONE                = 0x00000000,
4941DCP_GRPH_ENDIAN_SWAP_8IN16               = 0x00000001,
4942DCP_GRPH_ENDIAN_SWAP_8IN32               = 0x00000002,
4943DCP_GRPH_ENDIAN_SWAP_8IN64               = 0x00000003,
4944} DCP_GRPH_ENDIAN_SWAP;
4945
4946/*
4947 * DCP_GRPH_RED_CROSSBAR enum
4948 */
4949
4950typedef enum DCP_GRPH_RED_CROSSBAR {
4951DCP_GRPH_RED_CROSSBAR_FROM_R             = 0x00000000,
4952DCP_GRPH_RED_CROSSBAR_FROM_G             = 0x00000001,
4953DCP_GRPH_RED_CROSSBAR_FROM_B             = 0x00000002,
4954DCP_GRPH_RED_CROSSBAR_FROM_A             = 0x00000003,
4955} DCP_GRPH_RED_CROSSBAR;
4956
4957/*
4958 * DCP_GRPH_GREEN_CROSSBAR enum
4959 */
4960
4961typedef enum DCP_GRPH_GREEN_CROSSBAR {
4962DCP_GRPH_GREEN_CROSSBAR_FROM_G           = 0x00000000,
4963DCP_GRPH_GREEN_CROSSBAR_FROM_B           = 0x00000001,
4964DCP_GRPH_GREEN_CROSSBAR_FROM_A           = 0x00000002,
4965DCP_GRPH_GREEN_CROSSBAR_FROM_R           = 0x00000003,
4966} DCP_GRPH_GREEN_CROSSBAR;
4967
4968/*
4969 * DCP_GRPH_BLUE_CROSSBAR enum
4970 */
4971
4972typedef enum DCP_GRPH_BLUE_CROSSBAR {
4973DCP_GRPH_BLUE_CROSSBAR_FROM_B            = 0x00000000,
4974DCP_GRPH_BLUE_CROSSBAR_FROM_A            = 0x00000001,
4975DCP_GRPH_BLUE_CROSSBAR_FROM_R            = 0x00000002,
4976DCP_GRPH_BLUE_CROSSBAR_FROM_G            = 0x00000003,
4977} DCP_GRPH_BLUE_CROSSBAR;
4978
4979/*
4980 * DCP_GRPH_ALPHA_CROSSBAR enum
4981 */
4982
4983typedef enum DCP_GRPH_ALPHA_CROSSBAR {
4984DCP_GRPH_ALPHA_CROSSBAR_FROM_A           = 0x00000000,
4985DCP_GRPH_ALPHA_CROSSBAR_FROM_R           = 0x00000001,
4986DCP_GRPH_ALPHA_CROSSBAR_FROM_G           = 0x00000002,
4987DCP_GRPH_ALPHA_CROSSBAR_FROM_B           = 0x00000003,
4988} DCP_GRPH_ALPHA_CROSSBAR;
4989
4990/*
4991 * DCP_GRPH_PRIMARY_DFQ_ENABLE enum
4992 */
4993
4994typedef enum DCP_GRPH_PRIMARY_DFQ_ENABLE {
4995DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE        = 0x00000000,
4996DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE         = 0x00000001,
4997} DCP_GRPH_PRIMARY_DFQ_ENABLE;
4998
4999/*
5000 * DCP_GRPH_SECONDARY_DFQ_ENABLE enum
5001 */
5002
5003typedef enum DCP_GRPH_SECONDARY_DFQ_ENABLE {
5004DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE      = 0x00000000,
5005DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE       = 0x00000001,
5006} DCP_GRPH_SECONDARY_DFQ_ENABLE;
5007
5008/*
5009 * DCP_GRPH_INPUT_GAMMA_MODE enum
5010 */
5011
5012typedef enum DCP_GRPH_INPUT_GAMMA_MODE {
5013DCP_GRPH_INPUT_GAMMA_MODE_LUT            = 0x00000000,
5014DCP_GRPH_INPUT_GAMMA_MODE_BYPASS         = 0x00000001,
5015} DCP_GRPH_INPUT_GAMMA_MODE;
5016
5017/*
5018 * DCP_GRPH_MODE_UPDATE_PENDING enum
5019 */
5020
5021typedef enum DCP_GRPH_MODE_UPDATE_PENDING {
5022DCP_GRPH_MODE_UPDATE_PENDING_FALSE       = 0x00000000,
5023DCP_GRPH_MODE_UPDATE_PENDING_TRUE        = 0x00000001,
5024} DCP_GRPH_MODE_UPDATE_PENDING;
5025
5026/*
5027 * DCP_GRPH_MODE_UPDATE_TAKEN enum
5028 */
5029
5030typedef enum DCP_GRPH_MODE_UPDATE_TAKEN {
5031DCP_GRPH_MODE_UPDATE_TAKEN_FALSE         = 0x00000000,
5032DCP_GRPH_MODE_UPDATE_TAKEN_TRUE          = 0x00000001,
5033} DCP_GRPH_MODE_UPDATE_TAKEN;
5034
5035/*
5036 * DCP_GRPH_SURFACE_UPDATE_PENDING enum
5037 */
5038
5039typedef enum DCP_GRPH_SURFACE_UPDATE_PENDING {
5040DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE    = 0x00000000,
5041DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE     = 0x00000001,
5042} DCP_GRPH_SURFACE_UPDATE_PENDING;
5043
5044/*
5045 * DCP_GRPH_SURFACE_UPDATE_TAKEN enum
5046 */
5047
5048typedef enum DCP_GRPH_SURFACE_UPDATE_TAKEN {
5049DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE      = 0x00000000,
5050DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE       = 0x00000001,
5051} DCP_GRPH_SURFACE_UPDATE_TAKEN;
5052
5053/*
5054 * DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE enum
5055 */
5056
5057typedef enum DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE {
5058DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE = 0x00000000,
5059DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE = 0x00000001,
5060} DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE;
5061
5062/*
5063 * DCP_GRPH_UPDATE_LOCK enum
5064 */
5065
5066typedef enum DCP_GRPH_UPDATE_LOCK {
5067DCP_GRPH_UPDATE_LOCK_FALSE               = 0x00000000,
5068DCP_GRPH_UPDATE_LOCK_TRUE                = 0x00000001,
5069} DCP_GRPH_UPDATE_LOCK;
5070
5071/*
5072 * DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK enum
5073 */
5074
5075typedef enum DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
5076DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE  = 0x00000000,
5077DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE  = 0x00000001,
5078} DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK;
5079
5080/*
5081 * DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE enum
5082 */
5083
5084typedef enum DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
5085DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE  = 0x00000000,
5086DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE  = 0x00000001,
5087} DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE;
5088
5089/*
5090 * DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE enum
5091 */
5092
5093typedef enum DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
5094DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE  = 0x00000000,
5095DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE  = 0x00000001,
5096} DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE;
5097
5098/*
5099 * DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN enum
5100 */
5101
5102typedef enum DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN {
5103DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE  = 0x00000000,
5104DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE  = 0x00000001,
5105} DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
5106
5107/*
5108 * DCP_GRPH_XDMA_SUPER_AA_EN enum
5109 */
5110
5111typedef enum DCP_GRPH_XDMA_SUPER_AA_EN {
5112DCP_GRPH_XDMA_SUPER_AA_EN_FALSE          = 0x00000000,
5113DCP_GRPH_XDMA_SUPER_AA_EN_TRUE           = 0x00000001,
5114} DCP_GRPH_XDMA_SUPER_AA_EN;
5115
5116/*
5117 * DCP_GRPH_DFQ_RESET enum
5118 */
5119
5120typedef enum DCP_GRPH_DFQ_RESET {
5121DCP_GRPH_DFQ_RESET_FALSE                 = 0x00000000,
5122DCP_GRPH_DFQ_RESET_TRUE                  = 0x00000001,
5123} DCP_GRPH_DFQ_RESET;
5124
5125/*
5126 * DCP_GRPH_DFQ_SIZE enum
5127 */
5128
5129typedef enum DCP_GRPH_DFQ_SIZE {
5130DCP_GRPH_DFQ_SIZE_DEEP1                  = 0x00000000,
5131DCP_GRPH_DFQ_SIZE_DEEP2                  = 0x00000001,
5132DCP_GRPH_DFQ_SIZE_DEEP3                  = 0x00000002,
5133DCP_GRPH_DFQ_SIZE_DEEP4                  = 0x00000003,
5134DCP_GRPH_DFQ_SIZE_DEEP5                  = 0x00000004,
5135DCP_GRPH_DFQ_SIZE_DEEP6                  = 0x00000005,
5136DCP_GRPH_DFQ_SIZE_DEEP7                  = 0x00000006,
5137DCP_GRPH_DFQ_SIZE_DEEP8                  = 0x00000007,
5138} DCP_GRPH_DFQ_SIZE;
5139
5140/*
5141 * DCP_GRPH_DFQ_MIN_FREE_ENTRIES enum
5142 */
5143
5144typedef enum DCP_GRPH_DFQ_MIN_FREE_ENTRIES {
5145DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1          = 0x00000000,
5146DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2          = 0x00000001,
5147DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3          = 0x00000002,
5148DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4          = 0x00000003,
5149DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5          = 0x00000004,
5150DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6          = 0x00000005,
5151DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7          = 0x00000006,
5152DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8          = 0x00000007,
5153} DCP_GRPH_DFQ_MIN_FREE_ENTRIES;
5154
5155/*
5156 * DCP_GRPH_DFQ_RESET_ACK enum
5157 */
5158
5159typedef enum DCP_GRPH_DFQ_RESET_ACK {
5160DCP_GRPH_DFQ_RESET_ACK_FALSE             = 0x00000000,
5161DCP_GRPH_DFQ_RESET_ACK_TRUE              = 0x00000001,
5162} DCP_GRPH_DFQ_RESET_ACK;
5163
5164/*
5165 * DCP_GRPH_PFLIP_INT_CLEAR enum
5166 */
5167
5168typedef enum DCP_GRPH_PFLIP_INT_CLEAR {
5169DCP_GRPH_PFLIP_INT_CLEAR_FALSE           = 0x00000000,
5170DCP_GRPH_PFLIP_INT_CLEAR_TRUE            = 0x00000001,
5171} DCP_GRPH_PFLIP_INT_CLEAR;
5172
5173/*
5174 * DCP_GRPH_PFLIP_INT_MASK enum
5175 */
5176
5177typedef enum DCP_GRPH_PFLIP_INT_MASK {
5178DCP_GRPH_PFLIP_INT_MASK_FALSE            = 0x00000000,
5179DCP_GRPH_PFLIP_INT_MASK_TRUE             = 0x00000001,
5180} DCP_GRPH_PFLIP_INT_MASK;
5181
5182/*
5183 * DCP_GRPH_PFLIP_INT_TYPE enum
5184 */
5185
5186typedef enum DCP_GRPH_PFLIP_INT_TYPE {
5187DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL     = 0x00000000,
5188DCP_GRPH_PFLIP_INT_TYPE_PULSE            = 0x00000001,
5189} DCP_GRPH_PFLIP_INT_TYPE;
5190
5191/*
5192 * DCP_GRPH_PRESCALE_SELECT enum
5193 */
5194
5195typedef enum DCP_GRPH_PRESCALE_SELECT {
5196DCP_GRPH_PRESCALE_SELECT_FIXED           = 0x00000000,
5197DCP_GRPH_PRESCALE_SELECT_FLOATING        = 0x00000001,
5198} DCP_GRPH_PRESCALE_SELECT;
5199
5200/*
5201 * DCP_GRPH_PRESCALE_R_SIGN enum
5202 */
5203
5204typedef enum DCP_GRPH_PRESCALE_R_SIGN {
5205DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED        = 0x00000000,
5206DCP_GRPH_PRESCALE_R_SIGN_SIGNED          = 0x00000001,
5207} DCP_GRPH_PRESCALE_R_SIGN;
5208
5209/*
5210 * DCP_GRPH_PRESCALE_G_SIGN enum
5211 */
5212
5213typedef enum DCP_GRPH_PRESCALE_G_SIGN {
5214DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED        = 0x00000000,
5215DCP_GRPH_PRESCALE_G_SIGN_SIGNED          = 0x00000001,
5216} DCP_GRPH_PRESCALE_G_SIGN;
5217
5218/*
5219 * DCP_GRPH_PRESCALE_B_SIGN enum
5220 */
5221
5222typedef enum DCP_GRPH_PRESCALE_B_SIGN {
5223DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED        = 0x00000000,
5224DCP_GRPH_PRESCALE_B_SIGN_SIGNED          = 0x00000001,
5225} DCP_GRPH_PRESCALE_B_SIGN;
5226
5227/*
5228 * DCP_GRPH_PRESCALE_BYPASS enum
5229 */
5230
5231typedef enum DCP_GRPH_PRESCALE_BYPASS {
5232DCP_GRPH_PRESCALE_BYPASS_FALSE           = 0x00000000,
5233DCP_GRPH_PRESCALE_BYPASS_TRUE            = 0x00000001,
5234} DCP_GRPH_PRESCALE_BYPASS;
5235
5236/*
5237 * DCP_INPUT_CSC_GRPH_MODE enum
5238 */
5239
5240typedef enum DCP_INPUT_CSC_GRPH_MODE {
5241DCP_INPUT_CSC_GRPH_MODE_BYPASS           = 0x00000000,
5242DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF   = 0x00000001,
5243DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF      = 0x00000002,
5244DCP_INPUT_CSC_GRPH_MODE_RESERVED         = 0x00000003,
5245} DCP_INPUT_CSC_GRPH_MODE;
5246
5247/*
5248 * DCP_OUTPUT_CSC_GRPH_MODE enum
5249 */
5250
5251typedef enum DCP_OUTPUT_CSC_GRPH_MODE {
5252DCP_OUTPUT_CSC_GRPH_MODE_BYPASS          = 0x00000000,
5253DCP_OUTPUT_CSC_GRPH_MODE_RGB             = 0x00000001,
5254DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601        = 0x00000002,
5255DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709        = 0x00000003,
5256DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF  = 0x00000004,
5257DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF     = 0x00000005,
5258DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0       = 0x00000006,
5259DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1       = 0x00000007,
5260} DCP_OUTPUT_CSC_GRPH_MODE;
5261
5262/*
5263 * DCP_DENORM_MODE enum
5264 */
5265
5266typedef enum DCP_DENORM_MODE {
5267DCP_DENORM_MODE_UNITY                    = 0x00000000,
5268DCP_DENORM_MODE_6BIT                     = 0x00000001,
5269DCP_DENORM_MODE_8BIT                     = 0x00000002,
5270DCP_DENORM_MODE_10BIT                    = 0x00000003,
5271DCP_DENORM_MODE_11BIT                    = 0x00000004,
5272DCP_DENORM_MODE_12BIT                    = 0x00000005,
5273DCP_DENORM_MODE_RESERVED0                = 0x00000006,
5274DCP_DENORM_MODE_RESERVED1                = 0x00000007,
5275} DCP_DENORM_MODE;
5276
5277/*
5278 * DCP_DENORM_14BIT_OUT enum
5279 */
5280
5281typedef enum DCP_DENORM_14BIT_OUT {
5282DCP_DENORM_14BIT_OUT_FALSE               = 0x00000000,
5283DCP_DENORM_14BIT_OUT_TRUE                = 0x00000001,
5284} DCP_DENORM_14BIT_OUT;
5285
5286/*
5287 * DCP_OUT_ROUND_TRUNC_MODE enum
5288 */
5289
5290typedef enum DCP_OUT_ROUND_TRUNC_MODE {
5291DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12     = 0x00000000,
5292DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11     = 0x00000001,
5293DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10     = 0x00000002,
5294DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9      = 0x00000003,
5295DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8      = 0x00000004,
5296DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED  = 0x00000005,
5297DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14     = 0x00000006,
5298DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13     = 0x00000007,
5299DCP_OUT_ROUND_TRUNC_MODE_ROUND_12        = 0x00000008,
5300DCP_OUT_ROUND_TRUNC_MODE_ROUND_11        = 0x00000009,
5301DCP_OUT_ROUND_TRUNC_MODE_ROUND_10        = 0x0000000a,
5302DCP_OUT_ROUND_TRUNC_MODE_ROUND_9         = 0x0000000b,
5303DCP_OUT_ROUND_TRUNC_MODE_ROUND_8         = 0x0000000c,
5304DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED  = 0x0000000d,
5305DCP_OUT_ROUND_TRUNC_MODE_ROUND_14        = 0x0000000e,
5306DCP_OUT_ROUND_TRUNC_MODE_ROUND_13        = 0x0000000f,
5307} DCP_OUT_ROUND_TRUNC_MODE;
5308
5309/*
5310 * DCP_KEY_MODE enum
5311 */
5312
5313typedef enum DCP_KEY_MODE {
5314DCP_KEY_MODE_ALPHA0                      = 0x00000000,
5315DCP_KEY_MODE_ALPHA1                      = 0x00000001,
5316DCP_KEY_MODE_IN_RANGE_ALPHA1             = 0x00000002,
5317DCP_KEY_MODE_IN_RANGE_ALPHA0             = 0x00000003,
5318} DCP_KEY_MODE;
5319
5320/*
5321 * DCP_GRPH_DEGAMMA_MODE enum
5322 */
5323
5324typedef enum DCP_GRPH_DEGAMMA_MODE {
5325DCP_GRPH_DEGAMMA_MODE_BYPASS             = 0x00000000,
5326DCP_GRPH_DEGAMMA_MODE_ROMA               = 0x00000001,
5327DCP_GRPH_DEGAMMA_MODE_ROMB               = 0x00000002,
5328DCP_GRPH_DEGAMMA_MODE_RESERVED           = 0x00000003,
5329} DCP_GRPH_DEGAMMA_MODE;
5330
5331/*
5332 * DCP_CURSOR_DEGAMMA_MODE enum
5333 */
5334
5335typedef enum DCP_CURSOR_DEGAMMA_MODE {
5336DCP_CURSOR_DEGAMMA_MODE_BYPASS           = 0x00000000,
5337DCP_CURSOR_DEGAMMA_MODE_ROMA             = 0x00000001,
5338DCP_CURSOR_DEGAMMA_MODE_ROMB             = 0x00000002,
5339DCP_CURSOR_DEGAMMA_MODE_RESERVED         = 0x00000003,
5340} DCP_CURSOR_DEGAMMA_MODE;
5341
5342/*
5343 * DCP_GRPH_GAMUT_REMAP_MODE enum
5344 */
5345
5346typedef enum DCP_GRPH_GAMUT_REMAP_MODE {
5347DCP_GRPH_GAMUT_REMAP_MODE_BYPASS         = 0x00000000,
5348DCP_GRPH_GAMUT_REMAP_MODE_ROMA           = 0x00000001,
5349DCP_GRPH_GAMUT_REMAP_MODE_ROMB           = 0x00000002,
5350DCP_GRPH_GAMUT_REMAP_MODE_RESERVED       = 0x00000003,
5351} DCP_GRPH_GAMUT_REMAP_MODE;
5352
5353/*
5354 * DCP_SPATIAL_DITHER_EN enum
5355 */
5356
5357typedef enum DCP_SPATIAL_DITHER_EN {
5358DCP_SPATIAL_DITHER_EN_FALSE              = 0x00000000,
5359DCP_SPATIAL_DITHER_EN_TRUE               = 0x00000001,
5360} DCP_SPATIAL_DITHER_EN;
5361
5362/*
5363 * DCP_SPATIAL_DITHER_MODE enum
5364 */
5365
5366typedef enum DCP_SPATIAL_DITHER_MODE {
5367DCP_SPATIAL_DITHER_MODE_BYPASS           = 0x00000000,
5368DCP_SPATIAL_DITHER_MODE_ROMA             = 0x00000001,
5369DCP_SPATIAL_DITHER_MODE_ROMB             = 0x00000002,
5370DCP_SPATIAL_DITHER_MODE_RESERVED         = 0x00000003,
5371} DCP_SPATIAL_DITHER_MODE;
5372
5373/*
5374 * DCP_SPATIAL_DITHER_DEPTH enum
5375 */
5376
5377typedef enum DCP_SPATIAL_DITHER_DEPTH {
5378DCP_SPATIAL_DITHER_DEPTH_30BPP           = 0x00000000,
5379DCP_SPATIAL_DITHER_DEPTH_24BPP           = 0x00000001,
5380DCP_SPATIAL_DITHER_DEPTH_36BPP           = 0x00000002,
5381DCP_SPATIAL_DITHER_DEPTH_UNDEFINED       = 0x00000003,
5382} DCP_SPATIAL_DITHER_DEPTH;
5383
5384/*
5385 * DCP_FRAME_RANDOM_ENABLE enum
5386 */
5387
5388typedef enum DCP_FRAME_RANDOM_ENABLE {
5389DCP_FRAME_RANDOM_ENABLE_FALSE            = 0x00000000,
5390DCP_FRAME_RANDOM_ENABLE_TRUE             = 0x00000001,
5391} DCP_FRAME_RANDOM_ENABLE;
5392
5393/*
5394 * DCP_RGB_RANDOM_ENABLE enum
5395 */
5396
5397typedef enum DCP_RGB_RANDOM_ENABLE {
5398DCP_RGB_RANDOM_ENABLE_FALSE              = 0x00000000,
5399DCP_RGB_RANDOM_ENABLE_TRUE               = 0x00000001,
5400} DCP_RGB_RANDOM_ENABLE;
5401
5402/*
5403 * DCP_HIGHPASS_RANDOM_ENABLE enum
5404 */
5405
5406typedef enum DCP_HIGHPASS_RANDOM_ENABLE {
5407DCP_HIGHPASS_RANDOM_ENABLE_FALSE         = 0x00000000,
5408DCP_HIGHPASS_RANDOM_ENABLE_TRUE          = 0x00000001,
5409} DCP_HIGHPASS_RANDOM_ENABLE;
5410
5411/*
5412 * DCP_CURSOR_EN enum
5413 */
5414
5415typedef enum DCP_CURSOR_EN {
5416DCP_CURSOR_EN_FALSE                      = 0x00000000,
5417DCP_CURSOR_EN_TRUE                       = 0x00000001,
5418} DCP_CURSOR_EN;
5419
5420/*
5421 * DCP_CUR_INV_TRANS_CLAMP enum
5422 */
5423
5424typedef enum DCP_CUR_INV_TRANS_CLAMP {
5425DCP_CUR_INV_TRANS_CLAMP_FALSE            = 0x00000000,
5426DCP_CUR_INV_TRANS_CLAMP_TRUE             = 0x00000001,
5427} DCP_CUR_INV_TRANS_CLAMP;
5428
5429/*
5430 * DCP_CURSOR_MODE enum
5431 */
5432
5433typedef enum DCP_CURSOR_MODE {
5434DCP_CURSOR_MODE_MONO_2BPP                = 0x00000000,
5435DCP_CURSOR_MODE_24BPP_1BIT               = 0x00000001,
5436DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI      = 0x00000002,
5437DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI    = 0x00000003,
5438} DCP_CURSOR_MODE;
5439
5440/*
5441 * DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM enum
5442 */
5443
5444typedef enum DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM {
5445DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_ONE  = 0x00000000,
5446DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_TWO  = 0x00000001,
5447} DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM;
5448
5449/*
5450 * DCP_CURSOR_2X_MAGNIFY enum
5451 */
5452
5453typedef enum DCP_CURSOR_2X_MAGNIFY {
5454DCP_CURSOR_2X_MAGNIFY_FALSE              = 0x00000000,
5455DCP_CURSOR_2X_MAGNIFY_TRUE               = 0x00000001,
5456} DCP_CURSOR_2X_MAGNIFY;
5457
5458/*
5459 * DCP_CURSOR_FORCE_MC_ON enum
5460 */
5461
5462typedef enum DCP_CURSOR_FORCE_MC_ON {
5463DCP_CURSOR_FORCE_MC_ON_FALSE             = 0x00000000,
5464DCP_CURSOR_FORCE_MC_ON_TRUE              = 0x00000001,
5465} DCP_CURSOR_FORCE_MC_ON;
5466
5467/*
5468 * DCP_CURSOR_URGENT_CONTROL enum
5469 */
5470
5471typedef enum DCP_CURSOR_URGENT_CONTROL {
5472DCP_CURSOR_URGENT_CONTROL_MODE_0         = 0x00000000,
5473DCP_CURSOR_URGENT_CONTROL_MODE_1         = 0x00000001,
5474DCP_CURSOR_URGENT_CONTROL_MODE_2         = 0x00000002,
5475DCP_CURSOR_URGENT_CONTROL_MODE_3         = 0x00000003,
5476DCP_CURSOR_URGENT_CONTROL_MODE_4         = 0x00000004,
5477} DCP_CURSOR_URGENT_CONTROL;
5478
5479/*
5480 * DCP_CURSOR_UPDATE_PENDING enum
5481 */
5482
5483typedef enum DCP_CURSOR_UPDATE_PENDING {
5484DCP_CURSOR_UPDATE_PENDING_FALSE          = 0x00000000,
5485DCP_CURSOR_UPDATE_PENDING_TRUE           = 0x00000001,
5486} DCP_CURSOR_UPDATE_PENDING;
5487
5488/*
5489 * DCP_CURSOR_UPDATE_TAKEN enum
5490 */
5491
5492typedef enum DCP_CURSOR_UPDATE_TAKEN {
5493DCP_CURSOR_UPDATE_TAKEN_FALSE            = 0x00000000,
5494DCP_CURSOR_UPDATE_TAKEN_TRUE             = 0x00000001,
5495} DCP_CURSOR_UPDATE_TAKEN;
5496
5497/*
5498 * DCP_CURSOR_UPDATE_LOCK enum
5499 */
5500
5501typedef enum DCP_CURSOR_UPDATE_LOCK {
5502DCP_CURSOR_UPDATE_LOCK_FALSE             = 0x00000000,
5503DCP_CURSOR_UPDATE_LOCK_TRUE              = 0x00000001,
5504} DCP_CURSOR_UPDATE_LOCK;
5505
5506/*
5507 * DCP_CURSOR_DISABLE_MULTIPLE_UPDATE enum
5508 */
5509
5510typedef enum DCP_CURSOR_DISABLE_MULTIPLE_UPDATE {
5511DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE  = 0x00000000,
5512DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE  = 0x00000001,
5513} DCP_CURSOR_DISABLE_MULTIPLE_UPDATE;
5514
5515/*
5516 * DCP_CURSOR_UPDATE_STEREO_MODE enum
5517 */
5518
5519typedef enum DCP_CURSOR_UPDATE_STEREO_MODE {
5520DCP_CURSOR_UPDATE_STEREO_MODE_BOTH       = 0x00000000,
5521DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY  = 0x00000001,
5522DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED  = 0x00000002,
5523DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY  = 0x00000003,
5524} DCP_CURSOR_UPDATE_STEREO_MODE;
5525
5526/*
5527 * DCP_CUR2_INV_TRANS_CLAMP enum
5528 */
5529
5530typedef enum DCP_CUR2_INV_TRANS_CLAMP {
5531DCP_CUR2_INV_TRANS_CLAMP_FALSE           = 0x00000000,
5532DCP_CUR2_INV_TRANS_CLAMP_TRUE            = 0x00000001,
5533} DCP_CUR2_INV_TRANS_CLAMP;
5534
5535/*
5536 * DCP_CUR_REQUEST_FILTER_DIS enum
5537 */
5538
5539typedef enum DCP_CUR_REQUEST_FILTER_DIS {
5540DCP_CUR_REQUEST_FILTER_DIS_FALSE         = 0x00000000,
5541DCP_CUR_REQUEST_FILTER_DIS_TRUE          = 0x00000001,
5542} DCP_CUR_REQUEST_FILTER_DIS;
5543
5544/*
5545 * DCP_CURSOR_STEREO_EN enum
5546 */
5547
5548typedef enum DCP_CURSOR_STEREO_EN {
5549DCP_CURSOR_STEREO_EN_FALSE               = 0x00000000,
5550DCP_CURSOR_STEREO_EN_TRUE                = 0x00000001,
5551} DCP_CURSOR_STEREO_EN;
5552
5553/*
5554 * DCP_CURSOR_STEREO_OFFSET_YNX enum
5555 */
5556
5557typedef enum DCP_CURSOR_STEREO_OFFSET_YNX {
5558DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION  = 0x00000000,
5559DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION  = 0x00000001,
5560} DCP_CURSOR_STEREO_OFFSET_YNX;
5561
5562/*
5563 * DCP_DC_LUT_RW_MODE enum
5564 */
5565
5566typedef enum DCP_DC_LUT_RW_MODE {
5567DCP_DC_LUT_RW_MODE_256_ENTRY             = 0x00000000,
5568DCP_DC_LUT_RW_MODE_PWL                   = 0x00000001,
5569} DCP_DC_LUT_RW_MODE;
5570
5571/*
5572 * DCP_DC_LUT_VGA_ACCESS_ENABLE enum
5573 */
5574
5575typedef enum DCP_DC_LUT_VGA_ACCESS_ENABLE {
5576DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE       = 0x00000000,
5577DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE        = 0x00000001,
5578} DCP_DC_LUT_VGA_ACCESS_ENABLE;
5579
5580/*
5581 * DCP_DC_LUT_AUTOFILL enum
5582 */
5583
5584typedef enum DCP_DC_LUT_AUTOFILL {
5585DCP_DC_LUT_AUTOFILL_FALSE                = 0x00000000,
5586DCP_DC_LUT_AUTOFILL_TRUE                 = 0x00000001,
5587} DCP_DC_LUT_AUTOFILL;
5588
5589/*
5590 * DCP_DC_LUT_AUTOFILL_DONE enum
5591 */
5592
5593typedef enum DCP_DC_LUT_AUTOFILL_DONE {
5594DCP_DC_LUT_AUTOFILL_DONE_FALSE           = 0x00000000,
5595DCP_DC_LUT_AUTOFILL_DONE_TRUE            = 0x00000001,
5596} DCP_DC_LUT_AUTOFILL_DONE;
5597
5598/*
5599 * DCP_DC_LUT_INC_B enum
5600 */
5601
5602typedef enum DCP_DC_LUT_INC_B {
5603DCP_DC_LUT_INC_B_NA                      = 0x00000000,
5604DCP_DC_LUT_INC_B_2                       = 0x00000001,
5605DCP_DC_LUT_INC_B_4                       = 0x00000002,
5606DCP_DC_LUT_INC_B_8                       = 0x00000003,
5607DCP_DC_LUT_INC_B_16                      = 0x00000004,
5608DCP_DC_LUT_INC_B_32                      = 0x00000005,
5609DCP_DC_LUT_INC_B_64                      = 0x00000006,
5610DCP_DC_LUT_INC_B_128                     = 0x00000007,
5611DCP_DC_LUT_INC_B_256                     = 0x00000008,
5612DCP_DC_LUT_INC_B_512                     = 0x00000009,
5613} DCP_DC_LUT_INC_B;
5614
5615/*
5616 * DCP_DC_LUT_DATA_B_SIGNED_EN enum
5617 */
5618
5619typedef enum DCP_DC_LUT_DATA_B_SIGNED_EN {
5620DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE        = 0x00000000,
5621DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE         = 0x00000001,
5622} DCP_DC_LUT_DATA_B_SIGNED_EN;
5623
5624/*
5625 * DCP_DC_LUT_DATA_B_FLOAT_POINT_EN enum
5626 */
5627
5628typedef enum DCP_DC_LUT_DATA_B_FLOAT_POINT_EN {
5629DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE   = 0x00000000,
5630DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE    = 0x00000001,
5631} DCP_DC_LUT_DATA_B_FLOAT_POINT_EN;
5632
5633/*
5634 * DCP_DC_LUT_DATA_B_FORMAT enum
5635 */
5636
5637typedef enum DCP_DC_LUT_DATA_B_FORMAT {
5638DCP_DC_LUT_DATA_B_FORMAT_U0P10           = 0x00000000,
5639DCP_DC_LUT_DATA_B_FORMAT_S1P10           = 0x00000001,
5640DCP_DC_LUT_DATA_B_FORMAT_U1P11           = 0x00000002,
5641DCP_DC_LUT_DATA_B_FORMAT_U0P12           = 0x00000003,
5642} DCP_DC_LUT_DATA_B_FORMAT;
5643
5644/*
5645 * DCP_DC_LUT_INC_G enum
5646 */
5647
5648typedef enum DCP_DC_LUT_INC_G {
5649DCP_DC_LUT_INC_G_NA                      = 0x00000000,
5650DCP_DC_LUT_INC_G_2                       = 0x00000001,
5651DCP_DC_LUT_INC_G_4                       = 0x00000002,
5652DCP_DC_LUT_INC_G_8                       = 0x00000003,
5653DCP_DC_LUT_INC_G_16                      = 0x00000004,
5654DCP_DC_LUT_INC_G_32                      = 0x00000005,
5655DCP_DC_LUT_INC_G_64                      = 0x00000006,
5656DCP_DC_LUT_INC_G_128                     = 0x00000007,
5657DCP_DC_LUT_INC_G_256                     = 0x00000008,
5658DCP_DC_LUT_INC_G_512                     = 0x00000009,
5659} DCP_DC_LUT_INC_G;
5660
5661/*
5662 * DCP_DC_LUT_DATA_G_SIGNED_EN enum
5663 */
5664
5665typedef enum DCP_DC_LUT_DATA_G_SIGNED_EN {
5666DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE        = 0x00000000,
5667DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE         = 0x00000001,
5668} DCP_DC_LUT_DATA_G_SIGNED_EN;
5669
5670/*
5671 * DCP_DC_LUT_DATA_G_FLOAT_POINT_EN enum
5672 */
5673
5674typedef enum DCP_DC_LUT_DATA_G_FLOAT_POINT_EN {
5675DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE   = 0x00000000,
5676DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE    = 0x00000001,
5677} DCP_DC_LUT_DATA_G_FLOAT_POINT_EN;
5678
5679/*
5680 * DCP_DC_LUT_DATA_G_FORMAT enum
5681 */
5682
5683typedef enum DCP_DC_LUT_DATA_G_FORMAT {
5684DCP_DC_LUT_DATA_G_FORMAT_U0P10           = 0x00000000,
5685DCP_DC_LUT_DATA_G_FORMAT_S1P10           = 0x00000001,
5686DCP_DC_LUT_DATA_G_FORMAT_U1P11           = 0x00000002,
5687DCP_DC_LUT_DATA_G_FORMAT_U0P12           = 0x00000003,
5688} DCP_DC_LUT_DATA_G_FORMAT;
5689
5690/*
5691 * DCP_DC_LUT_INC_R enum
5692 */
5693
5694typedef enum DCP_DC_LUT_INC_R {
5695DCP_DC_LUT_INC_R_NA                      = 0x00000000,
5696DCP_DC_LUT_INC_R_2                       = 0x00000001,
5697DCP_DC_LUT_INC_R_4                       = 0x00000002,
5698DCP_DC_LUT_INC_R_8                       = 0x00000003,
5699DCP_DC_LUT_INC_R_16                      = 0x00000004,
5700DCP_DC_LUT_INC_R_32                      = 0x00000005,
5701DCP_DC_LUT_INC_R_64                      = 0x00000006,
5702DCP_DC_LUT_INC_R_128                     = 0x00000007,
5703DCP_DC_LUT_INC_R_256                     = 0x00000008,
5704DCP_DC_LUT_INC_R_512                     = 0x00000009,
5705} DCP_DC_LUT_INC_R;
5706
5707/*
5708 * DCP_DC_LUT_DATA_R_SIGNED_EN enum
5709 */
5710
5711typedef enum DCP_DC_LUT_DATA_R_SIGNED_EN {
5712DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE        = 0x00000000,
5713DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE         = 0x00000001,
5714} DCP_DC_LUT_DATA_R_SIGNED_EN;
5715
5716/*
5717 * DCP_DC_LUT_DATA_R_FLOAT_POINT_EN enum
5718 */
5719
5720typedef enum DCP_DC_LUT_DATA_R_FLOAT_POINT_EN {
5721DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE   = 0x00000000,
5722DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE    = 0x00000001,
5723} DCP_DC_LUT_DATA_R_FLOAT_POINT_EN;
5724
5725/*
5726 * DCP_DC_LUT_DATA_R_FORMAT enum
5727 */
5728
5729typedef enum DCP_DC_LUT_DATA_R_FORMAT {
5730DCP_DC_LUT_DATA_R_FORMAT_U0P10           = 0x00000000,
5731DCP_DC_LUT_DATA_R_FORMAT_S1P10           = 0x00000001,
5732DCP_DC_LUT_DATA_R_FORMAT_U1P11           = 0x00000002,