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23#ifndef _HWMGR_H_
24#define _HWMGR_H_
25
26#include <linux/seq_file.h>
27#include "amd_powerplay.h"
28#include "hardwaremanager.h"
29#include "hwmgr_ppt.h"
30#include "ppatomctrl.h"
31#include "power_state.h"
32#include "smu_helper.h"
33
34struct pp_hwmgr;
35struct phm_fan_speed_info;
36struct pp_atomctrl_voltage_table;
37
38#define VOLTAGE_SCALE 4
39#define VOLTAGE_VID_OFFSET_SCALE1 625
40#define VOLTAGE_VID_OFFSET_SCALE2 100
41
42enum DISPLAY_GAP {
43 DISPLAY_GAP_VBLANK_OR_WM = 0,
44 DISPLAY_GAP_VBLANK = 1,
45 DISPLAY_GAP_WATERMARK = 2,
46 DISPLAY_GAP_IGNORE = 3
47};
48typedef enum DISPLAY_GAP DISPLAY_GAP;
49
50enum BACO_STATE {
51 BACO_STATE_OUT = 0,
52 BACO_STATE_IN,
53};
54
55struct vi_dpm_level {
56 bool enabled;
57 uint32_t value;
58 uint32_t param1;
59};
60
61struct vi_dpm_table {
62 uint32_t count;
63 struct vi_dpm_level dpm_level[];
64};
65
66#define PCIE_PERF_REQ_REMOVE_REGISTRY 0
67#define PCIE_PERF_REQ_FORCE_LOWPOWER 1
68#define PCIE_PERF_REQ_GEN1 2
69#define PCIE_PERF_REQ_GEN2 3
70#define PCIE_PERF_REQ_GEN3 4
71
72enum PHM_BackEnd_Magic {
73 PHM_Dummy_Magic = 0xAA5555AA,
74 PHM_RV770_Magic = 0xDCBAABCD,
75 PHM_Kong_Magic = 0x239478DF,
76 PHM_NIslands_Magic = 0x736C494E,
77 PHM_Sumo_Magic = 0x8339FA11,
78 PHM_SIslands_Magic = 0x369431AC,
79 PHM_Trinity_Magic = 0x96751873,
80 PHM_CIslands_Magic = 0x38AC78B0,
81 PHM_Kv_Magic = 0xDCBBABC0,
82 PHM_VIslands_Magic = 0x20130307,
83 PHM_Cz_Magic = 0x67DCBA25,
84 PHM_Rv_Magic = 0x20161121
85};
86
87struct phm_set_power_state_input {
88 const struct pp_hw_power_state *pcurrent_state;
89 const struct pp_hw_power_state *pnew_state;
90};
91
92struct phm_clock_array {
93 uint32_t count;
94 uint32_t values[];
95};
96
97struct phm_clock_voltage_dependency_record {
98 uint32_t clk;
99 uint32_t v;
100};
101
102struct phm_vceclock_voltage_dependency_record {
103 uint32_t ecclk;
104 uint32_t evclk;
105 uint32_t v;
106};
107
108struct phm_uvdclock_voltage_dependency_record {
109 uint32_t vclk;
110 uint32_t dclk;
111 uint32_t v;
112};
113
114struct phm_samuclock_voltage_dependency_record {
115 uint32_t samclk;
116 uint32_t v;
117};
118
119struct phm_acpclock_voltage_dependency_record {
120 uint32_t acpclk;
121 uint32_t v;
122};
123
124struct phm_clock_voltage_dependency_table {
125 uint32_t count;
126 struct phm_clock_voltage_dependency_record entries[];
127};
128
129struct phm_phase_shedding_limits_record {
130 uint32_t Voltage;
131 uint32_t Sclk;
132 uint32_t Mclk;
133};
134
135struct phm_uvd_clock_voltage_dependency_record {
136 uint32_t vclk;
137 uint32_t dclk;
138 uint32_t v;
139};
140
141struct phm_uvd_clock_voltage_dependency_table {
142 uint8_t count;
143 struct phm_uvd_clock_voltage_dependency_record entries[];
144};
145
146struct phm_acp_clock_voltage_dependency_record {
147 uint32_t acpclk;
148 uint32_t v;
149};
150
151struct phm_acp_clock_voltage_dependency_table {
152 uint32_t count;
153 struct phm_acp_clock_voltage_dependency_record entries[];
154};
155
156struct phm_vce_clock_voltage_dependency_record {
157 uint32_t ecclk;
158 uint32_t evclk;
159 uint32_t v;
160};
161
162struct phm_phase_shedding_limits_table {
163 uint32_t count;
164 struct phm_phase_shedding_limits_record entries[];
165};
166
167struct phm_vceclock_voltage_dependency_table {
168 uint8_t count;
169 struct phm_vceclock_voltage_dependency_record entries[1];
170};
171
172struct phm_uvdclock_voltage_dependency_table {
173 uint8_t count;
174 struct phm_uvdclock_voltage_dependency_record entries[1];
175};
176
177struct phm_samuclock_voltage_dependency_table {
178 uint8_t count;
179 struct phm_samuclock_voltage_dependency_record entries[1];
180};
181
182struct phm_acpclock_voltage_dependency_table {
183 uint32_t count;
184 struct phm_acpclock_voltage_dependency_record entries[1];
185};
186
187struct phm_vce_clock_voltage_dependency_table {
188 uint8_t count;
189 struct phm_vce_clock_voltage_dependency_record entries[];
190};
191
192
193enum SMU_ASIC_RESET_MODE
194{
195 SMU_ASIC_RESET_MODE_0,
196 SMU_ASIC_RESET_MODE_1,
197 SMU_ASIC_RESET_MODE_2,
198};
199
200struct pp_smumgr_func {
201 char *name;
202 int (*smu_init)(struct pp_hwmgr *hwmgr);
203 int (*smu_fini)(struct pp_hwmgr *hwmgr);
204 int (*start_smu)(struct pp_hwmgr *hwmgr);
205 int (*check_fw_load_finish)(struct pp_hwmgr *hwmgr,
206 uint32_t firmware);
207 int (*request_smu_load_fw)(struct pp_hwmgr *hwmgr);
208 int (*request_smu_load_specific_fw)(struct pp_hwmgr *hwmgr,
209 uint32_t firmware);
210 uint32_t (*get_argument)(struct pp_hwmgr *hwmgr);
211 int (*send_msg_to_smc)(struct pp_hwmgr *hwmgr, uint16_t msg);
212 int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr *hwmgr,
213 uint16_t msg, uint32_t parameter);
214 int (*download_pptable_settings)(struct pp_hwmgr *hwmgr,
215 void **table);
216 int (*upload_pptable_settings)(struct pp_hwmgr *hwmgr);
217 int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type);
218 int (*process_firmware_header)(struct pp_hwmgr *hwmgr);
219 int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr);
220 int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr);
221 int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr);
222 int (*init_smc_table)(struct pp_hwmgr *hwmgr);
223 int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr);
224 int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr);
225 int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr);
226 uint32_t (*get_offsetof)(uint32_t type, uint32_t member);
227 uint32_t (*get_mac_definition)(uint32_t value);
228 bool (*is_dpm_running)(struct pp_hwmgr *hwmgr);
229 bool (*is_hw_avfs_present)(struct pp_hwmgr *hwmgr);
230 int (*update_dpm_settings)(struct pp_hwmgr *hwmgr, void *profile_setting);
231 int (*smc_table_manager)(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw);
232 int (*stop_smc)(struct pp_hwmgr *hwmgr);
233};
234
235struct pp_hwmgr_func {
236 int (*backend_init)(struct pp_hwmgr *hw_mgr);
237 int (*backend_fini)(struct pp_hwmgr *hw_mgr);
238 int (*asic_setup)(struct pp_hwmgr *hw_mgr);
239 int (*get_power_state_size)(struct pp_hwmgr *hw_mgr);
240
241 int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr,
242 struct pp_power_state *prequest_ps,
243 const struct pp_power_state *pcurrent_ps);
244
245 int (*apply_clocks_adjust_rules)(struct pp_hwmgr *hwmgr);
246
247 int (*force_dpm_level)(struct pp_hwmgr *hw_mgr,
248 enum amd_dpm_forced_level level);
249
250 int (*dynamic_state_management_enable)(
251 struct pp_hwmgr *hw_mgr);
252 int (*dynamic_state_management_disable)(
253 struct pp_hwmgr *hw_mgr);
254
255 int (*patch_boot_state)(struct pp_hwmgr *hwmgr,
256 struct pp_hw_power_state *hw_ps);
257
258 int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr,
259 unsigned long, struct pp_power_state *);
260 int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
261 int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
262 void (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
263 void (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
264 void (*powergate_acp)(struct pp_hwmgr *hwmgr, bool bgate);
265 uint32_t (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
266 uint32_t (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
267 int (*power_state_set)(struct pp_hwmgr *hwmgr,
268 const void *state);
269 int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr);
270 int (*pre_display_config_changed)(struct pp_hwmgr *hwmgr);
271 int (*display_config_changed)(struct pp_hwmgr *hwmgr);
272 int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr);
273 int (*update_clock_gatings)(struct pp_hwmgr *hwmgr,
274 const uint32_t *msg_id);
275 int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
276 int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
277 int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr);
278 int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
279 void (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode);
280 uint32_t (*get_fan_control_mode)(struct pp_hwmgr *hwmgr);
281 int (*set_fan_speed_pwm)(struct pp_hwmgr *hwmgr, uint32_t speed);
282 int (*get_fan_speed_pwm)(struct pp_hwmgr *hwmgr, uint32_t *speed);
283 int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t speed);
284 int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed);
285 int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr);
286 int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr);
287 int (*register_irq_handlers)(struct pp_hwmgr *hwmgr);
288 bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr);
289 int (*check_states_equal)(struct pp_hwmgr *hwmgr,
290 const struct pp_hw_power_state *pstate1,
291 const struct pp_hw_power_state *pstate2,
292 bool *equal);
293 int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr);
294 int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time,
295 bool cc6_disable, bool pstate_disable,
296 bool pstate_switch_disable);
297 int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
298 struct amd_pp_simple_clock_info *info);
299 int (*get_performance_level)(struct pp_hwmgr *, const struct pp_hw_power_state *,
300 PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *);
301 int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr,
302 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
303 int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
304 int (*get_clock_by_type_with_latency)(struct pp_hwmgr *hwmgr,
305 enum amd_pp_clock_type type,
306 struct pp_clock_levels_with_latency *clocks);
307 int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr,
308 enum amd_pp_clock_type type,
309 struct pp_clock_levels_with_voltage *clocks);
310 int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr, void *clock_ranges);
311 int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
312 struct pp_display_clock_request *clock);
313 int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
314 int (*power_off_asic)(struct pp_hwmgr *hwmgr);
315 int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
316 int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
317 int (*powergate_gfx)(struct pp_hwmgr *hwmgr, bool enable);
318 int (*get_sclk_od)(struct pp_hwmgr *hwmgr);
319 int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
320 int (*get_mclk_od)(struct pp_hwmgr *hwmgr);
321 int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
322 int (*read_sensor)(struct pp_hwmgr *hwmgr, int idx, void *value, int *size);
323 int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable);
324 int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr);
325 int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count);
326 int (*set_min_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock);
327 int (*start_thermal_controller)(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *range);
328 int (*notify_cac_buffer_info)(struct pp_hwmgr *hwmgr,
329 uint32_t virtual_addr_low,
330 uint32_t virtual_addr_hi,
331 uint32_t mc_addr_low,
332 uint32_t mc_addr_hi,
333 uint32_t size);
334 int (*update_nbdpm_pstate)(struct pp_hwmgr *hwmgr,
335 bool enable,
336 bool lock);
337 int (*get_thermal_temperature_range)(struct pp_hwmgr *hwmgr,
338 struct PP_TemperatureRange *range);
339 int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf);
340 int (*set_power_profile_mode)(struct pp_hwmgr *hwmgr, long *input, uint32_t size);
341 int (*odn_edit_dpm_table)(struct pp_hwmgr *hwmgr,
342 enum PP_OD_DPM_TABLE_COMMAND type,
343 long *input, uint32_t size);
344 int (*set_fine_grain_clk_vol)(struct pp_hwmgr *hwmgr,
345 enum PP_OD_DPM_TABLE_COMMAND type,
346 long *input, uint32_t size);
347 int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n);
348 int (*powergate_mmhub)(struct pp_hwmgr *hwmgr);
349 int (*smus_notify_pwe)(struct pp_hwmgr *hwmgr);
350 int (*powergate_sdma)(struct pp_hwmgr *hwmgr, bool bgate);
351 int (*enable_mgpu_fan_boost)(struct pp_hwmgr *hwmgr);
352 int (*set_hard_min_dcefclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
353 int (*set_hard_min_fclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
354 int (*set_hard_min_gfxclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
355 int (*set_soft_max_gfxclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
356 int (*get_asic_baco_capability)(struct pp_hwmgr *hwmgr, bool *cap);
357 int (*get_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
358 int (*set_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
359 int (*get_ppfeature_status)(struct pp_hwmgr *hwmgr, char *buf);
360 int (*set_ppfeature_status)(struct pp_hwmgr *hwmgr, uint64_t ppfeature_masks);
361 int (*set_mp1_state)(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state);
362 int (*asic_reset)(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode);
363 int (*smu_i2c_bus_access)(struct pp_hwmgr *hwmgr, bool aquire);
364 int (*set_df_cstate)(struct pp_hwmgr *hwmgr, enum pp_df_cstate state);
365 int (*set_xgmi_pstate)(struct pp_hwmgr *hwmgr, uint32_t pstate);
366 int (*disable_power_features_for_compute_performance)(struct pp_hwmgr *hwmgr,
367 bool disable);
368 ssize_t (*get_gpu_metrics)(struct pp_hwmgr *hwmgr, void **table);
369 int (*gfx_state_change)(struct pp_hwmgr *hwmgr, uint32_t state);
370};
371
372struct pp_table_func {
373 int (*pptable_init)(struct pp_hwmgr *hw_mgr);
374 int (*pptable_fini)(struct pp_hwmgr *hw_mgr);
375 int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr);
376 int (*pptable_get_vce_state_table_entry)(
377 struct pp_hwmgr *hwmgr,
378 unsigned long i,
379 struct amd_vce_state *vce_state,
380 void **clock_info,
381 unsigned long *flag);
382};
383
384union phm_cac_leakage_record {
385 struct {
386 uint16_t Vddc;
387 uint32_t Leakage;
388 };
389 struct {
390 uint16_t Vddc1;
391 uint16_t Vddc2;
392 uint16_t Vddc3;
393 };
394};
395
396struct phm_cac_leakage_table {
397 uint32_t count;
398 union phm_cac_leakage_record entries[];
399};
400
401struct phm_samu_clock_voltage_dependency_record {
402 uint32_t samclk;
403 uint32_t v;
404};
405
406
407struct phm_samu_clock_voltage_dependency_table {
408 uint8_t count;
409 struct phm_samu_clock_voltage_dependency_record entries[];
410};
411
412struct phm_cac_tdp_table {
413 uint16_t usTDP;
414 uint16_t usConfigurableTDP;
415 uint16_t usTDC;
416 uint16_t usBatteryPowerLimit;
417 uint16_t usSmallPowerLimit;
418 uint16_t usLowCACLeakage;
419 uint16_t usHighCACLeakage;
420 uint16_t usMaximumPowerDeliveryLimit;
421 uint16_t usEDCLimit;
422 uint16_t usOperatingTempMinLimit;
423 uint16_t usOperatingTempMaxLimit;
424 uint16_t usOperatingTempStep;
425 uint16_t usOperatingTempHyst;
426 uint16_t usDefaultTargetOperatingTemp;
427 uint16_t usTargetOperatingTemp;
428 uint16_t usPowerTuneDataSetID;
429 uint16_t usSoftwareShutdownTemp;
430 uint16_t usClockStretchAmount;
431 uint16_t usTemperatureLimitHotspot;
432 uint16_t usTemperatureLimitLiquid1;
433 uint16_t usTemperatureLimitLiquid2;
434 uint16_t usTemperatureLimitVrVddc;
435 uint16_t usTemperatureLimitVrMvdd;
436 uint16_t usTemperatureLimitPlx;
437 uint8_t ucLiquid1_I2C_address;
438 uint8_t ucLiquid2_I2C_address;
439 uint8_t ucLiquid_I2C_Line;
440 uint8_t ucVr_I2C_address;
441 uint8_t ucVr_I2C_Line;
442 uint8_t ucPlx_I2C_address;
443 uint8_t ucPlx_I2C_Line;
444 uint32_t usBoostPowerLimit;
445 uint8_t ucCKS_LDO_REFSEL;
446 uint8_t ucHotSpotOnly;
447};
448
449struct phm_tdp_table {
450 uint16_t usTDP;
451 uint16_t usConfigurableTDP;
452 uint16_t usTDC;
453 uint16_t usBatteryPowerLimit;
454 uint16_t usSmallPowerLimit;
455 uint16_t usLowCACLeakage;
456 uint16_t usHighCACLeakage;
457 uint16_t usMaximumPowerDeliveryLimit;
458 uint16_t usEDCLimit;
459 uint16_t usOperatingTempMinLimit;
460 uint16_t usOperatingTempMaxLimit;
461 uint16_t usOperatingTempStep;
462 uint16_t usOperatingTempHyst;
463 uint16_t usDefaultTargetOperatingTemp;
464 uint16_t usTargetOperatingTemp;
465 uint16_t usPowerTuneDataSetID;
466 uint16_t usSoftwareShutdownTemp;
467 uint16_t usClockStretchAmount;
468 uint16_t usTemperatureLimitTedge;
469 uint16_t usTemperatureLimitHotspot;
470 uint16_t usTemperatureLimitLiquid1;
471 uint16_t usTemperatureLimitLiquid2;
472 uint16_t usTemperatureLimitHBM;
473 uint16_t usTemperatureLimitVrVddc;
474 uint16_t usTemperatureLimitVrMvdd;
475 uint16_t usTemperatureLimitPlx;
476 uint8_t ucLiquid1_I2C_address;
477 uint8_t ucLiquid2_I2C_address;
478 uint8_t ucLiquid_I2C_Line;
479 uint8_t ucVr_I2C_address;
480 uint8_t ucVr_I2C_Line;
481 uint8_t ucPlx_I2C_address;
482 uint8_t ucPlx_I2C_Line;
483 uint8_t ucLiquid_I2C_LineSDA;
484 uint8_t ucVr_I2C_LineSDA;
485 uint8_t ucPlx_I2C_LineSDA;
486 uint32_t usBoostPowerLimit;
487 uint16_t usBoostStartTemperature;
488 uint16_t usBoostStopTemperature;
489 uint32_t ulBoostClock;
490};
491
492struct phm_ppm_table {
493 uint8_t ppm_design;
494 uint16_t cpu_core_number;
495 uint32_t platform_tdp;
496 uint32_t small_ac_platform_tdp;
497 uint32_t platform_tdc;
498 uint32_t small_ac_platform_tdc;
499 uint32_t apu_tdp;
500 uint32_t dgpu_tdp;
501 uint32_t dgpu_ulv_power;
502 uint32_t tj_max;
503};
504
505struct phm_vq_budgeting_record {
506 uint32_t ulCUs;
507 uint32_t ulSustainableSOCPowerLimitLow;
508 uint32_t ulSustainableSOCPowerLimitHigh;
509 uint32_t ulMinSclkLow;
510 uint32_t ulMinSclkHigh;
511 uint8_t ucDispConfig;
512 uint32_t ulDClk;
513 uint32_t ulEClk;
514 uint32_t ulSustainableSclk;
515 uint32_t ulSustainableCUs;
516};
517
518struct phm_vq_budgeting_table {
519 uint8_t numEntries;
520 struct phm_vq_budgeting_record entries[1];
521};
522
523struct phm_clock_and_voltage_limits {
524 uint32_t sclk;
525 uint32_t mclk;
526 uint32_t gfxclk;
527 uint16_t vddc;
528 uint16_t vddci;
529 uint16_t vddgfx;
530 uint16_t vddmem;
531};
532
533
534
535struct phm_ppt_v1_information {
536 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
537 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
538 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
539 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
540 struct phm_clock_array *valid_sclk_values;
541 struct phm_clock_array *valid_mclk_values;
542 struct phm_clock_array *valid_socclk_values;
543 struct phm_clock_array *valid_dcefclk_values;
544 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
545 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
546 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
547 struct phm_ppm_table *ppm_parameter_table;
548 struct phm_cac_tdp_table *cac_dtp_table;
549 struct phm_tdp_table *tdp_table;
550 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
551 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
552 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
553 struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
554 struct phm_ppt_v1_pcie_table *pcie_table;
555 struct phm_ppt_v1_gpio_table *gpio_table;
556 uint16_t us_ulv_voltage_offset;
557 uint16_t us_ulv_smnclk_did;
558 uint16_t us_ulv_mp1clk_did;
559 uint16_t us_ulv_gfxclk_bypass;
560 uint16_t us_gfxclk_slew_rate;
561 uint16_t us_min_gfxclk_freq_limit;
562};
563
564struct phm_ppt_v2_information {
565 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
566 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
567 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
568 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
569 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_pixclk;
570 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dispclk;
571 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_phyclk;
572 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
573
574 struct phm_clock_voltage_dependency_table *vddc_dep_on_dalpwrl;
575
576 struct phm_clock_array *valid_sclk_values;
577 struct phm_clock_array *valid_mclk_values;
578 struct phm_clock_array *valid_socclk_values;
579 struct phm_clock_array *valid_dcefclk_values;
580
581 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
582 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
583
584 struct phm_ppm_table *ppm_parameter_table;
585 struct phm_cac_tdp_table *cac_dtp_table;
586 struct phm_tdp_table *tdp_table;
587
588 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
589 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
590 struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
591 struct phm_ppt_v1_voltage_lookup_table *vddci_lookup_table;
592
593 struct phm_ppt_v1_pcie_table *pcie_table;
594
595 uint16_t us_ulv_voltage_offset;
596 uint16_t us_ulv_smnclk_did;
597 uint16_t us_ulv_mp1clk_did;
598 uint16_t us_ulv_gfxclk_bypass;
599 uint16_t us_gfxclk_slew_rate;
600 uint16_t us_min_gfxclk_freq_limit;
601
602 uint8_t uc_gfx_dpm_voltage_mode;
603 uint8_t uc_soc_dpm_voltage_mode;
604 uint8_t uc_uclk_dpm_voltage_mode;
605 uint8_t uc_uvd_dpm_voltage_mode;
606 uint8_t uc_vce_dpm_voltage_mode;
607 uint8_t uc_mp0_dpm_voltage_mode;
608 uint8_t uc_dcef_dpm_voltage_mode;
609};
610
611struct phm_ppt_v3_information
612{
613 uint8_t uc_thermal_controller_type;
614
615 uint16_t us_small_power_limit1;
616 uint16_t us_small_power_limit2;
617 uint16_t us_boost_power_limit;
618
619 uint16_t us_od_turbo_power_limit;
620 uint16_t us_od_powersave_power_limit;
621 uint16_t us_software_shutdown_temp;
622
623 uint32_t *power_saving_clock_max;
624 uint32_t *power_saving_clock_min;
625
626 uint8_t *od_feature_capabilities;
627 uint32_t *od_settings_max;
628 uint32_t *od_settings_min;
629
630 void *smc_pptable;
631};
632
633struct phm_dynamic_state_info {
634 struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
635 struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
636 struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
637 struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
638 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
639 struct phm_clock_array *valid_sclk_values;
640 struct phm_clock_array *valid_mclk_values;
641 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
642 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
643 uint32_t mclk_sclk_ratio;
644 uint32_t sclk_mclk_delta;
645 uint32_t vddc_vddci_delta;
646 uint32_t min_vddc_for_pcie_gen2;
647 struct phm_cac_leakage_table *cac_leakage_table;
648 struct phm_phase_shedding_limits_table *vddc_phase_shed_limits_table;
649
650 struct phm_vce_clock_voltage_dependency_table
651 *vce_clock_voltage_dependency_table;
652 struct phm_uvd_clock_voltage_dependency_table
653 *uvd_clock_voltage_dependency_table;
654 struct phm_acp_clock_voltage_dependency_table
655 *acp_clock_voltage_dependency_table;
656 struct phm_samu_clock_voltage_dependency_table
657 *samu_clock_voltage_dependency_table;
658
659 struct phm_ppm_table *ppm_parameter_table;
660 struct phm_cac_tdp_table *cac_dtp_table;
661 struct phm_clock_voltage_dependency_table *vdd_gfx_dependency_on_sclk;
662};
663
664struct pp_fan_info {
665 bool bNoFan;
666 uint8_t ucTachometerPulsesPerRevolution;
667 uint32_t ulMinRPM;
668 uint32_t ulMaxRPM;
669};
670
671struct pp_advance_fan_control_parameters {
672 uint16_t usTMin;
673 uint16_t usTMed;
674 uint16_t usTHigh;
675 uint16_t usPWMMin;
676 uint16_t usPWMMed;
677 uint16_t usPWMHigh;
678 uint8_t ucTHyst;
679 uint32_t ulCycleDelay;
680 uint16_t usTMax;
681 uint8_t ucFanControlMode;
682 uint16_t usFanPWMMinLimit;
683 uint16_t usFanPWMMaxLimit;
684 uint16_t usFanPWMStep;
685 uint16_t usDefaultMaxFanPWM;
686 uint16_t usFanOutputSensitivity;
687 uint16_t usDefaultFanOutputSensitivity;
688 uint16_t usMaxFanPWM;
689 uint16_t usFanRPMMinLimit;
690 uint16_t usFanRPMMaxLimit;
691 uint16_t usFanRPMStep;
692 uint16_t usDefaultMaxFanRPM;
693 uint16_t usMaxFanRPM;
694 uint16_t usFanCurrentLow;
695 uint16_t usFanCurrentHigh;
696 uint16_t usFanRPMLow;
697 uint16_t usFanRPMHigh;
698 uint32_t ulMinFanSCLKAcousticLimit;
699 uint8_t ucTargetTemperature;
700 uint8_t ucMinimumPWMLimit;
701 uint16_t usFanGainEdge;
702 uint16_t usFanGainHotspot;
703 uint16_t usFanGainLiquid;
704 uint16_t usFanGainVrVddc;
705 uint16_t usFanGainVrMvdd;
706 uint16_t usFanGainPlx;
707 uint16_t usFanGainHbm;
708 uint8_t ucEnableZeroRPM;
709 uint8_t ucFanStopTemperature;
710 uint8_t ucFanStartTemperature;
711 uint32_t ulMaxFanSCLKAcousticLimit;
712 uint32_t ulTargetGfxClk;
713 uint16_t usZeroRPMStartTemperature;
714 uint16_t usZeroRPMStopTemperature;
715 uint16_t usMGpuThrottlingRPMLimit;
716};
717
718struct pp_thermal_controller_info {
719 uint8_t ucType;
720 uint8_t ucI2cLine;
721 uint8_t ucI2cAddress;
722 uint8_t use_hw_fan_control;
723 struct pp_fan_info fanInfo;
724 struct pp_advance_fan_control_parameters advanceFanControlParameters;
725};
726
727struct phm_microcode_version_info {
728 uint32_t SMC;
729 uint32_t DMCU;
730 uint32_t MC;
731 uint32_t NB;
732};
733
734enum PP_TABLE_VERSION {
735 PP_TABLE_V0 = 0,
736 PP_TABLE_V1,
737 PP_TABLE_V2,
738 PP_TABLE_MAX
739};
740
741
742
743
744#define Workload_Policy_Max 6
745
746struct pp_hwmgr {
747 void *adev;
748 uint32_t chip_family;
749 uint32_t chip_id;
750 uint32_t smu_version;
751 bool not_vf;
752 bool pm_en;
753 bool pp_one_vf;
754 struct mutex smu_lock;
755 struct mutex msg_lock;
756
757 uint32_t pp_table_version;
758 void *device;
759 struct pp_smumgr *smumgr;
760 const void *soft_pp_table;
761 uint32_t soft_pp_table_size;
762 void *hardcode_pp_table;
763 bool need_pp_table_upload;
764
765 struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
766 uint32_t num_vce_state_tables;
767
768 enum amd_dpm_forced_level dpm_level;
769 enum amd_dpm_forced_level saved_dpm_level;
770 enum amd_dpm_forced_level request_dpm_level;
771 uint32_t usec_timeout;
772 void *pptable;
773 struct phm_platform_descriptor platform_descriptor;
774 void *backend;
775
776 void *smu_backend;
777 const struct pp_smumgr_func *smumgr_funcs;
778 bool is_kicker;
779
780 enum PP_DAL_POWERLEVEL dal_power_level;
781 struct phm_dynamic_state_info dyn_state;
782 const struct pp_hwmgr_func *hwmgr_func;
783 const struct pp_table_func *pptable_func;
784
785 struct pp_power_state *ps;
786 uint32_t num_ps;
787 struct pp_thermal_controller_info thermal_controller;
788 bool fan_ctrl_is_in_default_mode;
789 uint32_t fan_ctrl_default_mode;
790 bool fan_ctrl_enabled;
791 uint32_t tmin;
792 struct phm_microcode_version_info microcode_version_info;
793 uint32_t ps_size;
794 struct pp_power_state *current_ps;
795 struct pp_power_state *request_ps;
796 struct pp_power_state *boot_ps;
797 struct pp_power_state *uvd_ps;
798 const struct amd_pp_display_configuration *display_config;
799 uint32_t feature_mask;
800 bool avfs_supported;
801
802 bool en_umd_pstate;
803 uint32_t power_profile_mode;
804 uint32_t default_power_profile_mode;
805 uint32_t pstate_sclk;
806 uint32_t pstate_mclk;
807 bool od_enabled;
808 uint32_t power_limit;
809 uint32_t default_power_limit;
810 uint32_t workload_mask;
811 uint32_t workload_prority[Workload_Policy_Max];
812 uint32_t workload_setting[Workload_Policy_Max];
813 bool gfxoff_state_changed_by_workload;
814};
815
816int hwmgr_early_init(struct pp_hwmgr *hwmgr);
817int hwmgr_sw_init(struct pp_hwmgr *hwmgr);
818int hwmgr_sw_fini(struct pp_hwmgr *hwmgr);
819int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
820int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
821int hwmgr_suspend(struct pp_hwmgr *hwmgr);
822int hwmgr_resume(struct pp_hwmgr *hwmgr);
823
824int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
825 enum amd_pp_task task_id,
826 enum amd_pm_state_type *user_state);
827
828
829#define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
830
831int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
832int smu8_init_function_pointers(struct pp_hwmgr *hwmgr);
833int vega12_hwmgr_init(struct pp_hwmgr *hwmgr);
834int vega20_hwmgr_init(struct pp_hwmgr *hwmgr);
835
836#endif
837
