linux/drivers/gpu/drm/amd/pm/inc/smu73_discrete.h
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   1/*
   2 * Copyright 2015 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23#ifndef _SMU73_DISCRETE_H_
  24#define _SMU73_DISCRETE_H_
  25
  26#include "smu73.h"
  27
  28#pragma pack(push, 1)
  29
  30struct SMIO_Pattern
  31{
  32  uint16_t Voltage;
  33  uint8_t  Smio;
  34  uint8_t  padding;
  35};
  36
  37typedef struct SMIO_Pattern SMIO_Pattern;
  38
  39struct SMIO_Table
  40{
  41  SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS];
  42};
  43
  44typedef struct SMIO_Table SMIO_Table;
  45
  46struct SMU73_Discrete_GraphicsLevel {
  47        uint32_t    MinVoltage;
  48
  49        uint32_t    SclkFrequency;
  50
  51        uint8_t     pcieDpmLevel;
  52        uint8_t     DeepSleepDivId;
  53        uint16_t    ActivityLevel;
  54        uint32_t    CgSpllFuncCntl3;
  55        uint32_t    CgSpllFuncCntl4;
  56        uint32_t    SpllSpreadSpectrum;
  57        uint32_t    SpllSpreadSpectrum2;
  58        uint32_t    CcPwrDynRm;
  59        uint32_t    CcPwrDynRm1;
  60        uint8_t     SclkDid;
  61        uint8_t     DisplayWatermark;
  62        uint8_t     EnabledForActivity;
  63        uint8_t     EnabledForThrottle;
  64        uint8_t     UpHyst;
  65        uint8_t     DownHyst;
  66        uint8_t     VoltageDownHyst;
  67        uint8_t     PowerThrottle;
  68};
  69
  70typedef struct SMU73_Discrete_GraphicsLevel SMU73_Discrete_GraphicsLevel;
  71
  72struct SMU73_Discrete_ACPILevel {
  73    uint32_t    Flags;
  74    uint32_t MinVoltage;
  75    uint32_t    SclkFrequency;
  76    uint8_t     SclkDid;
  77    uint8_t     DisplayWatermark;
  78    uint8_t     DeepSleepDivId;
  79    uint8_t     padding;
  80    uint32_t    CgSpllFuncCntl;
  81    uint32_t    CgSpllFuncCntl2;
  82    uint32_t    CgSpllFuncCntl3;
  83    uint32_t    CgSpllFuncCntl4;
  84    uint32_t    SpllSpreadSpectrum;
  85    uint32_t    SpllSpreadSpectrum2;
  86    uint32_t    CcPwrDynRm;
  87    uint32_t    CcPwrDynRm1;
  88};
  89
  90typedef struct SMU73_Discrete_ACPILevel SMU73_Discrete_ACPILevel;
  91
  92struct SMU73_Discrete_Ulv {
  93        uint32_t    CcPwrDynRm;
  94        uint32_t    CcPwrDynRm1;
  95        uint16_t    VddcOffset;
  96        uint8_t     VddcOffsetVid;
  97        uint8_t     VddcPhase;
  98        uint32_t    Reserved;
  99};
 100
 101typedef struct SMU73_Discrete_Ulv SMU73_Discrete_Ulv;
 102
 103struct SMU73_Discrete_MemoryLevel
 104{
 105    uint32_t MinVoltage;
 106    uint32_t    MinMvdd;
 107
 108    uint32_t    MclkFrequency;
 109
 110    uint8_t     StutterEnable;
 111    uint8_t     FreqRange;
 112    uint8_t     EnabledForThrottle;
 113    uint8_t     EnabledForActivity;
 114
 115    uint8_t     UpHyst;
 116    uint8_t     DownHyst;
 117    uint8_t     VoltageDownHyst;
 118    uint8_t     padding;
 119
 120    uint16_t    ActivityLevel;
 121    uint8_t     DisplayWatermark;
 122    uint8_t     MclkDivider;
 123};
 124
 125typedef struct SMU73_Discrete_MemoryLevel SMU73_Discrete_MemoryLevel;
 126
 127struct SMU73_Discrete_LinkLevel
 128{
 129    uint8_t     PcieGenSpeed;           ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3
 130    uint8_t     PcieLaneCount;          ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 
 131    uint8_t     EnabledForActivity;
 132    uint8_t     SPC;
 133    uint32_t    DownThreshold;
 134    uint32_t    UpThreshold;
 135    uint32_t    Reserved;
 136};
 137
 138typedef struct SMU73_Discrete_LinkLevel SMU73_Discrete_LinkLevel;
 139
 140
 141// MC ARB DRAM Timing registers.
 142struct SMU73_Discrete_MCArbDramTimingTableEntry
 143{
 144    uint32_t McArbDramTiming;
 145    uint32_t McArbDramTiming2;
 146    uint8_t  McArbBurstTime;
 147    uint8_t  TRRDS;
 148    uint8_t  TRRDL;
 149    uint8_t  padding;
 150};
 151
 152typedef struct SMU73_Discrete_MCArbDramTimingTableEntry SMU73_Discrete_MCArbDramTimingTableEntry;
 153
 154struct SMU73_Discrete_MCArbDramTimingTable
 155{
 156    SMU73_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
 157};
 158
 159typedef struct SMU73_Discrete_MCArbDramTimingTable SMU73_Discrete_MCArbDramTimingTable;
 160
 161// UVD VCLK/DCLK state (level) definition.
 162struct SMU73_Discrete_UvdLevel
 163{
 164    uint32_t VclkFrequency;
 165    uint32_t DclkFrequency;
 166    uint32_t MinVoltage;
 167    uint8_t  VclkDivider;
 168    uint8_t  DclkDivider;
 169    uint8_t  padding[2];
 170};
 171
 172typedef struct SMU73_Discrete_UvdLevel SMU73_Discrete_UvdLevel;
 173
 174// Clocks for other external blocks (VCE, ACP, SAMU).
 175struct SMU73_Discrete_ExtClkLevel
 176{
 177    uint32_t Frequency;
 178    uint32_t MinVoltage;
 179    uint8_t  Divider;
 180    uint8_t  padding[3];
 181};
 182
 183typedef struct SMU73_Discrete_ExtClkLevel SMU73_Discrete_ExtClkLevel;
 184
 185struct SMU73_Discrete_StateInfo
 186{
 187    uint32_t SclkFrequency;
 188    uint32_t MclkFrequency;
 189    uint32_t VclkFrequency;
 190    uint32_t DclkFrequency;
 191    uint32_t SamclkFrequency;
 192    uint32_t AclkFrequency;
 193    uint32_t EclkFrequency;
 194    uint16_t MvddVoltage;
 195    uint16_t padding16;
 196    uint8_t  DisplayWatermark;
 197    uint8_t  McArbIndex;
 198    uint8_t  McRegIndex;
 199    uint8_t  SeqIndex;
 200    uint8_t  SclkDid;
 201    int8_t   SclkIndex;
 202    int8_t   MclkIndex;
 203    uint8_t  PCIeGen;
 204
 205};
 206
 207typedef struct SMU73_Discrete_StateInfo SMU73_Discrete_StateInfo;
 208
 209struct SMU73_Discrete_DpmTable
 210{
 211    // Multi-DPM controller settings
 212    SMU73_PIDController                  GraphicsPIDController;
 213    SMU73_PIDController                  MemoryPIDController;
 214    SMU73_PIDController                  LinkPIDController;
 215
 216    uint32_t                            SystemFlags;
 217
 218    // SMIO masks for voltage and phase controls
 219    uint32_t                            VRConfig;
 220    uint32_t                            SmioMask1;
 221    uint32_t                            SmioMask2;
 222    SMIO_Table                          SmioTable1;
 223    SMIO_Table                          SmioTable2;
 224
 225    uint32_t                            MvddLevelCount;
 226
 227
 228    uint8_t                             BapmVddcVidHiSidd        [SMU73_MAX_LEVELS_VDDC];
 229    uint8_t                             BapmVddcVidLoSidd        [SMU73_MAX_LEVELS_VDDC];
 230    uint8_t                             BapmVddcVidHiSidd2       [SMU73_MAX_LEVELS_VDDC];
 231
 232    uint8_t                             GraphicsDpmLevelCount;
 233    uint8_t                             MemoryDpmLevelCount;
 234    uint8_t                             LinkLevelCount;
 235    uint8_t                             MasterDeepSleepControl;
 236
 237    uint8_t                             UvdLevelCount;
 238    uint8_t                             VceLevelCount;
 239    uint8_t                             AcpLevelCount;
 240    uint8_t                             SamuLevelCount;
 241
 242    uint8_t                             ThermOutGpio;
 243    uint8_t                             ThermOutPolarity;
 244    uint8_t                             ThermOutMode;
 245    uint8_t                             BootPhases;
 246    uint32_t                            Reserved[4];
 247
 248    // State table entries for each DPM state
 249    SMU73_Discrete_GraphicsLevel        GraphicsLevel           [SMU73_MAX_LEVELS_GRAPHICS];
 250    SMU73_Discrete_MemoryLevel          MemoryACPILevel;
 251    SMU73_Discrete_MemoryLevel          MemoryLevel             [SMU73_MAX_LEVELS_MEMORY];
 252    SMU73_Discrete_LinkLevel            LinkLevel               [SMU73_MAX_LEVELS_LINK];
 253    SMU73_Discrete_ACPILevel            ACPILevel;
 254    SMU73_Discrete_UvdLevel             UvdLevel                [SMU73_MAX_LEVELS_UVD];
 255    SMU73_Discrete_ExtClkLevel          VceLevel                [SMU73_MAX_LEVELS_VCE];
 256    SMU73_Discrete_ExtClkLevel          AcpLevel                [SMU73_MAX_LEVELS_ACP];
 257    SMU73_Discrete_ExtClkLevel          SamuLevel               [SMU73_MAX_LEVELS_SAMU];
 258    SMU73_Discrete_Ulv                  Ulv;
 259
 260    uint32_t                            SclkStepSize;
 261    uint32_t                            Smio                    [SMU73_MAX_ENTRIES_SMIO];
 262
 263    uint8_t                             UvdBootLevel;
 264    uint8_t                             VceBootLevel;
 265    uint8_t                             AcpBootLevel;
 266    uint8_t                             SamuBootLevel;
 267
 268    uint8_t                             GraphicsBootLevel;
 269    uint8_t                             GraphicsVoltageChangeEnable;
 270    uint8_t                             GraphicsThermThrottleEnable;
 271    uint8_t                             GraphicsInterval;
 272
 273    uint8_t                             VoltageInterval;
 274    uint8_t                             ThermalInterval;
 275    uint16_t                            TemperatureLimitHigh;
 276
 277    uint16_t                            TemperatureLimitLow;
 278    uint8_t                             MemoryBootLevel;
 279    uint8_t                             MemoryVoltageChangeEnable;
 280
 281    uint16_t                            BootMVdd;
 282    uint8_t                             MemoryInterval;
 283    uint8_t                             MemoryThermThrottleEnable;
 284
 285    uint16_t                            VoltageResponseTime;
 286    uint16_t                            PhaseResponseTime;
 287
 288    uint8_t                             PCIeBootLinkLevel;
 289    uint8_t                             PCIeGenInterval;
 290    uint8_t                             DTEInterval;
 291    uint8_t                             DTEMode;
 292
 293    uint8_t                             SVI2Enable;
 294    uint8_t                             VRHotGpio;
 295    uint8_t                             AcDcGpio;
 296    uint8_t                             ThermGpio;
 297
 298    uint16_t                            PPM_PkgPwrLimit;
 299    uint16_t                            PPM_TemperatureLimit;
 300
 301    uint16_t                            DefaultTdp;
 302    uint16_t                            TargetTdp;
 303
 304    uint16_t                            FpsHighThreshold;
 305    uint16_t                            FpsLowThreshold;
 306
 307    uint16_t                            TemperatureLimitEdge;
 308    uint16_t                            TemperatureLimitHotspot;
 309    uint16_t                            TemperatureLimitLiquid1;
 310    uint16_t                            TemperatureLimitLiquid2;
 311    uint16_t                            TemperatureLimitVrVddc;
 312    uint16_t                            TemperatureLimitVrMvdd;
 313    uint16_t                            TemperatureLimitPlx;
 314
 315    uint16_t                            FanGainEdge;
 316    uint16_t                            FanGainHotspot;
 317    uint16_t                            FanGainLiquid;
 318    uint16_t                            FanGainVrVddc;
 319    uint16_t                            FanGainVrMvdd;
 320    uint16_t                            FanGainPlx;
 321    uint16_t                            FanGainHbm;
 322
 323    uint8_t                             Liquid1_I2C_address;
 324    uint8_t                             Liquid2_I2C_address;
 325    uint8_t                             Vr_I2C_address;
 326    uint8_t                             Plx_I2C_address;
 327
 328    uint8_t                             GeminiMode;
 329    uint8_t                             spare17[3];
 330    uint32_t                            GeminiApertureHigh;
 331    uint32_t                            GeminiApertureLow;
 332
 333    uint8_t                             Liquid_I2C_LineSCL;
 334    uint8_t                             Liquid_I2C_LineSDA;
 335    uint8_t                             Vr_I2C_LineSCL;
 336    uint8_t                             Vr_I2C_LineSDA;
 337    uint8_t                             Plx_I2C_LineSCL;
 338    uint8_t                             Plx_I2C_LineSDA;
 339
 340    uint8_t                             spare1253[2];
 341    uint32_t                            spare123[2];
 342
 343    uint8_t                             DTEAmbientTempBase;
 344    uint8_t                             DTETjOffset;
 345    uint8_t                             GpuTjMax;
 346    uint8_t                             GpuTjHyst;
 347
 348    uint16_t                            BootVddc;
 349    uint16_t                            BootVddci;
 350
 351    uint32_t                            BAPM_TEMP_GRADIENT;
 352
 353    uint32_t                            LowSclkInterruptThreshold;
 354    uint32_t                            VddGfxReChkWait;
 355
 356    uint8_t                             ClockStretcherAmount;
 357    uint8_t                             Sclk_CKS_masterEn0_7;
 358    uint8_t                             Sclk_CKS_masterEn8_15;
 359    uint8_t                             DPMFreezeAndForced;
 360
 361    uint8_t                             Sclk_voltageOffset[8];
 362
 363    SMU_ClockStretcherDataTable         ClockStretcherDataTable;
 364    SMU_CKS_LOOKUPTable                 CKS_LOOKUPTable;
 365};
 366
 367typedef struct SMU73_Discrete_DpmTable SMU73_Discrete_DpmTable;
 368
 369
 370// --------------------------------------------------- Fan Table -----------------------------------------------------------
 371struct SMU73_Discrete_FanTable
 372{
 373    uint16_t FdoMode;
 374    int16_t  TempMin;
 375    int16_t  TempMed;
 376    int16_t  TempMax;
 377    int16_t  Slope1;
 378    int16_t  Slope2;
 379    int16_t  FdoMin;
 380    int16_t  HystUp;
 381    int16_t  HystDown;
 382    int16_t  HystSlope;
 383    int16_t  TempRespLim;
 384    int16_t  TempCurr;
 385    int16_t  SlopeCurr;
 386    int16_t  PwmCurr;
 387    uint32_t RefreshPeriod;
 388    int16_t  FdoMax;
 389    uint8_t  TempSrc;
 390    int8_t   Padding;
 391};
 392
 393typedef struct SMU73_Discrete_FanTable SMU73_Discrete_FanTable;
 394
 395#define SMU7_DISCRETE_GPIO_SCLK_DEBUG             4
 396#define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT         (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
 397
 398
 399
 400struct SMU7_MclkDpmScoreboard
 401{
 402
 403    uint32_t PercentageBusy;
 404
 405    int32_t  PIDError;
 406    int32_t  PIDIntegral;
 407    int32_t  PIDOutput;
 408
 409    uint32_t SigmaDeltaAccum;
 410    uint32_t SigmaDeltaOutput;
 411    uint32_t SigmaDeltaLevel;
 412
 413    uint32_t UtilizationSetpoint;
 414
 415    uint8_t  TdpClampMode;
 416    uint8_t  TdcClampMode;
 417    uint8_t  ThermClampMode;
 418    uint8_t  VoltageBusy;
 419
 420    int8_t   CurrLevel;
 421    int8_t   TargLevel;
 422    uint8_t  LevelChangeInProgress;
 423    uint8_t  UpHyst;
 424
 425    uint8_t  DownHyst;
 426    uint8_t  VoltageDownHyst;
 427    uint8_t  DpmEnable;
 428    uint8_t  DpmRunning;
 429
 430    uint8_t  DpmForce;
 431    uint8_t  DpmForceLevel;
 432    uint8_t  DisplayWatermark;
 433    uint8_t  McArbIndex;
 434
 435    uint32_t MinimumPerfMclk;
 436
 437    uint8_t  AcpiReq;
 438    uint8_t  AcpiAck;
 439    uint8_t  MclkSwitchInProgress;
 440    uint8_t  MclkSwitchCritical;
 441
 442    uint8_t  IgnoreVBlank;
 443    uint8_t  TargetMclkIndex;
 444    uint8_t  TargetMvddIndex;
 445    uint8_t  MclkSwitchResult;
 446
 447    uint16_t VbiFailureCount;
 448    uint8_t  VbiWaitCounter;
 449    uint8_t  EnabledLevelsChange;
 450
 451    uint16_t LevelResidencyCounters [SMU73_MAX_LEVELS_MEMORY];
 452    uint16_t LevelSwitchCounters [SMU73_MAX_LEVELS_MEMORY];
 453
 454    void     (*TargetStateCalculator)(uint8_t);
 455    void     (*SavedTargetStateCalculator)(uint8_t);
 456
 457    uint16_t AutoDpmInterval;
 458    uint16_t AutoDpmRange;
 459
 460    uint16_t VbiTimeoutCount;
 461    uint16_t MclkSwitchingTime;
 462
 463    uint8_t  fastSwitch;
 464    uint8_t  Save_PIC_VDDGFX_EXIT;
 465    uint8_t  Save_PIC_VDDGFX_ENTER;
 466    uint8_t  padding;
 467
 468};
 469
 470typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard;
 471
 472struct SMU7_UlvScoreboard
 473{
 474    uint8_t     EnterUlv;
 475    uint8_t     ExitUlv;
 476    uint8_t     UlvActive;
 477    uint8_t     WaitingForUlv;
 478    uint8_t     UlvEnable;
 479    uint8_t     UlvRunning;
 480    uint8_t     UlvMasterEnable;
 481    uint8_t     padding;
 482    uint32_t    UlvAbortedCount;
 483    uint32_t    UlvTimeStamp;
 484};
 485
 486typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard;
 487
 488struct VddgfxSavedRegisters
 489{
 490  uint32_t GPU_DBG[3];
 491  uint32_t MEC_BaseAddress_Hi;
 492  uint32_t MEC_BaseAddress_Lo;
 493  uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;
 494  uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;
 495  uint32_t CP_INT_CNTL;
 496};
 497
 498typedef struct VddgfxSavedRegisters VddgfxSavedRegisters;
 499
 500struct SMU7_VddGfxScoreboard
 501{
 502    uint8_t     VddGfxEnable;
 503    uint8_t     VddGfxActive;
 504    uint8_t     VPUResetOccured;
 505    uint8_t     padding;
 506
 507    uint32_t    VddGfxEnteredCount;
 508    uint32_t    VddGfxAbortedCount;
 509
 510    uint32_t    VddGfxVid;
 511
 512    VddgfxSavedRegisters SavedRegisters;
 513};
 514
 515typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard;
 516
 517struct SMU7_TdcLimitScoreboard {
 518  uint8_t  Enable;
 519  uint8_t  Running;
 520  uint16_t Alpha;
 521  uint32_t FilteredIddc;
 522  uint32_t IddcLimit;
 523  uint32_t IddcHyst;
 524  SMU7_HystController_Data HystControllerData;
 525};
 526
 527typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard;
 528
 529struct SMU7_PkgPwrLimitScoreboard {
 530  uint8_t  Enable;
 531  uint8_t  Running;
 532  uint16_t Alpha;
 533  uint32_t FilteredPkgPwr;
 534  uint32_t Limit;
 535  uint32_t Hyst;
 536  uint32_t LimitFromDriver;
 537  SMU7_HystController_Data HystControllerData;
 538};
 539
 540typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard;
 541
 542struct SMU7_BapmScoreboard {
 543  uint32_t source_powers[SMU73_DTE_SOURCES];
 544  uint32_t source_powers_last[SMU73_DTE_SOURCES];
 545  int32_t entity_temperatures[SMU73_NUM_GPU_TES];
 546  int32_t initial_entity_temperatures[SMU73_NUM_GPU_TES];
 547  int32_t Limit;
 548  int32_t Hyst;
 549  int32_t therm_influence_coeff_table[SMU73_DTE_ITERATIONS * SMU73_DTE_SOURCES * SMU73_DTE_SINKS * 2];
 550  int32_t therm_node_table[SMU73_DTE_ITERATIONS * SMU73_DTE_SOURCES * SMU73_DTE_SINKS];
 551  uint16_t ConfigTDPPowerScalar;
 552  uint16_t FanSpeedPowerScalar;
 553  uint16_t OverDrivePowerScalar;
 554  uint16_t OverDriveLimitScalar;
 555  uint16_t FinalPowerScalar;
 556  uint8_t VariantID;
 557  uint8_t spare997;
 558
 559  SMU7_HystController_Data HystControllerData;
 560
 561  int32_t temperature_gradient_slope;
 562  int32_t temperature_gradient;
 563  uint32_t measured_temperature;
 564};
 565
 566
 567typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard;
 568
 569struct SMU7_AcpiScoreboard {
 570  uint32_t SavedInterruptMask[2];
 571  uint8_t LastACPIRequest;
 572  uint8_t CgBifResp;
 573  uint8_t RequestType;
 574  uint8_t Padding;
 575  SMU73_Discrete_ACPILevel D0Level;
 576};
 577
 578typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;
 579
 580struct SMU_QuadraticCoeffs {
 581  int32_t m1;
 582  uint32_t b;
 583
 584  int16_t m2;
 585  uint8_t m1_shift;
 586  uint8_t m2_shift;
 587};
 588
 589typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs;
 590
 591struct SMU73_Discrete_PmFuses {
 592  /* dw0-dw1 */
 593  uint8_t BapmVddCVidHiSidd[8];
 594
 595  /* dw2-dw3 */
 596  uint8_t BapmVddCVidLoSidd[8];
 597
 598  /* dw4-dw5 */
 599  uint8_t VddCVid[8];
 600
 601  /* dw1*/
 602  uint8_t SviLoadLineEn;
 603  uint8_t SviLoadLineVddC;
 604  uint8_t SviLoadLineTrimVddC;
 605  uint8_t SviLoadLineOffsetVddC;
 606
 607  /* dw2 */
 608  uint16_t TDC_VDDC_PkgLimit;
 609  uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
 610  uint8_t TDC_MAWt;
 611
 612  /* dw3 */
 613  uint8_t TdcWaterfallCtl;
 614  uint8_t LPMLTemperatureMin;
 615  uint8_t LPMLTemperatureMax;
 616  uint8_t Reserved;
 617
 618  /* dw4-dw7 */
 619  uint8_t LPMLTemperatureScaler[16];
 620
 621  /* dw8-dw9 */
 622  int16_t FuzzyFan_ErrorSetDelta;
 623  int16_t FuzzyFan_ErrorRateSetDelta;
 624  int16_t FuzzyFan_PwmSetDelta;
 625  uint16_t Reserved6;
 626
 627  /* dw10-dw14 */
 628  uint8_t GnbLPML[16];
 629
 630  /* dw15 */
 631  uint8_t GnbLPMLMaxVid;
 632  uint8_t GnbLPMLMinVid;
 633  uint8_t Reserved1[2];
 634
 635  /* dw16 */
 636  uint16_t BapmVddCBaseLeakageHiSidd;
 637  uint16_t BapmVddCBaseLeakageLoSidd;
 638
 639  /* AVFS */
 640  uint16_t  VFT_Temp[3];
 641  uint16_t  padding;
 642
 643  SMU_QuadraticCoeffs VFT_ATE[3];
 644
 645  SMU_QuadraticCoeffs AVFS_GB;
 646  SMU_QuadraticCoeffs ATE_ACBTC_GB;
 647
 648  SMU_QuadraticCoeffs P2V;
 649
 650  uint32_t PsmCharzFreq;
 651
 652  uint16_t InversionVoltage;
 653  uint16_t PsmCharzTemp;
 654
 655  uint32_t EnabledAvfsModules;
 656};
 657
 658typedef struct SMU73_Discrete_PmFuses SMU73_Discrete_PmFuses;
 659
 660struct SMU7_Discrete_Log_Header_Table {
 661  uint32_t    version;
 662  uint32_t    asic_id;
 663  uint16_t    flags;
 664  uint16_t    entry_size;
 665  uint32_t    total_size;
 666  uint32_t    num_of_entries;
 667  uint8_t     type;
 668  uint8_t     mode;
 669  uint8_t     filler_0[2];
 670  uint32_t    filler_1[2];
 671};
 672
 673typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table;
 674
 675struct SMU7_Discrete_Log_Cntl {
 676    uint8_t             Enabled;
 677    uint8_t             Type;
 678    uint8_t             padding[2];
 679    uint32_t            BufferSize;
 680    uint32_t            SamplesLogged;
 681    uint32_t            SampleSize;
 682    uint32_t            AddrL;
 683    uint32_t            AddrH;
 684};
 685
 686typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl;
 687
 688#define CAC_ACC_NW_NUM_OF_SIGNALS 87
 689
 690struct SMU7_Discrete_Cac_Collection_Table {
 691  uint32_t temperature;
 692  uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
 693};
 694
 695typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table;
 696
 697struct SMU7_Discrete_Cac_Verification_Table {
 698  uint32_t VddcTotalPower;
 699  uint32_t VddcLeakagePower;
 700  uint32_t VddcConstantPower;
 701  uint32_t VddcGfxDynamicPower;
 702  uint32_t VddcUvdDynamicPower;
 703  uint32_t VddcVceDynamicPower;
 704  uint32_t VddcAcpDynamicPower;
 705  uint32_t VddcPcieDynamicPower;
 706  uint32_t VddcDceDynamicPower;
 707  uint32_t VddcCurrent;
 708  uint32_t VddcVoltage;
 709  uint32_t VddciTotalPower;
 710  uint32_t VddciLeakagePower;
 711  uint32_t VddciConstantPower;
 712  uint32_t VddciDynamicPower;
 713  uint32_t Vddr1TotalPower;
 714  uint32_t Vddr1LeakagePower;
 715  uint32_t Vddr1ConstantPower;
 716  uint32_t Vddr1DynamicPower;
 717  uint32_t spare[4];
 718  uint32_t temperature;
 719};
 720
 721typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table;
 722
 723struct SMU7_Discrete_Pm_Status_Table {
 724  //Thermal entities
 725  int32_t  T_meas_max[SMU73_THERMAL_INPUT_LOOP_COUNT];
 726  int32_t  T_meas_acc[SMU73_THERMAL_INPUT_LOOP_COUNT];
 727  int32_t  T_meas_acc_cnt[SMU73_THERMAL_INPUT_LOOP_COUNT];
 728  uint32_t T_hbm_acc;
 729
 730  //Voltage domains
 731  uint32_t I_calc_max;
 732  uint32_t I_calc_acc;
 733  uint32_t P_meas_acc;
 734  uint32_t V_meas_load_acc;
 735  uint32_t I_meas_acc;
 736  uint32_t P_meas_acc_vddci;
 737  uint32_t V_meas_load_acc_vddci;
 738  uint32_t I_meas_acc_vddci;
 739
 740  //Frequency
 741  uint16_t Sclk_dpm_residency[8];
 742  uint16_t Uvd_dpm_residency[8];
 743  uint16_t Vce_dpm_residency[8];
 744
 745  //Chip
 746  uint32_t P_roc_acc;
 747  uint32_t PkgPwr_max;
 748  uint32_t PkgPwr_acc;
 749  uint32_t MclkSwitchingTime_max;
 750  uint32_t MclkSwitchingTime_acc;
 751  uint32_t FanPwm_acc;
 752  uint32_t FanRpm_acc;
 753  uint32_t Gfx_busy_acc;
 754  uint32_t Mc_busy_acc;
 755  uint32_t Fps_acc;
 756
 757  uint32_t AccCnt;
 758};
 759
 760typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table;
 761
 762//FIXME THESE NEED TO BE UPDATED
 763#define SMU7_SCLK_CAC 0x561
 764#define SMU7_MCLK_CAC 0xF9
 765#define SMU7_VCLK_CAC 0x2DE
 766#define SMU7_DCLK_CAC 0x2DE
 767#define SMU7_ECLK_CAC 0x25E
 768#define SMU7_ACLK_CAC 0x25E
 769#define SMU7_SAMCLK_CAC 0x25E
 770#define SMU7_DISPCLK_CAC 0x100
 771#define SMU7_CAC_CONSTANT 0x2EE3430
 772#define SMU7_CAC_CONSTANT_SHIFT 18
 773
 774#define SMU7_VDDCI_MCLK_CONST        1765
 775#define SMU7_VDDCI_MCLK_CONST_SHIFT  16
 776#define SMU7_VDDCI_VDDCI_CONST       50958
 777#define SMU7_VDDCI_VDDCI_CONST_SHIFT 14
 778#define SMU7_VDDCI_CONST             11781
 779#define SMU7_VDDCI_STROBE_PWR        1331
 780
 781#define SMU7_VDDR1_CONST            693
 782#define SMU7_VDDR1_CAC_WEIGHT       20
 783#define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19
 784#define SMU7_VDDR1_STROBE_PWR       512
 785
 786#define SMU7_AREA_COEFF_UVD 0xA78
 787#define SMU7_AREA_COEFF_VCE 0x190A
 788#define SMU7_AREA_COEFF_ACP 0x22D1
 789#define SMU7_AREA_COEFF_SAMU 0x534
 790
 791//ThermOutMode values
 792#define SMU7_THERM_OUT_MODE_DISABLE       0x0
 793#define SMU7_THERM_OUT_MODE_THERM_ONLY    0x1
 794#define SMU7_THERM_OUT_MODE_THERM_VRHOT   0x2
 795
 796#pragma pack(pop)
 797
 798#endif
 799
 800