1/* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23#ifndef _CI_SMUMANAGER_H_ 24#define _CI_SMUMANAGER_H_ 25 26#define SMU__NUM_SCLK_DPM_STATE 8 27#define SMU__NUM_MCLK_DPM_LEVELS 6 28#define SMU__NUM_LCLK_DPM_LEVELS 8 29#define SMU__NUM_PCIE_DPM_LEVELS 8 30 31#include "smu7_discrete.h" 32#include <pp_endian.h> 33#include "ppatomctrl.h" 34 35struct ci_pt_defaults { 36 u8 svi_load_line_en; 37 u8 svi_load_line_vddc; 38 u8 tdc_vddc_throttle_release_limit_perc; 39 u8 tdc_mawt; 40 u8 tdc_waterfall_ctl; 41 u8 dte_ambient_temp_base; 42 u32 display_cac; 43 u32 bapm_temp_gradient; 44 u16 bapmti_r[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS]; 45 u16 bapmti_rc[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS]; 46}; 47 48struct ci_mc_reg_entry { 49 uint32_t mclk_max; 50 uint32_t mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; 51}; 52 53struct ci_mc_reg_table { 54 uint8_t last; 55 uint8_t num_entries; 56 uint16_t validflag; 57 struct ci_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; 58 SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; 59}; 60 61struct ci_smumgr { 62 uint32_t soft_regs_start; 63 uint32_t dpm_table_start; 64 uint32_t mc_reg_table_start; 65 uint32_t fan_table_start; 66 uint32_t arb_table_start; 67 uint32_t ulv_setting_starts; 68 struct SMU7_Discrete_DpmTable smc_state_table; 69 struct SMU7_Discrete_PmFuses power_tune_table; 70 const struct ci_pt_defaults *power_tune_defaults; 71 SMU7_Discrete_MCRegisters mc_regs; 72 struct ci_mc_reg_table mc_reg_table; 73}; 74 75#endif 76 77