LXR linux/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus

   1/*
   2 * Copyright 2019 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23
  24#define SWSMU_CODE_LAYER_L2
  25
  26#include <linux/firmware.h>
  27#include "amdgpu.h"
  28#include "amdgpu_smu.h"
  29#include "atomfirmware.h"
  30#include "amdgpu_atomfirmware.h"
  31#include "amdgpu_atombios.h"
  32#include "smu_v11_0.h"
  33#include "smu11_driver_if_arcturus.h"
  34#include "soc15_common.h"
  35#include "atom.h"
  36#include "power_state.h"
  37#include "arcturus_ppt.h"
  38#include "smu_v11_0_pptable.h"
  39#include "arcturus_ppsmc.h"
  40#include "nbio/nbio_7_4_offset.h"
  41#include "nbio/nbio_7_4_sh_mask.h"
  42#include "thm/thm_11_0_2_offset.h"
  43#include "thm/thm_11_0_2_sh_mask.h"
  44#include "amdgpu_xgmi.h"
  45#include <linux/i2c.h>
  46#include <linux/pci.h>
  47#include "amdgpu_ras.h"
  48#include "smu_cmn.h"
  49
  50/*
  51 * DO NOT use these for err/warn/info/debug messages.
  52 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  53 * They are more MGPU friendly.
  54 */
  55#undef pr_err
  56#undef pr_warn
  57#undef pr_info
  58#undef pr_debug
  59
  60#define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  61
  62#define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
  63        [smu_feature] = {1, (arcturus_feature)}
  64
  65#define SMU_FEATURES_LOW_MASK        0x00000000FFFFFFFF
  66#define SMU_FEATURES_LOW_SHIFT       0
  67#define SMU_FEATURES_HIGH_MASK       0xFFFFFFFF00000000
  68#define SMU_FEATURES_HIGH_SHIFT      32
  69
  70#define SMC_DPM_FEATURE ( \
  71        FEATURE_DPM_PREFETCHER_MASK | \
  72        FEATURE_DPM_GFXCLK_MASK | \
  73        FEATURE_DPM_UCLK_MASK | \
  74        FEATURE_DPM_SOCCLK_MASK | \
  75        FEATURE_DPM_MP0CLK_MASK | \
  76        FEATURE_DPM_FCLK_MASK | \
  77        FEATURE_DPM_XGMI_MASK)
  78
  79/* possible frequency drift (1Mhz) */
  80#define EPSILON                         1
  81
  82#define smnPCIE_ESM_CTRL                        0x111003D0
  83
  84#define mmCG_FDO_CTRL0_ARCT                     0x8B
  85#define mmCG_FDO_CTRL0_ARCT_BASE_IDX            0
  86
  87#define mmCG_FDO_CTRL1_ARCT                     0x8C
  88#define mmCG_FDO_CTRL1_ARCT_BASE_IDX            0
  89
  90#define mmCG_FDO_CTRL2_ARCT                     0x8D
  91#define mmCG_FDO_CTRL2_ARCT_BASE_IDX            0
  92
  93#define mmCG_TACH_CTRL_ARCT                     0x8E
  94#define mmCG_TACH_CTRL_ARCT_BASE_IDX            0
  95
  96#define mmCG_TACH_STATUS_ARCT                   0x8F
  97#define mmCG_TACH_STATUS_ARCT_BASE_IDX          0
  98
  99#define mmCG_THERMAL_STATUS_ARCT                0x90
 100#define mmCG_THERMAL_STATUS_ARCT_BASE_IDX       0
 101
 102static const struct cmn2asic_msg_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
 103        MSG_MAP(TestMessage,                         PPSMC_MSG_TestMessage,                     0),
 104        MSG_MAP(GetSmuVersion,                       PPSMC_MSG_GetSmuVersion,                   1),
 105        MSG_MAP(GetDriverIfVersion,                  PPSMC_MSG_GetDriverIfVersion,              1),
 106        MSG_MAP(SetAllowedFeaturesMaskLow,           PPSMC_MSG_SetAllowedFeaturesMaskLow,       0),
 107        MSG_MAP(SetAllowedFeaturesMaskHigh,          PPSMC_MSG_SetAllowedFeaturesMaskHigh,      0),
 108        MSG_MAP(EnableAllSmuFeatures,                PPSMC_MSG_EnableAllSmuFeatures,            0),
 109        MSG_MAP(DisableAllSmuFeatures,               PPSMC_MSG_DisableAllSmuFeatures,           0),
 110        MSG_MAP(EnableSmuFeaturesLow,                PPSMC_MSG_EnableSmuFeaturesLow,            1),
 111        MSG_MAP(EnableSmuFeaturesHigh,               PPSMC_MSG_EnableSmuFeaturesHigh,           1),
 112        MSG_MAP(DisableSmuFeaturesLow,               PPSMC_MSG_DisableSmuFeaturesLow,           0),
 113        MSG_MAP(DisableSmuFeaturesHigh,              PPSMC_MSG_DisableSmuFeaturesHigh,          0),
 114        MSG_MAP(GetEnabledSmuFeaturesLow,            PPSMC_MSG_GetEnabledSmuFeaturesLow,        0),
 115        MSG_MAP(GetEnabledSmuFeaturesHigh,           PPSMC_MSG_GetEnabledSmuFeaturesHigh,       0),
 116        MSG_MAP(SetDriverDramAddrHigh,               PPSMC_MSG_SetDriverDramAddrHigh,           1),
 117        MSG_MAP(SetDriverDramAddrLow,                PPSMC_MSG_SetDriverDramAddrLow,            1),
 118        MSG_MAP(SetToolsDramAddrHigh,                PPSMC_MSG_SetToolsDramAddrHigh,            0),
 119        MSG_MAP(SetToolsDramAddrLow,                 PPSMC_MSG_SetToolsDramAddrLow,             0),
 120        MSG_MAP(TransferTableSmu2Dram,               PPSMC_MSG_TransferTableSmu2Dram,           1),
 121        MSG_MAP(TransferTableDram2Smu,               PPSMC_MSG_TransferTableDram2Smu,           0),
 122        MSG_MAP(UseDefaultPPTable,                   PPSMC_MSG_UseDefaultPPTable,               0),
 123        MSG_MAP(UseBackupPPTable,                    PPSMC_MSG_UseBackupPPTable,                0),
 124        MSG_MAP(SetSystemVirtualDramAddrHigh,        PPSMC_MSG_SetSystemVirtualDramAddrHigh,    0),
 125        MSG_MAP(SetSystemVirtualDramAddrLow,         PPSMC_MSG_SetSystemVirtualDramAddrLow,     0),
 126        MSG_MAP(EnterBaco,                           PPSMC_MSG_EnterBaco,                       0),
 127        MSG_MAP(ExitBaco,                            PPSMC_MSG_ExitBaco,                        0),
 128        MSG_MAP(ArmD3,                               PPSMC_MSG_ArmD3,                           0),
 129        MSG_MAP(SetSoftMinByFreq,                    PPSMC_MSG_SetSoftMinByFreq,                0),
 130        MSG_MAP(SetSoftMaxByFreq,                    PPSMC_MSG_SetSoftMaxByFreq,                0),
 131        MSG_MAP(SetHardMinByFreq,                    PPSMC_MSG_SetHardMinByFreq,                0),
 132        MSG_MAP(SetHardMaxByFreq,                    PPSMC_MSG_SetHardMaxByFreq,                0),
 133        MSG_MAP(GetMinDpmFreq,                       PPSMC_MSG_GetMinDpmFreq,                   0),
 134        MSG_MAP(GetMaxDpmFreq,                       PPSMC_MSG_GetMaxDpmFreq,                   0),
 135        MSG_MAP(GetDpmFreqByIndex,                   PPSMC_MSG_GetDpmFreqByIndex,               1),
 136        MSG_MAP(SetWorkloadMask,                     PPSMC_MSG_SetWorkloadMask,                 1),
 137        MSG_MAP(SetDfSwitchType,                     PPSMC_MSG_SetDfSwitchType,                 0),
 138        MSG_MAP(GetVoltageByDpm,                     PPSMC_MSG_GetVoltageByDpm,                 0),
 139        MSG_MAP(GetVoltageByDpmOverdrive,            PPSMC_MSG_GetVoltageByDpmOverdrive,        0),
 140        MSG_MAP(SetPptLimit,                         PPSMC_MSG_SetPptLimit,                     0),
 141        MSG_MAP(GetPptLimit,                         PPSMC_MSG_GetPptLimit,                     1),
 142        MSG_MAP(PowerUpVcn0,                         PPSMC_MSG_PowerUpVcn0,                     0),
 143        MSG_MAP(PowerDownVcn0,                       PPSMC_MSG_PowerDownVcn0,                   0),
 144        MSG_MAP(PowerUpVcn1,                         PPSMC_MSG_PowerUpVcn1,                     0),
 145        MSG_MAP(PowerDownVcn1,                       PPSMC_MSG_PowerDownVcn1,                   0),
 146        MSG_MAP(PrepareMp1ForUnload,                 PPSMC_MSG_PrepareMp1ForUnload,             0),
 147        MSG_MAP(PrepareMp1ForReset,                  PPSMC_MSG_PrepareMp1ForReset,              0),
 148        MSG_MAP(PrepareMp1ForShutdown,               PPSMC_MSG_PrepareMp1ForShutdown,           0),
 149        MSG_MAP(SoftReset,                           PPSMC_MSG_SoftReset,                       0),
 150        MSG_MAP(RunAfllBtc,                          PPSMC_MSG_RunAfllBtc,                      0),
 151        MSG_MAP(RunDcBtc,                            PPSMC_MSG_RunDcBtc,                        0),
 152        MSG_MAP(DramLogSetDramAddrHigh,              PPSMC_MSG_DramLogSetDramAddrHigh,          0),
 153        MSG_MAP(DramLogSetDramAddrLow,               PPSMC_MSG_DramLogSetDramAddrLow,           0),
 154        MSG_MAP(DramLogSetDramSize,                  PPSMC_MSG_DramLogSetDramSize,              0),
 155        MSG_MAP(GetDebugData,                        PPSMC_MSG_GetDebugData,                    0),
 156        MSG_MAP(WaflTest,                            PPSMC_MSG_WaflTest,                        0),
 157        MSG_MAP(SetXgmiMode,                         PPSMC_MSG_SetXgmiMode,                     0),
 158        MSG_MAP(SetMemoryChannelEnable,              PPSMC_MSG_SetMemoryChannelEnable,          0),
 159        MSG_MAP(DFCstateControl,                     PPSMC_MSG_DFCstateControl,                 0),
 160        MSG_MAP(GmiPwrDnControl,                     PPSMC_MSG_GmiPwrDnControl,                 0),
 161        MSG_MAP(ReadSerialNumTop32,                  PPSMC_MSG_ReadSerialNumTop32,              1),
 162        MSG_MAP(ReadSerialNumBottom32,               PPSMC_MSG_ReadSerialNumBottom32,           1),
 163        MSG_MAP(LightSBR,                            PPSMC_MSG_LightSBR,                        0),
 164};
 165
 166static const struct cmn2asic_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
 167        CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 168        CLK_MAP(SCLK,   PPCLK_GFXCLK),
 169        CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 170        CLK_MAP(FCLK, PPCLK_FCLK),
 171        CLK_MAP(UCLK, PPCLK_UCLK),
 172        CLK_MAP(MCLK, PPCLK_UCLK),
 173        CLK_MAP(DCLK, PPCLK_DCLK),
 174        CLK_MAP(VCLK, PPCLK_VCLK),
 175};
 176
 177static const struct cmn2asic_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
 178        FEA_MAP(DPM_PREFETCHER),
 179        FEA_MAP(DPM_GFXCLK),
 180        FEA_MAP(DPM_UCLK),
 181        FEA_MAP(DPM_SOCCLK),
 182        FEA_MAP(DPM_FCLK),
 183        FEA_MAP(DPM_MP0CLK),
 184        FEA_MAP(DPM_XGMI),
 185        FEA_MAP(DS_GFXCLK),
 186        FEA_MAP(DS_SOCCLK),
 187        FEA_MAP(DS_LCLK),
 188        FEA_MAP(DS_FCLK),
 189        FEA_MAP(DS_UCLK),
 190        FEA_MAP(GFX_ULV),
 191        ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN_BIT),
 192        FEA_MAP(RSMU_SMN_CG),
 193        FEA_MAP(WAFL_CG),
 194        FEA_MAP(PPT),
 195        FEA_MAP(TDC),
 196        FEA_MAP(APCC_PLUS),
 197        FEA_MAP(VR0HOT),
 198        FEA_MAP(VR1HOT),
 199        FEA_MAP(FW_CTF),
 200        FEA_MAP(FAN_CONTROL),
 201        FEA_MAP(THERMAL),
 202        FEA_MAP(OUT_OF_BAND_MONITOR),
 203        FEA_MAP(TEMP_DEPENDENT_VMIN),
 204};
 205
 206static const struct cmn2asic_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
 207        TAB_MAP(PPTABLE),
 208        TAB_MAP(AVFS),
 209        TAB_MAP(AVFS_PSM_DEBUG),
 210        TAB_MAP(AVFS_FUSE_OVERRIDE),
 211        TAB_MAP(PMSTATUSLOG),
 212        TAB_MAP(SMU_METRICS),
 213        TAB_MAP(DRIVER_SMU_CONFIG),
 214        TAB_MAP(OVERDRIVE),
 215        TAB_MAP(I2C_COMMANDS),
 216        TAB_MAP(ACTIVITY_MONITOR_COEFF),
 217};
 218
 219static const struct cmn2asic_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 220        PWR_MAP(AC),
 221        PWR_MAP(DC),
 222};
 223
 224static const struct cmn2asic_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 225        WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 226        WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 227        WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 228        WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 229        WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 230};
 231
 232static const uint8_t arcturus_throttler_map[] = {
 233        [THROTTLER_TEMP_EDGE_BIT]       = (SMU_THROTTLER_TEMP_EDGE_BIT),
 234        [THROTTLER_TEMP_HOTSPOT_BIT]    = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
 235        [THROTTLER_TEMP_MEM_BIT]        = (SMU_THROTTLER_TEMP_MEM_BIT),
 236        [THROTTLER_TEMP_VR_GFX_BIT]     = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
 237        [THROTTLER_TEMP_VR_MEM_BIT]     = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
 238        [THROTTLER_TEMP_VR_SOC_BIT]     = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
 239        [THROTTLER_TDC_GFX_BIT]         = (SMU_THROTTLER_TDC_GFX_BIT),
 240        [THROTTLER_TDC_SOC_BIT]         = (SMU_THROTTLER_TDC_SOC_BIT),
 241        [THROTTLER_PPT0_BIT]            = (SMU_THROTTLER_PPT0_BIT),
 242        [THROTTLER_PPT1_BIT]            = (SMU_THROTTLER_PPT1_BIT),
 243        [THROTTLER_PPT2_BIT]            = (SMU_THROTTLER_PPT2_BIT),
 244        [THROTTLER_PPT3_BIT]            = (SMU_THROTTLER_PPT3_BIT),
 245        [THROTTLER_PPM_BIT]             = (SMU_THROTTLER_PPM_BIT),
 246        [THROTTLER_FIT_BIT]             = (SMU_THROTTLER_FIT_BIT),
 247        [THROTTLER_APCC_BIT]            = (SMU_THROTTLER_APCC_BIT),
 248        [THROTTLER_VRHOT0_BIT]          = (SMU_THROTTLER_VRHOT0_BIT),
 249        [THROTTLER_VRHOT1_BIT]          = (SMU_THROTTLER_VRHOT1_BIT),
 250};
 251
 252static int arcturus_tables_init(struct smu_context *smu)
 253{
 254        struct smu_table_context *smu_table = &smu->smu_table;
 255        struct smu_table *tables = smu_table->tables;
 256
 257        SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 258                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 259
 260        SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 261                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 262
 263        SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 264                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 265
 266        SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 267                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 268
 269        SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 270                       sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 271                       AMDGPU_GEM_DOMAIN_VRAM);
 272
 273        smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 274        if (!smu_table->metrics_table)
 275                return -ENOMEM;
 276        smu_table->metrics_time = 0;
 277
 278        smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 279        smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 280        if (!smu_table->gpu_metrics_table) {
 281                kfree(smu_table->metrics_table);
 282                return -ENOMEM;
 283        }
 284
 285        return 0;
 286}
 287
 288static int arcturus_allocate_dpm_context(struct smu_context *smu)
 289{
 290        struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 291
 292        smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 293                                       GFP_KERNEL);
 294        if (!smu_dpm->dpm_context)
 295                return -ENOMEM;
 296        smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 297
 298        smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
 299                                       GFP_KERNEL);
 300        if (!smu_dpm->dpm_current_power_state)
 301                return -ENOMEM;
 302
 303        smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
 304                                       GFP_KERNEL);
 305        if (!smu_dpm->dpm_request_power_state)
 306                return -ENOMEM;
 307
 308        return 0;
 309}
 310
 311static int arcturus_init_smc_tables(struct smu_context *smu)
 312{
 313        int ret = 0;
 314
 315        ret = arcturus_tables_init(smu);
 316        if (ret)
 317                return ret;
 318
 319        ret = arcturus_allocate_dpm_context(smu);
 320        if (ret)
 321                return ret;
 322
 323        return smu_v11_0_init_smc_tables(smu);
 324}
 325
 326static int
 327arcturus_get_allowed_feature_mask(struct smu_context *smu,
 328                                  uint32_t *feature_mask, uint32_t num)
 329{
 330        if (num > 2)
 331                return -EINVAL;
 332
 333        /* pptable will handle the features to enable */
 334        memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
 335
 336        return 0;
 337}
 338
 339static int arcturus_set_default_dpm_table(struct smu_context *smu)
 340{
 341        struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 342        PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
 343        struct smu_11_0_dpm_table *dpm_table = NULL;
 344        int ret = 0;
 345
 346        /* socclk dpm table setup */
 347        dpm_table = &dpm_context->dpm_tables.soc_table;
 348        if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 349                ret = smu_v11_0_set_single_dpm_table(smu,
 350                                                     SMU_SOCCLK,
 351                                                     dpm_table);
 352                if (ret)
 353                        return ret;
 354                dpm_table->is_fine_grained =
 355                        !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
 356        } else {
 357                dpm_table->count = 1;
 358                dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 359                dpm_table->dpm_levels[0].enabled = true;
 360                dpm_table->min = dpm_table->dpm_levels[0].value;
 361                dpm_table->max = dpm_table->dpm_levels[0].value;
 362        }
 363
 364        /* gfxclk dpm table setup */
 365        dpm_table = &dpm_context->dpm_tables.gfx_table;
 366        if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 367                ret = smu_v11_0_set_single_dpm_table(smu,
 368                                                     SMU_GFXCLK,
 369                                                     dpm_table);
 370                if (ret)
 371                        return ret;
 372                dpm_table->is_fine_grained =
 373                        !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
 374        } else {
 375                dpm_table->count = 1;
 376                dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 377                dpm_table->dpm_levels[0].enabled = true;
 378                dpm_table->min = dpm_table->dpm_levels[0].value;
 379                dpm_table->max = dpm_table->dpm_levels[0].value;
 380        }
 381
 382        /* memclk dpm table setup */
 383        dpm_table = &dpm_context->dpm_tables.uclk_table;
 384        if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 385                ret = smu_v11_0_set_single_dpm_table(smu,
 386                                                     SMU_UCLK,
 387                                                     dpm_table);
 388                if (ret)
 389                        return ret;
 390                dpm_table->is_fine_grained =
 391                        !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
 392        } else {
 393                dpm_table->count = 1;
 394                dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 395                dpm_table->dpm_levels[0].enabled = true;
 396                dpm_table->min = dpm_table->dpm_levels[0].value;
 397                dpm_table->max = dpm_table->dpm_levels[0].value;
 398        }
 399
 400        /* fclk dpm table setup */
 401        dpm_table = &dpm_context->dpm_tables.fclk_table;
 402        if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 403                ret = smu_v11_0_set_single_dpm_table(smu,
 404                                                     SMU_FCLK,
 405                                                     dpm_table);
 406                if (ret)
 407                        return ret;
 408                dpm_table->is_fine_grained =
 409                        !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
 410        } else {
 411                dpm_table->count = 1;
 412                dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 413                dpm_table->dpm_levels[0].enabled = true;
 414                dpm_table->min = dpm_table->dpm_levels[0].value;
 415                dpm_table->max = dpm_table->dpm_levels[0].value;
 416        }
 417
 418        return 0;
 419}
 420
 421static void arcturus_check_bxco_support(struct smu_context *smu)
 422{
 423        struct smu_table_context *table_context = &smu->smu_table;
 424        struct smu_11_0_powerplay_table *powerplay_table =
 425                table_context->power_play_table;
 426        struct smu_baco_context *smu_baco = &smu->smu_baco;
 427        struct amdgpu_device *adev = smu->adev;
 428        uint32_t val;
 429
 430        if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 431            powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) {
 432                val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
 433                smu_baco->platform_support =
 434                        (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
 435                                                                        false;
 436        }
 437}
 438
 439static int arcturus_check_powerplay_table(struct smu_context *smu)
 440{
 441        struct smu_table_context *table_context = &smu->smu_table;
 442        struct smu_11_0_powerplay_table *powerplay_table =
 443                table_context->power_play_table;
 444
 445        arcturus_check_bxco_support(smu);
 446
 447        table_context->thermal_controller_type =
 448                powerplay_table->thermal_controller_type;
 449
 450        return 0;
 451}
 452
 453static int arcturus_store_powerplay_table(struct smu_context *smu)
 454{
 455        struct smu_table_context *table_context = &smu->smu_table;
 456        struct smu_11_0_powerplay_table *powerplay_table =
 457                table_context->power_play_table;
 458
 459        memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 460               sizeof(PPTable_t));
 461
 462        return 0;
 463}
 464
 465static int arcturus_append_powerplay_table(struct smu_context *smu)
 466{
 467        struct smu_table_context *table_context = &smu->smu_table;
 468        PPTable_t *smc_pptable = table_context->driver_pptable;
 469        struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
 470        int index, ret;
 471
 472        index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 473                                           smc_dpm_info);
 474
 475        ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 476                                      (uint8_t **)&smc_dpm_table);
 477        if (ret)
 478                return ret;
 479
 480        dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
 481                        smc_dpm_table->table_header.format_revision,
 482                        smc_dpm_table->table_header.content_revision);
 483
 484        if ((smc_dpm_table->table_header.format_revision == 4) &&
 485            (smc_dpm_table->table_header.content_revision == 6))
 486                smu_memcpy_trailing(smc_pptable, MaxVoltageStepGfx, BoardReserved,
 487                                    smc_dpm_table, maxvoltagestepgfx);
 488        return 0;
 489}
 490
 491static int arcturus_setup_pptable(struct smu_context *smu)
 492{
 493        int ret = 0;
 494
 495        ret = smu_v11_0_setup_pptable(smu);
 496        if (ret)
 497                return ret;
 498
 499        ret = arcturus_store_powerplay_table(smu);
 500        if (ret)
 501                return ret;
 502
 503        ret = arcturus_append_powerplay_table(smu);
 504        if (ret)
 505                return ret;
 506
 507        ret = arcturus_check_powerplay_table(smu);
 508        if (ret)
 509                return ret;
 510
 511        return ret;
 512}
 513
 514static int arcturus_run_btc(struct smu_context *smu)
 515{
 516        int ret = 0;
 517
 518        ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunAfllBtc, NULL);
 519        if (ret) {
 520                dev_err(smu->adev->dev, "RunAfllBtc failed!\n");
 521                return ret;
 522        }
 523
 524        return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
 525}
 526
 527static int arcturus_populate_umd_state_clk(struct smu_context *smu)
 528{
 529        struct smu_11_0_dpm_context *dpm_context =
 530                                smu->smu_dpm.dpm_context;
 531        struct smu_11_0_dpm_table *gfx_table =
 532                                &dpm_context->dpm_tables.gfx_table;
 533        struct smu_11_0_dpm_table *mem_table =
 534                                &dpm_context->dpm_tables.uclk_table;
 535        struct smu_11_0_dpm_table *soc_table =
 536                                &dpm_context->dpm_tables.soc_table;
 537        struct smu_umd_pstate_table *pstate_table =
 538                                &smu->pstate_table;
 539
 540        pstate_table->gfxclk_pstate.min = gfx_table->min;
 541        pstate_table->gfxclk_pstate.peak = gfx_table->max;
 542
 543        pstate_table->uclk_pstate.min = mem_table->min;
 544        pstate_table->uclk_pstate.peak = mem_table->max;
 545
 546        pstate_table->socclk_pstate.min = soc_table->min;
 547        pstate_table->socclk_pstate.peak = soc_table->max;
 548
 549        if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
 550            mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
 551            soc_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
 552                pstate_table->gfxclk_pstate.standard =
 553                        gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
 554                pstate_table->uclk_pstate.standard =
 555                        mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
 556                pstate_table->socclk_pstate.standard =
 557                        soc_table->dpm_levels[ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL].value;
 558        } else {
 559                pstate_table->gfxclk_pstate.standard =
 560                        pstate_table->gfxclk_pstate.min;
 561                pstate_table->uclk_pstate.standard =
 562                        pstate_table->uclk_pstate.min;
 563                pstate_table->socclk_pstate.standard =
 564                        pstate_table->socclk_pstate.min;
 565        }
 566
 567        return 0;
 568}
 569
 570static int arcturus_get_clk_table(struct smu_context *smu,
 571                        struct pp_clock_levels_with_latency *clocks,
 572                        struct smu_11_0_dpm_table *dpm_table)
 573{
 574        int i, count;
 575
 576        count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
 577        clocks->num_levels = count;
 578
 579        for (i = 0; i < count; i++) {
 580                clocks->data[i].clocks_in_khz =
 581                        dpm_table->dpm_levels[i].value * 1000;
 582                clocks->data[i].latency_in_us = 0;
 583        }
 584
 585        return 0;
 586}
 587
 588static int arcturus_freqs_in_same_level(int32_t frequency1,
 589                                        int32_t frequency2)
 590{
 591        return (abs(frequency1 - frequency2) <= EPSILON);
 592}
 593
 594static int arcturus_get_smu_metrics_data(struct smu_context *smu,
 595                                         MetricsMember_t member,
 596                                         uint32_t *value)
 597{
 598        struct smu_table_context *smu_table= &smu->smu_table;
 599        SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 600        int ret = 0;
 601
 602        mutex_lock(&smu->metrics_lock);
 603
 604        ret = smu_cmn_get_metrics_table_locked(smu,
 605                                               NULL,
 606                                               false);
 607        if (ret) {
 608                mutex_unlock(&smu->metrics_lock);
 609                return ret;
 610        }
 611
 612        switch (member) {
 613        case METRICS_CURR_GFXCLK:
 614                *value = metrics->CurrClock[PPCLK_GFXCLK];
 615                break;
 616        case METRICS_CURR_SOCCLK:
 617                *value = metrics->CurrClock[PPCLK_SOCCLK];
 618                break;
 619        case METRICS_CURR_UCLK:
 620                *value = metrics->CurrClock[PPCLK_UCLK];
 621                break;
 622        case METRICS_CURR_VCLK:
 623                *value = metrics->CurrClock[PPCLK_VCLK];
 624                break;
 625        case METRICS_CURR_DCLK:
 626                *value = metrics->CurrClock[PPCLK_DCLK];
 627                break;
 628        case METRICS_CURR_FCLK:
 629                *value = metrics->CurrClock[PPCLK_FCLK];
 630                break;
 631        case METRICS_AVERAGE_GFXCLK:
 632                *value = metrics->AverageGfxclkFrequency;
 633                break;
 634        case METRICS_AVERAGE_SOCCLK:
 635                *value = metrics->AverageSocclkFrequency;
 636                break;
 637        case METRICS_AVERAGE_UCLK:
 638                *value = metrics->AverageUclkFrequency;
 639                break;
 640        case METRICS_AVERAGE_VCLK:
 641                *value = metrics->AverageVclkFrequency;
 642                break;
 643        case METRICS_AVERAGE_DCLK:
 644                *value = metrics->AverageDclkFrequency;
 645                break;
 646        case METRICS_AVERAGE_GFXACTIVITY:
 647                *value = metrics->AverageGfxActivity;
 648                break;
 649        case METRICS_AVERAGE_MEMACTIVITY:
 650                *value = metrics->AverageUclkActivity;
 651                break;
 652        case METRICS_AVERAGE_VCNACTIVITY:
 653                *value = metrics->VcnActivityPercentage;
 654                break;
 655        case METRICS_AVERAGE_SOCKETPOWER:
 656                *value = metrics->AverageSocketPower << 8;
 657                break;
 658        case METRICS_TEMPERATURE_EDGE:
 659                *value = metrics->TemperatureEdge *
 660                        SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 661                break;
 662        case METRICS_TEMPERATURE_HOTSPOT:
 663                *value = metrics->TemperatureHotspot *
 664                        SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 665                break;
 666        case METRICS_TEMPERATURE_MEM:
 667                *value = metrics->TemperatureHBM *
 668                        SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 669                break;
 670        case METRICS_TEMPERATURE_VRGFX:
 671                *value = metrics->TemperatureVrGfx *
 672                        SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 673                break;
 674        case METRICS_TEMPERATURE_VRSOC:
 675                *value = metrics->TemperatureVrSoc *
 676                        SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 677                break;
 678        case METRICS_TEMPERATURE_VRMEM:
 679                *value = metrics->TemperatureVrMem *
 680                        SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 681                break;
 682        case METRICS_THROTTLER_STATUS:
 683                *value = metrics->ThrottlerStatus;
 684                break;
 685        case METRICS_CURR_FANSPEED:
 686                *value = metrics->CurrFanSpeed;
 687                break;
 688        default:
 689                *value = UINT_MAX;
 690                break;
 691        }
 692
 693        mutex_unlock(&smu->metrics_lock);
 694
 695        return ret;
 696}
 697
 698static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
 699                                       enum smu_clk_type clk_type,
 700                                       uint32_t *value)
 701{
 702        MetricsMember_t member_type;
 703        int clk_id = 0;
 704
 705        if (!value)
 706                return -EINVAL;
 707
 708        clk_id = smu_cmn_to_asic_specific_index(smu,
 709                                                CMN2ASIC_MAPPING_CLK,
 710                                                clk_type);
 711        if (clk_id < 0)
 712                return -EINVAL;
 713
 714        switch (clk_id) {
 715        case PPCLK_GFXCLK:
 716                /*
 717                 * CurrClock[clk_id] can provide accurate
 718                 *   output only when the dpm feature is enabled.
 719                 * We can use Average_* for dpm disabled case.
 720                 *   But this is available for gfxclk/uclk/socclk/vclk/dclk.
 721                 */
 722                if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
 723                        member_type = METRICS_CURR_GFXCLK;
 724                else
 725                        member_type = METRICS_AVERAGE_GFXCLK;
 726                break;
 727        case PPCLK_UCLK:
 728                if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
 729                        member_type = METRICS_CURR_UCLK;
 730                else
 731                        member_type = METRICS_AVERAGE_UCLK;
 732                break;
 733        case PPCLK_SOCCLK:
 734                if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
 735                        member_type = METRICS_CURR_SOCCLK;
 736                else
 737                        member_type = METRICS_AVERAGE_SOCCLK;
 738                break;
 739        case PPCLK_VCLK:
 740                if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT))
 741                        member_type = METRICS_CURR_VCLK;
 742                else
 743                        member_type = METRICS_AVERAGE_VCLK;
 744                break;
 745        case PPCLK_DCLK:
 746                if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT))
 747                        member_type = METRICS_CURR_DCLK;
 748                else
 749                        member_type = METRICS_AVERAGE_DCLK;
 750                break;
 751        case PPCLK_FCLK:
 752                member_type = METRICS_CURR_FCLK;
 753                break;
 754        default:
 755                return -EINVAL;
 756        }
 757
 758        return arcturus_get_smu_metrics_data(smu,
 759                                             member_type,
 760                                             value);
 761}
 762
 763static int arcturus_print_clk_levels(struct smu_context *smu,
 764                        enum smu_clk_type type, char *buf)
 765{
 766        int i, now, size = 0;
 767        int ret = 0;
 768        struct pp_clock_levels_with_latency clocks;
 769        struct smu_11_0_dpm_table *single_dpm_table;
 770        struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 771        struct smu_11_0_dpm_context *dpm_context = NULL;
 772        uint32_t gen_speed, lane_width;
 773
 774        smu_cmn_get_sysfs_buf(&buf, &size);
 775
 776        if (amdgpu_ras_intr_triggered()) {
 777                size += sysfs_emit_at(buf, size, "unavailable\n");
 778                return size;
 779        }
 780
 781        dpm_context = smu_dpm->dpm_context;
 782
 783        switch (type) {
 784        case SMU_SCLK:
 785                ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now);
 786                if (ret) {
 787                        dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!");
 788                        return ret;
 789                }
 790
 791                single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
 792                ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 793                if (ret) {
 794                        dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!");
 795                        return ret;
 796                }
 797
 798                /*
 799                 * For DPM disabled case, there will be only one clock level.
 800                 * And it's safe to assume that is always the current clock.
 801                 */
 802                for (i = 0; i < clocks.num_levels; i++)
 803                        size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
 804                                        clocks.data[i].clocks_in_khz / 1000,
 805                                        (clocks.num_levels == 1) ? "*" :
 806                                        (arcturus_freqs_in_same_level(
 807                                        clocks.data[i].clocks_in_khz / 1000,
 808                                        now) ? "*" : ""));
 809                break;
 810
 811        case SMU_MCLK:
 812                ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, &now);
 813                if (ret) {
 814                        dev_err(smu->adev->dev, "Attempt to get current mclk Failed!");
 815                        return ret;
 816                }
 817
 818                single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
 819                ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 820                if (ret) {
 821                        dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!");
 822                        return ret;
 823                }
 824
 825                for (i = 0; i < clocks.num_levels; i++)
 826                        size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 827                                i, clocks.data[i].clocks_in_khz / 1000,
 828                                (clocks.num_levels == 1) ? "*" :
 829                                (arcturus_freqs_in_same_level(
 830                                clocks.data[i].clocks_in_khz / 1000,
 831                                now) ? "*" : ""));
 832                break;
 833
 834        case SMU_SOCCLK:
 835                ret = arcturus_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now);
 836                if (ret) {
 837                        dev_err(smu->adev->dev, "Attempt to get current socclk Failed!");
 838                        return ret;
 839                }
 840
 841                single_dpm_table = &(dpm_context->dpm_tables.soc_table);
 842                ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 843                if (ret) {
 844                        dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!");
 845                        return ret;
 846                }
 847
 848                for (i = 0; i < clocks.num_levels; i++)
 849                        size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 850                                i, clocks.data[i].clocks_in_khz / 1000,
 851                                (clocks.num_levels == 1) ? "*" :
 852                                (arcturus_freqs_in_same_level(
 853                                clocks.data[i].clocks_in_khz / 1000,
 854                                now) ? "*" : ""));
 855                break;
 856
 857        case SMU_FCLK:
 858                ret = arcturus_get_current_clk_freq_by_table(smu, SMU_FCLK, &now);
 859                if (ret) {
 860                        dev_err(smu->adev->dev, "Attempt to get current fclk Failed!");
 861                        return ret;
 862                }
 863
 864                single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
 865                ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 866                if (ret) {
 867                        dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!");
 868                        return ret;
 869                }
 870
 871                for (i = 0; i < single_dpm_table->count; i++)
 872                        size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 873                                i, single_dpm_table->dpm_levels[i].value,
 874                                (clocks.num_levels == 1) ? "*" :
 875                                (arcturus_freqs_in_same_level(
 876                                clocks.data[i].clocks_in_khz / 1000,
 877                                now) ? "*" : ""));
 878                break;
 879
 880        case SMU_VCLK:
 881                ret = arcturus_get_current_clk_freq_by_table(smu, SMU_VCLK, &now);
 882                if (ret) {
 883                        dev_err(smu->adev->dev, "Attempt to get current vclk Failed!");
 884                        return ret;
 885                }
 886
 887                single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
 888                ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 889                if (ret) {
 890                        dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!");
 891                        return ret;
 892                }
 893
 894                for (i = 0; i < single_dpm_table->count; i++)
 895                        size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 896                                i, single_dpm_table->dpm_levels[i].value,
 897                                (clocks.num_levels == 1) ? "*" :
 898                                (arcturus_freqs_in_same_level(
 899                                clocks.data[i].clocks_in_khz / 1000,
 900                                now) ? "*" : ""));
 901                break;
 902
 903        case SMU_DCLK:
 904                ret = arcturus_get_current_clk_freq_by_table(smu, SMU_DCLK, &now);
 905                if (ret) {
 906                        dev_err(smu->adev->dev, "Attempt to get current dclk Failed!");
 907                        return ret;
 908                }
 909
 910                single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
 911                ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 912                if (ret) {
 913                        dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!");
 914                        return ret;
 915                }
 916
 917                for (i = 0; i < single_dpm_table->count; i++)
 918                        size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 919                                i, single_dpm_table->dpm_levels[i].value,
 920                                (clocks.num_levels == 1) ? "*" :
 921                                (arcturus_freqs_in_same_level(
 922                                clocks.data[i].clocks_in_khz / 1000,
 923                                now) ? "*" : ""));
 924                break;
 925
 926        case SMU_PCIE:
 927                gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
 928                lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
 929                size += sysfs_emit_at(buf, size, "0: %s %s %dMhz *\n",
 930                                (gen_speed == 0) ? "2.5GT/s," :
 931                                (gen_speed == 1) ? "5.0GT/s," :
 932                                (gen_speed == 2) ? "8.0GT/s," :
 933                                (gen_speed == 3) ? "16.0GT/s," : "",
 934                                (lane_width == 1) ? "x1" :
 935                                (lane_width == 2) ? "x2" :
 936                                (lane_width == 3) ? "x4" :
 937                                (lane_width == 4) ? "x8" :
 938                                (lane_width == 5) ? "x12" :
 939                                (lane_width == 6) ? "x16" : "",
 940                                smu->smu_table.boot_values.lclk / 100);
 941                break;
 942
 943        default:
 944                break;
 945        }
 946
 947        return size;
 948}
 949
 950static int arcturus_upload_dpm_level(struct smu_context *smu,
 951                                     bool max,
 952                                     uint32_t feature_mask,
 953                                     uint32_t level)
 954{
 955        struct smu_11_0_dpm_context *dpm_context =
 956                        smu->smu_dpm.dpm_context;
 957        uint32_t freq;
 958        int ret = 0;
 959
 960        if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
 961            (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
 962                freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
 963                ret = smu_cmn_send_smc_msg_with_param(smu,
 964                        (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 965                        (PPCLK_GFXCLK << 16) | (freq & 0xffff),
 966                        NULL);
 967                if (ret) {
 968                        dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
 969                                                max ? "max" : "min");
 970                        return ret;
 971                }
 972        }
 973
 974        if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 975            (feature_mask & FEATURE_DPM_UCLK_MASK)) {
 976                freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
 977                ret = smu_cmn_send_smc_msg_with_param(smu,
 978                        (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 979                        (PPCLK_UCLK << 16) | (freq & 0xffff),
 980                        NULL);
 981                if (ret) {
 982                        dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
 983                                                max ? "max" : "min");
 984                        return ret;
 985                }
 986        }
 987
 988        if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
 989            (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
 990                freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
 991                ret = smu_cmn_send_smc_msg_with_param(smu,
 992                        (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 993                        (PPCLK_SOCCLK << 16) | (freq & 0xffff),
 994                        NULL);
 995                if (ret) {
 996                        dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
 997                                                max ? "max" : "min");
 998                        return ret;
 999                }
1000        }

1001
1002        return ret;
1003}
1004
1005static int arcturus_force_clk_levels(struct smu_context *smu,
1006                        enum smu_clk_type type, uint32_t mask)
1007{
1008        struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1009        struct smu_11_0_dpm_table *single_dpm_table = NULL;
1010        uint32_t soft_min_level, soft_max_level;
1011        uint32_t smu_version;
1012        int ret = 0;
1013
1014        ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1015        if (ret) {
1016                dev_err(smu->adev->dev, "Failed to get smu version!\n");
1017                return ret;
1018        }
1019
1020        if ((smu_version >= 0x361200) &&
1021            (smu_version <= 0x361a00)) {
1022                dev_err(smu->adev->dev, "Forcing clock level is not supported with "
1023                       "54.18 - 54.26(included) SMU firmwares\n");
1024                return -EOPNOTSUPP;
1025        }
1026
1027        soft_min_level = mask ? (ffs(mask) - 1) : 0;
1028        soft_max_level = mask ? (fls(mask) - 1) : 0;
1029
1030        switch (type) {
1031        case SMU_SCLK:
1032                single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1033                if (soft_max_level >= single_dpm_table->count) {
1034                        dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
1035                                        soft_max_level, single_dpm_table->count - 1);
1036                        ret = -EINVAL;
1037                        break;
1038                }
1039
1040                ret = arcturus_upload_dpm_level(smu,
1041                                                false,
1042                                                FEATURE_DPM_GFXCLK_MASK,
1043                                                soft_min_level);
1044                if (ret) {
1045                        dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
1046                        break;
1047                }
1048
1049                ret = arcturus_upload_dpm_level(smu,
1050                                                true,
1051                                                FEATURE_DPM_GFXCLK_MASK,
1052                                                soft_max_level);
1053                if (ret)
1054                        dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
1055
1056                break;
1057
1058        case SMU_MCLK:
1059        case SMU_SOCCLK:
1060        case SMU_FCLK:
1061                /*
1062                 * Should not arrive here since Arcturus does not
1063                 * support mclk/socclk/fclk softmin/softmax settings
1064                 */
1065                ret = -EINVAL;
1066                break;
1067
1068        default:
1069                break;
1070        }
1071
1072        return ret;
1073}
1074
1075static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
1076                                                struct smu_temperature_range *range)
1077{
1078        struct smu_table_context *table_context = &smu->smu_table;
1079        struct smu_11_0_powerplay_table *powerplay_table =
1080                                table_context->power_play_table;
1081        PPTable_t *pptable = smu->smu_table.driver_pptable;
1082
1083        if (!range)
1084                return -EINVAL;
1085
1086        memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1087
1088        range->max = pptable->TedgeLimit *
1089                SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1090        range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
1091                SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1092        range->hotspot_crit_max = pptable->ThotspotLimit *
1093                SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1094        range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
1095                SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1096        range->mem_crit_max = pptable->TmemLimit *
1097                SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1098        range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
1099                SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1100        range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1101
1102        return 0;
1103}
1104
1105static int arcturus_read_sensor(struct smu_context *smu,
1106                                enum amd_pp_sensors sensor,
1107                                void *data, uint32_t *size)
1108{
1109        struct smu_table_context *table_context = &smu->smu_table;
1110        PPTable_t *pptable = table_context->driver_pptable;
1111        int ret = 0;
1112
1113        if (amdgpu_ras_intr_triggered())
1114                return 0;
1115
1116        if (!data || !size)
1117                return -EINVAL;
1118
1119        mutex_lock(&smu->sensor_lock);
1120        switch (sensor) {
1121        case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1122                *(uint32_t *)data = pptable->FanMaximumRpm;
1123                *size = 4;
1124                break;
1125        case AMDGPU_PP_SENSOR_MEM_LOAD:
1126                ret = arcturus_get_smu_metrics_data(smu,
1127                                                    METRICS_AVERAGE_MEMACTIVITY,
1128                                                    (uint32_t *)data);
1129                *size = 4;
1130                break;
1131        case AMDGPU_PP_SENSOR_GPU_LOAD:
1132                ret = arcturus_get_smu_metrics_data(smu,
1133                                                    METRICS_AVERAGE_GFXACTIVITY,
1134                                                    (uint32_t *)data);
1135                *size = 4;
1136                break;
1137        case AMDGPU_PP_SENSOR_GPU_POWER:
1138                ret = arcturus_get_smu_metrics_data(smu,
1139                                                    METRICS_AVERAGE_SOCKETPOWER,
1140                                                    (uint32_t *)data);
1141                *size = 4;
1142                break;
1143        case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1144                ret = arcturus_get_smu_metrics_data(smu,
1145                                                    METRICS_TEMPERATURE_HOTSPOT,
1146                                                    (uint32_t *)data);
1147                *size = 4;
1148                break;
1149        case AMDGPU_PP_SENSOR_EDGE_TEMP:
1150                ret = arcturus_get_smu_metrics_data(smu,
1151                                                    METRICS_TEMPERATURE_EDGE,
1152                                                    (uint32_t *)data);
1153                *size = 4;
1154                break;
1155        case AMDGPU_PP_SENSOR_MEM_TEMP:
1156                ret = arcturus_get_smu_metrics_data(smu,
1157                                                    METRICS_TEMPERATURE_MEM,
1158                                                    (uint32_t *)data);
1159                *size = 4;
1160                break;
1161        case AMDGPU_PP_SENSOR_GFX_MCLK:
1162                ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1163                /* the output clock frequency in 10K unit */
1164                *(uint32_t *)data *= 100;
1165                *size = 4;
1166                break;
1167        case AMDGPU_PP_SENSOR_GFX_SCLK:
1168                ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1169                *(uint32_t *)data *= 100;
1170                *size = 4;
1171                break;
1172        case AMDGPU_PP_SENSOR_VDDGFX:
1173                ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1174                *size = 4;
1175                break;
1176        default:
1177                ret = -EOPNOTSUPP;
1178                break;
1179        }
1180        mutex_unlock(&smu->sensor_lock);
1181
1182        return ret;
1183}
1184
1185static int arcturus_set_fan_static_mode(struct smu_context *smu,
1186                                        uint32_t mode)
1187{
1188        struct amdgpu_device *adev = smu->adev;
1189
1190        WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT,
1191                     REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT),
1192                                   CG_FDO_CTRL2, TMIN, 0));
1193        WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT,
1194                     REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT),
1195                                   CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1196
1197        return 0;
1198}
1199
1200static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
1201                                      uint32_t *speed)
1202{
1203        struct amdgpu_device *adev = smu->adev;
1204        uint32_t crystal_clock_freq = 2500;
1205        uint32_t tach_status;
1206        uint64_t tmp64;
1207        int ret = 0;
1208
1209        if (!speed)
1210                return -EINVAL;
1211
1212        switch (smu_v11_0_get_fan_control_mode(smu)) {
1213        case AMD_FAN_CTRL_AUTO:
1214                ret = arcturus_get_smu_metrics_data(smu,
1215                                                    METRICS_CURR_FANSPEED,
1216                                                    speed);
1217                break;
1218        default:
1219                /*
1220                 * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
1221                 * detected via register retrieving. To workaround this, we will
1222                 * report the fan speed as 0 RPM if user just requested such.
1223                 */
1224                if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_RPM)
1225                     && !smu->user_dpm_profile.fan_speed_rpm) {
1226                        *speed = 0;
1227                        return 0;
1228                }
1229
1230                tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000;
1231                tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS_ARCT);
1232                if (tach_status) {
1233                        do_div(tmp64, tach_status);
1234                        *speed = (uint32_t)tmp64;
1235                } else {
1236                        *speed = 0;
1237                }
1238
1239                break;
1240        }
1241
1242        return ret;
1243}
1244
1245static int arcturus_set_fan_speed_pwm(struct smu_context *smu,
1246                                      uint32_t speed)
1247{
1248        struct amdgpu_device *adev = smu->adev;
1249        uint32_t duty100, duty;
1250        uint64_t tmp64;
1251
1252        speed = MIN(speed, 255);
1253
1254        duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT),
1255                                CG_FDO_CTRL1, FMAX_DUTY100);
1256        if (!duty100)
1257                return -EINVAL;
1258
1259        tmp64 = (uint64_t)speed * duty100;
1260        do_div(tmp64, 255);
1261        duty = (uint32_t)tmp64;
1262
1263        WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT,
1264                     REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT),
1265                                   CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1266
1267        return arcturus_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1268}
1269
1270static int arcturus_set_fan_speed_rpm(struct smu_context *smu,
1271                                      uint32_t speed)
1272{
1273        struct amdgpu_device *adev = smu->adev;
1274        /*
1275         * crystal_clock_freq used for fan speed rpm calculation is
1276         * always 25Mhz. So, hardcode it as 2500(in 10K unit).
1277         */
1278        uint32_t crystal_clock_freq = 2500;
1279        uint32_t tach_period;
1280
1281        tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1282        WREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT,
1283                     REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT),
1284                                   CG_TACH_CTRL, TARGET_PERIOD,
1285                                   tach_period));
1286
1287        return arcturus_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1288}
1289
1290static int arcturus_get_fan_speed_pwm(struct smu_context *smu,
1291                                      uint32_t *speed)
1292{
1293        struct amdgpu_device *adev = smu->adev;
1294        uint32_t duty100, duty;
1295        uint64_t tmp64;
1296
1297        /*
1298         * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
1299         * detected via register retrieving. To workaround this, we will
1300         * report the fan speed as 0 PWM if user just requested such.
1301         */
1302        if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_PWM)
1303             && !smu->user_dpm_profile.fan_speed_pwm) {
1304                *speed = 0;
1305                return 0;
1306        }
1307
1308        duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT),
1309                                CG_FDO_CTRL1, FMAX_DUTY100);
1310        duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS_ARCT),
1311                                CG_THERMAL_STATUS, FDO_PWM_DUTY);
1312
1313        if (duty100) {
1314                tmp64 = (uint64_t)duty * 255;
1315                do_div(tmp64, duty100);
1316                *speed = MIN((uint32_t)tmp64, 255);
1317        } else {
1318                *speed = 0;
1319        }
1320
1321        return 0;
1322}
1323
1324static int arcturus_get_fan_parameters(struct smu_context *smu)
1325{
1326        PPTable_t *pptable = smu->smu_table.driver_pptable;
1327
1328        smu->fan_max_rpm = pptable->FanMaximumRpm;
1329
1330        return 0;
1331}
1332
1333static int arcturus_get_power_limit(struct smu_context *smu,
1334                                    uint32_t *current_power_limit,
1335                                    uint32_t *default_power_limit,
1336                                    uint32_t *max_power_limit)
1337{
1338        struct smu_11_0_powerplay_table *powerplay_table =
1339                (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
1340        PPTable_t *pptable = smu->smu_table.driver_pptable;
1341        uint32_t power_limit, od_percent;
1342
1343        if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1344                /* the last hope to figure out the ppt limit */
1345                if (!pptable) {
1346                        dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1347                        return -EINVAL;
1348                }
1349                power_limit =
1350                        pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1351        }
1352
1353        if (current_power_limit)
1354                *current_power_limit = power_limit;
1355        if (default_power_limit)
1356                *default_power_limit = power_limit;
1357
1358        if (max_power_limit) {
1359                if (smu->od_enabled) {
1360                        od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
1361
1362                        dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1363
1364                        power_limit *= (100 + od_percent);
1365                        power_limit /= 100;
1366                }
1367
1368                *max_power_limit = power_limit;
1369        }
1370
1371        return 0;
1372}
1373
1374static int arcturus_get_power_profile_mode(struct smu_context *smu,
1375                                           char *buf)
1376{
1377        DpmActivityMonitorCoeffInt_t activity_monitor;
1378        static const char *profile_name[] = {
1379                                        "BOOTUP_DEFAULT",
1380                                        "3D_FULL_SCREEN",
1381                                        "POWER_SAVING",
1382                                        "VIDEO",
1383                                        "VR",
1384                                        "COMPUTE",
1385                                        "CUSTOM"};
1386        static const char *title[] = {
1387                        "PROFILE_INDEX(NAME)",
1388                        "CLOCK_TYPE(NAME)",
1389                        "FPS",
1390                        "UseRlcBusy",
1391                        "MinActiveFreqType",
1392                        "MinActiveFreq",
1393                        "BoosterFreqType",
1394                        "BoosterFreq",
1395                        "PD_Data_limit_c",
1396                        "PD_Data_error_coeff",
1397                        "PD_Data_error_rate_coeff"};
1398        uint32_t i, size = 0;
1399        int16_t workload_type = 0;
1400        int result = 0;
1401        uint32_t smu_version;
1402
1403        if (!buf)
1404                return -EINVAL;
1405
1406        result = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1407        if (result)
1408                return result;
1409
1410        if (smu_version >= 0x360d00)
1411                size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1412                        title[0], title[1], title[2], title[3], title[4], title[5],
1413                        title[6], title[7], title[8], title[9], title[10]);
1414        else
1415                size += sysfs_emit_at(buf, size, "%16s\n",
1416                        title[0]);
1417
1418        for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1419                /*
1420                 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1421                 * Not all profile modes are supported on arcturus.
1422                 */
1423                workload_type = smu_cmn_to_asic_specific_index(smu,
1424                                                               CMN2ASIC_MAPPING_WORKLOAD,
1425                                                               i);
1426                if (workload_type < 0)
1427                        continue;
1428
1429                if (smu_version >= 0x360d00) {
1430                        result = smu_cmn_update_table(smu,
1431                                                  SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1432                                                  workload_type,
1433                                                  (void *)(&activity_monitor),
1434                                                  false);
1435                        if (result) {
1436                                dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1437                                return result;
1438                        }
1439                }
1440
1441                size += sysfs_emit_at(buf, size, "%2d %14s%s\n",
1442                        i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1443
1444                if (smu_version >= 0x360d00) {
1445                        size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1446                                " ",
1447                                0,
1448                                "GFXCLK",
1449                                activity_monitor.Gfx_FPS,
1450                                activity_monitor.Gfx_UseRlcBusy,
1451                                activity_monitor.Gfx_MinActiveFreqType,
1452                                activity_monitor.Gfx_MinActiveFreq,
1453                                activity_monitor.Gfx_BoosterFreqType,
1454                                activity_monitor.Gfx_BoosterFreq,
1455                                activity_monitor.Gfx_PD_Data_limit_c,
1456                                activity_monitor.Gfx_PD_Data_error_coeff,
1457                                activity_monitor.Gfx_PD_Data_error_rate_coeff);
1458
1459                        size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1460                                " ",
1461                                1,
1462                                "UCLK",
1463                                activity_monitor.Mem_FPS,
1464                                activity_monitor.Mem_UseRlcBusy,
1465                                activity_monitor.Mem_MinActiveFreqType,
1466                                activity_monitor.Mem_MinActiveFreq,
1467                                activity_monitor.Mem_BoosterFreqType,
1468                                activity_monitor.Mem_BoosterFreq,
1469                                activity_monitor.Mem_PD_Data_limit_c,
1470                                activity_monitor.Mem_PD_Data_error_coeff,
1471                                activity_monitor.Mem_PD_Data_error_rate_coeff);
1472                }
1473        }
1474
1475        return size;
1476}
1477
1478static int arcturus_set_power_profile_mode(struct smu_context *smu,
1479                                           long *input,
1480                                           uint32_t size)
1481{
1482        DpmActivityMonitorCoeffInt_t activity_monitor;
1483        int workload_type = 0;
1484        uint32_t profile_mode = input[size];
1485        int ret = 0;
1486        uint32_t smu_version;
1487
1488        if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1489                dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
1490                return -EINVAL;
1491        }
1492
1493        ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1494        if (ret)
1495                return ret;
1496
1497        if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) &&
1498             (smu_version >=0x360d00)) {
1499                ret = smu_cmn_update_table(smu,
1500                                       SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1501                                       WORKLOAD_PPLIB_CUSTOM_BIT,
1502                                       (void *)(&activity_monitor),
1503                                       false);
1504                if (ret) {
1505                        dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1506                        return ret;
1507                }
1508
1509                switch (input[0]) {
1510                case 0: /* Gfxclk */
1511                        activity_monitor.Gfx_FPS = input[1];
1512                        activity_monitor.Gfx_UseRlcBusy = input[2];
1513                        activity_monitor.Gfx_MinActiveFreqType = input[3];
1514                        activity_monitor.Gfx_MinActiveFreq = input[4];
1515                        activity_monitor.Gfx_BoosterFreqType = input[5];
1516                        activity_monitor.Gfx_BoosterFreq = input[6];
1517                        activity_monitor.Gfx_PD_Data_limit_c = input[7];
1518                        activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1519                        activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1520                        break;
1521                case 1: /* Uclk */
1522                        activity_monitor.Mem_FPS = input[1];
1523                        activity_monitor.Mem_UseRlcBusy = input[2];
1524                        activity_monitor.Mem_MinActiveFreqType = input[3];
1525                        activity_monitor.Mem_MinActiveFreq = input[4];
1526                        activity_monitor.Mem_BoosterFreqType = input[5];
1527                        activity_monitor.Mem_BoosterFreq = input[6];
1528                        activity_monitor.Mem_PD_Data_limit_c = input[7];
1529                        activity_monitor.Mem_PD_Data_error_coeff = input[8];
1530                        activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1531                        break;
1532                }
1533
1534                ret = smu_cmn_update_table(smu,
1535                                       SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1536                                       WORKLOAD_PPLIB_CUSTOM_BIT,
1537                                       (void *)(&activity_monitor),
1538                                       true);
1539                if (ret) {
1540                        dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1541                        return ret;
1542                }
1543        }
1544
1545        /*
1546         * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1547         * Not all profile modes are supported on arcturus.
1548         */
1549        workload_type = smu_cmn_to_asic_specific_index(smu,
1550                                                       CMN2ASIC_MAPPING_WORKLOAD,
1551                                                       profile_mode);
1552        if (workload_type < 0) {
1553                dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on arcturus\n", profile_mode);
1554                return -EINVAL;
1555        }
1556
1557        ret = smu_cmn_send_smc_msg_with_param(smu,
1558                                          SMU_MSG_SetWorkloadMask,
1559                                          1 << workload_type,
1560                                          NULL);
1561        if (ret) {
1562                dev_err(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
1563                return ret;
1564        }
1565
1566        smu->power_profile_mode = profile_mode;
1567
1568        return 0;
1569}
1570
1571static int arcturus_set_performance_level(struct smu_context *smu,
1572                                          enum amd_dpm_forced_level level)
1573{
1574        uint32_t smu_version;
1575        int ret;
1576
1577        ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1578        if (ret) {
1579                dev_err(smu->adev->dev, "Failed to get smu version!\n");
1580                return ret;
1581        }
1582
1583        switch (level) {
1584        case AMD_DPM_FORCED_LEVEL_HIGH:
1585        case AMD_DPM_FORCED_LEVEL_LOW:
1586        case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1587        case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1588        case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1589        case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1590                if ((smu_version >= 0x361200) &&
1591                    (smu_version <= 0x361a00)) {
1592                        dev_err(smu->adev->dev, "Forcing clock level is not supported with "
1593                               "54.18 - 54.26(included) SMU firmwares\n");
1594                        return -EOPNOTSUPP;
1595                }
1596                break;
1597        default:
1598                break;
1599        }
1600
1601        return smu_v11_0_set_performance_level(smu, level);
1602}
1603
1604static void arcturus_dump_pptable(struct smu_context *smu)
1605{
1606        struct smu_table_context *table_context = &smu->smu_table;
1607        PPTable_t *pptable = table_context->driver_pptable;
1608        int i;
1609
1610        dev_info(smu->adev->dev, "Dumped PPTable:\n");
1611
1612        dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
1613
1614        dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1615        dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1616
1617        for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1618                dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
1619                dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
1620        }
1621
1622        dev_info(smu->adev->dev, "TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
1623        dev_info(smu->adev->dev, "TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
1624        dev_info(smu->adev->dev, "TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
1625        dev_info(smu->adev->dev, "TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
1626
1627        dev_info(smu->adev->dev, "TedgeLimit = %d\n", pptable->TedgeLimit);
1628        dev_info(smu->adev->dev, "ThotspotLimit = %d\n", pptable->ThotspotLimit);
1629        dev_info(smu->adev->dev, "TmemLimit = %d\n", pptable->TmemLimit);
1630        dev_info(smu->adev->dev, "Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
1631        dev_info(smu->adev->dev, "Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
1632        dev_info(smu->adev->dev, "Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
1633        dev_info(smu->adev->dev, "FitLimit = %d\n", pptable->FitLimit);
1634
1635        dev_info(smu->adev->dev, "PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
1636        dev_info(smu->adev->dev, "PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
1637
1638        dev_info(smu->adev->dev, "ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
1639
1640        dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
1641        dev_info(smu->adev->dev, "UlvPadding = 0x%08x\n", pptable->UlvPadding);
1642
1643        dev_info(smu->adev->dev, "UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
1644        dev_info(smu->adev->dev, "Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
1645        dev_info(smu->adev->dev, "Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
1646        dev_info(smu->adev->dev, "Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
1647
1648        dev_info(smu->adev->dev, "MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
1649        dev_info(smu->adev->dev, "MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
1650        dev_info(smu->adev->dev, "MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
1651        dev_info(smu->adev->dev, "MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
1652
1653        dev_info(smu->adev->dev, "LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
1654        dev_info(smu->adev->dev, "LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
1655
1656        dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
1657                        "  .VoltageMode          = 0x%02x\n"
1658                        "  .SnapToDiscrete       = 0x%02x\n"
1659                        "  .NumDiscreteLevels    = 0x%02x\n"
1660                        "  .padding              = 0x%02x\n"
1661                        "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1662                        "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1663                        "  .SsFmin               = 0x%04x\n"
1664                        "  .Padding_16           = 0x%04x\n",
1665                        pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1666                        pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1667                        pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1668                        pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
1669                        pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1670                        pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1671                        pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1672                        pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1673                        pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1674                        pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1675                        pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1676
1677        dev_info(smu->adev->dev, "[PPCLK_VCLK]\n"
1678                        "  .VoltageMode          = 0x%02x\n"
1679                        "  .SnapToDiscrete       = 0x%02x\n"
1680                        "  .NumDiscreteLevels    = 0x%02x\n"
1681                        "  .padding              = 0x%02x\n"
1682                        "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1683                        "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1684                        "  .SsFmin               = 0x%04x\n"
1685                        "  .Padding_16           = 0x%04x\n",
1686                        pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
1687                        pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
1688                        pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
1689                        pptable->DpmDescriptor[PPCLK_VCLK].padding,
1690                        pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
1691                        pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
1692                        pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
1693                        pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
1694                        pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,
1695                        pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,
1696                        pptable->DpmDescriptor[PPCLK_VCLK].Padding16);
1697
1698        dev_info(smu->adev->dev, "[PPCLK_DCLK]\n"
1699                        "  .VoltageMode          = 0x%02x\n"
1700                        "  .SnapToDiscrete       = 0x%02x\n"
1701                        "  .NumDiscreteLevels    = 0x%02x\n"
1702                        "  .padding              = 0x%02x\n"
1703                        "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1704                        "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1705                        "  .SsFmin               = 0x%04x\n"
1706                        "  .Padding_16           = 0x%04x\n",
1707                        pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
1708                        pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
1709                        pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
1710                        pptable->DpmDescriptor[PPCLK_DCLK].padding,
1711                        pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
1712                        pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
1713                        pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
1714                        pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
1715                        pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,
1716                        pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,
1717                        pptable->DpmDescriptor[PPCLK_DCLK].Padding16);
1718
1719        dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
1720                        "  .VoltageMode          = 0x%02x\n"
1721                        "  .SnapToDiscrete       = 0x%02x\n"
1722                        "  .NumDiscreteLevels    = 0x%02x\n"
1723                        "  .padding              = 0x%02x\n"
1724                        "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1725                        "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1726                        "  .SsFmin               = 0x%04x\n"
1727                        "  .Padding_16           = 0x%04x\n",
1728                        pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1729                        pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1730                        pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1731                        pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
1732                        pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1733                        pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1734                        pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1735                        pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1736                        pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1737                        pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1738                        pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1739
1740        dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
1741                        "  .VoltageMode          = 0x%02x\n"
1742                        "  .SnapToDiscrete       = 0x%02x\n"
1743                        "  .NumDiscreteLevels    = 0x%02x\n"
1744                        "  .padding              = 0x%02x\n"
1745                        "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1746                        "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1747                        "  .SsFmin               = 0x%04x\n"
1748                        "  .Padding_16           = 0x%04x\n",
1749                        pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1750                        pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1751                        pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1752                        pptable->DpmDescriptor[PPCLK_UCLK].padding,
1753                        pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1754                        pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1755                        pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1756                        pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1757                        pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1758                        pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1759                        pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1760
1761        dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
1762                        "  .VoltageMode          = 0x%02x\n"
1763                        "  .SnapToDiscrete       = 0x%02x\n"
1764                        "  .NumDiscreteLevels    = 0x%02x\n"
1765                        "  .padding              = 0x%02x\n"
1766                        "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1767                        "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1768                        "  .SsFmin               = 0x%04x\n"
1769                        "  .Padding_16           = 0x%04x\n",
1770                        pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1771                        pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1772                        pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1773                        pptable->DpmDescriptor[PPCLK_FCLK].padding,
1774                        pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1775                        pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1776                        pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1777                        pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1778                        pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1779                        pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1780                        pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1781
1782
1783        dev_info(smu->adev->dev, "FreqTableGfx\n");
1784        for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1785                dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
1786
1787        dev_info(smu->adev->dev, "FreqTableVclk\n");
1788        for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1789                dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
1790
1791        dev_info(smu->adev->dev, "FreqTableDclk\n");
1792        for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1793                dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
1794
1795        dev_info(smu->adev->dev, "FreqTableSocclk\n");
1796        for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1797                dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
1798
1799        dev_info(smu->adev->dev, "FreqTableUclk\n");
1800        for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1801                dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
1802
1803        dev_info(smu->adev->dev, "FreqTableFclk\n");
1804        for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1805                dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
1806
1807        dev_info(smu->adev->dev, "Mp0clkFreq\n");
1808        for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1809                dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
1810
1811        dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
1812        for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1813                dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
1814
1815        dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1816        dev_info(smu->adev->dev, "GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
1817        dev_info(smu->adev->dev, "Padding567[0] = 0x%x\n", pptable->Padding567[0]);
1818        dev_info(smu->adev->dev, "Padding567[1] = 0x%x\n", pptable->Padding567[1]);
1819        dev_info(smu->adev->dev, "Padding567[2] = 0x%x\n", pptable->Padding567[2]);
1820        dev_info(smu->adev->dev, "Padding567[3] = 0x%x\n", pptable->Padding567[3]);
1821        dev_info(smu->adev->dev, "GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
1822        dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1823        dev_info(smu->adev->dev, "Padding456 = 0x%x\n", pptable->Padding456);
1824
1825        dev_info(smu->adev->dev, "EnableTdpm = %d\n", pptable->EnableTdpm);
1826        dev_info(smu->adev->dev, "TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
1827        dev_info(smu->adev->dev, "TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
1828        dev_info(smu->adev->dev, "GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
1829
1830        dev_info(smu->adev->dev, "FanStopTemp = %d\n", pptable->FanStopTemp);
1831        dev_info(smu->adev->dev, "FanStartTemp = %d\n", pptable->FanStartTemp);
1832
1833        dev_info(smu->adev->dev, "FanGainEdge = %d\n", pptable->FanGainEdge);
1834        dev_info(smu->adev->dev, "FanGainHotspot = %d\n", pptable->FanGainHotspot);
1835        dev_info(smu->adev->dev, "FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
1836        dev_info(smu->adev->dev, "FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
1837        dev_info(smu->adev->dev, "FanGainVrMem = %d\n", pptable->FanGainVrMem);
1838        dev_info(smu->adev->dev, "FanGainHbm = %d\n", pptable->FanGainHbm);
1839
1840        dev_info(smu->adev->dev, "FanPwmMin = %d\n", pptable->FanPwmMin);
1841        dev_info(smu->adev->dev, "FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
1842        dev_info(smu->adev->dev, "FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
1843        dev_info(smu->adev->dev, "FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
1844        dev_info(smu->adev->dev, "FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
1845        dev_info(smu->adev->dev, "FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
1846        dev_info(smu->adev->dev, "FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
1847        dev_info(smu->adev->dev, "FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
1848        dev_info(smu->adev->dev, "FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
1849
1850        dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
1851        dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
1852        dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
1853        dev_info(smu->adev->dev, "FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
1854
1855        dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1856        dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1857        dev_info(smu->adev->dev, "Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
1858        dev_info(smu->adev->dev, "Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
1859
1860        dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1861                        pptable->dBtcGbGfxPll.a,
1862                        pptable->dBtcGbGfxPll.b,
1863                        pptable->dBtcGbGfxPll.c);
1864        dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1865                        pptable->dBtcGbGfxAfll.a,
1866                        pptable->dBtcGbGfxAfll.b,
1867                        pptable->dBtcGbGfxAfll.c);
1868        dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1869                        pptable->dBtcGbSoc.a,
1870                        pptable->dBtcGbSoc.b,
1871                        pptable->dBtcGbSoc.c);
1872
1873        dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1874                        pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1875                        pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1876        dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1877                        pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1878                        pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1879
1880        dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1881                        pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1882                        pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1883                        pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1884        dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1885                        pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1886                        pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1887                        pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1888
1889        dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1890        dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1891
1892        dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1893        dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1894        dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1895        dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1896
1897        dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1898        dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1899        dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1900        dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1901
1902        dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1903        dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1904
1905        dev_info(smu->adev->dev, "XgmiDpmPstates\n");
1906        for (i = 0; i < NUM_XGMI_LEVELS; i++)
1907                dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
1908        dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1909        dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1910
1911        dev_info(smu->adev->dev, "VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
1912        dev_info(smu->adev->dev, "VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
1913        dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
1914        dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
1915        dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
1916        dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
1917        dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
1918        dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
1919
1920        dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1921        dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1922                        pptable->ReservedEquation0.a,
1923                        pptable->ReservedEquation0.b,
1924                        pptable->ReservedEquation0.c);
1925        dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1926                        pptable->ReservedEquation1.a,
1927                        pptable->ReservedEquation1.b,
1928                        pptable->ReservedEquation1.c);
1929        dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1930                        pptable->ReservedEquation2.a,
1931                        pptable->ReservedEquation2.b,
1932                        pptable->ReservedEquation2.c);
1933        dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1934                        pptable->ReservedEquation3.a,
1935                        pptable->ReservedEquation3.b,
1936                        pptable->ReservedEquation3.c);
1937
1938        dev_info(smu->adev->dev, "MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
1939        dev_info(smu->adev->dev, "PaddingUlv = %d\n", pptable->PaddingUlv);
1940
1941        dev_info(smu->adev->dev, "TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
1942        dev_info(smu->adev->dev, "TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
1943        dev_info(smu->adev->dev, "TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
1944
1945        dev_info(smu->adev->dev, "PccThresholdLow = %d\n", pptable->PccThresholdLow);
1946        dev_info(smu->adev->dev, "PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
1947
1948        dev_info(smu->adev->dev, "Board Parameters:\n");
1949        dev_info(smu->adev->dev, "MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
1950        dev_info(smu->adev->dev, "MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
1951
1952        dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1953        dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1954        dev_info(smu->adev->dev, "VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
1955        dev_info(smu->adev->dev, "BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
1956
1957        dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1958        dev_info(smu->adev->dev, "ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
1959
1960        dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1961        dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
1962        dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1963
1964        dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1965        dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
1966        dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1967
1968        dev_info(smu->adev->dev, "MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
1969        dev_info(smu->adev->dev, "MemOffset = 0x%x\n", pptable->MemOffset);
1970        dev_info(smu->adev->dev, "Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
1971
1972        dev_info(smu->adev->dev, "BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
1973        dev_info(smu->adev->dev, "BoardOffset = 0x%x\n", pptable->BoardOffset);
1974        dev_info(smu->adev->dev, "Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
1975
1976        dev_info(smu->adev->dev, "VR0HotGpio = %d\n", pptable->VR0HotGpio);
1977        dev_info(smu->adev->dev, "VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
1978        dev_info(smu->adev->dev, "VR1HotGpio = %d\n", pptable->VR1HotGpio);
1979        dev_info(smu->adev->dev, "VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
1980
1981        dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
1982        dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
1983        dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
1984
1985        dev_info(smu->adev->dev, "UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
1986        dev_info(smu->adev->dev, "UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
1987        dev_info(smu->adev->dev, "UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
1988
1989        dev_info(smu->adev->dev, "FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
1990        dev_info(smu->adev->dev, "FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
1991        dev_info(smu->adev->dev, "FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
1992
1993        dev_info(smu->adev->dev, "FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
1994        dev_info(smu->adev->dev, "FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
1995        dev_info(smu->adev->dev, "FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
1996
1997        for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
1998                dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
1999                dev_info(smu->adev->dev, "                   .Enabled = %d\n",
2000                                pptable->I2cControllers[i].Enabled);

2001                dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
2002                                pptable->I2cControllers[i].SlaveAddress);
2003                dev_info(smu->adev->dev, "                   .ControllerPort = %d\n",
2004                                pptable->I2cControllers[i].ControllerPort);
2005                dev_info(smu->adev->dev, "                   .ControllerName = %d\n",
2006                                pptable->I2cControllers[i].ControllerName);
2007                dev_info(smu->adev->dev, "                   .ThermalThrottler = %d\n",
2008                                pptable->I2cControllers[i].ThermalThrotter);
2009                dev_info(smu->adev->dev, "                   .I2cProtocol = %d\n",
2010                                pptable->I2cControllers[i].I2cProtocol);
2011                dev_info(smu->adev->dev, "                   .Speed = %d\n",
2012                                pptable->I2cControllers[i].Speed);
2013        }
2014
2015        dev_info(smu->adev->dev, "MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
2016        dev_info(smu->adev->dev, "DramBitWidth = %d\n", pptable->DramBitWidth);
2017
2018        dev_info(smu->adev->dev, "TotalBoardPower = %d\n", pptable->TotalBoardPower);
2019
2020        dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
2021        for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2022                dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
2023        dev_info(smu->adev->dev, "XgmiLinkWidth\n");
2024        for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2025                dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
2026        dev_info(smu->adev->dev, "XgmiFclkFreq\n");
2027        for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2028                dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
2029        dev_info(smu->adev->dev, "XgmiSocVoltage\n");
2030        for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2031                dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
2032
2033}
2034
2035static bool arcturus_is_dpm_running(struct smu_context *smu)
2036{
2037        int ret = 0;
2038        uint32_t feature_mask[2];
2039        uint64_t feature_enabled;
2040
2041        ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
2042        if (ret)
2043                return false;
2044
2045        feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
2046
2047        return !!(feature_enabled & SMC_DPM_FEATURE);
2048}
2049
2050static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
2051{
2052        int ret = 0;
2053
2054        if (enable) {
2055                if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT)) {
2056                        ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_DPM_BIT, 1);
2057                        if (ret) {
2058                                dev_err(smu->adev->dev, "[EnableVCNDPM] failed!\n");
2059                                return ret;
2060                        }
2061                }
2062        } else {
2063                if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT)) {
2064                        ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_DPM_BIT, 0);
2065                        if (ret) {
2066                                dev_err(smu->adev->dev, "[DisableVCNDPM] failed!\n");
2067                                return ret;
2068                        }
2069                }
2070        }
2071
2072        return ret;
2073}
2074
2075static int arcturus_i2c_xfer(struct i2c_adapter *i2c_adap,
2076                             struct i2c_msg *msg, int num_msgs)
2077{
2078        struct amdgpu_device *adev = to_amdgpu_device(i2c_adap);
2079        struct smu_table_context *smu_table = &adev->smu.smu_table;
2080        struct smu_table *table = &smu_table->driver_table;
2081        SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
2082        int i, j, r, c;
2083        u16 dir;
2084
2085        req = kzalloc(sizeof(*req), GFP_KERNEL);
2086        if (!req)
2087                return -ENOMEM;
2088
2089        req->I2CcontrollerPort = 0;
2090        req->I2CSpeed = I2C_SPEED_FAST_400K;
2091        req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
2092        dir = msg[0].flags & I2C_M_RD;
2093
2094        for (c = i = 0; i < num_msgs; i++) {
2095                for (j = 0; j < msg[i].len; j++, c++) {
2096                        SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
2097
2098                        if (!(msg[i].flags & I2C_M_RD)) {
2099                                /* write */
2100                                cmd->Cmd = I2C_CMD_WRITE;
2101                                cmd->RegisterAddr = msg[i].buf[j];
2102                        }
2103
2104                        if ((dir ^ msg[i].flags) & I2C_M_RD) {
2105                                /* The direction changes.
2106                                 */
2107                                dir = msg[i].flags & I2C_M_RD;
2108                                cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
2109                        }
2110
2111                        req->NumCmds++;
2112
2113                        /*
2114                         * Insert STOP if we are at the last byte of either last
2115                         * message for the transaction or the client explicitly
2116                         * requires a STOP at this particular message.
2117                         */
2118                        if ((j == msg[i].len - 1) &&
2119                            ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
2120                                cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
2121                                cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
2122                        }
2123                }
2124        }
2125        mutex_lock(&adev->smu.mutex);
2126        r = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
2127        mutex_unlock(&adev->smu.mutex);
2128        if (r)
2129                goto fail;
2130
2131        for (c = i = 0; i < num_msgs; i++) {
2132                if (!(msg[i].flags & I2C_M_RD)) {
2133                        c += msg[i].len;
2134                        continue;
2135                }
2136                for (j = 0; j < msg[i].len; j++, c++) {
2137                        SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
2138
2139                        msg[i].buf[j] = cmd->Data;
2140                }
2141        }
2142        r = num_msgs;
2143fail:
2144        kfree(req);
2145        return r;
2146}
2147
2148static u32 arcturus_i2c_func(struct i2c_adapter *adap)
2149{
2150        return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2151}
2152
2153
2154static const struct i2c_algorithm arcturus_i2c_algo = {
2155        .master_xfer = arcturus_i2c_xfer,
2156        .functionality = arcturus_i2c_func,
2157};
2158
2159
2160static const struct i2c_adapter_quirks arcturus_i2c_control_quirks = {
2161        .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
2162        .max_read_len  = MAX_SW_I2C_COMMANDS,
2163        .max_write_len = MAX_SW_I2C_COMMANDS,
2164        .max_comb_1st_msg_len = 2,
2165        .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
2166};
2167
2168static int arcturus_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
2169{
2170        struct amdgpu_device *adev = to_amdgpu_device(control);
2171        int res;
2172
2173        control->owner = THIS_MODULE;
2174        control->class = I2C_CLASS_HWMON;
2175        control->dev.parent = &adev->pdev->dev;
2176        control->algo = &arcturus_i2c_algo;
2177        control->quirks = &arcturus_i2c_control_quirks;
2178        snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
2179
2180        res = i2c_add_adapter(control);
2181        if (res)
2182                DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2183
2184        return res;
2185}
2186
2187static void arcturus_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
2188{
2189        i2c_del_adapter(control);
2190}
2191
2192static void arcturus_get_unique_id(struct smu_context *smu)
2193{
2194        struct amdgpu_device *adev = smu->adev;
2195        uint32_t top32 = 0, bottom32 = 0, smu_version;
2196        uint64_t id;
2197
2198        if (smu_cmn_get_smc_version(smu, NULL, &smu_version)) {
2199                dev_warn(adev->dev, "Failed to get smu version, cannot get unique_id or serial_number\n");
2200                return;
2201        }
2202
2203        /* PPSMC_MSG_ReadSerial* is supported by 54.23.0 and onwards */
2204        if (smu_version < 0x361700) {
2205                dev_warn(adev->dev, "ReadSerial is only supported by PMFW 54.23.0 and onwards\n");
2206                return;
2207        }
2208
2209        /* Get the SN to turn into a Unique ID */
2210        smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumTop32, &top32);
2211        smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumBottom32, &bottom32);
2212
2213        id = ((uint64_t)bottom32 << 32) | top32;
2214        adev->unique_id = id;
2215        /* For Arcturus-and-later, unique_id == serial_number, so convert it to a
2216         * 16-digit HEX string for convenience and backwards-compatibility
2217         */
2218        sprintf(adev->serial, "%llx", id);
2219}
2220
2221static int arcturus_set_df_cstate(struct smu_context *smu,
2222                                  enum pp_df_cstate state)
2223{
2224        uint32_t smu_version;
2225        int ret;
2226
2227        ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2228        if (ret) {
2229                dev_err(smu->adev->dev, "Failed to get smu version!\n");
2230                return ret;
2231        }
2232
2233        /* PPSMC_MSG_DFCstateControl is supported by 54.15.0 and onwards */
2234        if (smu_version < 0x360F00) {
2235                dev_err(smu->adev->dev, "DFCstateControl is only supported by PMFW 54.15.0 and onwards\n");
2236                return -EINVAL;
2237        }
2238
2239        return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
2240}
2241
2242static int arcturus_allow_xgmi_power_down(struct smu_context *smu, bool en)
2243{
2244        uint32_t smu_version;
2245        int ret;
2246
2247        ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2248        if (ret) {
2249                dev_err(smu->adev->dev, "Failed to get smu version!\n");
2250                return ret;
2251        }
2252
2253        /* PPSMC_MSG_GmiPwrDnControl is supported by 54.23.0 and onwards */
2254        if (smu_version < 0x00361700) {
2255                dev_err(smu->adev->dev, "XGMI power down control is only supported by PMFW 54.23.0 and onwards\n");
2256                return -EINVAL;
2257        }
2258
2259        if (en)
2260                return smu_cmn_send_smc_msg_with_param(smu,
2261                                                   SMU_MSG_GmiPwrDnControl,
2262                                                   1,
2263                                                   NULL);
2264
2265        return smu_cmn_send_smc_msg_with_param(smu,
2266                                           SMU_MSG_GmiPwrDnControl,
2267                                           0,
2268                                           NULL);
2269}
2270
2271static const struct throttling_logging_label {
2272        uint32_t feature_mask;
2273        const char *label;
2274} logging_label[] = {
2275        {(1U << THROTTLER_TEMP_HOTSPOT_BIT), "GPU"},
2276        {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
2277        {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
2278        {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
2279        {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
2280        {(1U << THROTTLER_VRHOT0_BIT), "VR0 HOT"},
2281        {(1U << THROTTLER_VRHOT1_BIT), "VR1 HOT"},
2282};
2283static void arcturus_log_thermal_throttling_event(struct smu_context *smu)
2284{
2285        int ret;
2286        int throttler_idx, throtting_events = 0, buf_idx = 0;
2287        struct amdgpu_device *adev = smu->adev;
2288        uint32_t throttler_status;
2289        char log_buf[256];
2290
2291        ret = arcturus_get_smu_metrics_data(smu,
2292                                            METRICS_THROTTLER_STATUS,
2293                                            &throttler_status);
2294        if (ret)
2295                return;
2296
2297        memset(log_buf, 0, sizeof(log_buf));
2298        for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
2299             throttler_idx++) {
2300                if (throttler_status & logging_label[throttler_idx].feature_mask) {
2301                        throtting_events++;
2302                        buf_idx += snprintf(log_buf + buf_idx,
2303                                            sizeof(log_buf) - buf_idx,
2304                                            "%s%s",
2305                                            throtting_events > 1 ? " and " : "",
2306                                            logging_label[throttler_idx].label);
2307                        if (buf_idx >= sizeof(log_buf)) {
2308                                dev_err(adev->dev, "buffer overflow!\n");
2309                                log_buf[sizeof(log_buf) - 1] = '\0';
2310                                break;
2311                        }
2312                }
2313        }
2314
2315        dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
2316                        log_buf);
2317        kgd2kfd_smi_event_throttle(smu->adev->kfd.dev,
2318                smu_cmn_get_indep_throttler_status(throttler_status,
2319                                                   arcturus_throttler_map));
2320}
2321
2322static uint16_t arcturus_get_current_pcie_link_speed(struct smu_context *smu)
2323{
2324        struct amdgpu_device *adev = smu->adev;
2325        uint32_t esm_ctrl;
2326
2327        /* TODO: confirm this on real target */
2328        esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
2329        if ((esm_ctrl >> 15) & 0x1FFFF)
2330                return (uint16_t)(((esm_ctrl >> 8) & 0x3F) + 128);
2331
2332        return smu_v11_0_get_current_pcie_link_speed(smu);
2333}
2334
2335static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu,
2336                                        void **table)
2337{
2338        struct smu_table_context *smu_table = &smu->smu_table;
2339        struct gpu_metrics_v1_3 *gpu_metrics =
2340                (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2341        SmuMetrics_t metrics;
2342        int ret = 0;
2343
2344        ret = smu_cmn_get_metrics_table(smu,
2345                                        &metrics,
2346                                        true);
2347        if (ret)
2348                return ret;
2349
2350        smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2351
2352        gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2353        gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2354        gpu_metrics->temperature_mem = metrics.TemperatureHBM;
2355        gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2356        gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2357        gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
2358
2359        gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2360        gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2361        gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
2362
2363        gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2364        gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
2365
2366        gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2367        gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2368        gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2369        gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
2370        gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
2371
2372        gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2373        gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2374        gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2375        gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2376        gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2377
2378        gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2379        gpu_metrics->indep_throttle_status =
2380                        smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
2381                                                           arcturus_throttler_map);
2382
2383        gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2384
2385        gpu_metrics->pcie_link_width =
2386                        smu_v11_0_get_current_pcie_link_width(smu);
2387        gpu_metrics->pcie_link_speed =
2388                        arcturus_get_current_pcie_link_speed(smu);
2389
2390        gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2391
2392        *table = (void *)gpu_metrics;
2393
2394        return sizeof(struct gpu_metrics_v1_3);
2395}
2396
2397static const struct pptable_funcs arcturus_ppt_funcs = {
2398        /* init dpm */
2399        .get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
2400        /* btc */
2401        .run_btc = arcturus_run_btc,
2402        /* dpm/clk tables */
2403        .set_default_dpm_table = arcturus_set_default_dpm_table,
2404        .populate_umd_state_clk = arcturus_populate_umd_state_clk,
2405        .get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
2406        .print_clk_levels = arcturus_print_clk_levels,
2407        .force_clk_levels = arcturus_force_clk_levels,
2408        .read_sensor = arcturus_read_sensor,
2409        .get_fan_speed_pwm = arcturus_get_fan_speed_pwm,
2410        .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
2411        .get_power_profile_mode = arcturus_get_power_profile_mode,
2412        .set_power_profile_mode = arcturus_set_power_profile_mode,
2413        .set_performance_level = arcturus_set_performance_level,
2414        /* debug (internal used) */
2415        .dump_pptable = arcturus_dump_pptable,
2416        .get_power_limit = arcturus_get_power_limit,
2417        .is_dpm_running = arcturus_is_dpm_running,
2418        .dpm_set_vcn_enable = arcturus_dpm_set_vcn_enable,
2419        .i2c_init = arcturus_i2c_control_init,
2420        .i2c_fini = arcturus_i2c_control_fini,
2421        .get_unique_id = arcturus_get_unique_id,
2422        .init_microcode = smu_v11_0_init_microcode,
2423        .load_microcode = smu_v11_0_load_microcode,
2424        .fini_microcode = smu_v11_0_fini_microcode,
2425        .init_smc_tables = arcturus_init_smc_tables,
2426        .fini_smc_tables = smu_v11_0_fini_smc_tables,
2427        .init_power = smu_v11_0_init_power,
2428        .fini_power = smu_v11_0_fini_power,
2429        .check_fw_status = smu_v11_0_check_fw_status,
2430        /* pptable related */
2431        .setup_pptable = arcturus_setup_pptable,
2432        .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2433        .check_fw_version = smu_v11_0_check_fw_version,
2434        .write_pptable = smu_cmn_write_pptable,
2435        .set_driver_table_location = smu_v11_0_set_driver_table_location,
2436        .set_tool_table_location = smu_v11_0_set_tool_table_location,
2437        .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2438        .system_features_control = smu_v11_0_system_features_control,
2439        .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2440        .send_smc_msg = smu_cmn_send_smc_msg,
2441        .init_display_count = NULL,
2442        .set_allowed_mask = smu_v11_0_set_allowed_mask,
2443        .get_enabled_mask = smu_cmn_get_enabled_mask,
2444        .feature_is_enabled = smu_cmn_feature_is_enabled,
2445        .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2446        .notify_display_change = NULL,
2447        .set_power_limit = smu_v11_0_set_power_limit,
2448        .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2449        .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2450        .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2451        .set_min_dcef_deep_sleep = NULL,
2452        .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2453        .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2454        .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2455        .set_fan_speed_pwm = arcturus_set_fan_speed_pwm,
2456        .set_fan_speed_rpm = arcturus_set_fan_speed_rpm,
2457        .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2458        .gfx_off_control = smu_v11_0_gfx_off_control,
2459        .register_irq_handler = smu_v11_0_register_irq_handler,
2460        .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2461        .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2462        .baco_is_support = smu_v11_0_baco_is_support,
2463        .baco_get_state = smu_v11_0_baco_get_state,
2464        .baco_set_state = smu_v11_0_baco_set_state,
2465        .baco_enter = smu_v11_0_baco_enter,
2466        .baco_exit = smu_v11_0_baco_exit,
2467        .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2468        .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2469        .set_df_cstate = arcturus_set_df_cstate,
2470        .allow_xgmi_power_down = arcturus_allow_xgmi_power_down,
2471        .log_thermal_throttling_event = arcturus_log_thermal_throttling_event,
2472        .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2473        .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2474        .get_gpu_metrics = arcturus_get_gpu_metrics,
2475        .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
2476        .deep_sleep_control = smu_v11_0_deep_sleep_control,
2477        .get_fan_parameters = arcturus_get_fan_parameters,
2478        .interrupt_work = smu_v11_0_interrupt_work,
2479        .set_light_sbr = smu_v11_0_set_light_sbr,
2480        .set_mp1_state = smu_cmn_set_mp1_state,
2481};
2482
2483void arcturus_set_ppt_funcs(struct smu_context *smu)
2484{
2485        smu->ppt_funcs = &arcturus_ppt_funcs;
2486        smu->message_map = arcturus_message_map;
2487        smu->clock_map = arcturus_clk_map;
2488        smu->feature_map = arcturus_feature_mask_map;
2489        smu->table_map = arcturus_table_map;
2490        smu->pwr_src_map = arcturus_pwr_src_map;
2491        smu->workload_map = arcturus_workload_map;
2492}
2493