1/* 2 * Copyright (C) 2013,2014 ARM Limited 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file COPYING in the main directory of this archive 6 * for more details. 7 * 8 * ARM HDLCD Controller register definition 9 */ 10 11#ifndef __HDLCD_REGS_H__ 12#define __HDLCD_REGS_H__ 13 14/* register offsets */ 15#define HDLCD_REG_VERSION 0x0000 /* ro */ 16#define HDLCD_REG_INT_RAWSTAT 0x0010 /* rw */ 17#define HDLCD_REG_INT_CLEAR 0x0014 /* wo */ 18#define HDLCD_REG_INT_MASK 0x0018 /* rw */ 19#define HDLCD_REG_INT_STATUS 0x001c /* ro */ 20#define HDLCD_REG_FB_BASE 0x0100 /* rw */ 21#define HDLCD_REG_FB_LINE_LENGTH 0x0104 /* rw */ 22#define HDLCD_REG_FB_LINE_COUNT 0x0108 /* rw */ 23#define HDLCD_REG_FB_LINE_PITCH 0x010c /* rw */ 24#define HDLCD_REG_BUS_OPTIONS 0x0110 /* rw */ 25#define HDLCD_REG_V_SYNC 0x0200 /* rw */ 26#define HDLCD_REG_V_BACK_PORCH 0x0204 /* rw */ 27#define HDLCD_REG_V_DATA 0x0208 /* rw */ 28#define HDLCD_REG_V_FRONT_PORCH 0x020c /* rw */ 29#define HDLCD_REG_H_SYNC 0x0210 /* rw */ 30#define HDLCD_REG_H_BACK_PORCH 0x0214 /* rw */ 31#define HDLCD_REG_H_DATA 0x0218 /* rw */ 32#define HDLCD_REG_H_FRONT_PORCH 0x021c /* rw */ 33#define HDLCD_REG_POLARITIES 0x0220 /* rw */ 34#define HDLCD_REG_COMMAND 0x0230 /* rw */ 35#define HDLCD_REG_PIXEL_FORMAT 0x0240 /* rw */ 36#define HDLCD_REG_RED_SELECT 0x0244 /* rw */ 37#define HDLCD_REG_GREEN_SELECT 0x0248 /* rw */ 38#define HDLCD_REG_BLUE_SELECT 0x024c /* rw */ 39 40/* version */ 41#define HDLCD_PRODUCT_ID 0x1CDC0000 42#define HDLCD_PRODUCT_MASK 0xFFFF0000 43#define HDLCD_VERSION_MAJOR_MASK 0x0000FF00 44#define HDLCD_VERSION_MINOR_MASK 0x000000FF 45 46/* interrupts */ 47#define HDLCD_INTERRUPT_DMA_END (1 << 0) 48#define HDLCD_INTERRUPT_BUS_ERROR (1 << 1) 49#define HDLCD_INTERRUPT_VSYNC (1 << 2) 50#define HDLCD_INTERRUPT_UNDERRUN (1 << 3) 51#define HDLCD_DEBUG_INT_MASK (HDLCD_INTERRUPT_DMA_END | \ 52 HDLCD_INTERRUPT_BUS_ERROR | \ 53 HDLCD_INTERRUPT_UNDERRUN) 54 55/* polarities */ 56#define HDLCD_POLARITY_VSYNC (1 << 0) 57#define HDLCD_POLARITY_HSYNC (1 << 1) 58#define HDLCD_POLARITY_DATAEN (1 << 2) 59#define HDLCD_POLARITY_DATA (1 << 3) 60#define HDLCD_POLARITY_PIXELCLK (1 << 4) 61 62/* commands */ 63#define HDLCD_COMMAND_DISABLE (0 << 0) 64#define HDLCD_COMMAND_ENABLE (1 << 0) 65 66/* pixel format */ 67#define HDLCD_PIXEL_FMT_LITTLE_ENDIAN (0 << 31) 68#define HDLCD_PIXEL_FMT_BIG_ENDIAN (1 << 31) 69#define HDLCD_BYTES_PER_PIXEL_MASK (3 << 3) 70 71/* bus options */ 72#define HDLCD_BUS_BURST_MASK 0x01f 73#define HDLCD_BUS_MAX_OUTSTAND 0xf00 74#define HDLCD_BUS_BURST_NONE (0 << 0) 75#define HDLCD_BUS_BURST_1 (1 << 0) 76#define HDLCD_BUS_BURST_2 (1 << 1) 77#define HDLCD_BUS_BURST_4 (1 << 2) 78#define HDLCD_BUS_BURST_8 (1 << 3) 79#define HDLCD_BUS_BURST_16 (1 << 4) 80 81/* Max resolution supported is 4096x4096, 32bpp */ 82#define HDLCD_MAX_XRES 4096 83#define HDLCD_MAX_YRES 4096 84 85#define NR_PALETTE 256 86 87#endif /* __HDLCD_REGS_H__ */ 88