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10#include <linux/module.h>
11#include <linux/device.h>
12#include <linux/interrupt.h>
13#include <linux/i2c.h>
14#include <linux/bitfield.h>
15#include <linux/property.h>
16#include <linux/regmap.h>
17#include <linux/of_graph.h>
18#include <linux/gpio/consumer.h>
19#include <linux/pinctrl/consumer.h>
20#include <linux/regulator/consumer.h>
21
22#include <drm/drm_atomic_helper.h>
23#include <drm/drm_bridge.h>
24#include <drm/drm_crtc_helper.h>
25#include <drm/drm_edid.h>
26#include <drm/drm_modes.h>
27#include <drm/drm_print.h>
28#include <drm/drm_probe_helper.h>
29
30#define IT66121_VENDOR_ID0_REG 0x00
31#define IT66121_VENDOR_ID1_REG 0x01
32#define IT66121_DEVICE_ID0_REG 0x02
33#define IT66121_DEVICE_ID1_REG 0x03
34
35#define IT66121_VENDOR_ID0 0x54
36#define IT66121_VENDOR_ID1 0x49
37#define IT66121_DEVICE_ID0 0x12
38#define IT66121_DEVICE_ID1 0x06
39#define IT66121_REVISION_MASK GENMASK(7, 4)
40#define IT66121_DEVICE_ID1_MASK GENMASK(3, 0)
41
42#define IT66121_MASTER_SEL_REG 0x10
43#define IT66121_MASTER_SEL_HOST BIT(0)
44
45#define IT66121_AFE_DRV_REG 0x61
46#define IT66121_AFE_DRV_RST BIT(4)
47#define IT66121_AFE_DRV_PWD BIT(5)
48
49#define IT66121_INPUT_MODE_REG 0x70
50#define IT66121_INPUT_MODE_RGB (0 << 6)
51#define IT66121_INPUT_MODE_YUV422 BIT(6)
52#define IT66121_INPUT_MODE_YUV444 (2 << 6)
53#define IT66121_INPUT_MODE_CCIR656 BIT(4)
54#define IT66121_INPUT_MODE_SYNCEMB BIT(3)
55#define IT66121_INPUT_MODE_DDR BIT(2)
56
57#define IT66121_INPUT_CSC_REG 0x72
58#define IT66121_INPUT_CSC_ENDITHER BIT(7)
59#define IT66121_INPUT_CSC_ENUDFILTER BIT(6)
60#define IT66121_INPUT_CSC_DNFREE_GO BIT(5)
61#define IT66121_INPUT_CSC_RGB_TO_YUV 0x02
62#define IT66121_INPUT_CSC_YUV_TO_RGB 0x03
63#define IT66121_INPUT_CSC_NO_CONV 0x00
64
65#define IT66121_AFE_XP_REG 0x62
66#define IT66121_AFE_XP_GAINBIT BIT(7)
67#define IT66121_AFE_XP_PWDPLL BIT(6)
68#define IT66121_AFE_XP_ENI BIT(5)
69#define IT66121_AFE_XP_ENO BIT(4)
70#define IT66121_AFE_XP_RESETB BIT(3)
71#define IT66121_AFE_XP_PWDI BIT(2)
72
73#define IT66121_AFE_IP_REG 0x64
74#define IT66121_AFE_IP_GAINBIT BIT(7)
75#define IT66121_AFE_IP_PWDPLL BIT(6)
76#define IT66121_AFE_IP_CKSEL_05 (0 << 4)
77#define IT66121_AFE_IP_CKSEL_1 BIT(4)
78#define IT66121_AFE_IP_CKSEL_2 (2 << 4)
79#define IT66121_AFE_IP_CKSEL_2OR4 (3 << 4)
80#define IT66121_AFE_IP_ER0 BIT(3)
81#define IT66121_AFE_IP_RESETB BIT(2)
82#define IT66121_AFE_IP_ENC BIT(1)
83#define IT66121_AFE_IP_EC1 BIT(0)
84
85#define IT66121_AFE_XP_EC1_REG 0x68
86#define IT66121_AFE_XP_EC1_LOWCLK BIT(4)
87
88#define IT66121_SW_RST_REG 0x04
89#define IT66121_SW_RST_REF BIT(5)
90#define IT66121_SW_RST_AREF BIT(4)
91#define IT66121_SW_RST_VID BIT(3)
92#define IT66121_SW_RST_AUD BIT(2)
93#define IT66121_SW_RST_HDCP BIT(0)
94
95#define IT66121_DDC_COMMAND_REG 0x15
96#define IT66121_DDC_COMMAND_BURST_READ 0x0
97#define IT66121_DDC_COMMAND_EDID_READ 0x3
98#define IT66121_DDC_COMMAND_FIFO_CLR 0x9
99#define IT66121_DDC_COMMAND_SCL_PULSE 0xA
100#define IT66121_DDC_COMMAND_ABORT 0xF
101
102#define IT66121_HDCP_REG 0x20
103#define IT66121_HDCP_CPDESIRED BIT(0)
104#define IT66121_HDCP_EN1P1FEAT BIT(1)
105
106#define IT66121_INT_STATUS1_REG 0x06
107#define IT66121_INT_STATUS1_AUD_OVF BIT(7)
108#define IT66121_INT_STATUS1_DDC_NOACK BIT(5)
109#define IT66121_INT_STATUS1_DDC_FIFOERR BIT(4)
110#define IT66121_INT_STATUS1_DDC_BUSHANG BIT(2)
111#define IT66121_INT_STATUS1_RX_SENS_STATUS BIT(1)
112#define IT66121_INT_STATUS1_HPD_STATUS BIT(0)
113
114#define IT66121_DDC_HEADER_REG 0x11
115#define IT66121_DDC_HEADER_HDCP 0x74
116#define IT66121_DDC_HEADER_EDID 0xA0
117
118#define IT66121_DDC_OFFSET_REG 0x12
119#define IT66121_DDC_BYTE_REG 0x13
120#define IT66121_DDC_SEGMENT_REG 0x14
121#define IT66121_DDC_RD_FIFO_REG 0x17
122
123#define IT66121_CLK_BANK_REG 0x0F
124#define IT66121_CLK_BANK_PWROFF_RCLK BIT(6)
125#define IT66121_CLK_BANK_PWROFF_ACLK BIT(5)
126#define IT66121_CLK_BANK_PWROFF_TXCLK BIT(4)
127#define IT66121_CLK_BANK_PWROFF_CRCLK BIT(3)
128#define IT66121_CLK_BANK_0 0
129#define IT66121_CLK_BANK_1 1
130
131#define IT66121_INT_REG 0x05
132#define IT66121_INT_ACTIVE_HIGH BIT(7)
133#define IT66121_INT_OPEN_DRAIN BIT(6)
134#define IT66121_INT_TX_CLK_OFF BIT(0)
135
136#define IT66121_INT_MASK1_REG 0x09
137#define IT66121_INT_MASK1_AUD_OVF BIT(7)
138#define IT66121_INT_MASK1_DDC_NOACK BIT(5)
139#define IT66121_INT_MASK1_DDC_FIFOERR BIT(4)
140#define IT66121_INT_MASK1_DDC_BUSHANG BIT(2)
141#define IT66121_INT_MASK1_RX_SENS BIT(1)
142#define IT66121_INT_MASK1_HPD BIT(0)
143
144#define IT66121_INT_CLR1_REG 0x0C
145#define IT66121_INT_CLR1_PKTACP BIT(7)
146#define IT66121_INT_CLR1_PKTNULL BIT(6)
147#define IT66121_INT_CLR1_PKTGEN BIT(5)
148#define IT66121_INT_CLR1_KSVLISTCHK BIT(4)
149#define IT66121_INT_CLR1_AUTHDONE BIT(3)
150#define IT66121_INT_CLR1_AUTHFAIL BIT(2)
151#define IT66121_INT_CLR1_RX_SENS BIT(1)
152#define IT66121_INT_CLR1_HPD BIT(0)
153
154#define IT66121_AV_MUTE_REG 0xC1
155#define IT66121_AV_MUTE_ON BIT(0)
156#define IT66121_AV_MUTE_BLUESCR BIT(1)
157
158#define IT66121_PKT_GEN_CTRL_REG 0xC6
159#define IT66121_PKT_GEN_CTRL_ON BIT(0)
160#define IT66121_PKT_GEN_CTRL_RPT BIT(1)
161
162#define IT66121_AVIINFO_DB1_REG 0x158
163#define IT66121_AVIINFO_DB2_REG 0x159
164#define IT66121_AVIINFO_DB3_REG 0x15A
165#define IT66121_AVIINFO_DB4_REG 0x15B
166#define IT66121_AVIINFO_DB5_REG 0x15C
167#define IT66121_AVIINFO_CSUM_REG 0x15D
168#define IT66121_AVIINFO_DB6_REG 0x15E
169#define IT66121_AVIINFO_DB7_REG 0x15F
170#define IT66121_AVIINFO_DB8_REG 0x160
171#define IT66121_AVIINFO_DB9_REG 0x161
172#define IT66121_AVIINFO_DB10_REG 0x162
173#define IT66121_AVIINFO_DB11_REG 0x163
174#define IT66121_AVIINFO_DB12_REG 0x164
175#define IT66121_AVIINFO_DB13_REG 0x165
176
177#define IT66121_AVI_INFO_PKT_REG 0xCD
178#define IT66121_AVI_INFO_PKT_ON BIT(0)
179#define IT66121_AVI_INFO_PKT_RPT BIT(1)
180
181#define IT66121_HDMI_MODE_REG 0xC0
182#define IT66121_HDMI_MODE_HDMI BIT(0)
183
184#define IT66121_SYS_STATUS_REG 0x0E
185#define IT66121_SYS_STATUS_ACTIVE_IRQ BIT(7)
186#define IT66121_SYS_STATUS_HPDETECT BIT(6)
187#define IT66121_SYS_STATUS_SENDECTECT BIT(5)
188#define IT66121_SYS_STATUS_VID_STABLE BIT(4)
189#define IT66121_SYS_STATUS_AUD_CTS_CLR BIT(1)
190#define IT66121_SYS_STATUS_CLEAR_IRQ BIT(0)
191
192#define IT66121_DDC_STATUS_REG 0x16
193#define IT66121_DDC_STATUS_TX_DONE BIT(7)
194#define IT66121_DDC_STATUS_ACTIVE BIT(6)
195#define IT66121_DDC_STATUS_NOACK BIT(5)
196#define IT66121_DDC_STATUS_WAIT_BUS BIT(4)
197#define IT66121_DDC_STATUS_ARBI_LOSE BIT(3)
198#define IT66121_DDC_STATUS_FIFO_FULL BIT(2)
199#define IT66121_DDC_STATUS_FIFO_EMPTY BIT(1)
200#define IT66121_DDC_STATUS_FIFO_VALID BIT(0)
201
202#define IT66121_EDID_SLEEP_US 20000
203#define IT66121_EDID_TIMEOUT_US 200000
204#define IT66121_EDID_FIFO_SIZE 32
205#define IT66121_AFE_CLK_HIGH 80000
206
207struct it66121_ctx {
208 struct regmap *regmap;
209 struct drm_bridge bridge;
210 struct drm_bridge *next_bridge;
211 struct drm_connector *connector;
212 struct device *dev;
213 struct gpio_desc *gpio_reset;
214 struct i2c_client *client;
215 struct regulator_bulk_data supplies[3];
216 u32 bus_width;
217 struct mutex lock;
218 struct hdmi_avi_infoframe hdmi_avi_infoframe;
219};
220
221static const struct regmap_range_cfg it66121_regmap_banks[] = {
222 {
223 .name = "it66121",
224 .range_min = 0x00,
225 .range_max = 0x1FF,
226 .selector_reg = IT66121_CLK_BANK_REG,
227 .selector_mask = 0x1,
228 .selector_shift = 0,
229 .window_start = 0x00,
230 .window_len = 0x130,
231 },
232};
233
234static const struct regmap_config it66121_regmap_config = {
235 .val_bits = 8,
236 .reg_bits = 8,
237 .max_register = 0x1FF,
238 .ranges = it66121_regmap_banks,
239 .num_ranges = ARRAY_SIZE(it66121_regmap_banks),
240};
241
242static void it66121_hw_reset(struct it66121_ctx *ctx)
243{
244 gpiod_set_value(ctx->gpio_reset, 1);
245 msleep(20);
246 gpiod_set_value(ctx->gpio_reset, 0);
247}
248
249static inline int ite66121_power_on(struct it66121_ctx *ctx)
250{
251 return regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
252}
253
254static inline int ite66121_power_off(struct it66121_ctx *ctx)
255{
256 return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
257}
258
259static inline int it66121_preamble_ddc(struct it66121_ctx *ctx)
260{
261 return regmap_write(ctx->regmap, IT66121_MASTER_SEL_REG, IT66121_MASTER_SEL_HOST);
262}
263
264static inline int it66121_fire_afe(struct it66121_ctx *ctx)
265{
266 return regmap_write(ctx->regmap, IT66121_AFE_DRV_REG, 0);
267}
268
269
270static int it66121_configure_input(struct it66121_ctx *ctx)
271{
272 int ret;
273 u8 mode = IT66121_INPUT_MODE_RGB;
274
275 if (ctx->bus_width == 12)
276 mode |= IT66121_INPUT_MODE_DDR;
277
278 ret = regmap_write(ctx->regmap, IT66121_INPUT_MODE_REG, mode);
279 if (ret)
280 return ret;
281
282 return regmap_write(ctx->regmap, IT66121_INPUT_CSC_REG, IT66121_INPUT_CSC_NO_CONV);
283}
284
285
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289
290
291
292
293static int it66121_configure_afe(struct it66121_ctx *ctx,
294 const struct drm_display_mode *mode)
295{
296 int ret;
297
298 ret = regmap_write(ctx->regmap, IT66121_AFE_DRV_REG,
299 IT66121_AFE_DRV_RST);
300 if (ret)
301 return ret;
302
303 if (mode->clock > IT66121_AFE_CLK_HIGH) {
304 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG,
305 IT66121_AFE_XP_GAINBIT |
306 IT66121_AFE_XP_ENO,
307 IT66121_AFE_XP_GAINBIT);
308 if (ret)
309 return ret;
310
311 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG,
312 IT66121_AFE_IP_GAINBIT |
313 IT66121_AFE_IP_ER0 |
314 IT66121_AFE_IP_EC1,
315 IT66121_AFE_IP_GAINBIT);
316 if (ret)
317 return ret;
318
319 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_EC1_REG,
320 IT66121_AFE_XP_EC1_LOWCLK, 0x80);
321 if (ret)
322 return ret;
323 } else {
324 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG,
325 IT66121_AFE_XP_GAINBIT |
326 IT66121_AFE_XP_ENO,
327 IT66121_AFE_XP_ENO);
328 if (ret)
329 return ret;
330
331 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG,
332 IT66121_AFE_IP_GAINBIT |
333 IT66121_AFE_IP_ER0 |
334 IT66121_AFE_IP_EC1, IT66121_AFE_IP_ER0 |
335 IT66121_AFE_IP_EC1);
336 if (ret)
337 return ret;
338
339 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_EC1_REG,
340 IT66121_AFE_XP_EC1_LOWCLK,
341 IT66121_AFE_XP_EC1_LOWCLK);
342 if (ret)
343 return ret;
344 }
345
346
347 ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG,
348 IT66121_SW_RST_REF | IT66121_SW_RST_VID, 0);
349 if (ret)
350 return ret;
351
352 return it66121_fire_afe(ctx);
353}
354
355static inline int it66121_wait_ddc_ready(struct it66121_ctx *ctx)
356{
357 int ret, val;
358 u32 busy = IT66121_DDC_STATUS_NOACK | IT66121_DDC_STATUS_WAIT_BUS |
359 IT66121_DDC_STATUS_ARBI_LOSE;
360
361 ret = regmap_read_poll_timeout(ctx->regmap, IT66121_DDC_STATUS_REG, val, true,
362 IT66121_EDID_SLEEP_US, IT66121_EDID_TIMEOUT_US);
363 if (ret)
364 return ret;
365
366 if (val & busy)
367 return -EAGAIN;
368
369 return 0;
370}
371
372static int it66121_clear_ddc_fifo(struct it66121_ctx *ctx)
373{
374 int ret;
375
376 ret = it66121_preamble_ddc(ctx);
377 if (ret)
378 return ret;
379
380 return regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG,
381 IT66121_DDC_COMMAND_FIFO_CLR);
382}
383
384static int it66121_abort_ddc_ops(struct it66121_ctx *ctx)
385{
386 int ret;
387 unsigned int swreset, cpdesire;
388
389 ret = regmap_read(ctx->regmap, IT66121_SW_RST_REG, &swreset);
390 if (ret)
391 return ret;
392
393 ret = regmap_read(ctx->regmap, IT66121_HDCP_REG, &cpdesire);
394 if (ret)
395 return ret;
396
397 ret = regmap_write(ctx->regmap, IT66121_HDCP_REG,
398 cpdesire & (~IT66121_HDCP_CPDESIRED & 0xFF));
399 if (ret)
400 return ret;
401
402 ret = regmap_write(ctx->regmap, IT66121_SW_RST_REG,
403 (swreset | IT66121_SW_RST_HDCP));
404 if (ret)
405 return ret;
406
407 ret = it66121_preamble_ddc(ctx);
408 if (ret)
409 return ret;
410
411 ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG,
412 IT66121_DDC_COMMAND_ABORT);
413 if (ret)
414 return ret;
415
416 return it66121_wait_ddc_ready(ctx);
417}
418
419static int it66121_get_edid_block(void *context, u8 *buf,
420 unsigned int block, size_t len)
421{
422 struct it66121_ctx *ctx = context;
423 unsigned int val;
424 int remain = len;
425 int offset = 0;
426 int ret, cnt;
427
428 offset = (block % 2) * len;
429 block = block / 2;
430
431 ret = regmap_read(ctx->regmap, IT66121_INT_STATUS1_REG, &val);
432 if (ret)
433 return ret;
434
435 if (val & IT66121_INT_STATUS1_DDC_BUSHANG) {
436 ret = it66121_abort_ddc_ops(ctx);
437 if (ret)
438 return ret;
439 }
440
441 ret = it66121_clear_ddc_fifo(ctx);
442 if (ret)
443 return ret;
444
445 while (remain > 0) {
446 cnt = (remain > IT66121_EDID_FIFO_SIZE) ?
447 IT66121_EDID_FIFO_SIZE : remain;
448 ret = it66121_preamble_ddc(ctx);
449 if (ret)
450 return ret;
451
452 ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG,
453 IT66121_DDC_COMMAND_FIFO_CLR);
454 if (ret)
455 return ret;
456
457 ret = it66121_wait_ddc_ready(ctx);
458 if (ret)
459 return ret;
460
461 ret = regmap_read(ctx->regmap, IT66121_INT_STATUS1_REG, &val);
462 if (ret)
463 return ret;
464
465 if (val & IT66121_INT_STATUS1_DDC_BUSHANG) {
466 ret = it66121_abort_ddc_ops(ctx);
467 if (ret)
468 return ret;
469 }
470
471 ret = it66121_preamble_ddc(ctx);
472 if (ret)
473 return ret;
474
475 ret = regmap_write(ctx->regmap, IT66121_DDC_HEADER_REG,
476 IT66121_DDC_HEADER_EDID);
477 if (ret)
478 return ret;
479
480 ret = regmap_write(ctx->regmap, IT66121_DDC_OFFSET_REG, offset);
481 if (ret)
482 return ret;
483
484 ret = regmap_write(ctx->regmap, IT66121_DDC_BYTE_REG, cnt);
485 if (ret)
486 return ret;
487
488 ret = regmap_write(ctx->regmap, IT66121_DDC_SEGMENT_REG, block);
489 if (ret)
490 return ret;
491
492 ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG,
493 IT66121_DDC_COMMAND_EDID_READ);
494 if (ret)
495 return ret;
496
497 offset += cnt;
498 remain -= cnt;
499
500
501 msleep(20);
502
503 ret = it66121_wait_ddc_ready(ctx);
504 if (ret)
505 return ret;
506
507 do {
508 ret = regmap_read(ctx->regmap, IT66121_DDC_RD_FIFO_REG, &val);
509 if (ret)
510 return ret;
511 *(buf++) = val;
512 cnt--;
513 } while (cnt > 0);
514 }
515
516 return 0;
517}
518
519static bool it66121_is_hpd_detect(struct it66121_ctx *ctx)
520{
521 int val;
522
523 if (regmap_read(ctx->regmap, IT66121_SYS_STATUS_REG, &val))
524 return false;
525
526 return val & IT66121_SYS_STATUS_HPDETECT;
527}
528
529static int it66121_bridge_attach(struct drm_bridge *bridge,
530 enum drm_bridge_attach_flags flags)
531{
532 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
533 int ret;
534
535 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
536 return -EINVAL;
537
538 ret = drm_bridge_attach(bridge->encoder, ctx->next_bridge, bridge, flags);
539 if (ret)
540 return ret;
541
542 ret = regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG,
543 IT66121_CLK_BANK_PWROFF_RCLK, 0);
544 if (ret)
545 return ret;
546
547 ret = regmap_write_bits(ctx->regmap, IT66121_INT_REG,
548 IT66121_INT_TX_CLK_OFF, 0);
549 if (ret)
550 return ret;
551
552 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_DRV_REG,
553 IT66121_AFE_DRV_PWD, 0);
554 if (ret)
555 return ret;
556
557 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG,
558 IT66121_AFE_XP_PWDI | IT66121_AFE_XP_PWDPLL, 0);
559 if (ret)
560 return ret;
561
562 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG,
563 IT66121_AFE_IP_PWDPLL, 0);
564 if (ret)
565 return ret;
566
567 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_DRV_REG,
568 IT66121_AFE_DRV_RST, 0);
569 if (ret)
570 return ret;
571
572 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG,
573 IT66121_AFE_XP_RESETB, IT66121_AFE_XP_RESETB);
574 if (ret)
575 return ret;
576
577 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG,
578 IT66121_AFE_IP_RESETB, IT66121_AFE_IP_RESETB);
579 if (ret)
580 return ret;
581
582 ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG,
583 IT66121_SW_RST_REF,
584 IT66121_SW_RST_REF);
585 if (ret)
586 return ret;
587
588
589 msleep(50);
590
591
592 return regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG,
593 IT66121_INT_MASK1_DDC_NOACK |
594 IT66121_INT_MASK1_DDC_FIFOERR |
595 IT66121_INT_MASK1_DDC_BUSHANG, 0);
596}
597
598static int it66121_set_mute(struct it66121_ctx *ctx, bool mute)
599{
600 int ret;
601 unsigned int val = 0;
602
603 if (mute)
604 val = IT66121_AV_MUTE_ON;
605
606 ret = regmap_write_bits(ctx->regmap, IT66121_AV_MUTE_REG, IT66121_AV_MUTE_ON, val);
607 if (ret)
608 return ret;
609
610 return regmap_write(ctx->regmap, IT66121_PKT_GEN_CTRL_REG,
611 IT66121_PKT_GEN_CTRL_ON | IT66121_PKT_GEN_CTRL_RPT);
612}
613
614#define MAX_OUTPUT_SEL_FORMATS 1
615
616static u32 *it66121_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
617 struct drm_bridge_state *bridge_state,
618 struct drm_crtc_state *crtc_state,
619 struct drm_connector_state *conn_state,
620 unsigned int *num_output_fmts)
621{
622 u32 *output_fmts;
623
624 output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts),
625 GFP_KERNEL);
626 if (!output_fmts)
627 return NULL;
628
629
630 output_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
631 *num_output_fmts = 1;
632
633 return output_fmts;
634}
635
636#define MAX_INPUT_SEL_FORMATS 1
637
638static u32 *it66121_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
639 struct drm_bridge_state *bridge_state,
640 struct drm_crtc_state *crtc_state,
641 struct drm_connector_state *conn_state,
642 u32 output_fmt,
643 unsigned int *num_input_fmts)
644{
645 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
646 u32 *input_fmts;
647
648 *num_input_fmts = 0;
649
650 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
651 GFP_KERNEL);
652 if (!input_fmts)
653 return NULL;
654
655 if (ctx->bus_width == 12)
656
657 input_fmts[0] = MEDIA_BUS_FMT_RGB888_2X12_LE;
658 else
659
660 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
661 *num_input_fmts = 1;
662
663 return input_fmts;
664}
665
666static void it66121_bridge_enable(struct drm_bridge *bridge,
667 struct drm_bridge_state *bridge_state)
668{
669 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
670 struct drm_atomic_state *state = bridge_state->base.state;
671
672 ctx->connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
673
674 it66121_set_mute(ctx, false);
675}
676
677static void it66121_bridge_disable(struct drm_bridge *bridge,
678 struct drm_bridge_state *bridge_state)
679{
680 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
681
682 it66121_set_mute(ctx, true);
683
684 ctx->connector = NULL;
685}
686
687static
688void it66121_bridge_mode_set(struct drm_bridge *bridge,
689 const struct drm_display_mode *mode,
690 const struct drm_display_mode *adjusted_mode)
691{
692 int ret, i;
693 u8 buf[HDMI_INFOFRAME_SIZE(AVI)];
694 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
695 const u16 aviinfo_reg[HDMI_AVI_INFOFRAME_SIZE] = {
696 IT66121_AVIINFO_DB1_REG,
697 IT66121_AVIINFO_DB2_REG,
698 IT66121_AVIINFO_DB3_REG,
699 IT66121_AVIINFO_DB4_REG,
700 IT66121_AVIINFO_DB5_REG,
701 IT66121_AVIINFO_DB6_REG,
702 IT66121_AVIINFO_DB7_REG,
703 IT66121_AVIINFO_DB8_REG,
704 IT66121_AVIINFO_DB9_REG,
705 IT66121_AVIINFO_DB10_REG,
706 IT66121_AVIINFO_DB11_REG,
707 IT66121_AVIINFO_DB12_REG,
708 IT66121_AVIINFO_DB13_REG
709 };
710
711 mutex_lock(&ctx->lock);
712
713 hdmi_avi_infoframe_init(&ctx->hdmi_avi_infoframe);
714
715 ret = drm_hdmi_avi_infoframe_from_display_mode(&ctx->hdmi_avi_infoframe, ctx->connector,
716 adjusted_mode);
717 if (ret) {
718 DRM_ERROR("Failed to setup AVI infoframe: %d\n", ret);
719 goto unlock;
720 }
721
722 ret = hdmi_avi_infoframe_pack(&ctx->hdmi_avi_infoframe, buf, sizeof(buf));
723 if (ret < 0) {
724 DRM_ERROR("Failed to pack infoframe: %d\n", ret);
725 goto unlock;
726 }
727
728
729 for (i = 0; i < HDMI_AVI_INFOFRAME_SIZE; i++) {
730 if (regmap_write(ctx->regmap, aviinfo_reg[i], buf[i + HDMI_INFOFRAME_HEADER_SIZE]))
731 goto unlock;
732 }
733 if (regmap_write(ctx->regmap, IT66121_AVIINFO_CSUM_REG, buf[3]))
734 goto unlock;
735
736
737 if (regmap_write(ctx->regmap, IT66121_AVI_INFO_PKT_REG,
738 IT66121_AVI_INFO_PKT_ON | IT66121_AVI_INFO_PKT_RPT))
739 goto unlock;
740
741
742 if (regmap_write(ctx->regmap, IT66121_HDMI_MODE_REG, IT66121_HDMI_MODE_HDMI))
743 goto unlock;
744
745 if (regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG,
746 IT66121_CLK_BANK_PWROFF_TXCLK, IT66121_CLK_BANK_PWROFF_TXCLK))
747 goto unlock;
748
749 if (it66121_configure_input(ctx))
750 goto unlock;
751
752 if (it66121_configure_afe(ctx, adjusted_mode))
753 goto unlock;
754
755 regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG, IT66121_CLK_BANK_PWROFF_TXCLK, 0);
756
757unlock:
758 mutex_unlock(&ctx->lock);
759}
760
761static enum drm_mode_status it66121_bridge_mode_valid(struct drm_bridge *bridge,
762 const struct drm_display_info *info,
763 const struct drm_display_mode *mode)
764{
765 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
766 unsigned long max_clock;
767
768 max_clock = (ctx->bus_width == 12) ? 74250 : 148500;
769
770 if (mode->clock > max_clock)
771 return MODE_CLOCK_HIGH;
772
773 if (mode->clock < 25000)
774 return MODE_CLOCK_LOW;
775
776 return MODE_OK;
777}
778
779static enum drm_connector_status it66121_bridge_detect(struct drm_bridge *bridge)
780{
781 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
782
783 return it66121_is_hpd_detect(ctx) ? connector_status_connected
784 : connector_status_disconnected;
785}
786
787static void it66121_bridge_hpd_enable(struct drm_bridge *bridge)
788{
789 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
790 int ret;
791
792 ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG, IT66121_INT_MASK1_HPD, 0);
793 if (ret)
794 dev_err(ctx->dev, "failed to enable HPD IRQ\n");
795}
796
797static void it66121_bridge_hpd_disable(struct drm_bridge *bridge)
798{
799 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
800 int ret;
801
802 ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG,
803 IT66121_INT_MASK1_HPD, IT66121_INT_MASK1_HPD);
804 if (ret)
805 dev_err(ctx->dev, "failed to disable HPD IRQ\n");
806}
807
808static struct edid *it66121_bridge_get_edid(struct drm_bridge *bridge,
809 struct drm_connector *connector)
810{
811 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
812 struct edid *edid;
813
814 mutex_lock(&ctx->lock);
815 edid = drm_do_get_edid(connector, it66121_get_edid_block, ctx);
816 mutex_unlock(&ctx->lock);
817
818 return edid;
819}
820
821static const struct drm_bridge_funcs it66121_bridge_funcs = {
822 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
823 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
824 .atomic_reset = drm_atomic_helper_bridge_reset,
825 .attach = it66121_bridge_attach,
826 .atomic_get_output_bus_fmts = it66121_bridge_atomic_get_output_bus_fmts,
827 .atomic_get_input_bus_fmts = it66121_bridge_atomic_get_input_bus_fmts,
828 .atomic_enable = it66121_bridge_enable,
829 .atomic_disable = it66121_bridge_disable,
830 .mode_set = it66121_bridge_mode_set,
831 .mode_valid = it66121_bridge_mode_valid,
832 .detect = it66121_bridge_detect,
833 .get_edid = it66121_bridge_get_edid,
834 .hpd_enable = it66121_bridge_hpd_enable,
835 .hpd_disable = it66121_bridge_hpd_disable,
836};
837
838static irqreturn_t it66121_irq_threaded_handler(int irq, void *dev_id)
839{
840 int ret;
841 unsigned int val;
842 struct it66121_ctx *ctx = dev_id;
843 struct device *dev = ctx->dev;
844 enum drm_connector_status status;
845 bool event = false;
846
847 mutex_lock(&ctx->lock);
848
849 ret = regmap_read(ctx->regmap, IT66121_SYS_STATUS_REG, &val);
850 if (ret)
851 goto unlock;
852
853 if (!(val & IT66121_SYS_STATUS_ACTIVE_IRQ))
854 goto unlock;
855
856 ret = regmap_read(ctx->regmap, IT66121_INT_STATUS1_REG, &val);
857 if (ret) {
858 dev_err(dev, "Cannot read STATUS1_REG %d\n", ret);
859 } else {
860 if (val & IT66121_INT_STATUS1_DDC_FIFOERR)
861 it66121_clear_ddc_fifo(ctx);
862 if (val & (IT66121_INT_STATUS1_DDC_BUSHANG |
863 IT66121_INT_STATUS1_DDC_NOACK))
864 it66121_abort_ddc_ops(ctx);
865 if (val & IT66121_INT_STATUS1_HPD_STATUS) {
866 regmap_write_bits(ctx->regmap, IT66121_INT_CLR1_REG,
867 IT66121_INT_CLR1_HPD, IT66121_INT_CLR1_HPD);
868
869 status = it66121_is_hpd_detect(ctx) ? connector_status_connected
870 : connector_status_disconnected;
871
872 event = true;
873 }
874 }
875
876 regmap_write_bits(ctx->regmap, IT66121_SYS_STATUS_REG,
877 IT66121_SYS_STATUS_CLEAR_IRQ,
878 IT66121_SYS_STATUS_CLEAR_IRQ);
879
880unlock:
881 mutex_unlock(&ctx->lock);
882
883 if (event)
884 drm_bridge_hpd_notify(&ctx->bridge, status);
885
886 return IRQ_HANDLED;
887}
888
889static int it66121_probe(struct i2c_client *client,
890 const struct i2c_device_id *id)
891{
892 u32 vendor_ids[2], device_ids[2], revision_id;
893 struct device_node *ep;
894 int ret;
895 struct it66121_ctx *ctx;
896 struct device *dev = &client->dev;
897
898 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
899 dev_err(dev, "I2C check functionality failed.\n");
900 return -ENXIO;
901 }
902
903 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
904 if (!ctx)
905 return -ENOMEM;
906
907 ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0);
908 if (!ep)
909 return -EINVAL;
910
911 ctx->dev = dev;
912 ctx->client = client;
913
914 of_property_read_u32(ep, "bus-width", &ctx->bus_width);
915 of_node_put(ep);
916
917 if (ctx->bus_width != 12 && ctx->bus_width != 24)
918 return -EINVAL;
919
920 ep = of_graph_get_remote_node(dev->of_node, 1, -1);
921 if (!ep)
922 return -EPROBE_DEFER;
923
924 ctx->next_bridge = of_drm_find_bridge(ep);
925 of_node_put(ep);
926
927 i2c_set_clientdata(client, ctx);
928 mutex_init(&ctx->lock);
929
930 ctx->supplies[0].supply = "vcn33";
931 ctx->supplies[1].supply = "vcn18";
932 ctx->supplies[2].supply = "vrf12";
933 ret = devm_regulator_bulk_get(ctx->dev, 3, ctx->supplies);
934 if (ret) {
935 dev_err(ctx->dev, "regulator_bulk failed\n");
936 return ret;
937 }
938
939 ret = ite66121_power_on(ctx);
940 if (ret)
941 return ret;
942
943 it66121_hw_reset(ctx);
944
945 ctx->regmap = devm_regmap_init_i2c(client, &it66121_regmap_config);
946 if (IS_ERR(ctx->regmap)) {
947 ite66121_power_off(ctx);
948 return PTR_ERR(ctx->regmap);
949 }
950
951 regmap_read(ctx->regmap, IT66121_VENDOR_ID0_REG, &vendor_ids[0]);
952 regmap_read(ctx->regmap, IT66121_VENDOR_ID1_REG, &vendor_ids[1]);
953 regmap_read(ctx->regmap, IT66121_DEVICE_ID0_REG, &device_ids[0]);
954 regmap_read(ctx->regmap, IT66121_DEVICE_ID1_REG, &device_ids[1]);
955
956
957 revision_id = FIELD_GET(IT66121_REVISION_MASK, device_ids[1]);
958 device_ids[1] &= IT66121_DEVICE_ID1_MASK;
959
960 if (vendor_ids[0] != IT66121_VENDOR_ID0 || vendor_ids[1] != IT66121_VENDOR_ID1 ||
961 device_ids[0] != IT66121_DEVICE_ID0 || device_ids[1] != IT66121_DEVICE_ID1) {
962 ite66121_power_off(ctx);
963 return -ENODEV;
964 }
965
966 ctx->bridge.funcs = &it66121_bridge_funcs;
967 ctx->bridge.of_node = dev->of_node;
968 ctx->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
969 ctx->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD;
970
971 ret = devm_request_threaded_irq(dev, client->irq, NULL, it66121_irq_threaded_handler,
972 IRQF_ONESHOT, dev_name(dev), ctx);
973 if (ret < 0) {
974 dev_err(dev, "Failed to request irq %d:%d\n", client->irq, ret);
975 ite66121_power_off(ctx);
976 return ret;
977 }
978
979 drm_bridge_add(&ctx->bridge);
980
981 dev_info(ctx->dev, "IT66121 revision %d probed\n", revision_id);
982
983 return 0;
984}
985
986static int it66121_remove(struct i2c_client *client)
987{
988 struct it66121_ctx *ctx = i2c_get_clientdata(client);
989
990 ite66121_power_off(ctx);
991 drm_bridge_remove(&ctx->bridge);
992 mutex_destroy(&ctx->lock);
993
994 return 0;
995}
996
997static const struct of_device_id it66121_dt_match[] = {
998 { .compatible = "ite,it66121" },
999 { }
1000};
1001MODULE_DEVICE_TABLE(of, it66121_dt_match);
1002
1003static const struct i2c_device_id it66121_id[] = {
1004 { "it66121", 0 },
1005 { }
1006};
1007MODULE_DEVICE_TABLE(i2c, it66121_id);
1008
1009static struct i2c_driver it66121_driver = {
1010 .driver = {
1011 .name = "it66121",
1012 .of_match_table = it66121_dt_match,
1013 },
1014 .probe = it66121_probe,
1015 .remove = it66121_remove,
1016 .id_table = it66121_id,
1017};
1018
1019module_i2c_driver(it66121_driver);
1020
1021MODULE_AUTHOR("Phong LE");
1022MODULE_DESCRIPTION("IT66121 HDMI transmitter driver");
1023MODULE_LICENSE("GPL v2");
1024
