linux/drivers/gpu/drm/bridge/tc358767.c
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   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * tc358767 eDP bridge driver
   4 *
   5 * Copyright (C) 2016 CogentEmbedded Inc
   6 * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
   7 *
   8 * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
   9 *
  10 * Copyright (C) 2016 Zodiac Inflight Innovations
  11 *
  12 * Initially based on: drivers/gpu/drm/i2c/tda998x_drv.c
  13 *
  14 * Copyright (C) 2012 Texas Instruments
  15 * Author: Rob Clark <robdclark@gmail.com>
  16 */
  17
  18#include <linux/bitfield.h>
  19#include <linux/clk.h>
  20#include <linux/device.h>
  21#include <linux/gpio/consumer.h>
  22#include <linux/i2c.h>
  23#include <linux/kernel.h>
  24#include <linux/module.h>
  25#include <linux/regmap.h>
  26#include <linux/slab.h>
  27
  28#include <drm/drm_atomic_helper.h>
  29#include <drm/drm_dp_helper.h>
  30#include <drm/drm_edid.h>
  31#include <drm/drm_of.h>
  32#include <drm/drm_panel.h>
  33#include <drm/drm_probe_helper.h>
  34
  35/* Registers */
  36
  37/* Display Parallel Interface */
  38#define DPIPXLFMT               0x0440
  39#define VS_POL_ACTIVE_LOW               (1 << 10)
  40#define HS_POL_ACTIVE_LOW               (1 << 9)
  41#define DE_POL_ACTIVE_HIGH              (0 << 8)
  42#define SUB_CFG_TYPE_CONFIG1            (0 << 2) /* LSB aligned */
  43#define SUB_CFG_TYPE_CONFIG2            (1 << 2) /* Loosely Packed */
  44#define SUB_CFG_TYPE_CONFIG3            (2 << 2) /* LSB aligned 8-bit */
  45#define DPI_BPP_RGB888                  (0 << 0)
  46#define DPI_BPP_RGB666                  (1 << 0)
  47#define DPI_BPP_RGB565                  (2 << 0)
  48
  49/* Video Path */
  50#define VPCTRL0                 0x0450
  51#define VSDELAY                 GENMASK(31, 20)
  52#define OPXLFMT_RGB666                  (0 << 8)
  53#define OPXLFMT_RGB888                  (1 << 8)
  54#define FRMSYNC_DISABLED                (0 << 4) /* Video Timing Gen Disabled */
  55#define FRMSYNC_ENABLED                 (1 << 4) /* Video Timing Gen Enabled */
  56#define MSF_DISABLED                    (0 << 0) /* Magic Square FRC disabled */
  57#define MSF_ENABLED                     (1 << 0) /* Magic Square FRC enabled */
  58#define HTIM01                  0x0454
  59#define HPW                     GENMASK(8, 0)
  60#define HBPR                    GENMASK(24, 16)
  61#define HTIM02                  0x0458
  62#define HDISPR                  GENMASK(10, 0)
  63#define HFPR                    GENMASK(24, 16)
  64#define VTIM01                  0x045c
  65#define VSPR                    GENMASK(7, 0)
  66#define VBPR                    GENMASK(23, 16)
  67#define VTIM02                  0x0460
  68#define VFPR                    GENMASK(23, 16)
  69#define VDISPR                  GENMASK(10, 0)
  70#define VFUEN0                  0x0464
  71#define VFUEN                           BIT(0)   /* Video Frame Timing Upload */
  72
  73/* System */
  74#define TC_IDREG                0x0500
  75#define SYSSTAT                 0x0508
  76#define SYSCTRL                 0x0510
  77#define DP0_AUDSRC_NO_INPUT             (0 << 3)
  78#define DP0_AUDSRC_I2S_RX               (1 << 3)
  79#define DP0_VIDSRC_NO_INPUT             (0 << 0)
  80#define DP0_VIDSRC_DSI_RX               (1 << 0)
  81#define DP0_VIDSRC_DPI_RX               (2 << 0)
  82#define DP0_VIDSRC_COLOR_BAR            (3 << 0)
  83#define SYSRSTENB               0x050c
  84#define ENBI2C                          (1 << 0)
  85#define ENBLCD0                         (1 << 2)
  86#define ENBBM                           (1 << 3)
  87#define ENBDSIRX                        (1 << 4)
  88#define ENBREG                          (1 << 5)
  89#define ENBHDCP                         (1 << 8)
  90#define GPIOM                   0x0540
  91#define GPIOC                   0x0544
  92#define GPIOO                   0x0548
  93#define GPIOI                   0x054c
  94#define INTCTL_G                0x0560
  95#define INTSTS_G                0x0564
  96
  97#define INT_SYSERR              BIT(16)
  98#define INT_GPIO_H(x)           (1 << (x == 0 ? 2 : 10))
  99#define INT_GPIO_LC(x)          (1 << (x == 0 ? 3 : 11))
 100
 101#define INT_GP0_LCNT            0x0584
 102#define INT_GP1_LCNT            0x0588
 103
 104/* Control */
 105#define DP0CTL                  0x0600
 106#define VID_MN_GEN                      BIT(6)   /* Auto-generate M/N values */
 107#define EF_EN                           BIT(5)   /* Enable Enhanced Framing */
 108#define VID_EN                          BIT(1)   /* Video transmission enable */
 109#define DP_EN                           BIT(0)   /* Enable DPTX function */
 110
 111/* Clocks */
 112#define DP0_VIDMNGEN0           0x0610
 113#define DP0_VIDMNGEN1           0x0614
 114#define DP0_VMNGENSTATUS        0x0618
 115
 116/* Main Channel */
 117#define DP0_SECSAMPLE           0x0640
 118#define DP0_VIDSYNCDELAY        0x0644
 119#define VID_SYNC_DLY            GENMASK(15, 0)
 120#define THRESH_DLY              GENMASK(31, 16)
 121
 122#define DP0_TOTALVAL            0x0648
 123#define H_TOTAL                 GENMASK(15, 0)
 124#define V_TOTAL                 GENMASK(31, 16)
 125#define DP0_STARTVAL            0x064c
 126#define H_START                 GENMASK(15, 0)
 127#define V_START                 GENMASK(31, 16)
 128#define DP0_ACTIVEVAL           0x0650
 129#define H_ACT                   GENMASK(15, 0)
 130#define V_ACT                   GENMASK(31, 16)
 131
 132#define DP0_SYNCVAL             0x0654
 133#define VS_WIDTH                GENMASK(30, 16)
 134#define HS_WIDTH                GENMASK(14, 0)
 135#define SYNCVAL_HS_POL_ACTIVE_LOW       (1 << 15)
 136#define SYNCVAL_VS_POL_ACTIVE_LOW       (1 << 31)
 137#define DP0_MISC                0x0658
 138#define TU_SIZE_RECOMMENDED             (63) /* LSCLK cycles per TU */
 139#define MAX_TU_SYMBOL           GENMASK(28, 23)
 140#define TU_SIZE                 GENMASK(21, 16)
 141#define BPC_6                           (0 << 5)
 142#define BPC_8                           (1 << 5)
 143
 144/* AUX channel */
 145#define DP0_AUXCFG0             0x0660
 146#define DP0_AUXCFG0_BSIZE       GENMASK(11, 8)
 147#define DP0_AUXCFG0_ADDR_ONLY   BIT(4)
 148#define DP0_AUXCFG1             0x0664
 149#define AUX_RX_FILTER_EN                BIT(16)
 150
 151#define DP0_AUXADDR             0x0668
 152#define DP0_AUXWDATA(i)         (0x066c + (i) * 4)
 153#define DP0_AUXRDATA(i)         (0x067c + (i) * 4)
 154#define DP0_AUXSTATUS           0x068c
 155#define AUX_BYTES               GENMASK(15, 8)
 156#define AUX_STATUS              GENMASK(7, 4)
 157#define AUX_TIMEOUT             BIT(1)
 158#define AUX_BUSY                BIT(0)
 159#define DP0_AUXI2CADR           0x0698
 160
 161/* Link Training */
 162#define DP0_SRCCTRL             0x06a0
 163#define DP0_SRCCTRL_SCRMBLDIS           BIT(13)
 164#define DP0_SRCCTRL_EN810B              BIT(12)
 165#define DP0_SRCCTRL_NOTP                (0 << 8)
 166#define DP0_SRCCTRL_TP1                 (1 << 8)
 167#define DP0_SRCCTRL_TP2                 (2 << 8)
 168#define DP0_SRCCTRL_LANESKEW            BIT(7)
 169#define DP0_SRCCTRL_SSCG                BIT(3)
 170#define DP0_SRCCTRL_LANES_1             (0 << 2)
 171#define DP0_SRCCTRL_LANES_2             (1 << 2)
 172#define DP0_SRCCTRL_BW27                (1 << 1)
 173#define DP0_SRCCTRL_BW162               (0 << 1)
 174#define DP0_SRCCTRL_AUTOCORRECT         BIT(0)
 175#define DP0_LTSTAT              0x06d0
 176#define LT_LOOPDONE                     BIT(13)
 177#define LT_STATUS_MASK                  (0x1f << 8)
 178#define LT_CHANNEL1_EQ_BITS             (DP_CHANNEL_EQ_BITS << 4)
 179#define LT_INTERLANE_ALIGN_DONE         BIT(3)
 180#define LT_CHANNEL0_EQ_BITS             (DP_CHANNEL_EQ_BITS)
 181#define DP0_SNKLTCHGREQ         0x06d4
 182#define DP0_LTLOOPCTRL          0x06d8
 183#define DP0_SNKLTCTRL           0x06e4
 184
 185#define DP1_SRCCTRL             0x07a0
 186
 187/* PHY */
 188#define DP_PHY_CTRL             0x0800
 189#define DP_PHY_RST                      BIT(28)  /* DP PHY Global Soft Reset */
 190#define BGREN                           BIT(25)  /* AUX PHY BGR Enable */
 191#define PWR_SW_EN                       BIT(24)  /* PHY Power Switch Enable */
 192#define PHY_M1_RST                      BIT(12)  /* Reset PHY1 Main Channel */
 193#define PHY_RDY                         BIT(16)  /* PHY Main Channels Ready */
 194#define PHY_M0_RST                      BIT(8)   /* Reset PHY0 Main Channel */
 195#define PHY_2LANE                       BIT(2)   /* PHY Enable 2 lanes */
 196#define PHY_A0_EN                       BIT(1)   /* PHY Aux Channel0 Enable */
 197#define PHY_M0_EN                       BIT(0)   /* PHY Main Channel0 Enable */
 198
 199/* PLL */
 200#define DP0_PLLCTRL             0x0900
 201#define DP1_PLLCTRL             0x0904  /* not defined in DS */
 202#define PXL_PLLCTRL             0x0908
 203#define PLLUPDATE                       BIT(2)
 204#define PLLBYP                          BIT(1)
 205#define PLLEN                           BIT(0)
 206#define PXL_PLLPARAM            0x0914
 207#define IN_SEL_REFCLK                   (0 << 14)
 208#define SYS_PLLPARAM            0x0918
 209#define REF_FREQ_38M4                   (0 << 8) /* 38.4 MHz */
 210#define REF_FREQ_19M2                   (1 << 8) /* 19.2 MHz */
 211#define REF_FREQ_26M                    (2 << 8) /* 26 MHz */
 212#define REF_FREQ_13M                    (3 << 8) /* 13 MHz */
 213#define SYSCLK_SEL_LSCLK                (0 << 4)
 214#define LSCLK_DIV_1                     (0 << 0)
 215#define LSCLK_DIV_2                     (1 << 0)
 216
 217/* Test & Debug */
 218#define TSTCTL                  0x0a00
 219#define COLOR_R                 GENMASK(31, 24)
 220#define COLOR_G                 GENMASK(23, 16)
 221#define COLOR_B                 GENMASK(15, 8)
 222#define ENI2CFILTER             BIT(4)
 223#define COLOR_BAR_MODE          GENMASK(1, 0)
 224#define COLOR_BAR_MODE_BARS     2
 225#define PLL_DBG                 0x0a04
 226
 227static bool tc_test_pattern;
 228module_param_named(test, tc_test_pattern, bool, 0644);
 229
 230struct tc_edp_link {
 231        struct drm_dp_link      base;
 232        u8                      assr;
 233        bool                    scrambler_dis;
 234        bool                    spread;
 235};
 236
 237struct tc_data {
 238        struct device           *dev;
 239        struct regmap           *regmap;
 240        struct drm_dp_aux       aux;
 241
 242        struct drm_bridge       bridge;
 243        struct drm_connector    connector;
 244        struct drm_panel        *panel;
 245
 246        /* link settings */
 247        struct tc_edp_link      link;
 248
 249        /* display edid */
 250        struct edid             *edid;
 251        /* current mode */
 252        struct drm_display_mode mode;
 253
 254        u32                     rev;
 255        u8                      assr;
 256
 257        struct gpio_desc        *sd_gpio;
 258        struct gpio_desc        *reset_gpio;
 259        struct clk              *refclk;
 260
 261        /* do we have IRQ */
 262        bool                    have_irq;
 263
 264        /* HPD pin number (0 or 1) or -ENODEV */
 265        int                     hpd_pin;
 266};
 267
 268static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a)
 269{
 270        return container_of(a, struct tc_data, aux);
 271}
 272
 273static inline struct tc_data *bridge_to_tc(struct drm_bridge *b)
 274{
 275        return container_of(b, struct tc_data, bridge);
 276}
 277
 278static inline struct tc_data *connector_to_tc(struct drm_connector *c)
 279{
 280        return container_of(c, struct tc_data, connector);
 281}
 282
 283static inline int tc_poll_timeout(struct tc_data *tc, unsigned int addr,
 284                                  unsigned int cond_mask,
 285                                  unsigned int cond_value,
 286                                  unsigned long sleep_us, u64 timeout_us)
 287{
 288        unsigned int val;
 289
 290        return regmap_read_poll_timeout(tc->regmap, addr, val,
 291                                        (val & cond_mask) == cond_value,
 292                                        sleep_us, timeout_us);
 293}
 294
 295static int tc_aux_wait_busy(struct tc_data *tc)
 296{
 297        return tc_poll_timeout(tc, DP0_AUXSTATUS, AUX_BUSY, 0, 1000, 100000);
 298}
 299
 300static int tc_aux_write_data(struct tc_data *tc, const void *data,
 301                             size_t size)
 302{
 303        u32 auxwdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)] = { 0 };
 304        int ret, count = ALIGN(size, sizeof(u32));
 305
 306        memcpy(auxwdata, data, size);
 307
 308        ret = regmap_raw_write(tc->regmap, DP0_AUXWDATA(0), auxwdata, count);
 309        if (ret)
 310                return ret;
 311
 312        return size;
 313}
 314
 315static int tc_aux_read_data(struct tc_data *tc, void *data, size_t size)
 316{
 317        u32 auxrdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)];
 318        int ret, count = ALIGN(size, sizeof(u32));
 319
 320        ret = regmap_raw_read(tc->regmap, DP0_AUXRDATA(0), auxrdata, count);
 321        if (ret)
 322                return ret;
 323
 324        memcpy(data, auxrdata, size);
 325
 326        return size;
 327}
 328
 329static u32 tc_auxcfg0(struct drm_dp_aux_msg *msg, size_t size)
 330{
 331        u32 auxcfg0 = msg->request;
 332
 333        if (size)
 334                auxcfg0 |= FIELD_PREP(DP0_AUXCFG0_BSIZE, size - 1);
 335        else
 336                auxcfg0 |= DP0_AUXCFG0_ADDR_ONLY;
 337
 338        return auxcfg0;
 339}
 340
 341static ssize_t tc_aux_transfer(struct drm_dp_aux *aux,
 342                               struct drm_dp_aux_msg *msg)
 343{
 344        struct tc_data *tc = aux_to_tc(aux);
 345        size_t size = min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES - 1, msg->size);
 346        u8 request = msg->request & ~DP_AUX_I2C_MOT;
 347        u32 auxstatus;
 348        int ret;
 349
 350        ret = tc_aux_wait_busy(tc);
 351        if (ret)
 352                return ret;
 353
 354        switch (request) {
 355        case DP_AUX_NATIVE_READ:
 356        case DP_AUX_I2C_READ:
 357                break;
 358        case DP_AUX_NATIVE_WRITE:
 359        case DP_AUX_I2C_WRITE:
 360                if (size) {
 361                        ret = tc_aux_write_data(tc, msg->buffer, size);
 362                        if (ret < 0)
 363                                return ret;
 364                }
 365                break;
 366        default:
 367                return -EINVAL;
 368        }
 369
 370        /* Store address */
 371        ret = regmap_write(tc->regmap, DP0_AUXADDR, msg->address);
 372        if (ret)
 373                return ret;
 374        /* Start transfer */
 375        ret = regmap_write(tc->regmap, DP0_AUXCFG0, tc_auxcfg0(msg, size));
 376        if (ret)
 377                return ret;
 378
 379        ret = tc_aux_wait_busy(tc);
 380        if (ret)
 381                return ret;
 382
 383        ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &auxstatus);
 384        if (ret)
 385                return ret;
 386
 387        if (auxstatus & AUX_TIMEOUT)
 388                return -ETIMEDOUT;
 389        /*
 390         * For some reason address-only DP_AUX_I2C_WRITE (MOT), still
 391         * reports 1 byte transferred in its status. To deal we that
 392         * we ignore aux_bytes field if we know that this was an
 393         * address-only transfer
 394         */
 395        if (size)
 396                size = FIELD_GET(AUX_BYTES, auxstatus);
 397        msg->reply = FIELD_GET(AUX_STATUS, auxstatus);
 398
 399        switch (request) {
 400        case DP_AUX_NATIVE_READ:
 401        case DP_AUX_I2C_READ:
 402                if (size)
 403                        return tc_aux_read_data(tc, msg->buffer, size);
 404                break;
 405        }
 406
 407        return size;
 408}
 409
 410static const char * const training_pattern1_errors[] = {
 411        "No errors",
 412        "Aux write error",
 413        "Aux read error",
 414        "Max voltage reached error",
 415        "Loop counter expired error",
 416        "res", "res", "res"
 417};
 418
 419static const char * const training_pattern2_errors[] = {
 420        "No errors",
 421        "Aux write error",
 422        "Aux read error",
 423        "Clock recovery failed error",
 424        "Loop counter expired error",
 425        "res", "res", "res"
 426};
 427
 428static u32 tc_srcctrl(struct tc_data *tc)
 429{
 430        /*
 431         * No training pattern, skew lane 1 data by two LSCLK cycles with
 432         * respect to lane 0 data, AutoCorrect Mode = 0
 433         */
 434        u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_EN810B;
 435
 436        if (tc->link.scrambler_dis)
 437                reg |= DP0_SRCCTRL_SCRMBLDIS;   /* Scrambler Disabled */
 438        if (tc->link.spread)
 439                reg |= DP0_SRCCTRL_SSCG;        /* Spread Spectrum Enable */
 440        if (tc->link.base.num_lanes == 2)
 441                reg |= DP0_SRCCTRL_LANES_2;     /* Two Main Channel Lanes */
 442        if (tc->link.base.rate != 162000)
 443                reg |= DP0_SRCCTRL_BW27;        /* 2.7 Gbps link */
 444        return reg;
 445}
 446
 447static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl)
 448{
 449        int ret;
 450
 451        ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN);
 452        if (ret)
 453                return ret;
 454
 455        /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */
 456        usleep_range(3000, 6000);
 457
 458        return 0;
 459}
 460
 461static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
 462{
 463        int ret;
 464        int i_pre, best_pre = 1;
 465        int i_post, best_post = 1;
 466        int div, best_div = 1;
 467        int mul, best_mul = 1;
 468        int delta, best_delta;
 469        int ext_div[] = {1, 2, 3, 5, 7};
 470        int best_pixelclock = 0;
 471        int vco_hi = 0;
 472        u32 pxl_pllparam;
 473
 474        dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock,
 475                refclk);
 476        best_delta = pixelclock;
 477        /* Loop over all possible ext_divs, skipping invalid configurations */
 478        for (i_pre = 0; i_pre < ARRAY_SIZE(ext_div); i_pre++) {
 479                /*
 480                 * refclk / ext_pre_div should be in the 1 to 200 MHz range.
 481                 * We don't allow any refclk > 200 MHz, only check lower bounds.
 482                 */
 483                if (refclk / ext_div[i_pre] < 1000000)
 484                        continue;
 485                for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) {
 486                        for (div = 1; div <= 16; div++) {
 487                                u32 clk;
 488                                u64 tmp;
 489
 490                                tmp = pixelclock * ext_div[i_pre] *
 491                                      ext_div[i_post] * div;
 492                                do_div(tmp, refclk);
 493                                mul = tmp;
 494
 495                                /* Check limits */
 496                                if ((mul < 1) || (mul > 128))
 497                                        continue;
 498
 499                                clk = (refclk / ext_div[i_pre] / div) * mul;
 500                                /*
 501                                 * refclk * mul / (ext_pre_div * pre_div)
 502                                 * should be in the 150 to 650 MHz range
 503                                 */
 504                                if ((clk > 650000000) || (clk < 150000000))
 505                                        continue;
 506
 507                                clk = clk / ext_div[i_post];
 508                                delta = clk - pixelclock;
 509
 510                                if (abs(delta) < abs(best_delta)) {
 511                                        best_pre = i_pre;
 512                                        best_post = i_post;
 513                                        best_div = div;
 514                                        best_mul = mul;
 515                                        best_delta = delta;
 516                                        best_pixelclock = clk;
 517                                }
 518                        }
 519                }
 520        }
 521        if (best_pixelclock == 0) {
 522                dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n",
 523                        pixelclock);
 524                return -EINVAL;
 525        }
 526
 527        dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock,
 528                best_delta);
 529        dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk,
 530                ext_div[best_pre], best_div, best_mul, ext_div[best_post]);
 531
 532        /* if VCO >= 300 MHz */
 533        if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000)
 534                vco_hi = 1;
 535        /* see DS */
 536        if (best_div == 16)
 537                best_div = 0;
 538        if (best_mul == 128)
 539                best_mul = 0;
 540
 541        /* Power up PLL and switch to bypass */
 542        ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN);
 543        if (ret)
 544                return ret;
 545
 546        pxl_pllparam  = vco_hi << 24; /* For PLL VCO >= 300 MHz = 1 */
 547        pxl_pllparam |= ext_div[best_pre] << 20; /* External Pre-divider */
 548        pxl_pllparam |= ext_div[best_post] << 16; /* External Post-divider */
 549        pxl_pllparam |= IN_SEL_REFCLK; /* Use RefClk as PLL input */
 550        pxl_pllparam |= best_div << 8; /* Divider for PLL RefClk */
 551        pxl_pllparam |= best_mul; /* Multiplier for PLL */
 552
 553        ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam);
 554        if (ret)
 555                return ret;
 556
 557        /* Force PLL parameter update and disable bypass */
 558        return tc_pllupdate(tc, PXL_PLLCTRL);
 559}
 560
 561static int tc_pxl_pll_dis(struct tc_data *tc)
 562{
 563        /* Enable PLL bypass, power down PLL */
 564        return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP);
 565}
 566
 567static int tc_stream_clock_calc(struct tc_data *tc)
 568{
 569        /*
 570         * If the Stream clock and Link Symbol clock are
 571         * asynchronous with each other, the value of M changes over
 572         * time. This way of generating link clock and stream
 573         * clock is called Asynchronous Clock mode. The value M
 574         * must change while the value N stays constant. The
 575         * value of N in this Asynchronous Clock mode must be set
 576         * to 2^15 or 32,768.
 577         *
 578         * LSCLK = 1/10 of high speed link clock
 579         *
 580         * f_STRMCLK = M/N * f_LSCLK
 581         * M/N = f_STRMCLK / f_LSCLK
 582         *
 583         */
 584        return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768);
 585}
 586
 587static int tc_set_syspllparam(struct tc_data *tc)
 588{
 589        unsigned long rate;
 590        u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
 591
 592        rate = clk_get_rate(tc->refclk);
 593        switch (rate) {
 594        case 38400000:
 595                pllparam |= REF_FREQ_38M4;
 596                break;
 597        case 26000000:
 598                pllparam |= REF_FREQ_26M;
 599                break;
 600        case 19200000:
 601                pllparam |= REF_FREQ_19M2;
 602                break;
 603        case 13000000:
 604                pllparam |= REF_FREQ_13M;
 605                break;
 606        default:
 607                dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
 608                return -EINVAL;
 609        }
 610
 611        return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam);
 612}
 613
 614static int tc_aux_link_setup(struct tc_data *tc)
 615{
 616        int ret;
 617        u32 dp0_auxcfg1;
 618
 619        /* Setup DP-PHY / PLL */
 620        ret = tc_set_syspllparam(tc);
 621        if (ret)
 622                goto err;
 623
 624        ret = regmap_write(tc->regmap, DP_PHY_CTRL,
 625                           BGREN | PWR_SW_EN | PHY_A0_EN);
 626        if (ret)
 627                goto err;
 628        /*
 629         * Initially PLLs are in bypass. Force PLL parameter update,
 630         * disable PLL bypass, enable PLL
 631         */
 632        ret = tc_pllupdate(tc, DP0_PLLCTRL);
 633        if (ret)
 634                goto err;
 635
 636        ret = tc_pllupdate(tc, DP1_PLLCTRL);
 637        if (ret)
 638                goto err;
 639
 640        ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1, 1000);
 641        if (ret == -ETIMEDOUT) {
 642                dev_err(tc->dev, "Timeout waiting for PHY to become ready");
 643                return ret;
 644        } else if (ret) {
 645                goto err;
 646        }
 647
 648        /* Setup AUX link */
 649        dp0_auxcfg1  = AUX_RX_FILTER_EN;
 650        dp0_auxcfg1 |= 0x06 << 8; /* Aux Bit Period Calculator Threshold */
 651        dp0_auxcfg1 |= 0x3f << 0; /* Aux Response Timeout Timer */
 652
 653        ret = regmap_write(tc->regmap, DP0_AUXCFG1, dp0_auxcfg1);
 654        if (ret)
 655                goto err;
 656
 657        return 0;
 658err:
 659        dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret);
 660        return ret;
 661}
 662
 663static int tc_get_display_props(struct tc_data *tc)
 664{
 665        int ret;
 666        u8 reg;
 667
 668        /* Read DP Rx Link Capability */
 669        ret = drm_dp_link_probe(&tc->aux, &tc->link.base);
 670        if (ret < 0)
 671                goto err_dpcd_read;
 672        if (tc->link.base.rate != 162000 && tc->link.base.rate != 270000) {
 673                dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n");
 674                tc->link.base.rate = 270000;
 675        }
 676
 677        if (tc->link.base.num_lanes > 2) {
 678                dev_dbg(tc->dev, "Falling to 2 lanes\n");
 679                tc->link.base.num_lanes = 2;
 680        }
 681
 682        ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, &reg);
 683        if (ret < 0)
 684                goto err_dpcd_read;
 685        tc->link.spread = reg & DP_MAX_DOWNSPREAD_0_5;
 686
 687        ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, &reg);
 688        if (ret < 0)
 689                goto err_dpcd_read;
 690
 691        tc->link.scrambler_dis = false;
 692        /* read assr */
 693        ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, &reg);
 694        if (ret < 0)
 695                goto err_dpcd_read;
 696        tc->link.assr = reg & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
 697
 698        dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n",
 699                tc->link.base.revision >> 4, tc->link.base.revision & 0x0f,
 700                (tc->link.base.rate == 162000) ? "1.62Gbps" : "2.7Gbps",
 701                tc->link.base.num_lanes,
 702                (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) ?
 703                "enhanced" : "non-enhanced");
 704        dev_dbg(tc->dev, "Downspread: %s, scrambler: %s\n",
 705                tc->link.spread ? "0.5%" : "0.0%",
 706                tc->link.scrambler_dis ? "disabled" : "enabled");
 707        dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n",
 708                tc->link.assr, tc->assr);
 709
 710        return 0;
 711
 712err_dpcd_read:
 713        dev_err(tc->dev, "failed to read DPCD: %d\n", ret);
 714        return ret;
 715}
 716
 717static int tc_set_video_mode(struct tc_data *tc,
 718                             const struct drm_display_mode *mode)
 719{
 720        int ret;
 721        int vid_sync_dly;
 722        int max_tu_symbol;
 723
 724        int left_margin = mode->htotal - mode->hsync_end;
 725        int right_margin = mode->hsync_start - mode->hdisplay;
 726        int hsync_len = mode->hsync_end - mode->hsync_start;
 727        int upper_margin = mode->vtotal - mode->vsync_end;
 728        int lower_margin = mode->vsync_start - mode->vdisplay;
 729        int vsync_len = mode->vsync_end - mode->vsync_start;
 730        u32 dp0_syncval;
 731        u32 bits_per_pixel = 24;
 732        u32 in_bw, out_bw;
 733
 734        /*
 735         * Recommended maximum number of symbols transferred in a transfer unit:
 736         * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size,
 737         *              (output active video bandwidth in bytes))
 738         * Must be less than tu_size.
 739         */
 740
 741        in_bw = mode->clock * bits_per_pixel / 8;
 742        out_bw = tc->link.base.num_lanes * tc->link.base.rate;
 743        max_tu_symbol = DIV_ROUND_UP(in_bw * TU_SIZE_RECOMMENDED, out_bw);
 744
 745        dev_dbg(tc->dev, "set mode %dx%d\n",
 746                mode->hdisplay, mode->vdisplay);
 747        dev_dbg(tc->dev, "H margin %d,%d sync %d\n",
 748                left_margin, right_margin, hsync_len);
 749        dev_dbg(tc->dev, "V margin %d,%d sync %d\n",
 750                upper_margin, lower_margin, vsync_len);
 751        dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal);
 752
 753
 754        /*
 755         * LCD Ctl Frame Size
 756         * datasheet is not clear of vsdelay in case of DPI
 757         * assume we do not need any delay when DPI is a source of
 758         * sync signals
 759         */
 760        ret = regmap_write(tc->regmap, VPCTRL0,
 761                           FIELD_PREP(VSDELAY, 0) |
 762                           OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED);
 763        if (ret)
 764                return ret;
 765
 766        ret = regmap_write(tc->regmap, HTIM01,
 767                           FIELD_PREP(HBPR, ALIGN(left_margin, 2)) |
 768                           FIELD_PREP(HPW, ALIGN(hsync_len, 2)));
 769        if (ret)
 770                return ret;
 771
 772        ret = regmap_write(tc->regmap, HTIM02,
 773                           FIELD_PREP(HDISPR, ALIGN(mode->hdisplay, 2)) |
 774                           FIELD_PREP(HFPR, ALIGN(right_margin, 2)));
 775        if (ret)
 776                return ret;
 777
 778        ret = regmap_write(tc->regmap, VTIM01,
 779                           FIELD_PREP(VBPR, upper_margin) |
 780                           FIELD_PREP(VSPR, vsync_len));
 781        if (ret)
 782                return ret;
 783
 784        ret = regmap_write(tc->regmap, VTIM02,
 785                           FIELD_PREP(VFPR, lower_margin) |
 786                           FIELD_PREP(VDISPR, mode->vdisplay));
 787        if (ret)
 788                return ret;
 789
 790        ret = regmap_write(tc->regmap, VFUEN0, VFUEN); /* update settings */
 791        if (ret)
 792                return ret;
 793
 794        /* Test pattern settings */
 795        ret = regmap_write(tc->regmap, TSTCTL,
 796                           FIELD_PREP(COLOR_R, 120) |
 797                           FIELD_PREP(COLOR_G, 20) |
 798                           FIELD_PREP(COLOR_B, 99) |
 799                           ENI2CFILTER |
 800                           FIELD_PREP(COLOR_BAR_MODE, COLOR_BAR_MODE_BARS));
 801        if (ret)
 802                return ret;
 803
 804        /* DP Main Stream Attributes */
 805        vid_sync_dly = hsync_len + left_margin + mode->hdisplay;
 806        ret = regmap_write(tc->regmap, DP0_VIDSYNCDELAY,
 807                 FIELD_PREP(THRESH_DLY, max_tu_symbol) |
 808                 FIELD_PREP(VID_SYNC_DLY, vid_sync_dly));
 809
 810        ret = regmap_write(tc->regmap, DP0_TOTALVAL,
 811                           FIELD_PREP(H_TOTAL, mode->htotal) |
 812                           FIELD_PREP(V_TOTAL, mode->vtotal));
 813        if (ret)
 814                return ret;
 815
 816        ret = regmap_write(tc->regmap, DP0_STARTVAL,
 817                           FIELD_PREP(H_START, left_margin + hsync_len) |
 818                           FIELD_PREP(V_START, upper_margin + vsync_len));
 819        if (ret)
 820                return ret;
 821
 822        ret = regmap_write(tc->regmap, DP0_ACTIVEVAL,
 823                           FIELD_PREP(V_ACT, mode->vdisplay) |
 824                           FIELD_PREP(H_ACT, mode->hdisplay));
 825        if (ret)
 826                return ret;
 827
 828        dp0_syncval = FIELD_PREP(VS_WIDTH, vsync_len) |
 829                      FIELD_PREP(HS_WIDTH, hsync_len);
 830
 831        if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 832                dp0_syncval |= SYNCVAL_VS_POL_ACTIVE_LOW;
 833
 834        if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 835                dp0_syncval |= SYNCVAL_HS_POL_ACTIVE_LOW;
 836
 837        ret = regmap_write(tc->regmap, DP0_SYNCVAL, dp0_syncval);
 838        if (ret)
 839                return ret;
 840
 841        ret = regmap_write(tc->regmap, DPIPXLFMT,
 842                           VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW |
 843                           DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 |
 844                           DPI_BPP_RGB888);
 845        if (ret)
 846                return ret;
 847
 848        ret = regmap_write(tc->regmap, DP0_MISC,
 849                           FIELD_PREP(MAX_TU_SYMBOL, max_tu_symbol) |
 850                           FIELD_PREP(TU_SIZE, TU_SIZE_RECOMMENDED) |
 851                           BPC_8);
 852        if (ret)
 853                return ret;
 854
 855        return 0;
 856}
 857
 858static int tc_wait_link_training(struct tc_data *tc)
 859{
 860        u32 value;
 861        int ret;
 862
 863        ret = tc_poll_timeout(tc, DP0_LTSTAT, LT_LOOPDONE,
 864                              LT_LOOPDONE, 1, 1000);
 865        if (ret) {
 866                dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n");
 867                return ret;
 868        }
 869
 870        ret = regmap_read(tc->regmap, DP0_LTSTAT, &value);
 871        if (ret)
 872                return ret;
 873
 874        return (value >> 8) & 0x7;
 875}
 876
 877static int tc_main_link_enable(struct tc_data *tc)
 878{
 879        struct drm_dp_aux *aux = &tc->aux;
 880        struct device *dev = tc->dev;
 881        u32 dp_phy_ctrl;
 882        u32 value;
 883        int ret;
 884        u8 tmp[DP_LINK_STATUS_SIZE];
 885
 886        dev_dbg(tc->dev, "link enable\n");
 887
 888        ret = regmap_read(tc->regmap, DP0CTL, &value);
 889        if (ret)
 890                return ret;
 891
 892        if (WARN_ON(value & DP_EN)) {
 893                ret = regmap_write(tc->regmap, DP0CTL, 0);
 894                if (ret)
 895                        return ret;
 896        }
 897
 898        ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc));
 899        if (ret)
 900                return ret;
 901        /* SSCG and BW27 on DP1 must be set to the same as on DP0 */
 902        ret = regmap_write(tc->regmap, DP1_SRCCTRL,
 903                 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) |
 904                 ((tc->link.base.rate != 162000) ? DP0_SRCCTRL_BW27 : 0));
 905        if (ret)
 906                return ret;
 907
 908        ret = tc_set_syspllparam(tc);
 909        if (ret)
 910                return ret;
 911
 912        /* Setup Main Link */
 913        dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN;
 914        if (tc->link.base.num_lanes == 2)
 915                dp_phy_ctrl |= PHY_2LANE;
 916
 917        ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
 918        if (ret)
 919                return ret;
 920
 921        /* PLL setup */
 922        ret = tc_pllupdate(tc, DP0_PLLCTRL);
 923        if (ret)
 924                return ret;
 925
 926        ret = tc_pllupdate(tc, DP1_PLLCTRL);
 927        if (ret)
 928                return ret;
 929
 930        /* Reset/Enable Main Links */
 931        dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST;
 932        ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
 933        usleep_range(100, 200);
 934        dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST);
 935        ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
 936
 937        ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1, 1000);
 938        if (ret) {
 939                dev_err(dev, "timeout waiting for phy become ready");
 940                return ret;
 941        }
 942
 943        /* Set misc: 8 bits per color */
 944        ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8);
 945        if (ret)
 946                return ret;
 947
 948        /*
 949         * ASSR mode
 950         * on TC358767 side ASSR configured through strap pin
 951         * seems there is no way to change this setting from SW
 952         *
 953         * check is tc configured for same mode
 954         */
 955        if (tc->assr != tc->link.assr) {
 956                dev_dbg(dev, "Trying to set display to ASSR: %d\n",
 957                        tc->assr);
 958                /* try to set ASSR on display side */
 959                tmp[0] = tc->assr;
 960                ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]);
 961                if (ret < 0)
 962                        goto err_dpcd_read;
 963                /* read back */
 964                ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp);
 965                if (ret < 0)
 966                        goto err_dpcd_read;
 967
 968                if (tmp[0] != tc->assr) {
 969                        dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n",
 970                                tc->assr);
 971                        /* trying with disabled scrambler */
 972                        tc->link.scrambler_dis = true;
 973                }
 974        }
 975
 976        /* Setup Link & DPRx Config for Training */
 977        ret = drm_dp_link_configure(aux, &tc->link.base);
 978        if (ret < 0)
 979                goto err_dpcd_write;
 980
 981        /* DOWNSPREAD_CTRL */
 982        tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00;
 983        /* MAIN_LINK_CHANNEL_CODING_SET */
 984        tmp[1] =  DP_SET_ANSI_8B10B;
 985        ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2);
 986        if (ret < 0)
 987                goto err_dpcd_write;
 988
 989        /* Reset voltage-swing & pre-emphasis */
 990        tmp[0] = tmp[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 |
 991                          DP_TRAIN_PRE_EMPH_LEVEL_0;
 992        ret = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, tmp, 2);
 993        if (ret < 0)
 994                goto err_dpcd_write;
 995
 996        /* Clock-Recovery */
 997
 998        /* Set DPCD 0x102 for Training Pattern 1 */
 999        ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
1000                           DP_LINK_SCRAMBLING_DISABLE |
1001                           DP_TRAINING_PATTERN_1);
1002        if (ret)
1003                return ret;
1004
1005        ret = regmap_write(tc->regmap, DP0_LTLOOPCTRL,
1006                           (15 << 28) | /* Defer Iteration Count */
1007                           (15 << 24) | /* Loop Iteration Count */
1008                           (0xd << 0)); /* Loop Timer Delay */
1009        if (ret)
1010                return ret;
1011
1012        ret = regmap_write(tc->regmap, DP0_SRCCTRL,
1013                           tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
1014                           DP0_SRCCTRL_AUTOCORRECT |
1015                           DP0_SRCCTRL_TP1);
1016        if (ret)
1017                return ret;
1018
1019        /* Enable DP0 to start Link Training */
1020        ret = regmap_write(tc->regmap, DP0CTL,
1021                           ((tc->link.base.capabilities &
1022                             DP_LINK_CAP_ENHANCED_FRAMING) ? EF_EN : 0) |
1023                           DP_EN);
1024        if (ret)
1025                return ret;
1026
1027        /* wait */
1028
1029        ret = tc_wait_link_training(tc);
1030        if (ret < 0)
1031                return ret;
1032
1033        if (ret) {
1034                dev_err(tc->dev, "Link training phase 1 failed: %s\n",
1035                        training_pattern1_errors[ret]);
1036                return -ENODEV;
1037        }
1038
1039        /* Channel Equalization */
1040
1041        /* Set DPCD 0x102 for Training Pattern 2 */
1042        ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
1043                           DP_LINK_SCRAMBLING_DISABLE |
1044                           DP_TRAINING_PATTERN_2);
1045        if (ret)
1046                return ret;
1047
1048        ret = regmap_write(tc->regmap, DP0_SRCCTRL,
1049                           tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
1050                           DP0_SRCCTRL_AUTOCORRECT |
1051                           DP0_SRCCTRL_TP2);
1052        if (ret)
1053                return ret;
1054
1055        /* wait */
1056        ret = tc_wait_link_training(tc);
1057        if (ret < 0)
1058                return ret;
1059
1060        if (ret) {
1061                dev_err(tc->dev, "Link training phase 2 failed: %s\n",
1062                        training_pattern2_errors[ret]);
1063                return -ENODEV;
1064        }
1065
1066        /*
1067         * Toshiba's documentation suggests to first clear DPCD 0x102, then
1068         * clear the training pattern bit in DP0_SRCCTRL. Testing shows
1069         * that the link sometimes drops if those steps are done in that order,
1070         * but if the steps are done in reverse order, the link stays up.
1071         *
1072         * So we do the steps differently than documented here.
1073         */
1074
1075        /* Clear Training Pattern, set AutoCorrect Mode = 1 */
1076        ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc) |
1077                           DP0_SRCCTRL_AUTOCORRECT);
1078        if (ret)
1079                return ret;
1080
1081        /* Clear DPCD 0x102 */
1082        /* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */
1083        tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00;
1084        ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, tmp[0]);
1085        if (ret < 0)
1086                goto err_dpcd_write;
1087
1088        /* Check link status */
1089        ret = drm_dp_dpcd_read_link_status(aux, tmp);
1090        if (ret < 0)
1091                goto err_dpcd_read;
1092
1093        ret = 0;
1094
1095        value = tmp[0] & DP_CHANNEL_EQ_BITS;
1096
1097        if (value != DP_CHANNEL_EQ_BITS) {
1098                dev_err(tc->dev, "Lane 0 failed: %x\n", value);
1099                ret = -ENODEV;
1100        }
1101
1102        if (tc->link.base.num_lanes == 2) {
1103                value = (tmp[0] >> 4) & DP_CHANNEL_EQ_BITS;
1104
1105                if (value != DP_CHANNEL_EQ_BITS) {
1106                        dev_err(tc->dev, "Lane 1 failed: %x\n", value);
1107                        ret = -ENODEV;
1108                }
1109
1110                if (!(tmp[2] & DP_INTERLANE_ALIGN_DONE)) {
1111                        dev_err(tc->dev, "Interlane align failed\n");
1112                        ret = -ENODEV;
1113                }
1114        }
1115
1116        if (ret) {
1117                dev_err(dev, "0x0202 LANE0_1_STATUS:            0x%02x\n", tmp[0]);
1118                dev_err(dev, "0x0203 LANE2_3_STATUS             0x%02x\n", tmp[1]);
1119                dev_err(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n", tmp[2]);
1120                dev_err(dev, "0x0205 SINK_STATUS:               0x%02x\n", tmp[3]);
1121                dev_err(dev, "0x0206 ADJUST_REQUEST_LANE0_1:    0x%02x\n", tmp[4]);
1122                dev_err(dev, "0x0207 ADJUST_REQUEST_LANE2_3:    0x%02x\n", tmp[5]);
1123                return ret;
1124        }
1125
1126        return 0;
1127err_dpcd_read:
1128        dev_err(tc->dev, "Failed to read DPCD: %d\n", ret);
1129        return ret;
1130err_dpcd_write:
1131        dev_err(tc->dev, "Failed to write DPCD: %d\n", ret);
1132        return ret;
1133}
1134
1135static int tc_main_link_disable(struct tc_data *tc)
1136{
1137        int ret;
1138
1139        dev_dbg(tc->dev, "link disable\n");
1140
1141        ret = regmap_write(tc->regmap, DP0_SRCCTRL, 0);
1142        if (ret)
1143                return ret;
1144
1145        return regmap_write(tc->regmap, DP0CTL, 0);
1146}
1147
1148static int tc_stream_enable(struct tc_data *tc)
1149{
1150        int ret;
1151        u32 value;
1152
1153        dev_dbg(tc->dev, "enable video stream\n");
1154
1155        /* PXL PLL setup */
1156        if (tc_test_pattern) {
1157                ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
1158                                    1000 * tc->mode.clock);
1159                if (ret)
1160                        return ret;
1161        }
1162
1163        ret = tc_set_video_mode(tc, &tc->mode);
1164        if (ret)
1165                return ret;
1166
1167        /* Set M/N */
1168        ret = tc_stream_clock_calc(tc);
1169        if (ret)
1170                return ret;
1171
1172        value = VID_MN_GEN | DP_EN;
1173        if (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
1174                value |= EF_EN;
1175        ret = regmap_write(tc->regmap, DP0CTL, value);
1176        if (ret)
1177                return ret;
1178        /*
1179         * VID_EN assertion should be delayed by at least N * LSCLK
1180         * cycles from the time VID_MN_GEN is enabled in order to
1181         * generate stable values for VID_M. LSCLK is 270 MHz or
1182         * 162 MHz, VID_N is set to 32768 in  tc_stream_clock_calc(),
1183         * so a delay of at least 203 us should suffice.
1184         */
1185        usleep_range(500, 1000);
1186        value |= VID_EN;
1187        ret = regmap_write(tc->regmap, DP0CTL, value);
1188        if (ret)
1189                return ret;
1190        /* Set input interface */
1191        value = DP0_AUDSRC_NO_INPUT;
1192        if (tc_test_pattern)
1193                value |= DP0_VIDSRC_COLOR_BAR;
1194        else
1195                value |= DP0_VIDSRC_DPI_RX;
1196        ret = regmap_write(tc->regmap, SYSCTRL, value);
1197        if (ret)
1198                return ret;
1199
1200        return 0;
1201}
1202
1203static int tc_stream_disable(struct tc_data *tc)
1204{
1205        int ret;
1206
1207        dev_dbg(tc->dev, "disable video stream\n");
1208
1209        ret = regmap_update_bits(tc->regmap, DP0CTL, VID_EN, 0);
1210        if (ret)
1211                return ret;
1212
1213        tc_pxl_pll_dis(tc);
1214
1215        return 0;
1216}
1217
1218static void tc_bridge_pre_enable(struct drm_bridge *bridge)
1219{
1220        struct tc_data *tc = bridge_to_tc(bridge);
1221
1222        drm_panel_prepare(tc->panel);
1223}
1224
1225static void tc_bridge_enable(struct drm_bridge *bridge)
1226{
1227        struct tc_data *tc = bridge_to_tc(bridge);
1228        int ret;
1229
1230        ret = tc_get_display_props(tc);
1231        if (ret < 0) {
1232                dev_err(tc->dev, "failed to read display props: %d\n", ret);
1233                return;
1234        }
1235
1236        ret = tc_main_link_enable(tc);
1237        if (ret < 0) {
1238                dev_err(tc->dev, "main link enable error: %d\n", ret);
1239                return;
1240        }
1241
1242        ret = tc_stream_enable(tc);
1243        if (ret < 0) {
1244                dev_err(tc->dev, "main link stream start error: %d\n", ret);
1245                tc_main_link_disable(tc);
1246                return;
1247        }
1248
1249        drm_panel_enable(tc->panel);
1250}
1251
1252static void tc_bridge_disable(struct drm_bridge *bridge)
1253{
1254        struct tc_data *tc = bridge_to_tc(bridge);
1255        int ret;
1256
1257        drm_panel_disable(tc->panel);
1258
1259        ret = tc_stream_disable(tc);
1260        if (ret < 0)
1261                dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1262
1263        ret = tc_main_link_disable(tc);
1264        if (ret < 0)
1265                dev_err(tc->dev, "main link disable error: %d\n", ret);
1266}
1267
1268static void tc_bridge_post_disable(struct drm_bridge *bridge)
1269{
1270        struct tc_data *tc = bridge_to_tc(bridge);
1271
1272        drm_panel_unprepare(tc->panel);
1273}
1274
1275static bool tc_bridge_mode_fixup(struct drm_bridge *bridge,
1276                                 const struct drm_display_mode *mode,
1277                                 struct drm_display_mode *adj)
1278{
1279        /* Fixup sync polarities, both hsync and vsync are active low */
1280        adj->flags = mode->flags;
1281        adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
1282        adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1283
1284        return true;
1285}
1286
1287static enum drm_mode_status tc_mode_valid(struct drm_bridge *bridge,
1288                                          const struct drm_display_mode *mode)
1289{
1290        struct tc_data *tc = bridge_to_tc(bridge);
1291        u32 req, avail;
1292        u32 bits_per_pixel = 24;
1293
1294        /* DPI interface clock limitation: upto 154 MHz */
1295        if (mode->clock > 154000)
1296                return MODE_CLOCK_HIGH;
1297
1298        req = mode->clock * bits_per_pixel / 8;
1299        avail = tc->link.base.num_lanes * tc->link.base.rate;
1300
1301        if (req > avail)
1302                return MODE_BAD;
1303
1304        return MODE_OK;
1305}
1306
1307static void tc_bridge_mode_set(struct drm_bridge *bridge,
1308                               const struct drm_display_mode *mode,
1309                               const struct drm_display_mode *adj)
1310{
1311        struct tc_data *tc = bridge_to_tc(bridge);
1312
1313        tc->mode = *mode;
1314}
1315
1316static int tc_connector_get_modes(struct drm_connector *connector)
1317{
1318        struct tc_data *tc = connector_to_tc(connector);
1319        struct edid *edid;
1320        int count;
1321        int ret;
1322
1323        ret = tc_get_display_props(tc);
1324        if (ret < 0) {
1325                dev_err(tc->dev, "failed to read display props: %d\n", ret);
1326                return 0;
1327        }
1328
1329        count = drm_panel_get_modes(tc->panel);
1330        if (count > 0)
1331                return count;
1332
1333        edid = drm_get_edid(connector, &tc->aux.ddc);
1334
1335        kfree(tc->edid);
1336        tc->edid = edid;
1337        if (!edid)
1338                return 0;
1339
1340        drm_connector_update_edid_property(connector, edid);
1341        count = drm_add_edid_modes(connector, edid);
1342
1343        return count;
1344}
1345
1346static const struct drm_connector_helper_funcs tc_connector_helper_funcs = {
1347        .get_modes = tc_connector_get_modes,
1348};
1349
1350static enum drm_connector_status tc_connector_detect(struct drm_connector *connector,
1351                                                     bool force)
1352{
1353        struct tc_data *tc = connector_to_tc(connector);
1354        bool conn;
1355        u32 val;
1356        int ret;
1357
1358        if (tc->hpd_pin < 0) {
1359                if (tc->panel)
1360                        return connector_status_connected;
1361                else
1362                        return connector_status_unknown;
1363        }
1364
1365        ret = regmap_read(tc->regmap, GPIOI, &val);
1366        if (ret)
1367                return connector_status_unknown;
1368
1369        conn = val & BIT(tc->hpd_pin);
1370
1371        if (conn)
1372                return connector_status_connected;
1373        else
1374                return connector_status_disconnected;
1375}
1376
1377static const struct drm_connector_funcs tc_connector_funcs = {
1378        .detect = tc_connector_detect,
1379        .fill_modes = drm_helper_probe_single_connector_modes,
1380        .destroy = drm_connector_cleanup,
1381        .reset = drm_atomic_helper_connector_reset,
1382        .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1383        .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1384};
1385
1386static int tc_bridge_attach(struct drm_bridge *bridge)
1387{
1388        u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1389        struct tc_data *tc = bridge_to_tc(bridge);
1390        struct drm_device *drm = bridge->dev;
1391        int ret;
1392
1393        /* Create DP/eDP connector */
1394        drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs);
1395        ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs,
1396                                 tc->panel ? DRM_MODE_CONNECTOR_eDP :
1397                                 DRM_MODE_CONNECTOR_DisplayPort);
1398        if (ret)
1399                return ret;
1400
1401        /* Don't poll if don't have HPD connected */
1402        if (tc->hpd_pin >= 0) {
1403                if (tc->have_irq)
1404                        tc->connector.polled = DRM_CONNECTOR_POLL_HPD;
1405                else
1406                        tc->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
1407                                               DRM_CONNECTOR_POLL_DISCONNECT;
1408        }
1409
1410        if (tc->panel)
1411                drm_panel_attach(tc->panel, &tc->connector);
1412
1413        drm_display_info_set_bus_formats(&tc->connector.display_info,
1414                                         &bus_format, 1);
1415        tc->connector.display_info.bus_flags =
1416                DRM_BUS_FLAG_DE_HIGH |
1417                DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE |
1418                DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE;
1419        drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder);
1420
1421        return 0;
1422}
1423
1424static const struct drm_bridge_funcs tc_bridge_funcs = {
1425        .attach = tc_bridge_attach,
1426        .mode_valid = tc_mode_valid,
1427        .mode_set = tc_bridge_mode_set,
1428        .pre_enable = tc_bridge_pre_enable,
1429        .enable = tc_bridge_enable,
1430        .disable = tc_bridge_disable,
1431        .post_disable = tc_bridge_post_disable,
1432        .mode_fixup = tc_bridge_mode_fixup,
1433};
1434
1435static bool tc_readable_reg(struct device *dev, unsigned int reg)
1436{
1437        return reg != SYSCTRL;
1438}
1439
1440static const struct regmap_range tc_volatile_ranges[] = {
1441        regmap_reg_range(DP0_AUXWDATA(0), DP0_AUXSTATUS),
1442        regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ),
1443        regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL),
1444        regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL),
1445        regmap_reg_range(VFUEN0, VFUEN0),
1446        regmap_reg_range(INTSTS_G, INTSTS_G),
1447        regmap_reg_range(GPIOI, GPIOI),
1448};
1449
1450static const struct regmap_access_table tc_volatile_table = {
1451        .yes_ranges = tc_volatile_ranges,
1452        .n_yes_ranges = ARRAY_SIZE(tc_volatile_ranges),
1453};
1454
1455static bool tc_writeable_reg(struct device *dev, unsigned int reg)
1456{
1457        return (reg != TC_IDREG) &&
1458               (reg != DP0_LTSTAT) &&
1459               (reg != DP0_SNKLTCHGREQ);
1460}
1461
1462static const struct regmap_config tc_regmap_config = {
1463        .name = "tc358767",
1464        .reg_bits = 16,
1465        .val_bits = 32,
1466        .reg_stride = 4,
1467        .max_register = PLL_DBG,
1468        .cache_type = REGCACHE_RBTREE,
1469        .readable_reg = tc_readable_reg,
1470        .volatile_table = &tc_volatile_table,
1471        .writeable_reg = tc_writeable_reg,
1472        .reg_format_endian = REGMAP_ENDIAN_BIG,
1473        .val_format_endian = REGMAP_ENDIAN_LITTLE,
1474};
1475
1476static irqreturn_t tc_irq_handler(int irq, void *arg)
1477{
1478        struct tc_data *tc = arg;
1479        u32 val;
1480        int r;
1481
1482        r = regmap_read(tc->regmap, INTSTS_G, &val);
1483        if (r)
1484                return IRQ_NONE;
1485
1486        if (!val)
1487                return IRQ_NONE;
1488
1489        if (val & INT_SYSERR) {
1490                u32 stat = 0;
1491
1492                regmap_read(tc->regmap, SYSSTAT, &stat);
1493
1494                dev_err(tc->dev, "syserr %x\n", stat);
1495        }
1496
1497        if (tc->hpd_pin >= 0 && tc->bridge.dev) {
1498                /*
1499                 * H is triggered when the GPIO goes high.
1500                 *
1501                 * LC is triggered when the GPIO goes low and stays low for
1502                 * the duration of LCNT
1503                 */
1504                bool h = val & INT_GPIO_H(tc->hpd_pin);
1505                bool lc = val & INT_GPIO_LC(tc->hpd_pin);
1506
1507                dev_dbg(tc->dev, "GPIO%d: %s %s\n", tc->hpd_pin,
1508                        h ? "H" : "", lc ? "LC" : "");
1509
1510                if (h || lc)
1511                        drm_kms_helper_hotplug_event(tc->bridge.dev);
1512        }
1513
1514        regmap_write(tc->regmap, INTSTS_G, val);
1515
1516        return IRQ_HANDLED;
1517}
1518
1519static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id)
1520{
1521        struct device *dev = &client->dev;
1522        struct tc_data *tc;
1523        int ret;
1524
1525        tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
1526        if (!tc)
1527                return -ENOMEM;
1528
1529        tc->dev = dev;
1530
1531        /* port@2 is the output port */
1532        ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &tc->panel, NULL);
1533        if (ret && ret != -ENODEV)
1534                return ret;
1535
1536        /* Shut down GPIO is optional */
1537        tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH);
1538        if (IS_ERR(tc->sd_gpio))
1539                return PTR_ERR(tc->sd_gpio);
1540
1541        if (tc->sd_gpio) {
1542                gpiod_set_value_cansleep(tc->sd_gpio, 0);
1543                usleep_range(5000, 10000);
1544        }
1545
1546        /* Reset GPIO is optional */
1547        tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1548        if (IS_ERR(tc->reset_gpio))
1549                return PTR_ERR(tc->reset_gpio);
1550
1551        if (tc->reset_gpio) {
1552                gpiod_set_value_cansleep(tc->reset_gpio, 1);
1553                usleep_range(5000, 10000);
1554        }
1555
1556        tc->refclk = devm_clk_get(dev, "ref");
1557        if (IS_ERR(tc->refclk)) {
1558                ret = PTR_ERR(tc->refclk);
1559                dev_err(dev, "Failed to get refclk: %d\n", ret);
1560                return ret;
1561        }
1562
1563        tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config);
1564        if (IS_ERR(tc->regmap)) {
1565                ret = PTR_ERR(tc->regmap);
1566                dev_err(dev, "Failed to initialize regmap: %d\n", ret);
1567                return ret;
1568        }
1569
1570        ret = of_property_read_u32(dev->of_node, "toshiba,hpd-pin",
1571                                   &tc->hpd_pin);
1572        if (ret) {
1573                tc->hpd_pin = -ENODEV;
1574        } else {
1575                if (tc->hpd_pin < 0 || tc->hpd_pin > 1) {
1576                        dev_err(dev, "failed to parse HPD number\n");
1577                        return ret;
1578                }
1579        }
1580
1581        if (client->irq > 0) {
1582                /* enable SysErr */
1583                regmap_write(tc->regmap, INTCTL_G, INT_SYSERR);
1584
1585                ret = devm_request_threaded_irq(dev, client->irq,
1586                                                NULL, tc_irq_handler,
1587                                                IRQF_ONESHOT,
1588                                                "tc358767-irq", tc);
1589                if (ret) {
1590                        dev_err(dev, "failed to register dp interrupt\n");
1591                        return ret;
1592                }
1593
1594                tc->have_irq = true;
1595        }
1596
1597        ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev);
1598        if (ret) {
1599                dev_err(tc->dev, "can not read device ID: %d\n", ret);
1600                return ret;
1601        }
1602
1603        if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) {
1604                dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev);
1605                return -EINVAL;
1606        }
1607
1608        tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */
1609
1610        if (!tc->reset_gpio) {
1611                /*
1612                 * If the reset pin isn't present, do a software reset. It isn't
1613                 * as thorough as the hardware reset, as we can't reset the I2C
1614                 * communication block for obvious reasons, but it's getting the
1615                 * chip into a defined state.
1616                 */
1617                regmap_update_bits(tc->regmap, SYSRSTENB,
1618                                ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP,
1619                                0);
1620                regmap_update_bits(tc->regmap, SYSRSTENB,
1621                                ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP,
1622                                ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP);
1623                usleep_range(5000, 10000);
1624        }
1625
1626        if (tc->hpd_pin >= 0) {
1627                u32 lcnt_reg = tc->hpd_pin == 0 ? INT_GP0_LCNT : INT_GP1_LCNT;
1628                u32 h_lc = INT_GPIO_H(tc->hpd_pin) | INT_GPIO_LC(tc->hpd_pin);
1629
1630                /* Set LCNT to 2ms */
1631                regmap_write(tc->regmap, lcnt_reg,
1632                             clk_get_rate(tc->refclk) * 2 / 1000);
1633                /* We need the "alternate" mode for HPD */
1634                regmap_write(tc->regmap, GPIOM, BIT(tc->hpd_pin));
1635
1636                if (tc->have_irq) {
1637                        /* enable H & LC */
1638                        regmap_update_bits(tc->regmap, INTCTL_G, h_lc, h_lc);
1639                }
1640        }
1641
1642        ret = tc_aux_link_setup(tc);
1643        if (ret)
1644                return ret;
1645
1646        /* Register DP AUX channel */
1647        tc->aux.name = "TC358767 AUX i2c adapter";
1648        tc->aux.dev = tc->dev;
1649        tc->aux.transfer = tc_aux_transfer;
1650        ret = drm_dp_aux_register(&tc->aux);
1651        if (ret)
1652                return ret;
1653
1654        tc->bridge.funcs = &tc_bridge_funcs;
1655        tc->bridge.of_node = dev->of_node;
1656        drm_bridge_add(&tc->bridge);
1657
1658        i2c_set_clientdata(client, tc);
1659
1660        return 0;
1661}
1662
1663static int tc_remove(struct i2c_client *client)
1664{
1665        struct tc_data *tc = i2c_get_clientdata(client);
1666
1667        drm_bridge_remove(&tc->bridge);
1668        drm_dp_aux_unregister(&tc->aux);
1669
1670        return 0;
1671}
1672
1673static const struct i2c_device_id tc358767_i2c_ids[] = {
1674        { "tc358767", 0 },
1675        { }
1676};
1677MODULE_DEVICE_TABLE(i2c, tc358767_i2c_ids);
1678
1679static const struct of_device_id tc358767_of_ids[] = {
1680        { .compatible = "toshiba,tc358767", },
1681        { }
1682};
1683MODULE_DEVICE_TABLE(of, tc358767_of_ids);
1684
1685static struct i2c_driver tc358767_driver = {
1686        .driver = {
1687                .name = "tc358767",
1688                .of_match_table = tc358767_of_ids,
1689        },
1690        .id_table = tc358767_i2c_ids,
1691        .probe = tc_probe,
1692        .remove = tc_remove,
1693};
1694module_i2c_driver(tc358767_driver);
1695
1696MODULE_AUTHOR("Andrey Gusakov <andrey.gusakov@cogentembedded.com>");
1697MODULE_DESCRIPTION("tc358767 eDP encoder driver");
1698MODULE_LICENSE("GPL");
1699