LXR linux/drivers/gpu/drm/bridge/tc358775.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * TC358775 DSI to LVDS bridge driver
   4 *
   5 * Copyright (C) 2020 SMART Wireless Computing
   6 * Author: Vinay Simha BN <simhavcs@gmail.com>
   7 *
   8 */
   9/* #define DEBUG */
  10#include <linux/bitfield.h>
  11#include <linux/clk.h>
  12#include <linux/device.h>
  13#include <linux/gpio/consumer.h>
  14#include <linux/i2c.h>
  15#include <linux/kernel.h>
  16#include <linux/module.h>
  17#include <linux/regulator/consumer.h>
  18#include <linux/slab.h>
  19
  20#include <asm/unaligned.h>
  21
  22#include <drm/drm_atomic_helper.h>
  23#include <drm/drm_bridge.h>
  24#include <drm/drm_crtc_helper.h>
  25#include <drm/drm_dp_helper.h>
  26#include <drm/drm_mipi_dsi.h>
  27#include <drm/drm_of.h>
  28#include <drm/drm_panel.h>
  29#include <drm/drm_probe_helper.h>
  30
  31#define FLD_VAL(val, start, end) FIELD_PREP(GENMASK(start, end), val)
  32
  33/* Registers */
  34
  35/* DSI D-PHY Layer Registers */
  36#define D0W_DPHYCONTTX  0x0004  /* Data Lane 0 DPHY Tx Control */
  37#define CLW_DPHYCONTRX  0x0020  /* Clock Lane DPHY Rx Control */
  38#define D0W_DPHYCONTRX  0x0024  /* Data Lane 0 DPHY Rx Control */
  39#define D1W_DPHYCONTRX  0x0028  /* Data Lane 1 DPHY Rx Control */
  40#define D2W_DPHYCONTRX  0x002C  /* Data Lane 2 DPHY Rx Control */
  41#define D3W_DPHYCONTRX  0x0030  /* Data Lane 3 DPHY Rx Control */
  42#define COM_DPHYCONTRX  0x0038  /* DPHY Rx Common Control */
  43#define CLW_CNTRL       0x0040  /* Clock Lane Control */
  44#define D0W_CNTRL       0x0044  /* Data Lane 0 Control */
  45#define D1W_CNTRL       0x0048  /* Data Lane 1 Control */
  46#define D2W_CNTRL       0x004C  /* Data Lane 2 Control */
  47#define D3W_CNTRL       0x0050  /* Data Lane 3 Control */
  48#define DFTMODE_CNTRL   0x0054  /* DFT Mode Control */
  49
  50/* DSI PPI Layer Registers */
  51#define PPI_STARTPPI    0x0104  /* START control bit of PPI-TX function. */
  52#define PPI_START_FUNCTION      1
  53
  54#define PPI_BUSYPPI     0x0108
  55#define PPI_LINEINITCNT 0x0110  /* Line Initialization Wait Counter  */
  56#define PPI_LPTXTIMECNT 0x0114
  57#define PPI_LANEENABLE  0x0134  /* Enables each lane at the PPI layer. */
  58#define PPI_TX_RX_TA    0x013C  /* DSI Bus Turn Around timing parameters */
  59
  60/* Analog timer function enable */
  61#define PPI_CLS_ATMR    0x0140  /* Delay for Clock Lane in LPRX  */
  62#define PPI_D0S_ATMR    0x0144  /* Delay for Data Lane 0 in LPRX */
  63#define PPI_D1S_ATMR    0x0148  /* Delay for Data Lane 1 in LPRX */
  64#define PPI_D2S_ATMR    0x014C  /* Delay for Data Lane 2 in LPRX */
  65#define PPI_D3S_ATMR    0x0150  /* Delay for Data Lane 3 in LPRX */
  66
  67#define PPI_D0S_CLRSIPOCOUNT    0x0164  /* For lane 0 */
  68#define PPI_D1S_CLRSIPOCOUNT    0x0168  /* For lane 1 */
  69#define PPI_D2S_CLRSIPOCOUNT    0x016C  /* For lane 2 */
  70#define PPI_D3S_CLRSIPOCOUNT    0x0170  /* For lane 3 */
  71
  72#define CLS_PRE         0x0180  /* Digital Counter inside of PHY IO */
  73#define D0S_PRE         0x0184  /* Digital Counter inside of PHY IO */
  74#define D1S_PRE         0x0188  /* Digital Counter inside of PHY IO */
  75#define D2S_PRE         0x018C  /* Digital Counter inside of PHY IO */
  76#define D3S_PRE         0x0190  /* Digital Counter inside of PHY IO */
  77#define CLS_PREP        0x01A0  /* Digital Counter inside of PHY IO */
  78#define D0S_PREP        0x01A4  /* Digital Counter inside of PHY IO */
  79#define D1S_PREP        0x01A8  /* Digital Counter inside of PHY IO */
  80#define D2S_PREP        0x01AC  /* Digital Counter inside of PHY IO */
  81#define D3S_PREP        0x01B0  /* Digital Counter inside of PHY IO */
  82#define CLS_ZERO        0x01C0  /* Digital Counter inside of PHY IO */
  83#define D0S_ZERO        0x01C4  /* Digital Counter inside of PHY IO */
  84#define D1S_ZERO        0x01C8  /* Digital Counter inside of PHY IO */
  85#define D2S_ZERO        0x01CC  /* Digital Counter inside of PHY IO */
  86#define D3S_ZERO        0x01D0  /* Digital Counter inside of PHY IO */
  87
  88#define PPI_CLRFLG      0x01E0  /* PRE Counters has reached set values */
  89#define PPI_CLRSIPO     0x01E4  /* Clear SIPO values, Slave mode use only. */
  90#define HSTIMEOUT       0x01F0  /* HS Rx Time Out Counter */
  91#define HSTIMEOUTENABLE 0x01F4  /* Enable HS Rx Time Out Counter */
  92#define DSI_STARTDSI    0x0204  /* START control bit of DSI-TX function */
  93#define DSI_RX_START    1
  94
  95#define DSI_BUSYDSI     0x0208
  96#define DSI_LANEENABLE  0x0210  /* Enables each lane at the Protocol layer. */
  97#define DSI_LANESTATUS0 0x0214  /* Displays lane is in HS RX mode. */
  98#define DSI_LANESTATUS1 0x0218  /* Displays lane is in ULPS or STOP state */
  99
 100#define DSI_INTSTATUS   0x0220  /* Interrupt Status */
 101#define DSI_INTMASK     0x0224  /* Interrupt Mask */
 102#define DSI_INTCLR      0x0228  /* Interrupt Clear */
 103#define DSI_LPTXTO      0x0230  /* Low Power Tx Time Out Counter */
 104
 105#define DSIERRCNT       0x0300  /* DSI Error Count */
 106#define APLCTRL         0x0400  /* Application Layer Control */
 107#define RDPKTLN         0x0404  /* Command Read Packet Length */
 108
 109#define VPCTRL          0x0450  /* Video Path Control */
 110#define HTIM1           0x0454  /* Horizontal Timing Control 1 */
 111#define HTIM2           0x0458  /* Horizontal Timing Control 2 */
 112#define VTIM1           0x045C  /* Vertical Timing Control 1 */
 113#define VTIM2           0x0460  /* Vertical Timing Control 2 */
 114#define VFUEN           0x0464  /* Video Frame Timing Update Enable */
 115#define VFUEN_EN        BIT(0)  /* Upload Enable */
 116
 117/* Mux Input Select for LVDS LINK Input */
 118#define LV_MX0003        0x0480  /* Bit 0 to 3 */
 119#define LV_MX0407        0x0484  /* Bit 4 to 7 */
 120#define LV_MX0811        0x0488  /* Bit 8 to 11 */
 121#define LV_MX1215        0x048C  /* Bit 12 to 15 */
 122#define LV_MX1619        0x0490  /* Bit 16 to 19 */
 123#define LV_MX2023        0x0494  /* Bit 20 to 23 */
 124#define LV_MX2427        0x0498  /* Bit 24 to 27 */
 125#define LV_MX(b0, b1, b2, b3)   (FLD_VAL(b0, 4, 0) | FLD_VAL(b1, 12, 8) | \
 126                                FLD_VAL(b2, 20, 16) | FLD_VAL(b3, 28, 24))
 127
 128/* Input bit numbers used in mux registers */
 129enum {
 130        LVI_R0,
 131        LVI_R1,
 132        LVI_R2,
 133        LVI_R3,
 134        LVI_R4,
 135        LVI_R5,
 136        LVI_R6,
 137        LVI_R7,
 138        LVI_G0,
 139        LVI_G1,
 140        LVI_G2,
 141        LVI_G3,
 142        LVI_G4,
 143        LVI_G5,
 144        LVI_G6,
 145        LVI_G7,
 146        LVI_B0,
 147        LVI_B1,
 148        LVI_B2,
 149        LVI_B3,
 150        LVI_B4,
 151        LVI_B5,
 152        LVI_B6,
 153        LVI_B7,
 154        LVI_HS,
 155        LVI_VS,
 156        LVI_DE,
 157        LVI_L0
 158};
 159
 160#define LVCFG           0x049C  /* LVDS Configuration  */
 161#define LVPHY0          0x04A0  /* LVDS PHY 0 */
 162#define LV_PHY0_RST(v)          FLD_VAL(v, 22, 22) /* PHY reset */
 163#define LV_PHY0_IS(v)           FLD_VAL(v, 15, 14)
 164#define LV_PHY0_ND(v)           FLD_VAL(v, 4, 0) /* Frequency range select */
 165#define LV_PHY0_PRBS_ON(v)      FLD_VAL(v, 20, 16) /* Clock/Data Flag pins */
 166
 167#define LVPHY1          0x04A4  /* LVDS PHY 1 */
 168#define SYSSTAT         0x0500  /* System Status  */
 169#define SYSRST          0x0504  /* System Reset  */
 170
 171#define SYS_RST_I2CS    BIT(0) /* Reset I2C-Slave controller */
 172#define SYS_RST_I2CM    BIT(1) /* Reset I2C-Master controller */
 173#define SYS_RST_LCD     BIT(2) /* Reset LCD controller */
 174#define SYS_RST_BM      BIT(3) /* Reset Bus Management controller */
 175#define SYS_RST_DSIRX   BIT(4) /* Reset DSI-RX and App controller */
 176#define SYS_RST_REG     BIT(5) /* Reset Register module */
 177
 178/* GPIO Registers */
 179#define GPIOC           0x0520  /* GPIO Control  */
 180#define GPIOO           0x0524  /* GPIO Output  */
 181#define GPIOI           0x0528  /* GPIO Input  */
 182
 183/* I2C Registers */
 184#define I2CTIMCTRL      0x0540  /* I2C IF Timing and Enable Control */
 185#define I2CMADDR        0x0544  /* I2C Master Addressing */
 186#define WDATAQ          0x0548  /* Write Data Queue */
 187#define RDATAQ          0x054C  /* Read Data Queue */
 188
 189/* Chip ID and Revision ID Register */
 190#define IDREG           0x0580
 191
 192#define LPX_PERIOD              4
 193#define TTA_GET                 0x40000
 194#define TTA_SURE                6
 195#define SINGLE_LINK             1
 196#define DUAL_LINK               2
 197
 198#define TC358775XBG_ID  0x00007500
 199
 200/* Debug Registers */
 201#define DEBUG00         0x05A0  /* Debug */
 202#define DEBUG01         0x05A4  /* LVDS Data */
 203
 204#define DSI_CLEN_BIT            BIT(0)
 205#define DIVIDE_BY_3             3 /* PCLK=DCLK/3 */
 206#define DIVIDE_BY_6             6 /* PCLK=DCLK/6 */
 207#define LVCFG_LVEN_BIT          BIT(0)
 208
 209#define L0EN BIT(1)
 210
 211#define TC358775_VPCTRL_VSDELAY__MASK   0x3FF00000
 212#define TC358775_VPCTRL_VSDELAY__SHIFT  20
 213static inline u32 TC358775_VPCTRL_VSDELAY(uint32_t val)
 214{
 215        return ((val) << TC358775_VPCTRL_VSDELAY__SHIFT) &
 216                        TC358775_VPCTRL_VSDELAY__MASK;
 217}
 218
 219#define TC358775_VPCTRL_OPXLFMT__MASK   0x00000100
 220#define TC358775_VPCTRL_OPXLFMT__SHIFT  8
 221static inline u32 TC358775_VPCTRL_OPXLFMT(uint32_t val)
 222{
 223        return ((val) << TC358775_VPCTRL_OPXLFMT__SHIFT) &
 224                        TC358775_VPCTRL_OPXLFMT__MASK;
 225}
 226
 227#define TC358775_VPCTRL_MSF__MASK       0x00000001
 228#define TC358775_VPCTRL_MSF__SHIFT      0
 229static inline u32 TC358775_VPCTRL_MSF(uint32_t val)
 230{
 231        return ((val) << TC358775_VPCTRL_MSF__SHIFT) &
 232                        TC358775_VPCTRL_MSF__MASK;
 233}
 234
 235#define TC358775_LVCFG_PCLKDIV__MASK    0x000000f0
 236#define TC358775_LVCFG_PCLKDIV__SHIFT   4
 237static inline u32 TC358775_LVCFG_PCLKDIV(uint32_t val)
 238{
 239        return ((val) << TC358775_LVCFG_PCLKDIV__SHIFT) &
 240                        TC358775_LVCFG_PCLKDIV__MASK;
 241}
 242
 243#define TC358775_LVCFG_LVDLINK__MASK                         0x00000002
 244#define TC358775_LVCFG_LVDLINK__SHIFT                        0
 245static inline u32 TC358775_LVCFG_LVDLINK(uint32_t val)
 246{
 247        return ((val) << TC358775_LVCFG_LVDLINK__SHIFT) &
 248                        TC358775_LVCFG_LVDLINK__MASK;
 249}
 250
 251enum tc358775_ports {
 252        TC358775_DSI_IN,
 253        TC358775_LVDS_OUT0,
 254        TC358775_LVDS_OUT1,
 255};
 256
 257struct tc_data {
 258        struct i2c_client       *i2c;
 259        struct device           *dev;
 260
 261        struct drm_bridge       bridge;
 262        struct drm_bridge       *panel_bridge;
 263
 264        struct device_node *host_node;
 265        struct mipi_dsi_device *dsi;
 266        u8 num_dsi_lanes;
 267
 268        struct regulator        *vdd;
 269        struct regulator        *vddio;
 270        struct gpio_desc        *reset_gpio;
 271        struct gpio_desc        *stby_gpio;
 272        u8                      lvds_link; /* single-link or dual-link */
 273        u8                      bpc;
 274};
 275
 276static inline struct tc_data *bridge_to_tc(struct drm_bridge *b)
 277{
 278        return container_of(b, struct tc_data, bridge);
 279}
 280
 281static void tc_bridge_pre_enable(struct drm_bridge *bridge)
 282{
 283        struct tc_data *tc = bridge_to_tc(bridge);
 284        struct device *dev = &tc->dsi->dev;
 285        int ret;
 286
 287        ret = regulator_enable(tc->vddio);
 288        if (ret < 0)
 289                dev_err(dev, "regulator vddio enable failed, %d\n", ret);
 290        usleep_range(10000, 11000);
 291
 292        ret = regulator_enable(tc->vdd);
 293        if (ret < 0)
 294                dev_err(dev, "regulator vdd enable failed, %d\n", ret);
 295        usleep_range(10000, 11000);
 296
 297        gpiod_set_value(tc->stby_gpio, 0);
 298        usleep_range(10000, 11000);
 299
 300        gpiod_set_value(tc->reset_gpio, 0);
 301        usleep_range(10, 20);
 302}
 303
 304static void tc_bridge_post_disable(struct drm_bridge *bridge)
 305{
 306        struct tc_data *tc = bridge_to_tc(bridge);
 307        struct device *dev = &tc->dsi->dev;
 308        int ret;
 309
 310        gpiod_set_value(tc->reset_gpio, 1);
 311        usleep_range(10, 20);
 312
 313        gpiod_set_value(tc->stby_gpio, 1);
 314        usleep_range(10000, 11000);
 315
 316        ret = regulator_disable(tc->vdd);
 317        if (ret < 0)
 318                dev_err(dev, "regulator vdd disable failed, %d\n", ret);
 319        usleep_range(10000, 11000);
 320
 321        ret = regulator_disable(tc->vddio);
 322        if (ret < 0)
 323                dev_err(dev, "regulator vddio disable failed, %d\n", ret);
 324        usleep_range(10000, 11000);
 325}
 326
 327static void d2l_read(struct i2c_client *i2c, u16 addr, u32 *val)
 328{
 329        int ret;
 330        u8 buf_addr[2];
 331
 332        put_unaligned_be16(addr, buf_addr);
 333        ret = i2c_master_send(i2c, buf_addr, sizeof(buf_addr));
 334        if (ret < 0)
 335                goto fail;
 336
 337        ret = i2c_master_recv(i2c, (u8 *)val, sizeof(*val));
 338        if (ret < 0)
 339                goto fail;
 340
 341        pr_debug("d2l: I2C : addr:%04x value:%08x\n", addr, *val);
 342
 343fail:
 344        dev_err(&i2c->dev, "Error %d reading from subaddress 0x%x\n",
 345                ret, addr);
 346}
 347
 348static void d2l_write(struct i2c_client *i2c, u16 addr, u32 val)
 349{
 350        u8 data[6];
 351        int ret;
 352
 353        put_unaligned_be16(addr, data);
 354        put_unaligned_le32(val, data + 2);
 355
 356        ret = i2c_master_send(i2c, data, ARRAY_SIZE(data));
 357        if (ret < 0)
 358                dev_err(&i2c->dev, "Error %d writing to subaddress 0x%x\n",
 359                        ret, addr);
 360}
 361
 362/* helper function to access bus_formats */
 363static struct drm_connector *get_connector(struct drm_encoder *encoder)
 364{
 365        struct drm_device *dev = encoder->dev;
 366        struct drm_connector *connector;
 367
 368        list_for_each_entry(connector, &dev->mode_config.connector_list, head)
 369                if (connector->encoder == encoder)
 370                        return connector;
 371
 372        return NULL;
 373}
 374
 375static void tc_bridge_enable(struct drm_bridge *bridge)
 376{
 377        struct tc_data *tc = bridge_to_tc(bridge);
 378        u32 hback_porch, hsync_len, hfront_porch, hactive, htime1, htime2;
 379        u32 vback_porch, vsync_len, vfront_porch, vactive, vtime1, vtime2;
 380        u32 val = 0;
 381        u16 dsiclk, clkdiv, byteclk, t1, t2, t3, vsdelay;
 382        struct drm_display_mode *mode;
 383        struct drm_connector *connector = get_connector(bridge->encoder);
 384
 385        mode = &bridge->encoder->crtc->state->adjusted_mode;
 386
 387        hback_porch = mode->htotal - mode->hsync_end;
 388        hsync_len  = mode->hsync_end - mode->hsync_start;
 389        vback_porch = mode->vtotal - mode->vsync_end;
 390        vsync_len  = mode->vsync_end - mode->vsync_start;
 391
 392        htime1 = (hback_porch << 16) + hsync_len;
 393        vtime1 = (vback_porch << 16) + vsync_len;
 394
 395        hfront_porch = mode->hsync_start - mode->hdisplay;
 396        hactive = mode->hdisplay;
 397        vfront_porch = mode->vsync_start - mode->vdisplay;
 398        vactive = mode->vdisplay;
 399
 400        htime2 = (hfront_porch << 16) + hactive;
 401        vtime2 = (vfront_porch << 16) + vactive;
 402
 403        d2l_read(tc->i2c, IDREG, &val);
 404
 405        dev_info(tc->dev, "DSI2LVDS Chip ID.%02x Revision ID. %02x **\n",
 406                 (val >> 8) & 0xFF, val & 0xFF);
 407
 408        d2l_write(tc->i2c, SYSRST, SYS_RST_REG | SYS_RST_DSIRX | SYS_RST_BM |
 409                  SYS_RST_LCD | SYS_RST_I2CM | SYS_RST_I2CS);
 410        usleep_range(30000, 40000);
 411
 412        d2l_write(tc->i2c, PPI_TX_RX_TA, TTA_GET | TTA_SURE);
 413        d2l_write(tc->i2c, PPI_LPTXTIMECNT, LPX_PERIOD);
 414        d2l_write(tc->i2c, PPI_D0S_CLRSIPOCOUNT, 3);
 415        d2l_write(tc->i2c, PPI_D1S_CLRSIPOCOUNT, 3);
 416        d2l_write(tc->i2c, PPI_D2S_CLRSIPOCOUNT, 3);
 417        d2l_write(tc->i2c, PPI_D3S_CLRSIPOCOUNT, 3);
 418
 419        val = ((L0EN << tc->num_dsi_lanes) - L0EN) | DSI_CLEN_BIT;
 420        d2l_write(tc->i2c, PPI_LANEENABLE, val);
 421        d2l_write(tc->i2c, DSI_LANEENABLE, val);
 422
 423        d2l_write(tc->i2c, PPI_STARTPPI, PPI_START_FUNCTION);
 424        d2l_write(tc->i2c, DSI_STARTDSI, DSI_RX_START);
 425
 426        if (tc->bpc == 8)
 427                val = TC358775_VPCTRL_OPXLFMT(1);
 428        else /* bpc = 6; */
 429                val = TC358775_VPCTRL_MSF(1);
 430
 431        dsiclk = mode->crtc_clock * 3 * tc->bpc / tc->num_dsi_lanes / 1000;
 432        clkdiv = dsiclk / DIVIDE_BY_3 * tc->lvds_link;
 433        byteclk = dsiclk / 4;
 434        t1 = hactive * (tc->bpc * 3 / 8) / tc->num_dsi_lanes;
 435        t2 = ((100000 / clkdiv)) * (hactive + hback_porch + hsync_len + hfront_porch) / 1000;
 436        t3 = ((t2 * byteclk) / 100) - (hactive * (tc->bpc * 3 / 8) /
 437                tc->num_dsi_lanes);
 438
 439        vsdelay = (clkdiv * (t1 + t3) / byteclk) - hback_porch - hsync_len - hactive;
 440
 441        val |= TC358775_VPCTRL_VSDELAY(vsdelay);
 442        d2l_write(tc->i2c, VPCTRL, val);
 443
 444        d2l_write(tc->i2c, HTIM1, htime1);
 445        d2l_write(tc->i2c, VTIM1, vtime1);
 446        d2l_write(tc->i2c, HTIM2, htime2);
 447        d2l_write(tc->i2c, VTIM2, vtime2);
 448
 449        d2l_write(tc->i2c, VFUEN, VFUEN_EN);
 450        d2l_write(tc->i2c, SYSRST, SYS_RST_LCD);
 451        d2l_write(tc->i2c, LVPHY0, LV_PHY0_PRBS_ON(4) | LV_PHY0_ND(6));
 452
 453        dev_dbg(tc->dev, "bus_formats %04x bpc %d\n",
 454                connector->display_info.bus_formats[0],
 455                tc->bpc);
 456        /*
 457         * Default hardware register settings of tc358775 configured
 458         * with MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA jeida-24 format
 459         */
 460        if (connector->display_info.bus_formats[0] ==
 461                MEDIA_BUS_FMT_RGB888_1X7X4_SPWG) {
 462                /* VESA-24 */
 463                d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3));
 464                d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R4, LVI_R7, LVI_R5, LVI_G0));
 465                d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_G6, LVI_G7));
 466                d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0));
 467                d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_B6, LVI_B7, LVI_B1, LVI_B2));
 468                d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0));
 469                d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R6));
 470        } else { /*  MEDIA_BUS_FMT_RGB666_1X7X3_SPWG - JEIDA-18 */
 471                d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3));
 472                d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R4, LVI_L0, LVI_R5, LVI_G0));
 473                d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_L0, LVI_L0));
 474                d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0));
 475                d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_L0, LVI_L0, LVI_B1, LVI_B2));
 476                d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0));
 477                d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_L0));
 478        }
 479
 480        d2l_write(tc->i2c, VFUEN, VFUEN_EN);
 481
 482        val = LVCFG_LVEN_BIT;
 483        if (tc->lvds_link == DUAL_LINK) {
 484                val |= TC358775_LVCFG_LVDLINK(1);
 485                val |= TC358775_LVCFG_PCLKDIV(DIVIDE_BY_6);
 486        } else {
 487                val |= TC358775_LVCFG_PCLKDIV(DIVIDE_BY_3);
 488        }
 489        d2l_write(tc->i2c, LVCFG, val);
 490}
 491
 492static enum drm_mode_status
 493tc_mode_valid(struct drm_bridge *bridge,
 494              const struct drm_display_info *info,
 495              const struct drm_display_mode *mode)
 496{
 497        struct tc_data *tc = bridge_to_tc(bridge);
 498
 499        /*
 500         * Maximum pixel clock speed 135MHz for single-link
 501         * 270MHz for dual-link
 502         */
 503        if ((mode->clock > 135000 && tc->lvds_link == SINGLE_LINK) ||
 504            (mode->clock > 270000 && tc->lvds_link == DUAL_LINK))
 505                return MODE_CLOCK_HIGH;
 506
 507        switch (info->bus_formats[0]) {
 508        case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
 509        case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
 510                /* RGB888 */
 511                tc->bpc = 8;
 512                break;
 513        case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
 514                /* RGB666 */
 515                tc->bpc = 6;
 516                break;
 517        default:
 518                dev_warn(tc->dev,
 519                         "unsupported LVDS bus format 0x%04x\n",
 520                         info->bus_formats[0]);
 521                return MODE_NOMODE;
 522        }
 523
 524        return MODE_OK;
 525}
 526
 527static int tc358775_parse_dt(struct device_node *np, struct tc_data *tc)
 528{
 529        struct device_node *endpoint;
 530        struct device_node *parent;
 531        struct device_node *remote;
 532        struct property *prop;
 533        int len = 0;
 534
 535        /*
 536         * To get the data-lanes of dsi, we need to access the dsi0_out of port1
 537         *  of dsi0 endpoint from bridge port0 of d2l_in
 538         */
 539        endpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node,
 540                                                 TC358775_DSI_IN, -1);
 541        if (endpoint) {
 542                /* dsi0_out node */
 543                parent = of_graph_get_remote_port_parent(endpoint);
 544                of_node_put(endpoint);
 545                if (parent) {
 546                        /* dsi0 port 1 */
 547                        endpoint = of_graph_get_endpoint_by_regs(parent, 1, -1);
 548                        of_node_put(parent);
 549                        if (endpoint) {
 550                                prop = of_find_property(endpoint, "data-lanes",
 551                                                        &len);
 552                                of_node_put(endpoint);
 553                                if (!prop) {
 554                                        dev_err(tc->dev,
 555                                                "failed to find data lane\n");
 556                                        return -EPROBE_DEFER;
 557                                }
 558                        }
 559                }
 560        }
 561
 562        tc->num_dsi_lanes = len / sizeof(u32);
 563
 564        if (tc->num_dsi_lanes < 1 || tc->num_dsi_lanes > 4)
 565                return -EINVAL;
 566
 567        tc->host_node = of_graph_get_remote_node(np, 0, 0);
 568        if (!tc->host_node)
 569                return -ENODEV;
 570
 571        of_node_put(tc->host_node);
 572
 573        tc->lvds_link = SINGLE_LINK;
 574        endpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node,
 575                                                 TC358775_LVDS_OUT1, -1);
 576        if (endpoint) {
 577                remote = of_graph_get_remote_port_parent(endpoint);
 578                of_node_put(endpoint);
 579
 580                if (remote) {
 581                        if (of_device_is_available(remote))
 582                                tc->lvds_link = DUAL_LINK;
 583                        of_node_put(remote);
 584                }
 585        }
 586
 587        dev_dbg(tc->dev, "no.of dsi lanes: %d\n", tc->num_dsi_lanes);
 588        dev_dbg(tc->dev, "operating in %d-link mode\n", tc->lvds_link);
 589
 590        return 0;
 591}
 592
 593static int tc_bridge_attach(struct drm_bridge *bridge,
 594                            enum drm_bridge_attach_flags flags)
 595{
 596        struct tc_data *tc = bridge_to_tc(bridge);
 597        struct device *dev = &tc->i2c->dev;
 598        struct mipi_dsi_host *host;
 599        struct mipi_dsi_device *dsi;
 600        int ret;
 601
 602        const struct mipi_dsi_device_info info = { .type = "tc358775",
 603                                                        .channel = 0,
 604                                                        .node = NULL,
 605                                                };
 606
 607        host = of_find_mipi_dsi_host_by_node(tc->host_node);
 608        if (!host) {
 609                dev_err(dev, "failed to find dsi host\n");
 610                return -EPROBE_DEFER;
 611        }
 612
 613        dsi = mipi_dsi_device_register_full(host, &info);
 614        if (IS_ERR(dsi)) {
 615                dev_err(dev, "failed to create dsi device\n");
 616                ret = PTR_ERR(dsi);
 617                goto err_dsi_device;
 618        }
 619
 620        tc->dsi = dsi;
 621
 622        dsi->lanes = tc->num_dsi_lanes;
 623        dsi->format = MIPI_DSI_FMT_RGB888;
 624        dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
 625
 626        ret = mipi_dsi_attach(dsi);
 627        if (ret < 0) {
 628                dev_err(dev, "failed to attach dsi to host\n");
 629                goto err_dsi_attach;
 630        }
 631
 632        /* Attach the panel-bridge to the dsi bridge */
 633        return drm_bridge_attach(bridge->encoder, tc->panel_bridge,
 634                                 &tc->bridge, flags);
 635err_dsi_attach:
 636        mipi_dsi_device_unregister(dsi);
 637err_dsi_device:
 638        return ret;
 639}
 640
 641static const struct drm_bridge_funcs tc_bridge_funcs = {
 642        .attach = tc_bridge_attach,
 643        .pre_enable = tc_bridge_pre_enable,
 644        .enable = tc_bridge_enable,
 645        .mode_valid = tc_mode_valid,
 646        .post_disable = tc_bridge_post_disable,
 647};
 648
 649static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id)
 650{
 651        struct device *dev = &client->dev;
 652        struct drm_panel *panel;
 653        struct tc_data *tc;
 654        int ret;
 655
 656        tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
 657        if (!tc)
 658                return -ENOMEM;
 659
 660        tc->dev = dev;
 661        tc->i2c = client;
 662
 663        ret = drm_of_find_panel_or_bridge(dev->of_node, TC358775_LVDS_OUT0,
 664                                          0, &panel, NULL);
 665        if (ret < 0)
 666                return ret;
 667        if (!panel)
 668                return -ENODEV;
 669
 670        tc->panel_bridge = devm_drm_panel_bridge_add(dev, panel);
 671        if (IS_ERR(tc->panel_bridge))
 672                return PTR_ERR(tc->panel_bridge);
 673
 674        ret = tc358775_parse_dt(dev->of_node, tc);
 675        if (ret)
 676                return ret;
 677
 678        tc->vddio = devm_regulator_get(dev, "vddio-supply");
 679        if (IS_ERR(tc->vddio)) {
 680                ret = PTR_ERR(tc->vddio);
 681                dev_err(dev, "vddio-supply not found\n");
 682                return ret;
 683        }
 684
 685        tc->vdd = devm_regulator_get(dev, "vdd-supply");
 686        if (IS_ERR(tc->vdd)) {
 687                ret = PTR_ERR(tc->vdd);
 688                dev_err(dev, "vdd-supply not found\n");
 689                return ret;
 690        }
 691
 692        tc->stby_gpio = devm_gpiod_get(dev, "stby", GPIOD_OUT_HIGH);
 693        if (IS_ERR(tc->stby_gpio)) {
 694                ret = PTR_ERR(tc->stby_gpio);
 695                dev_err(dev, "cannot get stby-gpio %d\n", ret);
 696                return ret;
 697        }
 698
 699        tc->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
 700        if (IS_ERR(tc->reset_gpio)) {
 701                ret = PTR_ERR(tc->reset_gpio);
 702                dev_err(dev, "cannot get reset-gpios %d\n", ret);
 703                return ret;
 704        }
 705
 706        tc->bridge.funcs = &tc_bridge_funcs;
 707        tc->bridge.of_node = dev->of_node;
 708        drm_bridge_add(&tc->bridge);
 709
 710        i2c_set_clientdata(client, tc);
 711
 712        return 0;
 713}
 714
 715static int tc_remove(struct i2c_client *client)
 716{
 717        struct tc_data *tc = i2c_get_clientdata(client);
 718
 719        drm_bridge_remove(&tc->bridge);
 720
 721        return 0;
 722}
 723
 724static const struct i2c_device_id tc358775_i2c_ids[] = {
 725        { "tc358775", 0 },
 726        { }
 727};
 728MODULE_DEVICE_TABLE(i2c, tc358775_i2c_ids);
 729
 730static const struct of_device_id tc358775_of_ids[] = {
 731        { .compatible = "toshiba,tc358775", },
 732        { }
 733};
 734MODULE_DEVICE_TABLE(of, tc358775_of_ids);
 735
 736static struct i2c_driver tc358775_driver = {
 737        .driver = {
 738                .name = "tc358775",
 739                .of_match_table = tc358775_of_ids,
 740        },
 741        .id_table = tc358775_i2c_ids,
 742        .probe = tc_probe,
 743        .remove = tc_remove,
 744};
 745module_i2c_driver(tc358775_driver);
 746
 747MODULE_AUTHOR("Vinay Simha BN <simhavcs@gmail.com>");
 748MODULE_DESCRIPTION("TC358775 DSI/LVDS bridge driver");
 749MODULE_LICENSE("GPL v2");
 750