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23#include <linux/delay.h>
24#include <linux/errno.h>
25#include <linux/i2c.h>
26#include <linux/init.h>
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/sched.h>
30#include <linux/seq_file.h>
31
32#include <drm/drm_dp_helper.h>
33#include <drm/drm_print.h>
34#include <drm/drm_vblank.h>
35#include <drm/drm_dp_mst_helper.h>
36#include <drm/drm_panel.h>
37
38#include "drm_crtc_helper_internal.h"
39
40struct dp_aux_backlight {
41 struct backlight_device *base;
42 struct drm_dp_aux *aux;
43 struct drm_edp_backlight_info info;
44 bool enabled;
45};
46
47
48
49
50
51
52
53
54
55
56
57static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
58{
59 return link_status[r - DP_LANE0_1_STATUS];
60}
61
62static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
63 int lane)
64{
65 int i = DP_LANE0_1_STATUS + (lane >> 1);
66 int s = (lane & 1) * 4;
67 u8 l = dp_link_status(link_status, i);
68
69 return (l >> s) & 0xf;
70}
71
72bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
73 int lane_count)
74{
75 u8 lane_align;
76 u8 lane_status;
77 int lane;
78
79 lane_align = dp_link_status(link_status,
80 DP_LANE_ALIGN_STATUS_UPDATED);
81 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
82 return false;
83 for (lane = 0; lane < lane_count; lane++) {
84 lane_status = dp_get_lane_status(link_status, lane);
85 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
86 return false;
87 }
88 return true;
89}
90EXPORT_SYMBOL(drm_dp_channel_eq_ok);
91
92bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
93 int lane_count)
94{
95 int lane;
96 u8 lane_status;
97
98 for (lane = 0; lane < lane_count; lane++) {
99 lane_status = dp_get_lane_status(link_status, lane);
100 if ((lane_status & DP_LANE_CR_DONE) == 0)
101 return false;
102 }
103 return true;
104}
105EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
106
107u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
108 int lane)
109{
110 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
111 int s = ((lane & 1) ?
112 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
113 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
114 u8 l = dp_link_status(link_status, i);
115
116 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
117}
118EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
119
120u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
121 int lane)
122{
123 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
124 int s = ((lane & 1) ?
125 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
126 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
127 u8 l = dp_link_status(link_status, i);
128
129 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
130}
131EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
132
133u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE],
134 unsigned int lane)
135{
136 unsigned int offset = DP_ADJUST_REQUEST_POST_CURSOR2;
137 u8 value = dp_link_status(link_status, offset);
138
139 return (value >> (lane << 1)) & 0x3;
140}
141EXPORT_SYMBOL(drm_dp_get_adjust_request_post_cursor);
142
143void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
144 const u8 dpcd[DP_RECEIVER_CAP_SIZE])
145{
146 unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
147 DP_TRAINING_AUX_RD_MASK;
148
149 if (rd_interval > 4)
150 drm_dbg_kms(aux->drm_dev, "%s: AUX interval %lu, out of range (max 4)\n",
151 aux->name, rd_interval);
152
153 if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
154 rd_interval = 100;
155 else
156 rd_interval *= 4 * USEC_PER_MSEC;
157
158 usleep_range(rd_interval, rd_interval * 2);
159}
160EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
161
162static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
163 unsigned long rd_interval)
164{
165 if (rd_interval > 4)
166 drm_dbg_kms(aux->drm_dev, "%s: AUX interval %lu, out of range (max 4)\n",
167 aux->name, rd_interval);
168
169 if (rd_interval == 0)
170 rd_interval = 400;
171 else
172 rd_interval *= 4 * USEC_PER_MSEC;
173
174 usleep_range(rd_interval, rd_interval * 2);
175}
176
177void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
178 const u8 dpcd[DP_RECEIVER_CAP_SIZE])
179{
180 __drm_dp_link_train_channel_eq_delay(aux,
181 dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
182 DP_TRAINING_AUX_RD_MASK);
183}
184EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
185
186void drm_dp_lttpr_link_train_clock_recovery_delay(void)
187{
188 usleep_range(100, 200);
189}
190EXPORT_SYMBOL(drm_dp_lttpr_link_train_clock_recovery_delay);
191
192static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r)
193{
194 return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1];
195}
196
197void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
198 const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE])
199{
200 u8 interval = dp_lttpr_phy_cap(phy_cap,
201 DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) &
202 DP_TRAINING_AUX_RD_MASK;
203
204 __drm_dp_link_train_channel_eq_delay(aux, interval);
205}
206EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay);
207
208u8 drm_dp_link_rate_to_bw_code(int link_rate)
209{
210
211 return link_rate / 27000;
212}
213EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
214
215int drm_dp_bw_code_to_link_rate(u8 link_bw)
216{
217
218 return link_bw * 27000;
219}
220EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
221
222#define AUX_RETRY_INTERVAL 500
223
224static inline void
225drm_dp_dump_access(const struct drm_dp_aux *aux,
226 u8 request, uint offset, void *buffer, int ret)
227{
228 const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-";
229
230 if (ret > 0)
231 drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d) %*ph\n",
232 aux->name, offset, arrow, ret, min(ret, 20), buffer);
233 else
234 drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d)\n",
235 aux->name, offset, arrow, ret);
236}
237
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247
248
249
250static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,
251 unsigned int offset, void *buffer, size_t size)
252{
253 struct drm_dp_aux_msg msg;
254 unsigned int retry, native_reply;
255 int err = 0, ret = 0;
256
257 memset(&msg, 0, sizeof(msg));
258 msg.address = offset;
259 msg.request = request;
260 msg.buffer = buffer;
261 msg.size = size;
262
263 mutex_lock(&aux->hw_mutex);
264
265
266
267
268
269
270
271 for (retry = 0; retry < 32; retry++) {
272 if (ret != 0 && ret != -ETIMEDOUT) {
273 usleep_range(AUX_RETRY_INTERVAL,
274 AUX_RETRY_INTERVAL + 100);
275 }
276
277 ret = aux->transfer(aux, &msg);
278 if (ret >= 0) {
279 native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK;
280 if (native_reply == DP_AUX_NATIVE_REPLY_ACK) {
281 if (ret == size)
282 goto unlock;
283
284 ret = -EPROTO;
285 } else
286 ret = -EIO;
287 }
288
289
290
291
292
293
294 if (!err)
295 err = ret;
296 }
297
298 drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up. First error: %d\n",
299 aux->name, err);
300 ret = err;
301
302unlock:
303 mutex_unlock(&aux->hw_mutex);
304 return ret;
305}
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316
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320
321ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
322 void *buffer, size_t size)
323{
324 int ret;
325
326
327
328
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330
331
332
333
334
335
336
337
338 if (!aux->is_remote) {
339 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, DP_DPCD_REV,
340 buffer, 1);
341 if (ret != 1)
342 goto out;
343 }
344
345 if (aux->is_remote)
346 ret = drm_dp_mst_dpcd_read(aux, offset, buffer, size);
347 else
348 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset,
349 buffer, size);
350
351out:
352 drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer, ret);
353 return ret;
354}
355EXPORT_SYMBOL(drm_dp_dpcd_read);
356
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370
371ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
372 void *buffer, size_t size)
373{
374 int ret;
375
376 if (aux->is_remote)
377 ret = drm_dp_mst_dpcd_write(aux, offset, buffer, size);
378 else
379 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset,
380 buffer, size);
381
382 drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret);
383 return ret;
384}
385EXPORT_SYMBOL(drm_dp_dpcd_write);
386
387
388
389
390
391
392
393
394
395int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
396 u8 status[DP_LINK_STATUS_SIZE])
397{
398 return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status,
399 DP_LINK_STATUS_SIZE);
400}
401EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
402
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414
415
416int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
417 enum drm_dp_phy dp_phy,
418 u8 link_status[DP_LINK_STATUS_SIZE])
419{
420 int ret;
421
422 if (dp_phy == DP_PHY_DPRX) {
423 ret = drm_dp_dpcd_read(aux,
424 DP_LANE0_1_STATUS,
425 link_status,
426 DP_LINK_STATUS_SIZE);
427
428 if (ret < 0)
429 return ret;
430
431 WARN_ON(ret != DP_LINK_STATUS_SIZE);
432
433 return 0;
434 }
435
436 ret = drm_dp_dpcd_read(aux,
437 DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy),
438 link_status,
439 DP_LINK_STATUS_SIZE - 1);
440
441 if (ret < 0)
442 return ret;
443
444 WARN_ON(ret != DP_LINK_STATUS_SIZE - 1);
445
446
447 memmove(&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS + 1],
448 &link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS],
449 DP_LINK_STATUS_SIZE - (DP_SINK_STATUS - DP_LANE0_1_STATUS) - 1);
450 link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS] = 0;
451
452 return 0;
453}
454EXPORT_SYMBOL(drm_dp_dpcd_read_phy_link_status);
455
456static bool is_edid_digital_input_dp(const struct edid *edid)
457{
458 return edid && edid->revision >= 4 &&
459 edid->input & DRM_EDID_INPUT_DIGITAL &&
460 (edid->input & DRM_EDID_DIGITAL_TYPE_MASK) == DRM_EDID_DIGITAL_TYPE_DP;
461}
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475
476bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
477 const u8 port_cap[4], u8 type)
478{
479 return drm_dp_is_branch(dpcd) &&
480 dpcd[DP_DPCD_REV] >= 0x11 &&
481 (port_cap[0] & DP_DS_PORT_TYPE_MASK) == type;
482}
483EXPORT_SYMBOL(drm_dp_downstream_is_type);
484
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491
492
493bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
494 const u8 port_cap[4],
495 const struct edid *edid)
496{
497 if (dpcd[DP_DPCD_REV] < 0x11) {
498 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
499 case DP_DWN_STRM_PORT_TYPE_TMDS:
500 return true;
501 default:
502 return false;
503 }
504 }
505
506 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
507 case DP_DS_PORT_TYPE_DP_DUALMODE:
508 if (is_edid_digital_input_dp(edid))
509 return false;
510 fallthrough;
511 case DP_DS_PORT_TYPE_DVI:
512 case DP_DS_PORT_TYPE_HDMI:
513 return true;
514 default:
515 return false;
516 }
517}
518EXPORT_SYMBOL(drm_dp_downstream_is_tmds);
519
520
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522
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526
527
528bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
529 u8 real_edid_checksum)
530{
531 u8 link_edid_read = 0, auto_test_req = 0, test_resp = 0;
532
533 if (drm_dp_dpcd_read(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
534 &auto_test_req, 1) < 1) {
535 drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n",
536 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR);
537 return false;
538 }
539 auto_test_req &= DP_AUTOMATED_TEST_REQUEST;
540
541 if (drm_dp_dpcd_read(aux, DP_TEST_REQUEST, &link_edid_read, 1) < 1) {
542 drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n",
543 aux->name, DP_TEST_REQUEST);
544 return false;
545 }
546 link_edid_read &= DP_TEST_LINK_EDID_READ;
547
548 if (!auto_test_req || !link_edid_read) {
549 drm_dbg_kms(aux->drm_dev, "%s: Source DUT does not support TEST_EDID_READ\n",
550 aux->name);
551 return false;
552 }
553
554 if (drm_dp_dpcd_write(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
555 &auto_test_req, 1) < 1) {
556 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",
557 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR);
558 return false;
559 }
560
561
562 if (drm_dp_dpcd_write(aux, DP_TEST_EDID_CHECKSUM,
563 &real_edid_checksum, 1) < 1) {
564 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",
565 aux->name, DP_TEST_EDID_CHECKSUM);
566 return false;
567 }
568
569 test_resp |= DP_TEST_EDID_CHECKSUM_WRITE;
570 if (drm_dp_dpcd_write(aux, DP_TEST_RESPONSE, &test_resp, 1) < 1) {
571 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",
572 aux->name, DP_TEST_RESPONSE);
573 return false;
574 }
575
576 return true;
577}
578EXPORT_SYMBOL(drm_dp_send_real_edid_checksum);
579
580static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
581{
582 u8 port_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK;
583
584 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE && port_count > 4)
585 port_count = 4;
586
587 return port_count;
588}
589
590static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux,
591 u8 dpcd[DP_RECEIVER_CAP_SIZE])
592{
593 u8 dpcd_ext[6];
594 int ret;
595
596
597
598
599
600
601
602
603 if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
604 DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
605 return 0;
606
607 ret = drm_dp_dpcd_read(aux, DP_DP13_DPCD_REV, &dpcd_ext,
608 sizeof(dpcd_ext));
609 if (ret < 0)
610 return ret;
611 if (ret != sizeof(dpcd_ext))
612 return -EIO;
613
614 if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
615 drm_dbg_kms(aux->drm_dev,
616 "%s: Extended DPCD rev less than base DPCD rev (%d > %d)\n",
617 aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]);
618 return 0;
619 }
620
621 if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext)))
622 return 0;
623
624 drm_dbg_kms(aux->drm_dev, "%s: Base DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd);
625
626 memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext));
627
628 return 0;
629}
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
645 u8 dpcd[DP_RECEIVER_CAP_SIZE])
646{
647 int ret;
648
649 ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE);
650 if (ret < 0)
651 return ret;
652 if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0)
653 return -EIO;
654
655 ret = drm_dp_read_extended_dpcd_caps(aux, dpcd);
656 if (ret < 0)
657 return ret;
658
659 drm_dbg_kms(aux->drm_dev, "%s: DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd);
660
661 return ret;
662}
663EXPORT_SYMBOL(drm_dp_read_dpcd_caps);
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
679 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
680 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS])
681{
682 int ret;
683 u8 len;
684
685 memset(downstream_ports, 0, DP_MAX_DOWNSTREAM_PORTS);
686
687
688 if (!drm_dp_is_branch(dpcd) || dpcd[DP_DPCD_REV] == DP_DPCD_REV_10)
689 return 0;
690
691
692
693
694
695 len = drm_dp_downstream_port_count(dpcd);
696 if (!len)
697 return 0;
698
699 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE)
700 len *= 4;
701
702 ret = drm_dp_dpcd_read(aux, DP_DOWNSTREAM_PORT_0, downstream_ports, len);
703 if (ret < 0)
704 return ret;
705 if (ret != len)
706 return -EIO;
707
708 drm_dbg_kms(aux->drm_dev, "%s: DPCD DFP: %*ph\n", aux->name, len, downstream_ports);
709
710 return 0;
711}
712EXPORT_SYMBOL(drm_dp_read_downstream_info);
713
714
715
716
717
718
719
720
721
722int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
723 const u8 port_cap[4])
724{
725 if (!drm_dp_is_branch(dpcd))
726 return 0;
727
728 if (dpcd[DP_DPCD_REV] < 0x11)
729 return 0;
730
731 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
732 case DP_DS_PORT_TYPE_VGA:
733 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
734 return 0;
735 return port_cap[1] * 8000;
736 default:
737 return 0;
738 }
739}
740EXPORT_SYMBOL(drm_dp_downstream_max_dotclock);
741
742
743
744
745
746
747
748
749
750
751int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
752 const u8 port_cap[4],
753 const struct edid *edid)
754{
755 if (!drm_dp_is_branch(dpcd))
756 return 0;
757
758 if (dpcd[DP_DPCD_REV] < 0x11) {
759 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
760 case DP_DWN_STRM_PORT_TYPE_TMDS:
761 return 165000;
762 default:
763 return 0;
764 }
765 }
766
767 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
768 case DP_DS_PORT_TYPE_DP_DUALMODE:
769 if (is_edid_digital_input_dp(edid))
770 return 0;
771
772
773
774
775
776
777
778
779 fallthrough;
780 case DP_DS_PORT_TYPE_HDMI:
781
782
783
784
785
786
787
788
789
790
791
792
793 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
794 return 300000;
795 return port_cap[1] * 2500;
796 case DP_DS_PORT_TYPE_DVI:
797 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
798 return 165000;
799
800 return port_cap[1] * 2500;
801 default:
802 return 0;
803 }
804}
805EXPORT_SYMBOL(drm_dp_downstream_max_tmds_clock);
806
807
808
809
810
811
812
813
814
815
816int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
817 const u8 port_cap[4],
818 const struct edid *edid)
819{
820 if (!drm_dp_is_branch(dpcd))
821 return 0;
822
823 if (dpcd[DP_DPCD_REV] < 0x11) {
824 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
825 case DP_DWN_STRM_PORT_TYPE_TMDS:
826 return 25000;
827 default:
828 return 0;
829 }
830 }
831
832 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
833 case DP_DS_PORT_TYPE_DP_DUALMODE:
834 if (is_edid_digital_input_dp(edid))
835 return 0;
836 fallthrough;
837 case DP_DS_PORT_TYPE_DVI:
838 case DP_DS_PORT_TYPE_HDMI:
839
840
841
842
843 return 25000;
844 default:
845 return 0;
846 }
847}
848EXPORT_SYMBOL(drm_dp_downstream_min_tmds_clock);
849
850
851
852
853
854
855
856
857
858
859int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
860 const u8 port_cap[4],
861 const struct edid *edid)
862{
863 if (!drm_dp_is_branch(dpcd))
864 return 0;
865
866 if (dpcd[DP_DPCD_REV] < 0x11) {
867 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
868 case DP_DWN_STRM_PORT_TYPE_DP:
869 return 0;
870 default:
871 return 8;
872 }
873 }
874
875 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
876 case DP_DS_PORT_TYPE_DP:
877 return 0;
878 case DP_DS_PORT_TYPE_DP_DUALMODE:
879 if (is_edid_digital_input_dp(edid))
880 return 0;
881 fallthrough;
882 case DP_DS_PORT_TYPE_HDMI:
883 case DP_DS_PORT_TYPE_DVI:
884 case DP_DS_PORT_TYPE_VGA:
885 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
886 return 8;
887
888 switch (port_cap[2] & DP_DS_MAX_BPC_MASK) {
889 case DP_DS_8BPC:
890 return 8;
891 case DP_DS_10BPC:
892 return 10;
893 case DP_DS_12BPC:
894 return 12;
895 case DP_DS_16BPC:
896 return 16;
897 default:
898 return 8;
899 }
900 break;
901 default:
902 return 8;
903 }
904}
905EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
906
907
908
909
910
911
912
913
914
915bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
916 const u8 port_cap[4])
917{
918 if (!drm_dp_is_branch(dpcd))
919 return false;
920
921 if (dpcd[DP_DPCD_REV] < 0x13)
922 return false;
923
924 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
925 case DP_DS_PORT_TYPE_DP:
926 return true;
927 case DP_DS_PORT_TYPE_HDMI:
928 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
929 return false;
930
931 return port_cap[3] & DP_DS_HDMI_YCBCR420_PASS_THROUGH;
932 default:
933 return false;
934 }
935}
936EXPORT_SYMBOL(drm_dp_downstream_420_passthrough);
937
938
939
940
941
942
943
944
945
946bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
947 const u8 port_cap[4])
948{
949 if (!drm_dp_is_branch(dpcd))
950 return false;
951
952 if (dpcd[DP_DPCD_REV] < 0x13)
953 return false;
954
955 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
956 case DP_DS_PORT_TYPE_HDMI:
957 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
958 return false;
959
960 return port_cap[3] & DP_DS_HDMI_YCBCR444_TO_420_CONV;
961 default:
962 return false;
963 }
964}
965EXPORT_SYMBOL(drm_dp_downstream_444_to_420_conversion);
966
967
968
969
970
971
972
973
974
975
976
977bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
978 const u8 port_cap[4],
979 u8 color_spc)
980{
981 if (!drm_dp_is_branch(dpcd))
982 return false;
983
984 if (dpcd[DP_DPCD_REV] < 0x13)
985 return false;
986
987 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
988 case DP_DS_PORT_TYPE_HDMI:
989 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
990 return false;
991
992 return port_cap[3] & color_spc;
993 default:
994 return false;
995 }
996}
997EXPORT_SYMBOL(drm_dp_downstream_rgb_to_ycbcr_conversion);
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009struct drm_display_mode *
1010drm_dp_downstream_mode(struct drm_device *dev,
1011 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1012 const u8 port_cap[4])
1013
1014{
1015 u8 vic;
1016
1017 if (!drm_dp_is_branch(dpcd))
1018 return NULL;
1019
1020 if (dpcd[DP_DPCD_REV] < 0x11)
1021 return NULL;
1022
1023 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1024 case DP_DS_PORT_TYPE_NON_EDID:
1025 switch (port_cap[0] & DP_DS_NON_EDID_MASK) {
1026 case DP_DS_NON_EDID_720x480i_60:
1027 vic = 6;
1028 break;
1029 case DP_DS_NON_EDID_720x480i_50:
1030 vic = 21;
1031 break;
1032 case DP_DS_NON_EDID_1920x1080i_60:
1033 vic = 5;
1034 break;
1035 case DP_DS_NON_EDID_1920x1080i_50:
1036 vic = 20;
1037 break;
1038 case DP_DS_NON_EDID_1280x720_60:
1039 vic = 4;
1040 break;
1041 case DP_DS_NON_EDID_1280x720_50:
1042 vic = 19;
1043 break;
1044 default:
1045 return NULL;
1046 }
1047 return drm_display_mode_from_cea_vic(dev, vic);
1048 default:
1049 return NULL;
1050 }
1051}
1052EXPORT_SYMBOL(drm_dp_downstream_mode);
1053
1054
1055
1056
1057
1058
1059
1060
1061int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6])
1062{
1063 return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6);
1064}
1065EXPORT_SYMBOL(drm_dp_downstream_id);
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076void drm_dp_downstream_debug(struct seq_file *m,
1077 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1078 const u8 port_cap[4],
1079 const struct edid *edid,
1080 struct drm_dp_aux *aux)
1081{
1082 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1083 DP_DETAILED_CAP_INFO_AVAILABLE;
1084 int clk;
1085 int bpc;
1086 char id[7];
1087 int len;
1088 uint8_t rev[2];
1089 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
1090 bool branch_device = drm_dp_is_branch(dpcd);
1091
1092 seq_printf(m, "\tDP branch device present: %s\n",
1093 branch_device ? "yes" : "no");
1094
1095 if (!branch_device)
1096 return;
1097
1098 switch (type) {
1099 case DP_DS_PORT_TYPE_DP:
1100 seq_puts(m, "\t\tType: DisplayPort\n");
1101 break;
1102 case DP_DS_PORT_TYPE_VGA:
1103 seq_puts(m, "\t\tType: VGA\n");
1104 break;
1105 case DP_DS_PORT_TYPE_DVI:
1106 seq_puts(m, "\t\tType: DVI\n");
1107 break;
1108 case DP_DS_PORT_TYPE_HDMI:
1109 seq_puts(m, "\t\tType: HDMI\n");
1110 break;
1111 case DP_DS_PORT_TYPE_NON_EDID:
1112 seq_puts(m, "\t\tType: others without EDID support\n");
1113 break;
1114 case DP_DS_PORT_TYPE_DP_DUALMODE:
1115 seq_puts(m, "\t\tType: DP++\n");
1116 break;
1117 case DP_DS_PORT_TYPE_WIRELESS:
1118 seq_puts(m, "\t\tType: Wireless\n");
1119 break;
1120 default:
1121 seq_puts(m, "\t\tType: N/A\n");
1122 }
1123
1124 memset(id, 0, sizeof(id));
1125 drm_dp_downstream_id(aux, id);
1126 seq_printf(m, "\t\tID: %s\n", id);
1127
1128 len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &rev[0], 1);
1129 if (len > 0)
1130 seq_printf(m, "\t\tHW: %d.%d\n",
1131 (rev[0] & 0xf0) >> 4, rev[0] & 0xf);
1132
1133 len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, rev, 2);
1134 if (len > 0)
1135 seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]);
1136
1137 if (detailed_cap_info) {
1138 clk = drm_dp_downstream_max_dotclock(dpcd, port_cap);
1139 if (clk > 0)
1140 seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk);
1141
1142 clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, edid);
1143 if (clk > 0)
1144 seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk);
1145
1146 clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, edid);
1147 if (clk > 0)
1148 seq_printf(m, "\t\tMin TMDS clock: %d kHz\n", clk);
1149
1150 bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, edid);
1151
1152 if (bpc > 0)
1153 seq_printf(m, "\t\tMax bpc: %d\n", bpc);
1154 }
1155}
1156EXPORT_SYMBOL(drm_dp_downstream_debug);
1157
1158
1159
1160
1161
1162
1163enum drm_mode_subconnector
1164drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1165 const u8 port_cap[4])
1166{
1167 int type;
1168 if (!drm_dp_is_branch(dpcd))
1169 return DRM_MODE_SUBCONNECTOR_Native;
1170
1171 if (dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) {
1172 type = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1173 DP_DWN_STRM_PORT_TYPE_MASK;
1174
1175 switch (type) {
1176 case DP_DWN_STRM_PORT_TYPE_TMDS:
1177
1178 return DRM_MODE_SUBCONNECTOR_DVID;
1179 case DP_DWN_STRM_PORT_TYPE_ANALOG:
1180
1181 return DRM_MODE_SUBCONNECTOR_VGA;
1182 case DP_DWN_STRM_PORT_TYPE_DP:
1183 return DRM_MODE_SUBCONNECTOR_DisplayPort;
1184 case DP_DWN_STRM_PORT_TYPE_OTHER:
1185 default:
1186 return DRM_MODE_SUBCONNECTOR_Unknown;
1187 }
1188 }
1189 type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
1190
1191 switch (type) {
1192 case DP_DS_PORT_TYPE_DP:
1193 case DP_DS_PORT_TYPE_DP_DUALMODE:
1194 return DRM_MODE_SUBCONNECTOR_DisplayPort;
1195 case DP_DS_PORT_TYPE_VGA:
1196 return DRM_MODE_SUBCONNECTOR_VGA;
1197 case DP_DS_PORT_TYPE_DVI:
1198 return DRM_MODE_SUBCONNECTOR_DVID;
1199 case DP_DS_PORT_TYPE_HDMI:
1200 return DRM_MODE_SUBCONNECTOR_HDMIA;
1201 case DP_DS_PORT_TYPE_WIRELESS:
1202 return DRM_MODE_SUBCONNECTOR_Wireless;
1203 case DP_DS_PORT_TYPE_NON_EDID:
1204 default:
1205 return DRM_MODE_SUBCONNECTOR_Unknown;
1206 }
1207}
1208EXPORT_SYMBOL(drm_dp_subconnector_type);
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219void drm_dp_set_subconnector_property(struct drm_connector *connector,
1220 enum drm_connector_status status,
1221 const u8 *dpcd,
1222 const u8 port_cap[4])
1223{
1224 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
1225
1226 if (status == connector_status_connected)
1227 subconnector = drm_dp_subconnector_type(dpcd, port_cap);
1228 drm_object_property_set_value(&connector->base,
1229 connector->dev->mode_config.dp_subconnector_property,
1230 subconnector);
1231}
1232EXPORT_SYMBOL(drm_dp_set_subconnector_property);
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
1247 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1248 const struct drm_dp_desc *desc)
1249{
1250
1251 return connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
1252 dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 &&
1253 dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
1254 !drm_dp_has_quirk(desc, DP_DPCD_QUIRK_NO_SINK_COUNT);
1255}
1256EXPORT_SYMBOL(drm_dp_read_sink_count_cap);
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267int drm_dp_read_sink_count(struct drm_dp_aux *aux)
1268{
1269 u8 count;
1270 int ret;
1271
1272 ret = drm_dp_dpcd_readb(aux, DP_SINK_COUNT, &count);
1273 if (ret < 0)
1274 return ret;
1275 if (ret != 1)
1276 return -EIO;
1277
1278 return DP_GET_SINK_COUNT(count);
1279}
1280EXPORT_SYMBOL(drm_dp_read_sink_count);
1281
1282
1283
1284
1285
1286static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter)
1287{
1288 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
1289 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
1290 I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
1291 I2C_FUNC_10BIT_ADDR;
1292}
1293
1294static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg)
1295{
1296
1297
1298
1299
1300
1301 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) {
1302 msg->request &= DP_AUX_I2C_MOT;
1303 msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE;
1304 }
1305}
1306
1307#define AUX_PRECHARGE_LEN 10
1308#define AUX_SYNC_LEN (16 + 4)
1309#define AUX_STOP_LEN 4
1310#define AUX_CMD_LEN 4
1311#define AUX_ADDRESS_LEN 20
1312#define AUX_REPLY_PAD_LEN 4
1313#define AUX_LENGTH_LEN 8
1314
1315
1316
1317
1318
1319static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg)
1320{
1321 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
1322 AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN;
1323
1324 if ((msg->request & DP_AUX_I2C_READ) == 0)
1325 len += msg->size * 8;
1326
1327 return len;
1328}
1329
1330static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg)
1331{
1332 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
1333 AUX_CMD_LEN + AUX_REPLY_PAD_LEN;
1334
1335
1336
1337
1338
1339 if (msg->request & DP_AUX_I2C_READ)
1340 len += msg->size * 8;
1341
1342 return len;
1343}
1344
1345#define I2C_START_LEN 1
1346#define I2C_STOP_LEN 1
1347#define I2C_ADDR_LEN 9
1348#define I2C_DATA_LEN 9
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg,
1359 int i2c_speed_khz)
1360{
1361
1362 return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN +
1363 msg->size * I2C_DATA_LEN +
1364 I2C_STOP_LEN) * 1000, i2c_speed_khz);
1365}
1366
1367
1368
1369
1370
1371
1372static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg,
1373 int i2c_speed_khz)
1374{
1375 int aux_time_us = drm_dp_aux_req_duration(msg) +
1376 drm_dp_aux_reply_duration(msg);
1377 int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz);
1378
1379 return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL);
1380}
1381
1382
1383
1384
1385
1386static int dp_aux_i2c_speed_khz __read_mostly = 10;
1387module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644);
1388MODULE_PARM_DESC(dp_aux_i2c_speed_khz,
1389 "Assumed speed of the i2c bus in kHz, (1-400, default 10)");
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1400{
1401 unsigned int retry, defer_i2c;
1402 int ret;
1403
1404
1405
1406
1407
1408
1409
1410 int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz));
1411
1412 for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) {
1413 ret = aux->transfer(aux, msg);
1414 if (ret < 0) {
1415 if (ret == -EBUSY)
1416 continue;
1417
1418
1419
1420
1421
1422
1423
1424 if (ret == -ETIMEDOUT)
1425 drm_dbg_kms_ratelimited(aux->drm_dev, "%s: transaction timed out\n",
1426 aux->name);
1427 else
1428 drm_dbg_kms(aux->drm_dev, "%s: transaction failed: %d\n",
1429 aux->name, ret);
1430 return ret;
1431 }
1432
1433
1434 switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) {
1435 case DP_AUX_NATIVE_REPLY_ACK:
1436
1437
1438
1439
1440 break;
1441
1442 case DP_AUX_NATIVE_REPLY_NACK:
1443 drm_dbg_kms(aux->drm_dev, "%s: native nack (result=%d, size=%zu)\n",
1444 aux->name, ret, msg->size);
1445 return -EREMOTEIO;
1446
1447 case DP_AUX_NATIVE_REPLY_DEFER:
1448 drm_dbg_kms(aux->drm_dev, "%s: native defer\n", aux->name);
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
1459 continue;
1460
1461 default:
1462 drm_err(aux->drm_dev, "%s: invalid native reply %#04x\n",
1463 aux->name, msg->reply);
1464 return -EREMOTEIO;
1465 }
1466
1467 switch (msg->reply & DP_AUX_I2C_REPLY_MASK) {
1468 case DP_AUX_I2C_REPLY_ACK:
1469
1470
1471
1472
1473 if (ret != msg->size)
1474 drm_dp_i2c_msg_write_status_update(msg);
1475 return ret;
1476
1477 case DP_AUX_I2C_REPLY_NACK:
1478 drm_dbg_kms(aux->drm_dev, "%s: I2C nack (result=%d, size=%zu)\n",
1479 aux->name, ret, msg->size);
1480 aux->i2c_nack_count++;
1481 return -EREMOTEIO;
1482
1483 case DP_AUX_I2C_REPLY_DEFER:
1484 drm_dbg_kms(aux->drm_dev, "%s: I2C defer\n", aux->name);
1485
1486
1487
1488
1489 aux->i2c_defer_count++;
1490 if (defer_i2c < 7)
1491 defer_i2c++;
1492 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
1493 drm_dp_i2c_msg_write_status_update(msg);
1494
1495 continue;
1496
1497 default:
1498 drm_err(aux->drm_dev, "%s: invalid I2C reply %#04x\n",
1499 aux->name, msg->reply);
1500 return -EREMOTEIO;
1501 }
1502 }
1503
1504 drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up\n", aux->name);
1505 return -EREMOTEIO;
1506}
1507
1508static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg,
1509 const struct i2c_msg *i2c_msg)
1510{
1511 msg->request = (i2c_msg->flags & I2C_M_RD) ?
1512 DP_AUX_I2C_READ : DP_AUX_I2C_WRITE;
1513 if (!(i2c_msg->flags & I2C_M_STOP))
1514 msg->request |= DP_AUX_I2C_MOT;
1515}
1516
1517
1518
1519
1520
1521
1522static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg)
1523{
1524 int err, ret = orig_msg->size;
1525 struct drm_dp_aux_msg msg = *orig_msg;
1526
1527 while (msg.size > 0) {
1528 err = drm_dp_i2c_do_msg(aux, &msg);
1529 if (err <= 0)
1530 return err == 0 ? -EPROTO : err;
1531
1532 if (err < msg.size && err < ret) {
1533 drm_dbg_kms(aux->drm_dev,
1534 "%s: Partial I2C reply: requested %zu bytes got %d bytes\n",
1535 aux->name, msg.size, err);
1536 ret = err;
1537 }
1538
1539 msg.size -= err;
1540 msg.buffer += err;
1541 }
1542
1543 return ret;
1544}
1545
1546
1547
1548
1549
1550
1551static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES;
1552module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644);
1553MODULE_PARM_DESC(dp_aux_i2c_transfer_size,
1554 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)");
1555
1556static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs,
1557 int num)
1558{
1559 struct drm_dp_aux *aux = adapter->algo_data;
1560 unsigned int i, j;
1561 unsigned transfer_size;
1562 struct drm_dp_aux_msg msg;
1563 int err = 0;
1564
1565 dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES);
1566
1567 memset(&msg, 0, sizeof(msg));
1568
1569 for (i = 0; i < num; i++) {
1570 msg.address = msgs[i].addr;
1571 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
1572
1573
1574
1575
1576 msg.buffer = NULL;
1577 msg.size = 0;
1578 err = drm_dp_i2c_do_msg(aux, &msg);
1579
1580
1581
1582
1583
1584 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
1585
1586 if (err < 0)
1587 break;
1588
1589
1590
1591
1592 transfer_size = dp_aux_i2c_transfer_size;
1593 for (j = 0; j < msgs[i].len; j += msg.size) {
1594 msg.buffer = msgs[i].buf + j;
1595 msg.size = min(transfer_size, msgs[i].len - j);
1596
1597 err = drm_dp_i2c_drain_msg(aux, &msg);
1598
1599
1600
1601
1602
1603 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
1604
1605 if (err < 0)
1606 break;
1607 transfer_size = err;
1608 }
1609 if (err < 0)
1610 break;
1611 }
1612 if (err >= 0)
1613 err = num;
1614
1615
1616
1617
1618 msg.request &= ~DP_AUX_I2C_MOT;
1619 msg.buffer = NULL;
1620 msg.size = 0;
1621 (void)drm_dp_i2c_do_msg(aux, &msg);
1622
1623 return err;
1624}
1625
1626static const struct i2c_algorithm drm_dp_i2c_algo = {
1627 .functionality = drm_dp_i2c_functionality,
1628 .master_xfer = drm_dp_i2c_xfer,
1629};
1630
1631static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c)
1632{
1633 return container_of(i2c, struct drm_dp_aux, ddc);
1634}
1635
1636static void lock_bus(struct i2c_adapter *i2c, unsigned int flags)
1637{
1638 mutex_lock(&i2c_to_aux(i2c)->hw_mutex);
1639}
1640
1641static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags)
1642{
1643 return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex);
1644}
1645
1646static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags)
1647{
1648 mutex_unlock(&i2c_to_aux(i2c)->hw_mutex);
1649}
1650
1651static const struct i2c_lock_operations drm_dp_i2c_lock_ops = {
1652 .lock_bus = lock_bus,
1653 .trylock_bus = trylock_bus,
1654 .unlock_bus = unlock_bus,
1655};
1656
1657static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc)
1658{
1659 u8 buf, count;
1660 int ret;
1661
1662 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1663 if (ret < 0)
1664 return ret;
1665
1666 WARN_ON(!(buf & DP_TEST_SINK_START));
1667
1668 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK_MISC, &buf);
1669 if (ret < 0)
1670 return ret;
1671
1672 count = buf & DP_TEST_COUNT_MASK;
1673 if (count == aux->crc_count)
1674 return -EAGAIN;
1675
1676 aux->crc_count = count;
1677
1678
1679
1680
1681
1682 ret = drm_dp_dpcd_read(aux, DP_TEST_CRC_R_CR, crc, 6);
1683 if (ret < 0)
1684 return ret;
1685
1686 return 0;
1687}
1688
1689static void drm_dp_aux_crc_work(struct work_struct *work)
1690{
1691 struct drm_dp_aux *aux = container_of(work, struct drm_dp_aux,
1692 crc_work);
1693 struct drm_crtc *crtc;
1694 u8 crc_bytes[6];
1695 uint32_t crcs[3];
1696 int ret;
1697
1698 if (WARN_ON(!aux->crtc))
1699 return;
1700
1701 crtc = aux->crtc;
1702 while (crtc->crc.opened) {
1703 drm_crtc_wait_one_vblank(crtc);
1704 if (!crtc->crc.opened)
1705 break;
1706
1707 ret = drm_dp_aux_get_crc(aux, crc_bytes);
1708 if (ret == -EAGAIN) {
1709 usleep_range(1000, 2000);
1710 ret = drm_dp_aux_get_crc(aux, crc_bytes);
1711 }
1712
1713 if (ret == -EAGAIN) {
1714 drm_dbg_kms(aux->drm_dev, "%s: Get CRC failed after retrying: %d\n",
1715 aux->name, ret);
1716 continue;
1717 } else if (ret) {
1718 drm_dbg_kms(aux->drm_dev, "%s: Failed to get a CRC: %d\n", aux->name, ret);
1719 continue;
1720 }
1721
1722 crcs[0] = crc_bytes[0] | crc_bytes[1] << 8;
1723 crcs[1] = crc_bytes[2] | crc_bytes[3] << 8;
1724 crcs[2] = crc_bytes[4] | crc_bytes[5] << 8;
1725 drm_crtc_add_crc_entry(crtc, false, 0, crcs);
1726 }
1727}
1728
1729
1730
1731
1732
1733
1734
1735
1736void drm_dp_remote_aux_init(struct drm_dp_aux *aux)
1737{
1738 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
1739}
1740EXPORT_SYMBOL(drm_dp_remote_aux_init);
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759void drm_dp_aux_init(struct drm_dp_aux *aux)
1760{
1761 mutex_init(&aux->hw_mutex);
1762 mutex_init(&aux->cec.lock);
1763 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
1764
1765 aux->ddc.algo = &drm_dp_i2c_algo;
1766 aux->ddc.algo_data = aux;
1767 aux->ddc.retries = 3;
1768
1769 aux->ddc.lock_ops = &drm_dp_i2c_lock_ops;
1770}
1771EXPORT_SYMBOL(drm_dp_aux_init);
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800int drm_dp_aux_register(struct drm_dp_aux *aux)
1801{
1802 int ret;
1803
1804 WARN_ON_ONCE(!aux->drm_dev);
1805
1806 if (!aux->ddc.algo)
1807 drm_dp_aux_init(aux);
1808
1809 aux->ddc.class = I2C_CLASS_DDC;
1810 aux->ddc.owner = THIS_MODULE;
1811 aux->ddc.dev.parent = aux->dev;
1812
1813 strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev),
1814 sizeof(aux->ddc.name));
1815
1816 ret = drm_dp_aux_register_devnode(aux);
1817 if (ret)
1818 return ret;
1819
1820 ret = i2c_add_adapter(&aux->ddc);
1821 if (ret) {
1822 drm_dp_aux_unregister_devnode(aux);
1823 return ret;
1824 }
1825
1826 return 0;
1827}
1828EXPORT_SYMBOL(drm_dp_aux_register);
1829
1830
1831
1832
1833
1834void drm_dp_aux_unregister(struct drm_dp_aux *aux)
1835{
1836 drm_dp_aux_unregister_devnode(aux);
1837 i2c_del_adapter(&aux->ddc);
1838}
1839EXPORT_SYMBOL(drm_dp_aux_unregister);
1840
1841#define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x)
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
1852{
1853 static const u16 psr_setup_time_us[] = {
1854 PSR_SETUP_TIME(330),
1855 PSR_SETUP_TIME(275),
1856 PSR_SETUP_TIME(220),
1857 PSR_SETUP_TIME(165),
1858 PSR_SETUP_TIME(110),
1859 PSR_SETUP_TIME(55),
1860 PSR_SETUP_TIME(0),
1861 };
1862 int i;
1863
1864 i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT;
1865 if (i >= ARRAY_SIZE(psr_setup_time_us))
1866 return -EINVAL;
1867
1868 return psr_setup_time_us[i];
1869}
1870EXPORT_SYMBOL(drm_dp_psr_setup_time);
1871
1872#undef PSR_SETUP_TIME
1873
1874
1875
1876
1877
1878
1879
1880
1881int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc)
1882{
1883 u8 buf;
1884 int ret;
1885
1886 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1887 if (ret < 0)
1888 return ret;
1889
1890 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf | DP_TEST_SINK_START);
1891 if (ret < 0)
1892 return ret;
1893
1894 aux->crc_count = 0;
1895 aux->crtc = crtc;
1896 schedule_work(&aux->crc_work);
1897
1898 return 0;
1899}
1900EXPORT_SYMBOL(drm_dp_start_crc);
1901
1902
1903
1904
1905
1906
1907
1908int drm_dp_stop_crc(struct drm_dp_aux *aux)
1909{
1910 u8 buf;
1911 int ret;
1912
1913 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1914 if (ret < 0)
1915 return ret;
1916
1917 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf & ~DP_TEST_SINK_START);
1918 if (ret < 0)
1919 return ret;
1920
1921 flush_work(&aux->crc_work);
1922 aux->crtc = NULL;
1923
1924 return 0;
1925}
1926EXPORT_SYMBOL(drm_dp_stop_crc);
1927
1928struct dpcd_quirk {
1929 u8 oui[3];
1930 u8 device_id[6];
1931 bool is_branch;
1932 u32 quirks;
1933};
1934
1935#define OUI(first, second, third) { (first), (second), (third) }
1936#define DEVICE_ID(first, second, third, fourth, fifth, sixth) \
1937 { (first), (second), (third), (fourth), (fifth), (sixth) }
1938
1939#define DEVICE_ID_ANY DEVICE_ID(0, 0, 0, 0, 0, 0)
1940
1941static const struct dpcd_quirk dpcd_quirk_list[] = {
1942
1943 { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
1944
1945 { OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
1946
1947 { OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) },
1948
1949 { OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
1950
1951 { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
1952
1953 { OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
1954};
1955
1956#undef OUI
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966static u32
1967drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch)
1968{
1969 const struct dpcd_quirk *quirk;
1970 u32 quirks = 0;
1971 int i;
1972 u8 any_device[] = DEVICE_ID_ANY;
1973
1974 for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) {
1975 quirk = &dpcd_quirk_list[i];
1976
1977 if (quirk->is_branch != is_branch)
1978 continue;
1979
1980 if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0)
1981 continue;
1982
1983 if (memcmp(quirk->device_id, any_device, sizeof(any_device)) != 0 &&
1984 memcmp(quirk->device_id, ident->device_id, sizeof(ident->device_id)) != 0)
1985 continue;
1986
1987 quirks |= quirk->quirks;
1988 }
1989
1990 return quirks;
1991}
1992
1993#undef DEVICE_ID_ANY
1994#undef DEVICE_ID
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
2008 bool is_branch)
2009{
2010 struct drm_dp_dpcd_ident *ident = &desc->ident;
2011 unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI;
2012 int ret, dev_id_len;
2013
2014 ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident));
2015 if (ret < 0)
2016 return ret;
2017
2018 desc->quirks = drm_dp_get_quirks(ident, is_branch);
2019
2020 dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id));
2021
2022 drm_dbg_kms(aux->drm_dev,
2023 "%s: DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n",
2024 aux->name, is_branch ? "branch" : "sink",
2025 (int)sizeof(ident->oui), ident->oui, dev_id_len,
2026 ident->device_id, ident->hw_rev >> 4, ident->hw_rev & 0xf,
2027 ident->sw_major_rev, ident->sw_minor_rev, desc->quirks);
2028
2029 return 0;
2030}
2031EXPORT_SYMBOL(drm_dp_read_desc);
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
2050 bool is_edp)
2051{
2052 u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];
2053
2054 if (is_edp) {
2055
2056 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
2057 return 4;
2058 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
2059 return 2;
2060 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
2061 return 1;
2062 } else {
2063
2064 u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT];
2065
2066 if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK)
2067 return 24;
2068 if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK)
2069 return 20;
2070 if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK)
2071 return 16;
2072 if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK)
2073 return 12;
2074 if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK)
2075 return 10;
2076 if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK)
2077 return 8;
2078 if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK)
2079 return 6;
2080 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
2081 return 4;
2082 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
2083 return 2;
2084 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
2085 return 1;
2086 }
2087
2088 return 0;
2089}
2090EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
2108{
2109 u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT];
2110
2111 switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) {
2112 case DP_DSC_LINE_BUF_BIT_DEPTH_9:
2113 return 9;
2114 case DP_DSC_LINE_BUF_BIT_DEPTH_10:
2115 return 10;
2116 case DP_DSC_LINE_BUF_BIT_DEPTH_11:
2117 return 11;
2118 case DP_DSC_LINE_BUF_BIT_DEPTH_12:
2119 return 12;
2120 case DP_DSC_LINE_BUF_BIT_DEPTH_13:
2121 return 13;
2122 case DP_DSC_LINE_BUF_BIT_DEPTH_14:
2123 return 14;
2124 case DP_DSC_LINE_BUF_BIT_DEPTH_15:
2125 return 15;
2126 case DP_DSC_LINE_BUF_BIT_DEPTH_16:
2127 return 16;
2128 case DP_DSC_LINE_BUF_BIT_DEPTH_8:
2129 return 8;
2130 }
2131
2132 return 0;
2133}
2134EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
2154 u8 dsc_bpc[3])
2155{
2156 int num_bpc = 0;
2157 u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
2158
2159 if (color_depth & DP_DSC_12_BPC)
2160 dsc_bpc[num_bpc++] = 12;
2161 if (color_depth & DP_DSC_10_BPC)
2162 dsc_bpc[num_bpc++] = 10;
2163 if (color_depth & DP_DSC_8_BPC)
2164 dsc_bpc[num_bpc++] = 8;
2165
2166 return num_bpc;
2167}
2168EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
2180 u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2181{
2182 int ret;
2183
2184 ret = drm_dp_dpcd_read(aux,
2185 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
2186 caps, DP_LTTPR_COMMON_CAP_SIZE);
2187 if (ret < 0)
2188 return ret;
2189
2190 WARN_ON(ret != DP_LTTPR_COMMON_CAP_SIZE);
2191
2192 return 0;
2193}
2194EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps);
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
2207 enum drm_dp_phy dp_phy,
2208 u8 caps[DP_LTTPR_PHY_CAP_SIZE])
2209{
2210 int ret;
2211
2212 ret = drm_dp_dpcd_read(aux,
2213 DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy),
2214 caps, DP_LTTPR_PHY_CAP_SIZE);
2215 if (ret < 0)
2216 return ret;
2217
2218 WARN_ON(ret != DP_LTTPR_PHY_CAP_SIZE);
2219
2220 return 0;
2221}
2222EXPORT_SYMBOL(drm_dp_read_lttpr_phy_caps);
2223
2224static u8 dp_lttpr_common_cap(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE], int r)
2225{
2226 return caps[r - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
2227}
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240int drm_dp_lttpr_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2241{
2242 u8 count = dp_lttpr_common_cap(caps, DP_PHY_REPEATER_CNT);
2243
2244 switch (hweight8(count)) {
2245 case 0:
2246 return 0;
2247 case 1:
2248 return 8 - ilog2(count);
2249 case 8:
2250 return -ERANGE;
2251 default:
2252 return -EINVAL;
2253 }
2254}
2255EXPORT_SYMBOL(drm_dp_lttpr_count);
2256
2257
2258
2259
2260
2261
2262
2263int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2264{
2265 u8 rate = dp_lttpr_common_cap(caps, DP_MAX_LINK_RATE_PHY_REPEATER);
2266
2267 return drm_dp_bw_code_to_link_rate(rate);
2268}
2269EXPORT_SYMBOL(drm_dp_lttpr_max_link_rate);
2270
2271
2272
2273
2274
2275
2276
2277int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2278{
2279 u8 max_lanes = dp_lttpr_common_cap(caps, DP_MAX_LANE_COUNT_PHY_REPEATER);
2280
2281 return max_lanes & DP_MAX_LANE_COUNT_MASK;
2282}
2283EXPORT_SYMBOL(drm_dp_lttpr_max_lane_count);
2284
2285
2286
2287
2288
2289
2290
2291
2292bool
2293drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])
2294{
2295 u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);
2296
2297 return txcap & DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED;
2298}
2299EXPORT_SYMBOL(drm_dp_lttpr_voltage_swing_level_3_supported);
2300
2301
2302
2303
2304
2305
2306
2307
2308bool
2309drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])
2310{
2311 u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);
2312
2313 return txcap & DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED;
2314}
2315EXPORT_SYMBOL(drm_dp_lttpr_pre_emphasis_level_3_supported);
2316
2317
2318
2319
2320
2321
2322
2323
2324int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
2325 struct drm_dp_phy_test_params *data)
2326{
2327 int err;
2328 u8 rate, lanes;
2329
2330 err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate);
2331 if (err < 0)
2332 return err;
2333 data->link_rate = drm_dp_bw_code_to_link_rate(rate);
2334
2335 err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes);
2336 if (err < 0)
2337 return err;
2338 data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
2339
2340 if (lanes & DP_ENHANCED_FRAME_CAP)
2341 data->enhanced_frame_cap = true;
2342
2343 err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern);
2344 if (err < 0)
2345 return err;
2346
2347 switch (data->phy_pattern) {
2348 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
2349 err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
2350 &data->custom80, sizeof(data->custom80));
2351 if (err < 0)
2352 return err;
2353
2354 break;
2355 case DP_PHY_TEST_PATTERN_CP2520:
2356 err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
2357 &data->hbr2_reset,
2358 sizeof(data->hbr2_reset));
2359 if (err < 0)
2360 return err;
2361 }
2362
2363 return 0;
2364}
2365EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
2376 struct drm_dp_phy_test_params *data, u8 dp_rev)
2377{
2378 int err, i;
2379 u8 link_config[2];
2380 u8 test_pattern;
2381
2382 link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate);
2383 link_config[1] = data->num_lanes;
2384 if (data->enhanced_frame_cap)
2385 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2386 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2);
2387 if (err < 0)
2388 return err;
2389
2390 test_pattern = data->phy_pattern;
2391 if (dp_rev < 0x12) {
2392 test_pattern = (test_pattern << 2) &
2393 DP_LINK_QUAL_PATTERN_11_MASK;
2394 err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
2395 test_pattern);
2396 if (err < 0)
2397 return err;
2398 } else {
2399 for (i = 0; i < data->num_lanes; i++) {
2400 err = drm_dp_dpcd_writeb(aux,
2401 DP_LINK_QUAL_LANE0_SET + i,
2402 test_pattern);
2403 if (err < 0)
2404 return err;
2405 }
2406 }
2407
2408 return 0;
2409}
2410EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
2411
2412static const char *dp_pixelformat_get_name(enum dp_pixelformat pixelformat)
2413{
2414 if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
2415 return "Invalid";
2416
2417 switch (pixelformat) {
2418 case DP_PIXELFORMAT_RGB:
2419 return "RGB";
2420 case DP_PIXELFORMAT_YUV444:
2421 return "YUV444";
2422 case DP_PIXELFORMAT_YUV422:
2423 return "YUV422";
2424 case DP_PIXELFORMAT_YUV420:
2425 return "YUV420";
2426 case DP_PIXELFORMAT_Y_ONLY:
2427 return "Y_ONLY";
2428 case DP_PIXELFORMAT_RAW:
2429 return "RAW";
2430 default:
2431 return "Reserved";
2432 }
2433}
2434
2435static const char *dp_colorimetry_get_name(enum dp_pixelformat pixelformat,
2436 enum dp_colorimetry colorimetry)
2437{
2438 if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
2439 return "Invalid";
2440
2441 switch (colorimetry) {
2442 case DP_COLORIMETRY_DEFAULT:
2443 switch (pixelformat) {
2444 case DP_PIXELFORMAT_RGB:
2445 return "sRGB";
2446 case DP_PIXELFORMAT_YUV444:
2447 case DP_PIXELFORMAT_YUV422:
2448 case DP_PIXELFORMAT_YUV420:
2449 return "BT.601";
2450 case DP_PIXELFORMAT_Y_ONLY:
2451 return "DICOM PS3.14";
2452 case DP_PIXELFORMAT_RAW:
2453 return "Custom Color Profile";
2454 default:
2455 return "Reserved";
2456 }
2457 case DP_COLORIMETRY_RGB_WIDE_FIXED:
2458 switch (pixelformat) {
2459 case DP_PIXELFORMAT_RGB:
2460 return "Wide Fixed";
2461 case DP_PIXELFORMAT_YUV444:
2462 case DP_PIXELFORMAT_YUV422:
2463 case DP_PIXELFORMAT_YUV420:
2464 return "BT.709";
2465 default:
2466 return "Reserved";
2467 }
2468 case DP_COLORIMETRY_RGB_WIDE_FLOAT:
2469 switch (pixelformat) {
2470 case DP_PIXELFORMAT_RGB:
2471 return "Wide Float";
2472 case DP_PIXELFORMAT_YUV444:
2473 case DP_PIXELFORMAT_YUV422:
2474 case DP_PIXELFORMAT_YUV420:
2475 return "xvYCC 601";
2476 default:
2477 return "Reserved";
2478 }
2479 case DP_COLORIMETRY_OPRGB:
2480 switch (pixelformat) {
2481 case DP_PIXELFORMAT_RGB:
2482 return "OpRGB";
2483 case DP_PIXELFORMAT_YUV444:
2484 case DP_PIXELFORMAT_YUV422:
2485 case DP_PIXELFORMAT_YUV420:
2486 return "xvYCC 709";
2487 default:
2488 return "Reserved";
2489 }
2490 case DP_COLORIMETRY_DCI_P3_RGB:
2491 switch (pixelformat) {
2492 case DP_PIXELFORMAT_RGB:
2493 return "DCI-P3";
2494 case DP_PIXELFORMAT_YUV444:
2495 case DP_PIXELFORMAT_YUV422:
2496 case DP_PIXELFORMAT_YUV420:
2497 return "sYCC 601";
2498 default:
2499 return "Reserved";
2500 }
2501 case DP_COLORIMETRY_RGB_CUSTOM:
2502 switch (pixelformat) {
2503 case DP_PIXELFORMAT_RGB:
2504 return "Custom Profile";
2505 case DP_PIXELFORMAT_YUV444:
2506 case DP_PIXELFORMAT_YUV422:
2507 case DP_PIXELFORMAT_YUV420:
2508 return "OpYCC 601";
2509 default:
2510 return "Reserved";
2511 }
2512 case DP_COLORIMETRY_BT2020_RGB:
2513 switch (pixelformat) {
2514 case DP_PIXELFORMAT_RGB:
2515 return "BT.2020 RGB";
2516 case DP_PIXELFORMAT_YUV444:
2517 case DP_PIXELFORMAT_YUV422:
2518 case DP_PIXELFORMAT_YUV420:
2519 return "BT.2020 CYCC";
2520 default:
2521 return "Reserved";
2522 }
2523 case DP_COLORIMETRY_BT2020_YCC:
2524 switch (pixelformat) {
2525 case DP_PIXELFORMAT_YUV444:
2526 case DP_PIXELFORMAT_YUV422:
2527 case DP_PIXELFORMAT_YUV420:
2528 return "BT.2020 YCC";
2529 default:
2530 return "Reserved";
2531 }
2532 default:
2533 return "Invalid";
2534 }
2535}
2536
2537static const char *dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range)
2538{
2539 switch (dynamic_range) {
2540 case DP_DYNAMIC_RANGE_VESA:
2541 return "VESA range";
2542 case DP_DYNAMIC_RANGE_CTA:
2543 return "CTA range";
2544 default:
2545 return "Invalid";
2546 }
2547}
2548
2549static const char *dp_content_type_get_name(enum dp_content_type content_type)
2550{
2551 switch (content_type) {
2552 case DP_CONTENT_TYPE_NOT_DEFINED:
2553 return "Not defined";
2554 case DP_CONTENT_TYPE_GRAPHICS:
2555 return "Graphics";
2556 case DP_CONTENT_TYPE_PHOTO:
2557 return "Photo";
2558 case DP_CONTENT_TYPE_VIDEO:
2559 return "Video";
2560 case DP_CONTENT_TYPE_GAME:
2561 return "Game";
2562 default:
2563 return "Reserved";
2564 }
2565}
2566
2567void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
2568 const struct drm_dp_vsc_sdp *vsc)
2569{
2570#define DP_SDP_LOG(fmt, ...) dev_printk(level, dev, fmt, ##__VA_ARGS__)
2571 DP_SDP_LOG("DP SDP: %s, revision %u, length %u\n", "VSC",
2572 vsc->revision, vsc->length);
2573 DP_SDP_LOG(" pixelformat: %s\n",
2574 dp_pixelformat_get_name(vsc->pixelformat));
2575 DP_SDP_LOG(" colorimetry: %s\n",
2576 dp_colorimetry_get_name(vsc->pixelformat, vsc->colorimetry));
2577 DP_SDP_LOG(" bpc: %u\n", vsc->bpc);
2578 DP_SDP_LOG(" dynamic range: %s\n",
2579 dp_dynamic_range_get_name(vsc->dynamic_range));
2580 DP_SDP_LOG(" content type: %s\n",
2581 dp_content_type_get_name(vsc->content_type));
2582#undef DP_SDP_LOG
2583}
2584EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2595 const u8 port_cap[4])
2596{
2597 int bw;
2598 u8 buf;
2599
2600 buf = port_cap[2];
2601 bw = buf & DP_PCON_MAX_FRL_BW;
2602
2603 switch (bw) {
2604 case DP_PCON_MAX_9GBPS:
2605 return 9;
2606 case DP_PCON_MAX_18GBPS:
2607 return 18;
2608 case DP_PCON_MAX_24GBPS:
2609 return 24;
2610 case DP_PCON_MAX_32GBPS:
2611 return 32;
2612 case DP_PCON_MAX_40GBPS:
2613 return 40;
2614 case DP_PCON_MAX_48GBPS:
2615 return 48;
2616 case DP_PCON_MAX_0GBPS:
2617 default:
2618 return 0;
2619 }
2620
2621 return 0;
2622}
2623EXPORT_SYMBOL(drm_dp_get_pcon_max_frl_bw);
2624
2625
2626
2627
2628
2629
2630
2631
2632int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd)
2633{
2634 int ret;
2635 u8 buf = DP_PCON_ENABLE_SOURCE_CTL_MODE |
2636 DP_PCON_ENABLE_LINK_FRL_MODE;
2637
2638 if (enable_frl_ready_hpd)
2639 buf |= DP_PCON_ENABLE_HPD_READY;
2640
2641 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2642
2643 return ret;
2644}
2645EXPORT_SYMBOL(drm_dp_pcon_frl_prepare);
2646
2647
2648
2649
2650
2651
2652
2653bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux)
2654{
2655 int ret;
2656 u8 buf;
2657
2658 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf);
2659 if (ret < 0)
2660 return false;
2661
2662 if (buf & DP_PCON_FRL_READY)
2663 return true;
2664
2665 return false;
2666}
2667EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready);
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
2682 u8 frl_mode)
2683{
2684 int ret;
2685 u8 buf;
2686
2687 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf);
2688 if (ret < 0)
2689 return ret;
2690
2691 if (frl_mode == DP_PCON_ENABLE_CONCURRENT_LINK)
2692 buf |= DP_PCON_ENABLE_CONCURRENT_LINK;
2693 else
2694 buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK;
2695
2696 switch (max_frl_gbps) {
2697 case 9:
2698 buf |= DP_PCON_ENABLE_MAX_BW_9GBPS;
2699 break;
2700 case 18:
2701 buf |= DP_PCON_ENABLE_MAX_BW_18GBPS;
2702 break;
2703 case 24:
2704 buf |= DP_PCON_ENABLE_MAX_BW_24GBPS;
2705 break;
2706 case 32:
2707 buf |= DP_PCON_ENABLE_MAX_BW_32GBPS;
2708 break;
2709 case 40:
2710 buf |= DP_PCON_ENABLE_MAX_BW_40GBPS;
2711 break;
2712 case 48:
2713 buf |= DP_PCON_ENABLE_MAX_BW_48GBPS;
2714 break;
2715 case 0:
2716 buf |= DP_PCON_ENABLE_MAX_BW_0GBPS;
2717 break;
2718 default:
2719 return -EINVAL;
2720 }
2721
2722 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2723 if (ret < 0)
2724 return ret;
2725
2726 return 0;
2727}
2728EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1);
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
2742 u8 frl_type)
2743{
2744 int ret;
2745 u8 buf = max_frl_mask;
2746
2747 if (frl_type == DP_PCON_FRL_LINK_TRAIN_EXTENDED)
2748 buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED;
2749 else
2750 buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED;
2751
2752 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf);
2753 if (ret < 0)
2754 return ret;
2755
2756 return 0;
2757}
2758EXPORT_SYMBOL(drm_dp_pcon_frl_configure_2);
2759
2760
2761
2762
2763
2764
2765
2766int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux)
2767{
2768 int ret;
2769
2770 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, 0x0);
2771 if (ret < 0)
2772 return ret;
2773
2774 return 0;
2775}
2776EXPORT_SYMBOL(drm_dp_pcon_reset_frl_config);
2777
2778
2779
2780
2781
2782
2783
2784int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux)
2785{
2786 int ret;
2787 u8 buf = 0;
2788
2789 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf);
2790 if (ret < 0)
2791 return ret;
2792 if (!(buf & DP_PCON_ENABLE_SOURCE_CTL_MODE)) {
2793 drm_dbg_kms(aux->drm_dev, "%s: PCON in Autonomous mode, can't enable FRL\n",
2794 aux->name);
2795 return -EINVAL;
2796 }
2797 buf |= DP_PCON_ENABLE_HDMI_LINK;
2798 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2799 if (ret < 0)
2800 return ret;
2801
2802 return 0;
2803}
2804EXPORT_SYMBOL(drm_dp_pcon_frl_enable);
2805
2806
2807
2808
2809
2810
2811
2812bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux)
2813{
2814 u8 buf;
2815 int ret;
2816
2817 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf);
2818 if (ret < 0)
2819 return false;
2820
2821 return buf & DP_PCON_HDMI_TX_LINK_ACTIVE;
2822}
2823EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_active);
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask)
2837{
2838 u8 buf;
2839 int mode;
2840 int ret;
2841
2842 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_POST_FRL_STATUS, &buf);
2843 if (ret < 0)
2844 return ret;
2845
2846 mode = buf & DP_PCON_HDMI_LINK_MODE;
2847
2848 if (frl_trained_mask && DP_PCON_HDMI_MODE_FRL == mode)
2849 *frl_trained_mask = (buf & DP_PCON_HDMI_FRL_TRAINED_BW) >> 1;
2850
2851 return mode;
2852}
2853EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_mode);
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
2864 struct drm_connector *connector)
2865{
2866 u8 buf, error_count;
2867 int i, num_error;
2868 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
2869
2870 for (i = 0; i < hdmi->max_lanes; i++) {
2871 if (drm_dp_dpcd_readb(aux, DP_PCON_HDMI_ERROR_STATUS_LN0 + i, &buf) < 0)
2872 return;
2873
2874 error_count = buf & DP_PCON_HDMI_ERROR_COUNT_MASK;
2875 switch (error_count) {
2876 case DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS:
2877 num_error = 100;
2878 break;
2879 case DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS:
2880 num_error = 10;
2881 break;
2882 case DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS:
2883 num_error = 3;
2884 break;
2885 default:
2886 num_error = 0;
2887 }
2888
2889 drm_err(aux->drm_dev, "%s: More than %d errors since the last read for lane %d",
2890 aux->name, num_error, i);
2891 }
2892}
2893EXPORT_SYMBOL(drm_dp_pcon_hdmi_frl_link_error_count);
2894
2895
2896
2897
2898
2899
2900
2901bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
2902{
2903 u8 buf;
2904 u8 major_v, minor_v;
2905
2906 buf = pcon_dsc_dpcd[DP_PCON_DSC_VERSION - DP_PCON_DSC_ENCODER];
2907 major_v = (buf & DP_PCON_DSC_MAJOR_MASK) >> DP_PCON_DSC_MAJOR_SHIFT;
2908 minor_v = (buf & DP_PCON_DSC_MINOR_MASK) >> DP_PCON_DSC_MINOR_SHIFT;
2909
2910 if (major_v == 1 && minor_v == 2)
2911 return true;
2912
2913 return false;
2914}
2915EXPORT_SYMBOL(drm_dp_pcon_enc_is_dsc_1_2);
2916
2917
2918
2919
2920
2921
2922
2923int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
2924{
2925 u8 slice_cap1, slice_cap2;
2926
2927 slice_cap1 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_1 - DP_PCON_DSC_ENCODER];
2928 slice_cap2 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_2 - DP_PCON_DSC_ENCODER];
2929
2930 if (slice_cap2 & DP_PCON_DSC_24_PER_DSC_ENC)
2931 return 24;
2932 if (slice_cap2 & DP_PCON_DSC_20_PER_DSC_ENC)
2933 return 20;
2934 if (slice_cap2 & DP_PCON_DSC_16_PER_DSC_ENC)
2935 return 16;
2936 if (slice_cap1 & DP_PCON_DSC_12_PER_DSC_ENC)
2937 return 12;
2938 if (slice_cap1 & DP_PCON_DSC_10_PER_DSC_ENC)
2939 return 10;
2940 if (slice_cap1 & DP_PCON_DSC_8_PER_DSC_ENC)
2941 return 8;
2942 if (slice_cap1 & DP_PCON_DSC_6_PER_DSC_ENC)
2943 return 6;
2944 if (slice_cap1 & DP_PCON_DSC_4_PER_DSC_ENC)
2945 return 4;
2946 if (slice_cap1 & DP_PCON_DSC_2_PER_DSC_ENC)
2947 return 2;
2948 if (slice_cap1 & DP_PCON_DSC_1_PER_DSC_ENC)
2949 return 1;
2950
2951 return 0;
2952}
2953EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slices);
2954
2955
2956
2957
2958
2959
2960
2961int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
2962{
2963 u8 buf;
2964
2965 buf = pcon_dsc_dpcd[DP_PCON_DSC_MAX_SLICE_WIDTH - DP_PCON_DSC_ENCODER];
2966
2967 return buf * DP_DSC_SLICE_WIDTH_MULTIPLIER;
2968}
2969EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slice_width);
2970
2971
2972
2973
2974
2975
2976
2977int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
2978{
2979 u8 buf;
2980
2981 buf = pcon_dsc_dpcd[DP_PCON_DSC_BPP_INCR - DP_PCON_DSC_ENCODER];
2982
2983 switch (buf & DP_PCON_DSC_BPP_INCR_MASK) {
2984 case DP_PCON_DSC_ONE_16TH_BPP:
2985 return 16;
2986 case DP_PCON_DSC_ONE_8TH_BPP:
2987 return 8;
2988 case DP_PCON_DSC_ONE_4TH_BPP:
2989 return 4;
2990 case DP_PCON_DSC_ONE_HALF_BPP:
2991 return 2;
2992 case DP_PCON_DSC_ONE_BPP:
2993 return 1;
2994 }
2995
2996 return 0;
2997}
2998EXPORT_SYMBOL(drm_dp_pcon_dsc_bpp_incr);
2999
3000static
3001int drm_dp_pcon_configure_dsc_enc(struct drm_dp_aux *aux, u8 pps_buf_config)
3002{
3003 u8 buf;
3004 int ret;
3005
3006 ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf);
3007 if (ret < 0)
3008 return ret;
3009
3010 buf |= DP_PCON_ENABLE_DSC_ENCODER;
3011
3012 if (pps_buf_config <= DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER) {
3013 buf &= ~DP_PCON_ENCODER_PPS_OVERRIDE_MASK;
3014 buf |= pps_buf_config << 2;
3015 }
3016
3017 ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf);
3018 if (ret < 0)
3019 return ret;
3020
3021 return 0;
3022}
3023
3024
3025
3026
3027
3028
3029
3030
3031int drm_dp_pcon_pps_default(struct drm_dp_aux *aux)
3032{
3033 int ret;
3034
3035 ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_DISABLED);
3036 if (ret < 0)
3037 return ret;
3038
3039 return 0;
3040}
3041EXPORT_SYMBOL(drm_dp_pcon_pps_default);
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128])
3052{
3053 int ret;
3054
3055 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVERRIDE_BASE, &pps_buf, 128);
3056 if (ret < 0)
3057 return ret;
3058
3059 ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER);
3060 if (ret < 0)
3061 return ret;
3062
3063 return 0;
3064}
3065EXPORT_SYMBOL(drm_dp_pcon_pps_override_buf);
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6])
3077{
3078 int ret;
3079
3080 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT, &pps_param[0], 2);
3081 if (ret < 0)
3082 return ret;
3083 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH, &pps_param[2], 2);
3084 if (ret < 0)
3085 return ret;
3086 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_BPP, &pps_param[4], 2);
3087 if (ret < 0)
3088 return ret;
3089
3090 ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER);
3091 if (ret < 0)
3092 return ret;
3093
3094 return 0;
3095}
3096EXPORT_SYMBOL(drm_dp_pcon_pps_override_param);
3097
3098
3099
3100
3101
3102
3103
3104
3105int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc)
3106{
3107 int ret;
3108 u8 buf;
3109
3110 ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf);
3111 if (ret < 0)
3112 return ret;
3113
3114 if (color_spc & DP_CONVERSION_RGB_YCBCR_MASK)
3115 buf |= (color_spc & DP_CONVERSION_RGB_YCBCR_MASK);
3116 else
3117 buf &= ~DP_CONVERSION_RGB_YCBCR_MASK;
3118
3119 ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf);
3120 if (ret < 0)
3121 return ret;
3122
3123 return 0;
3124}
3125EXPORT_SYMBOL(drm_dp_pcon_convert_rgb_to_ycbcr);
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
3139 u16 level)
3140{
3141 int ret;
3142 u8 buf[2] = { 0 };
3143
3144 if (bl->lsb_reg_used) {
3145 buf[0] = (level & 0xff00) >> 8;
3146 buf[1] = (level & 0x00ff);
3147 } else {
3148 buf[0] = level;
3149 }
3150
3151 ret = drm_dp_dpcd_write(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, sizeof(buf));
3152 if (ret != sizeof(buf)) {
3153 drm_err(aux->drm_dev,
3154 "%s: Failed to write aux backlight level: %d\n",
3155 aux->name, ret);
3156 return ret < 0 ? ret : -EIO;
3157 }
3158
3159 return 0;
3160}
3161EXPORT_SYMBOL(drm_edp_backlight_set_level);
3162
3163static int
3164drm_edp_backlight_set_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
3165 bool enable)
3166{
3167 int ret;
3168 u8 buf;
3169
3170
3171 if (!bl->aux_enable)
3172 return 0;
3173
3174 ret = drm_dp_dpcd_readb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, &buf);
3175 if (ret != 1) {
3176 drm_err(aux->drm_dev, "%s: Failed to read eDP display control register: %d\n",
3177 aux->name, ret);
3178 return ret < 0 ? ret : -EIO;
3179 }
3180 if (enable)
3181 buf |= DP_EDP_BACKLIGHT_ENABLE;
3182 else
3183 buf &= ~DP_EDP_BACKLIGHT_ENABLE;
3184
3185 ret = drm_dp_dpcd_writeb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, buf);
3186 if (ret != 1) {
3187 drm_err(aux->drm_dev, "%s: Failed to write eDP display control register: %d\n",
3188 aux->name, ret);
3189 return ret < 0 ? ret : -EIO;
3190 }
3191
3192 return 0;
3193}
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
3214 const u16 level)
3215{
3216 int ret;
3217 u8 dpcd_buf, new_dpcd_buf;
3218
3219 ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf);
3220 if (ret != 1) {
3221 drm_dbg_kms(aux->drm_dev,
3222 "%s: Failed to read backlight mode: %d\n", aux->name, ret);
3223 return ret < 0 ? ret : -EIO;
3224 }
3225
3226 new_dpcd_buf = dpcd_buf;
3227
3228 if ((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) != DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
3229 new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
3230 new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
3231
3232 if (bl->pwmgen_bit_count) {
3233 ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, bl->pwmgen_bit_count);
3234 if (ret != 1)
3235 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
3236 aux->name, ret);
3237 }
3238 }
3239
3240 if (bl->pwm_freq_pre_divider) {
3241 ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_FREQ_SET, bl->pwm_freq_pre_divider);
3242 if (ret != 1)
3243 drm_dbg_kms(aux->drm_dev,
3244 "%s: Failed to write aux backlight frequency: %d\n",
3245 aux->name, ret);
3246 else
3247 new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
3248 }
3249
3250 if (new_dpcd_buf != dpcd_buf) {
3251 ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, new_dpcd_buf);
3252 if (ret != 1) {
3253 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux backlight mode: %d\n",
3254 aux->name, ret);
3255 return ret < 0 ? ret : -EIO;
3256 }
3257 }
3258
3259 ret = drm_edp_backlight_set_level(aux, bl, level);
3260 if (ret < 0)
3261 return ret;
3262 ret = drm_edp_backlight_set_enable(aux, bl, true);
3263 if (ret < 0)
3264 return ret;
3265
3266 return 0;
3267}
3268EXPORT_SYMBOL(drm_edp_backlight_enable);
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl)
3285{
3286 int ret;
3287
3288 ret = drm_edp_backlight_set_enable(aux, bl, false);
3289 if (ret < 0)
3290 return ret;
3291
3292 return 0;
3293}
3294EXPORT_SYMBOL(drm_edp_backlight_disable);
3295
3296static inline int
3297drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
3298 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
3299{
3300 int fxp, fxp_min, fxp_max, fxp_actual, f = 1;
3301 int ret;
3302 u8 pn, pn_min, pn_max;
3303
3304 ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT, &pn);
3305 if (ret != 1) {
3306 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap: %d\n",
3307 aux->name, ret);
3308 return -ENODEV;
3309 }
3310
3311 pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
3312 bl->max = (1 << pn) - 1;
3313 if (!driver_pwm_freq_hz)
3314 return 0;
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329 fxp = DIV_ROUND_CLOSEST(1000 * DP_EDP_BACKLIGHT_FREQ_BASE_KHZ, driver_pwm_freq_hz);
3330
3331
3332
3333
3334
3335
3336
3337
3338 ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min);
3339 if (ret != 1) {
3340 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap min: %d\n",
3341 aux->name, ret);
3342 return 0;
3343 }
3344 ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max);
3345 if (ret != 1) {
3346 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap max: %d\n",
3347 aux->name, ret);
3348 return 0;
3349 }
3350 pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
3351 pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
3352
3353
3354 fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
3355 fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
3356 if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
3357 drm_dbg_kms(aux->drm_dev,
3358 "%s: Driver defined backlight frequency (%d) out of range\n",
3359 aux->name, driver_pwm_freq_hz);
3360 return 0;
3361 }
3362
3363 for (pn = pn_max; pn >= pn_min; pn--) {
3364 f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
3365 fxp_actual = f << pn;
3366 if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
3367 break;
3368 }
3369
3370 ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, pn);
3371 if (ret != 1) {
3372 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
3373 aux->name, ret);
3374 return 0;
3375 }
3376 bl->pwmgen_bit_count = pn;
3377 bl->max = (1 << pn) - 1;
3378
3379 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP) {
3380 bl->pwm_freq_pre_divider = f;
3381 drm_dbg_kms(aux->drm_dev, "%s: Using backlight frequency from driver (%dHz)\n",
3382 aux->name, driver_pwm_freq_hz);
3383 }
3384
3385 return 0;
3386}
3387
3388static inline int
3389drm_edp_backlight_probe_level(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
3390 u8 *current_mode)
3391{
3392 int ret;
3393 u8 buf[2];
3394 u8 mode_reg;
3395
3396 ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg);
3397 if (ret != 1) {
3398 drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight mode: %d\n",
3399 aux->name, ret);
3400 return ret < 0 ? ret : -EIO;
3401 }
3402
3403 *current_mode = (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK);
3404 if (*current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
3405 int size = 1 + bl->lsb_reg_used;
3406
3407 ret = drm_dp_dpcd_read(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, size);
3408 if (ret != size) {
3409 drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight level: %d\n",
3410 aux->name, ret);
3411 return ret < 0 ? ret : -EIO;
3412 }
3413
3414 if (bl->lsb_reg_used)
3415 return (buf[0] << 8) | buf[1];
3416 else
3417 return buf[0];
3418 }
3419
3420
3421
3422
3423
3424 return bl->max;
3425}
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445int
3446drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
3447 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
3448 u16 *current_level, u8 *current_mode)
3449{
3450 int ret;
3451
3452 if (edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)
3453 bl->aux_enable = true;
3454 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
3455 bl->lsb_reg_used = true;
3456
3457 ret = drm_edp_backlight_probe_max(aux, bl, driver_pwm_freq_hz, edp_dpcd);
3458 if (ret < 0)
3459 return ret;
3460
3461 ret = drm_edp_backlight_probe_level(aux, bl, current_mode);
3462 if (ret < 0)
3463 return ret;
3464 *current_level = ret;
3465
3466 drm_dbg_kms(aux->drm_dev,
3467 "%s: Found backlight level=%d/%d pwm_freq_pre_divider=%d mode=%x\n",
3468 aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider, *current_mode);
3469 drm_dbg_kms(aux->drm_dev,
3470 "%s: Backlight caps: pwmgen_bit_count=%d lsb_reg_used=%d aux_enable=%d\n",
3471 aux->name, bl->pwmgen_bit_count, bl->lsb_reg_used, bl->aux_enable);
3472 return 0;
3473}
3474EXPORT_SYMBOL(drm_edp_backlight_init);
3475
3476#if IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \
3477 (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE))
3478
3479static int dp_aux_backlight_update_status(struct backlight_device *bd)
3480{
3481 struct dp_aux_backlight *bl = bl_get_data(bd);
3482 u16 brightness = backlight_get_brightness(bd);
3483 int ret = 0;
3484
3485 if (!backlight_is_blank(bd)) {
3486 if (!bl->enabled) {
3487 drm_edp_backlight_enable(bl->aux, &bl->info, brightness);
3488 bl->enabled = true;
3489 return 0;
3490 }
3491 ret = drm_edp_backlight_set_level(bl->aux, &bl->info, brightness);
3492 } else {
3493 if (bl->enabled) {
3494 drm_edp_backlight_disable(bl->aux, &bl->info);
3495 bl->enabled = false;
3496 }
3497 }
3498
3499 return ret;
3500}
3501
3502static const struct backlight_ops dp_aux_bl_ops = {
3503 .update_status = dp_aux_backlight_update_status,
3504};
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux)
3531{
3532 struct dp_aux_backlight *bl;
3533 struct backlight_properties props = { 0 };
3534 u16 current_level;
3535 u8 current_mode;
3536 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
3537 int ret;
3538
3539 if (!panel || !panel->dev || !aux)
3540 return -EINVAL;
3541
3542 ret = drm_dp_dpcd_read(aux, DP_EDP_DPCD_REV, edp_dpcd,
3543 EDP_DISPLAY_CTL_CAP_SIZE);
3544 if (ret < 0)
3545 return ret;
3546
3547 if (!drm_edp_backlight_supported(edp_dpcd)) {
3548 DRM_DEV_INFO(panel->dev, "DP AUX backlight is not supported\n");
3549 return 0;
3550 }
3551
3552 bl = devm_kzalloc(panel->dev, sizeof(*bl), GFP_KERNEL);
3553 if (!bl)
3554 return -ENOMEM;
3555
3556 bl->aux = aux;
3557
3558 ret = drm_edp_backlight_init(aux, &bl->info, 0, edp_dpcd,
3559 ¤t_level, ¤t_mode);
3560 if (ret < 0)
3561 return ret;
3562
3563 props.type = BACKLIGHT_RAW;
3564 props.brightness = current_level;
3565 props.max_brightness = bl->info.max;
3566
3567 bl->base = devm_backlight_device_register(panel->dev, "dp_aux_backlight",
3568 panel->dev, bl,
3569 &dp_aux_bl_ops, &props);
3570 if (IS_ERR(bl->base))
3571 return PTR_ERR(bl->base);
3572
3573 backlight_disable(bl->base);
3574
3575 panel->backlight = bl->base;
3576
3577 return 0;
3578}
3579EXPORT_SYMBOL(drm_panel_dp_aux_backlight);
3580
3581#endif
3582