LXR linux/drivers/gpu/drm/drm

   1/*
   2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
   3 * Copyright (c) 2007-2008 Intel Corporation
   4 *   Jesse Barnes <jesse.barnes@intel.com>
   5 * Copyright 2010 Red Hat, Inc.
   6 *
   7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
   8 * FB layer.
   9 *   Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
  10 *
  11 * Permission is hereby granted, free of charge, to any person obtaining a
  12 * copy of this software and associated documentation files (the "Software"),
  13 * to deal in the Software without restriction, including without limitation
  14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
  15 * and/or sell copies of the Software, and to permit persons to whom the
  16 * Software is furnished to do so, subject to the following conditions:
  17 *
  18 * The above copyright notice and this permission notice (including the
  19 * next paragraph) shall be included in all copies or substantial portions
  20 * of the Software.
  21 *
  22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  28 * DEALINGS IN THE SOFTWARE.
  29 */
  30
  31#include <linux/hdmi.h>
  32#include <linux/i2c.h>
  33#include <linux/kernel.h>
  34#include <linux/module.h>
  35#include <linux/pci.h>
  36#include <linux/slab.h>
  37#include <linux/vga_switcheroo.h>
  38
  39#include <drm/drm_displayid.h>
  40#include <drm/drm_drv.h>
  41#include <drm/drm_edid.h>
  42#include <drm/drm_encoder.h>
  43#include <drm/drm_print.h>
  44#include <drm/drm_scdc_helper.h>
  45
  46#include "drm_crtc_internal.h"
  47
  48#define version_greater(edid, maj, min) \
  49        (((edid)->version > (maj)) || \
  50         ((edid)->version == (maj) && (edid)->revision > (min)))
  51
  52#define EDID_EST_TIMINGS 16
  53#define EDID_STD_TIMINGS 8
  54#define EDID_DETAILED_TIMINGS 4
  55
  56/*
  57 * EDID blocks out in the wild have a variety of bugs, try to collect
  58 * them here (note that userspace may work around broken monitors first,
  59 * but fixes should make their way here so that the kernel "just works"
  60 * on as many displays as possible).
  61 */
  62
  63/* First detailed mode wrong, use largest 60Hz mode */
  64#define EDID_QUIRK_PREFER_LARGE_60              (1 << 0)
  65/* Reported 135MHz pixel clock is too high, needs adjustment */
  66#define EDID_QUIRK_135_CLOCK_TOO_HIGH           (1 << 1)
  67/* Prefer the largest mode at 75 Hz */
  68#define EDID_QUIRK_PREFER_LARGE_75              (1 << 2)
  69/* Detail timing is in cm not mm */
  70#define EDID_QUIRK_DETAILED_IN_CM               (1 << 3)
  71/* Detailed timing descriptors have bogus size values, so just take the
  72 * maximum size and use that.
  73 */
  74#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE    (1 << 4)
  75/* use +hsync +vsync for detailed mode */
  76#define EDID_QUIRK_DETAILED_SYNC_PP             (1 << 6)
  77/* Force reduced-blanking timings for detailed modes */
  78#define EDID_QUIRK_FORCE_REDUCED_BLANKING       (1 << 7)
  79/* Force 8bpc */
  80#define EDID_QUIRK_FORCE_8BPC                   (1 << 8)
  81/* Force 12bpc */
  82#define EDID_QUIRK_FORCE_12BPC                  (1 << 9)
  83/* Force 6bpc */
  84#define EDID_QUIRK_FORCE_6BPC                   (1 << 10)
  85/* Force 10bpc */
  86#define EDID_QUIRK_FORCE_10BPC                  (1 << 11)
  87/* Non desktop display (i.e. HMD) */
  88#define EDID_QUIRK_NON_DESKTOP                  (1 << 12)
  89
  90struct detailed_mode_closure {
  91        struct drm_connector *connector;
  92        struct edid *edid;
  93        bool preferred;
  94        u32 quirks;
  95        int modes;
  96};
  97
  98#define LEVEL_DMT       0
  99#define LEVEL_GTF       1
 100#define LEVEL_GTF2      2
 101#define LEVEL_CVT       3
 102
 103static const struct edid_quirk {
 104        char vendor[4];
 105        int product_id;
 106        u32 quirks;
 107} edid_quirk_list[] = {
 108        /* Acer AL1706 */
 109        { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
 110        /* Acer F51 */
 111        { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
 112
 113        /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
 114        { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
 115
 116        /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
 117        { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC },
 118
 119        /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
 120        { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
 121
 122        /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
 123        { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
 124
 125        /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
 126        { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC },
 127
 128        /* Belinea 10 15 55 */
 129        { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
 130        { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
 131
 132        /* Envision Peripherals, Inc. EN-7100e */
 133        { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
 134        /* Envision EN2028 */
 135        { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
 136
 137        /* Funai Electronics PM36B */
 138        { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
 139          EDID_QUIRK_DETAILED_IN_CM },
 140
 141        /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
 142        { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
 143
 144        /* LG Philips LCD LP154W01-A5 */
 145        { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
 146        { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
 147
 148        /* Samsung SyncMaster 205BW.  Note: irony */
 149        { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
 150        /* Samsung SyncMaster 22[5-6]BW */
 151        { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
 152        { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
 153
 154        /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
 155        { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
 156
 157        /* ViewSonic VA2026w */
 158        { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
 159
 160        /* Medion MD 30217 PG */
 161        { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
 162
 163        /* Lenovo G50 */
 164        { "SDC", 18514, EDID_QUIRK_FORCE_6BPC },
 165
 166        /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
 167        { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
 168
 169        /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
 170        { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
 171
 172        /* Valve Index Headset */
 173        { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP },
 174        { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP },
 175        { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP },
 176        { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP },
 177        { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP },
 178        { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP },
 179        { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP },
 180        { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP },
 181        { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP },
 182        { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP },
 183        { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP },
 184        { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP },
 185        { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP },
 186        { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP },
 187        { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP },
 188        { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP },
 189        { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP },
 190
 191        /* HTC Vive and Vive Pro VR Headsets */
 192        { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
 193        { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP },
 194
 195        /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
 196        { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
 197        { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
 198        { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
 199        { "OVR", 0x0012, EDID_QUIRK_NON_DESKTOP },
 200
 201        /* Windows Mixed Reality Headsets */
 202        { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
 203        { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP },
 204        { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP },
 205        { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP },
 206        { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP },
 207        { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP },
 208        { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP },
 209        { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP },
 210
 211        /* Sony PlayStation VR Headset */
 212        { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP },
 213
 214        /* Sensics VR Headsets */
 215        { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP },
 216
 217        /* OSVR HDK and HDK2 VR Headsets */
 218        { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP },
 219};
 220
 221/*
 222 * Autogenerated from the DMT spec.
 223 * This table is copied from xfree86/modes/xf86EdidModes.c.
 224 */
 225static const struct drm_display_mode drm_dmt_modes[] = {
 226        /* 0x01 - 640x350@85Hz */
 227        { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
 228                   736, 832, 0, 350, 382, 385, 445, 0,
 229                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 230        /* 0x02 - 640x400@85Hz */
 231        { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
 232                   736, 832, 0, 400, 401, 404, 445, 0,
 233                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 234        /* 0x03 - 720x400@85Hz */
 235        { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
 236                   828, 936, 0, 400, 401, 404, 446, 0,
 237                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 238        /* 0x04 - 640x480@60Hz */
 239        { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
 240                   752, 800, 0, 480, 490, 492, 525, 0,
 241                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
 242        /* 0x05 - 640x480@72Hz */
 243        { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
 244                   704, 832, 0, 480, 489, 492, 520, 0,
 245                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
 246        /* 0x06 - 640x480@75Hz */
 247        { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
 248                   720, 840, 0, 480, 481, 484, 500, 0,
 249                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
 250        /* 0x07 - 640x480@85Hz */
 251        { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
 252                   752, 832, 0, 480, 481, 484, 509, 0,
 253                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
 254        /* 0x08 - 800x600@56Hz */
 255        { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
 256                   896, 1024, 0, 600, 601, 603, 625, 0,
 257                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 258        /* 0x09 - 800x600@60Hz */
 259        { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
 260                   968, 1056, 0, 600, 601, 605, 628, 0,
 261                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 262        /* 0x0a - 800x600@72Hz */
 263        { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
 264                   976, 1040, 0, 600, 637, 643, 666, 0,
 265                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 266        /* 0x0b - 800x600@75Hz */
 267        { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
 268                   896, 1056, 0, 600, 601, 604, 625, 0,
 269                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 270        /* 0x0c - 800x600@85Hz */
 271        { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
 272                   896, 1048, 0, 600, 601, 604, 631, 0,
 273                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 274        /* 0x0d - 800x600@120Hz RB */
 275        { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
 276                   880, 960, 0, 600, 603, 607, 636, 0,
 277                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 278        /* 0x0e - 848x480@60Hz */
 279        { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
 280                   976, 1088, 0, 480, 486, 494, 517, 0,
 281                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 282        /* 0x0f - 1024x768@43Hz, interlace */
 283        { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
 284                   1208, 1264, 0, 768, 768, 776, 817, 0,
 285                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
 286                   DRM_MODE_FLAG_INTERLACE) },
 287        /* 0x10 - 1024x768@60Hz */
 288        { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
 289                   1184, 1344, 0, 768, 771, 777, 806, 0,
 290                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
 291        /* 0x11 - 1024x768@70Hz */
 292        { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
 293                   1184, 1328, 0, 768, 771, 777, 806, 0,
 294                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
 295        /* 0x12 - 1024x768@75Hz */
 296        { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
 297                   1136, 1312, 0, 768, 769, 772, 800, 0,
 298                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 299        /* 0x13 - 1024x768@85Hz */
 300        { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
 301                   1168, 1376, 0, 768, 769, 772, 808, 0,
 302                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 303        /* 0x14 - 1024x768@120Hz RB */
 304        { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
 305                   1104, 1184, 0, 768, 771, 775, 813, 0,
 306                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 307        /* 0x15 - 1152x864@75Hz */
 308        { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
 309                   1344, 1600, 0, 864, 865, 868, 900, 0,
 310                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 311        /* 0x55 - 1280x720@60Hz */
 312        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
 313                   1430, 1650, 0, 720, 725, 730, 750, 0,
 314                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 315        /* 0x16 - 1280x768@60Hz RB */
 316        { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
 317                   1360, 1440, 0, 768, 771, 778, 790, 0,
 318                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 319        /* 0x17 - 1280x768@60Hz */
 320        { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
 321                   1472, 1664, 0, 768, 771, 778, 798, 0,
 322                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 323        /* 0x18 - 1280x768@75Hz */
 324        { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
 325                   1488, 1696, 0, 768, 771, 778, 805, 0,
 326                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 327        /* 0x19 - 1280x768@85Hz */
 328        { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
 329                   1496, 1712, 0, 768, 771, 778, 809, 0,
 330                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 331        /* 0x1a - 1280x768@120Hz RB */
 332        { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
 333                   1360, 1440, 0, 768, 771, 778, 813, 0,
 334                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 335        /* 0x1b - 1280x800@60Hz RB */
 336        { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
 337                   1360, 1440, 0, 800, 803, 809, 823, 0,
 338                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 339        /* 0x1c - 1280x800@60Hz */
 340        { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
 341                   1480, 1680, 0, 800, 803, 809, 831, 0,
 342                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 343        /* 0x1d - 1280x800@75Hz */
 344        { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
 345                   1488, 1696, 0, 800, 803, 809, 838, 0,
 346                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 347        /* 0x1e - 1280x800@85Hz */
 348        { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
 349                   1496, 1712, 0, 800, 803, 809, 843, 0,
 350                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 351        /* 0x1f - 1280x800@120Hz RB */
 352        { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
 353                   1360, 1440, 0, 800, 803, 809, 847, 0,
 354                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 355        /* 0x20 - 1280x960@60Hz */
 356        { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
 357                   1488, 1800, 0, 960, 961, 964, 1000, 0,
 358                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 359        /* 0x21 - 1280x960@85Hz */
 360        { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
 361                   1504, 1728, 0, 960, 961, 964, 1011, 0,
 362                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 363        /* 0x22 - 1280x960@120Hz RB */
 364        { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
 365                   1360, 1440, 0, 960, 963, 967, 1017, 0,
 366                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 367        /* 0x23 - 1280x1024@60Hz */
 368        { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
 369                   1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
 370                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 371        /* 0x24 - 1280x1024@75Hz */
 372        { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
 373                   1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
 374                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 375        /* 0x25 - 1280x1024@85Hz */
 376        { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
 377                   1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
 378                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 379        /* 0x26 - 1280x1024@120Hz RB */
 380        { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
 381                   1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
 382                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 383        /* 0x27 - 1360x768@60Hz */
 384        { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
 385                   1536, 1792, 0, 768, 771, 777, 795, 0,
 386                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 387        /* 0x28 - 1360x768@120Hz RB */
 388        { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
 389                   1440, 1520, 0, 768, 771, 776, 813, 0,
 390                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 391        /* 0x51 - 1366x768@60Hz */
 392        { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
 393                   1579, 1792, 0, 768, 771, 774, 798, 0,
 394                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 395        /* 0x56 - 1366x768@60Hz */
 396        { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
 397                   1436, 1500, 0, 768, 769, 772, 800, 0,
 398                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 399        /* 0x29 - 1400x1050@60Hz RB */
 400        { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
 401                   1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
 402                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 403        /* 0x2a - 1400x1050@60Hz */
 404        { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
 405                   1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
 406                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 407        /* 0x2b - 1400x1050@75Hz */
 408        { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
 409                   1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
 410                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 411        /* 0x2c - 1400x1050@85Hz */
 412        { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
 413                   1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
 414                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 415        /* 0x2d - 1400x1050@120Hz RB */
 416        { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
 417                   1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
 418                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 419        /* 0x2e - 1440x900@60Hz RB */
 420        { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
 421                   1520, 1600, 0, 900, 903, 909, 926, 0,
 422                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 423        /* 0x2f - 1440x900@60Hz */
 424        { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
 425                   1672, 1904, 0, 900, 903, 909, 934, 0,
 426                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 427        /* 0x30 - 1440x900@75Hz */
 428        { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
 429                   1688, 1936, 0, 900, 903, 909, 942, 0,
 430                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 431        /* 0x31 - 1440x900@85Hz */
 432        { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
 433                   1696, 1952, 0, 900, 903, 909, 948, 0,
 434                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 435        /* 0x32 - 1440x900@120Hz RB */
 436        { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
 437                   1520, 1600, 0, 900, 903, 909, 953, 0,
 438                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 439        /* 0x53 - 1600x900@60Hz */
 440        { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
 441                   1704, 1800, 0, 900, 901, 904, 1000, 0,
 442                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 443        /* 0x33 - 1600x1200@60Hz */
 444        { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
 445                   1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
 446                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 447        /* 0x34 - 1600x1200@65Hz */
 448        { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
 449                   1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
 450                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 451        /* 0x35 - 1600x1200@70Hz */
 452        { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
 453                   1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
 454                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 455        /* 0x36 - 1600x1200@75Hz */
 456        { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
 457                   1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
 458                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 459        /* 0x37 - 1600x1200@85Hz */
 460        { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
 461                   1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
 462                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 463        /* 0x38 - 1600x1200@120Hz RB */
 464        { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
 465                   1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
 466                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 467        /* 0x39 - 1680x1050@60Hz RB */
 468        { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
 469                   1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
 470                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 471        /* 0x3a - 1680x1050@60Hz */
 472        { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
 473                   1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
 474                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 475        /* 0x3b - 1680x1050@75Hz */
 476        { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
 477                   1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
 478                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 479        /* 0x3c - 1680x1050@85Hz */
 480        { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
 481                   1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
 482                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 483        /* 0x3d - 1680x1050@120Hz RB */
 484        { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
 485                   1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
 486                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 487        /* 0x3e - 1792x1344@60Hz */
 488        { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
 489                   2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
 490                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 491        /* 0x3f - 1792x1344@75Hz */
 492        { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
 493                   2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
 494                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 495        /* 0x40 - 1792x1344@120Hz RB */
 496        { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
 497                   1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
 498                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 499        /* 0x41 - 1856x1392@60Hz */
 500        { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
 501                   2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
 502                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 503        /* 0x42 - 1856x1392@75Hz */
 504        { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
 505                   2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
 506                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 507        /* 0x43 - 1856x1392@120Hz RB */
 508        { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
 509                   1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
 510                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 511        /* 0x52 - 1920x1080@60Hz */
 512        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
 513                   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
 514                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
 515        /* 0x44 - 1920x1200@60Hz RB */
 516        { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
 517                   2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
 518                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 519        /* 0x45 - 1920x1200@60Hz */
 520        { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
 521                   2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
 522                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 523        /* 0x46 - 1920x1200@75Hz */
 524        { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
 525                   2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
 526                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 527        /* 0x47 - 1920x1200@85Hz */
 528        { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
 529                   2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
 530                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 531        /* 0x48 - 1920x1200@120Hz RB */
 532        { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
 533                   2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
 534                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 535        /* 0x49 - 1920x1440@60Hz */
 536        { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
 537                   2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
 538                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 539        /* 0x4a - 1920x1440@75Hz */
 540        { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
 541                   2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
 542                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 543        /* 0x4b - 1920x1440@120Hz RB */
 544        { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
 545                   2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
 546                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 547        /* 0x54 - 2048x1152@60Hz */
 548        { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
 549                   2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
 550                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 551        /* 0x4c - 2560x1600@60Hz RB */
 552        { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
 553                   2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
 554                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 555        /* 0x4d - 2560x1600@60Hz */
 556        { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
 557                   3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
 558                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 559        /* 0x4e - 2560x1600@75Hz */
 560        { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
 561                   3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
 562                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 563        /* 0x4f - 2560x1600@85Hz */
 564        { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
 565                   3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
 566                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 567        /* 0x50 - 2560x1600@120Hz RB */
 568        { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
 569                   2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
 570                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 571        /* 0x57 - 4096x2160@60Hz RB */
 572        { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
 573                   4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
 574                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 575        /* 0x58 - 4096x2160@59.94Hz RB */
 576        { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
 577                   4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
 578                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 579};
 580
 581/*
 582 * These more or less come from the DMT spec.  The 720x400 modes are
 583 * inferred from historical 80x25 practice.  The 640x480@67 and 832x624@75
 584 * modes are old-school Mac modes.  The EDID spec says the 1152x864@75 mode
 585 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
 586 * mode.
 587 *
 588 * The DMT modes have been fact-checked; the rest are mild guesses.
 589 */
 590static const struct drm_display_mode edid_est_modes[] = {
 591        { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
 592                   968, 1056, 0, 600, 601, 605, 628, 0,
 593                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
 594        { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
 595                   896, 1024, 0, 600, 601, 603,  625, 0,
 596                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
 597        { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
 598                   720, 840, 0, 480, 481, 484, 500, 0,
 599                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
 600        { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
 601                   704,  832, 0, 480, 489, 492, 520, 0,
 602                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
 603        { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
 604                   768,  864, 0, 480, 483, 486, 525, 0,
 605                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
 606        { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
 607                   752, 800, 0, 480, 490, 492, 525, 0,
 608                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
 609        { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
 610                   846, 900, 0, 400, 421, 423,  449, 0,
 611                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
 612        { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
 613                   846,  900, 0, 400, 412, 414, 449, 0,
 614                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
 615        { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
 616                   1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
 617                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
 618        { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
 619                   1136, 1312, 0,  768, 769, 772, 800, 0,
 620                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
 621        { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
 622                   1184, 1328, 0,  768, 771, 777, 806, 0,
 623                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
 624        { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
 625                   1184, 1344, 0,  768, 771, 777, 806, 0,
 626                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
 627        { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
 628                   1208, 1264, 0, 768, 768, 776, 817, 0,
 629                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
 630        { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
 631                   928, 1152, 0, 624, 625, 628, 667, 0,
 632                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
 633        { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
 634                   896, 1056, 0, 600, 601, 604,  625, 0,
 635                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
 636        { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
 637                   976, 1040, 0, 600, 637, 643, 666, 0,
 638                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
 639        { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
 640                   1344, 1600, 0,  864, 865, 868, 900, 0,
 641                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
 642};
 643
 644struct minimode {
 645        short w;
 646        short h;
 647        short r;
 648        short rb;
 649};
 650
 651static const struct minimode est3_modes[] = {
 652        /* byte 6 */
 653        { 640, 350, 85, 0 },
 654        { 640, 400, 85, 0 },
 655        { 720, 400, 85, 0 },
 656        { 640, 480, 85, 0 },
 657        { 848, 480, 60, 0 },
 658        { 800, 600, 85, 0 },
 659        { 1024, 768, 85, 0 },
 660        { 1152, 864, 75, 0 },
 661        /* byte 7 */
 662        { 1280, 768, 60, 1 },
 663        { 1280, 768, 60, 0 },
 664        { 1280, 768, 75, 0 },
 665        { 1280, 768, 85, 0 },
 666        { 1280, 960, 60, 0 },
 667        { 1280, 960, 85, 0 },
 668        { 1280, 1024, 60, 0 },
 669        { 1280, 1024, 85, 0 },
 670        /* byte 8 */
 671        { 1360, 768, 60, 0 },
 672        { 1440, 900, 60, 1 },
 673        { 1440, 900, 60, 0 },
 674        { 1440, 900, 75, 0 },
 675        { 1440, 900, 85, 0 },
 676        { 1400, 1050, 60, 1 },
 677        { 1400, 1050, 60, 0 },
 678        { 1400, 1050, 75, 0 },
 679        /* byte 9 */
 680        { 1400, 1050, 85, 0 },
 681        { 1680, 1050, 60, 1 },
 682        { 1680, 1050, 60, 0 },
 683        { 1680, 1050, 75, 0 },
 684        { 1680, 1050, 85, 0 },
 685        { 1600, 1200, 60, 0 },
 686        { 1600, 1200, 65, 0 },
 687        { 1600, 1200, 70, 0 },
 688        /* byte 10 */
 689        { 1600, 1200, 75, 0 },
 690        { 1600, 1200, 85, 0 },
 691        { 1792, 1344, 60, 0 },
 692        { 1792, 1344, 75, 0 },
 693        { 1856, 1392, 60, 0 },
 694        { 1856, 1392, 75, 0 },
 695        { 1920, 1200, 60, 1 },
 696        { 1920, 1200, 60, 0 },
 697        /* byte 11 */
 698        { 1920, 1200, 75, 0 },
 699        { 1920, 1200, 85, 0 },
 700        { 1920, 1440, 60, 0 },
 701        { 1920, 1440, 75, 0 },
 702};
 703
 704static const struct minimode extra_modes[] = {
 705        { 1024, 576,  60, 0 },
 706        { 1366, 768,  60, 0 },
 707        { 1600, 900,  60, 0 },
 708        { 1680, 945,  60, 0 },
 709        { 1920, 1080, 60, 0 },
 710        { 2048, 1152, 60, 0 },
 711        { 2048, 1536, 60, 0 },
 712};
 713
 714/*
 715 * From CEA/CTA-861 spec.
 716 *
 717 * Do not access directly, instead always use cea_mode_for_vic().
 718 */
 719static const struct drm_display_mode edid_cea_modes_1[] = {
 720        /* 1 - 640x480@60Hz 4:3 */
 721        { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
 722                   752, 800, 0, 480, 490, 492, 525, 0,
 723                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 724          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 725        /* 2 - 720x480@60Hz 4:3 */
 726        { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
 727                   798, 858, 0, 480, 489, 495, 525, 0,
 728                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 729          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 730        /* 3 - 720x480@60Hz 16:9 */
 731        { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
 732                   798, 858, 0, 480, 489, 495, 525, 0,
 733                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 734          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 735        /* 4 - 1280x720@60Hz 16:9 */
 736        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
 737                   1430, 1650, 0, 720, 725, 730, 750, 0,
 738                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 739          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 740        /* 5 - 1920x1080i@60Hz 16:9 */
 741        { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
 742                   2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
 743                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
 744                   DRM_MODE_FLAG_INTERLACE),
 745          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 746        /* 6 - 720(1440)x480i@60Hz 4:3 */
 747        { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
 748                   801, 858, 0, 480, 488, 494, 525, 0,
 749                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 750                   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 751          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 752        /* 7 - 720(1440)x480i@60Hz 16:9 */
 753        { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
 754                   801, 858, 0, 480, 488, 494, 525, 0,
 755                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 756                   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 757          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 758        /* 8 - 720(1440)x240@60Hz 4:3 */
 759        { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
 760                   801, 858, 0, 240, 244, 247, 262, 0,
 761                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 762                   DRM_MODE_FLAG_DBLCLK),
 763          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 764        /* 9 - 720(1440)x240@60Hz 16:9 */
 765        { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
 766                   801, 858, 0, 240, 244, 247, 262, 0,
 767                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 768                   DRM_MODE_FLAG_DBLCLK),
 769          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 770        /* 10 - 2880x480i@60Hz 4:3 */
 771        { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
 772                   3204, 3432, 0, 480, 488, 494, 525, 0,
 773                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 774                   DRM_MODE_FLAG_INTERLACE),
 775          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 776        /* 11 - 2880x480i@60Hz 16:9 */
 777        { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
 778                   3204, 3432, 0, 480, 488, 494, 525, 0,
 779                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 780                   DRM_MODE_FLAG_INTERLACE),
 781          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 782        /* 12 - 2880x240@60Hz 4:3 */
 783        { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
 784                   3204, 3432, 0, 240, 244, 247, 262, 0,
 785                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 786          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 787        /* 13 - 2880x240@60Hz 16:9 */
 788        { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
 789                   3204, 3432, 0, 240, 244, 247, 262, 0,
 790                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 791          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 792        /* 14 - 1440x480@60Hz 4:3 */
 793        { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
 794                   1596, 1716, 0, 480, 489, 495, 525, 0,
 795                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 796          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 797        /* 15 - 1440x480@60Hz 16:9 */
 798        { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
 799                   1596, 1716, 0, 480, 489, 495, 525, 0,
 800                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 801          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 802        /* 16 - 1920x1080@60Hz 16:9 */
 803        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
 804                   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
 805                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 806          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 807        /* 17 - 720x576@50Hz 4:3 */
 808        { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
 809                   796, 864, 0, 576, 581, 586, 625, 0,
 810                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 811          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 812        /* 18 - 720x576@50Hz 16:9 */
 813        { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
 814                   796, 864, 0, 576, 581, 586, 625, 0,
 815                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 816          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 817        /* 19 - 1280x720@50Hz 16:9 */
 818        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
 819                   1760, 1980, 0, 720, 725, 730, 750, 0,
 820                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 821          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 822        /* 20 - 1920x1080i@50Hz 16:9 */
 823        { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
 824                   2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
 825                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
 826                   DRM_MODE_FLAG_INTERLACE),
 827          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 828        /* 21 - 720(1440)x576i@50Hz 4:3 */
 829        { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
 830                   795, 864, 0, 576, 580, 586, 625, 0,
 831                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 832                   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 833          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 834        /* 22 - 720(1440)x576i@50Hz 16:9 */
 835        { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
 836                   795, 864, 0, 576, 580, 586, 625, 0,
 837                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 838                   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 839          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 840        /* 23 - 720(1440)x288@50Hz 4:3 */
 841        { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
 842                   795, 864, 0, 288, 290, 293, 312, 0,
 843                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 844                   DRM_MODE_FLAG_DBLCLK),
 845          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 846        /* 24 - 720(1440)x288@50Hz 16:9 */
 847        { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
 848                   795, 864, 0, 288, 290, 293, 312, 0,
 849                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 850                   DRM_MODE_FLAG_DBLCLK),
 851          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 852        /* 25 - 2880x576i@50Hz 4:3 */
 853        { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
 854                   3180, 3456, 0, 576, 580, 586, 625, 0,
 855                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 856                   DRM_MODE_FLAG_INTERLACE),
 857          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 858        /* 26 - 2880x576i@50Hz 16:9 */
 859        { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
 860                   3180, 3456, 0, 576, 580, 586, 625, 0,
 861                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 862                   DRM_MODE_FLAG_INTERLACE),
 863          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 864        /* 27 - 2880x288@50Hz 4:3 */
 865        { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
 866                   3180, 3456, 0, 288, 290, 293, 312, 0,
 867                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 868          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 869        /* 28 - 2880x288@50Hz 16:9 */
 870        { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
 871                   3180, 3456, 0, 288, 290, 293, 312, 0,
 872                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 873          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 874        /* 29 - 1440x576@50Hz 4:3 */
 875        { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
 876                   1592, 1728, 0, 576, 581, 586, 625, 0,
 877                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 878          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 879        /* 30 - 1440x576@50Hz 16:9 */
 880        { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
 881                   1592, 1728, 0, 576, 581, 586, 625, 0,
 882                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 883          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 884        /* 31 - 1920x1080@50Hz 16:9 */
 885        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
 886                   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
 887                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 888          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 889        /* 32 - 1920x1080@24Hz 16:9 */
 890        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
 891                   2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
 892                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 893          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 894        /* 33 - 1920x1080@25Hz 16:9 */
 895        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
 896                   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
 897                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 898          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 899        /* 34 - 1920x1080@30Hz 16:9 */
 900        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
 901                   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
 902                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 903          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 904        /* 35 - 2880x480@60Hz 4:3 */
 905        { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
 906                   3192, 3432, 0, 480, 489, 495, 525, 0,
 907                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 908          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 909        /* 36 - 2880x480@60Hz 16:9 */
 910        { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
 911                   3192, 3432, 0, 480, 489, 495, 525, 0,
 912                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 913          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 914        /* 37 - 2880x576@50Hz 4:3 */
 915        { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
 916                   3184, 3456, 0, 576, 581, 586, 625, 0,
 917                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 918          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 919        /* 38 - 2880x576@50Hz 16:9 */
 920        { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
 921                   3184, 3456, 0, 576, 581, 586, 625, 0,
 922                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 923          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 924        /* 39 - 1920x1080i@50Hz 16:9 */
 925        { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
 926                   2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
 927                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
 928                   DRM_MODE_FLAG_INTERLACE),
 929          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 930        /* 40 - 1920x1080i@100Hz 16:9 */
 931        { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
 932                   2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
 933                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
 934                   DRM_MODE_FLAG_INTERLACE),
 935          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 936        /* 41 - 1280x720@100Hz 16:9 */
 937        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
 938                   1760, 1980, 0, 720, 725, 730, 750, 0,
 939                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 940          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 941        /* 42 - 720x576@100Hz 4:3 */
 942        { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
 943                   796, 864, 0, 576, 581, 586, 625, 0,
 944                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 945          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 946        /* 43 - 720x576@100Hz 16:9 */
 947        { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
 948                   796, 864, 0, 576, 581, 586, 625, 0,
 949                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 950          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 951        /* 44 - 720(1440)x576i@100Hz 4:3 */
 952        { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
 953                   795, 864, 0, 576, 580, 586, 625, 0,
 954                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 955                   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 956          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 957        /* 45 - 720(1440)x576i@100Hz 16:9 */
 958        { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
 959                   795, 864, 0, 576, 580, 586, 625, 0,
 960                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 961                   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 962          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 963        /* 46 - 1920x1080i@120Hz 16:9 */
 964        { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
 965                   2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
 966                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
 967                   DRM_MODE_FLAG_INTERLACE),
 968          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 969        /* 47 - 1280x720@120Hz 16:9 */
 970        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
 971                   1430, 1650, 0, 720, 725, 730, 750, 0,
 972                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 973          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 974        /* 48 - 720x480@120Hz 4:3 */
 975        { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
 976                   798, 858, 0, 480, 489, 495, 525, 0,
 977                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 978          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 979        /* 49 - 720x480@120Hz 16:9 */
 980        { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
 981                   798, 858, 0, 480, 489, 495, 525, 0,
 982                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 983          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 984        /* 50 - 720(1440)x480i@120Hz 4:3 */
 985        { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
 986                   801, 858, 0, 480, 488, 494, 525, 0,
 987                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 988                   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 989          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 990        /* 51 - 720(1440)x480i@120Hz 16:9 */
 991        { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
 992                   801, 858, 0, 480, 488, 494, 525, 0,
 993                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 994                   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 995          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 996        /* 52 - 720x576@200Hz 4:3 */
 997        { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
 998                   796, 864, 0, 576, 581, 586, 625, 0,
 999                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1000          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },

1001        /* 53 - 720x576@200Hz 16:9 */
1002        { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1003                   796, 864, 0, 576, 581, 586, 625, 0,
1004                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1005          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1006        /* 54 - 720(1440)x576i@200Hz 4:3 */
1007        { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1008                   795, 864, 0, 576, 580, 586, 625, 0,
1009                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1010                   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1011          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1012        /* 55 - 720(1440)x576i@200Hz 16:9 */
1013        { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1014                   795, 864, 0, 576, 580, 586, 625, 0,
1015                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1016                   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1017          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1018        /* 56 - 720x480@240Hz 4:3 */
1019        { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1020                   798, 858, 0, 480, 489, 495, 525, 0,
1021                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1022          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1023        /* 57 - 720x480@240Hz 16:9 */
1024        { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1025                   798, 858, 0, 480, 489, 495, 525, 0,
1026                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1027          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1028        /* 58 - 720(1440)x480i@240Hz 4:3 */
1029        { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1030                   801, 858, 0, 480, 488, 494, 525, 0,
1031                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1032                   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1033          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1034        /* 59 - 720(1440)x480i@240Hz 16:9 */
1035        { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1036                   801, 858, 0, 480, 488, 494, 525, 0,
1037                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1038                   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1039          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1040        /* 60 - 1280x720@24Hz 16:9 */
1041        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1042                   3080, 3300, 0, 720, 725, 730, 750, 0,
1043                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1044          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1045        /* 61 - 1280x720@25Hz 16:9 */
1046        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1047                   3740, 3960, 0, 720, 725, 730, 750, 0,
1048                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1049          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1050        /* 62 - 1280x720@30Hz 16:9 */
1051        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1052                   3080, 3300, 0, 720, 725, 730, 750, 0,
1053                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1054          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1055        /* 63 - 1920x1080@120Hz 16:9 */
1056        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1057                   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1058                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1059          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1060        /* 64 - 1920x1080@100Hz 16:9 */
1061        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1062                   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1063                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1064          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1065        /* 65 - 1280x720@24Hz 64:27 */
1066        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1067                   3080, 3300, 0, 720, 725, 730, 750, 0,
1068                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1069          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1070        /* 66 - 1280x720@25Hz 64:27 */
1071        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1072                   3740, 3960, 0, 720, 725, 730, 750, 0,
1073                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1074          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1075        /* 67 - 1280x720@30Hz 64:27 */
1076        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1077                   3080, 3300, 0, 720, 725, 730, 750, 0,
1078                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1079          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1080        /* 68 - 1280x720@50Hz 64:27 */
1081        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1082                   1760, 1980, 0, 720, 725, 730, 750, 0,
1083                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1084          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1085        /* 69 - 1280x720@60Hz 64:27 */
1086        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1087                   1430, 1650, 0, 720, 725, 730, 750, 0,
1088                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1089          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1090        /* 70 - 1280x720@100Hz 64:27 */
1091        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1092                   1760, 1980, 0, 720, 725, 730, 750, 0,
1093                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1094          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1095        /* 71 - 1280x720@120Hz 64:27 */
1096        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1097                   1430, 1650, 0, 720, 725, 730, 750, 0,
1098                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1099          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1100        /* 72 - 1920x1080@24Hz 64:27 */
1101        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1102                   2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1103                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1104          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1105        /* 73 - 1920x1080@25Hz 64:27 */
1106        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1107                   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1108                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1109          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1110        /* 74 - 1920x1080@30Hz 64:27 */
1111        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1112                   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1113                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1114          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1115        /* 75 - 1920x1080@50Hz 64:27 */
1116        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1117                   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1118                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1119          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1120        /* 76 - 1920x1080@60Hz 64:27 */
1121        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1122                   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1123                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1124          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1125        /* 77 - 1920x1080@100Hz 64:27 */
1126        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1127                   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1128                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1129          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1130        /* 78 - 1920x1080@120Hz 64:27 */
1131        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1132                   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1133                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1134          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1135        /* 79 - 1680x720@24Hz 64:27 */
1136        { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1137                   3080, 3300, 0, 720, 725, 730, 750, 0,
1138                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1139          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1140        /* 80 - 1680x720@25Hz 64:27 */
1141        { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1142                   2948, 3168, 0, 720, 725, 730, 750, 0,
1143                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1144          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1145        /* 81 - 1680x720@30Hz 64:27 */
1146        { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1147                   2420, 2640, 0, 720, 725, 730, 750, 0,
1148                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1149          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1150        /* 82 - 1680x720@50Hz 64:27 */
1151        { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1152                   1980, 2200, 0, 720, 725, 730, 750, 0,
1153                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1154          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1155        /* 83 - 1680x720@60Hz 64:27 */
1156        { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1157                   1980, 2200, 0, 720, 725, 730, 750, 0,
1158                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1159          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1160        /* 84 - 1680x720@100Hz 64:27 */
1161        { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1162                   1780, 2000, 0, 720, 725, 730, 825, 0,
1163                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1164          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1165        /* 85 - 1680x720@120Hz 64:27 */
1166        { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1167                   1780, 2000, 0, 720, 725, 730, 825, 0,
1168                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1169          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1170        /* 86 - 2560x1080@24Hz 64:27 */
1171        { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1172                   3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1173                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1174          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1175        /* 87 - 2560x1080@25Hz 64:27 */
1176        { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1177                   3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1178                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1179          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1180        /* 88 - 2560x1080@30Hz 64:27 */
1181        { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1182                   3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1183                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1184          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1185        /* 89 - 2560x1080@50Hz 64:27 */
1186        { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1187                   3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1188                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1189          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1190        /* 90 - 2560x1080@60Hz 64:27 */
1191        { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1192                   2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1193                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1194          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1195        /* 91 - 2560x1080@100Hz 64:27 */
1196        { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1197                   2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1198                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1199          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1200        /* 92 - 2560x1080@120Hz 64:27 */
1201        { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1202                   3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1203                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1204          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1205        /* 93 - 3840x2160@24Hz 16:9 */
1206        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1207                   5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1208                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1209          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1210        /* 94 - 3840x2160@25Hz 16:9 */
1211        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1212                   4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1213                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1214          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1215        /* 95 - 3840x2160@30Hz 16:9 */
1216        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1217                   4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1218                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1219          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1220        /* 96 - 3840x2160@50Hz 16:9 */
1221        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1222                   4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1223                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1224          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1225        /* 97 - 3840x2160@60Hz 16:9 */
1226        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1227                   4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1228                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1229          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1230        /* 98 - 4096x2160@24Hz 256:135 */
1231        { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1232                   5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1233                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1234          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1235        /* 99 - 4096x2160@25Hz 256:135 */
1236        { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1237                   5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1238                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1239          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1240        /* 100 - 4096x2160@30Hz 256:135 */
1241        { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1242                   4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1243                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1244          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1245        /* 101 - 4096x2160@50Hz 256:135 */
1246        { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1247                   5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1248                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1249          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1250        /* 102 - 4096x2160@60Hz 256:135 */
1251        { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1252                   4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1253                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1254          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1255        /* 103 - 3840x2160@24Hz 64:27 */
1256        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1257                   5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1258                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1259          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1260        /* 104 - 3840x2160@25Hz 64:27 */
1261        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1262                   4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1263                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1264          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1265        /* 105 - 3840x2160@30Hz 64:27 */
1266        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1267                   4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1268                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1269          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1270        /* 106 - 3840x2160@50Hz 64:27 */
1271        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1272                   4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1273                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1274          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1275        /* 107 - 3840x2160@60Hz 64:27 */
1276        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1277                   4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1278                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1279          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1280        /* 108 - 1280x720@48Hz 16:9 */
1281        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1282                   2280, 2500, 0, 720, 725, 730, 750, 0,
1283                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1284          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1285        /* 109 - 1280x720@48Hz 64:27 */
1286        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1287                   2280, 2500, 0, 720, 725, 730, 750, 0,
1288                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1289          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1290        /* 110 - 1680x720@48Hz 64:27 */
1291        { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1292                   2530, 2750, 0, 720, 725, 730, 750, 0,
1293                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1294          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1295        /* 111 - 1920x1080@48Hz 16:9 */
1296        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1297                   2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1298                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1299          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1300        /* 112 - 1920x1080@48Hz 64:27 */
1301        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1302                   2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1303                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1304          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1305        /* 113 - 2560x1080@48Hz 64:27 */
1306        { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1307                   3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1308                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1309          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1310        /* 114 - 3840x2160@48Hz 16:9 */
1311        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1312                   5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1313                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1314          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1315        /* 115 - 4096x2160@48Hz 256:135 */
1316        { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1317                   5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1318                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1319          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1320        /* 116 - 3840x2160@48Hz 64:27 */
1321        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1322                   5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1323                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1324          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1325        /* 117 - 3840x2160@100Hz 16:9 */
1326        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1327                   4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1328                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1329          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1330        /* 118 - 3840x2160@120Hz 16:9 */
1331        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1332                   4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1333                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1334          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1335        /* 119 - 3840x2160@100Hz 64:27 */
1336        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1337                   4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1338                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1339          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1340        /* 120 - 3840x2160@120Hz 64:27 */
1341        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1342                   4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1343                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1344          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1345        /* 121 - 5120x2160@24Hz 64:27 */
1346        { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1347                   7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1348                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1349          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1350        /* 122 - 5120x2160@25Hz 64:27 */
1351        { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1352                   6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1353                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1354          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1355        /* 123 - 5120x2160@30Hz 64:27 */
1356        { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1357                   5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1358                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1359          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1360        /* 124 - 5120x2160@48Hz 64:27 */
1361        { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1362                   5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1363                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1364          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1365        /* 125 - 5120x2160@50Hz 64:27 */
1366        { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1367                   6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1368                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1369          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1370        /* 126 - 5120x2160@60Hz 64:27 */
1371        { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1372                   5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1373                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1374          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1375        /* 127 - 5120x2160@100Hz 64:27 */
1376        { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1377                   6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1378                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1379          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1380};
1381
1382/*
1383 * From CEA/CTA-861 spec.
1384 *
1385 * Do not access directly, instead always use cea_mode_for_vic().
1386 */
1387static const struct drm_display_mode edid_cea_modes_193[] = {
1388        /* 193 - 5120x2160@120Hz 64:27 */
1389        { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1390                   5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1391                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1392          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1393        /* 194 - 7680x4320@24Hz 16:9 */
1394        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1395                   10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1396                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1397          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1398        /* 195 - 7680x4320@25Hz 16:9 */
1399        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1400                   10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1401                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1402          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1403        /* 196 - 7680x4320@30Hz 16:9 */
1404        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1405                   8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1406                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1407          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1408        /* 197 - 7680x4320@48Hz 16:9 */
1409        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1410                   10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1411                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1412          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1413        /* 198 - 7680x4320@50Hz 16:9 */
1414        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1415                   10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1416                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1417          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1418        /* 199 - 7680x4320@60Hz 16:9 */
1419        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1420                   8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1421                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1422          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1423        /* 200 - 7680x4320@100Hz 16:9 */
1424        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1425                   9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1426                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1427          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1428        /* 201 - 7680x4320@120Hz 16:9 */
1429        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1430                   8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1431                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1432          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1433        /* 202 - 7680x4320@24Hz 64:27 */
1434        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1435                   10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1436                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1437          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1438        /* 203 - 7680x4320@25Hz 64:27 */
1439        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1440                   10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1441                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1442          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1443        /* 204 - 7680x4320@30Hz 64:27 */
1444        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1445                   8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1446                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1447          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1448        /* 205 - 7680x4320@48Hz 64:27 */
1449        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1450                   10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1451                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1452          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1453        /* 206 - 7680x4320@50Hz 64:27 */
1454        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1455                   10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1456                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1457          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1458        /* 207 - 7680x4320@60Hz 64:27 */
1459        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1460                   8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1461                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1462          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1463        /* 208 - 7680x4320@100Hz 64:27 */
1464        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1465                   9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1466                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1467          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1468        /* 209 - 7680x4320@120Hz 64:27 */
1469        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1470                   8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1471                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1472          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1473        /* 210 - 10240x4320@24Hz 64:27 */
1474        { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1475                   11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1476                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1477          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1478        /* 211 - 10240x4320@25Hz 64:27 */
1479        { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1480                   12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1481                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1482          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1483        /* 212 - 10240x4320@30Hz 64:27 */
1484        { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1485                   10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1486                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1487          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1488        /* 213 - 10240x4320@48Hz 64:27 */
1489        { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1490                   11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1491                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1492          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1493        /* 214 - 10240x4320@50Hz 64:27 */
1494        { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1495                   12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1496                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1497          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1498        /* 215 - 10240x4320@60Hz 64:27 */
1499        { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1500                   10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1501                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1502          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1503        /* 216 - 10240x4320@100Hz 64:27 */
1504        { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1505                   12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1506                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1507          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1508        /* 217 - 10240x4320@120Hz 64:27 */
1509        { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1510                   10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1511                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1512          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1513        /* 218 - 4096x2160@100Hz 256:135 */
1514        { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1515                   4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1516                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1517          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1518        /* 219 - 4096x2160@120Hz 256:135 */
1519        { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1520                   4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1521                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1522          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1523};
1524
1525/*
1526 * HDMI 1.4 4k modes. Index using the VIC.
1527 */
1528static const struct drm_display_mode edid_4k_modes[] = {
1529        /* 0 - dummy, VICs start at 1 */
1530        { },
1531        /* 1 - 3840x2160@30Hz */
1532        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1533                   3840, 4016, 4104, 4400, 0,
1534                   2160, 2168, 2178, 2250, 0,
1535                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1536          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1537        /* 2 - 3840x2160@25Hz */
1538        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1539                   3840, 4896, 4984, 5280, 0,
1540                   2160, 2168, 2178, 2250, 0,
1541                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1542          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1543        /* 3 - 3840x2160@24Hz */
1544        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1545                   3840, 5116, 5204, 5500, 0,
1546                   2160, 2168, 2178, 2250, 0,
1547                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1548          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1549        /* 4 - 4096x2160@24Hz (SMPTE) */
1550        { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1551                   4096, 5116, 5204, 5500, 0,
1552                   2160, 2168, 2178, 2250, 0,
1553                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1554          .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1555};
1556
1557/*** DDC fetch and block validation ***/
1558
1559static const u8 edid_header[] = {
1560        0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1561};
1562
1563/**
1564 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1565 * @raw_edid: pointer to raw base EDID block
1566 *
1567 * Sanity check the header of the base EDID block.
1568 *
1569 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1570 */
1571int drm_edid_header_is_valid(const u8 *raw_edid)
1572{
1573        int i, score = 0;
1574
1575        for (i = 0; i < sizeof(edid_header); i++)
1576                if (raw_edid[i] == edid_header[i])
1577                        score++;
1578
1579        return score;
1580}
1581EXPORT_SYMBOL(drm_edid_header_is_valid);
1582
1583static int edid_fixup __read_mostly = 6;
1584module_param_named(edid_fixup, edid_fixup, int, 0400);
1585MODULE_PARM_DESC(edid_fixup,
1586                 "Minimum number of valid EDID header bytes (0-8, default 6)");
1587
1588static int drm_edid_block_checksum(const u8 *raw_edid)
1589{
1590        int i;
1591        u8 csum = 0, crc = 0;
1592
1593        for (i = 0; i < EDID_LENGTH - 1; i++)
1594                csum += raw_edid[i];
1595
1596        crc = 0x100 - csum;
1597
1598        return crc;
1599}
1600
1601static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum)
1602{
1603        if (raw_edid[EDID_LENGTH - 1] != real_checksum)
1604                return true;
1605        else
1606                return false;
1607}
1608
1609static bool drm_edid_is_zero(const u8 *in_edid, int length)
1610{
1611        if (memchr_inv(in_edid, 0, length))
1612                return false;
1613
1614        return true;
1615}
1616
1617/**
1618 * drm_edid_are_equal - compare two edid blobs.
1619 * @edid1: pointer to first blob
1620 * @edid2: pointer to second blob
1621 * This helper can be used during probing to determine if
1622 * edid had changed.
1623 */
1624bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1625{
1626        int edid1_len, edid2_len;
1627        bool edid1_present = edid1 != NULL;
1628        bool edid2_present = edid2 != NULL;
1629
1630        if (edid1_present != edid2_present)
1631                return false;
1632
1633        if (edid1) {
1634                edid1_len = EDID_LENGTH * (1 + edid1->extensions);
1635                edid2_len = EDID_LENGTH * (1 + edid2->extensions);
1636
1637                if (edid1_len != edid2_len)
1638                        return false;
1639
1640                if (memcmp(edid1, edid2, edid1_len))
1641                        return false;
1642        }
1643
1644        return true;
1645}
1646EXPORT_SYMBOL(drm_edid_are_equal);
1647
1648/**
1649 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1650 * @raw_edid: pointer to raw EDID block
1651 * @block: type of block to validate (0 for base, extension otherwise)
1652 * @print_bad_edid: if true, dump bad EDID blocks to the console
1653 * @edid_corrupt: if true, the header or checksum is invalid
1654 *
1655 * Validate a base or extension EDID block and optionally dump bad blocks to
1656 * the console.
1657 *
1658 * Return: True if the block is valid, false otherwise.
1659 */
1660bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1661                          bool *edid_corrupt)
1662{
1663        u8 csum;
1664        struct edid *edid = (struct edid *)raw_edid;
1665
1666        if (WARN_ON(!raw_edid))
1667                return false;
1668
1669        if (edid_fixup > 8 || edid_fixup < 0)
1670                edid_fixup = 6;
1671
1672        if (block == 0) {
1673                int score = drm_edid_header_is_valid(raw_edid);
1674
1675                if (score == 8) {
1676                        if (edid_corrupt)
1677                                *edid_corrupt = false;
1678                } else if (score >= edid_fixup) {
1679                        /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1680                         * The corrupt flag needs to be set here otherwise, the
1681                         * fix-up code here will correct the problem, the
1682                         * checksum is correct and the test fails
1683                         */
1684                        if (edid_corrupt)
1685                                *edid_corrupt = true;
1686                        DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1687                        memcpy(raw_edid, edid_header, sizeof(edid_header));
1688                } else {
1689                        if (edid_corrupt)
1690                                *edid_corrupt = true;
1691                        goto bad;
1692                }
1693        }
1694
1695        csum = drm_edid_block_checksum(raw_edid);
1696        if (drm_edid_block_checksum_diff(raw_edid, csum)) {
1697                if (edid_corrupt)
1698                        *edid_corrupt = true;
1699
1700                /* allow CEA to slide through, switches mangle this */
1701                if (raw_edid[0] == CEA_EXT) {
1702                        DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1703                        DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1704                } else {
1705                        if (print_bad_edid)
1706                                DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1707
1708                        goto bad;
1709                }
1710        }
1711
1712        /* per-block-type checks */
1713        switch (raw_edid[0]) {
1714        case 0: /* base */
1715                if (edid->version != 1) {
1716                        DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1717                        goto bad;
1718                }
1719
1720                if (edid->revision > 4)
1721                        DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1722                break;
1723
1724        default:
1725                break;
1726        }
1727
1728        return true;
1729
1730bad:
1731        if (print_bad_edid) {
1732                if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1733                        pr_notice("EDID block is all zeroes\n");
1734                } else {
1735                        pr_notice("Raw EDID:\n");
1736                        print_hex_dump(KERN_NOTICE,
1737                                       " \t", DUMP_PREFIX_NONE, 16, 1,
1738                                       raw_edid, EDID_LENGTH, false);
1739                }
1740        }
1741        return false;
1742}
1743EXPORT_SYMBOL(drm_edid_block_valid);
1744
1745/**
1746 * drm_edid_is_valid - sanity check EDID data
1747 * @edid: EDID data
1748 *
1749 * Sanity-check an entire EDID record (including extensions)
1750 *
1751 * Return: True if the EDID data is valid, false otherwise.
1752 */
1753bool drm_edid_is_valid(struct edid *edid)
1754{
1755        int i;
1756        u8 *raw = (u8 *)edid;
1757
1758        if (!edid)
1759                return false;
1760
1761        for (i = 0; i <= edid->extensions; i++)
1762                if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1763                        return false;
1764
1765        return true;
1766}
1767EXPORT_SYMBOL(drm_edid_is_valid);
1768
1769#define DDC_SEGMENT_ADDR 0x30
1770/**
1771 * drm_do_probe_ddc_edid() - get EDID information via I2C
1772 * @data: I2C device adapter
1773 * @buf: EDID data buffer to be filled
1774 * @block: 128 byte EDID block to start fetching from
1775 * @len: EDID data buffer length to fetch
1776 *
1777 * Try to fetch EDID information by calling I2C driver functions.
1778 *
1779 * Return: 0 on success or -1 on failure.
1780 */
1781static int
1782drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1783{
1784        struct i2c_adapter *adapter = data;
1785        unsigned char start = block * EDID_LENGTH;
1786        unsigned char segment = block >> 1;
1787        unsigned char xfers = segment ? 3 : 2;
1788        int ret, retries = 5;
1789
1790        /*
1791         * The core I2C driver will automatically retry the transfer if the
1792         * adapter reports EAGAIN. However, we find that bit-banging transfers
1793         * are susceptible to errors under a heavily loaded machine and
1794         * generate spurious NAKs and timeouts. Retrying the transfer
1795         * of the individual block a few times seems to overcome this.
1796         */
1797        do {
1798                struct i2c_msg msgs[] = {
1799                        {
1800                                .addr   = DDC_SEGMENT_ADDR,
1801                                .flags  = 0,
1802                                .len    = 1,
1803                                .buf    = &segment,
1804                        }, {
1805                                .addr   = DDC_ADDR,
1806                                .flags  = 0,
1807                                .len    = 1,
1808                                .buf    = &start,
1809                        }, {
1810                                .addr   = DDC_ADDR,
1811                                .flags  = I2C_M_RD,
1812                                .len    = len,
1813                                .buf    = buf,
1814                        }
1815                };
1816
1817                /*
1818                 * Avoid sending the segment addr to not upset non-compliant
1819                 * DDC monitors.
1820                 */
1821                ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1822
1823                if (ret == -ENXIO) {
1824                        DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1825                                        adapter->name);
1826                        break;
1827                }
1828        } while (ret != xfers && --retries);
1829
1830        return ret == xfers ? 0 : -1;
1831}
1832
1833static void connector_bad_edid(struct drm_connector *connector,
1834                               u8 *edid, int num_blocks)
1835{
1836        int i;
1837        u8 last_block;
1838
1839        /*
1840         * 0x7e in the EDID is the number of extension blocks. The EDID
1841         * is 1 (base block) + num_ext_blocks big. That means we can think
1842         * of 0x7e in the EDID of the _index_ of the last block in the
1843         * combined chunk of memory.
1844         */
1845        last_block = edid[0x7e];
1846
1847        /* Calculate real checksum for the last edid extension block data */
1848        if (last_block < num_blocks)
1849                connector->real_edid_checksum =
1850                        drm_edid_block_checksum(edid + last_block * EDID_LENGTH);
1851
1852        if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
1853                return;
1854
1855        drm_dbg_kms(connector->dev, "%s: EDID is invalid:\n", connector->name);
1856        for (i = 0; i < num_blocks; i++) {
1857                u8 *block = edid + i * EDID_LENGTH;
1858                char prefix[20];
1859
1860                if (drm_edid_is_zero(block, EDID_LENGTH))
1861                        sprintf(prefix, "\t[%02x] ZERO ", i);
1862                else if (!drm_edid_block_valid(block, i, false, NULL))
1863                        sprintf(prefix, "\t[%02x] BAD  ", i);
1864                else
1865                        sprintf(prefix, "\t[%02x] GOOD ", i);
1866
1867                print_hex_dump(KERN_DEBUG,
1868                               prefix, DUMP_PREFIX_NONE, 16, 1,
1869                               block, EDID_LENGTH, false);
1870        }
1871}
1872
1873/* Get override or firmware EDID */
1874static struct edid *drm_get_override_edid(struct drm_connector *connector)
1875{
1876        struct edid *override = NULL;
1877
1878        if (connector->override_edid)
1879                override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1880
1881        if (!override)
1882                override = drm_load_edid_firmware(connector);
1883
1884        return IS_ERR(override) ? NULL : override;
1885}
1886
1887/**
1888 * drm_add_override_edid_modes - add modes from override/firmware EDID
1889 * @connector: connector we're probing
1890 *
1891 * Add modes from the override/firmware EDID, if available. Only to be used from
1892 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
1893 * failed during drm_get_edid() and caused the override/firmware EDID to be
1894 * skipped.
1895 *
1896 * Return: The number of modes added or 0 if we couldn't find any.
1897 */
1898int drm_add_override_edid_modes(struct drm_connector *connector)
1899{
1900        struct edid *override;
1901        int num_modes = 0;
1902
1903        override = drm_get_override_edid(connector);
1904        if (override) {
1905                drm_connector_update_edid_property(connector, override);
1906                num_modes = drm_add_edid_modes(connector, override);
1907                kfree(override);
1908
1909                DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
1910                              connector->base.id, connector->name, num_modes);
1911        }
1912
1913        return num_modes;
1914}
1915EXPORT_SYMBOL(drm_add_override_edid_modes);
1916
1917/**
1918 * drm_do_get_edid - get EDID data using a custom EDID block read function
1919 * @connector: connector we're probing
1920 * @get_edid_block: EDID block read function
1921 * @data: private data passed to the block read function
1922 *
1923 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1924 * exposes a different interface to read EDID blocks this function can be used
1925 * to get EDID data using a custom block read function.
1926 *
1927 * As in the general case the DDC bus is accessible by the kernel at the I2C
1928 * level, drivers must make all reasonable efforts to expose it as an I2C
1929 * adapter and use drm_get_edid() instead of abusing this function.
1930 *
1931 * The EDID may be overridden using debugfs override_edid or firmware EDID
1932 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1933 * order. Having either of them bypasses actual EDID reads.
1934 *
1935 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1936 */
1937struct edid *drm_do_get_edid(struct drm_connector *connector,
1938        int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1939                              size_t len),
1940        void *data)
1941{
1942        int i, j = 0, valid_extensions = 0;
1943        u8 *edid, *new;
1944        struct edid *override;
1945
1946        override = drm_get_override_edid(connector);
1947        if (override)
1948                return override;
1949
1950        if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1951                return NULL;
1952
1953        /* base block fetch */
1954        for (i = 0; i < 4; i++) {
1955                if (get_edid_block(data, edid, 0, EDID_LENGTH))
1956                        goto out;
1957                if (drm_edid_block_valid(edid, 0, false,
1958                                         &connector->edid_corrupt))
1959                        break;
1960                if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1961                        connector->null_edid_counter++;
1962                        goto carp;
1963                }
1964        }
1965        if (i == 4)
1966                goto carp;
1967
1968        /* if there's no extensions, we're done */
1969        valid_extensions = edid[0x7e];
1970        if (valid_extensions == 0)
1971                return (struct edid *)edid;
1972
1973        new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1974        if (!new)
1975                goto out;
1976        edid = new;
1977
1978        for (j = 1; j <= edid[0x7e]; j++) {
1979                u8 *block = edid + j * EDID_LENGTH;
1980
1981                for (i = 0; i < 4; i++) {
1982                        if (get_edid_block(data, block, j, EDID_LENGTH))
1983                                goto out;
1984                        if (drm_edid_block_valid(block, j, false, NULL))
1985                                break;
1986                }
1987
1988                if (i == 4)
1989                        valid_extensions--;
1990        }
1991
1992        if (valid_extensions != edid[0x7e]) {
1993                u8 *base;
1994
1995                connector_bad_edid(connector, edid, edid[0x7e] + 1);
1996
1997                edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1998                edid[0x7e] = valid_extensions;
1999
2000                new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,

2001                                    GFP_KERNEL);
2002                if (!new)
2003                        goto out;
2004
2005                base = new;
2006                for (i = 0; i <= edid[0x7e]; i++) {
2007                        u8 *block = edid + i * EDID_LENGTH;
2008
2009                        if (!drm_edid_block_valid(block, i, false, NULL))
2010                                continue;
2011
2012                        memcpy(base, block, EDID_LENGTH);
2013                        base += EDID_LENGTH;
2014                }
2015
2016                kfree(edid);
2017                edid = new;
2018        }
2019
2020        return (struct edid *)edid;
2021
2022carp:
2023        connector_bad_edid(connector, edid, 1);
2024out:
2025        kfree(edid);
2026        return NULL;
2027}
2028EXPORT_SYMBOL_GPL(drm_do_get_edid);
2029
2030/**
2031 * drm_probe_ddc() - probe DDC presence
2032 * @adapter: I2C adapter to probe
2033 *
2034 * Return: True on success, false on failure.
2035 */
2036bool
2037drm_probe_ddc(struct i2c_adapter *adapter)
2038{
2039        unsigned char out;
2040
2041        return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2042}
2043EXPORT_SYMBOL(drm_probe_ddc);
2044
2045/**
2046 * drm_get_edid - get EDID data, if available
2047 * @connector: connector we're probing
2048 * @adapter: I2C adapter to use for DDC
2049 *
2050 * Poke the given I2C channel to grab EDID data if possible.  If found,
2051 * attach it to the connector.
2052 *
2053 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2054 */
2055struct edid *drm_get_edid(struct drm_connector *connector,
2056                          struct i2c_adapter *adapter)
2057{
2058        struct edid *edid;
2059
2060        if (connector->force == DRM_FORCE_OFF)
2061                return NULL;
2062
2063        if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2064                return NULL;
2065
2066        edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
2067        drm_connector_update_edid_property(connector, edid);
2068        return edid;
2069}
2070EXPORT_SYMBOL(drm_get_edid);
2071
2072/**
2073 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2074 * @connector: connector we're probing
2075 * @adapter: I2C adapter to use for DDC
2076 *
2077 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2078 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2079 * switch DDC to the GPU which is retrieving EDID.
2080 *
2081 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2082 */
2083struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2084                                     struct i2c_adapter *adapter)
2085{
2086        struct drm_device *dev = connector->dev;
2087        struct pci_dev *pdev = to_pci_dev(dev->dev);
2088        struct edid *edid;
2089
2090        if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2091                return NULL;
2092
2093        vga_switcheroo_lock_ddc(pdev);
2094        edid = drm_get_edid(connector, adapter);
2095        vga_switcheroo_unlock_ddc(pdev);
2096
2097        return edid;
2098}
2099EXPORT_SYMBOL(drm_get_edid_switcheroo);
2100
2101/**
2102 * drm_edid_duplicate - duplicate an EDID and the extensions
2103 * @edid: EDID to duplicate
2104 *
2105 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2106 */
2107struct edid *drm_edid_duplicate(const struct edid *edid)
2108{
2109        return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
2110}
2111EXPORT_SYMBOL(drm_edid_duplicate);
2112
2113/*** EDID parsing ***/
2114
2115/**
2116 * edid_vendor - match a string against EDID's obfuscated vendor field
2117 * @edid: EDID to match
2118 * @vendor: vendor string
2119 *
2120 * Returns true if @vendor is in @edid, false otherwise
2121 */
2122static bool edid_vendor(const struct edid *edid, const char *vendor)
2123{
2124        char edid_vendor[3];
2125
2126        edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
2127        edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
2128                          ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
2129        edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
2130
2131        return !strncmp(edid_vendor, vendor, 3);
2132}
2133
2134/**
2135 * edid_get_quirks - return quirk flags for a given EDID
2136 * @edid: EDID to process
2137 *
2138 * This tells subsequent routines what fixes they need to apply.
2139 */
2140static u32 edid_get_quirks(const struct edid *edid)
2141{
2142        const struct edid_quirk *quirk;
2143        int i;
2144
2145        for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2146                quirk = &edid_quirk_list[i];
2147
2148                if (edid_vendor(edid, quirk->vendor) &&
2149                    (EDID_PRODUCT_ID(edid) == quirk->product_id))
2150                        return quirk->quirks;
2151        }
2152
2153        return 0;
2154}
2155
2156#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2157#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
2158
2159/**
2160 * edid_fixup_preferred - set preferred modes based on quirk list
2161 * @connector: has mode list to fix up
2162 * @quirks: quirks list
2163 *
2164 * Walk the mode list for @connector, clearing the preferred status
2165 * on existing modes and setting it anew for the right mode ala @quirks.
2166 */
2167static void edid_fixup_preferred(struct drm_connector *connector,
2168                                 u32 quirks)
2169{
2170        struct drm_display_mode *t, *cur_mode, *preferred_mode;
2171        int target_refresh = 0;
2172        int cur_vrefresh, preferred_vrefresh;
2173
2174        if (list_empty(&connector->probed_modes))
2175                return;
2176
2177        if (quirks & EDID_QUIRK_PREFER_LARGE_60)
2178                target_refresh = 60;
2179        if (quirks & EDID_QUIRK_PREFER_LARGE_75)
2180                target_refresh = 75;
2181
2182        preferred_mode = list_first_entry(&connector->probed_modes,
2183                                          struct drm_display_mode, head);
2184
2185        list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2186                cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2187
2188                if (cur_mode == preferred_mode)
2189                        continue;
2190
2191                /* Largest mode is preferred */
2192                if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2193                        preferred_mode = cur_mode;
2194
2195                cur_vrefresh = drm_mode_vrefresh(cur_mode);
2196                preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
2197                /* At a given size, try to get closest to target refresh */
2198                if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2199                    MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2200                    MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2201                        preferred_mode = cur_mode;
2202                }
2203        }
2204
2205        preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2206}
2207
2208static bool
2209mode_is_rb(const struct drm_display_mode *mode)
2210{
2211        return (mode->htotal - mode->hdisplay == 160) &&
2212               (mode->hsync_end - mode->hdisplay == 80) &&
2213               (mode->hsync_end - mode->hsync_start == 32) &&
2214               (mode->vsync_start - mode->vdisplay == 3);
2215}
2216
2217/*
2218 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2219 * @dev: Device to duplicate against
2220 * @hsize: Mode width
2221 * @vsize: Mode height
2222 * @fresh: Mode refresh rate
2223 * @rb: Mode reduced-blanking-ness
2224 *
2225 * Walk the DMT mode list looking for a match for the given parameters.
2226 *
2227 * Return: A newly allocated copy of the mode, or NULL if not found.
2228 */
2229struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
2230                                           int hsize, int vsize, int fresh,
2231                                           bool rb)
2232{
2233        int i;
2234
2235        for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2236                const struct drm_display_mode *ptr = &drm_dmt_modes[i];
2237
2238                if (hsize != ptr->hdisplay)
2239                        continue;
2240                if (vsize != ptr->vdisplay)
2241                        continue;
2242                if (fresh != drm_mode_vrefresh(ptr))
2243                        continue;
2244                if (rb != mode_is_rb(ptr))
2245                        continue;
2246
2247                return drm_mode_duplicate(dev, ptr);
2248        }
2249
2250        return NULL;
2251}
2252EXPORT_SYMBOL(drm_mode_find_dmt);
2253
2254static bool is_display_descriptor(const u8 d[18], u8 tag)
2255{
2256        return d[0] == 0x00 && d[1] == 0x00 &&
2257                d[2] == 0x00 && d[3] == tag;
2258}
2259
2260static bool is_detailed_timing_descriptor(const u8 d[18])
2261{
2262        return d[0] != 0x00 || d[1] != 0x00;
2263}
2264
2265typedef void detailed_cb(struct detailed_timing *timing, void *closure);
2266
2267static void
2268cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2269{
2270        int i, n;
2271        u8 d = ext[0x02];
2272        u8 *det_base = ext + d;
2273
2274        if (d < 4 || d > 127)
2275                return;
2276
2277        n = (127 - d) / 18;
2278        for (i = 0; i < n; i++)
2279                cb((struct detailed_timing *)(det_base + 18 * i), closure);
2280}
2281
2282static void
2283vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2284{
2285        unsigned int i, n = min((int)ext[0x02], 6);
2286        u8 *det_base = ext + 5;
2287
2288        if (ext[0x01] != 1)
2289                return; /* unknown version */
2290
2291        for (i = 0; i < n; i++)
2292                cb((struct detailed_timing *)(det_base + 18 * i), closure);
2293}
2294
2295static void
2296drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
2297{
2298        int i;
2299        struct edid *edid = (struct edid *)raw_edid;
2300
2301        if (edid == NULL)
2302                return;
2303
2304        for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
2305                cb(&(edid->detailed_timings[i]), closure);
2306
2307        for (i = 1; i <= raw_edid[0x7e]; i++) {
2308                u8 *ext = raw_edid + (i * EDID_LENGTH);
2309
2310                switch (*ext) {
2311                case CEA_EXT:
2312                        cea_for_each_detailed_block(ext, cb, closure);
2313                        break;
2314                case VTB_EXT:
2315                        vtb_for_each_detailed_block(ext, cb, closure);
2316                        break;
2317                default:
2318                        break;
2319                }
2320        }
2321}
2322
2323static void
2324is_rb(struct detailed_timing *t, void *data)
2325{
2326        u8 *r = (u8 *)t;
2327
2328        if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
2329                return;
2330
2331        if (r[15] & 0x10)
2332                *(bool *)data = true;
2333}
2334
2335/* EDID 1.4 defines this explicitly.  For EDID 1.3, we guess, badly. */
2336static bool
2337drm_monitor_supports_rb(struct edid *edid)
2338{
2339        if (edid->revision >= 4) {
2340                bool ret = false;
2341
2342                drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
2343                return ret;
2344        }
2345
2346        return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
2347}
2348
2349static void
2350find_gtf2(struct detailed_timing *t, void *data)
2351{
2352        u8 *r = (u8 *)t;
2353
2354        if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
2355                return;
2356
2357        if (r[10] == 0x02)
2358                *(u8 **)data = r;
2359}
2360
2361/* Secondary GTF curve kicks in above some break frequency */
2362static int
2363drm_gtf2_hbreak(struct edid *edid)
2364{
2365        u8 *r = NULL;
2366
2367        drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2368        return r ? (r[12] * 2) : 0;
2369}
2370
2371static int
2372drm_gtf2_2c(struct edid *edid)
2373{
2374        u8 *r = NULL;
2375
2376        drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2377        return r ? r[13] : 0;
2378}
2379
2380static int
2381drm_gtf2_m(struct edid *edid)
2382{
2383        u8 *r = NULL;
2384
2385        drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2386        return r ? (r[15] << 8) + r[14] : 0;
2387}
2388
2389static int
2390drm_gtf2_k(struct edid *edid)
2391{
2392        u8 *r = NULL;
2393
2394        drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2395        return r ? r[16] : 0;
2396}
2397
2398static int
2399drm_gtf2_2j(struct edid *edid)
2400{
2401        u8 *r = NULL;
2402
2403        drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2404        return r ? r[17] : 0;
2405}
2406
2407/**
2408 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2409 * @edid: EDID block to scan
2410 */
2411static int standard_timing_level(struct edid *edid)
2412{
2413        if (edid->revision >= 2) {
2414                if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2415                        return LEVEL_CVT;
2416                if (drm_gtf2_hbreak(edid))
2417                        return LEVEL_GTF2;
2418                if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
2419                        return LEVEL_GTF;
2420        }
2421        return LEVEL_DMT;
2422}
2423
2424/*
2425 * 0 is reserved.  The spec says 0x01 fill for unused timings.  Some old
2426 * monitors fill with ascii space (0x20) instead.
2427 */
2428static int
2429bad_std_timing(u8 a, u8 b)
2430{
2431        return (a == 0x00 && b == 0x00) ||
2432               (a == 0x01 && b == 0x01) ||
2433               (a == 0x20 && b == 0x20);
2434}
2435
2436static int drm_mode_hsync(const struct drm_display_mode *mode)
2437{
2438        if (mode->htotal <= 0)
2439                return 0;
2440
2441        return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
2442}
2443
2444/**
2445 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2446 * @connector: connector of for the EDID block
2447 * @edid: EDID block to scan
2448 * @t: standard timing params
2449 *
2450 * Take the standard timing params (in this case width, aspect, and refresh)
2451 * and convert them into a real mode using CVT/GTF/DMT.
2452 */
2453static struct drm_display_mode *
2454drm_mode_std(struct drm_connector *connector, struct edid *edid,
2455             struct std_timing *t)
2456{
2457        struct drm_device *dev = connector->dev;
2458        struct drm_display_mode *m, *mode = NULL;
2459        int hsize, vsize;
2460        int vrefresh_rate;
2461        unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2462                >> EDID_TIMING_ASPECT_SHIFT;
2463        unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2464                >> EDID_TIMING_VFREQ_SHIFT;
2465        int timing_level = standard_timing_level(edid);
2466
2467        if (bad_std_timing(t->hsize, t->vfreq_aspect))
2468                return NULL;
2469
2470        /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2471        hsize = t->hsize * 8 + 248;
2472        /* vrefresh_rate = vfreq + 60 */
2473        vrefresh_rate = vfreq + 60;
2474        /* the vdisplay is calculated based on the aspect ratio */
2475        if (aspect_ratio == 0) {
2476                if (edid->revision < 3)
2477                        vsize = hsize;
2478                else
2479                        vsize = (hsize * 10) / 16;
2480        } else if (aspect_ratio == 1)
2481                vsize = (hsize * 3) / 4;
2482        else if (aspect_ratio == 2)
2483                vsize = (hsize * 4) / 5;
2484        else
2485                vsize = (hsize * 9) / 16;
2486
2487        /* HDTV hack, part 1 */
2488        if (vrefresh_rate == 60 &&
2489            ((hsize == 1360 && vsize == 765) ||
2490             (hsize == 1368 && vsize == 769))) {
2491                hsize = 1366;
2492                vsize = 768;
2493        }
2494
2495        /*
2496         * If this connector already has a mode for this size and refresh
2497         * rate (because it came from detailed or CVT info), use that
2498         * instead.  This way we don't have to guess at interlace or
2499         * reduced blanking.
2500         */
2501        list_for_each_entry(m, &connector->probed_modes, head)
2502                if (m->hdisplay == hsize && m->vdisplay == vsize &&
2503                    drm_mode_vrefresh(m) == vrefresh_rate)
2504                        return NULL;
2505
2506        /* HDTV hack, part 2 */
2507        if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2508                mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2509                                    false);
2510                if (!mode)
2511                        return NULL;
2512                mode->hdisplay = 1366;
2513                mode->hsync_start = mode->hsync_start - 1;
2514                mode->hsync_end = mode->hsync_end - 1;
2515                return mode;
2516        }
2517
2518        /* check whether it can be found in default mode table */
2519        if (drm_monitor_supports_rb(edid)) {
2520                mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2521                                         true);
2522                if (mode)
2523                        return mode;
2524        }
2525        mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2526        if (mode)
2527                return mode;
2528
2529        /* okay, generate it */
2530        switch (timing_level) {
2531        case LEVEL_DMT:
2532                break;
2533        case LEVEL_GTF:
2534                mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2535                break;
2536        case LEVEL_GTF2:
2537                /*
2538                 * This is potentially wrong if there's ever a monitor with
2539                 * more than one ranges section, each claiming a different
2540                 * secondary GTF curve.  Please don't do that.
2541                 */
2542                mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2543                if (!mode)
2544                        return NULL;
2545                if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2546                        drm_mode_destroy(dev, mode);
2547                        mode = drm_gtf_mode_complex(dev, hsize, vsize,
2548                                                    vrefresh_rate, 0, 0,
2549                                                    drm_gtf2_m(edid),
2550                                                    drm_gtf2_2c(edid),
2551                                                    drm_gtf2_k(edid),
2552                                                    drm_gtf2_2j(edid));
2553                }
2554                break;
2555        case LEVEL_CVT:
2556                mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2557                                    false);
2558                break;
2559        }
2560        return mode;
2561}
2562
2563/*
2564 * EDID is delightfully ambiguous about how interlaced modes are to be
2565 * encoded.  Our internal representation is of frame height, but some
2566 * HDTV detailed timings are encoded as field height.
2567 *
2568 * The format list here is from CEA, in frame size.  Technically we
2569 * should be checking refresh rate too.  Whatever.
2570 */
2571static void
2572drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2573                            struct detailed_pixel_timing *pt)
2574{
2575        int i;
2576        static const struct {
2577                int w, h;
2578        } cea_interlaced[] = {
2579                { 1920, 1080 },
2580                {  720,  480 },
2581                { 1440,  480 },
2582                { 2880,  480 },
2583                {  720,  576 },
2584                { 1440,  576 },
2585                { 2880,  576 },
2586        };
2587
2588        if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2589                return;
2590
2591        for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2592                if ((mode->hdisplay == cea_interlaced[i].w) &&
2593                    (mode->vdisplay == cea_interlaced[i].h / 2)) {
2594                        mode->vdisplay *= 2;
2595                        mode->vsync_start *= 2;
2596                        mode->vsync_end *= 2;
2597                        mode->vtotal *= 2;
2598                        mode->vtotal |= 1;
2599                }
2600        }
2601
2602        mode->flags |= DRM_MODE_FLAG_INTERLACE;
2603}
2604
2605/**
2606 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2607 * @dev: DRM device (needed to create new mode)
2608 * @edid: EDID block
2609 * @timing: EDID detailed timing info
2610 * @quirks: quirks to apply
2611 *
2612 * An EDID detailed timing block contains enough info for us to create and
2613 * return a new struct drm_display_mode.
2614 */
2615static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2616                                                  struct edid *edid,
2617                                                  struct detailed_timing *timing,
2618                                                  u32 quirks)
2619{
2620        struct drm_display_mode *mode;
2621        struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2622        unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2623        unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2624        unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2625        unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2626        unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2627        unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2628        unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2629        unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2630
2631        /* ignore tiny modes */
2632        if (hactive < 64 || vactive < 64)
2633                return NULL;
2634
2635        if (pt->misc & DRM_EDID_PT_STEREO) {
2636                DRM_DEBUG_KMS("stereo mode not supported\n");
2637                return NULL;
2638        }
2639        if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2640                DRM_DEBUG_KMS("composite sync not supported\n");
2641        }
2642
2643        /* it is incorrect if hsync/vsync width is zero */
2644        if (!hsync_pulse_width || !vsync_pulse_width) {
2645                DRM_DEBUG_KMS("Incorrect Detailed timing. "
2646                                "Wrong Hsync/Vsync pulse width\n");
2647                return NULL;
2648        }
2649
2650        if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2651                mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2652                if (!mode)
2653                        return NULL;
2654
2655                goto set_size;
2656        }
2657
2658        mode = drm_mode_create(dev);
2659        if (!mode)
2660                return NULL;
2661
2662        if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2663                timing->pixel_clock = cpu_to_le16(1088);
2664
2665        mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2666
2667        mode->hdisplay = hactive;
2668        mode->hsync_start = mode->hdisplay + hsync_offset;
2669        mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2670        mode->htotal = mode->hdisplay + hblank;
2671
2672        mode->vdisplay = vactive;
2673        mode->vsync_start = mode->vdisplay + vsync_offset;
2674        mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2675        mode->vtotal = mode->vdisplay + vblank;
2676
2677        /* Some EDIDs have bogus h/vtotal values */
2678        if (mode->hsync_end > mode->htotal)
2679                mode->htotal = mode->hsync_end + 1;
2680        if (mode->vsync_end > mode->vtotal)
2681                mode->vtotal = mode->vsync_end + 1;
2682
2683        drm_mode_do_interlace_quirk(mode, pt);
2684
2685        if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2686                pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2687        }
2688
2689        mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2690                DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2691        mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2692                DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2693
2694set_size:
2695        mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2696        mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2697
2698        if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2699                mode->width_mm *= 10;
2700                mode->height_mm *= 10;
2701        }
2702
2703        if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2704                mode->width_mm = edid->width_cm * 10;
2705                mode->height_mm = edid->height_cm * 10;
2706        }
2707
2708        mode->type = DRM_MODE_TYPE_DRIVER;
2709        drm_mode_set_name(mode);
2710
2711        return mode;
2712}
2713
2714static bool
2715mode_in_hsync_range(const struct drm_display_mode *mode,
2716                    struct edid *edid, u8 *t)
2717{
2718        int hsync, hmin, hmax;
2719
2720        hmin = t[7];
2721        if (edid->revision >= 4)
2722            hmin += ((t[4] & 0x04) ? 255 : 0);
2723        hmax = t[8];
2724        if (edid->revision >= 4)
2725            hmax += ((t[4] & 0x08) ? 255 : 0);
2726        hsync = drm_mode_hsync(mode);
2727
2728        return (hsync <= hmax && hsync >= hmin);
2729}
2730
2731static bool
2732mode_in_vsync_range(const struct drm_display_mode *mode,
2733                    struct edid *edid, u8 *t)
2734{
2735        int vsync, vmin, vmax;
2736
2737        vmin = t[5];
2738        if (edid->revision >= 4)
2739            vmin += ((t[4] & 0x01) ? 255 : 0);
2740        vmax = t[6];
2741        if (edid->revision >= 4)
2742            vmax += ((t[4] & 0x02) ? 255 : 0);
2743        vsync = drm_mode_vrefresh(mode);
2744
2745        return (vsync <= vmax && vsync >= vmin);
2746}
2747
2748static u32
2749range_pixel_clock(struct edid *edid, u8 *t)
2750{
2751        /* unspecified */
2752        if (t[9] == 0 || t[9] == 255)
2753                return 0;
2754
2755        /* 1.4 with CVT support gives us real precision, yay */
2756        if (edid->revision >= 4 && t[10] == 0x04)
2757                return (t[9] * 10000) - ((t[12] >> 2) * 250);
2758
2759        /* 1.3 is pathetic, so fuzz up a bit */
2760        return t[9] * 10000 + 5001;
2761}
2762
2763static bool
2764mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2765              struct detailed_timing *timing)
2766{
2767        u32 max_clock;
2768        u8 *t = (u8 *)timing;
2769
2770        if (!mode_in_hsync_range(mode, edid, t))
2771                return false;
2772
2773        if (!mode_in_vsync_range(mode, edid, t))
2774                return false;
2775
2776        if ((max_clock = range_pixel_clock(edid, t)))
2777                if (mode->clock > max_clock)
2778                        return false;
2779
2780        /* 1.4 max horizontal check */
2781        if (edid->revision >= 4 && t[10] == 0x04)
2782                if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2783                        return false;
2784
2785        if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2786                return false;
2787
2788        return true;
2789}
2790
2791static bool valid_inferred_mode(const struct drm_connector *connector,
2792                                const struct drm_display_mode *mode)
2793{
2794        const struct drm_display_mode *m;
2795        bool ok = false;
2796
2797        list_for_each_entry(m, &connector->probed_modes, head) {
2798                if (mode->hdisplay == m->hdisplay &&
2799                    mode->vdisplay == m->vdisplay &&
2800                    drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2801                        return false; /* duplicated */
2802                if (mode->hdisplay <= m->hdisplay &&
2803                    mode->vdisplay <= m->vdisplay)
2804                        ok = true;
2805        }
2806        return ok;
2807}
2808
2809static int
2810drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2811                        struct detailed_timing *timing)
2812{
2813        int i, modes = 0;
2814        struct drm_display_mode *newmode;
2815        struct drm_device *dev = connector->dev;
2816
2817        for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2818                if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2819                    valid_inferred_mode(connector, drm_dmt_modes + i)) {
2820                        newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2821                        if (newmode) {
2822                                drm_mode_probed_add(connector, newmode);
2823                                modes++;
2824                        }
2825                }
2826        }
2827
2828        return modes;
2829}
2830
2831/* fix up 1366x768 mode from 1368x768;
2832 * GFT/CVT can't express 1366 width which isn't dividable by 8
2833 */
2834void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2835{
2836        if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2837                mode->hdisplay = 1366;
2838                mode->hsync_start--;
2839                mode->hsync_end--;
2840                drm_mode_set_name(mode);
2841        }
2842}
2843
2844static int
2845drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2846                        struct detailed_timing *timing)
2847{
2848        int i, modes = 0;
2849        struct drm_display_mode *newmode;
2850        struct drm_device *dev = connector->dev;
2851
2852        for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2853                const struct minimode *m = &extra_modes[i];
2854
2855                newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2856                if (!newmode)
2857                        return modes;
2858
2859                drm_mode_fixup_1366x768(newmode);
2860                if (!mode_in_range(newmode, edid, timing) ||
2861                    !valid_inferred_mode(connector, newmode)) {
2862                        drm_mode_destroy(dev, newmode);
2863                        continue;
2864                }
2865
2866                drm_mode_probed_add(connector, newmode);
2867                modes++;
2868        }
2869
2870        return modes;
2871}
2872
2873static int
2874drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2875                        struct detailed_timing *timing)
2876{
2877        int i, modes = 0;
2878        struct drm_display_mode *newmode;
2879        struct drm_device *dev = connector->dev;
2880        bool rb = drm_monitor_supports_rb(edid);
2881
2882        for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2883                const struct minimode *m = &extra_modes[i];
2884
2885                newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2886                if (!newmode)
2887                        return modes;
2888
2889                drm_mode_fixup_1366x768(newmode);
2890                if (!mode_in_range(newmode, edid, timing) ||
2891                    !valid_inferred_mode(connector, newmode)) {
2892                        drm_mode_destroy(dev, newmode);
2893                        continue;
2894                }
2895
2896                drm_mode_probed_add(connector, newmode);
2897                modes++;
2898        }
2899
2900        return modes;
2901}
2902
2903static void
2904do_inferred_modes(struct detailed_timing *timing, void *c)
2905{
2906        struct detailed_mode_closure *closure = c;
2907        struct detailed_non_pixel *data = &timing->data.other_data;
2908        struct detailed_data_monitor_range *range = &data->data.range;
2909
2910        if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
2911                return;
2912
2913        closure->modes += drm_dmt_modes_for_range(closure->connector,
2914                                                  closure->edid,
2915                                                  timing);
2916
2917        if (!version_greater(closure->edid, 1, 1))
2918                return; /* GTF not defined yet */
2919
2920        switch (range->flags) {
2921        case 0x02: /* secondary gtf, XXX could do more */
2922        case 0x00: /* default gtf */
2923                closure->modes += drm_gtf_modes_for_range(closure->connector,
2924                                                          closure->edid,
2925                                                          timing);
2926                break;
2927        case 0x04: /* cvt, only in 1.4+ */
2928                if (!version_greater(closure->edid, 1, 3))
2929                        break;
2930
2931                closure->modes += drm_cvt_modes_for_range(closure->connector,
2932                                                          closure->edid,
2933                                                          timing);
2934                break;
2935        case 0x01: /* just the ranges, no formula */
2936        default:
2937                break;
2938        }
2939}
2940
2941static int
2942add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2943{
2944        struct detailed_mode_closure closure = {
2945                .connector = connector,
2946                .edid = edid,
2947        };
2948
2949        if (version_greater(edid, 1, 0))
2950                drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2951                                            &closure);
2952
2953        return closure.modes;
2954}
2955
2956static int
2957drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2958{
2959        int i, j, m, modes = 0;
2960        struct drm_display_mode *mode;
2961        u8 *est = ((u8 *)timing) + 6;
2962
2963        for (i = 0; i < 6; i++) {
2964                for (j = 7; j >= 0; j--) {
2965                        m = (i * 8) + (7 - j);
2966                        if (m >= ARRAY_SIZE(est3_modes))
2967                                break;
2968                        if (est[i] & (1 << j)) {
2969                                mode = drm_mode_find_dmt(connector->dev,
2970                                                         est3_modes[m].w,
2971                                                         est3_modes[m].h,
2972                                                         est3_modes[m].r,
2973                                                         est3_modes[m].rb);
2974                                if (mode) {
2975                                        drm_mode_probed_add(connector, mode);
2976                                        modes++;
2977                                }
2978                        }
2979                }
2980        }
2981
2982        return modes;
2983}
2984
2985static void
2986do_established_modes(struct detailed_timing *timing, void *c)
2987{
2988        struct detailed_mode_closure *closure = c;
2989
2990        if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_EST_TIMINGS))
2991                return;
2992
2993        closure->modes += drm_est3_modes(closure->connector, timing);
2994}
2995
2996/**
2997 * add_established_modes - get est. modes from EDID and add them
2998 * @connector: connector to add mode(s) to
2999 * @edid: EDID block to scan
3000 *

3001 * Each EDID block contains a bitmap of the supported "established modes" list
3002 * (defined above).  Tease them out and add them to the global modes list.
3003 */
3004static int
3005add_established_modes(struct drm_connector *connector, struct edid *edid)
3006{
3007        struct drm_device *dev = connector->dev;
3008        unsigned long est_bits = edid->established_timings.t1 |
3009                (edid->established_timings.t2 << 8) |
3010                ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3011        int i, modes = 0;
3012        struct detailed_mode_closure closure = {
3013                .connector = connector,
3014                .edid = edid,
3015        };
3016
3017        for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3018                if (est_bits & (1<<i)) {
3019                        struct drm_display_mode *newmode;
3020
3021                        newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3022                        if (newmode) {
3023                                drm_mode_probed_add(connector, newmode);
3024                                modes++;
3025                        }
3026                }
3027        }
3028
3029        if (version_greater(edid, 1, 0))
3030                    drm_for_each_detailed_block((u8 *)edid,
3031                                                do_established_modes, &closure);
3032
3033        return modes + closure.modes;
3034}
3035
3036static void
3037do_standard_modes(struct detailed_timing *timing, void *c)
3038{
3039        struct detailed_mode_closure *closure = c;
3040        struct detailed_non_pixel *data = &timing->data.other_data;
3041        struct drm_connector *connector = closure->connector;
3042        struct edid *edid = closure->edid;
3043        int i;
3044
3045        if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_STD_MODES))
3046                return;
3047
3048        for (i = 0; i < 6; i++) {
3049                struct std_timing *std = &data->data.timings[i];
3050                struct drm_display_mode *newmode;
3051
3052                newmode = drm_mode_std(connector, edid, std);
3053                if (newmode) {
3054                        drm_mode_probed_add(connector, newmode);
3055                        closure->modes++;
3056                }
3057        }
3058}
3059
3060/**
3061 * add_standard_modes - get std. modes from EDID and add them
3062 * @connector: connector to add mode(s) to
3063 * @edid: EDID block to scan
3064 *
3065 * Standard modes can be calculated using the appropriate standard (DMT,
3066 * GTF or CVT. Grab them from @edid and add them to the list.
3067 */
3068static int
3069add_standard_modes(struct drm_connector *connector, struct edid *edid)
3070{
3071        int i, modes = 0;
3072        struct detailed_mode_closure closure = {
3073                .connector = connector,
3074                .edid = edid,
3075        };
3076
3077        for (i = 0; i < EDID_STD_TIMINGS; i++) {
3078                struct drm_display_mode *newmode;
3079
3080                newmode = drm_mode_std(connector, edid,
3081                                       &edid->standard_timings[i]);
3082                if (newmode) {
3083                        drm_mode_probed_add(connector, newmode);
3084                        modes++;
3085                }
3086        }
3087
3088        if (version_greater(edid, 1, 0))
3089                drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
3090                                            &closure);
3091
3092        /* XXX should also look for standard codes in VTB blocks */
3093
3094        return modes + closure.modes;
3095}
3096
3097static int drm_cvt_modes(struct drm_connector *connector,
3098                         struct detailed_timing *timing)
3099{
3100        int i, j, modes = 0;
3101        struct drm_display_mode *newmode;
3102        struct drm_device *dev = connector->dev;
3103        struct cvt_timing *cvt;
3104        const int rates[] = { 60, 85, 75, 60, 50 };
3105        const u8 empty[3] = { 0, 0, 0 };
3106
3107        for (i = 0; i < 4; i++) {
3108                int width, height;
3109
3110                cvt = &(timing->data.other_data.data.cvt[i]);
3111
3112                if (!memcmp(cvt->code, empty, 3))
3113                        continue;
3114
3115                height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3116                switch (cvt->code[1] & 0x0c) {
3117                /* default - because compiler doesn't see that we've enumerated all cases */
3118                default:
3119                case 0x00:
3120                        width = height * 4 / 3;
3121                        break;
3122                case 0x04:
3123                        width = height * 16 / 9;
3124                        break;
3125                case 0x08:
3126                        width = height * 16 / 10;
3127                        break;
3128                case 0x0c:
3129                        width = height * 15 / 9;
3130                        break;
3131                }
3132
3133                for (j = 1; j < 5; j++) {
3134                        if (cvt->code[2] & (1 << j)) {
3135                                newmode = drm_cvt_mode(dev, width, height,
3136                                                       rates[j], j == 0,
3137                                                       false, false);
3138                                if (newmode) {
3139                                        drm_mode_probed_add(connector, newmode);
3140                                        modes++;
3141                                }
3142                        }
3143                }
3144        }
3145
3146        return modes;
3147}
3148
3149static void
3150do_cvt_mode(struct detailed_timing *timing, void *c)
3151{
3152        struct detailed_mode_closure *closure = c;
3153
3154        if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_CVT_3BYTE))
3155                return;
3156
3157        closure->modes += drm_cvt_modes(closure->connector, timing);
3158}
3159
3160static int
3161add_cvt_modes(struct drm_connector *connector, struct edid *edid)
3162{
3163        struct detailed_mode_closure closure = {
3164                .connector = connector,
3165                .edid = edid,
3166        };
3167
3168        if (version_greater(edid, 1, 2))
3169                drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
3170
3171        /* XXX should also look for CVT codes in VTB blocks */
3172
3173        return closure.modes;
3174}
3175
3176static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
3177
3178static void
3179do_detailed_mode(struct detailed_timing *timing, void *c)
3180{
3181        struct detailed_mode_closure *closure = c;
3182        struct drm_display_mode *newmode;
3183
3184        if (!is_detailed_timing_descriptor((const u8 *)timing))
3185                return;
3186
3187        newmode = drm_mode_detailed(closure->connector->dev,
3188                                    closure->edid, timing,
3189                                    closure->quirks);
3190        if (!newmode)
3191                return;
3192
3193        if (closure->preferred)
3194                newmode->type |= DRM_MODE_TYPE_PREFERRED;
3195
3196        /*
3197         * Detailed modes are limited to 10kHz pixel clock resolution,
3198         * so fix up anything that looks like CEA/HDMI mode, but the clock
3199         * is just slightly off.
3200         */
3201        fixup_detailed_cea_mode_clock(newmode);
3202
3203        drm_mode_probed_add(closure->connector, newmode);
3204        closure->modes++;
3205        closure->preferred = false;
3206}
3207
3208/*
3209 * add_detailed_modes - Add modes from detailed timings
3210 * @connector: attached connector
3211 * @edid: EDID block to scan
3212 * @quirks: quirks to apply
3213 */
3214static int
3215add_detailed_modes(struct drm_connector *connector, struct edid *edid,
3216                   u32 quirks)
3217{
3218        struct detailed_mode_closure closure = {
3219                .connector = connector,
3220                .edid = edid,
3221                .preferred = true,
3222                .quirks = quirks,
3223        };
3224
3225        if (closure.preferred && !version_greater(edid, 1, 3))
3226                closure.preferred =
3227                    (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
3228
3229        drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
3230
3231        return closure.modes;
3232}
3233
3234#define AUDIO_BLOCK     0x01
3235#define VIDEO_BLOCK     0x02
3236#define VENDOR_BLOCK    0x03
3237#define SPEAKER_BLOCK   0x04
3238#define HDR_STATIC_METADATA_BLOCK       0x6
3239#define USE_EXTENDED_TAG 0x07
3240#define EXT_VIDEO_CAPABILITY_BLOCK 0x00
3241#define EXT_VIDEO_DATA_BLOCK_420        0x0E
3242#define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
3243#define EDID_BASIC_AUDIO        (1 << 6)
3244#define EDID_CEA_YCRCB444       (1 << 5)
3245#define EDID_CEA_YCRCB422       (1 << 4)
3246#define EDID_CEA_VCDB_QS        (1 << 6)
3247
3248/*
3249 * Search EDID for CEA extension block.
3250 */
3251const u8 *drm_find_edid_extension(const struct edid *edid,
3252                                  int ext_id, int *ext_index)
3253{
3254        const u8 *edid_ext = NULL;
3255        int i;
3256
3257        /* No EDID or EDID extensions */
3258        if (edid == NULL || edid->extensions == 0)
3259                return NULL;
3260
3261        /* Find CEA extension */
3262        for (i = *ext_index; i < edid->extensions; i++) {
3263                edid_ext = (const u8 *)edid + EDID_LENGTH * (i + 1);
3264                if (edid_ext[0] == ext_id)
3265                        break;
3266        }
3267
3268        if (i >= edid->extensions)
3269                return NULL;
3270
3271        *ext_index = i + 1;
3272
3273        return edid_ext;
3274}
3275
3276static const u8 *drm_find_cea_extension(const struct edid *edid)
3277{
3278        const struct displayid_block *block;
3279        struct displayid_iter iter;
3280        const u8 *cea;
3281        int ext_index = 0;
3282
3283        /* Look for a top level CEA extension block */
3284        /* FIXME: make callers iterate through multiple CEA ext blocks? */
3285        cea = drm_find_edid_extension(edid, CEA_EXT, &ext_index);
3286        if (cea)
3287                return cea;
3288
3289        /* CEA blocks can also be found embedded in a DisplayID block */
3290        displayid_iter_edid_begin(edid, &iter);
3291        displayid_iter_for_each(block, &iter) {
3292                if (block->tag == DATA_BLOCK_CTA) {
3293                        cea = (const u8 *)block;
3294                        break;
3295                }
3296        }
3297        displayid_iter_end(&iter);
3298
3299        return cea;
3300}
3301
3302static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
3303{
3304        BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
3305        BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
3306
3307        if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
3308                return &edid_cea_modes_1[vic - 1];
3309        if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
3310                return &edid_cea_modes_193[vic - 193];
3311        return NULL;
3312}
3313
3314static u8 cea_num_vics(void)
3315{
3316        return 193 + ARRAY_SIZE(edid_cea_modes_193);
3317}
3318
3319static u8 cea_next_vic(u8 vic)
3320{
3321        if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
3322                vic = 193;
3323        return vic;
3324}
3325
3326/*
3327 * Calculate the alternate clock for the CEA mode
3328 * (60Hz vs. 59.94Hz etc.)
3329 */
3330static unsigned int
3331cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
3332{
3333        unsigned int clock = cea_mode->clock;
3334
3335        if (drm_mode_vrefresh(cea_mode) % 6 != 0)
3336                return clock;
3337
3338        /*
3339         * edid_cea_modes contains the 59.94Hz
3340         * variant for 240 and 480 line modes,
3341         * and the 60Hz variant otherwise.
3342         */
3343        if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
3344                clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
3345        else
3346                clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
3347
3348        return clock;
3349}
3350
3351static bool
3352cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
3353{
3354        /*
3355         * For certain VICs the spec allows the vertical
3356         * front porch to vary by one or two lines.
3357         *
3358         * cea_modes[] stores the variant with the shortest
3359         * vertical front porch. We can adjust the mode to
3360         * get the other variants by simply increasing the
3361         * vertical front porch length.
3362         */
3363        BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
3364                     cea_mode_for_vic(9)->vtotal != 262 ||
3365                     cea_mode_for_vic(12)->vtotal != 262 ||
3366                     cea_mode_for_vic(13)->vtotal != 262 ||
3367                     cea_mode_for_vic(23)->vtotal != 312 ||
3368                     cea_mode_for_vic(24)->vtotal != 312 ||
3369                     cea_mode_for_vic(27)->vtotal != 312 ||
3370                     cea_mode_for_vic(28)->vtotal != 312);
3371
3372        if (((vic == 8 || vic == 9 ||
3373              vic == 12 || vic == 13) && mode->vtotal < 263) ||
3374            ((vic == 23 || vic == 24 ||
3375              vic == 27 || vic == 28) && mode->vtotal < 314)) {
3376                mode->vsync_start++;
3377                mode->vsync_end++;
3378                mode->vtotal++;
3379
3380                return true;
3381        }
3382
3383        return false;
3384}
3385
3386static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
3387                                             unsigned int clock_tolerance)
3388{
3389        unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3390        u8 vic;
3391
3392        if (!to_match->clock)
3393                return 0;
3394
3395        if (to_match->picture_aspect_ratio)
3396                match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3397
3398        for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3399                struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
3400                unsigned int clock1, clock2;
3401
3402                /* Check both 60Hz and 59.94Hz */
3403                clock1 = cea_mode.clock;
3404                clock2 = cea_mode_alternate_clock(&cea_mode);
3405
3406                if (abs(to_match->clock - clock1) > clock_tolerance &&
3407                    abs(to_match->clock - clock2) > clock_tolerance)
3408                        continue;
3409
3410                do {
3411                        if (drm_mode_match(to_match, &cea_mode, match_flags))
3412                                return vic;
3413                } while (cea_mode_alternate_timings(vic, &cea_mode));
3414        }
3415
3416        return 0;
3417}
3418
3419/**
3420 * drm_match_cea_mode - look for a CEA mode matching given mode
3421 * @to_match: display mode
3422 *
3423 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
3424 * mode.
3425 */
3426u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
3427{
3428        unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3429        u8 vic;
3430
3431        if (!to_match->clock)
3432                return 0;
3433
3434        if (to_match->picture_aspect_ratio)
3435                match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3436
3437        for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3438                struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
3439                unsigned int clock1, clock2;
3440
3441                /* Check both 60Hz and 59.94Hz */
3442                clock1 = cea_mode.clock;
3443                clock2 = cea_mode_alternate_clock(&cea_mode);
3444
3445                if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
3446                    KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
3447                        continue;
3448
3449                do {
3450                        if (drm_mode_match(to_match, &cea_mode, match_flags))
3451                                return vic;
3452                } while (cea_mode_alternate_timings(vic, &cea_mode));
3453        }
3454
3455        return 0;
3456}
3457EXPORT_SYMBOL(drm_match_cea_mode);
3458
3459static bool drm_valid_cea_vic(u8 vic)
3460{
3461        return cea_mode_for_vic(vic) != NULL;
3462}
3463
3464static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
3465{
3466        const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
3467
3468        if (mode)
3469                return mode->picture_aspect_ratio;
3470
3471        return HDMI_PICTURE_ASPECT_NONE;
3472}
3473
3474static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
3475{
3476        return edid_4k_modes[video_code].picture_aspect_ratio;
3477}
3478
3479/*
3480 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3481 * specific block).
3482 */
3483static unsigned int
3484hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3485{
3486        return cea_mode_alternate_clock(hdmi_mode);
3487}
3488
3489static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3490                                              unsigned int clock_tolerance)
3491{
3492        unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3493        u8 vic;
3494
3495        if (!to_match->clock)
3496                return 0;
3497
3498        if (to_match->picture_aspect_ratio)
3499                match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3500
3501        for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3502                const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3503                unsigned int clock1, clock2;
3504
3505                /* Make sure to also match alternate clocks */
3506                clock1 = hdmi_mode->clock;
3507                clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3508
3509                if (abs(to_match->clock - clock1) > clock_tolerance &&
3510                    abs(to_match->clock - clock2) > clock_tolerance)
3511                        continue;
3512
3513                if (drm_mode_match(to_match, hdmi_mode, match_flags))
3514                        return vic;
3515        }
3516
3517        return 0;
3518}
3519
3520/*
3521 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3522 * @to_match: display mode
3523 *
3524 * An HDMI mode is one defined in the HDMI vendor specific block.
3525 *
3526 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3527 */
3528static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3529{
3530        unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3531        u8 vic;
3532
3533        if (!to_match->clock)
3534                return 0;
3535
3536        if (to_match->picture_aspect_ratio)
3537                match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3538
3539        for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3540                const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3541                unsigned int clock1, clock2;
3542
3543                /* Make sure to also match alternate clocks */
3544                clock1 = hdmi_mode->clock;
3545                clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3546
3547                if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3548                     KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3549                    drm_mode_match(to_match, hdmi_mode, match_flags))
3550                        return vic;
3551        }
3552        return 0;
3553}
3554
3555static bool drm_valid_hdmi_vic(u8 vic)
3556{
3557        return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3558}
3559
3560static int
3561add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3562{
3563        struct drm_device *dev = connector->dev;
3564        struct drm_display_mode *mode, *tmp;
3565        LIST_HEAD(list);
3566        int modes = 0;
3567
3568        /* Don't add CEA modes if the CEA extension block is missing */
3569        if (!drm_find_cea_extension(edid))
3570                return 0;
3571
3572        /*
3573         * Go through all probed modes and create a new mode
3574         * with the alternate clock for certain CEA modes.
3575         */
3576        list_for_each_entry(mode, &connector->probed_modes, head) {
3577                const struct drm_display_mode *cea_mode = NULL;
3578                struct drm_display_mode *newmode;
3579                u8 vic = drm_match_cea_mode(mode);
3580                unsigned int clock1, clock2;
3581
3582                if (drm_valid_cea_vic(vic)) {
3583                        cea_mode = cea_mode_for_vic(vic);
3584                        clock2 = cea_mode_alternate_clock(cea_mode);
3585                } else {
3586                        vic = drm_match_hdmi_mode(mode);
3587                        if (drm_valid_hdmi_vic(vic)) {
3588                                cea_mode = &edid_4k_modes[vic];
3589                                clock2 = hdmi_mode_alternate_clock(cea_mode);
3590                        }
3591                }
3592
3593                if (!cea_mode)
3594                        continue;
3595
3596                clock1 = cea_mode->clock;
3597
3598                if (clock1 == clock2)
3599                        continue;
3600
3601                if (mode->clock != clock1 && mode->clock != clock2)
3602                        continue;
3603
3604                newmode = drm_mode_duplicate(dev, cea_mode);
3605                if (!newmode)
3606                        continue;
3607
3608                /* Carry over the stereo flags */
3609                newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3610
3611                /*
3612                 * The current mode could be either variant. Make
3613                 * sure to pick the "other" clock for the new mode.
3614                 */
3615                if (mode->clock != clock1)
3616                        newmode->clock = clock1;
3617                else
3618                        newmode->clock = clock2;
3619
3620                list_add_tail(&newmode->head, &list);
3621        }
3622
3623        list_for_each_entry_safe(mode, tmp, &list, head) {
3624                list_del(&mode->head);
3625                drm_mode_probed_add(connector, mode);
3626                modes++;
3627        }
3628
3629        return modes;
3630}
3631
3632static u8 svd_to_vic(u8 svd)
3633{
3634        /* 0-6 bit vic, 7th bit native mode indicator */
3635        if ((svd >= 1 &&  svd <= 64) || (svd >= 129 && svd <= 192))
3636                return svd & 127;
3637
3638        return svd;
3639}
3640
3641static struct drm_display_mode *
3642drm_display_mode_from_vic_index(struct drm_connector *connector,
3643                                const u8 *video_db, u8 video_len,
3644                                u8 video_index)
3645{
3646        struct drm_device *dev = connector->dev;
3647        struct drm_display_mode *newmode;
3648        u8 vic;
3649
3650        if (video_db == NULL || video_index >= video_len)
3651                return NULL;
3652
3653        /* CEA modes are numbered 1..127 */
3654        vic = svd_to_vic(video_db[video_index]);
3655        if (!drm_valid_cea_vic(vic))
3656                return NULL;
3657
3658        newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
3659        if (!newmode)
3660                return NULL;
3661
3662        return newmode;
3663}
3664
3665/*
3666 * do_y420vdb_modes - Parse YCBCR 420 only modes
3667 * @connector: connector corresponding to the HDMI sink
3668 * @svds: start of the data block of CEA YCBCR 420 VDB
3669 * @len: length of the CEA YCBCR 420 VDB
3670 *
3671 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3672 * which contains modes which can be supported in YCBCR 420
3673 * output format only.
3674 */
3675static int do_y420vdb_modes(struct drm_connector *connector,
3676                            const u8 *svds, u8 svds_len)
3677{
3678        int modes = 0, i;
3679        struct drm_device *dev = connector->dev;
3680        struct drm_display_info *info = &connector->display_info;
3681        struct drm_hdmi_info *hdmi = &info->hdmi;
3682
3683        for (i = 0; i < svds_len; i++) {
3684                u8 vic = svd_to_vic(svds[i]);
3685                struct drm_display_mode *newmode;
3686
3687                if (!drm_valid_cea_vic(vic))
3688                        continue;
3689
3690                newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
3691                if (!newmode)
3692                        break;
3693                bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3694                drm_mode_probed_add(connector, newmode);
3695                modes++;
3696        }
3697
3698        if (modes > 0)
3699                info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3700        return modes;
3701}
3702
3703/*
3704 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3705 * @connector: connector corresponding to the HDMI sink
3706 * @vic: CEA vic for the video mode to be added in the map
3707 *
3708 * Makes an entry for a videomode in the YCBCR 420 bitmap
3709 */
3710static void
3711drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3712{
3713        u8 vic = svd_to_vic(svd);
3714        struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3715
3716        if (!drm_valid_cea_vic(vic))
3717                return;
3718
3719        bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3720}
3721
3722/**
3723 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
3724 * @dev: DRM device
3725 * @video_code: CEA VIC of the mode
3726 *
3727 * Creates a new mode matching the specified CEA VIC.
3728 *
3729 * Returns: A new drm_display_mode on success or NULL on failure
3730 */
3731struct drm_display_mode *
3732drm_display_mode_from_cea_vic(struct drm_device *dev,
3733                              u8 video_code)
3734{
3735        const struct drm_display_mode *cea_mode;
3736        struct drm_display_mode *newmode;
3737
3738        cea_mode = cea_mode_for_vic(video_code);
3739        if (!cea_mode)
3740                return NULL;
3741
3742        newmode = drm_mode_duplicate(dev, cea_mode);
3743        if (!newmode)
3744                return NULL;
3745
3746        return newmode;
3747}
3748EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
3749
3750static int
3751do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3752{
3753        int i, modes = 0;
3754        struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3755
3756        for (i = 0; i < len; i++) {
3757                struct drm_display_mode *mode;
3758
3759                mode = drm_display_mode_from_vic_index(connector, db, len, i);
3760                if (mode) {
3761                        /*
3762                         * YCBCR420 capability block contains a bitmap which
3763                         * gives the index of CEA modes from CEA VDB, which
3764                         * can support YCBCR 420 sampling output also (apart
3765                         * from RGB/YCBCR444 etc).
3766                         * For example, if the bit 0 in bitmap is set,
3767                         * first mode in VDB can support YCBCR420 output too.
3768                         * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3769                         */
3770                        if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3771                                drm_add_cmdb_modes(connector, db[i]);
3772
3773                        drm_mode_probed_add(connector, mode);
3774                        modes++;
3775                }
3776        }
3777
3778        return modes;
3779}
3780
3781struct stereo_mandatory_mode {
3782        int width, height, vrefresh;
3783        unsigned int flags;
3784};
3785
3786static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3787        { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3788        { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3789        { 1920, 1080, 50,
3790          DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3791        { 1920, 1080, 60,
3792          DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3793        { 1280, 720,  50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3794        { 1280, 720,  50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3795        { 1280, 720,  60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3796        { 1280, 720,  60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3797};
3798
3799static bool
3800stereo_match_mandatory(const struct drm_display_mode *mode,
3801                       const struct stereo_mandatory_mode *stereo_mode)
3802{
3803        unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3804
3805        return mode->hdisplay == stereo_mode->width &&
3806               mode->vdisplay == stereo_mode->height &&
3807               interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3808               drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3809}
3810
3811static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3812{
3813        struct drm_device *dev = connector->dev;
3814        const struct drm_display_mode *mode;
3815        struct list_head stereo_modes;
3816        int modes = 0, i;
3817
3818        INIT_LIST_HEAD(&stereo_modes);
3819
3820        list_for_each_entry(mode, &connector->probed_modes, head) {
3821                for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3822                        const struct stereo_mandatory_mode *mandatory;
3823                        struct drm_display_mode *new_mode;
3824
3825                        if (!stereo_match_mandatory(mode,
3826                                                    &stereo_mandatory_modes[i]))
3827                                continue;
3828
3829                        mandatory = &stereo_mandatory_modes[i];
3830                        new_mode = drm_mode_duplicate(dev, mode);
3831                        if (!new_mode)
3832                                continue;
3833
3834                        new_mode->flags |= mandatory->flags;
3835                        list_add_tail(&new_mode->head, &stereo_modes);
3836                        modes++;
3837                }
3838        }
3839
3840        list_splice_tail(&stereo_modes, &connector->probed_modes);
3841
3842        return modes;
3843}
3844
3845static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3846{
3847        struct drm_device *dev = connector->dev;
3848        struct drm_display_mode *newmode;
3849
3850        if (!drm_valid_hdmi_vic(vic)) {
3851                DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3852                return 0;
3853        }
3854
3855        newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3856        if (!newmode)
3857                return 0;
3858
3859        drm_mode_probed_add(connector, newmode);
3860
3861        return 1;
3862}
3863
3864static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3865                               const u8 *video_db, u8 video_len, u8 video_index)
3866{
3867        struct drm_display_mode *newmode;
3868        int modes = 0;
3869
3870        if (structure & (1 << 0)) {
3871                newmode = drm_display_mode_from_vic_index(connector, video_db,
3872                                                          video_len,
3873                                                          video_index);
3874                if (newmode) {
3875                        newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3876                        drm_mode_probed_add(connector, newmode);
3877                        modes++;
3878                }
3879        }
3880        if (structure & (1 << 6)) {
3881                newmode = drm_display_mode_from_vic_index(connector, video_db,
3882                                                          video_len,
3883                                                          video_index);
3884                if (newmode) {
3885                        newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3886                        drm_mode_probed_add(connector, newmode);
3887                        modes++;
3888                }
3889        }
3890        if (structure & (1 << 8)) {
3891                newmode = drm_display_mode_from_vic_index(connector, video_db,
3892                                                          video_len,
3893                                                          video_index);
3894                if (newmode) {
3895                        newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3896                        drm_mode_probed_add(connector, newmode);
3897                        modes++;
3898                }
3899        }
3900
3901        return modes;
3902}
3903
3904/*
3905 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3906 * @connector: connector corresponding to the HDMI sink
3907 * @db: start of the CEA vendor specific block
3908 * @len: length of the CEA block payload, ie. one can access up to db[len]
3909 *
3910 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3911 * also adds the stereo 3d modes when applicable.
3912 */
3913static int
3914do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3915                   const u8 *video_db, u8 video_len)
3916{
3917        struct drm_display_info *info = &connector->display_info;
3918        int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3919        u8 vic_len, hdmi_3d_len = 0;
3920        u16 mask;
3921        u16 structure_all;
3922
3923        if (len < 8)
3924                goto out;
3925
3926        /* no HDMI_Video_Present */
3927        if (!(db[8] & (1 << 5)))
3928                goto out;
3929
3930        /* Latency_Fields_Present */
3931        if (db[8] & (1 << 7))
3932                offset += 2;
3933
3934        /* I_Latency_Fields_Present */
3935        if (db[8] & (1 << 6))
3936                offset += 2;
3937
3938        /* the declared length is not long enough for the 2 first bytes
3939         * of additional video format capabilities */
3940        if (len < (8 + offset + 2))
3941                goto out;
3942
3943        /* 3D_Present */
3944        offset++;
3945        if (db[8 + offset] & (1 << 7)) {
3946                modes += add_hdmi_mandatory_stereo_modes(connector);
3947
3948                /* 3D_Multi_present */
3949                multi_present = (db[8 + offset] & 0x60) >> 5;
3950        }
3951
3952        offset++;
3953        vic_len = db[8 + offset] >> 5;
3954        hdmi_3d_len = db[8 + offset] & 0x1f;
3955
3956        for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3957                u8 vic;
3958
3959                vic = db[9 + offset + i];
3960                modes += add_hdmi_mode(connector, vic);
3961        }
3962        offset += 1 + vic_len;
3963
3964        if (multi_present == 1)
3965                multi_len = 2;
3966        else if (multi_present == 2)
3967                multi_len = 4;
3968        else
3969                multi_len = 0;
3970
3971        if (len < (8 + offset + hdmi_3d_len - 1))
3972                goto out;
3973
3974        if (hdmi_3d_len < multi_len)
3975                goto out;
3976
3977        if (multi_present == 1 || multi_present == 2) {
3978                /* 3D_Structure_ALL */
3979                structure_all = (db[8 + offset] << 8) | db[9 + offset];
3980
3981                /* check if 3D_MASK is present */
3982                if (multi_present == 2)
3983                        mask = (db[10 + offset] << 8) | db[11 + offset];
3984                else
3985                        mask = 0xffff;
3986
3987                for (i = 0; i < 16; i++) {
3988                        if (mask & (1 << i))
3989                                modes += add_3d_struct_modes(connector,
3990                                                structure_all,
3991                                                video_db,
3992                                                video_len, i);
3993                }
3994        }
3995
3996        offset += multi_len;
3997
3998        for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3999                int vic_index;
4000                struct drm_display_mode *newmode = NULL;

4001                unsigned int newflag = 0;
4002                bool detail_present;
4003
4004                detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4005
4006                if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4007                        break;
4008
4009                /* 2D_VIC_order_X */
4010                vic_index = db[8 + offset + i] >> 4;
4011
4012                /* 3D_Structure_X */
4013                switch (db[8 + offset + i] & 0x0f) {
4014                case 0:
4015                        newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4016                        break;
4017                case 6:
4018                        newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4019                        break;
4020                case 8:
4021                        /* 3D_Detail_X */
4022                        if ((db[9 + offset + i] >> 4) == 1)
4023                                newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4024                        break;
4025                }
4026
4027                if (newflag != 0) {
4028                        newmode = drm_display_mode_from_vic_index(connector,
4029                                                                  video_db,
4030                                                                  video_len,
4031                                                                  vic_index);
4032
4033                        if (newmode) {
4034                                newmode->flags |= newflag;
4035                                drm_mode_probed_add(connector, newmode);
4036                                modes++;
4037                        }
4038                }
4039
4040                if (detail_present)
4041                        i++;
4042        }
4043
4044out:
4045        if (modes > 0)
4046                info->has_hdmi_infoframe = true;
4047        return modes;
4048}
4049
4050static int
4051cea_db_payload_len(const u8 *db)
4052{
4053        return db[0] & 0x1f;
4054}
4055
4056static int
4057cea_db_extended_tag(const u8 *db)
4058{
4059        return db[1];
4060}
4061
4062static int
4063cea_db_tag(const u8 *db)
4064{
4065        return db[0] >> 5;
4066}
4067
4068static int
4069cea_revision(const u8 *cea)
4070{
4071        /*
4072         * FIXME is this correct for the DispID variant?
4073         * The DispID spec doesn't really specify whether
4074         * this is the revision of the CEA extension or
4075         * the DispID CEA data block. And the only value
4076         * given as an example is 0.
4077         */
4078        return cea[1];
4079}
4080
4081static int
4082cea_db_offsets(const u8 *cea, int *start, int *end)
4083{
4084        /* DisplayID CTA extension blocks and top-level CEA EDID
4085         * block header definitions differ in the following bytes:
4086         *   1) Byte 2 of the header specifies length differently,
4087         *   2) Byte 3 is only present in the CEA top level block.
4088         *
4089         * The different definitions for byte 2 follow.
4090         *
4091         * DisplayID CTA extension block defines byte 2 as:
4092         *   Number of payload bytes
4093         *
4094         * CEA EDID block defines byte 2 as:
4095         *   Byte number (decimal) within this block where the 18-byte
4096         *   DTDs begin. If no non-DTD data is present in this extension
4097         *   block, the value should be set to 04h (the byte after next).
4098         *   If set to 00h, there are no DTDs present in this block and
4099         *   no non-DTD data.
4100         */
4101        if (cea[0] == DATA_BLOCK_CTA) {
4102                /*
4103                 * for_each_displayid_db() has already verified
4104                 * that these stay within expected bounds.
4105                 */
4106                *start = 3;
4107                *end = *start + cea[2];
4108        } else if (cea[0] == CEA_EXT) {
4109                /* Data block offset in CEA extension block */
4110                *start = 4;
4111                *end = cea[2];
4112                if (*end == 0)
4113                        *end = 127;
4114                if (*end < 4 || *end > 127)
4115                        return -ERANGE;
4116        } else {
4117                return -EOPNOTSUPP;
4118        }
4119
4120        return 0;
4121}
4122
4123static bool cea_db_is_hdmi_vsdb(const u8 *db)
4124{
4125        int hdmi_id;
4126
4127        if (cea_db_tag(db) != VENDOR_BLOCK)
4128                return false;
4129
4130        if (cea_db_payload_len(db) < 5)
4131                return false;
4132
4133        hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
4134
4135        return hdmi_id == HDMI_IEEE_OUI;
4136}
4137
4138static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
4139{
4140        unsigned int oui;
4141
4142        if (cea_db_tag(db) != VENDOR_BLOCK)
4143                return false;
4144
4145        if (cea_db_payload_len(db) < 7)
4146                return false;
4147
4148        oui = db[3] << 16 | db[2] << 8 | db[1];
4149
4150        return oui == HDMI_FORUM_IEEE_OUI;
4151}
4152
4153static bool cea_db_is_vcdb(const u8 *db)
4154{
4155        if (cea_db_tag(db) != USE_EXTENDED_TAG)
4156                return false;
4157
4158        if (cea_db_payload_len(db) != 2)
4159                return false;
4160
4161        if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK)
4162                return false;
4163
4164        return true;
4165}
4166
4167static bool cea_db_is_y420cmdb(const u8 *db)
4168{
4169        if (cea_db_tag(db) != USE_EXTENDED_TAG)
4170                return false;
4171
4172        if (!cea_db_payload_len(db))
4173                return false;
4174
4175        if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
4176                return false;
4177
4178        return true;
4179}
4180
4181static bool cea_db_is_y420vdb(const u8 *db)
4182{
4183        if (cea_db_tag(db) != USE_EXTENDED_TAG)
4184                return false;
4185
4186        if (!cea_db_payload_len(db))
4187                return false;
4188
4189        if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
4190                return false;
4191
4192        return true;
4193}
4194
4195#define for_each_cea_db(cea, i, start, end) \
4196        for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
4197
4198static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
4199                                      const u8 *db)
4200{
4201        struct drm_display_info *info = &connector->display_info;
4202        struct drm_hdmi_info *hdmi = &info->hdmi;
4203        u8 map_len = cea_db_payload_len(db) - 1;
4204        u8 count;
4205        u64 map = 0;
4206
4207        if (map_len == 0) {
4208                /* All CEA modes support ycbcr420 sampling also.*/
4209                hdmi->y420_cmdb_map = U64_MAX;
4210                info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
4211                return;
4212        }
4213
4214        /*
4215         * This map indicates which of the existing CEA block modes
4216         * from VDB can support YCBCR420 output too. So if bit=0 is
4217         * set, first mode from VDB can support YCBCR420 output too.
4218         * We will parse and keep this map, before parsing VDB itself
4219         * to avoid going through the same block again and again.
4220         *
4221         * Spec is not clear about max possible size of this block.
4222         * Clamping max bitmap block size at 8 bytes. Every byte can
4223         * address 8 CEA modes, in this way this map can address
4224         * 8*8 = first 64 SVDs.
4225         */
4226        if (WARN_ON_ONCE(map_len > 8))
4227                map_len = 8;
4228
4229        for (count = 0; count < map_len; count++)
4230                map |= (u64)db[2 + count] << (8 * count);
4231
4232        if (map)
4233                info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
4234
4235        hdmi->y420_cmdb_map = map;
4236}
4237
4238static int
4239add_cea_modes(struct drm_connector *connector, struct edid *edid)
4240{
4241        const u8 *cea = drm_find_cea_extension(edid);
4242        const u8 *db, *hdmi = NULL, *video = NULL;
4243        u8 dbl, hdmi_len, video_len = 0;
4244        int modes = 0;
4245
4246        if (cea && cea_revision(cea) >= 3) {
4247                int i, start, end;
4248
4249                if (cea_db_offsets(cea, &start, &end))
4250                        return 0;
4251
4252                for_each_cea_db(cea, i, start, end) {
4253                        db = &cea[i];
4254                        dbl = cea_db_payload_len(db);
4255
4256                        if (cea_db_tag(db) == VIDEO_BLOCK) {
4257                                video = db + 1;
4258                                video_len = dbl;
4259                                modes += do_cea_modes(connector, video, dbl);
4260                        } else if (cea_db_is_hdmi_vsdb(db)) {
4261                                hdmi = db;
4262                                hdmi_len = dbl;
4263                        } else if (cea_db_is_y420vdb(db)) {
4264                                const u8 *vdb420 = &db[2];
4265
4266                                /* Add 4:2:0(only) modes present in EDID */
4267                                modes += do_y420vdb_modes(connector,
4268                                                          vdb420,
4269                                                          dbl - 1);
4270                        }
4271                }
4272        }
4273
4274        /*
4275         * We parse the HDMI VSDB after having added the cea modes as we will
4276         * be patching their flags when the sink supports stereo 3D.
4277         */
4278        if (hdmi)
4279                modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
4280                                            video_len);
4281
4282        return modes;
4283}
4284
4285static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
4286{
4287        const struct drm_display_mode *cea_mode;
4288        int clock1, clock2, clock;
4289        u8 vic;
4290        const char *type;
4291
4292        /*
4293         * allow 5kHz clock difference either way to account for
4294         * the 10kHz clock resolution limit of detailed timings.
4295         */
4296        vic = drm_match_cea_mode_clock_tolerance(mode, 5);
4297        if (drm_valid_cea_vic(vic)) {
4298                type = "CEA";
4299                cea_mode = cea_mode_for_vic(vic);
4300                clock1 = cea_mode->clock;
4301                clock2 = cea_mode_alternate_clock(cea_mode);
4302        } else {
4303                vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
4304                if (drm_valid_hdmi_vic(vic)) {
4305                        type = "HDMI";
4306                        cea_mode = &edid_4k_modes[vic];
4307                        clock1 = cea_mode->clock;
4308                        clock2 = hdmi_mode_alternate_clock(cea_mode);
4309                } else {
4310                        return;
4311                }
4312        }
4313
4314        /* pick whichever is closest */
4315        if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
4316                clock = clock1;
4317        else
4318                clock = clock2;
4319
4320        if (mode->clock == clock)
4321                return;
4322
4323        DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
4324                  type, vic, mode->clock, clock);
4325        mode->clock = clock;
4326}
4327
4328static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
4329{
4330        if (cea_db_tag(db) != USE_EXTENDED_TAG)
4331                return false;
4332
4333        if (db[1] != HDR_STATIC_METADATA_BLOCK)
4334                return false;
4335
4336        if (cea_db_payload_len(db) < 3)
4337                return false;
4338
4339        return true;
4340}
4341
4342static uint8_t eotf_supported(const u8 *edid_ext)
4343{
4344        return edid_ext[2] &
4345                (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
4346                 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
4347                 BIT(HDMI_EOTF_SMPTE_ST2084) |
4348                 BIT(HDMI_EOTF_BT_2100_HLG));
4349}
4350
4351static uint8_t hdr_metadata_type(const u8 *edid_ext)
4352{
4353        return edid_ext[3] &
4354                BIT(HDMI_STATIC_METADATA_TYPE1);
4355}
4356
4357static void
4358drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
4359{
4360        u16 len;
4361
4362        len = cea_db_payload_len(db);
4363
4364        connector->hdr_sink_metadata.hdmi_type1.eotf =
4365                                                eotf_supported(db);
4366        connector->hdr_sink_metadata.hdmi_type1.metadata_type =
4367                                                hdr_metadata_type(db);
4368
4369        if (len >= 4)
4370                connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
4371        if (len >= 5)
4372                connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
4373        if (len >= 6)
4374                connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
4375}
4376
4377static void
4378drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
4379{
4380        u8 len = cea_db_payload_len(db);
4381
4382        if (len >= 6 && (db[6] & (1 << 7)))
4383                connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
4384        if (len >= 8) {
4385                connector->latency_present[0] = db[8] >> 7;
4386                connector->latency_present[1] = (db[8] >> 6) & 1;
4387        }
4388        if (len >= 9)
4389                connector->video_latency[0] = db[9];
4390        if (len >= 10)
4391                connector->audio_latency[0] = db[10];
4392        if (len >= 11)
4393                connector->video_latency[1] = db[11];
4394        if (len >= 12)
4395                connector->audio_latency[1] = db[12];
4396
4397        DRM_DEBUG_KMS("HDMI: latency present %d %d, "
4398                      "video latency %d %d, "
4399                      "audio latency %d %d\n",
4400                      connector->latency_present[0],
4401                      connector->latency_present[1],
4402                      connector->video_latency[0],
4403                      connector->video_latency[1],
4404                      connector->audio_latency[0],
4405                      connector->audio_latency[1]);
4406}
4407
4408static void
4409monitor_name(struct detailed_timing *t, void *data)
4410{
4411        if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME))
4412                return;
4413
4414        *(u8 **)data = t->data.other_data.data.str.str;
4415}
4416
4417static int get_monitor_name(struct edid *edid, char name[13])
4418{
4419        char *edid_name = NULL;
4420        int mnl;
4421
4422        if (!edid || !name)
4423                return 0;
4424
4425        drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
4426        for (mnl = 0; edid_name && mnl < 13; mnl++) {
4427                if (edid_name[mnl] == 0x0a)
4428                        break;
4429
4430                name[mnl] = edid_name[mnl];
4431        }
4432
4433        return mnl;
4434}
4435
4436/**
4437 * drm_edid_get_monitor_name - fetch the monitor name from the edid
4438 * @edid: monitor EDID information
4439 * @name: pointer to a character array to hold the name of the monitor
4440 * @bufsize: The size of the name buffer (should be at least 14 chars.)
4441 *
4442 */
4443void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
4444{
4445        int name_length;
4446        char buf[13];
4447
4448        if (bufsize <= 0)
4449                return;
4450
4451        name_length = min(get_monitor_name(edid, buf), bufsize - 1);
4452        memcpy(name, buf, name_length);
4453        name[name_length] = '\0';
4454}
4455EXPORT_SYMBOL(drm_edid_get_monitor_name);
4456
4457static void clear_eld(struct drm_connector *connector)
4458{
4459        memset(connector->eld, 0, sizeof(connector->eld));
4460
4461        connector->latency_present[0] = false;
4462        connector->latency_present[1] = false;
4463        connector->video_latency[0] = 0;
4464        connector->audio_latency[0] = 0;
4465        connector->video_latency[1] = 0;
4466        connector->audio_latency[1] = 0;
4467}
4468
4469/*
4470 * drm_edid_to_eld - build ELD from EDID
4471 * @connector: connector corresponding to the HDMI/DP sink
4472 * @edid: EDID to parse
4473 *
4474 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
4475 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
4476 */
4477static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
4478{
4479        uint8_t *eld = connector->eld;
4480        const u8 *cea;
4481        const u8 *db;
4482        int total_sad_count = 0;
4483        int mnl;
4484        int dbl;
4485
4486        clear_eld(connector);
4487
4488        if (!edid)
4489                return;
4490
4491        cea = drm_find_cea_extension(edid);
4492        if (!cea) {
4493                DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
4494                return;
4495        }
4496
4497        mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
4498        DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
4499
4500        eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
4501        eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
4502
4503        eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
4504
4505        eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
4506        eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
4507        eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
4508        eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
4509
4510        if (cea_revision(cea) >= 3) {
4511                int i, start, end;
4512                int sad_count;
4513
4514                if (cea_db_offsets(cea, &start, &end)) {
4515                        start = 0;
4516                        end = 0;
4517                }
4518
4519                for_each_cea_db(cea, i, start, end) {
4520                        db = &cea[i];
4521                        dbl = cea_db_payload_len(db);
4522
4523                        switch (cea_db_tag(db)) {
4524                        case AUDIO_BLOCK:
4525                                /* Audio Data Block, contains SADs */
4526                                sad_count = min(dbl / 3, 15 - total_sad_count);
4527                                if (sad_count >= 1)
4528                                        memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
4529                                               &db[1], sad_count * 3);
4530                                total_sad_count += sad_count;
4531                                break;
4532                        case SPEAKER_BLOCK:
4533                                /* Speaker Allocation Data Block */
4534                                if (dbl >= 1)
4535                                        eld[DRM_ELD_SPEAKER] = db[1];
4536                                break;
4537                        case VENDOR_BLOCK:
4538                                /* HDMI Vendor-Specific Data Block */
4539                                if (cea_db_is_hdmi_vsdb(db))
4540                                        drm_parse_hdmi_vsdb_audio(connector, db);
4541                                break;
4542                        default:
4543                                break;
4544                        }
4545                }
4546        }
4547        eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
4548
4549        if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4550            connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4551                eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
4552        else
4553                eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
4554
4555        eld[DRM_ELD_BASELINE_ELD_LEN] =
4556                DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
4557
4558        DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
4559                      drm_eld_size(eld), total_sad_count);
4560}
4561
4562/**
4563 * drm_edid_to_sad - extracts SADs from EDID
4564 * @edid: EDID to parse
4565 * @sads: pointer that will be set to the extracted SADs
4566 *
4567 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
4568 *
4569 * Note: The returned pointer needs to be freed using kfree().
4570 *
4571 * Return: The number of found SADs or negative number on error.
4572 */
4573int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
4574{
4575        int count = 0;
4576        int i, start, end, dbl;
4577        const u8 *cea;
4578
4579        cea = drm_find_cea_extension(edid);
4580        if (!cea) {
4581                DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4582                return 0;
4583        }
4584
4585        if (cea_revision(cea) < 3) {
4586                DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4587                return 0;
4588        }
4589
4590        if (cea_db_offsets(cea, &start, &end)) {
4591                DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4592                return -EPROTO;
4593        }
4594
4595        for_each_cea_db(cea, i, start, end) {
4596                const u8 *db = &cea[i];
4597
4598                if (cea_db_tag(db) == AUDIO_BLOCK) {
4599                        int j;
4600
4601                        dbl = cea_db_payload_len(db);
4602
4603                        count = dbl / 3; /* SAD is 3B */
4604                        *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4605                        if (!*sads)
4606                                return -ENOMEM;
4607                        for (j = 0; j < count; j++) {
4608                                const u8 *sad = &db[1 + j * 3];
4609
4610                                (*sads)[j].format = (sad[0] & 0x78) >> 3;
4611                                (*sads)[j].channels = sad[0] & 0x7;
4612                                (*sads)[j].freq = sad[1] & 0x7F;
4613                                (*sads)[j].byte2 = sad[2];
4614                        }
4615                        break;
4616                }
4617        }
4618
4619        return count;
4620}
4621EXPORT_SYMBOL(drm_edid_to_sad);
4622
4623/**
4624 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4625 * @edid: EDID to parse
4626 * @sadb: pointer to the speaker block
4627 *
4628 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
4629 *
4630 * Note: The returned pointer needs to be freed using kfree().
4631 *
4632 * Return: The number of found Speaker Allocation Blocks or negative number on
4633 * error.
4634 */
4635int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4636{
4637        int count = 0;
4638        int i, start, end, dbl;
4639        const u8 *cea;
4640
4641        cea = drm_find_cea_extension(edid);
4642        if (!cea) {
4643                DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4644                return 0;
4645        }
4646
4647        if (cea_revision(cea) < 3) {
4648                DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4649                return 0;
4650        }
4651
4652        if (cea_db_offsets(cea, &start, &end)) {
4653                DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4654                return -EPROTO;
4655        }
4656
4657        for_each_cea_db(cea, i, start, end) {
4658                const u8 *db = &cea[i];
4659
4660                if (cea_db_tag(db) == SPEAKER_BLOCK) {
4661                        dbl = cea_db_payload_len(db);
4662
4663                        /* Speaker Allocation Data Block */
4664                        if (dbl == 3) {
4665                                *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4666                                if (!*sadb)
4667                                        return -ENOMEM;
4668                                count = dbl;
4669                                break;
4670                        }
4671                }
4672        }
4673
4674        return count;
4675}
4676EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4677
4678/**
4679 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
4680 * @connector: connector associated with the HDMI/DP sink
4681 * @mode: the display mode
4682 *
4683 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4684 * the sink doesn't support audio or video.
4685 */
4686int drm_av_sync_delay(struct drm_connector *connector,
4687                      const struct drm_display_mode *mode)
4688{
4689        int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4690        int a, v;
4691
4692        if (!connector->latency_present[0])
4693                return 0;
4694        if (!connector->latency_present[1])
4695                i = 0;
4696
4697        a = connector->audio_latency[i];
4698        v = connector->video_latency[i];
4699
4700        /*
4701         * HDMI/DP sink doesn't support audio or video?
4702         */
4703        if (a == 255 || v == 255)
4704                return 0;
4705
4706        /*
4707         * Convert raw EDID values to millisecond.
4708         * Treat unknown latency as 0ms.
4709         */
4710        if (a)
4711                a = min(2 * (a - 1), 500);
4712        if (v)
4713                v = min(2 * (v - 1), 500);
4714
4715        return max(v - a, 0);
4716}
4717EXPORT_SYMBOL(drm_av_sync_delay);
4718
4719/**
4720 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
4721 * @edid: monitor EDID information
4722 *
4723 * Parse the CEA extension according to CEA-861-B.
4724 *
4725 * Drivers that have added the modes parsed from EDID to drm_display_info
4726 * should use &drm_display_info.is_hdmi instead of calling this function.
4727 *
4728 * Return: True if the monitor is HDMI, false if not or unknown.
4729 */
4730bool drm_detect_hdmi_monitor(struct edid *edid)
4731{
4732        const u8 *edid_ext;
4733        int i;
4734        int start_offset, end_offset;
4735
4736        edid_ext = drm_find_cea_extension(edid);
4737        if (!edid_ext)
4738                return false;
4739
4740        if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4741                return false;
4742
4743        /*
4744         * Because HDMI identifier is in Vendor Specific Block,
4745         * search it from all data blocks of CEA extension.
4746         */
4747        for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4748                if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4749                        return true;
4750        }
4751
4752        return false;
4753}
4754EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4755
4756/**
4757 * drm_detect_monitor_audio - check monitor audio capability
4758 * @edid: EDID block to scan
4759 *
4760 * Monitor should have CEA extension block.
4761 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4762 * audio' only. If there is any audio extension block and supported
4763 * audio format, assume at least 'basic audio' support, even if 'basic
4764 * audio' is not defined in EDID.
4765 *
4766 * Return: True if the monitor supports audio, false otherwise.
4767 */
4768bool drm_detect_monitor_audio(struct edid *edid)
4769{
4770        const u8 *edid_ext;
4771        int i, j;
4772        bool has_audio = false;
4773        int start_offset, end_offset;
4774
4775        edid_ext = drm_find_cea_extension(edid);
4776        if (!edid_ext)
4777                goto end;
4778
4779        has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4780
4781        if (has_audio) {
4782                DRM_DEBUG_KMS("Monitor has basic audio support\n");
4783                goto end;
4784        }
4785
4786        if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4787                goto end;
4788
4789        for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4790                if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
4791                        has_audio = true;
4792                        for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
4793                                DRM_DEBUG_KMS("CEA audio format %d\n",
4794                                              (edid_ext[i + j] >> 3) & 0xf);
4795                        goto end;
4796                }
4797        }
4798end:
4799        return has_audio;
4800}
4801EXPORT_SYMBOL(drm_detect_monitor_audio);
4802
4803
4804/**
4805 * drm_default_rgb_quant_range - default RGB quantization range
4806 * @mode: display mode
4807 *
4808 * Determine the default RGB quantization range for the mode,
4809 * as specified in CEA-861.
4810 *
4811 * Return: The default RGB quantization range for the mode
4812 */
4813enum hdmi_quantization_range
4814drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4815{
4816        /* All CEA modes other than VIC 1 use limited quantization range. */
4817        return drm_match_cea_mode(mode) > 1 ?
4818                HDMI_QUANTIZATION_RANGE_LIMITED :
4819                HDMI_QUANTIZATION_RANGE_FULL;
4820}
4821EXPORT_SYMBOL(drm_default_rgb_quant_range);
4822
4823static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
4824{
4825        struct drm_display_info *info = &connector->display_info;
4826
4827        DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
4828
4829        if (db[2] & EDID_CEA_VCDB_QS)
4830                info->rgb_quant_range_selectable = true;
4831}
4832
4833static
4834void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
4835{
4836        switch (max_frl_rate) {
4837        case 1:
4838                *max_lanes = 3;
4839                *max_rate_per_lane = 3;
4840                break;
4841        case 2:
4842                *max_lanes = 3;
4843                *max_rate_per_lane = 6;
4844                break;
4845        case 3:
4846                *max_lanes = 4;
4847                *max_rate_per_lane = 6;
4848                break;
4849        case 4:
4850                *max_lanes = 4;
4851                *max_rate_per_lane = 8;
4852                break;
4853        case 5:
4854                *max_lanes = 4;
4855                *max_rate_per_lane = 10;
4856                break;
4857        case 6:
4858                *max_lanes = 4;
4859                *max_rate_per_lane = 12;
4860                break;
4861        case 0:
4862        default:
4863                *max_lanes = 0;
4864                *max_rate_per_lane = 0;
4865        }
4866}
4867
4868static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4869                                               const u8 *db)
4870{
4871        u8 dc_mask;
4872        struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4873
4874        dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4875        hdmi->y420_dc_modes = dc_mask;
4876}
4877
4878static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4879                                 const u8 *hf_vsdb)
4880{
4881        struct drm_display_info *display = &connector->display_info;
4882        struct drm_hdmi_info *hdmi = &display->hdmi;
4883
4884        display->has_hdmi_infoframe = true;
4885
4886        if (hf_vsdb[6] & 0x80) {
4887                hdmi->scdc.supported = true;
4888                if (hf_vsdb[6] & 0x40)
4889                        hdmi->scdc.read_request = true;
4890        }
4891
4892        /*
4893         * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4894         * And as per the spec, three factors confirm this:
4895         * * Availability of a HF-VSDB block in EDID (check)
4896         * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4897         * * SCDC support available (let's check)
4898         * Lets check it out.
4899         */
4900
4901        if (hf_vsdb[5]) {
4902                /* max clock is 5000 KHz times block value */
4903                u32 max_tmds_clock = hf_vsdb[5] * 5000;
4904                struct drm_scdc *scdc = &hdmi->scdc;
4905
4906                if (max_tmds_clock > 340000) {
4907                        display->max_tmds_clock = max_tmds_clock;
4908                        DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4909                                display->max_tmds_clock);
4910                }
4911
4912                if (scdc->supported) {
4913                        scdc->scrambling.supported = true;
4914
4915                        /* Few sinks support scrambling for clocks < 340M */
4916                        if ((hf_vsdb[6] & 0x8))
4917                                scdc->scrambling.low_rates = true;
4918                }
4919        }
4920
4921        if (hf_vsdb[7]) {
4922                u8 max_frl_rate;
4923                u8 dsc_max_frl_rate;
4924                u8 dsc_max_slices;
4925                struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
4926
4927                DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n");
4928                max_frl_rate = (hf_vsdb[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
4929                drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
4930                                     &hdmi->max_frl_rate_per_lane);
4931                hdmi_dsc->v_1p2 = hf_vsdb[11] & DRM_EDID_DSC_1P2;
4932
4933                if (hdmi_dsc->v_1p2) {
4934                        hdmi_dsc->native_420 = hf_vsdb[11] & DRM_EDID_DSC_NATIVE_420;
4935                        hdmi_dsc->all_bpp = hf_vsdb[11] & DRM_EDID_DSC_ALL_BPP;
4936
4937                        if (hf_vsdb[11] & DRM_EDID_DSC_16BPC)
4938                                hdmi_dsc->bpc_supported = 16;
4939                        else if (hf_vsdb[11] & DRM_EDID_DSC_12BPC)
4940                                hdmi_dsc->bpc_supported = 12;
4941                        else if (hf_vsdb[11] & DRM_EDID_DSC_10BPC)
4942                                hdmi_dsc->bpc_supported = 10;
4943                        else
4944                                hdmi_dsc->bpc_supported = 0;
4945
4946                        dsc_max_frl_rate = (hf_vsdb[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
4947                        drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
4948                                             &hdmi_dsc->max_frl_rate_per_lane);
4949                        hdmi_dsc->total_chunk_kbytes = hf_vsdb[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
4950
4951                        dsc_max_slices = hf_vsdb[12] & DRM_EDID_DSC_MAX_SLICES;
4952                        switch (dsc_max_slices) {
4953                        case 1:
4954                                hdmi_dsc->max_slices = 1;
4955                                hdmi_dsc->clk_per_slice = 340;
4956                                break;
4957                        case 2:
4958                                hdmi_dsc->max_slices = 2;
4959                                hdmi_dsc->clk_per_slice = 340;
4960                                break;
4961                        case 3:
4962                                hdmi_dsc->max_slices = 4;
4963                                hdmi_dsc->clk_per_slice = 340;
4964                                break;
4965                        case 4:
4966                                hdmi_dsc->max_slices = 8;
4967                                hdmi_dsc->clk_per_slice = 340;
4968                                break;
4969                        case 5:
4970                                hdmi_dsc->max_slices = 8;
4971                                hdmi_dsc->clk_per_slice = 400;
4972                                break;
4973                        case 6:
4974                                hdmi_dsc->max_slices = 12;
4975                                hdmi_dsc->clk_per_slice = 400;
4976                                break;
4977                        case 7:
4978                                hdmi_dsc->max_slices = 16;
4979                                hdmi_dsc->clk_per_slice = 400;
4980                                break;
4981                        case 0:
4982                        default:
4983                                hdmi_dsc->max_slices = 0;
4984                                hdmi_dsc->clk_per_slice = 0;
4985                        }
4986                }
4987        }
4988
4989        drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
4990}
4991
4992static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4993                                           const u8 *hdmi)
4994{
4995        struct drm_display_info *info = &connector->display_info;
4996        unsigned int dc_bpc = 0;
4997
4998        /* HDMI supports at least 8 bpc */
4999        info->bpc = 8;
5000

5001        if (cea_db_payload_len(hdmi) < 6)
5002                return;
5003
5004        if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
5005                dc_bpc = 10;
5006                info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
5007                DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
5008                          connector->name);
5009        }
5010
5011        if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
5012                dc_bpc = 12;
5013                info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
5014                DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
5015                          connector->name);
5016        }
5017
5018        if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
5019                dc_bpc = 16;
5020                info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
5021                DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
5022                          connector->name);
5023        }
5024
5025        if (dc_bpc == 0) {
5026                DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
5027                          connector->name);
5028                return;
5029        }
5030
5031        DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
5032                  connector->name, dc_bpc);
5033        info->bpc = dc_bpc;
5034
5035        /*
5036         * Deep color support mandates RGB444 support for all video
5037         * modes and forbids YCRCB422 support for all video modes per
5038         * HDMI 1.3 spec.
5039         */
5040        info->color_formats = DRM_COLOR_FORMAT_RGB444;
5041
5042        /* YCRCB444 is optional according to spec. */
5043        if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
5044                info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
5045                DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
5046                          connector->name);
5047        }
5048
5049        /*
5050         * Spec says that if any deep color mode is supported at all,
5051         * then deep color 36 bit must be supported.
5052         */
5053        if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
5054                DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
5055                          connector->name);
5056        }
5057}
5058
5059static void
5060drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
5061{
5062        struct drm_display_info *info = &connector->display_info;
5063        u8 len = cea_db_payload_len(db);
5064
5065        info->is_hdmi = true;
5066
5067        if (len >= 6)
5068                info->dvi_dual = db[6] & 1;
5069        if (len >= 7)
5070                info->max_tmds_clock = db[7] * 5000;
5071
5072        DRM_DEBUG_KMS("HDMI: DVI dual %d, "
5073                      "max TMDS clock %d kHz\n",
5074                      info->dvi_dual,
5075                      info->max_tmds_clock);
5076
5077        drm_parse_hdmi_deep_color_info(connector, db);
5078}
5079
5080static void drm_parse_cea_ext(struct drm_connector *connector,
5081                              const struct edid *edid)
5082{
5083        struct drm_display_info *info = &connector->display_info;
5084        const u8 *edid_ext;
5085        int i, start, end;
5086
5087        edid_ext = drm_find_cea_extension(edid);
5088        if (!edid_ext)
5089                return;
5090
5091        info->cea_rev = edid_ext[1];
5092
5093        /* The existence of a CEA block should imply RGB support */
5094        info->color_formats = DRM_COLOR_FORMAT_RGB444;
5095        if (edid_ext[3] & EDID_CEA_YCRCB444)
5096                info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
5097        if (edid_ext[3] & EDID_CEA_YCRCB422)
5098                info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
5099
5100        if (cea_db_offsets(edid_ext, &start, &end))
5101                return;
5102
5103        for_each_cea_db(edid_ext, i, start, end) {
5104                const u8 *db = &edid_ext[i];
5105
5106                if (cea_db_is_hdmi_vsdb(db))
5107                        drm_parse_hdmi_vsdb_video(connector, db);
5108                if (cea_db_is_hdmi_forum_vsdb(db))
5109                        drm_parse_hdmi_forum_vsdb(connector, db);
5110                if (cea_db_is_y420cmdb(db))
5111                        drm_parse_y420cmdb_bitmap(connector, db);
5112                if (cea_db_is_vcdb(db))
5113                        drm_parse_vcdb(connector, db);
5114                if (cea_db_is_hdmi_hdr_metadata_block(db))
5115                        drm_parse_hdr_metadata_block(connector, db);
5116        }
5117}
5118
5119static
5120void get_monitor_range(struct detailed_timing *timing,
5121                       void *info_monitor_range)
5122{
5123        struct drm_monitor_range_info *monitor_range = info_monitor_range;
5124        const struct detailed_non_pixel *data = &timing->data.other_data;
5125        const struct detailed_data_monitor_range *range = &data->data.range;
5126
5127        if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
5128                return;
5129
5130        /*
5131         * Check for flag range limits only. If flag == 1 then
5132         * no additional timing information provided.
5133         * Default GTF, GTF Secondary curve and CVT are not
5134         * supported
5135         */
5136        if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
5137                return;
5138
5139        monitor_range->min_vfreq = range->min_vfreq;
5140        monitor_range->max_vfreq = range->max_vfreq;
5141}
5142
5143static
5144void drm_get_monitor_range(struct drm_connector *connector,
5145                           const struct edid *edid)
5146{
5147        struct drm_display_info *info = &connector->display_info;
5148
5149        if (!version_greater(edid, 1, 1))
5150                return;
5151
5152        drm_for_each_detailed_block((u8 *)edid, get_monitor_range,
5153                                    &info->monitor_range);
5154
5155        DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
5156                      info->monitor_range.min_vfreq,
5157                      info->monitor_range.max_vfreq);
5158}
5159
5160/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
5161 * all of the values which would have been set from EDID
5162 */
5163void
5164drm_reset_display_info(struct drm_connector *connector)
5165{
5166        struct drm_display_info *info = &connector->display_info;
5167
5168        info->width_mm = 0;
5169        info->height_mm = 0;
5170
5171        info->bpc = 0;
5172        info->color_formats = 0;
5173        info->cea_rev = 0;
5174        info->max_tmds_clock = 0;
5175        info->dvi_dual = false;
5176        info->is_hdmi = false;
5177        info->has_hdmi_infoframe = false;
5178        info->rgb_quant_range_selectable = false;
5179        memset(&info->hdmi, 0, sizeof(info->hdmi));
5180
5181        info->non_desktop = 0;
5182        memset(&info->monitor_range, 0, sizeof(info->monitor_range));
5183}
5184
5185u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
5186{
5187        struct drm_display_info *info = &connector->display_info;
5188
5189        u32 quirks = edid_get_quirks(edid);
5190
5191        drm_reset_display_info(connector);
5192
5193        info->width_mm = edid->width_cm * 10;
5194        info->height_mm = edid->height_cm * 10;
5195
5196        info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
5197
5198        drm_get_monitor_range(connector, edid);
5199
5200        DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
5201
5202        if (edid->revision < 3)
5203                return quirks;
5204
5205        if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
5206                return quirks;
5207
5208        drm_parse_cea_ext(connector, edid);
5209
5210        /*
5211         * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
5212         *
5213         * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
5214         * tells us to assume 8 bpc color depth if the EDID doesn't have
5215         * extensions which tell otherwise.
5216         */
5217        if (info->bpc == 0 && edid->revision == 3 &&
5218            edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
5219                info->bpc = 8;
5220                DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
5221                          connector->name, info->bpc);
5222        }
5223
5224        /* Only defined for 1.4 with digital displays */
5225        if (edid->revision < 4)
5226                return quirks;
5227
5228        switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
5229        case DRM_EDID_DIGITAL_DEPTH_6:
5230                info->bpc = 6;
5231                break;
5232        case DRM_EDID_DIGITAL_DEPTH_8:
5233                info->bpc = 8;
5234                break;
5235        case DRM_EDID_DIGITAL_DEPTH_10:
5236                info->bpc = 10;
5237                break;
5238        case DRM_EDID_DIGITAL_DEPTH_12:
5239                info->bpc = 12;
5240                break;
5241        case DRM_EDID_DIGITAL_DEPTH_14:
5242                info->bpc = 14;
5243                break;
5244        case DRM_EDID_DIGITAL_DEPTH_16:
5245                info->bpc = 16;
5246                break;
5247        case DRM_EDID_DIGITAL_DEPTH_UNDEF:
5248        default:
5249                info->bpc = 0;
5250                break;
5251        }
5252
5253        DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
5254                          connector->name, info->bpc);
5255
5256        info->color_formats |= DRM_COLOR_FORMAT_RGB444;
5257        if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
5258                info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
5259        if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
5260                info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
5261        return quirks;
5262}
5263
5264static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
5265                                                            struct displayid_detailed_timings_1 *timings)
5266{
5267        struct drm_display_mode *mode;
5268        unsigned pixel_clock = (timings->pixel_clock[0] |
5269                                (timings->pixel_clock[1] << 8) |
5270                                (timings->pixel_clock[2] << 16)) + 1;
5271        unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
5272        unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
5273        unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
5274        unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
5275        unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
5276        unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
5277        unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
5278        unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
5279        bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
5280        bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
5281
5282        mode = drm_mode_create(dev);
5283        if (!mode)
5284                return NULL;
5285
5286        mode->clock = pixel_clock * 10;
5287        mode->hdisplay = hactive;
5288        mode->hsync_start = mode->hdisplay + hsync;
5289        mode->hsync_end = mode->hsync_start + hsync_width;
5290        mode->htotal = mode->hdisplay + hblank;
5291
5292        mode->vdisplay = vactive;
5293        mode->vsync_start = mode->vdisplay + vsync;
5294        mode->vsync_end = mode->vsync_start + vsync_width;
5295        mode->vtotal = mode->vdisplay + vblank;
5296
5297        mode->flags = 0;
5298        mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
5299        mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
5300        mode->type = DRM_MODE_TYPE_DRIVER;
5301
5302        if (timings->flags & 0x80)
5303                mode->type |= DRM_MODE_TYPE_PREFERRED;
5304        drm_mode_set_name(mode);
5305
5306        return mode;
5307}
5308
5309static int add_displayid_detailed_1_modes(struct drm_connector *connector,
5310                                          const struct displayid_block *block)
5311{
5312        struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
5313        int i;
5314        int num_timings;
5315        struct drm_display_mode *newmode;
5316        int num_modes = 0;
5317        /* blocks must be multiple of 20 bytes length */
5318        if (block->num_bytes % 20)
5319                return 0;
5320
5321        num_timings = block->num_bytes / 20;
5322        for (i = 0; i < num_timings; i++) {
5323                struct displayid_detailed_timings_1 *timings = &det->timings[i];
5324
5325                newmode = drm_mode_displayid_detailed(connector->dev, timings);
5326                if (!newmode)
5327                        continue;
5328
5329                drm_mode_probed_add(connector, newmode);
5330                num_modes++;
5331        }
5332        return num_modes;
5333}
5334
5335static int add_displayid_detailed_modes(struct drm_connector *connector,
5336                                        struct edid *edid)
5337{
5338        const struct displayid_block *block;
5339        struct displayid_iter iter;
5340        int num_modes = 0;
5341
5342        displayid_iter_edid_begin(edid, &iter);
5343        displayid_iter_for_each(block, &iter) {
5344                if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING)
5345                        num_modes += add_displayid_detailed_1_modes(connector, block);
5346        }
5347        displayid_iter_end(&iter);
5348
5349        return num_modes;
5350}
5351
5352/**
5353 * drm_add_edid_modes - add modes from EDID data, if available
5354 * @connector: connector we're probing
5355 * @edid: EDID data
5356 *
5357 * Add the specified modes to the connector's mode list. Also fills out the
5358 * &drm_display_info structure and ELD in @connector with any information which
5359 * can be derived from the edid.
5360 *
5361 * Return: The number of modes added or 0 if we couldn't find any.
5362 */
5363int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
5364{
5365        int num_modes = 0;
5366        u32 quirks;
5367
5368        if (edid == NULL) {
5369                clear_eld(connector);
5370                return 0;
5371        }
5372        if (!drm_edid_is_valid(edid)) {
5373                clear_eld(connector);
5374                drm_warn(connector->dev, "%s: EDID invalid.\n",
5375                         connector->name);
5376                return 0;
5377        }
5378
5379        drm_edid_to_eld(connector, edid);
5380
5381        /*
5382         * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
5383         * To avoid multiple parsing of same block, lets parse that map
5384         * from sink info, before parsing CEA modes.
5385         */
5386        quirks = drm_add_display_info(connector, edid);
5387
5388        /*
5389         * EDID spec says modes should be preferred in this order:
5390         * - preferred detailed mode
5391         * - other detailed modes from base block
5392         * - detailed modes from extension blocks
5393         * - CVT 3-byte code modes
5394         * - standard timing codes
5395         * - established timing codes
5396         * - modes inferred from GTF or CVT range information
5397         *
5398         * We get this pretty much right.
5399         *
5400         * XXX order for additional mode types in extension blocks?
5401         */
5402        num_modes += add_detailed_modes(connector, edid, quirks);
5403        num_modes += add_cvt_modes(connector, edid);
5404        num_modes += add_standard_modes(connector, edid);
5405        num_modes += add_established_modes(connector, edid);
5406        num_modes += add_cea_modes(connector, edid);
5407        num_modes += add_alternate_cea_modes(connector, edid);
5408        num_modes += add_displayid_detailed_modes(connector, edid);
5409        if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
5410                num_modes += add_inferred_modes(connector, edid);
5411
5412        if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
5413                edid_fixup_preferred(connector, quirks);
5414
5415        if (quirks & EDID_QUIRK_FORCE_6BPC)
5416                connector->display_info.bpc = 6;
5417
5418        if (quirks & EDID_QUIRK_FORCE_8BPC)
5419                connector->display_info.bpc = 8;
5420
5421        if (quirks & EDID_QUIRK_FORCE_10BPC)
5422                connector->display_info.bpc = 10;
5423
5424        if (quirks & EDID_QUIRK_FORCE_12BPC)
5425                connector->display_info.bpc = 12;
5426
5427        return num_modes;
5428}
5429EXPORT_SYMBOL(drm_add_edid_modes);
5430
5431/**
5432 * drm_add_modes_noedid - add modes for the connectors without EDID
5433 * @connector: connector we're probing
5434 * @hdisplay: the horizontal display limit
5435 * @vdisplay: the vertical display limit
5436 *
5437 * Add the specified modes to the connector's mode list. Only when the
5438 * hdisplay/vdisplay is not beyond the given limit, it will be added.
5439 *
5440 * Return: The number of modes added or 0 if we couldn't find any.
5441 */
5442int drm_add_modes_noedid(struct drm_connector *connector,
5443                        int hdisplay, int vdisplay)
5444{
5445        int i, count, num_modes = 0;
5446        struct drm_display_mode *mode;
5447        struct drm_device *dev = connector->dev;
5448
5449        count = ARRAY_SIZE(drm_dmt_modes);
5450        if (hdisplay < 0)
5451                hdisplay = 0;
5452        if (vdisplay < 0)
5453                vdisplay = 0;
5454
5455        for (i = 0; i < count; i++) {
5456                const struct drm_display_mode *ptr = &drm_dmt_modes[i];
5457
5458                if (hdisplay && vdisplay) {
5459                        /*
5460                         * Only when two are valid, they will be used to check
5461                         * whether the mode should be added to the mode list of
5462                         * the connector.
5463                         */
5464                        if (ptr->hdisplay > hdisplay ||
5465                                        ptr->vdisplay > vdisplay)
5466                                continue;
5467                }
5468                if (drm_mode_vrefresh(ptr) > 61)
5469                        continue;
5470                mode = drm_mode_duplicate(dev, ptr);
5471                if (mode) {
5472                        drm_mode_probed_add(connector, mode);
5473                        num_modes++;
5474                }
5475        }
5476        return num_modes;
5477}
5478EXPORT_SYMBOL(drm_add_modes_noedid);
5479
5480/**
5481 * drm_set_preferred_mode - Sets the preferred mode of a connector
5482 * @connector: connector whose mode list should be processed
5483 * @hpref: horizontal resolution of preferred mode
5484 * @vpref: vertical resolution of preferred mode
5485 *
5486 * Marks a mode as preferred if it matches the resolution specified by @hpref
5487 * and @vpref.
5488 */
5489void drm_set_preferred_mode(struct drm_connector *connector,
5490                           int hpref, int vpref)
5491{
5492        struct drm_display_mode *mode;
5493
5494        list_for_each_entry(mode, &connector->probed_modes, head) {
5495                if (mode->hdisplay == hpref &&
5496                    mode->vdisplay == vpref)
5497                        mode->type |= DRM_MODE_TYPE_PREFERRED;
5498        }
5499}
5500EXPORT_SYMBOL(drm_set_preferred_mode);
5501
5502static bool is_hdmi2_sink(const struct drm_connector *connector)
5503{
5504        /*
5505         * FIXME: sil-sii8620 doesn't have a connector around when
5506         * we need one, so we have to be prepared for a NULL connector.
5507         */
5508        if (!connector)
5509                return true;
5510
5511        return connector->display_info.hdmi.scdc.supported ||
5512                connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420;
5513}
5514
5515static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf)
5516{
5517        return sink_eotf & BIT(output_eotf);
5518}
5519
5520/**
5521 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with
5522 *                                         HDR metadata from userspace
5523 * @frame: HDMI DRM infoframe
5524 * @conn_state: Connector state containing HDR metadata
5525 *
5526 * Return: 0 on success or a negative error code on failure.
5527 */
5528int
5529drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
5530                                    const struct drm_connector_state *conn_state)
5531{
5532        struct drm_connector *connector;
5533        struct hdr_output_metadata *hdr_metadata;
5534        int err;
5535
5536        if (!frame || !conn_state)
5537                return -EINVAL;
5538
5539        connector = conn_state->connector;
5540
5541        if (!conn_state->hdr_output_metadata)
5542                return -EINVAL;
5543
5544        hdr_metadata = conn_state->hdr_output_metadata->data;
5545
5546        if (!hdr_metadata || !connector)
5547                return -EINVAL;
5548
5549        /* Sink EOTF is Bit map while infoframe is absolute values */
5550        if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf,
5551            connector->hdr_sink_metadata.hdmi_type1.eotf)) {
5552                DRM_DEBUG_KMS("EOTF Not Supported\n");
5553                return -EINVAL;
5554        }
5555
5556        err = hdmi_drm_infoframe_init(frame);
5557        if (err < 0)
5558                return err;
5559
5560        frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
5561        frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
5562
5563        BUILD_BUG_ON(sizeof(frame->display_primaries) !=
5564                     sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries));
5565        BUILD_BUG_ON(sizeof(frame->white_point) !=
5566                     sizeof(hdr_metadata->hdmi_metadata_type1.white_point));
5567
5568        memcpy(&frame->display_primaries,
5569               &hdr_metadata->hdmi_metadata_type1.display_primaries,
5570               sizeof(frame->display_primaries));
5571
5572        memcpy(&frame->white_point,
5573               &hdr_metadata->hdmi_metadata_type1.white_point,
5574               sizeof(frame->white_point));
5575
5576        frame->max_display_mastering_luminance =
5577                hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance;
5578        frame->min_display_mastering_luminance =
5579                hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance;
5580        frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall;
5581        frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll;
5582
5583        return 0;
5584}
5585EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
5586
5587static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
5588                            const struct drm_display_mode *mode)
5589{
5590        bool has_hdmi_infoframe = connector ?
5591                connector->display_info.has_hdmi_infoframe : false;
5592
5593        if (!has_hdmi_infoframe)
5594                return 0;
5595
5596        /* No HDMI VIC when signalling 3D video format */
5597        if (mode->flags & DRM_MODE_FLAG_3D_MASK)
5598                return 0;
5599
5600        return drm_match_hdmi_mode(mode);
5601}
5602
5603static u8 drm_mode_cea_vic(const struct drm_connector *connector,
5604                           const struct drm_display_mode *mode)
5605{
5606        u8 vic;
5607
5608        /*
5609         * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
5610         * we should send its VIC in vendor infoframes, else send the
5611         * VIC in AVI infoframes. Lets check if this mode is present in
5612         * HDMI 1.4b 4K modes
5613         */
5614        if (drm_mode_hdmi_vic(connector, mode))
5615                return 0;
5616
5617        vic = drm_match_cea_mode(mode);
5618
5619        /*
5620         * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
5621         * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
5622         * have to make sure we dont break HDMI 1.4 sinks.
5623         */
5624        if (!is_hdmi2_sink(connector) && vic > 64)
5625                return 0;
5626
5627        return vic;
5628}
5629
5630/**
5631 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
5632 *                                              data from a DRM display mode
5633 * @frame: HDMI AVI infoframe
5634 * @connector: the connector
5635 * @mode: DRM display mode
5636 *
5637 * Return: 0 on success or a negative error code on failure.
5638 */
5639int
5640drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
5641                                         const struct drm_connector *connector,
5642                                         const struct drm_display_mode *mode)
5643{
5644        enum hdmi_picture_aspect picture_aspect;
5645        u8 vic, hdmi_vic;
5646
5647        if (!frame || !mode)
5648                return -EINVAL;
5649
5650        hdmi_avi_infoframe_init(frame);
5651
5652        if (mode->flags & DRM_MODE_FLAG_DBLCLK)
5653                frame->pixel_repeat = 1;
5654
5655        vic = drm_mode_cea_vic(connector, mode);
5656        hdmi_vic = drm_mode_hdmi_vic(connector, mode);
5657
5658        frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5659
5660        /*
5661         * As some drivers don't support atomic, we can't use connector state.
5662         * So just initialize the frame with default values, just the same way
5663         * as it's done with other properties here.
5664         */
5665        frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
5666        frame->itc = 0;
5667
5668        /*
5669         * Populate picture aspect ratio from either
5670         * user input (if specified) or from the CEA/HDMI mode lists.
5671         */
5672        picture_aspect = mode->picture_aspect_ratio;
5673        if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
5674                if (vic)
5675                        picture_aspect = drm_get_cea_aspect_ratio(vic);
5676                else if (hdmi_vic)
5677                        picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
5678        }
5679
5680        /*
5681         * The infoframe can't convey anything but none, 4:3
5682         * and 16:9, so if the user has asked for anything else
5683         * we can only satisfy it by specifying the right VIC.
5684         */
5685        if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
5686                if (vic) {
5687                        if (picture_aspect != drm_get_cea_aspect_ratio(vic))
5688                                return -EINVAL;
5689                } else if (hdmi_vic) {
5690                        if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
5691                                return -EINVAL;
5692                } else {
5693                        return -EINVAL;
5694                }
5695
5696                picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5697        }
5698
5699        frame->video_code = vic;
5700        frame->picture_aspect = picture_aspect;
5701        frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
5702        frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
5703
5704        return 0;
5705}
5706EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
5707
5708/* HDMI Colorspace Spec Definitions */
5709#define FULL_COLORIMETRY_MASK           0x1FF
5710#define NORMAL_COLORIMETRY_MASK         0x3
5711#define EXTENDED_COLORIMETRY_MASK       0x7
5712#define EXTENDED_ACE_COLORIMETRY_MASK   0xF
5713
5714#define C(x) ((x) << 0)
5715#define EC(x) ((x) << 2)
5716#define ACE(x) ((x) << 5)
5717
5718#define HDMI_COLORIMETRY_NO_DATA                0x0
5719#define HDMI_COLORIMETRY_SMPTE_170M_YCC         (C(1) | EC(0) | ACE(0))
5720#define HDMI_COLORIMETRY_BT709_YCC              (C(2) | EC(0) | ACE(0))
5721#define HDMI_COLORIMETRY_XVYCC_601              (C(3) | EC(0) | ACE(0))
5722#define HDMI_COLORIMETRY_XVYCC_709              (C(3) | EC(1) | ACE(0))
5723#define HDMI_COLORIMETRY_SYCC_601               (C(3) | EC(2) | ACE(0))
5724#define HDMI_COLORIMETRY_OPYCC_601              (C(3) | EC(3) | ACE(0))
5725#define HDMI_COLORIMETRY_OPRGB                  (C(3) | EC(4) | ACE(0))
5726#define HDMI_COLORIMETRY_BT2020_CYCC            (C(3) | EC(5) | ACE(0))
5727#define HDMI_COLORIMETRY_BT2020_RGB             (C(3) | EC(6) | ACE(0))
5728#define HDMI_COLORIMETRY_BT2020_YCC             (C(3) | EC(6) | ACE(0))
5729#define HDMI_COLORIMETRY_DCI_P3_RGB_D65         (C(3) | EC(7) | ACE(0))
5730#define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER     (C(3) | EC(7) | ACE(1))
5731
5732static const u32 hdmi_colorimetry_val[] = {
5733        [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA,
5734        [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC,
5735        [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC,
5736        [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601,
5737        [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709,
5738        [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601,
5739        [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
5740        [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
5741        [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
5742        [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
5743        [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC,
5744};
5745
5746#undef C
5747#undef EC
5748#undef ACE
5749
5750/**
5751 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe
5752 *                                       colorspace information
5753 * @frame: HDMI AVI infoframe
5754 * @conn_state: connector state
5755 */
5756void
5757drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
5758                                  const struct drm_connector_state *conn_state)
5759{
5760        u32 colorimetry_val;
5761        u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK;
5762
5763        if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val))
5764                colorimetry_val = HDMI_COLORIMETRY_NO_DATA;
5765        else
5766                colorimetry_val = hdmi_colorimetry_val[colorimetry_index];
5767
5768        frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK;
5769        /*
5770         * ToDo: Extend it for ACE formats as well. Modify the infoframe
5771         * structure and extend it in drivers/video/hdmi
5772         */
5773        frame->extended_colorimetry = (colorimetry_val >> 2) &
5774                                        EXTENDED_COLORIMETRY_MASK;
5775}
5776EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace);
5777
5778/**
5779 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
5780 *                                        quantization range information
5781 * @frame: HDMI AVI infoframe
5782 * @connector: the connector
5783 * @mode: DRM display mode
5784 * @rgb_quant_range: RGB quantization range (Q)
5785 */
5786void
5787drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
5788                                   const struct drm_connector *connector,
5789                                   const struct drm_display_mode *mode,
5790                                   enum hdmi_quantization_range rgb_quant_range)
5791{
5792        const struct drm_display_info *info = &connector->display_info;
5793
5794        /*
5795         * CEA-861:
5796         * "A Source shall not send a non-zero Q value that does not correspond
5797         *  to the default RGB Quantization Range for the transmitted Picture
5798         *  unless the Sink indicates support for the Q bit in a Video
5799         *  Capabilities Data Block."
5800         *
5801         * HDMI 2.0 recommends sending non-zero Q when it does match the
5802         * default RGB quantization range for the mode, even when QS=0.
5803         */
5804        if (info->rgb_quant_range_selectable ||
5805            rgb_quant_range == drm_default_rgb_quant_range(mode))
5806                frame->quantization_range = rgb_quant_range;
5807        else
5808                frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
5809
5810        /*
5811         * CEA-861-F:
5812         * "When transmitting any RGB colorimetry, the Source should set the
5813         *  YQ-field to match the RGB Quantization Range being transmitted
5814         *  (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
5815         *  set YQ=1) and the Sink shall ignore the YQ-field."
5816         *
5817         * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
5818         * by non-zero YQ when receiving RGB. There doesn't seem to be any
5819         * good way to tell which version of CEA-861 the sink supports, so
5820         * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
5821         * on on CEA-861-F.
5822         */
5823        if (!is_hdmi2_sink(connector) ||
5824            rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
5825                frame->ycc_quantization_range =
5826                        HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
5827        else
5828                frame->ycc_quantization_range =
5829                        HDMI_YCC_QUANTIZATION_RANGE_FULL;
5830}
5831EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
5832
5833/**
5834 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe
5835 *                                 bar information
5836 * @frame: HDMI AVI infoframe
5837 * @conn_state: connector state
5838 */
5839void
5840drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame,
5841                            const struct drm_connector_state *conn_state)
5842{
5843        frame->right_bar = conn_state->tv.margins.right;
5844        frame->left_bar = conn_state->tv.margins.left;
5845        frame->top_bar = conn_state->tv.margins.top;
5846        frame->bottom_bar = conn_state->tv.margins.bottom;
5847}
5848EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars);
5849
5850static enum hdmi_3d_structure
5851s3d_structure_from_display_mode(const struct drm_display_mode *mode)
5852{
5853        u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
5854
5855        switch (layout) {
5856        case DRM_MODE_FLAG_3D_FRAME_PACKING:
5857                return HDMI_3D_STRUCTURE_FRAME_PACKING;
5858        case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
5859                return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
5860        case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
5861                return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
5862        case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
5863                return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
5864        case DRM_MODE_FLAG_3D_L_DEPTH:
5865                return HDMI_3D_STRUCTURE_L_DEPTH;
5866        case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
5867                return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
5868        case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
5869                return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
5870        case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
5871                return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
5872        default:
5873                return HDMI_3D_STRUCTURE_INVALID;
5874        }
5875}
5876
5877/**
5878 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
5879 * data from a DRM display mode
5880 * @frame: HDMI vendor infoframe
5881 * @connector: the connector
5882 * @mode: DRM display mode
5883 *
5884 * Note that there's is a need to send HDMI vendor infoframes only when using a
5885 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
5886 * function will return -EINVAL, error that can be safely ignored.
5887 *
5888 * Return: 0 on success or a negative error code on failure.
5889 */
5890int
5891drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
5892                                            const struct drm_connector *connector,
5893                                            const struct drm_display_mode *mode)
5894{
5895        /*
5896         * FIXME: sil-sii8620 doesn't have a connector around when
5897         * we need one, so we have to be prepared for a NULL connector.
5898         */
5899        bool has_hdmi_infoframe = connector ?
5900                connector->display_info.has_hdmi_infoframe : false;
5901        int err;
5902
5903        if (!frame || !mode)
5904                return -EINVAL;
5905
5906        if (!has_hdmi_infoframe)
5907                return -EINVAL;
5908
5909        err = hdmi_vendor_infoframe_init(frame);
5910        if (err < 0)
5911                return err;
5912
5913        /*
5914         * Even if it's not absolutely necessary to send the infoframe
5915         * (ie.vic==0 and s3d_struct==0) we will still send it if we
5916         * know that the sink can handle it. This is based on a
5917         * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
5918         * have trouble realizing that they should switch from 3D to 2D
5919         * mode if the source simply stops sending the infoframe when
5920         * it wants to switch from 3D to 2D.
5921         */
5922        frame->vic = drm_mode_hdmi_vic(connector, mode);
5923        frame->s3d_struct = s3d_structure_from_display_mode(mode);
5924
5925        return 0;
5926}
5927EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
5928
5929static void drm_parse_tiled_block(struct drm_connector *connector,
5930                                  const struct displayid_block *block)
5931{
5932        const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5933        u16 w, h;
5934        u8 tile_v_loc, tile_h_loc;
5935        u8 num_v_tile, num_h_tile;
5936        struct drm_tile_group *tg;
5937
5938        w = tile->tile_size[0] | tile->tile_size[1] << 8;
5939        h = tile->tile_size[2] | tile->tile_size[3] << 8;
5940
5941        num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
5942        num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
5943        tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
5944        tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
5945
5946        connector->has_tile = true;
5947        if (tile->tile_cap & 0x80)
5948                connector->tile_is_single_monitor = true;
5949
5950        connector->num_h_tile = num_h_tile + 1;
5951        connector->num_v_tile = num_v_tile + 1;
5952        connector->tile_h_loc = tile_h_loc;
5953        connector->tile_v_loc = tile_v_loc;
5954        connector->tile_h_size = w + 1;
5955        connector->tile_v_size = h + 1;
5956
5957        DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
5958        DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
5959        DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5960                      num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
5961        DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5962
5963        tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
5964        if (!tg)
5965                tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5966        if (!tg)
5967                return;
5968
5969        if (connector->tile_group != tg) {
5970                /* if we haven't got a pointer,
5971                   take the reference, drop ref to old tile group */
5972                if (connector->tile_group)
5973                        drm_mode_put_tile_group(connector->dev, connector->tile_group);
5974                connector->tile_group = tg;
5975        } else {
5976                /* if same tile group, then release the ref we just took. */
5977                drm_mode_put_tile_group(connector->dev, tg);
5978        }
5979}
5980
5981void drm_update_tile_info(struct drm_connector *connector,
5982                          const struct edid *edid)
5983{
5984        const struct displayid_block *block;
5985        struct displayid_iter iter;
5986
5987        connector->has_tile = false;
5988
5989        displayid_iter_edid_begin(edid, &iter);
5990        displayid_iter_for_each(block, &iter) {
5991                if (block->tag == DATA_BLOCK_TILED_DISPLAY)
5992                        drm_parse_tiled_block(connector, block);
5993        }
5994        displayid_iter_end(&iter);
5995
5996        if (!connector->has_tile && connector->tile_group) {
5997                drm_mode_put_tile_group(connector->dev, connector->tile_group);
5998                connector->tile_group = NULL;
5999        }
6000}