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8#ifndef _PSB_DRV_H_
9#define _PSB_DRV_H_
10
11#include <linux/kref.h>
12#include <linux/mm_types.h>
13
14#include <drm/drm_device.h>
15
16#include "gma_display.h"
17#include "gtt.h"
18#include "intel_bios.h"
19#include "mmu.h"
20#include "oaktrail.h"
21#include "opregion.h"
22#include "power.h"
23#include "psb_intel_drv.h"
24#include "psb_reg.h"
25
26#define DRIVER_AUTHOR "Alan Cox <alan@linux.intel.com> and others"
27
28#define DRIVER_NAME "gma500"
29#define DRIVER_DESC "DRM driver for the Intel GMA500, GMA600, GMA3600, GMA3650"
30#define DRIVER_DATE "20140314"
31
32#define DRIVER_MAJOR 1
33#define DRIVER_MINOR 0
34#define DRIVER_PATCHLEVEL 0
35
36
37#define DRM_MODE_SCALE_NO_SCALE 2
38
39enum {
40 CHIP_PSB_8108 = 0,
41 CHIP_PSB_8109 = 1,
42 CHIP_MRST_4100 = 2,
43};
44
45#define IS_PSB(drm) ((to_pci_dev((drm)->dev)->device & 0xfffe) == 0x8108)
46#define IS_MRST(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x4100)
47#define IS_CDV(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x0be0)
48
49
50#define PSB_VDC_OFFSET 0x00000000
51#define PSB_VDC_SIZE 0x000080000
52#define MRST_MMIO_SIZE 0x0000C0000
53#define PSB_SGX_SIZE 0x8000
54#define PSB_SGX_OFFSET 0x00040000
55#define MRST_SGX_OFFSET 0x00080000
56
57
58#define PSB_MMIO_RESOURCE 0
59#define PSB_AUX_RESOURCE 0
60#define PSB_GATT_RESOURCE 2
61#define PSB_GTT_RESOURCE 3
62
63
64#define PSB_GMCH_CTRL 0x52
65#define PSB_BSM 0x5C
66#define _PSB_GMCH_ENABLED 0x4
67#define PSB_PGETBL_CTL 0x2020
68#define _PSB_PGETBL_ENABLED 0x00000001
69#define PSB_SGX_2D_SLAVE_PORT 0x4000
70#define PSB_LPC_GBA 0x44
71
72
73#define PSB_TT_PRIV0_LIMIT (256*1024*1024)
74#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
75
76
77
78
79#define PSB_MMU_CACHED_MEMORY 0x0001
80#define PSB_MMU_RO_MEMORY 0x0002
81#define PSB_MMU_WO_MEMORY 0x0004
82
83
84#define PSB_PDE_MASK 0x003FFFFF
85#define PSB_PDE_SHIFT 22
86#define PSB_PTE_SHIFT 12
87
88
89#define PSB_PTE_VALID 0x0001
90#define PSB_PTE_WO 0x0002
91#define PSB_PTE_RO 0x0004
92#define PSB_PTE_CACHED 0x0008
93
94
95#define PSB_MSVDX_CLOCKGATING 0x2064
96#define PSB_TOPAZ_CLOCKGATING 0x2068
97#define PSB_HWSTAM 0x2098
98#define PSB_INSTPM 0x20C0
99#define PSB_INT_IDENTITY_R 0x20A4
100#define _PSB_IRQ_ASLE (1<<0)
101#define _MDFLD_PIPEC_EVENT_FLAG (1<<2)
102#define _MDFLD_PIPEC_VBLANK_FLAG (1<<3)
103#define _PSB_DPST_PIPEB_FLAG (1<<4)
104#define _MDFLD_PIPEB_EVENT_FLAG (1<<4)
105#define _PSB_VSYNC_PIPEB_FLAG (1<<5)
106#define _PSB_DPST_PIPEA_FLAG (1<<6)
107#define _PSB_PIPEA_EVENT_FLAG (1<<6)
108#define _PSB_VSYNC_PIPEA_FLAG (1<<7)
109#define _PSB_IRQ_DISP_HOTSYNC (1<<17)
110#define _PSB_IRQ_SGX_FLAG (1<<18)
111#define _PSB_IRQ_MSVDX_FLAG (1<<19)
112#define _LNC_IRQ_TOPAZ_FLAG (1<<20)
113
114#define _PSB_PIPE_EVENT_FLAG (_PSB_VSYNC_PIPEA_FLAG | \
115 _PSB_VSYNC_PIPEB_FLAG)
116
117#define PSB_INT_IDENTITY_R 0x20A4
118#define PSB_INT_MASK_R 0x20A8
119#define PSB_INT_ENABLE_R 0x20A0
120
121#define _PSB_MMU_ER_MASK 0x0001FF00
122#define _PSB_MMU_ER_HOST (1 << 16)
123#define GPIOA 0x5010
124#define GPIOB 0x5014
125#define GPIOC 0x5018
126#define GPIOD 0x501c
127#define GPIOE 0x5020
128#define GPIOF 0x5024
129#define GPIOG 0x5028
130#define GPIOH 0x502c
131#define GPIO_CLOCK_DIR_MASK (1 << 0)
132#define GPIO_CLOCK_DIR_IN (0 << 1)
133#define GPIO_CLOCK_DIR_OUT (1 << 1)
134#define GPIO_CLOCK_VAL_MASK (1 << 2)
135#define GPIO_CLOCK_VAL_OUT (1 << 3)
136#define GPIO_CLOCK_VAL_IN (1 << 4)
137#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
138#define GPIO_DATA_DIR_MASK (1 << 8)
139#define GPIO_DATA_DIR_IN (0 << 9)
140#define GPIO_DATA_DIR_OUT (1 << 9)
141#define GPIO_DATA_VAL_MASK (1 << 10)
142#define GPIO_DATA_VAL_OUT (1 << 11)
143#define GPIO_DATA_VAL_IN (1 << 12)
144#define GPIO_DATA_PULLUP_DISABLE (1 << 13)
145
146#define VCLK_DIVISOR_VGA0 0x6000
147#define VCLK_DIVISOR_VGA1 0x6004
148#define VCLK_POST_DIV 0x6010
149
150#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
151#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
152#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
153#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
154#define PSB_COMM_USER_IRQ (1024 >> 2)
155#define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
156#define PSB_COMM_FW (2048 >> 2)
157
158#define PSB_UIRQ_VISTEST 1
159#define PSB_UIRQ_OOM_REPLY 2
160#define PSB_UIRQ_FIRE_TA_REPLY 3
161#define PSB_UIRQ_FIRE_RASTER_REPLY 4
162
163#define PSB_2D_SIZE (256*1024*1024)
164#define PSB_MAX_RELOC_PAGES 1024
165
166#define PSB_LOW_REG_OFFS 0x0204
167#define PSB_HIGH_REG_OFFS 0x0600
168
169#define PSB_NUM_VBLANKS 2
170
171
172#define PSB_2D_SIZE (256*1024*1024)
173#define PSB_MAX_RELOC_PAGES 1024
174
175#define PSB_LOW_REG_OFFS 0x0204
176#define PSB_HIGH_REG_OFFS 0x0600
177
178#define PSB_NUM_VBLANKS 2
179#define PSB_WATCHDOG_DELAY (HZ * 2)
180#define PSB_LID_DELAY (HZ / 10)
181
182#define PSB_PWR_STATE_ON 1
183#define PSB_PWR_STATE_OFF 2
184
185#define PSB_PMPOLICY_NOPM 0
186#define PSB_PMPOLICY_CLOCKGATING 1
187#define PSB_PMPOLICY_POWERDOWN 2
188
189#define PSB_PMSTATE_POWERUP 0
190#define PSB_PMSTATE_CLOCKGATED 1
191#define PSB_PMSTATE_POWERDOWN 2
192#define PSB_PCIx_MSI_ADDR_LOC 0x94
193#define PSB_PCIx_MSI_DATA_LOC 0x98
194
195
196#define KSEL_CRYSTAL_19 1
197#define KSEL_BYPASS_19 5
198#define KSEL_BYPASS_25 6
199#define KSEL_BYPASS_83_100 7
200
201struct drm_fb_helper;
202
203struct opregion_header;
204struct opregion_acpi;
205struct opregion_swsci;
206struct opregion_asle;
207
208struct psb_intel_opregion {
209 struct opregion_header *header;
210 struct opregion_acpi *acpi;
211 struct opregion_swsci *swsci;
212 struct opregion_asle *asle;
213 void *vbt;
214 u32 __iomem *lid_state;
215 struct work_struct asle_work;
216};
217
218struct sdvo_device_mapping {
219 u8 initialized;
220 u8 dvo_port;
221 u8 slave_addr;
222 u8 dvo_wiring;
223 u8 i2c_pin;
224 u8 i2c_speed;
225 u8 ddc_pin;
226};
227
228struct intel_gmbus {
229 struct i2c_adapter adapter;
230 struct i2c_adapter *force_bit;
231 u32 reg0;
232};
233
234
235struct psb_offset {
236 u32 fp0;
237 u32 fp1;
238 u32 cntr;
239 u32 conf;
240 u32 src;
241 u32 dpll;
242 u32 dpll_md;
243 u32 htotal;
244 u32 hblank;
245 u32 hsync;
246 u32 vtotal;
247 u32 vblank;
248 u32 vsync;
249 u32 stride;
250 u32 size;
251 u32 pos;
252 u32 surf;
253 u32 addr;
254 u32 base;
255 u32 status;
256 u32 linoff;
257 u32 tileoff;
258 u32 palette;
259};
260
261
262
263
264
265
266
267
268
269struct psb_pipe {
270 u32 fp0;
271 u32 fp1;
272 u32 cntr;
273 u32 conf;
274 u32 src;
275 u32 dpll;
276 u32 dpll_md;
277 u32 htotal;
278 u32 hblank;
279 u32 hsync;
280 u32 vtotal;
281 u32 vblank;
282 u32 vsync;
283 u32 stride;
284 u32 size;
285 u32 pos;
286 u32 base;
287 u32 surf;
288 u32 addr;
289 u32 status;
290 u32 linoff;
291 u32 tileoff;
292 u32 palette[256];
293};
294
295struct psb_state {
296 uint32_t saveVCLK_DIVISOR_VGA0;
297 uint32_t saveVCLK_DIVISOR_VGA1;
298 uint32_t saveVCLK_POST_DIV;
299 uint32_t saveVGACNTRL;
300 uint32_t saveADPA;
301 uint32_t saveLVDS;
302 uint32_t saveDVOA;
303 uint32_t saveDVOB;
304 uint32_t saveDVOC;
305 uint32_t savePP_ON;
306 uint32_t savePP_OFF;
307 uint32_t savePP_CONTROL;
308 uint32_t savePP_CYCLE;
309 uint32_t savePFIT_CONTROL;
310 uint32_t saveCLOCKGATING;
311 uint32_t saveDSPARB;
312 uint32_t savePFIT_AUTO_RATIOS;
313 uint32_t savePFIT_PGM_RATIOS;
314 uint32_t savePP_ON_DELAYS;
315 uint32_t savePP_OFF_DELAYS;
316 uint32_t savePP_DIVISOR;
317 uint32_t saveBCLRPAT_A;
318 uint32_t saveBCLRPAT_B;
319 uint32_t savePERF_MODE;
320 uint32_t saveDSPFW1;
321 uint32_t saveDSPFW2;
322 uint32_t saveDSPFW3;
323 uint32_t saveDSPFW4;
324 uint32_t saveDSPFW5;
325 uint32_t saveDSPFW6;
326 uint32_t saveCHICKENBIT;
327 uint32_t saveDSPACURSOR_CTRL;
328 uint32_t saveDSPBCURSOR_CTRL;
329 uint32_t saveDSPACURSOR_BASE;
330 uint32_t saveDSPBCURSOR_BASE;
331 uint32_t saveDSPACURSOR_POS;
332 uint32_t saveDSPBCURSOR_POS;
333 uint32_t saveOV_OVADD;
334 uint32_t saveOV_OGAMC0;
335 uint32_t saveOV_OGAMC1;
336 uint32_t saveOV_OGAMC2;
337 uint32_t saveOV_OGAMC3;
338 uint32_t saveOV_OGAMC4;
339 uint32_t saveOV_OGAMC5;
340 uint32_t saveOVC_OVADD;
341 uint32_t saveOVC_OGAMC0;
342 uint32_t saveOVC_OGAMC1;
343 uint32_t saveOVC_OGAMC2;
344 uint32_t saveOVC_OGAMC3;
345 uint32_t saveOVC_OGAMC4;
346 uint32_t saveOVC_OGAMC5;
347
348
349 uint32_t saveHISTOGRAM_INT_CONTROL_REG;
350 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
351 uint32_t savePWM_CONTROL_LOGIC;
352};
353
354struct cdv_state {
355 uint32_t saveDSPCLK_GATE_D;
356 uint32_t saveRAMCLK_GATE_D;
357 uint32_t saveDSPARB;
358 uint32_t saveDSPFW[6];
359 uint32_t saveADPA;
360 uint32_t savePP_CONTROL;
361 uint32_t savePFIT_PGM_RATIOS;
362 uint32_t saveLVDS;
363 uint32_t savePFIT_CONTROL;
364 uint32_t savePP_ON_DELAYS;
365 uint32_t savePP_OFF_DELAYS;
366 uint32_t savePP_CYCLE;
367 uint32_t saveVGACNTRL;
368 uint32_t saveIER;
369 uint32_t saveIMR;
370 u8 saveLBB;
371};
372
373struct psb_save_area {
374 struct psb_pipe pipe[3];
375 uint32_t saveBSM;
376 uint32_t saveVBT;
377 union {
378 struct psb_state psb;
379 struct cdv_state cdv;
380 };
381 uint32_t saveBLC_PWM_CTL2;
382 uint32_t saveBLC_PWM_CTL;
383};
384
385struct psb_ops;
386
387#define PSB_NUM_PIPE 3
388
389struct intel_scu_ipc_dev;
390
391struct drm_psb_private {
392 struct drm_device *dev;
393 struct pci_dev *aux_pdev;
394 struct pci_dev *lpc_pdev;
395 const struct psb_ops *ops;
396 const struct psb_offset *regmap;
397
398 struct child_device_config *child_dev;
399 int child_dev_num;
400
401 struct psb_gtt gtt;
402
403
404 struct psb_gtt_mm *gtt_mm;
405 struct page *scratch_page;
406 u32 __iomem *gtt_map;
407 uint32_t stolen_base;
408 u8 __iomem *vram_addr;
409 unsigned long vram_stolen_size;
410 int gtt_initialized;
411 u16 gmch_ctrl;
412 u32 pge_ctl;
413
414 struct mutex gtt_mutex;
415 struct resource *gtt_mem;
416
417 struct mutex mmap_mutex;
418
419 struct psb_mmu_driver *mmu;
420 struct psb_mmu_pd *pf_pd;
421
422
423 uint8_t __iomem *sgx_reg;
424 uint8_t __iomem *vdc_reg;
425 uint8_t __iomem *aux_reg;
426 uint16_t lpc_gpio_base;
427 uint32_t gatt_free_offset;
428
429
430 uint32_t vdc_irq_mask;
431 uint32_t pipestat[PSB_NUM_PIPE];
432
433 spinlock_t irqmask_lock;
434
435
436 bool suspended;
437 bool display_power;
438 int display_count;
439
440
441 struct psb_intel_mode_device mode_dev;
442 bool modeset;
443
444 struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
445 struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
446 uint32_t num_pipe;
447
448
449 uint32_t ospm_base;
450
451
452 u32 fuse_reg_value;
453 u32 video_device_fuse;
454
455
456 uint8_t platform_rev_id;
457
458
459 struct intel_gmbus *gmbus;
460 uint8_t __iomem *gmbus_reg;
461
462
463 int crt_ddc_pin;
464
465
466 struct sdvo_device_mapping sdvo_mappings[2];
467 u32 hotplug_supported_mask;
468 struct drm_property *broadcast_rgb_property;
469 struct drm_property *force_audio_property;
470
471
472 int backlight_duty_cycle;
473 bool panel_wants_dither;
474 struct drm_display_mode *panel_fixed_mode;
475 struct drm_display_mode *lfp_lvds_vbt_mode;
476 struct drm_display_mode *sdvo_lvds_vbt_mode;
477
478 struct bdb_lvds_backlight *lvds_bl;
479 struct psb_intel_i2c_chan *lvds_i2c_bus;
480
481
482 unsigned int int_tv_support:1;
483 unsigned int lvds_dither:1;
484 unsigned int lvds_vbt:1;
485 unsigned int int_crt_support:1;
486 unsigned int lvds_use_ssc:1;
487 int lvds_ssc_freq;
488 bool is_lvds_on;
489 bool is_mipi_on;
490 bool lvds_enabled_in_vbt;
491 u32 mipi_ctrl_display;
492
493 unsigned int core_freq;
494 uint32_t iLVDS_enable;
495
496
497 int rpm_enabled;
498
499
500 bool has_gct;
501 struct oaktrail_gct_data gct_data;
502
503
504 struct oaktrail_hdmi_dev *hdmi_priv;
505
506
507 struct psb_save_area regs;
508
509
510 uint32_t msi_addr;
511 uint32_t msi_data;
512
513
514 struct work_struct hotplug_work;
515
516
517 spinlock_t lid_lock;
518 struct timer_list lid_timer;
519 struct psb_intel_opregion opregion;
520 u32 lid_last_state;
521
522
523 uint32_t apm_reg;
524 uint16_t apm_base;
525
526
527
528
529
530 struct intel_scu_ipc_dev *scu;
531 struct backlight_device *backlight_device;
532 struct drm_property *backlight_property;
533 bool backlight_enabled;
534 int backlight_level;
535 uint32_t blc_adj1;
536 uint32_t blc_adj2;
537
538 struct drm_fb_helper *fb_helper;
539
540
541 int brightness;
542 int brightness_adjusted;
543
544 bool dsr_enable;
545 u32 dsr_fb_update;
546 bool dpi_panel_on[3];
547 void *dsi_configs[2];
548 u32 bpp;
549 u32 bpp2;
550
551 u32 pipeconf[3];
552 u32 dspcntr[3];
553
554 bool dplla_96mhz;
555
556 struct {
557 int rate;
558 int lanes;
559 int preemphasis;
560 int vswing;
561
562 bool initialized;
563 bool support;
564 int bpp;
565 struct edp_power_seq pps;
566 } edp;
567 uint8_t panel_type;
568};
569
570
571
572struct psb_ops {
573 const char *name;
574 int pipes;
575 int crtcs;
576 int sgx_offset;
577 int hdmi_mask;
578 int lvds_mask;
579 int sdvo_mask;
580 int cursor_needs_phys;
581
582
583 struct drm_crtc_helper_funcs const *crtc_helper;
584 struct drm_crtc_funcs const *crtc_funcs;
585 const struct gma_clock_funcs *clock_funcs;
586
587
588 int (*chip_setup)(struct drm_device *dev);
589 void (*chip_teardown)(struct drm_device *dev);
590
591 void (*errata)(struct drm_device *dev);
592
593
594 int (*output_init)(struct drm_device *dev);
595 int (*hotplug)(struct drm_device *dev);
596 void (*hotplug_enable)(struct drm_device *dev, bool on);
597
598 void (*init_pm)(struct drm_device *dev);
599 int (*save_regs)(struct drm_device *dev);
600 int (*restore_regs)(struct drm_device *dev);
601 void (*save_crtc)(struct drm_crtc *crtc);
602 void (*restore_crtc)(struct drm_crtc *crtc);
603 int (*power_up)(struct drm_device *dev);
604 int (*power_down)(struct drm_device *dev);
605 void (*update_wm)(struct drm_device *dev, struct drm_crtc *crtc);
606 void (*disable_sr)(struct drm_device *dev);
607
608 void (*lvds_bl_power)(struct drm_device *dev, bool on);
609#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
610
611 int (*backlight_init)(struct drm_device *dev);
612#endif
613 int i2c_bus;
614};
615
616
617
618extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
619extern int drm_pick_crtcs(struct drm_device *dev);
620
621static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
622{
623 return (struct drm_psb_private *) dev->dev_private;
624}
625
626
627extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
628extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
629extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
630extern int psb_enable_vblank(struct drm_crtc *crtc);
631extern void psb_disable_vblank(struct drm_crtc *crtc);
632void
633psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
634
635void
636psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
637
638extern u32 psb_get_vblank_counter(struct drm_crtc *crtc);
639
640
641extern int psbfb_probed(struct drm_device *dev);
642extern int psbfb_remove(struct drm_device *dev,
643 struct drm_framebuffer *fb);
644
645extern void psb_spank(struct drm_psb_private *dev_priv);
646
647
648extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
649extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
650extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
651
652
653extern void psb_modeset_init(struct drm_device *dev);
654extern void psb_modeset_cleanup(struct drm_device *dev);
655extern int psb_fbdev_init(struct drm_device *dev);
656
657
658int gma_backlight_init(struct drm_device *dev);
659void gma_backlight_exit(struct drm_device *dev);
660void gma_backlight_disable(struct drm_device *dev);
661void gma_backlight_enable(struct drm_device *dev);
662void gma_backlight_set(struct drm_device *dev, int v);
663
664
665extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs;
666
667
668extern void oaktrail_lvds_init(struct drm_device *dev,
669 struct psb_intel_mode_device *mode_dev);
670
671
672extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
673extern const struct drm_crtc_funcs gma_intel_crtc_funcs;
674
675
676extern const struct drm_connector_helper_funcs
677 psb_intel_lvds_connector_helper_funcs;
678extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
679
680
681extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
682 struct drm_mode_create_dumb *args);
683
684
685extern const struct psb_ops psb_chip_ops;
686
687
688extern const struct psb_ops oaktrail_chip_ops;
689
690
691extern const struct psb_ops cdv_chip_ops;
692
693
694#define PSB_D_GENERAL (1 << 0)
695#define PSB_D_INIT (1 << 1)
696#define PSB_D_IRQ (1 << 2)
697#define PSB_D_ENTRY (1 << 3)
698
699#define PSB_D_HV (1 << 4)
700#define PSB_D_DBI_BF (1 << 5)
701#define PSB_D_PM (1 << 6)
702#define PSB_D_RENDER (1 << 7)
703#define PSB_D_REG (1 << 8)
704#define PSB_D_MSVDX (1 << 9)
705#define PSB_D_TOPAZ (1 << 10)
706
707extern int drm_idle_check_interval;
708
709
710static inline u32 MRST_MSG_READ32(int domain, uint port, uint offset)
711{
712 int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
713 uint32_t ret_val = 0;
714 struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
715 pci_write_config_dword(pci_root, 0xD0, mcr);
716 pci_read_config_dword(pci_root, 0xD4, &ret_val);
717 pci_dev_put(pci_root);
718 return ret_val;
719}
720static inline void MRST_MSG_WRITE32(int domain, uint port, uint offset,
721 u32 value)
722{
723 int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
724 struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
725 pci_write_config_dword(pci_root, 0xD4, value);
726 pci_write_config_dword(pci_root, 0xD0, mcr);
727 pci_dev_put(pci_root);
728}
729
730static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
731{
732 struct drm_psb_private *dev_priv = dev->dev_private;
733 return ioread32(dev_priv->vdc_reg + reg);
734}
735
736static inline uint32_t REGISTER_READ_AUX(struct drm_device *dev, uint32_t reg)
737{
738 struct drm_psb_private *dev_priv = dev->dev_private;
739 return ioread32(dev_priv->aux_reg + reg);
740}
741
742#define REG_READ(reg) REGISTER_READ(dev, (reg))
743#define REG_READ_AUX(reg) REGISTER_READ_AUX(dev, (reg))
744
745
746static inline uint32_t REGISTER_READ_WITH_AUX(struct drm_device *dev,
747 uint32_t reg, int aux)
748{
749 uint32_t val;
750
751 if (aux)
752 val = REG_READ_AUX(reg);
753 else
754 val = REG_READ(reg);
755
756 return val;
757}
758
759#define REG_READ_WITH_AUX(reg, aux) REGISTER_READ_WITH_AUX(dev, (reg), (aux))
760
761static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
762 uint32_t val)
763{
764 struct drm_psb_private *dev_priv = dev->dev_private;
765 iowrite32((val), dev_priv->vdc_reg + (reg));
766}
767
768static inline void REGISTER_WRITE_AUX(struct drm_device *dev, uint32_t reg,
769 uint32_t val)
770{
771 struct drm_psb_private *dev_priv = dev->dev_private;
772 iowrite32((val), dev_priv->aux_reg + (reg));
773}
774
775#define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
776#define REG_WRITE_AUX(reg, val) REGISTER_WRITE_AUX(dev, (reg), (val))
777
778static inline void REGISTER_WRITE_WITH_AUX(struct drm_device *dev, uint32_t reg,
779 uint32_t val, int aux)
780{
781 if (aux)
782 REG_WRITE_AUX(reg, val);
783 else
784 REG_WRITE(reg, val);
785}
786
787#define REG_WRITE_WITH_AUX(reg, val, aux) REGISTER_WRITE_WITH_AUX(dev, (reg), (val), (aux))
788
789static inline void REGISTER_WRITE16(struct drm_device *dev,
790 uint32_t reg, uint32_t val)
791{
792 struct drm_psb_private *dev_priv = dev->dev_private;
793 iowrite16((val), dev_priv->vdc_reg + (reg));
794}
795
796#define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val))
797
798static inline void REGISTER_WRITE8(struct drm_device *dev,
799 uint32_t reg, uint32_t val)
800{
801 struct drm_psb_private *dev_priv = dev->dev_private;
802 iowrite8((val), dev_priv->vdc_reg + (reg));
803}
804
805#define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val))
806
807#define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs))
808#define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs))
809
810
811#ifdef TRAP_SGX_PM_FAULT
812#define PSB_RSGX32(_offs) \
813({ \
814 if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \
815 pr_err("access sgx when it's off!! (READ) %s, %d\n", \
816 __FILE__, __LINE__); \
817 melay(1000); \
818 } \
819 ioread32(dev_priv->sgx_reg + (_offs)); \
820})
821#else
822#define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs))
823#endif
824#define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs))
825
826#define MSVDX_REG_DUMP 0
827
828#define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs))
829#define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs))
830
831#endif
832
