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25#include "intel_color.h"
26#include "intel_de.h"
27#include "intel_display_types.h"
28
29#define CTM_COEFF_SIGN (1ULL << 63)
30
31#define CTM_COEFF_1_0 (1ULL << 32)
32#define CTM_COEFF_2_0 (CTM_COEFF_1_0 << 1)
33#define CTM_COEFF_4_0 (CTM_COEFF_2_0 << 1)
34#define CTM_COEFF_8_0 (CTM_COEFF_4_0 << 1)
35#define CTM_COEFF_0_5 (CTM_COEFF_1_0 >> 1)
36#define CTM_COEFF_0_25 (CTM_COEFF_0_5 >> 1)
37#define CTM_COEFF_0_125 (CTM_COEFF_0_25 >> 1)
38
39#define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255)
40
41#define CTM_COEFF_NEGATIVE(coeff) (((coeff) & CTM_COEFF_SIGN) != 0)
42#define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1))
43
44#define LEGACY_LUT_LENGTH 256
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70#define ILK_CSC_COEFF_FP(coeff, fbits) \
71 (clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8)
72
73#define ILK_CSC_COEFF_LIMITED_RANGE 0x0dc0
74#define ILK_CSC_COEFF_1_0 0x7800
75
76#define ILK_CSC_POSTOFF_LIMITED_RANGE (16 * (1 << 12) / 255)
77
78
79static const u16 ilk_csc_off_zero[3] = {};
80
81
82static const u16 ilk_csc_coeff_identity[9] = {
83 ILK_CSC_COEFF_1_0, 0, 0,
84 0, ILK_CSC_COEFF_1_0, 0,
85 0, 0, ILK_CSC_COEFF_1_0,
86};
87
88
89static const u16 ilk_csc_postoff_limited_range[3] = {
90 ILK_CSC_POSTOFF_LIMITED_RANGE,
91 ILK_CSC_POSTOFF_LIMITED_RANGE,
92 ILK_CSC_POSTOFF_LIMITED_RANGE,
93};
94
95
96static const u16 ilk_csc_coeff_limited_range[9] = {
97 ILK_CSC_COEFF_LIMITED_RANGE, 0, 0,
98 0, ILK_CSC_COEFF_LIMITED_RANGE, 0,
99 0, 0, ILK_CSC_COEFF_LIMITED_RANGE,
100};
101
102
103static const u16 ilk_csc_coeff_rgb_to_ycbcr[9] = {
104 0x1e08, 0x9cc0, 0xb528,
105 0x2ba8, 0x09d8, 0x37e8,
106 0xbce8, 0x9ad8, 0x1e08,
107};
108
109
110static const u16 ilk_csc_postoff_rgb_to_ycbcr[3] = {
111 0x0800, 0x0100, 0x0800,
112};
113
114static bool lut_is_legacy(const struct drm_property_blob *lut)
115{
116 return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH;
117}
118
119static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state *crtc_state)
120{
121 return !crtc_state->hw.degamma_lut &&
122 !crtc_state->hw.ctm &&
123 crtc_state->hw.gamma_lut &&
124 lut_is_legacy(crtc_state->hw.gamma_lut);
125}
126
127
128
129
130
131static u64 *ctm_mult_by_limited(u64 *result, const u64 *input)
132{
133 int i;
134
135 for (i = 0; i < 9; i++) {
136 u64 user_coeff = input[i];
137 u32 limited_coeff = CTM_COEFF_LIMITED_RANGE;
138 u32 abs_coeff = clamp_val(CTM_COEFF_ABS(user_coeff), 0,
139 CTM_COEFF_4_0 - 1) >> 2;
140
141
142
143
144
145
146 result[i] = mul_u32_u32(limited_coeff, abs_coeff) >> 30;
147 result[i] |= user_coeff & CTM_COEFF_SIGN;
148 }
149
150 return result;
151}
152
153static void ilk_update_pipe_csc(struct intel_crtc *crtc,
154 const u16 preoff[3],
155 const u16 coeff[9],
156 const u16 postoff[3])
157{
158 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
159 enum pipe pipe = crtc->pipe;
160
161 intel_de_write(dev_priv, PIPE_CSC_PREOFF_HI(pipe), preoff[0]);
162 intel_de_write(dev_priv, PIPE_CSC_PREOFF_ME(pipe), preoff[1]);
163 intel_de_write(dev_priv, PIPE_CSC_PREOFF_LO(pipe), preoff[2]);
164
165 intel_de_write(dev_priv, PIPE_CSC_COEFF_RY_GY(pipe),
166 coeff[0] << 16 | coeff[1]);
167 intel_de_write(dev_priv, PIPE_CSC_COEFF_BY(pipe), coeff[2] << 16);
168
169 intel_de_write(dev_priv, PIPE_CSC_COEFF_RU_GU(pipe),
170 coeff[3] << 16 | coeff[4]);
171 intel_de_write(dev_priv, PIPE_CSC_COEFF_BU(pipe), coeff[5] << 16);
172
173 intel_de_write(dev_priv, PIPE_CSC_COEFF_RV_GV(pipe),
174 coeff[6] << 16 | coeff[7]);
175 intel_de_write(dev_priv, PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16);
176
177 if (DISPLAY_VER(dev_priv) >= 7) {
178 intel_de_write(dev_priv, PIPE_CSC_POSTOFF_HI(pipe),
179 postoff[0]);
180 intel_de_write(dev_priv, PIPE_CSC_POSTOFF_ME(pipe),
181 postoff[1]);
182 intel_de_write(dev_priv, PIPE_CSC_POSTOFF_LO(pipe),
183 postoff[2]);
184 }
185}
186
187static void icl_update_output_csc(struct intel_crtc *crtc,
188 const u16 preoff[3],
189 const u16 coeff[9],
190 const u16 postoff[3])
191{
192 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
193 enum pipe pipe = crtc->pipe;
194
195 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_PREOFF_HI(pipe), preoff[0]);
196 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_PREOFF_ME(pipe), preoff[1]);
197 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_PREOFF_LO(pipe), preoff[2]);
198
199 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe),
200 coeff[0] << 16 | coeff[1]);
201 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_BY(pipe),
202 coeff[2] << 16);
203
204 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe),
205 coeff[3] << 16 | coeff[4]);
206 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_BU(pipe),
207 coeff[5] << 16);
208
209 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe),
210 coeff[6] << 16 | coeff[7]);
211 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_BV(pipe),
212 coeff[8] << 16);
213
214 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), postoff[0]);
215 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), postoff[1]);
216 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe), postoff[2]);
217}
218
219static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
220{
221 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
222
223
224
225
226
227 return crtc_state->limited_color_range &&
228 (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
229 IS_DISPLAY_VER(dev_priv, 9, 10));
230}
231
232static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
233 u16 coeffs[9])
234{
235 const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
236 const u64 *input;
237 u64 temp[9];
238 int i;
239
240 if (ilk_csc_limited_range(crtc_state))
241 input = ctm_mult_by_limited(temp, ctm->matrix);
242 else
243 input = ctm->matrix;
244
245
246
247
248
249 for (i = 0; i < 9; i++) {
250 u64 abs_coeff = ((1ULL << 63) - 1) & input[i];
251
252
253
254
255
256 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
257
258 coeffs[i] = 0;
259
260
261 if (CTM_COEFF_NEGATIVE(input[i]))
262 coeffs[i] |= 1 << 15;
263
264 if (abs_coeff < CTM_COEFF_0_125)
265 coeffs[i] |= (3 << 12) |
266 ILK_CSC_COEFF_FP(abs_coeff, 12);
267 else if (abs_coeff < CTM_COEFF_0_25)
268 coeffs[i] |= (2 << 12) |
269 ILK_CSC_COEFF_FP(abs_coeff, 11);
270 else if (abs_coeff < CTM_COEFF_0_5)
271 coeffs[i] |= (1 << 12) |
272 ILK_CSC_COEFF_FP(abs_coeff, 10);
273 else if (abs_coeff < CTM_COEFF_1_0)
274 coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9);
275 else if (abs_coeff < CTM_COEFF_2_0)
276 coeffs[i] |= (7 << 12) |
277 ILK_CSC_COEFF_FP(abs_coeff, 8);
278 else
279 coeffs[i] |= (6 << 12) |
280 ILK_CSC_COEFF_FP(abs_coeff, 7);
281 }
282}
283
284static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
285{
286 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
287 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
288 bool limited_color_range = ilk_csc_limited_range(crtc_state);
289
290 if (crtc_state->hw.ctm) {
291 u16 coeff[9];
292
293 ilk_csc_convert_ctm(crtc_state, coeff);
294 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, coeff,
295 limited_color_range ?
296 ilk_csc_postoff_limited_range :
297 ilk_csc_off_zero);
298 } else if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {
299 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
300 ilk_csc_coeff_rgb_to_ycbcr,
301 ilk_csc_postoff_rgb_to_ycbcr);
302 } else if (limited_color_range) {
303 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
304 ilk_csc_coeff_limited_range,
305 ilk_csc_postoff_limited_range);
306 } else if (crtc_state->csc_enable) {
307
308
309
310
311
312
313 drm_WARN_ON(&dev_priv->drm, !IS_GEMINILAKE(dev_priv));
314
315 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
316 ilk_csc_coeff_identity,
317 ilk_csc_off_zero);
318 }
319
320 intel_de_write(dev_priv, PIPE_CSC_MODE(crtc->pipe),
321 crtc_state->csc_mode);
322}
323
324static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
325{
326 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
327 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
328
329 if (crtc_state->hw.ctm) {
330 u16 coeff[9];
331
332 ilk_csc_convert_ctm(crtc_state, coeff);
333 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
334 coeff, ilk_csc_off_zero);
335 }
336
337 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {
338 icl_update_output_csc(crtc, ilk_csc_off_zero,
339 ilk_csc_coeff_rgb_to_ycbcr,
340 ilk_csc_postoff_rgb_to_ycbcr);
341 } else if (crtc_state->limited_color_range) {
342 icl_update_output_csc(crtc, ilk_csc_off_zero,
343 ilk_csc_coeff_limited_range,
344 ilk_csc_postoff_limited_range);
345 }
346
347 intel_de_write(dev_priv, PIPE_CSC_MODE(crtc->pipe),
348 crtc_state->csc_mode);
349}
350
351static void chv_load_cgm_csc(struct intel_crtc *crtc,
352 const struct drm_property_blob *blob)
353{
354 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
355 const struct drm_color_ctm *ctm = blob->data;
356 enum pipe pipe = crtc->pipe;
357 u16 coeffs[9];
358 int i;
359
360 for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
361 u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i];
362
363
364 abs_coeff += 1 << (32 - 13);
365
366 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
367
368 coeffs[i] = 0;
369
370
371 if (ctm->matrix[i] & (1ULL << 63))
372 coeffs[i] |= 1 << 15;
373
374 coeffs[i] |= ((abs_coeff >> 32) & 7) << 12;
375 coeffs[i] |= (abs_coeff >> 20) & 0xfff;
376 }
377
378 intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF01(pipe),
379 coeffs[1] << 16 | coeffs[0]);
380 intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF23(pipe),
381 coeffs[3] << 16 | coeffs[2]);
382 intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF45(pipe),
383 coeffs[5] << 16 | coeffs[4]);
384 intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF67(pipe),
385 coeffs[7] << 16 | coeffs[6]);
386 intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF8(pipe),
387 coeffs[8]);
388}
389
390
391static u32 intel_color_lut_pack(u32 val, int bit_precision)
392{
393 u32 max = 0xffff >> (16 - bit_precision);
394
395 val = clamp_val(val, 0, max);
396
397 if (bit_precision < 16)
398 val <<= 16 - bit_precision;
399
400 return val;
401}
402
403static u32 i9xx_lut_8(const struct drm_color_lut *color)
404{
405 return drm_color_lut_extract(color->red, 8) << 16 |
406 drm_color_lut_extract(color->green, 8) << 8 |
407 drm_color_lut_extract(color->blue, 8);
408}
409
410static void i9xx_lut_8_pack(struct drm_color_lut *entry, u32 val)
411{
412 entry->red = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_RED_MASK, val), 8);
413 entry->green = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_GREEN_MASK, val), 8);
414 entry->blue = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_BLUE_MASK, val), 8);
415}
416
417
418static u32 i965_lut_10p6_ldw(const struct drm_color_lut *color)
419{
420 return (color->red & 0xff) << 16 |
421 (color->green & 0xff) << 8 |
422 (color->blue & 0xff);
423}
424
425
426static u32 i965_lut_10p6_udw(const struct drm_color_lut *color)
427{
428 return (color->red >> 8) << 16 |
429 (color->green >> 8) << 8 |
430 (color->blue >> 8);
431}
432
433static void i965_lut_10p6_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
434{
435 entry->red = REG_FIELD_GET(PALETTE_RED_MASK, udw) << 8 |
436 REG_FIELD_GET(PALETTE_RED_MASK, ldw);
437 entry->green = REG_FIELD_GET(PALETTE_GREEN_MASK, udw) << 8 |
438 REG_FIELD_GET(PALETTE_GREEN_MASK, ldw);
439 entry->blue = REG_FIELD_GET(PALETTE_BLUE_MASK, udw) << 8 |
440 REG_FIELD_GET(PALETTE_BLUE_MASK, ldw);
441}
442
443static u16 i965_lut_11p6_max_pack(u32 val)
444{
445
446 return clamp_val(val, 0, 0xffff);
447}
448
449static u32 ilk_lut_10(const struct drm_color_lut *color)
450{
451 return drm_color_lut_extract(color->red, 10) << 20 |
452 drm_color_lut_extract(color->green, 10) << 10 |
453 drm_color_lut_extract(color->blue, 10);
454}
455
456static void ilk_lut_10_pack(struct drm_color_lut *entry, u32 val)
457{
458 entry->red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_RED_MASK, val), 10);
459 entry->green = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_GREEN_MASK, val), 10);
460 entry->blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_BLUE_MASK, val), 10);
461}
462
463static void icl_lut_multi_seg_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
464{
465 entry->red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, udw) << 6 |
466 REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, ldw);
467 entry->green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, udw) << 6 |
468 REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, ldw);
469 entry->blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, udw) << 6 |
470 REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, ldw);
471}
472
473static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
474{
475 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
476 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
477 enum pipe pipe = crtc->pipe;
478 u32 val;
479
480 val = intel_de_read(dev_priv, PIPECONF(pipe));
481 val &= ~PIPECONF_GAMMA_MODE_MASK_I9XX;
482 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
483 intel_de_write(dev_priv, PIPECONF(pipe), val);
484}
485
486static void ilk_color_commit(const struct intel_crtc_state *crtc_state)
487{
488 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
489 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
490 enum pipe pipe = crtc->pipe;
491 u32 val;
492
493 val = intel_de_read(dev_priv, PIPECONF(pipe));
494 val &= ~PIPECONF_GAMMA_MODE_MASK_ILK;
495 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
496 intel_de_write(dev_priv, PIPECONF(pipe), val);
497
498 ilk_load_csc_matrix(crtc_state);
499}
500
501static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
502{
503 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
504 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
505
506 intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe),
507 crtc_state->gamma_mode);
508
509 ilk_load_csc_matrix(crtc_state);
510}
511
512static void skl_color_commit(const struct intel_crtc_state *crtc_state)
513{
514 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
515 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
516 enum pipe pipe = crtc->pipe;
517 u32 val = 0;
518
519
520
521
522
523
524 if (crtc_state->gamma_enable)
525 val |= SKL_BOTTOM_COLOR_GAMMA_ENABLE;
526 if (crtc_state->csc_enable)
527 val |= SKL_BOTTOM_COLOR_CSC_ENABLE;
528 intel_de_write(dev_priv, SKL_BOTTOM_COLOR(pipe), val);
529
530 intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe),
531 crtc_state->gamma_mode);
532
533 if (DISPLAY_VER(dev_priv) >= 11)
534 icl_load_csc_matrix(crtc_state);
535 else
536 ilk_load_csc_matrix(crtc_state);
537}
538
539static void i9xx_load_lut_8(struct intel_crtc *crtc,
540 const struct drm_property_blob *blob)
541{
542 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
543 const struct drm_color_lut *lut;
544 enum pipe pipe = crtc->pipe;
545 int i;
546
547 if (!blob)
548 return;
549
550 lut = blob->data;
551
552 for (i = 0; i < 256; i++)
553 intel_de_write(dev_priv, PALETTE(pipe, i),
554 i9xx_lut_8(&lut[i]));
555}
556
557static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
558{
559 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
560 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
561 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
562
563 assert_pll_enabled(dev_priv, crtc->pipe);
564
565 i9xx_load_lut_8(crtc, gamma_lut);
566}
567
568static void i965_load_lut_10p6(struct intel_crtc *crtc,
569 const struct drm_property_blob *blob)
570{
571 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
572 const struct drm_color_lut *lut = blob->data;
573 int i, lut_size = drm_color_lut_size(blob);
574 enum pipe pipe = crtc->pipe;
575
576 for (i = 0; i < lut_size - 1; i++) {
577 intel_de_write(dev_priv, PALETTE(pipe, 2 * i + 0),
578 i965_lut_10p6_ldw(&lut[i]));
579 intel_de_write(dev_priv, PALETTE(pipe, 2 * i + 1),
580 i965_lut_10p6_udw(&lut[i]));
581 }
582
583 intel_de_write(dev_priv, PIPEGCMAX(pipe, 0), lut[i].red);
584 intel_de_write(dev_priv, PIPEGCMAX(pipe, 1), lut[i].green);
585 intel_de_write(dev_priv, PIPEGCMAX(pipe, 2), lut[i].blue);
586}
587
588static void i965_load_luts(const struct intel_crtc_state *crtc_state)
589{
590 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
591 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
592 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
593
594 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
595 assert_dsi_pll_enabled(dev_priv);
596 else
597 assert_pll_enabled(dev_priv, crtc->pipe);
598
599 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
600 i9xx_load_lut_8(crtc, gamma_lut);
601 else
602 i965_load_lut_10p6(crtc, gamma_lut);
603}
604
605static void ilk_load_lut_8(struct intel_crtc *crtc,
606 const struct drm_property_blob *blob)
607{
608 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
609 const struct drm_color_lut *lut;
610 enum pipe pipe = crtc->pipe;
611 int i;
612
613 if (!blob)
614 return;
615
616 lut = blob->data;
617
618 for (i = 0; i < 256; i++)
619 intel_de_write(dev_priv, LGC_PALETTE(pipe, i),
620 i9xx_lut_8(&lut[i]));
621}
622
623static void ilk_load_lut_10(struct intel_crtc *crtc,
624 const struct drm_property_blob *blob)
625{
626 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
627 const struct drm_color_lut *lut = blob->data;
628 int i, lut_size = drm_color_lut_size(blob);
629 enum pipe pipe = crtc->pipe;
630
631 for (i = 0; i < lut_size; i++)
632 intel_de_write(dev_priv, PREC_PALETTE(pipe, i),
633 ilk_lut_10(&lut[i]));
634}
635
636static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
637{
638 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
639 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
640
641 switch (crtc_state->gamma_mode) {
642 case GAMMA_MODE_MODE_8BIT:
643 ilk_load_lut_8(crtc, gamma_lut);
644 break;
645 case GAMMA_MODE_MODE_10BIT:
646 ilk_load_lut_10(crtc, gamma_lut);
647 break;
648 default:
649 MISSING_CASE(crtc_state->gamma_mode);
650 break;
651 }
652}
653
654static int ivb_lut_10_size(u32 prec_index)
655{
656 if (prec_index & PAL_PREC_SPLIT_MODE)
657 return 512;
658 else
659 return 1024;
660}
661
662
663
664
665
666
667static void ivb_load_lut_10(struct intel_crtc *crtc,
668 const struct drm_property_blob *blob,
669 u32 prec_index)
670{
671 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
672 int hw_lut_size = ivb_lut_10_size(prec_index);
673 const struct drm_color_lut *lut = blob->data;
674 int i, lut_size = drm_color_lut_size(blob);
675 enum pipe pipe = crtc->pipe;
676
677 for (i = 0; i < hw_lut_size; i++) {
678
679 const struct drm_color_lut *entry =
680 &lut[i * (lut_size - 1) / (hw_lut_size - 1)];
681
682 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), prec_index++);
683 intel_de_write(dev_priv, PREC_PAL_DATA(pipe),
684 ilk_lut_10(entry));
685 }
686
687
688
689
690
691 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0);
692}
693
694
695static void bdw_load_lut_10(struct intel_crtc *crtc,
696 const struct drm_property_blob *blob,
697 u32 prec_index)
698{
699 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
700 int hw_lut_size = ivb_lut_10_size(prec_index);
701 const struct drm_color_lut *lut = blob->data;
702 int i, lut_size = drm_color_lut_size(blob);
703 enum pipe pipe = crtc->pipe;
704
705 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe),
706 prec_index | PAL_PREC_AUTO_INCREMENT);
707
708 for (i = 0; i < hw_lut_size; i++) {
709
710 const struct drm_color_lut *entry =
711 &lut[i * (lut_size - 1) / (hw_lut_size - 1)];
712
713 intel_de_write(dev_priv, PREC_PAL_DATA(pipe),
714 ilk_lut_10(entry));
715 }
716
717
718
719
720
721 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0);
722}
723
724static void ivb_load_lut_ext_max(const struct intel_crtc_state *crtc_state)
725{
726 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
727 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
728 enum pipe pipe = crtc->pipe;
729
730
731 intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
732 intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
733 intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
734
735
736
737
738
739
740 if (DISPLAY_VER(dev_priv) >= 10) {
741 intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 0),
742 1 << 16);
743 intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 1),
744 1 << 16);
745 intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 2),
746 1 << 16);
747 }
748}
749
750static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
751{
752 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
753 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
754 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
755 const struct drm_property_blob *blob = gamma_lut ?: degamma_lut;
756
757 switch (crtc_state->gamma_mode) {
758 case GAMMA_MODE_MODE_8BIT:
759 ilk_load_lut_8(crtc, blob);
760 break;
761 case GAMMA_MODE_MODE_SPLIT:
762 ivb_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
763 PAL_PREC_INDEX_VALUE(0));
764 ivb_load_lut_ext_max(crtc_state);
765 ivb_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE |
766 PAL_PREC_INDEX_VALUE(512));
767 break;
768 case GAMMA_MODE_MODE_10BIT:
769 ivb_load_lut_10(crtc, blob,
770 PAL_PREC_INDEX_VALUE(0));
771 ivb_load_lut_ext_max(crtc_state);
772 break;
773 default:
774 MISSING_CASE(crtc_state->gamma_mode);
775 break;
776 }
777}
778
779static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
780{
781 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
782 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
783 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
784 const struct drm_property_blob *blob = gamma_lut ?: degamma_lut;
785
786 switch (crtc_state->gamma_mode) {
787 case GAMMA_MODE_MODE_8BIT:
788 ilk_load_lut_8(crtc, blob);
789 break;
790 case GAMMA_MODE_MODE_SPLIT:
791 bdw_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
792 PAL_PREC_INDEX_VALUE(0));
793 ivb_load_lut_ext_max(crtc_state);
794 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE |
795 PAL_PREC_INDEX_VALUE(512));
796 break;
797 case GAMMA_MODE_MODE_10BIT:
798
799 bdw_load_lut_10(crtc, blob,
800 PAL_PREC_INDEX_VALUE(0));
801 ivb_load_lut_ext_max(crtc_state);
802 break;
803 default:
804 MISSING_CASE(crtc_state->gamma_mode);
805 break;
806 }
807}
808
809static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
810{
811 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
812 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
813 enum pipe pipe = crtc->pipe;
814 int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
815 const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data;
816
817
818
819
820
821
822 intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0);
823 intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe),
824 PRE_CSC_GAMC_AUTO_INCREMENT);
825
826 for (i = 0; i < lut_size; i++) {
827
828
829
830
831
832
833
834
835
836
837
838
839
840 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe),
841 lut[i].green);
842 }
843
844
845 while (i++ < 35)
846 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16);
847
848 intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0);
849}
850
851static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_state)
852{
853 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
854 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
855 enum pipe pipe = crtc->pipe;
856 int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
857
858
859
860
861
862
863 intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0);
864 intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe),
865 PRE_CSC_GAMC_AUTO_INCREMENT);
866
867 for (i = 0; i < lut_size; i++) {
868 u32 v = (i << 16) / (lut_size - 1);
869
870 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), v);
871 }
872
873
874 while (i++ < 35)
875 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16);
876
877 intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0);
878}
879
880static void glk_load_luts(const struct intel_crtc_state *crtc_state)
881{
882 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
883 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
884
885
886
887
888
889
890
891
892
893 if (crtc_state->hw.degamma_lut)
894 glk_load_degamma_lut(crtc_state);
895 else
896 glk_load_degamma_lut_linear(crtc_state);
897
898 switch (crtc_state->gamma_mode) {
899 case GAMMA_MODE_MODE_8BIT:
900 ilk_load_lut_8(crtc, gamma_lut);
901 break;
902 case GAMMA_MODE_MODE_10BIT:
903 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
904 ivb_load_lut_ext_max(crtc_state);
905 break;
906 default:
907 MISSING_CASE(crtc_state->gamma_mode);
908 break;
909 }
910}
911
912
913static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color)
914{
915 return (color->red >> 6) << 20 | (color->green >> 6) << 10 |
916 (color->blue >> 6);
917}
918
919
920static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
921{
922 return (color->red & 0x3f) << 24 | (color->green & 0x3f) << 14 |
923 (color->blue & 0x3f) << 4;
924}
925
926static void
927icl_load_gcmax(const struct intel_crtc_state *crtc_state,
928 const struct drm_color_lut *color)
929{
930 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
931 enum pipe pipe = crtc->pipe;
932
933
934 intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), color->red);
935 intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), color->green);
936 intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), color->blue);
937}
938
939static void
940icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
941{
942 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
943 const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
944 const struct drm_color_lut *lut = blob->data;
945 enum pipe pipe = crtc->pipe;
946 int i;
947
948
949
950
951
952
953
954
955 intel_dsb_reg_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe),
956 PAL_PREC_AUTO_INCREMENT);
957
958 for (i = 0; i < 9; i++) {
959 const struct drm_color_lut *entry = &lut[i];
960
961 intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_MULTI_SEG_DATA(pipe),
962 ilk_lut_12p4_ldw(entry));
963 intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_MULTI_SEG_DATA(pipe),
964 ilk_lut_12p4_udw(entry));
965 }
966}
967
968static void
969icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
970{
971 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
972 const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
973 const struct drm_color_lut *lut = blob->data;
974 const struct drm_color_lut *entry;
975 enum pipe pipe = crtc->pipe;
976 int i;
977
978
979
980
981
982
983
984
985
986
987
988 intel_dsb_reg_write(crtc_state, PREC_PAL_INDEX(pipe),
989 PAL_PREC_AUTO_INCREMENT);
990 for (i = 1; i < 257; i++) {
991 entry = &lut[i * 8];
992 intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe),
993 ilk_lut_12p4_ldw(entry));
994 intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe),
995 ilk_lut_12p4_udw(entry));
996 }
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010 for (i = 0; i < 256; i++) {
1011 entry = &lut[i * 8 * 128];
1012 intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe),
1013 ilk_lut_12p4_ldw(entry));
1014 intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe),
1015 ilk_lut_12p4_udw(entry));
1016 }
1017
1018
1019 entry = &lut[256 * 8 * 128];
1020 icl_load_gcmax(crtc_state, entry);
1021 ivb_load_lut_ext_max(crtc_state);
1022}
1023
1024static void icl_load_luts(const struct intel_crtc_state *crtc_state)
1025{
1026 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
1027 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1028
1029 if (crtc_state->hw.degamma_lut)
1030 glk_load_degamma_lut(crtc_state);
1031
1032 switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
1033 case GAMMA_MODE_MODE_8BIT:
1034 ilk_load_lut_8(crtc, gamma_lut);
1035 break;
1036 case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
1037 icl_program_gamma_superfine_segment(crtc_state);
1038 icl_program_gamma_multi_segment(crtc_state);
1039 break;
1040 case GAMMA_MODE_MODE_10BIT:
1041 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
1042 ivb_load_lut_ext_max(crtc_state);
1043 break;
1044 default:
1045 MISSING_CASE(crtc_state->gamma_mode);
1046 break;
1047 }
1048
1049 intel_dsb_commit(crtc_state);
1050}
1051
1052static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color)
1053{
1054 return drm_color_lut_extract(color->green, 14) << 16 |
1055 drm_color_lut_extract(color->blue, 14);
1056}
1057
1058static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color)
1059{
1060 return drm_color_lut_extract(color->red, 14);
1061}
1062
1063static void chv_load_cgm_degamma(struct intel_crtc *crtc,
1064 const struct drm_property_blob *blob)
1065{
1066 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1067 const struct drm_color_lut *lut = blob->data;
1068 int i, lut_size = drm_color_lut_size(blob);
1069 enum pipe pipe = crtc->pipe;
1070
1071 for (i = 0; i < lut_size; i++) {
1072 intel_de_write(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 0),
1073 chv_cgm_degamma_ldw(&lut[i]));
1074 intel_de_write(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 1),
1075 chv_cgm_degamma_udw(&lut[i]));
1076 }
1077}
1078
1079static u32 chv_cgm_gamma_ldw(const struct drm_color_lut *color)
1080{
1081 return drm_color_lut_extract(color->green, 10) << 16 |
1082 drm_color_lut_extract(color->blue, 10);
1083}
1084
1085static u32 chv_cgm_gamma_udw(const struct drm_color_lut *color)
1086{
1087 return drm_color_lut_extract(color->red, 10);
1088}
1089
1090static void chv_cgm_gamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
1091{
1092 entry->green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_MASK, ldw), 10);
1093 entry->blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_MASK, ldw), 10);
1094 entry->red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_MASK, udw), 10);
1095}
1096
1097static void chv_load_cgm_gamma(struct intel_crtc *crtc,
1098 const struct drm_property_blob *blob)
1099{
1100 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1101 const struct drm_color_lut *lut = blob->data;
1102 int i, lut_size = drm_color_lut_size(blob);
1103 enum pipe pipe = crtc->pipe;
1104
1105 for (i = 0; i < lut_size; i++) {
1106 intel_de_write(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0),
1107 chv_cgm_gamma_ldw(&lut[i]));
1108 intel_de_write(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1),
1109 chv_cgm_gamma_udw(&lut[i]));
1110 }
1111}
1112
1113static void chv_load_luts(const struct intel_crtc_state *crtc_state)
1114{
1115 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1116 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1117 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
1118 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
1119 const struct drm_property_blob *ctm = crtc_state->hw.ctm;
1120
1121 if (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC)
1122 chv_load_cgm_csc(crtc, ctm);
1123
1124 if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA)
1125 chv_load_cgm_degamma(crtc, degamma_lut);
1126
1127 if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
1128 chv_load_cgm_gamma(crtc, gamma_lut);
1129 else
1130 i965_load_luts(crtc_state);
1131
1132 intel_de_write(dev_priv, CGM_PIPE_MODE(crtc->pipe),
1133 crtc_state->cgm_mode);
1134}
1135
1136void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
1137{
1138 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1139
1140 dev_priv->display.load_luts(crtc_state);
1141}
1142
1143void intel_color_commit(const struct intel_crtc_state *crtc_state)
1144{
1145 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1146
1147 dev_priv->display.color_commit(crtc_state);
1148}
1149
1150static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
1151{
1152 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1153 struct intel_atomic_state *state =
1154 to_intel_atomic_state(new_crtc_state->uapi.state);
1155 const struct intel_crtc_state *old_crtc_state =
1156 intel_atomic_get_old_crtc_state(state, crtc);
1157
1158 return !old_crtc_state->hw.gamma_lut &&
1159 !old_crtc_state->hw.degamma_lut;
1160}
1161
1162static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
1163{
1164 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1165 struct intel_atomic_state *state =
1166 to_intel_atomic_state(new_crtc_state->uapi.state);
1167 const struct intel_crtc_state *old_crtc_state =
1168 intel_atomic_get_old_crtc_state(state, crtc);
1169
1170
1171
1172
1173
1174
1175 if (old_crtc_state->cgm_mode || new_crtc_state->cgm_mode)
1176 return false;
1177
1178 return !old_crtc_state->hw.gamma_lut;
1179}
1180
1181static bool glk_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
1182{
1183 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1184 struct intel_atomic_state *state =
1185 to_intel_atomic_state(new_crtc_state->uapi.state);
1186 const struct intel_crtc_state *old_crtc_state =
1187 intel_atomic_get_old_crtc_state(state, crtc);
1188
1189
1190
1191
1192
1193
1194
1195 return !old_crtc_state->csc_enable &&
1196 !old_crtc_state->hw.gamma_lut;
1197}
1198
1199int intel_color_check(struct intel_crtc_state *crtc_state)
1200{
1201 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1202
1203 return dev_priv->display.color_check(crtc_state);
1204}
1205
1206void intel_color_get_config(struct intel_crtc_state *crtc_state)
1207{
1208 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1209
1210 if (dev_priv->display.read_luts)
1211 dev_priv->display.read_luts(crtc_state);
1212}
1213
1214static bool need_plane_update(struct intel_plane *plane,
1215 const struct intel_crtc_state *crtc_state)
1216{
1217 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1218
1219
1220
1221
1222
1223
1224 return crtc_state->active_planes & BIT(plane->id) ||
1225 (DISPLAY_VER(dev_priv) < 9 &&
1226 plane->id == PLANE_PRIMARY);
1227}
1228
1229static int
1230intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
1231{
1232 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1233 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1234 struct intel_atomic_state *state =
1235 to_intel_atomic_state(new_crtc_state->uapi.state);
1236 const struct intel_crtc_state *old_crtc_state =
1237 intel_atomic_get_old_crtc_state(state, crtc);
1238 struct intel_plane *plane;
1239
1240 if (!new_crtc_state->hw.active ||
1241 drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi))
1242 return 0;
1243
1244 if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable &&
1245 new_crtc_state->csc_enable == old_crtc_state->csc_enable)
1246 return 0;
1247
1248 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
1249 struct intel_plane_state *plane_state;
1250
1251 if (!need_plane_update(plane, new_crtc_state))
1252 continue;
1253
1254 plane_state = intel_atomic_get_plane_state(state, plane);
1255 if (IS_ERR(plane_state))
1256 return PTR_ERR(plane_state);
1257
1258 new_crtc_state->update_planes |= BIT(plane->id);
1259 }
1260
1261 return 0;
1262}
1263
1264static int check_lut_size(const struct drm_property_blob *lut, int expected)
1265{
1266 int len;
1267
1268 if (!lut)
1269 return 0;
1270
1271 len = drm_color_lut_size(lut);
1272 if (len != expected) {
1273 DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n",
1274 len, expected);
1275 return -EINVAL;
1276 }
1277
1278 return 0;
1279}
1280
1281static int check_luts(const struct intel_crtc_state *crtc_state)
1282{
1283 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1284 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
1285 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
1286 int gamma_length, degamma_length;
1287 u32 gamma_tests, degamma_tests;
1288
1289
1290 if (crtc_state_is_legacy_gamma(crtc_state))
1291 return 0;
1292
1293
1294 if (crtc_state->c8_planes) {
1295 drm_dbg_kms(&dev_priv->drm,
1296 "C8 pixelformat requires the legacy LUT\n");
1297 return -EINVAL;
1298 }
1299
1300 degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
1301 gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1302 degamma_tests = INTEL_INFO(dev_priv)->color.degamma_lut_tests;
1303 gamma_tests = INTEL_INFO(dev_priv)->color.gamma_lut_tests;
1304
1305 if (check_lut_size(degamma_lut, degamma_length) ||
1306 check_lut_size(gamma_lut, gamma_length))
1307 return -EINVAL;
1308
1309 if (drm_color_lut_check(degamma_lut, degamma_tests) ||
1310 drm_color_lut_check(gamma_lut, gamma_tests))
1311 return -EINVAL;
1312
1313 return 0;
1314}
1315
1316static u32 i9xx_gamma_mode(struct intel_crtc_state *crtc_state)
1317{
1318 if (!crtc_state->gamma_enable ||
1319 crtc_state_is_legacy_gamma(crtc_state))
1320 return GAMMA_MODE_MODE_8BIT;
1321 else
1322 return GAMMA_MODE_MODE_10BIT;
1323}
1324
1325static int i9xx_color_check(struct intel_crtc_state *crtc_state)
1326{
1327 int ret;
1328
1329 ret = check_luts(crtc_state);
1330 if (ret)
1331 return ret;
1332
1333 crtc_state->gamma_enable =
1334 crtc_state->hw.gamma_lut &&
1335 !crtc_state->c8_planes;
1336
1337 crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state);
1338
1339 ret = intel_color_add_affected_planes(crtc_state);
1340 if (ret)
1341 return ret;
1342
1343 crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
1344
1345 return 0;
1346}
1347
1348static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state)
1349{
1350 u32 cgm_mode = 0;
1351
1352 if (crtc_state_is_legacy_gamma(crtc_state))
1353 return 0;
1354
1355 if (crtc_state->hw.degamma_lut)
1356 cgm_mode |= CGM_PIPE_MODE_DEGAMMA;
1357 if (crtc_state->hw.ctm)
1358 cgm_mode |= CGM_PIPE_MODE_CSC;
1359 if (crtc_state->hw.gamma_lut)
1360 cgm_mode |= CGM_PIPE_MODE_GAMMA;
1361
1362 return cgm_mode;
1363}
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373static int chv_color_check(struct intel_crtc_state *crtc_state)
1374{
1375 int ret;
1376
1377 ret = check_luts(crtc_state);
1378 if (ret)
1379 return ret;
1380
1381
1382
1383
1384
1385 crtc_state->gamma_enable =
1386 crtc_state_is_legacy_gamma(crtc_state) &&
1387 !crtc_state->c8_planes;
1388
1389 crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
1390
1391 crtc_state->cgm_mode = chv_cgm_mode(crtc_state);
1392
1393 ret = intel_color_add_affected_planes(crtc_state);
1394 if (ret)
1395 return ret;
1396
1397 crtc_state->preload_luts = chv_can_preload_luts(crtc_state);
1398
1399 return 0;
1400}
1401
1402static u32 ilk_gamma_mode(const struct intel_crtc_state *crtc_state)
1403{
1404 if (!crtc_state->gamma_enable ||
1405 crtc_state_is_legacy_gamma(crtc_state))
1406 return GAMMA_MODE_MODE_8BIT;
1407 else
1408 return GAMMA_MODE_MODE_10BIT;
1409}
1410
1411static u32 ilk_csc_mode(const struct intel_crtc_state *crtc_state)
1412{
1413
1414
1415
1416
1417
1418
1419 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
1420 return CSC_BLACK_SCREEN_OFFSET;
1421
1422 return CSC_MODE_YUV_TO_RGB |
1423 CSC_POSITION_BEFORE_GAMMA;
1424}
1425
1426static int ilk_color_check(struct intel_crtc_state *crtc_state)
1427{
1428 int ret;
1429
1430 ret = check_luts(crtc_state);
1431 if (ret)
1432 return ret;
1433
1434 crtc_state->gamma_enable =
1435 crtc_state->hw.gamma_lut &&
1436 !crtc_state->c8_planes;
1437
1438
1439
1440
1441
1442 crtc_state->csc_enable =
1443 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB;
1444
1445 crtc_state->gamma_mode = ilk_gamma_mode(crtc_state);
1446
1447 crtc_state->csc_mode = ilk_csc_mode(crtc_state);
1448
1449 ret = intel_color_add_affected_planes(crtc_state);
1450 if (ret)
1451 return ret;
1452
1453 crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
1454
1455 return 0;
1456}
1457
1458static u32 ivb_gamma_mode(const struct intel_crtc_state *crtc_state)
1459{
1460 if (!crtc_state->gamma_enable ||
1461 crtc_state_is_legacy_gamma(crtc_state))
1462 return GAMMA_MODE_MODE_8BIT;
1463 else if (crtc_state->hw.gamma_lut &&
1464 crtc_state->hw.degamma_lut)
1465 return GAMMA_MODE_MODE_SPLIT;
1466 else
1467 return GAMMA_MODE_MODE_10BIT;
1468}
1469
1470static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)
1471{
1472 bool limited_color_range = ilk_csc_limited_range(crtc_state);
1473
1474
1475
1476
1477
1478 if (crtc_state->hw.degamma_lut ||
1479 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1480 limited_color_range)
1481 return 0;
1482
1483 return CSC_POSITION_BEFORE_GAMMA;
1484}
1485
1486static int ivb_color_check(struct intel_crtc_state *crtc_state)
1487{
1488 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1489 bool limited_color_range = ilk_csc_limited_range(crtc_state);
1490 int ret;
1491
1492 ret = check_luts(crtc_state);
1493 if (ret)
1494 return ret;
1495
1496 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
1497 crtc_state->hw.ctm) {
1498 drm_dbg_kms(&dev_priv->drm,
1499 "YCBCR and CTM together are not possible\n");
1500 return -EINVAL;
1501 }
1502
1503 crtc_state->gamma_enable =
1504 (crtc_state->hw.gamma_lut ||
1505 crtc_state->hw.degamma_lut) &&
1506 !crtc_state->c8_planes;
1507
1508 crtc_state->csc_enable =
1509 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1510 crtc_state->hw.ctm || limited_color_range;
1511
1512 crtc_state->gamma_mode = ivb_gamma_mode(crtc_state);
1513
1514 crtc_state->csc_mode = ivb_csc_mode(crtc_state);
1515
1516 ret = intel_color_add_affected_planes(crtc_state);
1517 if (ret)
1518 return ret;
1519
1520 crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
1521
1522 return 0;
1523}
1524
1525static u32 glk_gamma_mode(const struct intel_crtc_state *crtc_state)
1526{
1527 if (!crtc_state->gamma_enable ||
1528 crtc_state_is_legacy_gamma(crtc_state))
1529 return GAMMA_MODE_MODE_8BIT;
1530 else
1531 return GAMMA_MODE_MODE_10BIT;
1532}
1533
1534static int glk_color_check(struct intel_crtc_state *crtc_state)
1535{
1536 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1537 int ret;
1538
1539 ret = check_luts(crtc_state);
1540 if (ret)
1541 return ret;
1542
1543 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
1544 crtc_state->hw.ctm) {
1545 drm_dbg_kms(&dev_priv->drm,
1546 "YCBCR and CTM together are not possible\n");
1547 return -EINVAL;
1548 }
1549
1550 crtc_state->gamma_enable =
1551 crtc_state->hw.gamma_lut &&
1552 !crtc_state->c8_planes;
1553
1554
1555 crtc_state->csc_enable =
1556 crtc_state->hw.degamma_lut ||
1557 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1558 crtc_state->hw.ctm || crtc_state->limited_color_range;
1559
1560 crtc_state->gamma_mode = glk_gamma_mode(crtc_state);
1561
1562 crtc_state->csc_mode = 0;
1563
1564 ret = intel_color_add_affected_planes(crtc_state);
1565 if (ret)
1566 return ret;
1567
1568 crtc_state->preload_luts = glk_can_preload_luts(crtc_state);
1569
1570 return 0;
1571}
1572
1573static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state)
1574{
1575 u32 gamma_mode = 0;
1576
1577 if (crtc_state->hw.degamma_lut)
1578 gamma_mode |= PRE_CSC_GAMMA_ENABLE;
1579
1580 if (crtc_state->hw.gamma_lut &&
1581 !crtc_state->c8_planes)
1582 gamma_mode |= POST_CSC_GAMMA_ENABLE;
1583
1584 if (!crtc_state->hw.gamma_lut ||
1585 crtc_state_is_legacy_gamma(crtc_state))
1586 gamma_mode |= GAMMA_MODE_MODE_8BIT;
1587 else
1588 gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED;
1589
1590 return gamma_mode;
1591}
1592
1593static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state)
1594{
1595 u32 csc_mode = 0;
1596
1597 if (crtc_state->hw.ctm)
1598 csc_mode |= ICL_CSC_ENABLE;
1599
1600 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1601 crtc_state->limited_color_range)
1602 csc_mode |= ICL_OUTPUT_CSC_ENABLE;
1603
1604 return csc_mode;
1605}
1606
1607static int icl_color_check(struct intel_crtc_state *crtc_state)
1608{
1609 int ret;
1610
1611 ret = check_luts(crtc_state);
1612 if (ret)
1613 return ret;
1614
1615 crtc_state->gamma_mode = icl_gamma_mode(crtc_state);
1616
1617 crtc_state->csc_mode = icl_csc_mode(crtc_state);
1618
1619 crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
1620
1621 return 0;
1622}
1623
1624static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
1625{
1626 if (!crtc_state->gamma_enable)
1627 return 0;
1628
1629 switch (crtc_state->gamma_mode) {
1630 case GAMMA_MODE_MODE_8BIT:
1631 return 8;
1632 case GAMMA_MODE_MODE_10BIT:
1633 return 16;
1634 default:
1635 MISSING_CASE(crtc_state->gamma_mode);
1636 return 0;
1637 }
1638}
1639
1640static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
1641{
1642 if (!crtc_state->gamma_enable)
1643 return 0;
1644
1645 if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
1646 return 0;
1647
1648 switch (crtc_state->gamma_mode) {
1649 case GAMMA_MODE_MODE_8BIT:
1650 return 8;
1651 case GAMMA_MODE_MODE_10BIT:
1652 return 10;
1653 default:
1654 MISSING_CASE(crtc_state->gamma_mode);
1655 return 0;
1656 }
1657}
1658
1659static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
1660{
1661 if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
1662 return 10;
1663 else
1664 return i9xx_gamma_precision(crtc_state);
1665}
1666
1667static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
1668{
1669 if (!crtc_state->gamma_enable)
1670 return 0;
1671
1672 switch (crtc_state->gamma_mode) {
1673 case GAMMA_MODE_MODE_8BIT:
1674 return 8;
1675 case GAMMA_MODE_MODE_10BIT:
1676 return 10;
1677 default:
1678 MISSING_CASE(crtc_state->gamma_mode);
1679 return 0;
1680 }
1681}
1682
1683static int icl_gamma_precision(const struct intel_crtc_state *crtc_state)
1684{
1685 if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0)
1686 return 0;
1687
1688 switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
1689 case GAMMA_MODE_MODE_8BIT:
1690 return 8;
1691 case GAMMA_MODE_MODE_10BIT:
1692 return 10;
1693 case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
1694 return 16;
1695 default:
1696 MISSING_CASE(crtc_state->gamma_mode);
1697 return 0;
1698 }
1699}
1700
1701int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state)
1702{
1703 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1704 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1705
1706 if (HAS_GMCH(dev_priv)) {
1707 if (IS_CHERRYVIEW(dev_priv))
1708 return chv_gamma_precision(crtc_state);
1709 else
1710 return i9xx_gamma_precision(crtc_state);
1711 } else {
1712 if (DISPLAY_VER(dev_priv) >= 11)
1713 return icl_gamma_precision(crtc_state);
1714 else if (DISPLAY_VER(dev_priv) == 10)
1715 return glk_gamma_precision(crtc_state);
1716 else if (IS_IRONLAKE(dev_priv))
1717 return ilk_gamma_precision(crtc_state);
1718 }
1719
1720 return 0;
1721}
1722
1723static bool err_check(struct drm_color_lut *lut1,
1724 struct drm_color_lut *lut2, u32 err)
1725{
1726 return ((abs((long)lut2->red - lut1->red)) <= err) &&
1727 ((abs((long)lut2->blue - lut1->blue)) <= err) &&
1728 ((abs((long)lut2->green - lut1->green)) <= err);
1729}
1730
1731static bool intel_color_lut_entries_equal(struct drm_color_lut *lut1,
1732 struct drm_color_lut *lut2,
1733 int lut_size, u32 err)
1734{
1735 int i;
1736
1737 for (i = 0; i < lut_size; i++) {
1738 if (!err_check(&lut1[i], &lut2[i], err))
1739 return false;
1740 }
1741
1742 return true;
1743}
1744
1745bool intel_color_lut_equal(struct drm_property_blob *blob1,
1746 struct drm_property_blob *blob2,
1747 u32 gamma_mode, u32 bit_precision)
1748{
1749 struct drm_color_lut *lut1, *lut2;
1750 int lut_size1, lut_size2;
1751 u32 err;
1752
1753 if (!blob1 != !blob2)
1754 return false;
1755
1756 if (!blob1)
1757 return true;
1758
1759 lut_size1 = drm_color_lut_size(blob1);
1760 lut_size2 = drm_color_lut_size(blob2);
1761
1762
1763 if (lut_size1 != lut_size2)
1764 return false;
1765
1766 lut1 = blob1->data;
1767 lut2 = blob2->data;
1768
1769 err = 0xffff >> bit_precision;
1770
1771
1772 switch (gamma_mode & GAMMA_MODE_MODE_MASK) {
1773 case GAMMA_MODE_MODE_8BIT:
1774 case GAMMA_MODE_MODE_10BIT:
1775 if (!intel_color_lut_entries_equal(lut1, lut2,
1776 lut_size2, err))
1777 return false;
1778 break;
1779 case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
1780 if (!intel_color_lut_entries_equal(lut1, lut2,
1781 9, err))
1782 return false;
1783 break;
1784 default:
1785 MISSING_CASE(gamma_mode);
1786 return false;
1787 }
1788
1789 return true;
1790}
1791
1792static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc)
1793{
1794 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1795 enum pipe pipe = crtc->pipe;
1796 struct drm_property_blob *blob;
1797 struct drm_color_lut *lut;
1798 int i;
1799
1800 blob = drm_property_create_blob(&dev_priv->drm,
1801 sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
1802 NULL);
1803 if (IS_ERR(blob))
1804 return NULL;
1805
1806 lut = blob->data;
1807
1808 for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
1809 u32 val = intel_de_read(dev_priv, PALETTE(pipe, i));
1810
1811 i9xx_lut_8_pack(&lut[i], val);
1812 }
1813
1814 return blob;
1815}
1816
1817static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
1818{
1819 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1820
1821 if (!crtc_state->gamma_enable)
1822 return;
1823
1824 crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc);
1825}
1826
1827static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc)
1828{
1829 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1830 int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1831 enum pipe pipe = crtc->pipe;
1832 struct drm_property_blob *blob;
1833 struct drm_color_lut *lut;
1834
1835 blob = drm_property_create_blob(&dev_priv->drm,
1836 sizeof(struct drm_color_lut) * lut_size,
1837 NULL);
1838 if (IS_ERR(blob))
1839 return NULL;
1840
1841 lut = blob->data;
1842
1843 for (i = 0; i < lut_size - 1; i++) {
1844 u32 ldw = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 0));
1845 u32 udw = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 1));
1846
1847 i965_lut_10p6_pack(&lut[i], ldw, udw);
1848 }
1849
1850 lut[i].red = i965_lut_11p6_max_pack(intel_de_read(dev_priv, PIPEGCMAX(pipe, 0)));
1851 lut[i].green = i965_lut_11p6_max_pack(intel_de_read(dev_priv, PIPEGCMAX(pipe, 1)));
1852 lut[i].blue = i965_lut_11p6_max_pack(intel_de_read(dev_priv, PIPEGCMAX(pipe, 2)));
1853
1854 return blob;
1855}
1856
1857static void i965_read_luts(struct intel_crtc_state *crtc_state)
1858{
1859 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1860
1861 if (!crtc_state->gamma_enable)
1862 return;
1863
1864 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
1865 crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc);
1866 else
1867 crtc_state->hw.gamma_lut = i965_read_lut_10p6(crtc);
1868}
1869
1870static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc)
1871{
1872 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1873 int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1874 enum pipe pipe = crtc->pipe;
1875 struct drm_property_blob *blob;
1876 struct drm_color_lut *lut;
1877
1878 blob = drm_property_create_blob(&dev_priv->drm,
1879 sizeof(struct drm_color_lut) * lut_size,
1880 NULL);
1881 if (IS_ERR(blob))
1882 return NULL;
1883
1884 lut = blob->data;
1885
1886 for (i = 0; i < lut_size; i++) {
1887 u32 ldw = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0));
1888 u32 udw = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1));
1889
1890 chv_cgm_gamma_pack(&lut[i], ldw, udw);
1891 }
1892
1893 return blob;
1894}
1895
1896static void chv_read_luts(struct intel_crtc_state *crtc_state)
1897{
1898 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1899
1900 if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
1901 crtc_state->hw.gamma_lut = chv_read_cgm_gamma(crtc);
1902 else
1903 i965_read_luts(crtc_state);
1904}
1905
1906static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc)
1907{
1908 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1909 enum pipe pipe = crtc->pipe;
1910 struct drm_property_blob *blob;
1911 struct drm_color_lut *lut;
1912 int i;
1913
1914 blob = drm_property_create_blob(&dev_priv->drm,
1915 sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
1916 NULL);
1917 if (IS_ERR(blob))
1918 return NULL;
1919
1920 lut = blob->data;
1921
1922 for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
1923 u32 val = intel_de_read(dev_priv, LGC_PALETTE(pipe, i));
1924
1925 i9xx_lut_8_pack(&lut[i], val);
1926 }
1927
1928 return blob;
1929}
1930
1931static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc)
1932{
1933 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1934 int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1935 enum pipe pipe = crtc->pipe;
1936 struct drm_property_blob *blob;
1937 struct drm_color_lut *lut;
1938
1939 blob = drm_property_create_blob(&dev_priv->drm,
1940 sizeof(struct drm_color_lut) * lut_size,
1941 NULL);
1942 if (IS_ERR(blob))
1943 return NULL;
1944
1945 lut = blob->data;
1946
1947 for (i = 0; i < lut_size; i++) {
1948 u32 val = intel_de_read(dev_priv, PREC_PALETTE(pipe, i));
1949
1950 ilk_lut_10_pack(&lut[i], val);
1951 }
1952
1953 return blob;
1954}
1955
1956static void ilk_read_luts(struct intel_crtc_state *crtc_state)
1957{
1958 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1959
1960 if (!crtc_state->gamma_enable)
1961 return;
1962
1963 if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
1964 return;
1965
1966 switch (crtc_state->gamma_mode) {
1967 case GAMMA_MODE_MODE_8BIT:
1968 crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc);
1969 break;
1970 case GAMMA_MODE_MODE_10BIT:
1971 crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc);
1972 break;
1973 default:
1974 MISSING_CASE(crtc_state->gamma_mode);
1975 break;
1976 }
1977}
1978
1979
1980static struct drm_property_blob *bdw_read_lut_10(struct intel_crtc *crtc,
1981 u32 prec_index)
1982{
1983 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1984 int i, hw_lut_size = ivb_lut_10_size(prec_index);
1985 int lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1986 enum pipe pipe = crtc->pipe;
1987 struct drm_property_blob *blob;
1988 struct drm_color_lut *lut;
1989
1990 drm_WARN_ON(&dev_priv->drm, lut_size != hw_lut_size);
1991
1992 blob = drm_property_create_blob(&dev_priv->drm,
1993 sizeof(struct drm_color_lut) * lut_size,
1994 NULL);
1995 if (IS_ERR(blob))
1996 return NULL;
1997
1998 lut = blob->data;
1999
2000 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe),
2001 prec_index | PAL_PREC_AUTO_INCREMENT);
2002
2003 for (i = 0; i < lut_size; i++) {
2004 u32 val = intel_de_read(dev_priv, PREC_PAL_DATA(pipe));
2005
2006 ilk_lut_10_pack(&lut[i], val);
2007 }
2008
2009 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0);
2010
2011 return blob;
2012}
2013
2014static void glk_read_luts(struct intel_crtc_state *crtc_state)
2015{
2016 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2017
2018 if (!crtc_state->gamma_enable)
2019 return;
2020
2021 switch (crtc_state->gamma_mode) {
2022 case GAMMA_MODE_MODE_8BIT:
2023 crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc);
2024 break;
2025 case GAMMA_MODE_MODE_10BIT:
2026 crtc_state->hw.gamma_lut = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0));
2027 break;
2028 default:
2029 MISSING_CASE(crtc_state->gamma_mode);
2030 break;
2031 }
2032}
2033
2034static struct drm_property_blob *
2035icl_read_lut_multi_segment(struct intel_crtc *crtc)
2036{
2037 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2038 int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
2039 enum pipe pipe = crtc->pipe;
2040 struct drm_property_blob *blob;
2041 struct drm_color_lut *lut;
2042
2043 blob = drm_property_create_blob(&dev_priv->drm,
2044 sizeof(struct drm_color_lut) * lut_size,
2045 NULL);
2046 if (IS_ERR(blob))
2047 return NULL;
2048
2049 lut = blob->data;
2050
2051 intel_de_write(dev_priv, PREC_PAL_MULTI_SEG_INDEX(pipe),
2052 PAL_PREC_AUTO_INCREMENT);
2053
2054 for (i = 0; i < 9; i++) {
2055 u32 ldw = intel_de_read(dev_priv, PREC_PAL_MULTI_SEG_DATA(pipe));
2056 u32 udw = intel_de_read(dev_priv, PREC_PAL_MULTI_SEG_DATA(pipe));
2057
2058 icl_lut_multi_seg_pack(&lut[i], ldw, udw);
2059 }
2060
2061 intel_de_write(dev_priv, PREC_PAL_MULTI_SEG_INDEX(pipe), 0);
2062
2063
2064
2065
2066
2067
2068
2069 return blob;
2070}
2071
2072static void icl_read_luts(struct intel_crtc_state *crtc_state)
2073{
2074 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2075
2076 if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0)
2077 return;
2078
2079 switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
2080 case GAMMA_MODE_MODE_8BIT:
2081 crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc);
2082 break;
2083 case GAMMA_MODE_MODE_10BIT:
2084 crtc_state->hw.gamma_lut = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0));
2085 break;
2086 case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
2087 crtc_state->hw.gamma_lut = icl_read_lut_multi_segment(crtc);
2088 break;
2089 default:
2090 MISSING_CASE(crtc_state->gamma_mode);
2091 break;
2092 }
2093}
2094
2095void intel_color_init(struct intel_crtc *crtc)
2096{
2097 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2098 bool has_ctm = INTEL_INFO(dev_priv)->color.degamma_lut_size != 0;
2099
2100 drm_mode_crtc_set_gamma_size(&crtc->base, 256);
2101
2102 if (HAS_GMCH(dev_priv)) {
2103 if (IS_CHERRYVIEW(dev_priv)) {
2104 dev_priv->display.color_check = chv_color_check;
2105 dev_priv->display.color_commit = i9xx_color_commit;
2106 dev_priv->display.load_luts = chv_load_luts;
2107 dev_priv->display.read_luts = chv_read_luts;
2108 } else if (DISPLAY_VER(dev_priv) >= 4) {
2109 dev_priv->display.color_check = i9xx_color_check;
2110 dev_priv->display.color_commit = i9xx_color_commit;
2111 dev_priv->display.load_luts = i965_load_luts;
2112 dev_priv->display.read_luts = i965_read_luts;
2113 } else {
2114 dev_priv->display.color_check = i9xx_color_check;
2115 dev_priv->display.color_commit = i9xx_color_commit;
2116 dev_priv->display.load_luts = i9xx_load_luts;
2117 dev_priv->display.read_luts = i9xx_read_luts;
2118 }
2119 } else {
2120 if (DISPLAY_VER(dev_priv) >= 11)
2121 dev_priv->display.color_check = icl_color_check;
2122 else if (DISPLAY_VER(dev_priv) >= 10)
2123 dev_priv->display.color_check = glk_color_check;
2124 else if (DISPLAY_VER(dev_priv) >= 7)
2125 dev_priv->display.color_check = ivb_color_check;
2126 else
2127 dev_priv->display.color_check = ilk_color_check;
2128
2129 if (DISPLAY_VER(dev_priv) >= 9)
2130 dev_priv->display.color_commit = skl_color_commit;
2131 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2132 dev_priv->display.color_commit = hsw_color_commit;
2133 else
2134 dev_priv->display.color_commit = ilk_color_commit;
2135
2136 if (DISPLAY_VER(dev_priv) >= 11) {
2137 dev_priv->display.load_luts = icl_load_luts;
2138 dev_priv->display.read_luts = icl_read_luts;
2139 } else if (DISPLAY_VER(dev_priv) == 10) {
2140 dev_priv->display.load_luts = glk_load_luts;
2141 dev_priv->display.read_luts = glk_read_luts;
2142 } else if (DISPLAY_VER(dev_priv) >= 8) {
2143 dev_priv->display.load_luts = bdw_load_luts;
2144 } else if (DISPLAY_VER(dev_priv) >= 7) {
2145 dev_priv->display.load_luts = ivb_load_luts;
2146 } else {
2147 dev_priv->display.load_luts = ilk_load_luts;
2148 dev_priv->display.read_luts = ilk_read_luts;
2149 }
2150 }
2151
2152 drm_crtc_enable_color_mgmt(&crtc->base,
2153 INTEL_INFO(dev_priv)->color.degamma_lut_size,
2154 has_ctm,
2155 INTEL_INFO(dev_priv)->color.gamma_lut_size);
2156}
2157