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26#ifndef __INTEL_DISPLAY_TYPES_H__
27#define __INTEL_DISPLAY_TYPES_H__
28
29#include <linux/async.h>
30#include <linux/i2c.h>
31#include <linux/pwm.h>
32#include <linux/sched/clock.h>
33
34#include <drm/drm_atomic.h>
35#include <drm/drm_crtc.h>
36#include <drm/drm_dp_dual_mode_helper.h>
37#include <drm/drm_dp_mst_helper.h>
38#include <drm/drm_encoder.h>
39#include <drm/drm_fb_helper.h>
40#include <drm/drm_fourcc.h>
41#include <drm/drm_probe_helper.h>
42#include <drm/drm_rect.h>
43#include <drm/drm_vblank.h>
44#include <drm/i915_mei_hdcp_interface.h>
45#include <media/cec-notifier.h>
46
47#include "i915_drv.h"
48
49struct drm_printer;
50struct __intel_global_objs_state;
51struct intel_ddi_buf_trans;
52
53
54
55
56
57
58
59enum intel_output_type {
60 INTEL_OUTPUT_UNUSED = 0,
61 INTEL_OUTPUT_ANALOG = 1,
62 INTEL_OUTPUT_DVO = 2,
63 INTEL_OUTPUT_SDVO = 3,
64 INTEL_OUTPUT_LVDS = 4,
65 INTEL_OUTPUT_TVOUT = 5,
66 INTEL_OUTPUT_HDMI = 6,
67 INTEL_OUTPUT_DP = 7,
68 INTEL_OUTPUT_EDP = 8,
69 INTEL_OUTPUT_DSI = 9,
70 INTEL_OUTPUT_DDI = 10,
71 INTEL_OUTPUT_DP_MST = 11,
72};
73
74enum hdmi_force_audio {
75 HDMI_AUDIO_OFF_DVI = -2,
76 HDMI_AUDIO_OFF,
77 HDMI_AUDIO_AUTO,
78 HDMI_AUDIO_ON,
79};
80
81
82enum intel_broadcast_rgb {
83 INTEL_BROADCAST_RGB_AUTO,
84 INTEL_BROADCAST_RGB_FULL,
85 INTEL_BROADCAST_RGB_LIMITED,
86};
87
88struct intel_fb_view {
89
90
91
92
93
94
95
96
97
98 struct i915_ggtt_view gtt;
99
100
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110
111
112 struct i915_color_plane_view {
113 u32 offset;
114 unsigned int x, y;
115
116
117
118
119
120 unsigned int stride;
121 } color_plane[4];
122};
123
124struct intel_framebuffer {
125 struct drm_framebuffer base;
126 struct intel_frontbuffer *frontbuffer;
127
128
129 struct intel_fb_view normal_view;
130 union {
131 struct intel_fb_view rotated_view;
132 struct intel_fb_view remapped_view;
133 };
134
135 struct i915_address_space *dpt_vm;
136};
137
138struct intel_fbdev {
139 struct drm_fb_helper helper;
140 struct intel_framebuffer *fb;
141 struct i915_vma *vma;
142 unsigned long vma_flags;
143 async_cookie_t cookie;
144 int preferred_bpp;
145
146
147 bool hpd_suspended : 1;
148
149
150
151 bool hpd_waiting : 1;
152
153
154 struct mutex hpd_lock;
155};
156
157enum intel_hotplug_state {
158 INTEL_HOTPLUG_UNCHANGED,
159 INTEL_HOTPLUG_CHANGED,
160 INTEL_HOTPLUG_RETRY,
161};
162
163struct intel_encoder {
164 struct drm_encoder base;
165
166 enum intel_output_type type;
167 enum port port;
168 u16 cloneable;
169 u8 pipe_mask;
170 enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder,
171 struct intel_connector *connector);
172 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
173 struct intel_crtc_state *,
174 struct drm_connector_state *);
175 int (*compute_config)(struct intel_encoder *,
176 struct intel_crtc_state *,
177 struct drm_connector_state *);
178 int (*compute_config_late)(struct intel_encoder *,
179 struct intel_crtc_state *,
180 struct drm_connector_state *);
181 void (*update_prepare)(struct intel_atomic_state *,
182 struct intel_encoder *,
183 struct intel_crtc *);
184 void (*pre_pll_enable)(struct intel_atomic_state *,
185 struct intel_encoder *,
186 const struct intel_crtc_state *,
187 const struct drm_connector_state *);
188 void (*pre_enable)(struct intel_atomic_state *,
189 struct intel_encoder *,
190 const struct intel_crtc_state *,
191 const struct drm_connector_state *);
192 void (*enable)(struct intel_atomic_state *,
193 struct intel_encoder *,
194 const struct intel_crtc_state *,
195 const struct drm_connector_state *);
196 void (*update_complete)(struct intel_atomic_state *,
197 struct intel_encoder *,
198 struct intel_crtc *);
199 void (*pre_disable)(struct intel_atomic_state *,
200 struct intel_encoder *,
201 const struct intel_crtc_state *,
202 const struct drm_connector_state *);
203 void (*disable)(struct intel_atomic_state *,
204 struct intel_encoder *,
205 const struct intel_crtc_state *,
206 const struct drm_connector_state *);
207 void (*post_disable)(struct intel_atomic_state *,
208 struct intel_encoder *,
209 const struct intel_crtc_state *,
210 const struct drm_connector_state *);
211 void (*post_pll_disable)(struct intel_atomic_state *,
212 struct intel_encoder *,
213 const struct intel_crtc_state *,
214 const struct drm_connector_state *);
215 void (*update_pipe)(struct intel_atomic_state *,
216 struct intel_encoder *,
217 const struct intel_crtc_state *,
218 const struct drm_connector_state *);
219
220
221
222 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
223
224
225
226
227 void (*get_config)(struct intel_encoder *,
228 struct intel_crtc_state *pipe_config);
229
230
231
232
233
234 void (*sync_state)(struct intel_encoder *encoder,
235 const struct intel_crtc_state *crtc_state);
236
237
238
239
240
241 bool (*initial_fastset_check)(struct intel_encoder *encoder,
242 struct intel_crtc_state *crtc_state);
243
244
245
246
247
248 void (*get_power_domains)(struct intel_encoder *encoder,
249 struct intel_crtc_state *crtc_state);
250
251
252
253
254
255 void (*suspend)(struct intel_encoder *);
256
257
258
259
260 void (*shutdown)(struct intel_encoder *encoder);
261
262
263
264 void (*enable_clock)(struct intel_encoder *encoder,
265 const struct intel_crtc_state *crtc_state);
266 void (*disable_clock)(struct intel_encoder *encoder);
267
268
269
270 bool (*is_clock_enabled)(struct intel_encoder *encoder);
271 const struct intel_ddi_buf_trans *(*get_buf_trans)(struct intel_encoder *encoder,
272 const struct intel_crtc_state *crtc_state,
273 int *n_entries);
274 enum hpd_pin hpd_pin;
275 enum intel_display_power_domain power_domain;
276
277 const struct drm_connector *audio_connector;
278
279
280 const struct intel_bios_encoder_data *devdata;
281};
282
283struct intel_panel_bl_funcs {
284
285 int (*setup)(struct intel_connector *connector, enum pipe pipe);
286 u32 (*get)(struct intel_connector *connector, enum pipe pipe);
287 void (*set)(const struct drm_connector_state *conn_state, u32 level);
288 void (*disable)(const struct drm_connector_state *conn_state, u32 level);
289 void (*enable)(const struct intel_crtc_state *crtc_state,
290 const struct drm_connector_state *conn_state, u32 level);
291 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
292};
293
294struct intel_panel {
295 struct drm_display_mode *fixed_mode;
296 struct drm_display_mode *downclock_mode;
297
298
299 struct {
300 bool present;
301 u32 level;
302 u32 min;
303 u32 max;
304 bool enabled;
305 bool combination_mode;
306 bool active_low_pwm;
307 bool alternate_pwm_increment;
308
309
310 u32 pwm_level_min;
311 u32 pwm_level_max;
312 bool pwm_enabled;
313 bool util_pin_active_low;
314 u8 controller;
315 struct pwm_device *pwm;
316 struct pwm_state pwm_state;
317
318
319 union {
320 struct {
321 struct drm_edp_backlight_info info;
322 } vesa;
323 struct {
324 bool sdr_uses_aux;
325 } intel;
326 } edp;
327
328 struct backlight_device *device;
329
330 const struct intel_panel_bl_funcs *funcs;
331 const struct intel_panel_bl_funcs *pwm_funcs;
332 void (*power)(struct intel_connector *, bool enable);
333 } backlight;
334};
335
336struct intel_digital_port;
337
338enum check_link_response {
339 HDCP_LINK_PROTECTED = 0,
340 HDCP_TOPOLOGY_CHANGE,
341 HDCP_LINK_INTEGRITY_FAILURE,
342 HDCP_REAUTH_REQUEST
343};
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371
372struct intel_hdcp_shim {
373
374 int (*write_an_aksv)(struct intel_digital_port *dig_port, u8 *an);
375
376
377 int (*read_bksv)(struct intel_digital_port *dig_port, u8 *bksv);
378
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383
384
385 int (*read_bstatus)(struct intel_digital_port *dig_port,
386 u8 *bstatus);
387
388
389 int (*repeater_present)(struct intel_digital_port *dig_port,
390 bool *repeater_present);
391
392
393 int (*read_ri_prime)(struct intel_digital_port *dig_port, u8 *ri);
394
395
396 int (*read_ksv_ready)(struct intel_digital_port *dig_port,
397 bool *ksv_ready);
398
399
400 int (*read_ksv_fifo)(struct intel_digital_port *dig_port,
401 int num_downstream, u8 *ksv_fifo);
402
403
404 int (*read_v_prime_part)(struct intel_digital_port *dig_port,
405 int i, u32 *part);
406
407
408 int (*toggle_signalling)(struct intel_digital_port *dig_port,
409 enum transcoder cpu_transcoder,
410 bool enable);
411
412
413 int (*stream_encryption)(struct intel_connector *connector,
414 bool enable);
415
416
417 bool (*check_link)(struct intel_digital_port *dig_port,
418 struct intel_connector *connector);
419
420
421 int (*hdcp_capable)(struct intel_digital_port *dig_port,
422 bool *hdcp_capable);
423
424
425 enum hdcp_wired_protocol protocol;
426
427
428 int (*hdcp_2_2_capable)(struct intel_digital_port *dig_port,
429 bool *capable);
430
431
432 int (*streams_type1_capable)(struct intel_connector *connector,
433 bool *capable);
434
435
436 int (*write_2_2_msg)(struct intel_digital_port *dig_port,
437 void *buf, size_t size);
438
439
440 int (*read_2_2_msg)(struct intel_digital_port *dig_port,
441 u8 msg_id, void *buf, size_t size);
442
443
444
445
446
447
448 int (*config_stream_type)(struct intel_digital_port *dig_port,
449 bool is_repeater, u8 type);
450
451
452 int (*stream_2_2_encryption)(struct intel_connector *connector,
453 bool enable);
454
455
456 int (*check_2_2_link)(struct intel_digital_port *dig_port,
457 struct intel_connector *connector);
458};
459
460struct intel_hdcp {
461 const struct intel_hdcp_shim *shim;
462
463 struct mutex mutex;
464 u64 value;
465 struct delayed_work check_work;
466 struct work_struct prop_work;
467
468
469 bool hdcp_encrypted;
470
471
472
473 bool hdcp2_supported;
474
475
476 bool hdcp2_encrypted;
477
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481
482
483 u8 content_type;
484
485 bool is_paired;
486 bool is_repeater;
487
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491
492
493 u32 seq_num_v;
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500
501 u32 seq_num_m;
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505
506
507 wait_queue_head_t cp_irq_queue;
508 atomic_t cp_irq_count;
509 int cp_irq_count_cached;
510
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514
515
516 enum transcoder cpu_transcoder;
517
518 enum transcoder stream_transcoder;
519};
520
521struct intel_connector {
522 struct drm_connector base;
523
524
525
526 struct intel_encoder *encoder;
527
528
529 u32 acpi_device_id;
530
531
532
533 bool (*get_hw_state)(struct intel_connector *);
534
535
536 struct intel_panel panel;
537
538
539 struct edid *edid;
540 struct edid *detect_edid;
541
542
543 int hotplug_retries;
544
545
546
547 u8 polled;
548
549 struct drm_dp_mst_port *port;
550
551 struct intel_dp *mst_port;
552
553
554 struct work_struct modeset_retry_work;
555
556 struct intel_hdcp hdcp;
557};
558
559struct intel_digital_connector_state {
560 struct drm_connector_state base;
561
562 enum hdmi_force_audio force_audio;
563 int broadcast_rgb;
564};
565
566#define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
567
568struct dpll {
569
570 int n;
571 int m1, m2;
572 int p1, p2;
573
574 int dot;
575 int vco;
576 int m;
577 int p;
578};
579
580struct intel_atomic_state {
581 struct drm_atomic_state base;
582
583 intel_wakeref_t wakeref;
584
585 struct __intel_global_objs_state *global_objs;
586 int num_global_objs;
587
588 bool dpll_set, modeset;
589
590 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
591
592
593
594
595
596 bool skip_intermediate_wm;
597
598 bool rps_interactive;
599
600 struct i915_sw_fence commit_ready;
601
602 struct llist_node freed;
603};
604
605struct intel_plane_state {
606 struct drm_plane_state uapi;
607
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611
612
613 struct {
614 struct drm_crtc *crtc;
615 struct drm_framebuffer *fb;
616
617 u16 alpha;
618 u16 pixel_blend_mode;
619 unsigned int rotation;
620 enum drm_color_encoding color_encoding;
621 enum drm_color_range color_range;
622 enum drm_scaling_filter scaling_filter;
623 } hw;
624
625 struct i915_vma *ggtt_vma;
626 struct i915_vma *dpt_vma;
627 unsigned long flags;
628#define PLANE_HAS_FENCE BIT(0)
629
630 struct intel_fb_view view;
631
632
633 u32 ctl;
634
635
636 u32 color_ctl;
637
638
639 u32 cus_ctl;
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659 int scaler_id;
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668
669 struct intel_plane *planar_linked_plane;
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678
679 u32 planar_slave;
680
681 struct drm_intel_sprite_colorkey ckey;
682
683 struct drm_rect psr2_sel_fetch_area;
684
685
686 u64 ccval;
687};
688
689struct intel_initial_plane_config {
690 struct intel_framebuffer *fb;
691 struct i915_vma *vma;
692 unsigned int tiling;
693 int size;
694 u32 base;
695 u8 rotation;
696};
697
698struct intel_scaler {
699 int in_use;
700 u32 mode;
701};
702
703struct intel_crtc_scaler_state {
704#define SKL_NUM_SCALERS 2
705 struct intel_scaler scalers[SKL_NUM_SCALERS];
706
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723
724#define SKL_CRTC_INDEX 31
725 unsigned scaler_users;
726
727
728 int scaler_id;
729};
730
731
732
733#define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
734
735#define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
736
737
738
739
740
741#define I915_MODE_FLAG_DSI_USE_TE0 (1<<3)
742
743#define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)
744
745#define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
746
747#define I915_MODE_FLAG_VRR (1<<6)
748
749struct intel_wm_level {
750 bool enable;
751 u32 pri_val;
752 u32 spr_val;
753 u32 cur_val;
754 u32 fbc_val;
755};
756
757struct intel_pipe_wm {
758 struct intel_wm_level wm[5];
759 bool fbc_wm_enabled;
760 bool pipe_enabled;
761 bool sprites_enabled;
762 bool sprites_scaled;
763};
764
765struct skl_wm_level {
766 u16 min_ddb_alloc;
767 u16 blocks;
768 u8 lines;
769 bool enable;
770 bool ignore_lines;
771 bool can_sagv;
772};
773
774struct skl_plane_wm {
775 struct skl_wm_level wm[8];
776 struct skl_wm_level uv_wm[8];
777 struct skl_wm_level trans_wm;
778 struct {
779 struct skl_wm_level wm0;
780 struct skl_wm_level trans_wm;
781 } sagv;
782 bool is_planar;
783};
784
785struct skl_pipe_wm {
786 struct skl_plane_wm planes[I915_MAX_PLANES];
787 bool use_sagv_wm;
788};
789
790enum vlv_wm_level {
791 VLV_WM_LEVEL_PM2,
792 VLV_WM_LEVEL_PM5,
793 VLV_WM_LEVEL_DDR_DVFS,
794 NUM_VLV_WM_LEVELS,
795};
796
797struct vlv_wm_state {
798 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
799 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
800 u8 num_levels;
801 bool cxsr;
802};
803
804struct vlv_fifo_state {
805 u16 plane[I915_MAX_PLANES];
806};
807
808enum g4x_wm_level {
809 G4X_WM_LEVEL_NORMAL,
810 G4X_WM_LEVEL_SR,
811 G4X_WM_LEVEL_HPLL,
812 NUM_G4X_WM_LEVELS,
813};
814
815struct g4x_wm_state {
816 struct g4x_pipe_wm wm;
817 struct g4x_sr_wm sr;
818 struct g4x_sr_wm hpll;
819 bool cxsr;
820 bool hpll_en;
821 bool fbc_en;
822};
823
824struct intel_crtc_wm_state {
825 union {
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847
848 struct {
849 struct intel_pipe_wm intermediate;
850 struct intel_pipe_wm optimal;
851 } ilk;
852
853 struct {
854 struct skl_pipe_wm raw;
855
856 struct skl_pipe_wm optimal;
857 struct skl_ddb_entry ddb;
858 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
859 struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
860 } skl;
861
862 struct {
863 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
864 struct vlv_wm_state intermediate;
865 struct vlv_wm_state optimal;
866 struct vlv_fifo_state fifo_state;
867 } vlv;
868
869 struct {
870 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
871 struct g4x_wm_state intermediate;
872 struct g4x_wm_state optimal;
873 } g4x;
874 };
875
876
877
878
879
880
881
882 bool need_postvbl_update;
883};
884
885enum intel_output_format {
886 INTEL_OUTPUT_FORMAT_RGB,
887 INTEL_OUTPUT_FORMAT_YCBCR420,
888 INTEL_OUTPUT_FORMAT_YCBCR444,
889};
890
891struct intel_mpllb_state {
892 u32 clock;
893 u32 ref_control;
894 u32 mpllb_cp;
895 u32 mpllb_div;
896 u32 mpllb_div2;
897 u32 mpllb_fracn1;
898 u32 mpllb_fracn2;
899 u32 mpllb_sscen;
900 u32 mpllb_sscstep;
901};
902
903struct intel_crtc_state {
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912
913
914 struct drm_crtc_state uapi;
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932
933 struct {
934 bool active, enable;
935 struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
936 struct drm_display_mode mode, pipe_mode, adjusted_mode;
937 enum drm_scaling_filter scaling_filter;
938 } hw;
939
940
941
942
943
944
945
946
947
948#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0)
949#define PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE (1<<1)
950 unsigned long quirks;
951
952 unsigned fb_bits;
953 bool update_pipe;
954 bool disable_cxsr;
955 bool update_wm_pre, update_wm_post;
956 bool fifo_changed;
957 bool preload_luts;
958 bool inherited;
959
960
961
962
963 int pipe_src_w, pipe_src_h;
964
965
966
967
968
969 unsigned int pixel_rate;
970
971
972
973 bool has_pch_encoder;
974
975
976 bool has_infoframe;
977
978
979
980
981 enum transcoder cpu_transcoder;
982
983
984
985
986
987 bool limited_color_range;
988
989
990
991
992 unsigned int output_types;
993
994
995 bool has_hdmi_sink;
996
997
998
999 bool has_audio;
1000
1001
1002
1003
1004
1005 bool dither;
1006
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1012
1013 bool dither_force_disable;
1014
1015
1016 bool clock_set;
1017
1018
1019
1020 bool sdvo_tv_clock;
1021
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1024
1025
1026
1027 bool bw_constrained;
1028
1029
1030
1031 struct dpll dpll;
1032
1033
1034 struct intel_shared_dpll *shared_dpll;
1035
1036
1037 union {
1038 struct intel_dpll_hw_state dpll_hw_state;
1039 struct intel_mpllb_state mpllb_state;
1040 };
1041
1042
1043
1044
1045
1046 struct icl_port_dpll {
1047 struct intel_shared_dpll *pll;
1048 struct intel_dpll_hw_state hw_state;
1049 } icl_port_dplls[ICL_PORT_DPLL_COUNT];
1050
1051
1052 struct {
1053 u32 ctrl, div;
1054 } dsi_pll;
1055
1056 int pipe_bpp;
1057 struct intel_link_m_n dp_m_n;
1058
1059
1060 struct intel_link_m_n dp_m2_n2;
1061 bool has_drrs;
1062
1063 bool has_psr;
1064 bool has_psr2;
1065 bool enable_psr2_sel_fetch;
1066 bool req_psr2_sdp_prior_scanline;
1067 u32 dc3co_exitline;
1068 u16 su_y_granularity;
1069
1070
1071
1072
1073
1074
1075 int port_clock;
1076
1077
1078 unsigned pixel_multiplier;
1079
1080
1081 u8 mode_flags;
1082
1083 u8 lane_count;
1084
1085
1086
1087
1088
1089 u8 lane_lat_optim_mask;
1090
1091
1092 u8 min_voltage_level;
1093
1094
1095 struct {
1096 u32 control;
1097 u32 pgm_ratios;
1098 u32 lvds_border_bits;
1099 } gmch_pfit;
1100
1101
1102 struct {
1103 struct drm_rect dst;
1104 bool enabled;
1105 bool force_thru;
1106 } pch_pfit;
1107
1108
1109 int fdi_lanes;
1110 struct intel_link_m_n fdi_m_n;
1111
1112 bool ips_enabled;
1113
1114 bool crc_enabled;
1115
1116 bool enable_fbc;
1117
1118 bool double_wide;
1119
1120 int pbn;
1121
1122 struct intel_crtc_scaler_state scaler_state;
1123
1124
1125 enum pipe hsw_workaround_pipe;
1126
1127
1128 bool disable_lp_wm;
1129
1130 struct intel_crtc_wm_state wm;
1131
1132 int min_cdclk[I915_MAX_PLANES];
1133
1134 u32 data_rate[I915_MAX_PLANES];
1135
1136
1137 u64 plane_data_rate[I915_MAX_PLANES];
1138 u64 uv_plane_data_rate[I915_MAX_PLANES];
1139
1140
1141 u32 gamma_mode;
1142
1143 union {
1144
1145 u32 csc_mode;
1146
1147
1148 u32 cgm_mode;
1149 };
1150
1151
1152 u8 enabled_planes;
1153
1154
1155 u8 active_planes;
1156 u8 nv12_planes;
1157 u8 c8_planes;
1158
1159
1160 u8 update_planes;
1161
1162 struct {
1163 u32 enable;
1164 u32 gcp;
1165 union hdmi_infoframe avi;
1166 union hdmi_infoframe spd;
1167 union hdmi_infoframe hdmi;
1168 union hdmi_infoframe drm;
1169 struct drm_dp_vsc_sdp vsc;
1170 } infoframes;
1171
1172
1173 bool hdmi_scrambling;
1174
1175
1176 bool hdmi_high_tmds_clock_ratio;
1177
1178
1179 enum intel_output_format output_format;
1180
1181
1182 bool gamma_enable;
1183
1184
1185 bool csc_enable;
1186
1187
1188 bool bigjoiner;
1189
1190
1191 bool bigjoiner_slave;
1192
1193
1194 struct intel_crtc *bigjoiner_linked_crtc;
1195
1196
1197 struct {
1198 bool compression_enable;
1199 bool dsc_split;
1200 u16 compressed_bpp;
1201 u8 slice_count;
1202 struct drm_dsc_config config;
1203 } dsc;
1204
1205
1206 u16 linetime;
1207 u16 ips_linetime;
1208
1209
1210 bool fec_enable;
1211
1212
1213 enum transcoder master_transcoder;
1214
1215
1216 u8 sync_mode_slaves_mask;
1217
1218
1219 enum transcoder mst_master_transcoder;
1220
1221
1222 struct intel_dsb *dsb;
1223
1224 u32 psr2_man_track_ctl;
1225
1226
1227 struct {
1228 bool enable;
1229 u8 pipeline_full;
1230 u16 flipline, vmin, vmax, guardband;
1231 } vrr;
1232
1233
1234 struct {
1235 bool enable;
1236 u8 link_count;
1237 u8 pixel_overlap;
1238 } splitter;
1239};
1240
1241enum intel_pipe_crc_source {
1242 INTEL_PIPE_CRC_SOURCE_NONE,
1243 INTEL_PIPE_CRC_SOURCE_PLANE1,
1244 INTEL_PIPE_CRC_SOURCE_PLANE2,
1245 INTEL_PIPE_CRC_SOURCE_PLANE3,
1246 INTEL_PIPE_CRC_SOURCE_PLANE4,
1247 INTEL_PIPE_CRC_SOURCE_PLANE5,
1248 INTEL_PIPE_CRC_SOURCE_PLANE6,
1249 INTEL_PIPE_CRC_SOURCE_PLANE7,
1250 INTEL_PIPE_CRC_SOURCE_PIPE,
1251
1252 INTEL_PIPE_CRC_SOURCE_TV,
1253 INTEL_PIPE_CRC_SOURCE_DP_B,
1254 INTEL_PIPE_CRC_SOURCE_DP_C,
1255 INTEL_PIPE_CRC_SOURCE_DP_D,
1256 INTEL_PIPE_CRC_SOURCE_AUTO,
1257 INTEL_PIPE_CRC_SOURCE_MAX,
1258};
1259
1260#define INTEL_PIPE_CRC_ENTRIES_NR 128
1261struct intel_pipe_crc {
1262 spinlock_t lock;
1263 int skipped;
1264 enum intel_pipe_crc_source source;
1265};
1266
1267struct intel_crtc {
1268 struct drm_crtc base;
1269 enum pipe pipe;
1270
1271
1272
1273
1274
1275 bool active;
1276 u8 plane_ids_mask;
1277
1278
1279 u8 mode_flags;
1280
1281 u16 vmax_vblank_start;
1282
1283 struct intel_display_power_domain_set enabled_power_domains;
1284 struct intel_overlay *overlay;
1285
1286 struct intel_crtc_state *config;
1287
1288
1289 bool cpu_fifo_underrun_disabled;
1290 bool pch_fifo_underrun_disabled;
1291
1292
1293 struct {
1294
1295 union {
1296 struct intel_pipe_wm ilk;
1297 struct vlv_wm_state vlv;
1298 struct g4x_wm_state g4x;
1299 } active;
1300 } wm;
1301
1302 int scanline_offset;
1303
1304 struct {
1305 unsigned start_vbl_count;
1306 ktime_t start_vbl_time;
1307 int min_vbl, max_vbl;
1308 int scanline_start;
1309#ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
1310 struct {
1311 u64 min;
1312 u64 max;
1313 u64 sum;
1314 unsigned int over;
1315 unsigned int times[17];
1316 } vbl;
1317#endif
1318 } debug;
1319
1320
1321 int num_scalers;
1322
1323#ifdef CONFIG_DEBUG_FS
1324 struct intel_pipe_crc pipe_crc;
1325#endif
1326};
1327
1328struct intel_plane {
1329 struct drm_plane base;
1330 enum i9xx_plane_id i9xx_plane;
1331 enum plane_id id;
1332 enum pipe pipe;
1333 bool has_fbc;
1334 bool has_ccs;
1335 bool need_async_flip_disable_wa;
1336 u32 frontbuffer_bit;
1337
1338 struct {
1339 u32 base, cntl, size;
1340 } cursor;
1341
1342
1343
1344
1345
1346
1347
1348 int (*min_width)(const struct drm_framebuffer *fb,
1349 int color_plane,
1350 unsigned int rotation);
1351 int (*max_width)(const struct drm_framebuffer *fb,
1352 int color_plane,
1353 unsigned int rotation);
1354 int (*max_height)(const struct drm_framebuffer *fb,
1355 int color_plane,
1356 unsigned int rotation);
1357 unsigned int (*max_stride)(struct intel_plane *plane,
1358 u32 pixel_format, u64 modifier,
1359 unsigned int rotation);
1360 void (*update_plane)(struct intel_plane *plane,
1361 const struct intel_crtc_state *crtc_state,
1362 const struct intel_plane_state *plane_state);
1363 void (*disable_plane)(struct intel_plane *plane,
1364 const struct intel_crtc_state *crtc_state);
1365 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1366 int (*check_plane)(struct intel_crtc_state *crtc_state,
1367 struct intel_plane_state *plane_state);
1368 int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
1369 const struct intel_plane_state *plane_state);
1370 void (*async_flip)(struct intel_plane *plane,
1371 const struct intel_crtc_state *crtc_state,
1372 const struct intel_plane_state *plane_state,
1373 bool async_flip);
1374 void (*enable_flip_done)(struct intel_plane *plane);
1375 void (*disable_flip_done)(struct intel_plane *plane);
1376};
1377
1378struct intel_watermark_params {
1379 u16 fifo_size;
1380 u16 max_wm;
1381 u8 default_wm;
1382 u8 guard_size;
1383 u8 cacheline_size;
1384};
1385
1386struct cxsr_latency {
1387 bool is_desktop : 1;
1388 bool is_ddr3 : 1;
1389 u16 fsb_freq;
1390 u16 mem_freq;
1391 u16 display_sr;
1392 u16 display_hpll_disable;
1393 u16 cursor_sr;
1394 u16 cursor_hpll_disable;
1395};
1396
1397#define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1398#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1399#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi)
1400#define to_intel_connector(x) container_of(x, struct intel_connector, base)
1401#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1402#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1403#define to_intel_plane(x) container_of(x, struct intel_plane, base)
1404#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi)
1405#define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1406
1407struct intel_hdmi {
1408 i915_reg_t hdmi_reg;
1409 int ddc_bus;
1410 struct {
1411 enum drm_dp_dual_mode_type type;
1412 int max_tmds_clock;
1413 } dp_dual_mode;
1414 bool has_hdmi_sink;
1415 bool has_audio;
1416 struct intel_connector *attached_connector;
1417 struct cec_notifier *cec_notifier;
1418};
1419
1420struct intel_dp_mst_encoder;
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435enum link_m_n_set {
1436
1437 M1_N1 = 0,
1438 M2_N2
1439};
1440
1441struct intel_dp_compliance_data {
1442 unsigned long edid;
1443 u8 video_pattern;
1444 u16 hdisplay, vdisplay;
1445 u8 bpc;
1446 struct drm_dp_phy_test_params phytest;
1447};
1448
1449struct intel_dp_compliance {
1450 unsigned long test_type;
1451 struct intel_dp_compliance_data test_data;
1452 bool test_active;
1453 int test_link_rate;
1454 u8 test_lane_count;
1455};
1456
1457struct intel_dp_pcon_frl {
1458 bool is_trained;
1459 int trained_rate_gbps;
1460};
1461
1462struct intel_pps {
1463 int panel_power_up_delay;
1464 int panel_power_down_delay;
1465 int panel_power_cycle_delay;
1466 int backlight_on_delay;
1467 int backlight_off_delay;
1468 struct delayed_work panel_vdd_work;
1469 bool want_panel_vdd;
1470 unsigned long last_power_on;
1471 unsigned long last_backlight_off;
1472 ktime_t panel_power_off_time;
1473 intel_wakeref_t vdd_wakeref;
1474
1475
1476
1477
1478
1479 enum pipe pps_pipe;
1480
1481
1482
1483
1484
1485 enum pipe active_pipe;
1486
1487
1488
1489
1490 bool pps_reset;
1491 struct edp_power_seq pps_delays;
1492};
1493
1494struct intel_psr {
1495
1496 struct mutex lock;
1497
1498#define I915_PSR_DEBUG_MODE_MASK 0x0f
1499#define I915_PSR_DEBUG_DEFAULT 0x00
1500#define I915_PSR_DEBUG_DISABLE 0x01
1501#define I915_PSR_DEBUG_ENABLE 0x02
1502#define I915_PSR_DEBUG_FORCE_PSR1 0x03
1503#define I915_PSR_DEBUG_ENABLE_SEL_FETCH 0x4
1504#define I915_PSR_DEBUG_IRQ 0x10
1505
1506 u32 debug;
1507 bool sink_support;
1508 bool source_support;
1509 bool enabled;
1510 bool paused;
1511 enum pipe pipe;
1512 enum transcoder transcoder;
1513 bool active;
1514 struct work_struct work;
1515 unsigned int busy_frontbuffer_bits;
1516 bool sink_psr2_support;
1517 bool link_standby;
1518 bool colorimetry_support;
1519 bool psr2_enabled;
1520 bool psr2_sel_fetch_enabled;
1521 bool req_psr2_sdp_prior_scanline;
1522 u8 sink_sync_latency;
1523 ktime_t last_entry_attempt;
1524 ktime_t last_exit;
1525 bool sink_not_reliable;
1526 bool irq_aux_error;
1527 u16 su_w_granularity;
1528 u16 su_y_granularity;
1529 u32 dc3co_exitline;
1530 u32 dc3co_exit_delay;
1531 struct delayed_work dc3co_work;
1532 struct drm_dp_vsc_sdp vsc;
1533};
1534
1535struct intel_dp {
1536 i915_reg_t output_reg;
1537 u32 DP;
1538 int link_rate;
1539 u8 lane_count;
1540 u8 sink_count;
1541 bool link_trained;
1542 bool has_hdmi_sink;
1543 bool has_audio;
1544 bool reset_link_params;
1545 bool use_max_params;
1546 u8 dpcd[DP_RECEIVER_CAP_SIZE];
1547 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1548 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1549 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1550 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1551 u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
1552 u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
1553 u8 fec_capable;
1554 u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];
1555
1556 int num_source_rates;
1557 const int *source_rates;
1558
1559 int num_sink_rates;
1560 int sink_rates[DP_MAX_SUPPORTED_RATES];
1561 bool use_rate_select;
1562
1563 int num_common_rates;
1564 int common_rates[DP_MAX_SUPPORTED_RATES];
1565
1566 int max_link_lane_count;
1567
1568 int max_link_rate;
1569 int mso_link_count;
1570 int mso_pixel_overlap;
1571
1572 struct drm_dp_desc desc;
1573 struct drm_dp_aux aux;
1574 u32 aux_busy_last_status;
1575 u8 train_set[4];
1576
1577 struct intel_pps pps;
1578
1579 bool can_mst;
1580 bool is_mst;
1581 int active_mst_links;
1582
1583
1584 struct intel_connector *attached_connector;
1585
1586
1587 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1588 struct drm_dp_mst_topology_mgr mst_mgr;
1589
1590 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1591
1592
1593
1594
1595 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1596 u32 aux_clock_divider);
1597
1598 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1599 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1600
1601
1602 void (*prepare_link_retrain)(struct intel_dp *intel_dp,
1603 const struct intel_crtc_state *crtc_state);
1604 void (*set_link_train)(struct intel_dp *intel_dp,
1605 const struct intel_crtc_state *crtc_state,
1606 u8 dp_train_pat);
1607 void (*set_idle_link_train)(struct intel_dp *intel_dp,
1608 const struct intel_crtc_state *crtc_state);
1609 void (*set_signal_levels)(struct intel_dp *intel_dp,
1610 const struct intel_crtc_state *crtc_state);
1611
1612 u8 (*preemph_max)(struct intel_dp *intel_dp);
1613 u8 (*voltage_max)(struct intel_dp *intel_dp,
1614 const struct intel_crtc_state *crtc_state);
1615
1616
1617 struct intel_dp_compliance compliance;
1618
1619
1620 struct {
1621 int min_tmds_clock, max_tmds_clock;
1622 int max_dotclock;
1623 int pcon_max_frl_bw;
1624 u8 max_bpc;
1625 bool ycbcr_444_to_420;
1626 bool rgb_to_ycbcr;
1627 } dfp;
1628
1629
1630 struct pm_qos_request pm_qos;
1631
1632
1633 bool force_dsc_en;
1634 int force_dsc_bpp;
1635
1636 bool hobl_failed;
1637 bool hobl_active;
1638
1639 struct intel_dp_pcon_frl frl;
1640
1641 struct intel_psr psr;
1642};
1643
1644enum lspcon_vendor {
1645 LSPCON_VENDOR_MCA,
1646 LSPCON_VENDOR_PARADE
1647};
1648
1649struct intel_lspcon {
1650 bool active;
1651 bool hdr_supported;
1652 enum drm_lspcon_mode mode;
1653 enum lspcon_vendor vendor;
1654};
1655
1656struct intel_digital_port {
1657 struct intel_encoder base;
1658 u32 saved_port_bits;
1659 struct intel_dp dp;
1660 struct intel_hdmi hdmi;
1661 struct intel_lspcon lspcon;
1662 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1663 bool release_cl2_override;
1664 u8 max_lanes;
1665
1666 enum aux_ch aux_ch;
1667 enum intel_display_power_domain ddi_io_power_domain;
1668 intel_wakeref_t ddi_io_wakeref;
1669 intel_wakeref_t aux_wakeref;
1670 struct mutex tc_lock;
1671 intel_wakeref_t tc_lock_wakeref;
1672 int tc_link_refcount;
1673 bool tc_legacy_port:1;
1674 char tc_port_name[8];
1675 enum tc_port_mode tc_mode;
1676 enum phy_fia tc_phy_fia;
1677 u8 tc_phy_fia_idx;
1678
1679
1680 struct mutex hdcp_mutex;
1681
1682 unsigned int num_hdcp_streams;
1683
1684 bool hdcp_auth_status;
1685
1686 struct hdcp_port_data hdcp_port_data;
1687
1688 void (*write_infoframe)(struct intel_encoder *encoder,
1689 const struct intel_crtc_state *crtc_state,
1690 unsigned int type,
1691 const void *frame, ssize_t len);
1692 void (*read_infoframe)(struct intel_encoder *encoder,
1693 const struct intel_crtc_state *crtc_state,
1694 unsigned int type,
1695 void *frame, ssize_t len);
1696 void (*set_infoframes)(struct intel_encoder *encoder,
1697 bool enable,
1698 const struct intel_crtc_state *crtc_state,
1699 const struct drm_connector_state *conn_state);
1700 u32 (*infoframes_enabled)(struct intel_encoder *encoder,
1701 const struct intel_crtc_state *pipe_config);
1702 bool (*connected)(struct intel_encoder *encoder);
1703};
1704
1705struct intel_dp_mst_encoder {
1706 struct intel_encoder base;
1707 enum pipe pipe;
1708 struct intel_digital_port *primary;
1709 struct intel_connector *connector;
1710};
1711
1712static inline enum dpio_channel
1713vlv_dig_port_to_channel(struct intel_digital_port *dig_port)
1714{
1715 switch (dig_port->base.port) {
1716 case PORT_B:
1717 case PORT_D:
1718 return DPIO_CH0;
1719 case PORT_C:
1720 return DPIO_CH1;
1721 default:
1722 BUG();
1723 }
1724}
1725
1726static inline enum dpio_phy
1727vlv_dig_port_to_phy(struct intel_digital_port *dig_port)
1728{
1729 switch (dig_port->base.port) {
1730 case PORT_B:
1731 case PORT_C:
1732 return DPIO_PHY0;
1733 case PORT_D:
1734 return DPIO_PHY1;
1735 default:
1736 BUG();
1737 }
1738}
1739
1740static inline enum dpio_channel
1741vlv_pipe_to_channel(enum pipe pipe)
1742{
1743 switch (pipe) {
1744 case PIPE_A:
1745 case PIPE_C:
1746 return DPIO_CH0;
1747 case PIPE_B:
1748 return DPIO_CH1;
1749 default:
1750 BUG();
1751 }
1752}
1753
1754static inline bool intel_pipe_valid(struct drm_i915_private *i915, enum pipe pipe)
1755{
1756 return (pipe >= 0 &&
1757 pipe < ARRAY_SIZE(i915->pipe_to_crtc_mapping) &&
1758 INTEL_INFO(i915)->pipe_mask & BIT(pipe) &&
1759 i915->pipe_to_crtc_mapping[pipe]);
1760}
1761
1762static inline struct intel_crtc *
1763intel_get_first_crtc(struct drm_i915_private *dev_priv)
1764{
1765 return to_intel_crtc(drm_crtc_from_index(&dev_priv->drm, 0));
1766}
1767
1768static inline struct intel_crtc *
1769intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1770{
1771
1772 drm_WARN_ON(&dev_priv->drm,
1773 !(INTEL_INFO(dev_priv)->pipe_mask & BIT(pipe)));
1774 return dev_priv->pipe_to_crtc_mapping[pipe];
1775}
1776
1777static inline struct intel_crtc *
1778intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1779{
1780 return dev_priv->plane_to_crtc_mapping[plane];
1781}
1782
1783struct intel_load_detect_pipe {
1784 struct drm_atomic_state *restore_state;
1785};
1786
1787static inline struct intel_encoder *
1788intel_attached_encoder(struct intel_connector *connector)
1789{
1790 return connector->encoder;
1791}
1792
1793static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1794{
1795 switch (encoder->type) {
1796 case INTEL_OUTPUT_DDI:
1797 case INTEL_OUTPUT_DP:
1798 case INTEL_OUTPUT_EDP:
1799 case INTEL_OUTPUT_HDMI:
1800 return true;
1801 default:
1802 return false;
1803 }
1804}
1805
1806static inline bool intel_encoder_is_mst(struct intel_encoder *encoder)
1807{
1808 return encoder->type == INTEL_OUTPUT_DP_MST;
1809}
1810
1811static inline struct intel_dp_mst_encoder *
1812enc_to_mst(struct intel_encoder *encoder)
1813{
1814 return container_of(&encoder->base, struct intel_dp_mst_encoder,
1815 base.base);
1816}
1817
1818static inline struct intel_digital_port *
1819enc_to_dig_port(struct intel_encoder *encoder)
1820{
1821 struct intel_encoder *intel_encoder = encoder;
1822
1823 if (intel_encoder_is_dig_port(intel_encoder))
1824 return container_of(&encoder->base, struct intel_digital_port,
1825 base.base);
1826 else if (intel_encoder_is_mst(intel_encoder))
1827 return enc_to_mst(encoder)->primary;
1828 else
1829 return NULL;
1830}
1831
1832static inline struct intel_digital_port *
1833intel_attached_dig_port(struct intel_connector *connector)
1834{
1835 return enc_to_dig_port(intel_attached_encoder(connector));
1836}
1837
1838static inline struct intel_hdmi *
1839enc_to_intel_hdmi(struct intel_encoder *encoder)
1840{
1841 return &enc_to_dig_port(encoder)->hdmi;
1842}
1843
1844static inline struct intel_hdmi *
1845intel_attached_hdmi(struct intel_connector *connector)
1846{
1847 return enc_to_intel_hdmi(intel_attached_encoder(connector));
1848}
1849
1850static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder)
1851{
1852 return &enc_to_dig_port(encoder)->dp;
1853}
1854
1855static inline struct intel_dp *intel_attached_dp(struct intel_connector *connector)
1856{
1857 return enc_to_intel_dp(intel_attached_encoder(connector));
1858}
1859
1860static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1861{
1862 switch (encoder->type) {
1863 case INTEL_OUTPUT_DP:
1864 case INTEL_OUTPUT_EDP:
1865 return true;
1866 case INTEL_OUTPUT_DDI:
1867
1868 return i915_mmio_reg_valid(enc_to_intel_dp(encoder)->output_reg);
1869 default:
1870 return false;
1871 }
1872}
1873
1874static inline struct intel_lspcon *
1875enc_to_intel_lspcon(struct intel_encoder *encoder)
1876{
1877 return &enc_to_dig_port(encoder)->lspcon;
1878}
1879
1880static inline struct intel_digital_port *
1881dp_to_dig_port(struct intel_dp *intel_dp)
1882{
1883 return container_of(intel_dp, struct intel_digital_port, dp);
1884}
1885
1886static inline struct intel_lspcon *
1887dp_to_lspcon(struct intel_dp *intel_dp)
1888{
1889 return &dp_to_dig_port(intel_dp)->lspcon;
1890}
1891
1892static inline struct drm_i915_private *
1893dp_to_i915(struct intel_dp *intel_dp)
1894{
1895 return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1896}
1897
1898#define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
1899 (intel_dp)->psr.source_support)
1900
1901static inline bool intel_encoder_can_psr(struct intel_encoder *encoder)
1902{
1903 if (!intel_encoder_is_dp(encoder))
1904 return false;
1905
1906 return CAN_PSR(enc_to_intel_dp(encoder));
1907}
1908
1909static inline struct intel_digital_port *
1910hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1911{
1912 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1913}
1914
1915static inline struct intel_plane_state *
1916intel_atomic_get_plane_state(struct intel_atomic_state *state,
1917 struct intel_plane *plane)
1918{
1919 struct drm_plane_state *ret =
1920 drm_atomic_get_plane_state(&state->base, &plane->base);
1921
1922 if (IS_ERR(ret))
1923 return ERR_CAST(ret);
1924
1925 return to_intel_plane_state(ret);
1926}
1927
1928static inline struct intel_plane_state *
1929intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1930 struct intel_plane *plane)
1931{
1932 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1933 &plane->base));
1934}
1935
1936static inline struct intel_plane_state *
1937intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1938 struct intel_plane *plane)
1939{
1940 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1941 &plane->base));
1942}
1943
1944static inline struct intel_crtc_state *
1945intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1946 struct intel_crtc *crtc)
1947{
1948 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1949 &crtc->base));
1950}
1951
1952static inline struct intel_crtc_state *
1953intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1954 struct intel_crtc *crtc)
1955{
1956 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1957 &crtc->base));
1958}
1959
1960static inline struct intel_digital_connector_state *
1961intel_atomic_get_new_connector_state(struct intel_atomic_state *state,
1962 struct intel_connector *connector)
1963{
1964 return to_intel_digital_connector_state(
1965 drm_atomic_get_new_connector_state(&state->base,
1966 &connector->base));
1967}
1968
1969static inline struct intel_digital_connector_state *
1970intel_atomic_get_old_connector_state(struct intel_atomic_state *state,
1971 struct intel_connector *connector)
1972{
1973 return to_intel_digital_connector_state(
1974 drm_atomic_get_old_connector_state(&state->base,
1975 &connector->base));
1976}
1977
1978
1979static inline bool
1980intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1981 enum intel_output_type type)
1982{
1983 return crtc_state->output_types & (1 << type);
1984}
1985static inline bool
1986intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1987{
1988 return crtc_state->output_types &
1989 ((1 << INTEL_OUTPUT_DP) |
1990 (1 << INTEL_OUTPUT_DP_MST) |
1991 (1 << INTEL_OUTPUT_EDP));
1992}
1993
1994static inline bool
1995intel_crtc_needs_modeset(const struct intel_crtc_state *crtc_state)
1996{
1997 return drm_atomic_crtc_needs_modeset(&crtc_state->uapi);
1998}
1999
2000static inline void
2001intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
2002{
2003 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
2004
2005 drm_crtc_wait_one_vblank(&crtc->base);
2006}
2007
2008static inline void
2009intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe pipe)
2010{
2011 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
2012
2013 if (crtc->active)
2014 intel_wait_for_vblank(dev_priv, pipe);
2015}
2016
2017static inline bool intel_modifier_uses_dpt(struct drm_i915_private *i915, u64 modifier)
2018{
2019 return DISPLAY_VER(i915) >= 13 && modifier != DRM_FORMAT_MOD_LINEAR;
2020}
2021
2022static inline bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
2023{
2024 return fb && intel_modifier_uses_dpt(to_i915(fb->dev), fb->modifier);
2025}
2026
2027static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state)
2028{
2029 return i915_ggtt_offset(plane_state->ggtt_vma);
2030}
2031
2032static inline struct intel_frontbuffer *
2033to_intel_frontbuffer(struct drm_framebuffer *fb)
2034{
2035 return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
2036}
2037
2038static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
2039{
2040 if (dev_priv->params.panel_use_ssc >= 0)
2041 return dev_priv->params.panel_use_ssc != 0;
2042 return dev_priv->vbt.lvds_use_ssc
2043 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
2044}
2045
2046static inline u32 i9xx_dpll_compute_fp(struct dpll *dpll)
2047{
2048 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
2049}
2050
2051static inline u32 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
2052 const struct intel_crtc_state *pipe_config)
2053{
2054 if (HAS_DDI(dev_priv))
2055 return pipe_config->port_clock;
2056 else
2057 return dev_priv->fdi_pll_freq;
2058}
2059
2060static inline bool is_ccs_modifier(u64 modifier)
2061{
2062 return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
2063 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
2064 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
2065 modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2066 modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2067}
2068
2069static inline bool is_gen12_ccs_modifier(u64 modifier)
2070{
2071 return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
2072 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
2073 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
2074}
2075
2076#endif
2077