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24#include "intel_display_types.h"
25#include "intel_dp.h"
26#include "intel_dp_link_training.h"
27
28static void
29intel_dp_dump_link_status(struct drm_device *drm,
30 const u8 link_status[DP_LINK_STATUS_SIZE])
31{
32 drm_dbg_kms(drm,
33 "ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x\n",
34 link_status[0], link_status[1], link_status[2],
35 link_status[3], link_status[4], link_status[5]);
36}
37
38static void intel_dp_reset_lttpr_common_caps(struct intel_dp *intel_dp)
39{
40 memset(intel_dp->lttpr_common_caps, 0, sizeof(intel_dp->lttpr_common_caps));
41}
42
43static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp)
44{
45 intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT -
46 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = 0;
47}
48
49static const char *intel_dp_phy_name(enum drm_dp_phy dp_phy,
50 char *buf, size_t buf_size)
51{
52 if (dp_phy == DP_PHY_DPRX)
53 snprintf(buf, buf_size, "DPRX");
54 else
55 snprintf(buf, buf_size, "LTTPR %d", dp_phy - DP_PHY_LTTPR1 + 1);
56
57 return buf;
58}
59
60static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp,
61 enum drm_dp_phy dp_phy)
62{
63 return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1];
64}
65
66static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
67 enum drm_dp_phy dp_phy)
68{
69 u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
70 char phy_name[10];
71
72 intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name));
73
74 if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dp_phy, phy_caps) < 0) {
75 drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
76 "failed to read the PHY caps for %s\n",
77 phy_name);
78 return;
79 }
80
81 drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
82 "%s PHY capabilities: %*ph\n",
83 phy_name,
84 (int)sizeof(intel_dp->lttpr_phy_caps[0]),
85 phy_caps);
86}
87
88static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp)
89{
90 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
91
92 if (intel_dp_is_edp(intel_dp))
93 return false;
94
95
96
97
98
99 if (DISPLAY_VER(i915) < 10 || IS_GEMINILAKE(i915))
100 return false;
101
102 if (drm_dp_read_lttpr_common_caps(&intel_dp->aux,
103 intel_dp->lttpr_common_caps) < 0)
104 goto reset_caps;
105
106 drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
107 "LTTPR common capabilities: %*ph\n",
108 (int)sizeof(intel_dp->lttpr_common_caps),
109 intel_dp->lttpr_common_caps);
110
111
112 if (intel_dp->lttpr_common_caps[0] < 0x14)
113 goto reset_caps;
114
115 return true;
116
117reset_caps:
118 intel_dp_reset_lttpr_common_caps(intel_dp);
119 return false;
120}
121
122static bool
123intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable)
124{
125 u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT :
126 DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
127
128 return drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) == 1;
129}
130
131static int intel_dp_init_lttpr(struct intel_dp *intel_dp)
132{
133 int lttpr_count;
134 int i;
135
136 if (!intel_dp_read_lttpr_common_caps(intel_dp))
137 return 0;
138
139 lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
140
141
142
143
144
145 if (lttpr_count == 0)
146 return 0;
147
148
149
150
151
152
153 intel_dp_set_lttpr_transparent_mode(intel_dp, true);
154
155
156
157
158
159
160 if (lttpr_count < 0)
161 return 0;
162
163 if (!intel_dp_set_lttpr_transparent_mode(intel_dp, false)) {
164 drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
165 "Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n");
166
167 intel_dp_set_lttpr_transparent_mode(intel_dp, true);
168 intel_dp_reset_lttpr_count(intel_dp);
169
170 return 0;
171 }
172
173 for (i = 0; i < lttpr_count; i++)
174 intel_dp_read_lttpr_phy_caps(intel_dp, DP_PHY_LTTPR(i));
175
176 return lttpr_count;
177}
178
179
180
181
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183
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189
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191
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193
194
195
196
197int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
198{
199 int lttpr_count = intel_dp_init_lttpr(intel_dp);
200
201
202 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) {
203 intel_dp_reset_lttpr_common_caps(intel_dp);
204 return -EIO;
205 }
206
207 return lttpr_count;
208}
209
210static u8 dp_voltage_max(u8 preemph)
211{
212 switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) {
213 case DP_TRAIN_PRE_EMPH_LEVEL_0:
214 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
215 case DP_TRAIN_PRE_EMPH_LEVEL_1:
216 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
217 case DP_TRAIN_PRE_EMPH_LEVEL_2:
218 return DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
219 case DP_TRAIN_PRE_EMPH_LEVEL_3:
220 default:
221 return DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
222 }
223}
224
225static u8 intel_dp_lttpr_voltage_max(struct intel_dp *intel_dp,
226 enum drm_dp_phy dp_phy)
227{
228 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
229
230 if (drm_dp_lttpr_voltage_swing_level_3_supported(phy_caps))
231 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
232 else
233 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
234}
235
236static u8 intel_dp_lttpr_preemph_max(struct intel_dp *intel_dp,
237 enum drm_dp_phy dp_phy)
238{
239 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
240
241 if (drm_dp_lttpr_pre_emphasis_level_3_supported(phy_caps))
242 return DP_TRAIN_PRE_EMPH_LEVEL_3;
243 else
244 return DP_TRAIN_PRE_EMPH_LEVEL_2;
245}
246
247static bool
248intel_dp_phy_is_downstream_of_source(struct intel_dp *intel_dp,
249 enum drm_dp_phy dp_phy)
250{
251 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
252 int lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
253
254 drm_WARN_ON_ONCE(&i915->drm, lttpr_count <= 0 && dp_phy != DP_PHY_DPRX);
255
256 return lttpr_count <= 0 || dp_phy == DP_PHY_LTTPR(lttpr_count - 1);
257}
258
259static u8 intel_dp_phy_voltage_max(struct intel_dp *intel_dp,
260 const struct intel_crtc_state *crtc_state,
261 enum drm_dp_phy dp_phy)
262{
263 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
264 u8 voltage_max;
265
266
267
268
269
270 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
271 voltage_max = intel_dp->voltage_max(intel_dp, crtc_state);
272 else
273 voltage_max = intel_dp_lttpr_voltage_max(intel_dp, dp_phy + 1);
274
275 drm_WARN_ON_ONCE(&i915->drm,
276 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_2 &&
277 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_3);
278
279 return voltage_max;
280}
281
282static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp,
283 enum drm_dp_phy dp_phy)
284{
285 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
286 u8 preemph_max;
287
288
289
290
291
292 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
293 preemph_max = intel_dp->preemph_max(intel_dp);
294 else
295 preemph_max = intel_dp_lttpr_preemph_max(intel_dp, dp_phy + 1);
296
297 drm_WARN_ON_ONCE(&i915->drm,
298 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_2 &&
299 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_3);
300
301 return preemph_max;
302}
303
304void
305intel_dp_get_adjust_train(struct intel_dp *intel_dp,
306 const struct intel_crtc_state *crtc_state,
307 enum drm_dp_phy dp_phy,
308 const u8 link_status[DP_LINK_STATUS_SIZE])
309{
310 u8 v = 0;
311 u8 p = 0;
312 int lane;
313 u8 voltage_max;
314 u8 preemph_max;
315
316 for (lane = 0; lane < crtc_state->lane_count; lane++) {
317 v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane));
318 p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane));
319 }
320
321 preemph_max = intel_dp_phy_preemph_max(intel_dp, dp_phy);
322 if (p >= preemph_max)
323 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
324
325 v = min(v, dp_voltage_max(p));
326
327 voltage_max = intel_dp_phy_voltage_max(intel_dp, crtc_state, dp_phy);
328 if (v >= voltage_max)
329 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
330
331 for (lane = 0; lane < 4; lane++)
332 intel_dp->train_set[lane] = v | p;
333}
334
335static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp,
336 enum drm_dp_phy dp_phy)
337{
338 return dp_phy == DP_PHY_DPRX ?
339 DP_TRAINING_PATTERN_SET :
340 DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy);
341}
342
343static bool
344intel_dp_set_link_train(struct intel_dp *intel_dp,
345 const struct intel_crtc_state *crtc_state,
346 enum drm_dp_phy dp_phy,
347 u8 dp_train_pat)
348{
349 int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy);
350 u8 buf[sizeof(intel_dp->train_set) + 1];
351 int len;
352
353 intel_dp_program_link_training_pattern(intel_dp, crtc_state,
354 dp_train_pat);
355
356 buf[0] = dp_train_pat;
357
358 memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count);
359 len = crtc_state->lane_count + 1;
360
361 return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len;
362}
363
364static char dp_training_pattern_name(u8 train_pat)
365{
366 switch (train_pat) {
367 case DP_TRAINING_PATTERN_1:
368 case DP_TRAINING_PATTERN_2:
369 case DP_TRAINING_PATTERN_3:
370 return '0' + train_pat;
371 case DP_TRAINING_PATTERN_4:
372 return '4';
373 default:
374 MISSING_CASE(train_pat);
375 return '?';
376 }
377}
378
379void
380intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
381 const struct intel_crtc_state *crtc_state,
382 u8 dp_train_pat)
383{
384 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
385 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
386 u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat);
387
388 if (train_pat != DP_TRAINING_PATTERN_DISABLE)
389 drm_dbg_kms(&dev_priv->drm,
390 "[ENCODER:%d:%s] Using DP training pattern TPS%c\n",
391 encoder->base.base.id, encoder->base.name,
392 dp_training_pattern_name(train_pat));
393
394 intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
395}
396
397void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
398 const struct intel_crtc_state *crtc_state,
399 enum drm_dp_phy dp_phy)
400{
401 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
402 u8 train_set = intel_dp->train_set[0];
403 char phy_name[10];
404
405 drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s, pre-emphasis level %d%s, at %s\n",
406 train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
407 train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "",
408 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
409 DP_TRAIN_PRE_EMPHASIS_SHIFT,
410 train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
411 " (max)" : "",
412 intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
413
414 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
415 intel_dp->set_signal_levels(intel_dp, crtc_state);
416}
417
418static bool
419intel_dp_reset_link_train(struct intel_dp *intel_dp,
420 const struct intel_crtc_state *crtc_state,
421 enum drm_dp_phy dp_phy,
422 u8 dp_train_pat)
423{
424 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
425 intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
426 return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat);
427}
428
429static bool
430intel_dp_update_link_train(struct intel_dp *intel_dp,
431 const struct intel_crtc_state *crtc_state,
432 enum drm_dp_phy dp_phy)
433{
434 int reg = dp_phy == DP_PHY_DPRX ?
435 DP_TRAINING_LANE0_SET :
436 DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy);
437 int ret;
438
439 intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
440
441 ret = drm_dp_dpcd_write(&intel_dp->aux, reg,
442 intel_dp->train_set, crtc_state->lane_count);
443
444 return ret == crtc_state->lane_count;
445}
446
447static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
448 const struct intel_crtc_state *crtc_state)
449{
450 int lane;
451
452 for (lane = 0; lane < crtc_state->lane_count; lane++)
453 if ((intel_dp->train_set[lane] &
454 DP_TRAIN_MAX_SWING_REACHED) == 0)
455 return false;
456
457 return true;
458}
459
460
461
462
463
464static bool
465intel_dp_prepare_link_train(struct intel_dp *intel_dp,
466 const struct intel_crtc_state *crtc_state)
467{
468 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
469 u8 link_config[2];
470 u8 link_bw, rate_select;
471
472 if (intel_dp->prepare_link_retrain)
473 intel_dp->prepare_link_retrain(intel_dp, crtc_state);
474
475 intel_dp_compute_rate(intel_dp, crtc_state->port_clock,
476 &link_bw, &rate_select);
477
478 if (link_bw)
479 drm_dbg_kms(&i915->drm,
480 "Using LINK_BW_SET value %02x\n", link_bw);
481 else
482 drm_dbg_kms(&i915->drm,
483 "Using LINK_RATE_SET value %02x\n", rate_select);
484
485
486 link_config[0] = link_bw;
487 link_config[1] = crtc_state->lane_count;
488 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
489 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
490 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
491
492
493 if (!link_bw)
494 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
495 &rate_select, 1);
496
497 link_config[0] = crtc_state->vrr.enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
498 link_config[1] = DP_SET_ANSI_8B10B;
499 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
500
501 intel_dp->DP |= DP_PORT_EN;
502
503 return true;
504}
505
506static void intel_dp_link_training_clock_recovery_delay(struct intel_dp *intel_dp,
507 enum drm_dp_phy dp_phy)
508{
509 if (dp_phy == DP_PHY_DPRX)
510 drm_dp_link_train_clock_recovery_delay(&intel_dp->aux, intel_dp->dpcd);
511 else
512 drm_dp_lttpr_link_train_clock_recovery_delay();
513}
514
515
516
517
518
519static bool
520intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
521 const struct intel_crtc_state *crtc_state,
522 enum drm_dp_phy dp_phy)
523{
524 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
525 u8 voltage;
526 int voltage_tries, cr_tries, max_cr_tries;
527 bool max_vswing_reached = false;
528
529
530 if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy,
531 DP_TRAINING_PATTERN_1 |
532 DP_LINK_SCRAMBLING_DISABLE)) {
533 drm_err(&i915->drm, "failed to enable link training\n");
534 return false;
535 }
536
537
538
539
540
541
542
543
544
545 if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
546 max_cr_tries = 10;
547 else
548 max_cr_tries = 80;
549
550 voltage_tries = 1;
551 for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
552 u8 link_status[DP_LINK_STATUS_SIZE];
553
554 intel_dp_link_training_clock_recovery_delay(intel_dp, dp_phy);
555
556 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
557 link_status) < 0) {
558 drm_err(&i915->drm, "failed to get link status\n");
559 return false;
560 }
561
562 if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) {
563 drm_dbg_kms(&i915->drm, "clock recovery OK\n");
564 return true;
565 }
566
567 if (voltage_tries == 5) {
568 drm_dbg_kms(&i915->drm,
569 "Same voltage tried 5 times\n");
570 return false;
571 }
572
573 if (max_vswing_reached) {
574 drm_dbg_kms(&i915->drm, "Max Voltage Swing reached\n");
575 return false;
576 }
577
578 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
579
580
581 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy,
582 link_status);
583 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {
584 drm_err(&i915->drm,
585 "failed to update link training\n");
586 return false;
587 }
588
589 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
590 voltage)
591 ++voltage_tries;
592 else
593 voltage_tries = 1;
594
595 if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state))
596 max_vswing_reached = true;
597
598 }
599 drm_err(&i915->drm,
600 "Failed clock recovery %d times, giving up!\n", max_cr_tries);
601 return false;
602}
603
604
605
606
607
608
609static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
610 const struct intel_crtc_state *crtc_state,
611 enum drm_dp_phy dp_phy)
612{
613 bool source_tps3, sink_tps3, source_tps4, sink_tps4;
614
615
616
617
618
619
620
621
622 source_tps4 = intel_dp_source_supports_hbr3(intel_dp);
623 sink_tps4 = dp_phy != DP_PHY_DPRX ||
624 drm_dp_tps4_supported(intel_dp->dpcd);
625 if (source_tps4 && sink_tps4) {
626 return DP_TRAINING_PATTERN_4;
627 } else if (crtc_state->port_clock == 810000) {
628 if (!source_tps4)
629 drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
630 "8.1 Gbps link rate without source HBR3/TPS4 support\n");
631 if (!sink_tps4)
632 drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
633 "8.1 Gbps link rate without sink TPS4 support\n");
634 }
635
636
637
638
639
640 source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
641 sink_tps3 = dp_phy != DP_PHY_DPRX ||
642 drm_dp_tps3_supported(intel_dp->dpcd);
643 if (source_tps3 && sink_tps3) {
644 return DP_TRAINING_PATTERN_3;
645 } else if (crtc_state->port_clock >= 540000) {
646 if (!source_tps3)
647 drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
648 ">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n");
649 if (!sink_tps3)
650 drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
651 ">=5.4/6.48 Gbps link rate without sink TPS3 support\n");
652 }
653
654 return DP_TRAINING_PATTERN_2;
655}
656
657static void
658intel_dp_link_training_channel_equalization_delay(struct intel_dp *intel_dp,
659 enum drm_dp_phy dp_phy)
660{
661 if (dp_phy == DP_PHY_DPRX) {
662 drm_dp_link_train_channel_eq_delay(&intel_dp->aux, intel_dp->dpcd);
663 } else {
664 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
665
666 drm_dp_lttpr_link_train_channel_eq_delay(&intel_dp->aux, phy_caps);
667 }
668}
669
670
671
672
673
674
675static bool
676intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
677 const struct intel_crtc_state *crtc_state,
678 enum drm_dp_phy dp_phy)
679{
680 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
681 int tries;
682 u32 training_pattern;
683 u8 link_status[DP_LINK_STATUS_SIZE];
684 bool channel_eq = false;
685
686 training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy);
687
688 if (training_pattern != DP_TRAINING_PATTERN_4)
689 training_pattern |= DP_LINK_SCRAMBLING_DISABLE;
690
691
692 if (!intel_dp_set_link_train(intel_dp, crtc_state, dp_phy,
693 training_pattern)) {
694 drm_err(&i915->drm, "failed to start channel equalization\n");
695 return false;
696 }
697
698 for (tries = 0; tries < 5; tries++) {
699 intel_dp_link_training_channel_equalization_delay(intel_dp,
700 dp_phy);
701 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
702 link_status) < 0) {
703 drm_err(&i915->drm,
704 "failed to get link status\n");
705 break;
706 }
707
708
709 if (!drm_dp_clock_recovery_ok(link_status,
710 crtc_state->lane_count)) {
711 intel_dp_dump_link_status(&i915->drm, link_status);
712 drm_dbg_kms(&i915->drm,
713 "Clock recovery check failed, cannot "
714 "continue channel equalization\n");
715 break;
716 }
717
718 if (drm_dp_channel_eq_ok(link_status,
719 crtc_state->lane_count)) {
720 channel_eq = true;
721 drm_dbg_kms(&i915->drm, "Channel EQ done. DP Training "
722 "successful\n");
723 break;
724 }
725
726
727 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy,
728 link_status);
729 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {
730 drm_err(&i915->drm,
731 "failed to update link training\n");
732 break;
733 }
734 }
735
736
737 if (tries == 5) {
738 intel_dp_dump_link_status(&i915->drm, link_status);
739 drm_dbg_kms(&i915->drm,
740 "Channel equalization failed 5 times\n");
741 }
742
743 return channel_eq;
744}
745
746static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp,
747 enum drm_dp_phy dp_phy)
748{
749 int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy);
750 u8 val = DP_TRAINING_PATTERN_DISABLE;
751
752 return drm_dp_dpcd_write(&intel_dp->aux, reg, &val, 1) == 1;
753}
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771void intel_dp_stop_link_train(struct intel_dp *intel_dp,
772 const struct intel_crtc_state *crtc_state)
773{
774 intel_dp->link_trained = true;
775
776 intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
777 intel_dp_program_link_training_pattern(intel_dp, crtc_state,
778 DP_TRAINING_PATTERN_DISABLE);
779}
780
781static bool
782intel_dp_link_train_phy(struct intel_dp *intel_dp,
783 const struct intel_crtc_state *crtc_state,
784 enum drm_dp_phy dp_phy)
785{
786 struct intel_connector *intel_connector = intel_dp->attached_connector;
787 char phy_name[10];
788 bool ret = false;
789
790 if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state, dp_phy))
791 goto out;
792
793 if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state, dp_phy))
794 goto out;
795
796 ret = true;
797
798out:
799 drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
800 "[CONNECTOR:%d:%s] Link Training %s at link rate = %d, lane count = %d, at %s\n",
801 intel_connector->base.base.id,
802 intel_connector->base.name,
803 ret ? "passed" : "failed",
804 crtc_state->port_clock, crtc_state->lane_count,
805 intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
806
807 return ret;
808}
809
810static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
811 const struct intel_crtc_state *crtc_state)
812{
813 struct intel_connector *intel_connector = intel_dp->attached_connector;
814
815 if (intel_dp->hobl_active) {
816 drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
817 "Link Training failed with HOBL active, not enabling it from now on");
818 intel_dp->hobl_failed = true;
819 } else if (intel_dp_get_link_train_fallback_values(intel_dp,
820 crtc_state->port_clock,
821 crtc_state->lane_count)) {
822 return;
823 }
824
825
826 schedule_work(&intel_connector->modeset_retry_work);
827}
828
829
830static bool
831intel_dp_link_train_all_phys(struct intel_dp *intel_dp,
832 const struct intel_crtc_state *crtc_state,
833 int lttpr_count)
834{
835 bool ret = true;
836 int i;
837
838 intel_dp_prepare_link_train(intel_dp, crtc_state);
839
840 for (i = lttpr_count - 1; i >= 0; i--) {
841 enum drm_dp_phy dp_phy = DP_PHY_LTTPR(i);
842
843 ret = intel_dp_link_train_phy(intel_dp, crtc_state, dp_phy);
844 intel_dp_disable_dpcd_training_pattern(intel_dp, dp_phy);
845
846 if (!ret)
847 break;
848 }
849
850 if (ret)
851 ret = intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX);
852
853 if (intel_dp->set_idle_link_train)
854 intel_dp->set_idle_link_train(intel_dp, crtc_state);
855
856 return ret;
857}
858
859
860
861
862
863
864
865
866
867
868
869void intel_dp_start_link_train(struct intel_dp *intel_dp,
870 const struct intel_crtc_state *crtc_state)
871{
872
873
874
875
876 int lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp);
877
878 if (lttpr_count < 0)
879
880 lttpr_count = 0;
881
882 if (!intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count))
883 intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
884}
885