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24#include <drm/drm_atomic_helper.h>
25
26#include "display/intel_dp.h"
27
28#include "i915_drv.h"
29#include "intel_atomic.h"
30#include "intel_de.h"
31#include "intel_display_types.h"
32#include "intel_dp_aux.h"
33#include "intel_hdmi.h"
34#include "intel_psr.h"
35#include "intel_snps_phy.h"
36#include "intel_sprite.h"
37#include "skl_universal_plane.h"
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86static bool psr_global_enabled(struct intel_dp *intel_dp)
87{
88 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
89
90 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
91 case I915_PSR_DEBUG_DEFAULT:
92 return i915->params.enable_psr;
93 case I915_PSR_DEBUG_DISABLE:
94 return false;
95 default:
96 return true;
97 }
98}
99
100static bool psr2_global_enabled(struct intel_dp *intel_dp)
101{
102 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
103 case I915_PSR_DEBUG_DISABLE:
104 case I915_PSR_DEBUG_FORCE_PSR1:
105 return false;
106 default:
107 return true;
108 }
109}
110
111static void psr_irq_control(struct intel_dp *intel_dp)
112{
113 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
114 enum transcoder trans_shift;
115 i915_reg_t imr_reg;
116 u32 mask, val;
117
118
119
120
121
122
123 if (DISPLAY_VER(dev_priv) >= 12) {
124 trans_shift = 0;
125 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
126 } else {
127 trans_shift = intel_dp->psr.transcoder;
128 imr_reg = EDP_PSR_IMR;
129 }
130
131 mask = EDP_PSR_ERROR(trans_shift);
132 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ)
133 mask |= EDP_PSR_POST_EXIT(trans_shift) |
134 EDP_PSR_PRE_ENTRY(trans_shift);
135
136
137 val = intel_de_read(dev_priv, imr_reg);
138 val &= ~EDP_PSR_TRANS_MASK(trans_shift);
139 val |= ~mask;
140 intel_de_write(dev_priv, imr_reg, val);
141}
142
143static void psr_event_print(struct drm_i915_private *i915,
144 u32 val, bool psr2_enabled)
145{
146 drm_dbg_kms(&i915->drm, "PSR exit events: 0x%x\n", val);
147 if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE)
148 drm_dbg_kms(&i915->drm, "\tPSR2 watchdog timer expired\n");
149 if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled)
150 drm_dbg_kms(&i915->drm, "\tPSR2 disabled\n");
151 if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN)
152 drm_dbg_kms(&i915->drm, "\tSU dirty FIFO underrun\n");
153 if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN)
154 drm_dbg_kms(&i915->drm, "\tSU CRC FIFO underrun\n");
155 if (val & PSR_EVENT_GRAPHICS_RESET)
156 drm_dbg_kms(&i915->drm, "\tGraphics reset\n");
157 if (val & PSR_EVENT_PCH_INTERRUPT)
158 drm_dbg_kms(&i915->drm, "\tPCH interrupt\n");
159 if (val & PSR_EVENT_MEMORY_UP)
160 drm_dbg_kms(&i915->drm, "\tMemory up\n");
161 if (val & PSR_EVENT_FRONT_BUFFER_MODIFY)
162 drm_dbg_kms(&i915->drm, "\tFront buffer modification\n");
163 if (val & PSR_EVENT_WD_TIMER_EXPIRE)
164 drm_dbg_kms(&i915->drm, "\tPSR watchdog timer expired\n");
165 if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE)
166 drm_dbg_kms(&i915->drm, "\tPIPE registers updated\n");
167 if (val & PSR_EVENT_REGISTER_UPDATE)
168 drm_dbg_kms(&i915->drm, "\tRegister updated\n");
169 if (val & PSR_EVENT_HDCP_ENABLE)
170 drm_dbg_kms(&i915->drm, "\tHDCP enabled\n");
171 if (val & PSR_EVENT_KVMR_SESSION_ENABLE)
172 drm_dbg_kms(&i915->drm, "\tKVMR session enabled\n");
173 if (val & PSR_EVENT_VBI_ENABLE)
174 drm_dbg_kms(&i915->drm, "\tVBI enabled\n");
175 if (val & PSR_EVENT_LPSP_MODE_EXIT)
176 drm_dbg_kms(&i915->drm, "\tLPSP mode exited\n");
177 if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled)
178 drm_dbg_kms(&i915->drm, "\tPSR disabled\n");
179}
180
181void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
182{
183 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
184 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
185 ktime_t time_ns = ktime_get();
186 enum transcoder trans_shift;
187 i915_reg_t imr_reg;
188
189 if (DISPLAY_VER(dev_priv) >= 12) {
190 trans_shift = 0;
191 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
192 } else {
193 trans_shift = intel_dp->psr.transcoder;
194 imr_reg = EDP_PSR_IMR;
195 }
196
197 if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) {
198 intel_dp->psr.last_entry_attempt = time_ns;
199 drm_dbg_kms(&dev_priv->drm,
200 "[transcoder %s] PSR entry attempt in 2 vblanks\n",
201 transcoder_name(cpu_transcoder));
202 }
203
204 if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) {
205 intel_dp->psr.last_exit = time_ns;
206 drm_dbg_kms(&dev_priv->drm,
207 "[transcoder %s] PSR exit completed\n",
208 transcoder_name(cpu_transcoder));
209
210 if (DISPLAY_VER(dev_priv) >= 9) {
211 u32 val = intel_de_read(dev_priv,
212 PSR_EVENT(cpu_transcoder));
213 bool psr2_enabled = intel_dp->psr.psr2_enabled;
214
215 intel_de_write(dev_priv, PSR_EVENT(cpu_transcoder),
216 val);
217 psr_event_print(dev_priv, val, psr2_enabled);
218 }
219 }
220
221 if (psr_iir & EDP_PSR_ERROR(trans_shift)) {
222 u32 val;
223
224 drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n",
225 transcoder_name(cpu_transcoder));
226
227 intel_dp->psr.irq_aux_error = true;
228
229
230
231
232
233
234
235
236
237 val = intel_de_read(dev_priv, imr_reg);
238 val |= EDP_PSR_ERROR(trans_shift);
239 intel_de_write(dev_priv, imr_reg, val);
240
241 schedule_work(&intel_dp->psr.work);
242 }
243}
244
245static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
246{
247 u8 alpm_caps = 0;
248
249 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
250 &alpm_caps) != 1)
251 return false;
252 return alpm_caps & DP_ALPM_CAP;
253}
254
255static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
256{
257 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
258 u8 val = 8;
259
260 if (drm_dp_dpcd_readb(&intel_dp->aux,
261 DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1)
262 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK;
263 else
264 drm_dbg_kms(&i915->drm,
265 "Unable to get sink synchronization latency, assuming 8 frames\n");
266 return val;
267}
268
269static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
270{
271 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
272 ssize_t r;
273 u16 w;
274 u8 y;
275
276
277 if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) {
278
279 w = 4;
280 y = 4;
281 goto exit;
282 }
283
284 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, 2);
285 if (r != 2)
286 drm_dbg_kms(&i915->drm,
287 "Unable to read DP_PSR2_SU_X_GRANULARITY\n");
288
289
290
291
292 if (r != 2 || w == 0)
293 w = 4;
294
295 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1);
296 if (r != 1) {
297 drm_dbg_kms(&i915->drm,
298 "Unable to read DP_PSR2_SU_Y_GRANULARITY\n");
299 y = 4;
300 }
301 if (y == 0)
302 y = 1;
303
304exit:
305 intel_dp->psr.su_w_granularity = w;
306 intel_dp->psr.su_y_granularity = y;
307}
308
309void intel_psr_init_dpcd(struct intel_dp *intel_dp)
310{
311 struct drm_i915_private *dev_priv =
312 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
313
314 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
315 sizeof(intel_dp->psr_dpcd));
316
317 if (!intel_dp->psr_dpcd[0])
318 return;
319 drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n",
320 intel_dp->psr_dpcd[0]);
321
322 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) {
323 drm_dbg_kms(&dev_priv->drm,
324 "PSR support not currently available for this panel\n");
325 return;
326 }
327
328 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
329 drm_dbg_kms(&dev_priv->drm,
330 "Panel lacks power state control, PSR cannot be enabled\n");
331 return;
332 }
333
334 intel_dp->psr.sink_support = true;
335 intel_dp->psr.sink_sync_latency =
336 intel_dp_get_sink_sync_latency(intel_dp);
337
338 if (DISPLAY_VER(dev_priv) >= 9 &&
339 (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
340 bool y_req = intel_dp->psr_dpcd[1] &
341 DP_PSR2_SU_Y_COORDINATE_REQUIRED;
342 bool alpm = intel_dp_get_alpm_status(intel_dp);
343
344
345
346
347
348
349
350
351
352
353
354
355 intel_dp->psr.sink_psr2_support = y_req && alpm;
356 drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n",
357 intel_dp->psr.sink_psr2_support ? "" : "not ");
358
359 if (intel_dp->psr.sink_psr2_support) {
360 intel_dp->psr.colorimetry_support =
361 intel_dp_get_colorimetry_status(intel_dp);
362 intel_dp_get_su_granularity(intel_dp);
363 }
364 }
365}
366
367static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
368{
369 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
370 u32 aux_clock_divider, aux_ctl;
371 int i;
372 static const u8 aux_msg[] = {
373 [0] = DP_AUX_NATIVE_WRITE << 4,
374 [1] = DP_SET_POWER >> 8,
375 [2] = DP_SET_POWER & 0xff,
376 [3] = 1 - 1,
377 [4] = DP_SET_POWER_D0,
378 };
379 u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK |
380 EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK |
381 EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK |
382 EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK;
383
384 BUILD_BUG_ON(sizeof(aux_msg) > 20);
385 for (i = 0; i < sizeof(aux_msg); i += 4)
386 intel_de_write(dev_priv,
387 EDP_PSR_AUX_DATA(intel_dp->psr.transcoder, i >> 2),
388 intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
389
390 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
391
392
393 aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg),
394 aux_clock_divider);
395
396
397 aux_ctl &= psr_aux_mask;
398 intel_de_write(dev_priv, EDP_PSR_AUX_CTL(intel_dp->psr.transcoder),
399 aux_ctl);
400}
401
402static void intel_psr_enable_sink(struct intel_dp *intel_dp)
403{
404 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
405 u8 dpcd_val = DP_PSR_ENABLE;
406
407
408 if (intel_dp->psr.psr2_enabled) {
409 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
410 DP_ALPM_ENABLE |
411 DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
412
413 dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
414 } else {
415 if (intel_dp->psr.link_standby)
416 dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
417
418 if (DISPLAY_VER(dev_priv) >= 8)
419 dpcd_val |= DP_PSR_CRC_VERIFICATION;
420 }
421
422 if (intel_dp->psr.req_psr2_sdp_prior_scanline)
423 dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE;
424
425 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
426
427 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
428}
429
430static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
431{
432 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
433 u32 val = 0;
434
435 if (DISPLAY_VER(dev_priv) >= 11)
436 val |= EDP_PSR_TP4_TIME_0US;
437
438 if (dev_priv->params.psr_safest_params) {
439 val |= EDP_PSR_TP1_TIME_2500us;
440 val |= EDP_PSR_TP2_TP3_TIME_2500us;
441 goto check_tp3_sel;
442 }
443
444 if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
445 val |= EDP_PSR_TP1_TIME_0us;
446 else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
447 val |= EDP_PSR_TP1_TIME_100us;
448 else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
449 val |= EDP_PSR_TP1_TIME_500us;
450 else
451 val |= EDP_PSR_TP1_TIME_2500us;
452
453 if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
454 val |= EDP_PSR_TP2_TP3_TIME_0us;
455 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
456 val |= EDP_PSR_TP2_TP3_TIME_100us;
457 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
458 val |= EDP_PSR_TP2_TP3_TIME_500us;
459 else
460 val |= EDP_PSR_TP2_TP3_TIME_2500us;
461
462check_tp3_sel:
463 if (intel_dp_source_supports_hbr2(intel_dp) &&
464 drm_dp_tps3_supported(intel_dp->dpcd))
465 val |= EDP_PSR_TP1_TP3_SEL;
466 else
467 val |= EDP_PSR_TP1_TP2_SEL;
468
469 return val;
470}
471
472static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
473{
474 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
475 int idle_frames;
476
477
478
479
480 idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
481 idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1);
482
483 if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf))
484 idle_frames = 0xf;
485
486 return idle_frames;
487}
488
489static void hsw_activate_psr1(struct intel_dp *intel_dp)
490{
491 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
492 u32 max_sleep_time = 0x1f;
493 u32 val = EDP_PSR_ENABLE;
494
495 val |= psr_compute_idle_frames(intel_dp) << EDP_PSR_IDLE_FRAME_SHIFT;
496
497 val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
498 if (IS_HASWELL(dev_priv))
499 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
500
501 if (intel_dp->psr.link_standby)
502 val |= EDP_PSR_LINK_STANDBY;
503
504 val |= intel_psr1_get_tp_time(intel_dp);
505
506 if (DISPLAY_VER(dev_priv) >= 8)
507 val |= EDP_PSR_CRC_ENABLE;
508
509 val |= (intel_de_read(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder)) &
510 EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK);
511 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), val);
512}
513
514static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
515{
516 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
517 u32 val = 0;
518
519 if (dev_priv->params.psr_safest_params)
520 return EDP_PSR2_TP2_TIME_2500us;
521
522 if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 &&
523 dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50)
524 val |= EDP_PSR2_TP2_TIME_50us;
525 else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100)
526 val |= EDP_PSR2_TP2_TIME_100us;
527 else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500)
528 val |= EDP_PSR2_TP2_TIME_500us;
529 else
530 val |= EDP_PSR2_TP2_TIME_2500us;
531
532 return val;
533}
534
535static void hsw_activate_psr2(struct intel_dp *intel_dp)
536{
537 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
538 u32 val = EDP_PSR2_ENABLE;
539
540 val |= psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
541
542 if (!IS_ALDERLAKE_P(dev_priv))
543 val |= EDP_SU_TRACK_ENABLE;
544
545 if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12)
546 val |= EDP_Y_COORDINATE_ENABLE;
547
548 val |= EDP_PSR2_FRAME_BEFORE_SU(intel_dp->psr.sink_sync_latency + 1);
549 val |= intel_psr2_get_tp_time(intel_dp);
550
551
552 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
553 static const u8 map[] = {
554 2,
555 1,
556 0,
557 3,
558 6,
559 5,
560 4,
561 7,
562 };
563
564
565
566
567 u32 tmp, lines = 7;
568
569 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
570
571 tmp = map[lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES];
572 tmp = tmp << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT;
573 val |= tmp;
574
575 tmp = map[lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];
576 tmp = tmp << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT;
577 val |= tmp;
578 } else if (DISPLAY_VER(dev_priv) >= 12) {
579
580
581
582
583
584
585
586 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
587 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7);
588 val |= TGL_EDP_PSR2_FAST_WAKE(7);
589 } else if (DISPLAY_VER(dev_priv) >= 9) {
590 val |= EDP_PSR2_IO_BUFFER_WAKE(7);
591 val |= EDP_PSR2_FAST_WAKE(7);
592 }
593
594 if (intel_dp->psr.req_psr2_sdp_prior_scanline)
595 val |= EDP_PSR2_SU_SDP_SCANLINE;
596
597 if (intel_dp->psr.psr2_sel_fetch_enabled) {
598
599 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
600 intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
601 DIS_RAM_BYPASS_PSR2_MAN_TRACK,
602 DIS_RAM_BYPASS_PSR2_MAN_TRACK);
603
604 intel_de_write(dev_priv,
605 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
606 PSR2_MAN_TRK_CTL_ENABLE);
607 } else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
608 intel_de_write(dev_priv,
609 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0);
610 }
611
612
613
614
615
616 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), 0);
617
618 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val);
619}
620
621static bool
622transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans)
623{
624 if (DISPLAY_VER(dev_priv) < 9)
625 return false;
626 else if (DISPLAY_VER(dev_priv) >= 12)
627 return trans == TRANSCODER_A;
628 else
629 return trans == TRANSCODER_EDP;
630}
631
632static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate)
633{
634 if (!cstate || !cstate->hw.active)
635 return 0;
636
637 return DIV_ROUND_UP(1000 * 1000,
638 drm_mode_vrefresh(&cstate->hw.adjusted_mode));
639}
640
641static void psr2_program_idle_frames(struct intel_dp *intel_dp,
642 u32 idle_frames)
643{
644 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
645 u32 val;
646
647 idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT;
648 val = intel_de_read(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder));
649 val &= ~EDP_PSR2_IDLE_FRAME_MASK;
650 val |= idle_frames;
651 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val);
652}
653
654static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp)
655{
656 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
657
658 psr2_program_idle_frames(intel_dp, 0);
659 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO);
660}
661
662static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp)
663{
664 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
665
666 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
667 psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp));
668}
669
670static void tgl_dc3co_disable_work(struct work_struct *work)
671{
672 struct intel_dp *intel_dp =
673 container_of(work, typeof(*intel_dp), psr.dc3co_work.work);
674
675 mutex_lock(&intel_dp->psr.lock);
676
677 if (delayed_work_pending(&intel_dp->psr.dc3co_work))
678 goto unlock;
679
680 tgl_psr2_disable_dc3co(intel_dp);
681unlock:
682 mutex_unlock(&intel_dp->psr.lock);
683}
684
685static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp)
686{
687 if (!intel_dp->psr.dc3co_exitline)
688 return;
689
690 cancel_delayed_work(&intel_dp->psr.dc3co_work);
691
692 tgl_psr2_disable_dc3co(intel_dp);
693}
694
695static bool
696dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp,
697 struct intel_crtc_state *crtc_state)
698{
699 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
700 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
701 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
702 enum port port = dig_port->base.port;
703
704 if (IS_ALDERLAKE_P(dev_priv))
705 return pipe <= PIPE_B && port <= PORT_B;
706 else
707 return pipe == PIPE_A && port == PORT_A;
708}
709
710static void
711tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
712 struct intel_crtc_state *crtc_state)
713{
714 const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay;
715 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
716 u32 exit_scanlines;
717
718
719
720
721
722
723 return;
724
725
726
727
728
729 if (crtc_state->enable_psr2_sel_fetch)
730 return;
731
732 if (!(dev_priv->dmc.allowed_dc_mask & DC_STATE_EN_DC3CO))
733 return;
734
735 if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))
736 return;
737
738
739 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
740 return;
741
742
743
744
745
746 exit_scanlines =
747 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1;
748
749 if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay))
750 return;
751
752 crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines;
753}
754
755static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
756 struct intel_crtc_state *crtc_state)
757{
758 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
759 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
760 struct intel_plane_state *plane_state;
761 struct intel_plane *plane;
762 int i;
763
764 if (!dev_priv->params.enable_psr2_sel_fetch &&
765 intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
766 drm_dbg_kms(&dev_priv->drm,
767 "PSR2 sel fetch not enabled, disabled by parameter\n");
768 return false;
769 }
770
771 if (crtc_state->uapi.async_flip) {
772 drm_dbg_kms(&dev_priv->drm,
773 "PSR2 sel fetch not enabled, async flip enabled\n");
774 return false;
775 }
776
777 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
778 if (plane_state->uapi.rotation != DRM_MODE_ROTATE_0) {
779 drm_dbg_kms(&dev_priv->drm,
780 "PSR2 sel fetch not enabled, plane rotated\n");
781 return false;
782 }
783 }
784
785
786 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
787 drm_dbg_kms(&dev_priv->drm,
788 "PSR2 sel fetch not enabled, missing the implementation of WAs\n");
789 return false;
790 }
791
792 return crtc_state->enable_psr2_sel_fetch = true;
793}
794
795static bool psr2_granularity_check(struct intel_dp *intel_dp,
796 struct intel_crtc_state *crtc_state)
797{
798 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
799 const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
800 const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
801 u16 y_granularity = 0;
802
803
804 if (crtc_hdisplay % intel_dp->psr.su_w_granularity)
805 return false;
806
807 if (crtc_vdisplay % intel_dp->psr.su_y_granularity)
808 return false;
809
810
811 if (!crtc_state->enable_psr2_sel_fetch)
812 return intel_dp->psr.su_y_granularity == 4;
813
814
815
816
817
818
819 if (IS_ALDERLAKE_P(dev_priv))
820 y_granularity = intel_dp->psr.su_y_granularity;
821 else if (intel_dp->psr.su_y_granularity <= 2)
822 y_granularity = 4;
823 else if ((intel_dp->psr.su_y_granularity % 4) == 0)
824 y_granularity = intel_dp->psr.su_y_granularity;
825
826 if (y_granularity == 0 || crtc_vdisplay % y_granularity)
827 return false;
828
829 crtc_state->su_y_granularity = y_granularity;
830 return true;
831}
832
833static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_dp,
834 struct intel_crtc_state *crtc_state)
835{
836 const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode;
837 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
838 u32 hblank_total, hblank_ns, req_ns;
839
840 hblank_total = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start;
841 hblank_ns = div_u64(1000000ULL * hblank_total, adjusted_mode->crtc_clock);
842
843
844 req_ns = (72 / crtc_state->lane_count) * 1000 / (crtc_state->port_clock / 1000);
845
846 if ((hblank_ns - req_ns) > 100)
847 return true;
848
849 if (DISPLAY_VER(dev_priv) < 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b)
850 return false;
851
852 crtc_state->req_psr2_sdp_prior_scanline = true;
853 return true;
854}
855
856static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
857 struct intel_crtc_state *crtc_state)
858{
859 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
860 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
861 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
862 int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
863
864 if (!intel_dp->psr.sink_psr2_support)
865 return false;
866
867
868 if (IS_JSL_EHL(dev_priv)) {
869 drm_dbg_kms(&dev_priv->drm, "PSR2 not supported by phy\n");
870 return false;
871 }
872
873
874 if (IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
875 IS_DG2(dev_priv)) {
876 drm_dbg_kms(&dev_priv->drm, "PSR2 is defeatured for this platform\n");
877 return false;
878 }
879
880
881
882
883
884 if (IS_ALDERLAKE_P(dev_priv)) {
885 drm_dbg_kms(&dev_priv->drm, "PSR2 is missing the implementation of workarounds\n");
886 return false;
887 }
888
889 if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) {
890 drm_dbg_kms(&dev_priv->drm,
891 "PSR2 not supported in transcoder %s\n",
892 transcoder_name(crtc_state->cpu_transcoder));
893 return false;
894 }
895
896 if (!psr2_global_enabled(intel_dp)) {
897 drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n");
898 return false;
899 }
900
901
902
903
904
905
906 if (crtc_state->dsc.compression_enable) {
907 drm_dbg_kms(&dev_priv->drm,
908 "PSR2 cannot be enabled since DSC is enabled\n");
909 return false;
910 }
911
912 if (crtc_state->crc_enabled) {
913 drm_dbg_kms(&dev_priv->drm,
914 "PSR2 not enabled because it would inhibit pipe CRC calculation\n");
915 return false;
916 }
917
918 if (DISPLAY_VER(dev_priv) >= 12) {
919 psr_max_h = 5120;
920 psr_max_v = 3200;
921 max_bpp = 30;
922 } else if (DISPLAY_VER(dev_priv) >= 10) {
923 psr_max_h = 4096;
924 psr_max_v = 2304;
925 max_bpp = 24;
926 } else if (DISPLAY_VER(dev_priv) == 9) {
927 psr_max_h = 3640;
928 psr_max_v = 2304;
929 max_bpp = 24;
930 }
931
932 if (crtc_state->pipe_bpp > max_bpp) {
933 drm_dbg_kms(&dev_priv->drm,
934 "PSR2 not enabled, pipe bpp %d > max supported %d\n",
935 crtc_state->pipe_bpp, max_bpp);
936 return false;
937 }
938
939 if (HAS_PSR2_SEL_FETCH(dev_priv)) {
940 if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
941 !HAS_PSR_HW_TRACKING(dev_priv)) {
942 drm_dbg_kms(&dev_priv->drm,
943 "PSR2 not enabled, selective fetch not valid and no HW tracking available\n");
944 return false;
945 }
946 }
947
948
949 if (!crtc_state->enable_psr2_sel_fetch &&
950 IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
951 drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported this Display stepping\n");
952 return false;
953 }
954
955 if (!psr2_granularity_check(intel_dp, crtc_state)) {
956 drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n");
957 return false;
958 }
959
960 if (!crtc_state->enable_psr2_sel_fetch &&
961 (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) {
962 drm_dbg_kms(&dev_priv->drm,
963 "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n",
964 crtc_hdisplay, crtc_vdisplay,
965 psr_max_h, psr_max_v);
966 return false;
967 }
968
969 if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) {
970 drm_dbg_kms(&dev_priv->drm,
971 "PSR2 not enabled, PSR2 SDP indication do not fit in hblank\n");
972 return false;
973 }
974
975
976 if (crtc_state->vrr.enable &&
977 IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
978 drm_dbg_kms(&dev_priv->drm,
979 "PSR2 not enabled, not compatible with HW stepping + VRR\n");
980 return false;
981 }
982
983 tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
984 return true;
985}
986
987void intel_psr_compute_config(struct intel_dp *intel_dp,
988 struct intel_crtc_state *crtc_state)
989{
990 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
991 const struct drm_display_mode *adjusted_mode =
992 &crtc_state->hw.adjusted_mode;
993 int psr_setup_time;
994
995
996
997
998
999 if (crtc_state->vrr.enable)
1000 return;
1001
1002 if (!CAN_PSR(intel_dp))
1003 return;
1004
1005 if (!psr_global_enabled(intel_dp)) {
1006 drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n");
1007 return;
1008 }
1009
1010 if (intel_dp->psr.sink_not_reliable) {
1011 drm_dbg_kms(&dev_priv->drm,
1012 "PSR sink implementation is not reliable\n");
1013 return;
1014 }
1015
1016 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1017 drm_dbg_kms(&dev_priv->drm,
1018 "PSR condition failed: Interlaced mode enabled\n");
1019 return;
1020 }
1021
1022 psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
1023 if (psr_setup_time < 0) {
1024 drm_dbg_kms(&dev_priv->drm,
1025 "PSR condition failed: Invalid PSR setup time (0x%02x)\n",
1026 intel_dp->psr_dpcd[1]);
1027 return;
1028 }
1029
1030 if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
1031 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
1032 drm_dbg_kms(&dev_priv->drm,
1033 "PSR condition failed: PSR setup time (%d us) too long\n",
1034 psr_setup_time);
1035 return;
1036 }
1037
1038 crtc_state->has_psr = true;
1039 crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
1040 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
1041}
1042
1043void intel_psr_get_config(struct intel_encoder *encoder,
1044 struct intel_crtc_state *pipe_config)
1045{
1046 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1047 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1048 struct intel_dp *intel_dp;
1049 u32 val;
1050
1051 if (!dig_port)
1052 return;
1053
1054 intel_dp = &dig_port->dp;
1055 if (!CAN_PSR(intel_dp))
1056 return;
1057
1058 mutex_lock(&intel_dp->psr.lock);
1059 if (!intel_dp->psr.enabled)
1060 goto unlock;
1061
1062
1063
1064
1065
1066 pipe_config->has_psr = true;
1067 pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;
1068 pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
1069
1070 if (!intel_dp->psr.psr2_enabled)
1071 goto unlock;
1072
1073 if (HAS_PSR2_SEL_FETCH(dev_priv)) {
1074 val = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));
1075 if (val & PSR2_MAN_TRK_CTL_ENABLE)
1076 pipe_config->enable_psr2_sel_fetch = true;
1077 }
1078
1079 if (DISPLAY_VER(dev_priv) >= 12) {
1080 val = intel_de_read(dev_priv, EXITLINE(intel_dp->psr.transcoder));
1081 val &= EXITLINE_MASK;
1082 pipe_config->dc3co_exitline = val;
1083 }
1084unlock:
1085 mutex_unlock(&intel_dp->psr.lock);
1086}
1087
1088static void intel_psr_activate(struct intel_dp *intel_dp)
1089{
1090 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1091 enum transcoder transcoder = intel_dp->psr.transcoder;
1092
1093 if (transcoder_has_psr2(dev_priv, transcoder))
1094 drm_WARN_ON(&dev_priv->drm,
1095 intel_de_read(dev_priv, EDP_PSR2_CTL(transcoder)) & EDP_PSR2_ENABLE);
1096
1097 drm_WARN_ON(&dev_priv->drm,
1098 intel_de_read(dev_priv, EDP_PSR_CTL(transcoder)) & EDP_PSR_ENABLE);
1099 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active);
1100 lockdep_assert_held(&intel_dp->psr.lock);
1101
1102
1103 if (intel_dp->psr.psr2_enabled)
1104 hsw_activate_psr2(intel_dp);
1105 else
1106 hsw_activate_psr1(intel_dp);
1107
1108 intel_dp->psr.active = true;
1109}
1110
1111static void intel_psr_enable_source(struct intel_dp *intel_dp)
1112{
1113 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1114 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
1115 u32 mask;
1116
1117
1118
1119
1120 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1121 hsw_psr_setup_aux(intel_dp);
1122
1123 if (intel_dp->psr.psr2_enabled && DISPLAY_VER(dev_priv) == 9) {
1124 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
1125 u32 chicken = intel_de_read(dev_priv, reg);
1126
1127 chicken |= PSR2_VSC_ENABLE_PROG_HEADER |
1128 PSR2_ADD_VERTICAL_LINE_COUNT;
1129 intel_de_write(dev_priv, reg, chicken);
1130 }
1131
1132
1133
1134
1135
1136
1137
1138 mask = EDP_PSR_DEBUG_MASK_MEMUP |
1139 EDP_PSR_DEBUG_MASK_HPD |
1140 EDP_PSR_DEBUG_MASK_LPSP |
1141 EDP_PSR_DEBUG_MASK_MAX_SLEEP;
1142
1143 if (DISPLAY_VER(dev_priv) < 11)
1144 mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
1145
1146 intel_de_write(dev_priv, EDP_PSR_DEBUG(intel_dp->psr.transcoder),
1147 mask);
1148
1149 psr_irq_control(intel_dp);
1150
1151 if (intel_dp->psr.dc3co_exitline) {
1152 u32 val;
1153
1154
1155
1156
1157
1158 val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder));
1159 val &= ~EXITLINE_MASK;
1160 val |= intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT;
1161 val |= EXITLINE_ENABLE;
1162 intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val);
1163 }
1164
1165 if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv))
1166 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING,
1167 intel_dp->psr.psr2_sel_fetch_enabled ?
1168 IGNORE_PSR2_HW_TRACKING : 0);
1169
1170
1171 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) &&
1172 intel_dp->psr.psr2_enabled)
1173 intel_de_rmw(dev_priv,
1174 TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
1175 TRANS_SET_CONTEXT_LATENCY_MASK,
1176 TRANS_SET_CONTEXT_LATENCY_VALUE(1));
1177}
1178
1179static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
1180{
1181 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1182 u32 val;
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192 if (DISPLAY_VER(dev_priv) >= 12) {
1193 val = intel_de_read(dev_priv,
1194 TRANS_PSR_IIR(intel_dp->psr.transcoder));
1195 val &= EDP_PSR_ERROR(0);
1196 } else {
1197 val = intel_de_read(dev_priv, EDP_PSR_IIR);
1198 val &= EDP_PSR_ERROR(intel_dp->psr.transcoder);
1199 }
1200 if (val) {
1201 intel_dp->psr.sink_not_reliable = true;
1202 drm_dbg_kms(&dev_priv->drm,
1203 "PSR interruption error set, not enabling PSR\n");
1204 return false;
1205 }
1206
1207 return true;
1208}
1209
1210static void intel_psr_enable_locked(struct intel_dp *intel_dp,
1211 const struct intel_crtc_state *crtc_state,
1212 const struct drm_connector_state *conn_state)
1213{
1214 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1215 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1216 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
1217 struct intel_encoder *encoder = &dig_port->base;
1218 u32 val;
1219
1220 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
1221
1222 intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
1223 intel_dp->psr.busy_frontbuffer_bits = 0;
1224 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
1225 intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
1226
1227 val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
1228 intel_dp->psr.dc3co_exit_delay = val;
1229 intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
1230 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
1231 intel_dp->psr.req_psr2_sdp_prior_scanline =
1232 crtc_state->req_psr2_sdp_prior_scanline;
1233
1234 if (!psr_interrupt_error_check(intel_dp))
1235 return;
1236
1237 drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
1238 intel_dp->psr.psr2_enabled ? "2" : "1");
1239 intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
1240 &intel_dp->psr.vsc);
1241 intel_write_dp_vsc_sdp(encoder, crtc_state, &intel_dp->psr.vsc);
1242 intel_snps_phy_update_psr_power_state(dev_priv, phy, true);
1243 intel_psr_enable_sink(intel_dp);
1244 intel_psr_enable_source(intel_dp);
1245 intel_dp->psr.enabled = true;
1246 intel_dp->psr.paused = false;
1247
1248 intel_psr_activate(intel_dp);
1249}
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259void intel_psr_enable(struct intel_dp *intel_dp,
1260 const struct intel_crtc_state *crtc_state,
1261 const struct drm_connector_state *conn_state)
1262{
1263 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1264
1265 if (!CAN_PSR(intel_dp))
1266 return;
1267
1268 if (!crtc_state->has_psr)
1269 return;
1270
1271 drm_WARN_ON(&dev_priv->drm, dev_priv->drrs.dp);
1272
1273 mutex_lock(&intel_dp->psr.lock);
1274 intel_psr_enable_locked(intel_dp, crtc_state, conn_state);
1275 mutex_unlock(&intel_dp->psr.lock);
1276}
1277
1278static void intel_psr_exit(struct intel_dp *intel_dp)
1279{
1280 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1281 u32 val;
1282
1283 if (!intel_dp->psr.active) {
1284 if (transcoder_has_psr2(dev_priv, intel_dp->psr.transcoder)) {
1285 val = intel_de_read(dev_priv,
1286 EDP_PSR2_CTL(intel_dp->psr.transcoder));
1287 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE);
1288 }
1289
1290 val = intel_de_read(dev_priv,
1291 EDP_PSR_CTL(intel_dp->psr.transcoder));
1292 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE);
1293
1294 return;
1295 }
1296
1297 if (intel_dp->psr.psr2_enabled) {
1298 tgl_disallow_dc3co_on_psr2_exit(intel_dp);
1299 val = intel_de_read(dev_priv,
1300 EDP_PSR2_CTL(intel_dp->psr.transcoder));
1301 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE));
1302 val &= ~EDP_PSR2_ENABLE;
1303 intel_de_write(dev_priv,
1304 EDP_PSR2_CTL(intel_dp->psr.transcoder), val);
1305 } else {
1306 val = intel_de_read(dev_priv,
1307 EDP_PSR_CTL(intel_dp->psr.transcoder));
1308 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE));
1309 val &= ~EDP_PSR_ENABLE;
1310 intel_de_write(dev_priv,
1311 EDP_PSR_CTL(intel_dp->psr.transcoder), val);
1312 }
1313 intel_dp->psr.active = false;
1314}
1315
1316static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp)
1317{
1318 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1319 i915_reg_t psr_status;
1320 u32 psr_status_mask;
1321
1322 if (intel_dp->psr.psr2_enabled) {
1323 psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder);
1324 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
1325 } else {
1326 psr_status = EDP_PSR_STATUS(intel_dp->psr.transcoder);
1327 psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
1328 }
1329
1330
1331 if (intel_de_wait_for_clear(dev_priv, psr_status,
1332 psr_status_mask, 2000))
1333 drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n");
1334}
1335
1336static void intel_psr_disable_locked(struct intel_dp *intel_dp)
1337{
1338 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1339 enum phy phy = intel_port_to_phy(dev_priv,
1340 dp_to_dig_port(intel_dp)->base.port);
1341
1342 lockdep_assert_held(&intel_dp->psr.lock);
1343
1344 if (!intel_dp->psr.enabled)
1345 return;
1346
1347 drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
1348 intel_dp->psr.psr2_enabled ? "2" : "1");
1349
1350 intel_psr_exit(intel_dp);
1351 intel_psr_wait_exit_locked(intel_dp);
1352
1353
1354 if (intel_dp->psr.psr2_sel_fetch_enabled &&
1355 IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
1356 intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
1357 DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
1358
1359
1360 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) &&
1361 intel_dp->psr.psr2_enabled)
1362 intel_de_rmw(dev_priv,
1363 TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
1364 TRANS_SET_CONTEXT_LATENCY_MASK, 0);
1365
1366 intel_snps_phy_update_psr_power_state(dev_priv, phy, false);
1367
1368
1369 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
1370
1371 if (intel_dp->psr.psr2_enabled)
1372 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0);
1373
1374 intel_dp->psr.enabled = false;
1375}
1376
1377
1378
1379
1380
1381
1382
1383
1384void intel_psr_disable(struct intel_dp *intel_dp,
1385 const struct intel_crtc_state *old_crtc_state)
1386{
1387 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1388
1389 if (!old_crtc_state->has_psr)
1390 return;
1391
1392 if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(intel_dp)))
1393 return;
1394
1395 mutex_lock(&intel_dp->psr.lock);
1396
1397 intel_psr_disable_locked(intel_dp);
1398
1399 mutex_unlock(&intel_dp->psr.lock);
1400 cancel_work_sync(&intel_dp->psr.work);
1401 cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
1402}
1403
1404
1405
1406
1407
1408
1409
1410void intel_psr_pause(struct intel_dp *intel_dp)
1411{
1412 struct intel_psr *psr = &intel_dp->psr;
1413
1414 if (!CAN_PSR(intel_dp))
1415 return;
1416
1417 mutex_lock(&psr->lock);
1418
1419 if (!psr->enabled) {
1420 mutex_unlock(&psr->lock);
1421 return;
1422 }
1423
1424 intel_psr_exit(intel_dp);
1425 intel_psr_wait_exit_locked(intel_dp);
1426 psr->paused = true;
1427
1428 mutex_unlock(&psr->lock);
1429
1430 cancel_work_sync(&psr->work);
1431 cancel_delayed_work_sync(&psr->dc3co_work);
1432}
1433
1434
1435
1436
1437
1438
1439
1440void intel_psr_resume(struct intel_dp *intel_dp)
1441{
1442 struct intel_psr *psr = &intel_dp->psr;
1443
1444 if (!CAN_PSR(intel_dp))
1445 return;
1446
1447 mutex_lock(&psr->lock);
1448
1449 if (!psr->paused)
1450 goto unlock;
1451
1452 psr->paused = false;
1453 intel_psr_activate(intel_dp);
1454
1455unlock:
1456 mutex_unlock(&psr->lock);
1457}
1458
1459static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
1460{
1461 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1462
1463 if (DISPLAY_VER(dev_priv) >= 9)
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
1474 else
1475
1476
1477
1478
1479 intel_psr_exit(intel_dp);
1480}
1481
1482void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
1483 const struct intel_crtc_state *crtc_state,
1484 const struct intel_plane_state *plane_state,
1485 int color_plane)
1486{
1487 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1488 enum pipe pipe = plane->pipe;
1489 const struct drm_rect *clip;
1490 u32 val, offset;
1491 int ret, x, y;
1492
1493 if (!crtc_state->enable_psr2_sel_fetch)
1494 return;
1495
1496 val = plane_state ? plane_state->ctl : 0;
1497 val &= plane->id == PLANE_CURSOR ? val : PLANE_SEL_FETCH_CTL_ENABLE;
1498 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), val);
1499 if (!val || plane->id == PLANE_CURSOR)
1500 return;
1501
1502 clip = &plane_state->psr2_sel_fetch_area;
1503
1504 val = (clip->y1 + plane_state->uapi.dst.y1) << 16;
1505 val |= plane_state->uapi.dst.x1;
1506 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val);
1507
1508
1509 x = plane_state->uapi.src.x1 >> 16;
1510 y = (plane_state->uapi.src.y1 >> 16) + clip->y1;
1511 ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset);
1512 if (ret)
1513 drm_warn_once(&dev_priv->drm, "skl_calc_main_surface_offset() returned %i\n",
1514 ret);
1515 val = y << 16 | x;
1516 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id),
1517 val);
1518
1519
1520 val = (drm_rect_height(clip) - 1) << 16;
1521 val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
1522 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val);
1523}
1524
1525void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state)
1526{
1527 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1528
1529 if (!HAS_PSR2_SEL_FETCH(dev_priv) ||
1530 !crtc_state->enable_psr2_sel_fetch)
1531 return;
1532
1533 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder),
1534 crtc_state->psr2_man_track_ctl);
1535}
1536
1537static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
1538 struct drm_rect *clip, bool full_update)
1539{
1540 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1541 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1542 u32 val = PSR2_MAN_TRK_CTL_ENABLE;
1543
1544 if (full_update) {
1545 if (IS_ALDERLAKE_P(dev_priv))
1546 val |= ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
1547 else
1548 val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
1549
1550 goto exit;
1551 }
1552
1553 if (clip->y1 == -1)
1554 goto exit;
1555
1556 if (IS_ALDERLAKE_P(dev_priv)) {
1557 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1);
1558 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2);
1559 } else {
1560 drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
1561
1562 val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
1563 val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
1564 val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
1565 }
1566exit:
1567 crtc_state->psr2_man_track_ctl = val;
1568}
1569
1570static void clip_area_update(struct drm_rect *overlap_damage_area,
1571 struct drm_rect *damage_area)
1572{
1573 if (overlap_damage_area->y1 == -1) {
1574 overlap_damage_area->y1 = damage_area->y1;
1575 overlap_damage_area->y2 = damage_area->y2;
1576 return;
1577 }
1578
1579 if (damage_area->y1 < overlap_damage_area->y1)
1580 overlap_damage_area->y1 = damage_area->y1;
1581
1582 if (damage_area->y2 > overlap_damage_area->y2)
1583 overlap_damage_area->y2 = damage_area->y2;
1584}
1585
1586static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *crtc_state,
1587 struct drm_rect *pipe_clip)
1588{
1589 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1590 const u16 y_alignment = crtc_state->su_y_granularity;
1591
1592 pipe_clip->y1 -= pipe_clip->y1 % y_alignment;
1593 if (pipe_clip->y2 % y_alignment)
1594 pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment;
1595
1596 if (IS_ALDERLAKE_P(dev_priv) && crtc_state->dsc.compression_enable)
1597 drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch alignment with DSC\n");
1598}
1599
1600int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
1601 struct intel_crtc *crtc)
1602{
1603 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
1604 struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 = -1 };
1605 struct intel_plane_state *new_plane_state, *old_plane_state;
1606 struct intel_plane *plane;
1607 bool full_update = false;
1608 int i, ret;
1609
1610 if (!crtc_state->enable_psr2_sel_fetch)
1611 return 0;
1612
1613 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
1614 if (ret)
1615 return ret;
1616
1617
1618
1619
1620
1621
1622
1623 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
1624 new_plane_state, i) {
1625 struct drm_rect src, damaged_area = { .y1 = -1 };
1626 struct drm_mode_rect *damaged_clips;
1627 u32 num_clips, j;
1628
1629 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc)
1630 continue;
1631
1632 if (!new_plane_state->uapi.visible &&
1633 !old_plane_state->uapi.visible)
1634 continue;
1635
1636
1637
1638
1639
1640
1641 if (new_plane_state->uapi.dst.y1 < 0 ||
1642 new_plane_state->uapi.dst.x1 < 0) {
1643 full_update = true;
1644 break;
1645 }
1646
1647 num_clips = drm_plane_get_damage_clips_count(&new_plane_state->uapi);
1648
1649
1650
1651
1652
1653
1654 if (new_plane_state->uapi.visible != old_plane_state->uapi.visible ||
1655 !drm_rect_equals(&new_plane_state->uapi.dst,
1656 &old_plane_state->uapi.dst)) {
1657 if (old_plane_state->uapi.visible) {
1658 damaged_area.y1 = old_plane_state->uapi.dst.y1;
1659 damaged_area.y2 = old_plane_state->uapi.dst.y2;
1660 clip_area_update(&pipe_clip, &damaged_area);
1661 }
1662
1663 if (new_plane_state->uapi.visible) {
1664 damaged_area.y1 = new_plane_state->uapi.dst.y1;
1665 damaged_area.y2 = new_plane_state->uapi.dst.y2;
1666 clip_area_update(&pipe_clip, &damaged_area);
1667 }
1668 continue;
1669 } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha ||
1670 (!num_clips &&
1671 new_plane_state->uapi.fb != old_plane_state->uapi.fb)) {
1672
1673
1674
1675
1676
1677 damaged_area.y1 = new_plane_state->uapi.dst.y1;
1678 damaged_area.y2 = new_plane_state->uapi.dst.y2;
1679 clip_area_update(&pipe_clip, &damaged_area);
1680 continue;
1681 }
1682
1683 drm_rect_fp_to_int(&src, &new_plane_state->uapi.src);
1684 damaged_clips = drm_plane_get_damage_clips(&new_plane_state->uapi);
1685
1686 for (j = 0; j < num_clips; j++) {
1687 struct drm_rect clip;
1688
1689 clip.x1 = damaged_clips[j].x1;
1690 clip.y1 = damaged_clips[j].y1;
1691 clip.x2 = damaged_clips[j].x2;
1692 clip.y2 = damaged_clips[j].y2;
1693 if (drm_rect_intersect(&clip, &src))
1694 clip_area_update(&damaged_area, &clip);
1695 }
1696
1697 if (damaged_area.y1 == -1)
1698 continue;
1699
1700 damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1;
1701 damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1;
1702 clip_area_update(&pipe_clip, &damaged_area);
1703 }
1704
1705 if (full_update)
1706 goto skip_sel_fetch_set_loop;
1707
1708 intel_psr2_sel_fetch_pipe_alignment(crtc_state, &pipe_clip);
1709
1710
1711
1712
1713
1714 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
1715 new_plane_state, i) {
1716 struct drm_rect *sel_fetch_area, inter;
1717
1718 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc ||
1719 !new_plane_state->uapi.visible)
1720 continue;
1721
1722 inter = pipe_clip;
1723 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst))
1724 continue;
1725
1726 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area;
1727 sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1;
1728 sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1;
1729 crtc_state->update_planes |= BIT(plane->id);
1730 }
1731
1732skip_sel_fetch_set_loop:
1733 psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update);
1734 return 0;
1735}
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747void intel_psr_update(struct intel_dp *intel_dp,
1748 const struct intel_crtc_state *crtc_state,
1749 const struct drm_connector_state *conn_state)
1750{
1751 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1752 struct intel_psr *psr = &intel_dp->psr;
1753 bool enable, psr2_enable;
1754
1755 if (!CAN_PSR(intel_dp))
1756 return;
1757
1758 mutex_lock(&intel_dp->psr.lock);
1759
1760 enable = crtc_state->has_psr;
1761 psr2_enable = crtc_state->has_psr2;
1762
1763 if (enable == psr->enabled && psr2_enable == psr->psr2_enabled &&
1764 crtc_state->enable_psr2_sel_fetch == psr->psr2_sel_fetch_enabled) {
1765
1766 if (crtc_state->crc_enabled && psr->enabled)
1767 psr_force_hw_tracking_exit(intel_dp);
1768 else if (DISPLAY_VER(dev_priv) < 9 && psr->enabled) {
1769
1770
1771
1772
1773 if (!intel_dp->psr.active &&
1774 !intel_dp->psr.busy_frontbuffer_bits)
1775 schedule_work(&intel_dp->psr.work);
1776 }
1777
1778 goto unlock;
1779 }
1780
1781 if (psr->enabled)
1782 intel_psr_disable_locked(intel_dp);
1783
1784 if (enable)
1785 intel_psr_enable_locked(intel_dp, crtc_state, conn_state);
1786
1787unlock:
1788 mutex_unlock(&intel_dp->psr.lock);
1789}
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799static int psr_wait_for_idle(struct intel_dp *intel_dp, u32 *out_value)
1800{
1801 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1802
1803
1804
1805
1806
1807
1808
1809 return __intel_wait_for_register(&dev_priv->uncore,
1810 EDP_PSR_STATUS(intel_dp->psr.transcoder),
1811 EDP_PSR_STATUS_STATE_MASK,
1812 EDP_PSR_STATUS_STATE_IDLE, 2, 50,
1813 out_value);
1814}
1815
1816
1817
1818
1819
1820
1821
1822
1823void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state)
1824{
1825 struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev);
1826 struct intel_encoder *encoder;
1827
1828 if (!new_crtc_state->has_psr)
1829 return;
1830
1831 for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder,
1832 new_crtc_state->uapi.encoder_mask) {
1833 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1834 u32 psr_status;
1835
1836 mutex_lock(&intel_dp->psr.lock);
1837 if (!intel_dp->psr.enabled || intel_dp->psr.psr2_enabled) {
1838 mutex_unlock(&intel_dp->psr.lock);
1839 continue;
1840 }
1841
1842
1843 if (psr_wait_for_idle(intel_dp, &psr_status))
1844 drm_err(&dev_priv->drm,
1845 "PSR idle timed out 0x%x, atomic update may fail\n",
1846 psr_status);
1847 mutex_unlock(&intel_dp->psr.lock);
1848 }
1849}
1850
1851static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp)
1852{
1853 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1854 i915_reg_t reg;
1855 u32 mask;
1856 int err;
1857
1858 if (!intel_dp->psr.enabled)
1859 return false;
1860
1861 if (intel_dp->psr.psr2_enabled) {
1862 reg = EDP_PSR2_STATUS(intel_dp->psr.transcoder);
1863 mask = EDP_PSR2_STATUS_STATE_MASK;
1864 } else {
1865 reg = EDP_PSR_STATUS(intel_dp->psr.transcoder);
1866 mask = EDP_PSR_STATUS_STATE_MASK;
1867 }
1868
1869 mutex_unlock(&intel_dp->psr.lock);
1870
1871 err = intel_de_wait_for_clear(dev_priv, reg, mask, 50);
1872 if (err)
1873 drm_err(&dev_priv->drm,
1874 "Timed out waiting for PSR Idle for re-enable\n");
1875
1876
1877 mutex_lock(&intel_dp->psr.lock);
1878 return err == 0 && intel_dp->psr.enabled;
1879}
1880
1881static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
1882{
1883 struct drm_connector_list_iter conn_iter;
1884 struct drm_device *dev = &dev_priv->drm;
1885 struct drm_modeset_acquire_ctx ctx;
1886 struct drm_atomic_state *state;
1887 struct drm_connector *conn;
1888 int err = 0;
1889
1890 state = drm_atomic_state_alloc(dev);
1891 if (!state)
1892 return -ENOMEM;
1893
1894 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
1895 state->acquire_ctx = &ctx;
1896
1897retry:
1898
1899 drm_connector_list_iter_begin(dev, &conn_iter);
1900 drm_for_each_connector_iter(conn, &conn_iter) {
1901 struct drm_connector_state *conn_state;
1902 struct drm_crtc_state *crtc_state;
1903
1904 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP)
1905 continue;
1906
1907 conn_state = drm_atomic_get_connector_state(state, conn);
1908 if (IS_ERR(conn_state)) {
1909 err = PTR_ERR(conn_state);
1910 break;
1911 }
1912
1913 if (!conn_state->crtc)
1914 continue;
1915
1916 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc);
1917 if (IS_ERR(crtc_state)) {
1918 err = PTR_ERR(crtc_state);
1919 break;
1920 }
1921
1922
1923 crtc_state->mode_changed = true;
1924 }
1925 drm_connector_list_iter_end(&conn_iter);
1926
1927 if (err == 0)
1928 err = drm_atomic_commit(state);
1929
1930 if (err == -EDEADLK) {
1931 drm_atomic_state_clear(state);
1932 err = drm_modeset_backoff(&ctx);
1933 if (!err)
1934 goto retry;
1935 }
1936
1937 drm_modeset_drop_locks(&ctx);
1938 drm_modeset_acquire_fini(&ctx);
1939 drm_atomic_state_put(state);
1940
1941 return err;
1942}
1943
1944int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val)
1945{
1946 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1947 const u32 mode = val & I915_PSR_DEBUG_MODE_MASK;
1948 u32 old_mode;
1949 int ret;
1950
1951 if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) ||
1952 mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
1953 drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val);
1954 return -EINVAL;
1955 }
1956
1957 ret = mutex_lock_interruptible(&intel_dp->psr.lock);
1958 if (ret)
1959 return ret;
1960
1961 old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK;
1962 intel_dp->psr.debug = val;
1963
1964
1965
1966
1967
1968 if (intel_dp->psr.enabled)
1969 psr_irq_control(intel_dp);
1970
1971 mutex_unlock(&intel_dp->psr.lock);
1972
1973 if (old_mode != mode)
1974 ret = intel_psr_fastset_force(dev_priv);
1975
1976 return ret;
1977}
1978
1979static void intel_psr_handle_irq(struct intel_dp *intel_dp)
1980{
1981 struct intel_psr *psr = &intel_dp->psr;
1982
1983 intel_psr_disable_locked(intel_dp);
1984 psr->sink_not_reliable = true;
1985
1986 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
1987}
1988
1989static void intel_psr_work(struct work_struct *work)
1990{
1991 struct intel_dp *intel_dp =
1992 container_of(work, typeof(*intel_dp), psr.work);
1993
1994 mutex_lock(&intel_dp->psr.lock);
1995
1996 if (!intel_dp->psr.enabled)
1997 goto unlock;
1998
1999 if (READ_ONCE(intel_dp->psr.irq_aux_error))
2000 intel_psr_handle_irq(intel_dp);
2001
2002
2003
2004
2005
2006
2007
2008 if (!__psr_wait_for_idle_locked(intel_dp))
2009 goto unlock;
2010
2011
2012
2013
2014
2015
2016 if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active)
2017 goto unlock;
2018
2019 intel_psr_activate(intel_dp);
2020unlock:
2021 mutex_unlock(&intel_dp->psr.lock);
2022}
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037void intel_psr_invalidate(struct drm_i915_private *dev_priv,
2038 unsigned frontbuffer_bits, enum fb_op_origin origin)
2039{
2040 struct intel_encoder *encoder;
2041
2042 if (origin == ORIGIN_FLIP)
2043 return;
2044
2045 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
2046 unsigned int pipe_frontbuffer_bits = frontbuffer_bits;
2047 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2048
2049 mutex_lock(&intel_dp->psr.lock);
2050 if (!intel_dp->psr.enabled) {
2051 mutex_unlock(&intel_dp->psr.lock);
2052 continue;
2053 }
2054
2055 pipe_frontbuffer_bits &=
2056 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
2057 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits;
2058
2059 if (pipe_frontbuffer_bits)
2060 intel_psr_exit(intel_dp);
2061
2062 mutex_unlock(&intel_dp->psr.lock);
2063 }
2064}
2065
2066
2067
2068
2069
2070
2071static void
2072tgl_dc3co_flush(struct intel_dp *intel_dp, unsigned int frontbuffer_bits,
2073 enum fb_op_origin origin)
2074{
2075 mutex_lock(&intel_dp->psr.lock);
2076
2077 if (!intel_dp->psr.dc3co_exitline)
2078 goto unlock;
2079
2080 if (!intel_dp->psr.psr2_enabled || !intel_dp->psr.active)
2081 goto unlock;
2082
2083
2084
2085
2086
2087 if (!(frontbuffer_bits &
2088 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))
2089 goto unlock;
2090
2091 tgl_psr2_enable_dc3co(intel_dp);
2092 mod_delayed_work(system_wq, &intel_dp->psr.dc3co_work,
2093 intel_dp->psr.dc3co_exit_delay);
2094
2095unlock:
2096 mutex_unlock(&intel_dp->psr.lock);
2097}
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112void intel_psr_flush(struct drm_i915_private *dev_priv,
2113 unsigned frontbuffer_bits, enum fb_op_origin origin)
2114{
2115 struct intel_encoder *encoder;
2116
2117 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
2118 unsigned int pipe_frontbuffer_bits = frontbuffer_bits;
2119 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2120
2121 if (origin == ORIGIN_FLIP) {
2122 tgl_dc3co_flush(intel_dp, frontbuffer_bits, origin);
2123 continue;
2124 }
2125
2126 mutex_lock(&intel_dp->psr.lock);
2127 if (!intel_dp->psr.enabled) {
2128 mutex_unlock(&intel_dp->psr.lock);
2129 continue;
2130 }
2131
2132 pipe_frontbuffer_bits &=
2133 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
2134 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits;
2135
2136
2137
2138
2139
2140
2141 if (intel_dp->psr.paused) {
2142 mutex_unlock(&intel_dp->psr.lock);
2143 continue;
2144 }
2145
2146
2147 if (pipe_frontbuffer_bits)
2148 psr_force_hw_tracking_exit(intel_dp);
2149
2150 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits)
2151 schedule_work(&intel_dp->psr.work);
2152 mutex_unlock(&intel_dp->psr.lock);
2153 }
2154}
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164void intel_psr_init(struct intel_dp *intel_dp)
2165{
2166 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2167 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2168
2169 if (!HAS_PSR(dev_priv))
2170 return;
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181 if (DISPLAY_VER(dev_priv) < 12 && dig_port->base.port != PORT_A) {
2182 drm_dbg_kms(&dev_priv->drm,
2183 "PSR condition failed: Port not supported\n");
2184 return;
2185 }
2186
2187 intel_dp->psr.source_support = true;
2188
2189 if (IS_HASWELL(dev_priv))
2190
2191
2192
2193
2194
2195 dev_priv->hsw_psr_mmio_adjust = _SRD_CTL_EDP - _HSW_EDP_PSR_BASE;
2196
2197 if (dev_priv->params.enable_psr == -1)
2198 if (DISPLAY_VER(dev_priv) < 9 || !dev_priv->vbt.psr.enable)
2199 dev_priv->params.enable_psr = 0;
2200
2201
2202 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2203
2204 intel_dp->psr.link_standby = false;
2205 else if (DISPLAY_VER(dev_priv) < 12)
2206
2207 intel_dp->psr.link_standby = dev_priv->vbt.psr.full_link;
2208
2209 INIT_WORK(&intel_dp->psr.work, intel_psr_work);
2210 INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work);
2211 mutex_init(&intel_dp->psr.lock);
2212}
2213
2214static int psr_get_status_and_error_status(struct intel_dp *intel_dp,
2215 u8 *status, u8 *error_status)
2216{
2217 struct drm_dp_aux *aux = &intel_dp->aux;
2218 int ret;
2219
2220 ret = drm_dp_dpcd_readb(aux, DP_PSR_STATUS, status);
2221 if (ret != 1)
2222 return ret;
2223
2224 ret = drm_dp_dpcd_readb(aux, DP_PSR_ERROR_STATUS, error_status);
2225 if (ret != 1)
2226 return ret;
2227
2228 *status = *status & DP_PSR_SINK_STATE_MASK;
2229
2230 return 0;
2231}
2232
2233static void psr_alpm_check(struct intel_dp *intel_dp)
2234{
2235 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2236 struct drm_dp_aux *aux = &intel_dp->aux;
2237 struct intel_psr *psr = &intel_dp->psr;
2238 u8 val;
2239 int r;
2240
2241 if (!psr->psr2_enabled)
2242 return;
2243
2244 r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val);
2245 if (r != 1) {
2246 drm_err(&dev_priv->drm, "Error reading ALPM status\n");
2247 return;
2248 }
2249
2250 if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) {
2251 intel_psr_disable_locked(intel_dp);
2252 psr->sink_not_reliable = true;
2253 drm_dbg_kms(&dev_priv->drm,
2254 "ALPM lock timeout error, disabling PSR\n");
2255
2256
2257 drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val);
2258 }
2259}
2260
2261static void psr_capability_changed_check(struct intel_dp *intel_dp)
2262{
2263 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2264 struct intel_psr *psr = &intel_dp->psr;
2265 u8 val;
2266 int r;
2267
2268 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val);
2269 if (r != 1) {
2270 drm_err(&dev_priv->drm, "Error reading DP_PSR_ESI\n");
2271 return;
2272 }
2273
2274 if (val & DP_PSR_CAPS_CHANGE) {
2275 intel_psr_disable_locked(intel_dp);
2276 psr->sink_not_reliable = true;
2277 drm_dbg_kms(&dev_priv->drm,
2278 "Sink PSR capability changed, disabling PSR\n");
2279
2280
2281 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val);
2282 }
2283}
2284
2285void intel_psr_short_pulse(struct intel_dp *intel_dp)
2286{
2287 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2288 struct intel_psr *psr = &intel_dp->psr;
2289 u8 status, error_status;
2290 const u8 errors = DP_PSR_RFB_STORAGE_ERROR |
2291 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
2292 DP_PSR_LINK_CRC_ERROR;
2293
2294 if (!CAN_PSR(intel_dp))
2295 return;
2296
2297 mutex_lock(&psr->lock);
2298
2299 if (!psr->enabled)
2300 goto exit;
2301
2302 if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) {
2303 drm_err(&dev_priv->drm,
2304 "Error reading PSR status or error status\n");
2305 goto exit;
2306 }
2307
2308 if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status & errors)) {
2309 intel_psr_disable_locked(intel_dp);
2310 psr->sink_not_reliable = true;
2311 }
2312
2313 if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status)
2314 drm_dbg_kms(&dev_priv->drm,
2315 "PSR sink internal error, disabling PSR\n");
2316 if (error_status & DP_PSR_RFB_STORAGE_ERROR)
2317 drm_dbg_kms(&dev_priv->drm,
2318 "PSR RFB storage error, disabling PSR\n");
2319 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
2320 drm_dbg_kms(&dev_priv->drm,
2321 "PSR VSC SDP uncorrectable error, disabling PSR\n");
2322 if (error_status & DP_PSR_LINK_CRC_ERROR)
2323 drm_dbg_kms(&dev_priv->drm,
2324 "PSR Link CRC error, disabling PSR\n");
2325
2326 if (error_status & ~errors)
2327 drm_err(&dev_priv->drm,
2328 "PSR_ERROR_STATUS unhandled errors %x\n",
2329 error_status & ~errors);
2330
2331 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status);
2332
2333 psr_alpm_check(intel_dp);
2334 psr_capability_changed_check(intel_dp);
2335
2336exit:
2337 mutex_unlock(&psr->lock);
2338}
2339
2340bool intel_psr_enabled(struct intel_dp *intel_dp)
2341{
2342 bool ret;
2343
2344 if (!CAN_PSR(intel_dp))
2345 return false;
2346
2347 mutex_lock(&intel_dp->psr.lock);
2348 ret = intel_dp->psr.enabled;
2349 mutex_unlock(&intel_dp->psr.lock);
2350
2351 return ret;
2352}
2353