1
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7
8#include <linux/limits.h>
9#include "i915_drv.h"
10#include "intel_de.h"
11#include "intel_display_types.h"
12#include "intel_dsi.h"
13#include "intel_vdsc.h"
14#include "intel_qp_tables.h"
15
16enum ROW_INDEX_BPP {
17 ROW_INDEX_6BPP = 0,
18 ROW_INDEX_8BPP,
19 ROW_INDEX_10BPP,
20 ROW_INDEX_12BPP,
21 ROW_INDEX_15BPP,
22 MAX_ROW_INDEX
23};
24
25enum COLUMN_INDEX_BPC {
26 COLUMN_INDEX_8BPC = 0,
27 COLUMN_INDEX_10BPC,
28 COLUMN_INDEX_12BPC,
29 COLUMN_INDEX_14BPC,
30 COLUMN_INDEX_16BPC,
31 MAX_COLUMN_INDEX
32};
33
34
35static const u16 rc_buf_thresh[] = {
36 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
37 7744, 7872, 8000, 8064
38};
39
40struct rc_parameters {
41 u16 initial_xmit_delay;
42 u8 first_line_bpg_offset;
43 u16 initial_offset;
44 u8 flatness_min_qp;
45 u8 flatness_max_qp;
46 u8 rc_quant_incr_limit0;
47 u8 rc_quant_incr_limit1;
48 struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
49};
50
51
52
53
54
55static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
56{
57
58 { 768, 15, 6144, 3, 13, 11, 11, {
59 { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
60 { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
61 { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
62 { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
63 }
64 },
65
66 { 768, 15, 6144, 7, 17, 15, 15, {
67 { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
68 { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
69 { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
70 { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
71 { 17, 18, -12 }
72 }
73 },
74
75 { 768, 15, 6144, 11, 21, 19, 19, {
76 { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
77 { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
78 { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
79 { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
80 { 21, 22, -12 }
81 }
82 },
83
84 { 768, 15, 6144, 15, 25, 23, 27, {
85 { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
86 { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
87 { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
88 { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
89 { 25, 26, -12 }
90 }
91 },
92
93 { 768, 15, 6144, 19, 29, 27, 27, {
94 { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
95 { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
96 { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
97 { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
98 { 29, 30, -12 }
99 }
100 },
101},
102{
103
104 { 512, 12, 6144, 3, 12, 11, 11, {
105 { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
106 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
107 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
108 { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
109 }
110 },
111
112 { 512, 12, 6144, 7, 16, 15, 15, {
113 { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
114 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
115 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
116 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
117 }
118 },
119
120 { 512, 12, 6144, 11, 20, 19, 19, {
121 { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
122 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
123 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
124 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
125 { 21, 23, -12 }
126 }
127 },
128
129 { 512, 12, 6144, 15, 24, 23, 23, {
130 { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
131 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
132 { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
133 { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
134 { 24, 25, -12 }
135 }
136 },
137
138 { 512, 12, 6144, 19, 28, 27, 27, {
139 { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
140 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
141 { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
142 { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
143 { 28, 29, -12 }
144 }
145 },
146},
147{
148
149 { 410, 15, 5632, 3, 12, 11, 11, {
150 { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
151 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
152 { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
153 { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
154 }
155 },
156
157 { 410, 15, 5632, 7, 16, 15, 15, {
158 { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
159 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
160 { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
161 { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
162 }
163 },
164
165 { 410, 15, 5632, 11, 20, 19, 19, {
166 { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
167 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
168 { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
169 { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
170 { 19, 20, -12 }
171 }
172 },
173
174 { 410, 15, 5632, 15, 24, 23, 23, {
175 { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
176 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
177 { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
178 { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
179 { 23, 24, -12 }
180 }
181 },
182
183 { 410, 15, 5632, 19, 28, 27, 27, {
184 { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
185 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
186 { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
187 { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
188 { 27, 28, -12 }
189 }
190 },
191},
192{
193
194 { 341, 15, 2048, 3, 12, 11, 11, {
195 { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
196 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
197 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
198 { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
199 }
200 },
201
202 { 341, 15, 2048, 7, 16, 15, 15, {
203 { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
204 { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
205 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
206 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
207 }
208 },
209
210 { 341, 15, 2048, 11, 20, 19, 19, {
211 { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
212 { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
213 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
214 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
215 { 21, 23, -12 }
216 }
217 },
218
219 { 341, 15, 2048, 15, 24, 23, 23, {
220 { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
221 { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
222 { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
223 { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
224 { 22, 23, -12 }
225 }
226 },
227
228 { 341, 15, 2048, 19, 28, 27, 27, {
229 { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
230 { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
231 { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
232 { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
233 { 26, 27, -12 }
234 }
235 },
236},
237{
238
239 { 273, 15, 2048, 3, 12, 11, 11, {
240 { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
241 { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
242 { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
243 { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
244 }
245 },
246
247 { 273, 15, 2048, 7, 16, 15, 15, {
248 { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
249 { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
250 { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
251 { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
252 }
253 },
254
255 { 273, 15, 2048, 11, 20, 19, 19, {
256 { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
257 { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
258 { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
259 { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
260 { 16, 17, -12 }
261 }
262 },
263
264 { 273, 15, 2048, 15, 24, 23, 23, {
265 { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
266 { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
267 { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
268 { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
269 { 20, 21, -12 }
270 }
271 },
272
273 { 273, 15, 2048, 19, 28, 27, 27, {
274 { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
275 { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
276 { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
277 { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
278 { 24, 25, -12 }
279 }
280 }
281}
282
283};
284
285static int get_row_index_for_rc_params(u16 compressed_bpp)
286{
287 switch (compressed_bpp) {
288 case 6:
289 return ROW_INDEX_6BPP;
290 case 8:
291 return ROW_INDEX_8BPP;
292 case 10:
293 return ROW_INDEX_10BPP;
294 case 12:
295 return ROW_INDEX_12BPP;
296 case 15:
297 return ROW_INDEX_15BPP;
298 default:
299 return -EINVAL;
300 }
301}
302
303static int get_column_index_for_rc_params(u8 bits_per_component)
304{
305 switch (bits_per_component) {
306 case 8:
307 return COLUMN_INDEX_8BPC;
308 case 10:
309 return COLUMN_INDEX_10BPC;
310 case 12:
311 return COLUMN_INDEX_12BPC;
312 case 14:
313 return COLUMN_INDEX_14BPC;
314 case 16:
315 return COLUMN_INDEX_16BPC;
316 default:
317 return -EINVAL;
318 }
319}
320
321static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
322 u8 bits_per_component)
323{
324 int row_index, column_index;
325
326 row_index = get_row_index_for_rc_params(compressed_bpp);
327 if (row_index < 0)
328 return NULL;
329
330 column_index = get_column_index_for_rc_params(bits_per_component);
331 if (column_index < 0)
332 return NULL;
333
334 return &rc_parameters[row_index][column_index];
335}
336
337bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
338{
339 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
340 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
341 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
342 enum pipe pipe = crtc->pipe;
343
344 if (!INTEL_INFO(i915)->display.has_dsc)
345 return false;
346
347
348 if (DISPLAY_VER(i915) >= 12)
349 return true;
350
351 if (DISPLAY_VER(i915) >= 11 &&
352 (pipe != PIPE_A || cpu_transcoder == TRANSCODER_EDP ||
353 cpu_transcoder == TRANSCODER_DSI_0 ||
354 cpu_transcoder == TRANSCODER_DSI_1))
355 return true;
356
357 return false;
358}
359
360static bool is_pipe_dsc(const struct intel_crtc_state *crtc_state)
361{
362 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
363 const struct drm_i915_private *i915 = to_i915(crtc->base.dev);
364 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
365
366 if (DISPLAY_VER(i915) >= 12)
367 return true;
368
369 if (cpu_transcoder == TRANSCODER_EDP ||
370 cpu_transcoder == TRANSCODER_DSI_0 ||
371 cpu_transcoder == TRANSCODER_DSI_1)
372 return false;
373
374
375 drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A);
376
377 return true;
378}
379
380static void
381calculate_rc_params(struct rc_parameters *rc,
382 struct drm_dsc_config *vdsc_cfg)
383{
384 int bpc = vdsc_cfg->bits_per_component;
385 int bpp = vdsc_cfg->bits_per_pixel >> 4;
386 int ofs_und6[] = { 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 };
387 int ofs_und8[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 };
388 int ofs_und12[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 };
389 int ofs_und15[] = { 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 };
390 int qp_bpc_modifier = (bpc - 8) * 2;
391 u32 res, buf_i, bpp_i;
392
393 if (vdsc_cfg->slice_height >= 8)
394 rc->first_line_bpg_offset =
395 12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100);
396 else
397 rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
398
399
400 if (bpp >= 12)
401 rc->initial_offset = 2048;
402 else if (bpp >= 10)
403 rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
404 else if (bpp >= 8)
405 rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
406 else
407 rc->initial_offset = 6144;
408
409
410 rc->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
411
412 rc->flatness_min_qp = 3 + qp_bpc_modifier;
413 rc->flatness_max_qp = 12 + qp_bpc_modifier;
414
415 rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
416 rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
417
418 bpp_i = (2 * (bpp - 6));
419 for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
420
421 rc->rc_range_params[buf_i].range_min_qp =
422 intel_lookup_range_min_qp(bpc, buf_i, bpp_i);
423 rc->rc_range_params[buf_i].range_max_qp =
424 intel_lookup_range_max_qp(bpc, buf_i, bpp_i);
425
426
427 if (bpp <= 6) {
428 rc->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i];
429 } else if (bpp <= 8) {
430 res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] - ofs_und6[buf_i])), 2);
431 rc->rc_range_params[buf_i].range_bpg_offset =
432 ofs_und6[buf_i] + res;
433 } else if (bpp <= 12) {
434 rc->rc_range_params[buf_i].range_bpg_offset =
435 ofs_und8[buf_i];
436 } else if (bpp <= 15) {
437 res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] - ofs_und12[buf_i])), 3);
438 rc->rc_range_params[buf_i].range_bpg_offset =
439 ofs_und12[buf_i] + res;
440 } else {
441 rc->rc_range_params[buf_i].range_bpg_offset =
442 ofs_und15[buf_i];
443 }
444 }
445}
446
447int intel_dsc_compute_params(struct intel_encoder *encoder,
448 struct intel_crtc_state *pipe_config)
449{
450 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
451 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
452 u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
453 const struct rc_parameters *rc_params;
454 struct rc_parameters *rc = NULL;
455 u8 i = 0;
456
457 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
458 vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay;
459 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
460 pipe_config->dsc.slice_count);
461
462
463 vdsc_cfg->simple_422 = false;
464
465 vdsc_cfg->vbr_enable = false;
466
467
468 vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
469 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
470
471 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
472
473
474
475
476
477 vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
478 }
479
480
481
482
483
484 if (compressed_bpp == 6) {
485 vdsc_cfg->rc_buf_thresh[12] = 0x7C;
486 vdsc_cfg->rc_buf_thresh[13] = 0x7D;
487 }
488
489
490
491
492
493
494 if (DISPLAY_VER(dev_priv) >= 13) {
495 rc = kmalloc(sizeof(*rc), GFP_KERNEL);
496 if (!rc)
497 return -ENOMEM;
498
499 calculate_rc_params(rc, vdsc_cfg);
500 rc_params = rc;
501 } else {
502 rc_params = get_rc_params(compressed_bpp,
503 vdsc_cfg->bits_per_component);
504 if (!rc_params)
505 return -EINVAL;
506 }
507
508 vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
509 vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
510 vdsc_cfg->initial_offset = rc_params->initial_offset;
511 vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
512 vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
513 vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
514 vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
515
516 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
517 vdsc_cfg->rc_range_params[i].range_min_qp =
518 rc_params->rc_range_params[i].range_min_qp;
519 vdsc_cfg->rc_range_params[i].range_max_qp =
520 rc_params->rc_range_params[i].range_max_qp;
521
522
523
524
525 vdsc_cfg->rc_range_params[i].range_bpg_offset =
526 rc_params->rc_range_params[i].range_bpg_offset &
527 DSC_RANGE_BPG_OFFSET_MASK;
528 }
529
530
531
532
533
534
535 if (vdsc_cfg->bits_per_component <= 10)
536 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
537 else
538 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
539
540
541 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
542 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
543
544 kfree(rc);
545
546 return 0;
547}
548
549enum intel_display_power_domain
550intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
551{
552 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
553 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
554 enum pipe pipe = crtc->pipe;
555
556
557
558
559
560
561
562
563
564
565
566
567 if (DISPLAY_VER(i915) == 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A)
568 return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
569 else if (is_pipe_dsc(crtc_state))
570 return POWER_DOMAIN_PIPE(pipe);
571 else
572 return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
573}
574
575static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
576{
577 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
578 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
579 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
580 enum pipe pipe = crtc->pipe;
581 u32 pps_val = 0;
582 u32 rc_buf_thresh_dword[4];
583 u32 rc_range_params_dword[8];
584 u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1;
585 int i = 0;
586
587 if (crtc_state->bigjoiner)
588 num_vdsc_instances *= 2;
589
590
591 pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
592 DSC_VER_MIN_SHIFT |
593 vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
594 vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
595 if (vdsc_cfg->block_pred_enable)
596 pps_val |= DSC_BLOCK_PREDICTION;
597 if (vdsc_cfg->convert_rgb)
598 pps_val |= DSC_COLOR_SPACE_CONVERSION;
599 if (vdsc_cfg->simple_422)
600 pps_val |= DSC_422_ENABLE;
601 if (vdsc_cfg->vbr_enable)
602 pps_val |= DSC_VBR_ENABLE;
603 drm_info(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);
604 if (!is_pipe_dsc(crtc_state)) {
605 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0,
606 pps_val);
607
608
609
610
611 if (crtc_state->dsc.dsc_split)
612 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_0,
613 pps_val);
614 } else {
615 intel_de_write(dev_priv,
616 ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe),
617 pps_val);
618 if (crtc_state->dsc.dsc_split)
619 intel_de_write(dev_priv,
620 ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
621 pps_val);
622 }
623
624
625 pps_val = 0;
626 pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
627 drm_info(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
628 if (!is_pipe_dsc(crtc_state)) {
629 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1,
630 pps_val);
631
632
633
634
635 if (crtc_state->dsc.dsc_split)
636 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_1,
637 pps_val);
638 } else {
639 intel_de_write(dev_priv,
640 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe),
641 pps_val);
642 if (crtc_state->dsc.dsc_split)
643 intel_de_write(dev_priv,
644 ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),
645 pps_val);
646 }
647
648
649 pps_val = 0;
650 pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
651 DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
652 drm_info(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
653 if (!is_pipe_dsc(crtc_state)) {
654 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2,
655 pps_val);
656
657
658
659
660 if (crtc_state->dsc.dsc_split)
661 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_2,
662 pps_val);
663 } else {
664 intel_de_write(dev_priv,
665 ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe),
666 pps_val);
667 if (crtc_state->dsc.dsc_split)
668 intel_de_write(dev_priv,
669 ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),
670 pps_val);
671 }
672
673
674 pps_val = 0;
675 pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
676 DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
677 drm_info(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
678 if (!is_pipe_dsc(crtc_state)) {
679 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_3,
680 pps_val);
681
682
683
684
685 if (crtc_state->dsc.dsc_split)
686 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_3,
687 pps_val);
688 } else {
689 intel_de_write(dev_priv,
690 ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe),
691 pps_val);
692 if (crtc_state->dsc.dsc_split)
693 intel_de_write(dev_priv,
694 ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),
695 pps_val);
696 }
697
698
699 pps_val = 0;
700 pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
701 DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
702 drm_info(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
703 if (!is_pipe_dsc(crtc_state)) {
704 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_4,
705 pps_val);
706
707
708
709
710 if (crtc_state->dsc.dsc_split)
711 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_4,
712 pps_val);
713 } else {
714 intel_de_write(dev_priv,
715 ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe),
716 pps_val);
717 if (crtc_state->dsc.dsc_split)
718 intel_de_write(dev_priv,
719 ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),
720 pps_val);
721 }
722
723
724 pps_val = 0;
725 pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
726 DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
727 drm_info(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
728 if (!is_pipe_dsc(crtc_state)) {
729 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_5,
730 pps_val);
731
732
733
734
735 if (crtc_state->dsc.dsc_split)
736 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_5,
737 pps_val);
738 } else {
739 intel_de_write(dev_priv,
740 ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe),
741 pps_val);
742 if (crtc_state->dsc.dsc_split)
743 intel_de_write(dev_priv,
744 ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),
745 pps_val);
746 }
747
748
749 pps_val = 0;
750 pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
751 DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
752 DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
753 DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
754 drm_info(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);
755 if (!is_pipe_dsc(crtc_state)) {
756 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_6,
757 pps_val);
758
759
760
761
762 if (crtc_state->dsc.dsc_split)
763 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_6,
764 pps_val);
765 } else {
766 intel_de_write(dev_priv,
767 ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe),
768 pps_val);
769 if (crtc_state->dsc.dsc_split)
770 intel_de_write(dev_priv,
771 ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),
772 pps_val);
773 }
774
775
776 pps_val = 0;
777 pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
778 DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
779 drm_info(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
780 if (!is_pipe_dsc(crtc_state)) {
781 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_7,
782 pps_val);
783
784
785
786
787 if (crtc_state->dsc.dsc_split)
788 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_7,
789 pps_val);
790 } else {
791 intel_de_write(dev_priv,
792 ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe),
793 pps_val);
794 if (crtc_state->dsc.dsc_split)
795 intel_de_write(dev_priv,
796 ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),
797 pps_val);
798 }
799
800
801 pps_val = 0;
802 pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
803 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
804 drm_info(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
805 if (!is_pipe_dsc(crtc_state)) {
806 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_8,
807 pps_val);
808
809
810
811
812 if (crtc_state->dsc.dsc_split)
813 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_8,
814 pps_val);
815 } else {
816 intel_de_write(dev_priv,
817 ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe),
818 pps_val);
819 if (crtc_state->dsc.dsc_split)
820 intel_de_write(dev_priv,
821 ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),
822 pps_val);
823 }
824
825
826 pps_val = 0;
827 pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
828 DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
829 drm_info(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
830 if (!is_pipe_dsc(crtc_state)) {
831 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_9,
832 pps_val);
833
834
835
836
837 if (crtc_state->dsc.dsc_split)
838 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_9,
839 pps_val);
840 } else {
841 intel_de_write(dev_priv,
842 ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe),
843 pps_val);
844 if (crtc_state->dsc.dsc_split)
845 intel_de_write(dev_priv,
846 ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),
847 pps_val);
848 }
849
850
851 pps_val = 0;
852 pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |
853 DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
854 DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
855 DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
856 drm_info(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);
857 if (!is_pipe_dsc(crtc_state)) {
858 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_10,
859 pps_val);
860
861
862
863
864 if (crtc_state->dsc.dsc_split)
865 intel_de_write(dev_priv,
866 DSCC_PICTURE_PARAMETER_SET_10, pps_val);
867 } else {
868 intel_de_write(dev_priv,
869 ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe),
870 pps_val);
871 if (crtc_state->dsc.dsc_split)
872 intel_de_write(dev_priv,
873 ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),
874 pps_val);
875 }
876
877
878 pps_val = 0;
879 pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
880 DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /
881 vdsc_cfg->slice_width) |
882 DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
883 vdsc_cfg->slice_height);
884 drm_info(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);
885 if (!is_pipe_dsc(crtc_state)) {
886 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_16,
887 pps_val);
888
889
890
891
892 if (crtc_state->dsc.dsc_split)
893 intel_de_write(dev_priv,
894 DSCC_PICTURE_PARAMETER_SET_16, pps_val);
895 } else {
896 intel_de_write(dev_priv,
897 ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe),
898 pps_val);
899 if (crtc_state->dsc.dsc_split)
900 intel_de_write(dev_priv,
901 ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),
902 pps_val);
903 }
904
905
906 memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
907 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
908 rc_buf_thresh_dword[i / 4] |=
909 (u32)(vdsc_cfg->rc_buf_thresh[i] <<
910 BITS_PER_BYTE * (i % 4));
911 drm_info(&dev_priv->drm, " RC_BUF_THRESH%d = 0x%08x\n", i,
912 rc_buf_thresh_dword[i / 4]);
913 }
914 if (!is_pipe_dsc(crtc_state)) {
915 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0,
916 rc_buf_thresh_dword[0]);
917 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW,
918 rc_buf_thresh_dword[1]);
919 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1,
920 rc_buf_thresh_dword[2]);
921 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW,
922 rc_buf_thresh_dword[3]);
923 if (crtc_state->dsc.dsc_split) {
924 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0,
925 rc_buf_thresh_dword[0]);
926 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0_UDW,
927 rc_buf_thresh_dword[1]);
928 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1,
929 rc_buf_thresh_dword[2]);
930 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1_UDW,
931 rc_buf_thresh_dword[3]);
932 }
933 } else {
934 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0(pipe),
935 rc_buf_thresh_dword[0]);
936 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
937 rc_buf_thresh_dword[1]);
938 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1(pipe),
939 rc_buf_thresh_dword[2]);
940 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
941 rc_buf_thresh_dword[3]);
942 if (crtc_state->dsc.dsc_split) {
943 intel_de_write(dev_priv,
944 ICL_DSC1_RC_BUF_THRESH_0(pipe),
945 rc_buf_thresh_dword[0]);
946 intel_de_write(dev_priv,
947 ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),
948 rc_buf_thresh_dword[1]);
949 intel_de_write(dev_priv,
950 ICL_DSC1_RC_BUF_THRESH_1(pipe),
951 rc_buf_thresh_dword[2]);
952 intel_de_write(dev_priv,
953 ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe),
954 rc_buf_thresh_dword[3]);
955 }
956 }
957
958
959 memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword));
960 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
961 rc_range_params_dword[i / 2] |=
962 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<
963 RC_BPG_OFFSET_SHIFT) |
964 (vdsc_cfg->rc_range_params[i].range_max_qp <<
965 RC_MAX_QP_SHIFT) |
966 (vdsc_cfg->rc_range_params[i].range_min_qp <<
967 RC_MIN_QP_SHIFT)) << 16 * (i % 2));
968 drm_info(&dev_priv->drm, " RC_RANGE_PARAM_%d = 0x%08x\n", i,
969 rc_range_params_dword[i / 2]);
970 }
971 if (!is_pipe_dsc(crtc_state)) {
972 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0,
973 rc_range_params_dword[0]);
974 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0_UDW,
975 rc_range_params_dword[1]);
976 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1,
977 rc_range_params_dword[2]);
978 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1_UDW,
979 rc_range_params_dword[3]);
980 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2,
981 rc_range_params_dword[4]);
982 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2_UDW,
983 rc_range_params_dword[5]);
984 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3,
985 rc_range_params_dword[6]);
986 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3_UDW,
987 rc_range_params_dword[7]);
988 if (crtc_state->dsc.dsc_split) {
989 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_0,
990 rc_range_params_dword[0]);
991 intel_de_write(dev_priv,
992 DSCC_RC_RANGE_PARAMETERS_0_UDW,
993 rc_range_params_dword[1]);
994 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_1,
995 rc_range_params_dword[2]);
996 intel_de_write(dev_priv,
997 DSCC_RC_RANGE_PARAMETERS_1_UDW,
998 rc_range_params_dword[3]);
999 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_2,
1000 rc_range_params_dword[4]);
1001 intel_de_write(dev_priv,
1002 DSCC_RC_RANGE_PARAMETERS_2_UDW,
1003 rc_range_params_dword[5]);
1004 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_3,
1005 rc_range_params_dword[6]);
1006 intel_de_write(dev_priv,
1007 DSCC_RC_RANGE_PARAMETERS_3_UDW,
1008 rc_range_params_dword[7]);
1009 }
1010 } else {
1011 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
1012 rc_range_params_dword[0]);
1013 intel_de_write(dev_priv,
1014 ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe),
1015 rc_range_params_dword[1]);
1016 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
1017 rc_range_params_dword[2]);
1018 intel_de_write(dev_priv,
1019 ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe),
1020 rc_range_params_dword[3]);
1021 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
1022 rc_range_params_dword[4]);
1023 intel_de_write(dev_priv,
1024 ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe),
1025 rc_range_params_dword[5]);
1026 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
1027 rc_range_params_dword[6]);
1028 intel_de_write(dev_priv,
1029 ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),
1030 rc_range_params_dword[7]);
1031 if (crtc_state->dsc.dsc_split) {
1032 intel_de_write(dev_priv,
1033 ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),
1034 rc_range_params_dword[0]);
1035 intel_de_write(dev_priv,
1036 ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),
1037 rc_range_params_dword[1]);
1038 intel_de_write(dev_priv,
1039 ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe),
1040 rc_range_params_dword[2]);
1041 intel_de_write(dev_priv,
1042 ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe),
1043 rc_range_params_dword[3]);
1044 intel_de_write(dev_priv,
1045 ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe),
1046 rc_range_params_dword[4]);
1047 intel_de_write(dev_priv,
1048 ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe),
1049 rc_range_params_dword[5]);
1050 intel_de_write(dev_priv,
1051 ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe),
1052 rc_range_params_dword[6]);
1053 intel_de_write(dev_priv,
1054 ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe),
1055 rc_range_params_dword[7]);
1056 }
1057 }
1058}
1059
1060static void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
1061 const struct intel_crtc_state *crtc_state)
1062{
1063 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1064 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1065 struct mipi_dsi_device *dsi;
1066 struct drm_dsc_picture_parameter_set pps;
1067 enum port port;
1068
1069 drm_dsc_pps_payload_pack(&pps, vdsc_cfg);
1070
1071 for_each_dsi_port(port, intel_dsi->ports) {
1072 dsi = intel_dsi->dsi_hosts[port]->device;
1073
1074 mipi_dsi_picture_parameter_set(dsi, &pps);
1075 mipi_dsi_compression_mode(dsi, true);
1076 }
1077}
1078
1079static void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
1080 const struct intel_crtc_state *crtc_state)
1081{
1082 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1083 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1084 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1085 struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
1086
1087
1088 drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp.pps_header);
1089
1090
1091 drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg);
1092
1093 dig_port->write_infoframe(encoder, crtc_state,
1094 DP_SDP_PPS, &dp_dsc_pps_sdp,
1095 sizeof(dp_dsc_pps_sdp));
1096}
1097
1098static i915_reg_t dss_ctl1_reg(const struct intel_crtc_state *crtc_state)
1099{
1100 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
1101
1102 return is_pipe_dsc(crtc_state) ? ICL_PIPE_DSS_CTL1(pipe) : DSS_CTL1;
1103}
1104
1105static i915_reg_t dss_ctl2_reg(const struct intel_crtc_state *crtc_state)
1106{
1107 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
1108
1109 return is_pipe_dsc(crtc_state) ? ICL_PIPE_DSS_CTL2(pipe) : DSS_CTL2;
1110}
1111
1112static struct intel_crtc *
1113_get_crtc_for_pipe(struct drm_i915_private *i915, enum pipe pipe)
1114{
1115 if (!intel_pipe_valid(i915, pipe))
1116 return NULL;
1117
1118 return intel_get_crtc_for_pipe(i915, pipe);
1119}
1120
1121struct intel_crtc *
1122intel_dsc_get_bigjoiner_secondary(const struct intel_crtc *primary_crtc)
1123{
1124 return _get_crtc_for_pipe(to_i915(primary_crtc->base.dev), primary_crtc->pipe + 1);
1125}
1126
1127static struct intel_crtc *
1128intel_dsc_get_bigjoiner_primary(const struct intel_crtc *secondary_crtc)
1129{
1130 return _get_crtc_for_pipe(to_i915(secondary_crtc->base.dev), secondary_crtc->pipe - 1);
1131}
1132
1133void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state)
1134{
1135 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1136 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1137 u32 dss_ctl1_val = 0;
1138
1139 if (crtc_state->bigjoiner && !crtc_state->dsc.compression_enable) {
1140 if (crtc_state->bigjoiner_slave)
1141 dss_ctl1_val |= UNCOMPRESSED_JOINER_SLAVE;
1142 else
1143 dss_ctl1_val |= UNCOMPRESSED_JOINER_MASTER;
1144
1145 intel_de_write(dev_priv, dss_ctl1_reg(crtc_state), dss_ctl1_val);
1146 }
1147}
1148
1149void intel_dsc_enable(struct intel_encoder *encoder,
1150 const struct intel_crtc_state *crtc_state)
1151{
1152 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1153 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1154 u32 dss_ctl1_val = 0;
1155 u32 dss_ctl2_val = 0;
1156
1157 if (!crtc_state->dsc.compression_enable)
1158 return;
1159
1160 intel_dsc_pps_configure(crtc_state);
1161
1162 if (!crtc_state->bigjoiner_slave) {
1163 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
1164 intel_dsc_dsi_pps_write(encoder, crtc_state);
1165 else
1166 intel_dsc_dp_pps_write(encoder, crtc_state);
1167 }
1168
1169 dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
1170 if (crtc_state->dsc.dsc_split) {
1171 dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
1172 dss_ctl1_val |= JOINER_ENABLE;
1173 }
1174 if (crtc_state->bigjoiner) {
1175 dss_ctl1_val |= BIG_JOINER_ENABLE;
1176 if (!crtc_state->bigjoiner_slave)
1177 dss_ctl1_val |= MASTER_BIG_JOINER_ENABLE;
1178 }
1179 intel_de_write(dev_priv, dss_ctl1_reg(crtc_state), dss_ctl1_val);
1180 intel_de_write(dev_priv, dss_ctl2_reg(crtc_state), dss_ctl2_val);
1181}
1182
1183void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
1184{
1185 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1186 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1187
1188
1189 if (old_crtc_state->dsc.compression_enable ||
1190 old_crtc_state->bigjoiner) {
1191 intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0);
1192 intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0);
1193 }
1194}
1195
1196void intel_uncompressed_joiner_get_config(struct intel_crtc_state *crtc_state)
1197{
1198 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1199 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1200 u32 dss_ctl1;
1201
1202 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc_state));
1203 if (dss_ctl1 & UNCOMPRESSED_JOINER_MASTER) {
1204 crtc_state->bigjoiner = true;
1205 crtc_state->bigjoiner_linked_crtc = intel_dsc_get_bigjoiner_secondary(crtc);
1206 drm_WARN_ON(&dev_priv->drm, !crtc_state->bigjoiner_linked_crtc);
1207 } else if (dss_ctl1 & UNCOMPRESSED_JOINER_SLAVE) {
1208 crtc_state->bigjoiner = true;
1209 crtc_state->bigjoiner_slave = true;
1210 crtc_state->bigjoiner_linked_crtc = intel_dsc_get_bigjoiner_primary(crtc);
1211 drm_WARN_ON(&dev_priv->drm, !crtc_state->bigjoiner_linked_crtc);
1212 }
1213}
1214
1215void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
1216{
1217 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1218 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1219 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1220 enum pipe pipe = crtc->pipe;
1221 enum intel_display_power_domain power_domain;
1222 intel_wakeref_t wakeref;
1223 u32 dss_ctl1, dss_ctl2, val;
1224
1225 if (!intel_dsc_source_support(crtc_state))
1226 return;
1227
1228 power_domain = intel_dsc_power_domain(crtc_state);
1229
1230 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1231 if (!wakeref)
1232 return;
1233
1234 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc_state));
1235 dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc_state));
1236
1237 crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE;
1238 if (!crtc_state->dsc.compression_enable)
1239 goto out;
1240
1241 crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
1242 (dss_ctl1 & JOINER_ENABLE);
1243
1244 if (dss_ctl1 & BIG_JOINER_ENABLE) {
1245 crtc_state->bigjoiner = true;
1246
1247 if (!(dss_ctl1 & MASTER_BIG_JOINER_ENABLE)) {
1248 crtc_state->bigjoiner_slave = true;
1249 crtc_state->bigjoiner_linked_crtc = intel_dsc_get_bigjoiner_primary(crtc);
1250 } else {
1251 crtc_state->bigjoiner_linked_crtc = intel_dsc_get_bigjoiner_secondary(crtc);
1252 }
1253 drm_WARN_ON(&dev_priv->drm, !crtc_state->bigjoiner_linked_crtc);
1254 }
1255
1256
1257
1258
1259 if (!is_pipe_dsc(crtc_state))
1260 val = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
1261 else
1262 val = intel_de_read(dev_priv,
1263 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
1264 vdsc_cfg->bits_per_pixel = val;
1265 crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
1266out:
1267 intel_display_power_put(dev_priv, power_domain, wakeref);
1268}
1269
