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5
6#ifndef __INTEL_GT_TYPES__
7#define __INTEL_GT_TYPES__
8
9#include <linux/ktime.h>
10#include <linux/list.h>
11#include <linux/llist.h>
12#include <linux/mutex.h>
13#include <linux/notifier.h>
14#include <linux/spinlock.h>
15#include <linux/types.h>
16#include <linux/workqueue.h>
17
18#include "uc/intel_uc.h"
19
20#include "i915_vma.h"
21#include "intel_engine_types.h"
22#include "intel_gt_buffer_pool_types.h"
23#include "intel_llc_types.h"
24#include "intel_reset_types.h"
25#include "intel_rc6_types.h"
26#include "intel_rps_types.h"
27#include "intel_migrate_types.h"
28#include "intel_wakeref.h"
29
30struct drm_i915_private;
31struct i915_ggtt;
32struct intel_engine_cs;
33struct intel_uncore;
34
35struct intel_mmio_range {
36 u32 start;
37 u32 end;
38};
39
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51
52
53
54enum intel_steering_type {
55 L3BANK,
56 MSLICE,
57 LNCF,
58
59 NUM_STEERING_TYPES
60};
61
62enum intel_submission_method {
63 INTEL_SUBMISSION_RING,
64 INTEL_SUBMISSION_ELSP,
65 INTEL_SUBMISSION_GUC,
66};
67
68struct intel_gt {
69 struct drm_i915_private *i915;
70 struct intel_uncore *uncore;
71 struct i915_ggtt *ggtt;
72
73 struct intel_uc uc;
74
75 struct intel_gt_timelines {
76 spinlock_t lock;
77 struct list_head active_list;
78 } timelines;
79
80 struct intel_gt_requests {
81
82
83
84
85
86
87
88 struct delayed_work retire_work;
89 } requests;
90
91 struct {
92 struct llist_head list;
93 struct work_struct work;
94 } watchdog;
95
96 struct intel_wakeref wakeref;
97 atomic_t user_wakeref;
98
99 struct list_head closed_vma;
100 spinlock_t closed_lock;
101
102 ktime_t last_init_time;
103 struct intel_reset reset;
104
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110
111
112 intel_wakeref_t awake;
113
114 u32 clock_frequency;
115 u32 clock_period_ns;
116
117 struct intel_llc llc;
118 struct intel_rc6 rc6;
119 struct intel_rps rps;
120
121 spinlock_t irq_lock;
122 u32 gt_imr;
123 u32 pm_ier;
124 u32 pm_imr;
125
126 u32 pm_guc_events;
127
128 struct {
129 bool active;
130
131
132
133
134 seqcount_mutex_t lock;
135
136
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140
141
142 ktime_t total;
143
144
145
146
147
148
149 ktime_t start;
150 } stats;
151
152 struct intel_engine_cs *engine[I915_NUM_ENGINES];
153 struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
154 [MAX_ENGINE_INSTANCE + 1];
155 enum intel_submission_method submission_method;
156
157
158
159
160
161
162 struct i915_address_space *vm;
163
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170
171
172 struct intel_gt_buffer_pool buffer_pool;
173
174 struct i915_vma *scratch;
175
176 struct intel_migrate migrate;
177
178 const struct intel_mmio_range *steering_table[NUM_STEERING_TYPES];
179
180 struct intel_gt_info {
181 intel_engine_mask_t engine_mask;
182
183 u32 l3bank_mask;
184
185 u8 num_engines;
186
187
188 u8 vdbox_sfc_access;
189
190
191 struct sseu_dev_info sseu;
192
193 unsigned long mslice_mask;
194 } info;
195};
196
197enum intel_gt_scratch_field {
198
199 INTEL_GT_SCRATCH_FIELD_DEFAULT = 0,
200
201
202 INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH = 128,
203
204
205 INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256,
206
207
208 INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR = 2048,
209
210
211 INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1 = 2096,
212};
213
214#endif
215