1/* SPDX-License-Identifier: MIT */ 2/* 3 * Copyright © 2014-2018 Intel Corporation 4 */ 5 6#ifndef _INTEL_LRC_REG_H_ 7#define _INTEL_LRC_REG_H_ 8 9#include <linux/types.h> 10 11#define CTX_DESC_FORCE_RESTORE BIT_ULL(2) 12 13/* GEN8 to GEN12 Reg State Context */ 14#define CTX_CONTEXT_CONTROL (0x02 + 1) 15#define CTX_RING_HEAD (0x04 + 1) 16#define CTX_RING_TAIL (0x06 + 1) 17#define CTX_RING_START (0x08 + 1) 18#define CTX_RING_CTL (0x0a + 1) 19#define CTX_BB_STATE (0x10 + 1) 20#define CTX_TIMESTAMP (0x22 + 1) 21#define CTX_PDP3_UDW (0x24 + 1) 22#define CTX_PDP3_LDW (0x26 + 1) 23#define CTX_PDP2_UDW (0x28 + 1) 24#define CTX_PDP2_LDW (0x2a + 1) 25#define CTX_PDP1_UDW (0x2c + 1) 26#define CTX_PDP1_LDW (0x2e + 1) 27#define CTX_PDP0_UDW (0x30 + 1) 28#define CTX_PDP0_LDW (0x32 + 1) 29#define CTX_R_PWR_CLK_STATE (0x42 + 1) 30 31#define GEN9_CTX_RING_MI_MODE 0x54 32 33#define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \ 34 u32 *reg_state__ = (reg_state); \ 35 const u64 addr__ = i915_page_dir_dma_addr((ppgtt), (n)); \ 36 (reg_state__)[CTX_PDP ## n ## _UDW] = upper_32_bits(addr__); \ 37 (reg_state__)[CTX_PDP ## n ## _LDW] = lower_32_bits(addr__); \ 38} while (0) 39 40#define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \ 41 u32 *reg_state__ = (reg_state); \ 42 const u64 addr__ = px_dma((ppgtt)->pd); \ 43 (reg_state__)[CTX_PDP0_UDW] = upper_32_bits(addr__); \ 44 (reg_state__)[CTX_PDP0_LDW] = lower_32_bits(addr__); \ 45} while (0) 46 47#define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 48#define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 49#define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x19 50#define GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x1A 51#define GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0xD 52 53#define GEN8_EXECLISTS_STATUS_BUF 0x370 54#define GEN11_EXECLISTS_STATUS_BUF2 0x3c0 55 56/* Execlists regs */ 57#define RING_ELSP(base) _MMIO((base) + 0x230) 58#define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234) 59#define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4) 60#define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244) 61#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0) 62#define CTX_CTRL_RS_CTX_ENABLE REG_BIT(1) 63#define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT REG_BIT(2) 64#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3) 65#define GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE REG_BIT(8) 66#define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0) 67#define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510) 68#define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550) 69#define EL_CTRL_LOAD REG_BIT(0) 70 71/* 72 * The docs specify that the write pointer wraps around after 5h, "After status 73 * is written out to the last available status QW at offset 5h, this pointer 74 * wraps to 0." 75 * 76 * Therefore, one must infer than even though there are 3 bits available, 6 and 77 * 7 appear to be * reserved. 78 */ 79#define GEN8_CSB_ENTRIES 6 80#define GEN8_CSB_PTR_MASK 0x7 81#define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8) 82#define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0) 83 84#define GEN11_CSB_ENTRIES 12 85#define GEN11_CSB_PTR_MASK 0xf 86#define GEN11_CSB_READ_PTR_MASK (GEN11_CSB_PTR_MASK << 8) 87#define GEN11_CSB_WRITE_PTR_MASK (GEN11_CSB_PTR_MASK << 0) 88 89#define MAX_CONTEXT_HW_ID (1 << 21) /* exclusive */ 90#define GEN11_MAX_CONTEXT_HW_ID (1 << 11) /* exclusive */ 91/* in Gen12 ID 0x7FF is reserved to indicate idle */ 92#define GEN12_MAX_CONTEXT_HW_ID (GEN11_MAX_CONTEXT_HW_ID - 1) 93/* in Xe_HP ID 0xFFFF is reserved to indicate "invalid context" */ 94#define XEHP_MAX_CONTEXT_HW_ID 0xFFFF 95 96#endif /* _INTEL_LRC_REG_H_ */ 97