1
2
3
4
5
6#include <linux/sched/mm.h>
7#include <linux/stop_machine.h>
8
9#include "display/intel_display_types.h"
10#include "display/intel_overlay.h"
11
12#include "gem/i915_gem_context.h"
13
14#include "i915_drv.h"
15#include "i915_gpu_error.h"
16#include "i915_irq.h"
17#include "intel_breadcrumbs.h"
18#include "intel_engine_pm.h"
19#include "intel_gt.h"
20#include "intel_gt_pm.h"
21#include "intel_gt_requests.h"
22#include "intel_reset.h"
23
24#include "uc/intel_guc.h"
25
26#define RESET_MAX_RETRIES 3
27
28
29#define RESET_UNDER_STOP_MACHINE 0
30
31static void rmw_set_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
32{
33 intel_uncore_rmw_fw(uncore, reg, 0, set);
34}
35
36static void rmw_clear_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
37{
38 intel_uncore_rmw_fw(uncore, reg, clr, 0);
39}
40
41static void client_mark_guilty(struct i915_gem_context *ctx, bool banned)
42{
43 struct drm_i915_file_private *file_priv = ctx->file_priv;
44 unsigned long prev_hang;
45 unsigned int score;
46
47 if (IS_ERR_OR_NULL(file_priv))
48 return;
49
50 score = 0;
51 if (banned)
52 score = I915_CLIENT_SCORE_CONTEXT_BAN;
53
54 prev_hang = xchg(&file_priv->hang_timestamp, jiffies);
55 if (time_before(jiffies, prev_hang + I915_CLIENT_FAST_HANG_JIFFIES))
56 score += I915_CLIENT_SCORE_HANG_FAST;
57
58 if (score) {
59 atomic_add(score, &file_priv->ban_score);
60
61 drm_dbg(&ctx->i915->drm,
62 "client %s: gained %u ban score, now %u\n",
63 ctx->name, score,
64 atomic_read(&file_priv->ban_score));
65 }
66}
67
68static bool mark_guilty(struct i915_request *rq)
69{
70 struct i915_gem_context *ctx;
71 unsigned long prev_hang;
72 bool banned;
73 int i;
74
75 if (intel_context_is_closed(rq->context))
76 return true;
77
78 rcu_read_lock();
79 ctx = rcu_dereference(rq->context->gem_context);
80 if (ctx && !kref_get_unless_zero(&ctx->ref))
81 ctx = NULL;
82 rcu_read_unlock();
83 if (!ctx)
84 return intel_context_is_banned(rq->context);
85
86 atomic_inc(&ctx->guilty_count);
87
88
89 if (!i915_gem_context_is_bannable(ctx)) {
90 banned = false;
91 goto out;
92 }
93
94 drm_notice(&ctx->i915->drm,
95 "%s context reset due to GPU hang\n",
96 ctx->name);
97
98
99 prev_hang = ctx->hang_timestamp[0];
100 for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp) - 1; i++)
101 ctx->hang_timestamp[i] = ctx->hang_timestamp[i + 1];
102 ctx->hang_timestamp[i] = jiffies;
103
104
105 banned = !i915_gem_context_is_recoverable(ctx);
106 if (time_before(jiffies, prev_hang + CONTEXT_FAST_HANG_JIFFIES))
107 banned = true;
108 if (banned)
109 drm_dbg(&ctx->i915->drm, "context %s: guilty %d, banned\n",
110 ctx->name, atomic_read(&ctx->guilty_count));
111
112 client_mark_guilty(ctx, banned);
113
114out:
115 i915_gem_context_put(ctx);
116 return banned;
117}
118
119static void mark_innocent(struct i915_request *rq)
120{
121 struct i915_gem_context *ctx;
122
123 rcu_read_lock();
124 ctx = rcu_dereference(rq->context->gem_context);
125 if (ctx)
126 atomic_inc(&ctx->active_count);
127 rcu_read_unlock();
128}
129
130void __i915_request_reset(struct i915_request *rq, bool guilty)
131{
132 bool banned = false;
133
134 RQ_TRACE(rq, "guilty? %s\n", yesno(guilty));
135 GEM_BUG_ON(__i915_request_is_complete(rq));
136
137 rcu_read_lock();
138 if (guilty) {
139 i915_request_set_error_once(rq, -EIO);
140 __i915_request_skip(rq);
141 banned = mark_guilty(rq);
142 } else {
143 i915_request_set_error_once(rq, -EAGAIN);
144 mark_innocent(rq);
145 }
146 rcu_read_unlock();
147
148 if (banned)
149 intel_context_ban(rq->context, rq);
150}
151
152static bool i915_in_reset(struct pci_dev *pdev)
153{
154 u8 gdrst;
155
156 pci_read_config_byte(pdev, I915_GDRST, &gdrst);
157 return gdrst & GRDOM_RESET_STATUS;
158}
159
160static int i915_do_reset(struct intel_gt *gt,
161 intel_engine_mask_t engine_mask,
162 unsigned int retry)
163{
164 struct pci_dev *pdev = to_pci_dev(gt->i915->drm.dev);
165 int err;
166
167
168 pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
169 udelay(50);
170 err = wait_for_atomic(i915_in_reset(pdev), 50);
171
172
173 pci_write_config_byte(pdev, I915_GDRST, 0);
174 udelay(50);
175 if (!err)
176 err = wait_for_atomic(!i915_in_reset(pdev), 50);
177
178 return err;
179}
180
181static bool g4x_reset_complete(struct pci_dev *pdev)
182{
183 u8 gdrst;
184
185 pci_read_config_byte(pdev, I915_GDRST, &gdrst);
186 return (gdrst & GRDOM_RESET_ENABLE) == 0;
187}
188
189static int g33_do_reset(struct intel_gt *gt,
190 intel_engine_mask_t engine_mask,
191 unsigned int retry)
192{
193 struct pci_dev *pdev = to_pci_dev(gt->i915->drm.dev);
194
195 pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
196 return wait_for_atomic(g4x_reset_complete(pdev), 50);
197}
198
199static int g4x_do_reset(struct intel_gt *gt,
200 intel_engine_mask_t engine_mask,
201 unsigned int retry)
202{
203 struct pci_dev *pdev = to_pci_dev(gt->i915->drm.dev);
204 struct intel_uncore *uncore = gt->uncore;
205 int ret;
206
207
208 rmw_set_fw(uncore, VDECCLK_GATE_D, VCP_UNIT_CLOCK_GATE_DISABLE);
209 intel_uncore_posting_read_fw(uncore, VDECCLK_GATE_D);
210
211 pci_write_config_byte(pdev, I915_GDRST,
212 GRDOM_MEDIA | GRDOM_RESET_ENABLE);
213 ret = wait_for_atomic(g4x_reset_complete(pdev), 50);
214 if (ret) {
215 GT_TRACE(gt, "Wait for media reset failed\n");
216 goto out;
217 }
218
219 pci_write_config_byte(pdev, I915_GDRST,
220 GRDOM_RENDER | GRDOM_RESET_ENABLE);
221 ret = wait_for_atomic(g4x_reset_complete(pdev), 50);
222 if (ret) {
223 GT_TRACE(gt, "Wait for render reset failed\n");
224 goto out;
225 }
226
227out:
228 pci_write_config_byte(pdev, I915_GDRST, 0);
229
230 rmw_clear_fw(uncore, VDECCLK_GATE_D, VCP_UNIT_CLOCK_GATE_DISABLE);
231 intel_uncore_posting_read_fw(uncore, VDECCLK_GATE_D);
232
233 return ret;
234}
235
236static int ilk_do_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask,
237 unsigned int retry)
238{
239 struct intel_uncore *uncore = gt->uncore;
240 int ret;
241
242 intel_uncore_write_fw(uncore, ILK_GDSR,
243 ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
244 ret = __intel_wait_for_register_fw(uncore, ILK_GDSR,
245 ILK_GRDOM_RESET_ENABLE, 0,
246 5000, 0,
247 NULL);
248 if (ret) {
249 GT_TRACE(gt, "Wait for render reset failed\n");
250 goto out;
251 }
252
253 intel_uncore_write_fw(uncore, ILK_GDSR,
254 ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
255 ret = __intel_wait_for_register_fw(uncore, ILK_GDSR,
256 ILK_GRDOM_RESET_ENABLE, 0,
257 5000, 0,
258 NULL);
259 if (ret) {
260 GT_TRACE(gt, "Wait for media reset failed\n");
261 goto out;
262 }
263
264out:
265 intel_uncore_write_fw(uncore, ILK_GDSR, 0);
266 intel_uncore_posting_read_fw(uncore, ILK_GDSR);
267 return ret;
268}
269
270
271static int gen6_hw_domain_reset(struct intel_gt *gt, u32 hw_domain_mask)
272{
273 struct intel_uncore *uncore = gt->uncore;
274 int err;
275
276
277
278
279
280
281 intel_uncore_write_fw(uncore, GEN6_GDRST, hw_domain_mask);
282
283
284 err = __intel_wait_for_register_fw(uncore,
285 GEN6_GDRST, hw_domain_mask, 0,
286 500, 0,
287 NULL);
288 if (err)
289 GT_TRACE(gt,
290 "Wait for 0x%08x engines reset failed\n",
291 hw_domain_mask);
292
293 return err;
294}
295
296static int gen6_reset_engines(struct intel_gt *gt,
297 intel_engine_mask_t engine_mask,
298 unsigned int retry)
299{
300 static const u32 hw_engine_mask[] = {
301 [RCS0] = GEN6_GRDOM_RENDER,
302 [BCS0] = GEN6_GRDOM_BLT,
303 [VCS0] = GEN6_GRDOM_MEDIA,
304 [VCS1] = GEN8_GRDOM_MEDIA2,
305 [VECS0] = GEN6_GRDOM_VECS,
306 };
307 struct intel_engine_cs *engine;
308 u32 hw_mask;
309
310 if (engine_mask == ALL_ENGINES) {
311 hw_mask = GEN6_GRDOM_FULL;
312 } else {
313 intel_engine_mask_t tmp;
314
315 hw_mask = 0;
316 for_each_engine_masked(engine, gt, engine_mask, tmp) {
317 GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
318 hw_mask |= hw_engine_mask[engine->id];
319 }
320 }
321
322 return gen6_hw_domain_reset(gt, hw_mask);
323}
324
325static struct intel_engine_cs *find_sfc_paired_vecs_engine(struct intel_engine_cs *engine)
326{
327 int vecs_id;
328
329 GEM_BUG_ON(engine->class != VIDEO_DECODE_CLASS);
330
331 vecs_id = _VECS((engine->instance) / 2);
332
333 return engine->gt->engine[vecs_id];
334}
335
336struct sfc_lock_data {
337 i915_reg_t lock_reg;
338 i915_reg_t ack_reg;
339 i915_reg_t usage_reg;
340 u32 lock_bit;
341 u32 ack_bit;
342 u32 usage_bit;
343 u32 reset_bit;
344};
345
346static void get_sfc_forced_lock_data(struct intel_engine_cs *engine,
347 struct sfc_lock_data *sfc_lock)
348{
349 switch (engine->class) {
350 default:
351 MISSING_CASE(engine->class);
352 fallthrough;
353 case VIDEO_DECODE_CLASS:
354 sfc_lock->lock_reg = GEN11_VCS_SFC_FORCED_LOCK(engine);
355 sfc_lock->lock_bit = GEN11_VCS_SFC_FORCED_LOCK_BIT;
356
357 sfc_lock->ack_reg = GEN11_VCS_SFC_LOCK_STATUS(engine);
358 sfc_lock->ack_bit = GEN11_VCS_SFC_LOCK_ACK_BIT;
359
360 sfc_lock->usage_reg = GEN11_VCS_SFC_LOCK_STATUS(engine);
361 sfc_lock->usage_bit = GEN11_VCS_SFC_USAGE_BIT;
362 sfc_lock->reset_bit = GEN11_VCS_SFC_RESET_BIT(engine->instance);
363
364 break;
365 case VIDEO_ENHANCEMENT_CLASS:
366 sfc_lock->lock_reg = GEN11_VECS_SFC_FORCED_LOCK(engine);
367 sfc_lock->lock_bit = GEN11_VECS_SFC_FORCED_LOCK_BIT;
368
369 sfc_lock->ack_reg = GEN11_VECS_SFC_LOCK_ACK(engine);
370 sfc_lock->ack_bit = GEN11_VECS_SFC_LOCK_ACK_BIT;
371
372 sfc_lock->usage_reg = GEN11_VECS_SFC_USAGE(engine);
373 sfc_lock->usage_bit = GEN11_VECS_SFC_USAGE_BIT;
374 sfc_lock->reset_bit = GEN11_VECS_SFC_RESET_BIT(engine->instance);
375
376 break;
377 }
378}
379
380static int gen11_lock_sfc(struct intel_engine_cs *engine,
381 u32 *reset_mask,
382 u32 *unlock_mask)
383{
384 struct intel_uncore *uncore = engine->uncore;
385 u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;
386 struct sfc_lock_data sfc_lock;
387 bool lock_obtained, lock_to_other = false;
388 int ret;
389
390 switch (engine->class) {
391 case VIDEO_DECODE_CLASS:
392 if ((BIT(engine->instance) & vdbox_sfc_access) == 0)
393 return 0;
394
395 fallthrough;
396 case VIDEO_ENHANCEMENT_CLASS:
397 get_sfc_forced_lock_data(engine, &sfc_lock);
398
399 break;
400 default:
401 return 0;
402 }
403
404 if (!(intel_uncore_read_fw(uncore, sfc_lock.usage_reg) & sfc_lock.usage_bit)) {
405 struct intel_engine_cs *paired_vecs;
406
407 if (engine->class != VIDEO_DECODE_CLASS ||
408 GRAPHICS_VER(engine->i915) != 12)
409 return 0;
410
411
412
413
414
415
416
417
418 if (!(intel_uncore_read_fw(uncore,
419 GEN12_HCP_SFC_LOCK_STATUS(engine)) &
420 GEN12_HCP_SFC_USAGE_BIT))
421 return 0;
422
423 paired_vecs = find_sfc_paired_vecs_engine(engine);
424 get_sfc_forced_lock_data(paired_vecs, &sfc_lock);
425 lock_to_other = true;
426 *unlock_mask |= paired_vecs->mask;
427 } else {
428 *unlock_mask |= engine->mask;
429 }
430
431
432
433
434
435
436
437
438 rmw_set_fw(uncore, sfc_lock.lock_reg, sfc_lock.lock_bit);
439
440 ret = __intel_wait_for_register_fw(uncore,
441 sfc_lock.ack_reg,
442 sfc_lock.ack_bit,
443 sfc_lock.ack_bit,
444 1000, 0, NULL);
445
446
447
448
449
450
451
452
453
454
455
456
457
458 lock_obtained = (intel_uncore_read_fw(uncore, sfc_lock.usage_reg) &
459 sfc_lock.usage_bit) != 0;
460 if (lock_obtained == lock_to_other)
461 return 0;
462
463 if (ret) {
464 ENGINE_TRACE(engine, "Wait for SFC forced lock ack failed\n");
465 return ret;
466 }
467
468 *reset_mask |= sfc_lock.reset_bit;
469 return 0;
470}
471
472static void gen11_unlock_sfc(struct intel_engine_cs *engine)
473{
474 struct intel_uncore *uncore = engine->uncore;
475 u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;
476 struct sfc_lock_data sfc_lock = {};
477
478 if (engine->class != VIDEO_DECODE_CLASS &&
479 engine->class != VIDEO_ENHANCEMENT_CLASS)
480 return;
481
482 if (engine->class == VIDEO_DECODE_CLASS &&
483 (BIT(engine->instance) & vdbox_sfc_access) == 0)
484 return;
485
486 get_sfc_forced_lock_data(engine, &sfc_lock);
487
488 rmw_clear_fw(uncore, sfc_lock.lock_reg, sfc_lock.lock_bit);
489}
490
491static int gen11_reset_engines(struct intel_gt *gt,
492 intel_engine_mask_t engine_mask,
493 unsigned int retry)
494{
495 static const u32 hw_engine_mask[] = {
496 [RCS0] = GEN11_GRDOM_RENDER,
497 [BCS0] = GEN11_GRDOM_BLT,
498 [VCS0] = GEN11_GRDOM_MEDIA,
499 [VCS1] = GEN11_GRDOM_MEDIA2,
500 [VCS2] = GEN11_GRDOM_MEDIA3,
501 [VCS3] = GEN11_GRDOM_MEDIA4,
502 [VCS4] = GEN11_GRDOM_MEDIA5,
503 [VCS5] = GEN11_GRDOM_MEDIA6,
504 [VCS6] = GEN11_GRDOM_MEDIA7,
505 [VCS7] = GEN11_GRDOM_MEDIA8,
506 [VECS0] = GEN11_GRDOM_VECS,
507 [VECS1] = GEN11_GRDOM_VECS2,
508 [VECS2] = GEN11_GRDOM_VECS3,
509 [VECS3] = GEN11_GRDOM_VECS4,
510 };
511 struct intel_engine_cs *engine;
512 intel_engine_mask_t tmp;
513 u32 reset_mask, unlock_mask = 0;
514 int ret;
515
516 if (engine_mask == ALL_ENGINES) {
517 reset_mask = GEN11_GRDOM_FULL;
518 } else {
519 reset_mask = 0;
520 for_each_engine_masked(engine, gt, engine_mask, tmp) {
521 GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
522 reset_mask |= hw_engine_mask[engine->id];
523 ret = gen11_lock_sfc(engine, &reset_mask, &unlock_mask);
524 if (ret)
525 goto sfc_unlock;
526 }
527 }
528
529 ret = gen6_hw_domain_reset(gt, reset_mask);
530
531sfc_unlock:
532
533
534
535
536
537
538
539
540
541
542
543 for_each_engine_masked(engine, gt, unlock_mask, tmp)
544 gen11_unlock_sfc(engine);
545
546 return ret;
547}
548
549static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
550{
551 struct intel_uncore *uncore = engine->uncore;
552 const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base);
553 u32 request, mask, ack;
554 int ret;
555
556 if (I915_SELFTEST_ONLY(should_fail(&engine->reset_timeout, 1)))
557 return -ETIMEDOUT;
558
559 ack = intel_uncore_read_fw(uncore, reg);
560 if (ack & RESET_CTL_CAT_ERROR) {
561
562
563
564
565 request = RESET_CTL_CAT_ERROR;
566 mask = RESET_CTL_CAT_ERROR;
567
568
569 ack = 0;
570 } else if (!(ack & RESET_CTL_READY_TO_RESET)) {
571 request = RESET_CTL_REQUEST_RESET;
572 mask = RESET_CTL_READY_TO_RESET;
573 ack = RESET_CTL_READY_TO_RESET;
574 } else {
575 return 0;
576 }
577
578 intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request));
579 ret = __intel_wait_for_register_fw(uncore, reg, mask, ack,
580 700, 0, NULL);
581 if (ret)
582 drm_err(&engine->i915->drm,
583 "%s reset request timed out: {request: %08x, RESET_CTL: %08x}\n",
584 engine->name, request,
585 intel_uncore_read_fw(uncore, reg));
586
587 return ret;
588}
589
590static void gen8_engine_reset_cancel(struct intel_engine_cs *engine)
591{
592 intel_uncore_write_fw(engine->uncore,
593 RING_RESET_CTL(engine->mmio_base),
594 _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
595}
596
597static int gen8_reset_engines(struct intel_gt *gt,
598 intel_engine_mask_t engine_mask,
599 unsigned int retry)
600{
601 struct intel_engine_cs *engine;
602 const bool reset_non_ready = retry >= 1;
603 intel_engine_mask_t tmp;
604 int ret;
605
606 for_each_engine_masked(engine, gt, engine_mask, tmp) {
607 ret = gen8_engine_reset_prepare(engine);
608 if (ret && !reset_non_ready)
609 goto skip_reset;
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624 }
625
626 if (GRAPHICS_VER(gt->i915) >= 11)
627 ret = gen11_reset_engines(gt, engine_mask, retry);
628 else
629 ret = gen6_reset_engines(gt, engine_mask, retry);
630
631skip_reset:
632 for_each_engine_masked(engine, gt, engine_mask, tmp)
633 gen8_engine_reset_cancel(engine);
634
635 return ret;
636}
637
638static int mock_reset(struct intel_gt *gt,
639 intel_engine_mask_t mask,
640 unsigned int retry)
641{
642 return 0;
643}
644
645typedef int (*reset_func)(struct intel_gt *,
646 intel_engine_mask_t engine_mask,
647 unsigned int retry);
648
649static reset_func intel_get_gpu_reset(const struct intel_gt *gt)
650{
651 struct drm_i915_private *i915 = gt->i915;
652
653 if (is_mock_gt(gt))
654 return mock_reset;
655 else if (GRAPHICS_VER(i915) >= 8)
656 return gen8_reset_engines;
657 else if (GRAPHICS_VER(i915) >= 6)
658 return gen6_reset_engines;
659 else if (GRAPHICS_VER(i915) >= 5)
660 return ilk_do_reset;
661 else if (IS_G4X(i915))
662 return g4x_do_reset;
663 else if (IS_G33(i915) || IS_PINEVIEW(i915))
664 return g33_do_reset;
665 else if (GRAPHICS_VER(i915) >= 3)
666 return i915_do_reset;
667 else
668 return NULL;
669}
670
671int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask)
672{
673 const int retries = engine_mask == ALL_ENGINES ? RESET_MAX_RETRIES : 1;
674 reset_func reset;
675 int ret = -ETIMEDOUT;
676 int retry;
677
678 reset = intel_get_gpu_reset(gt);
679 if (!reset)
680 return -ENODEV;
681
682
683
684
685
686 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
687 for (retry = 0; ret == -ETIMEDOUT && retry < retries; retry++) {
688 GT_TRACE(gt, "engine_mask=%x\n", engine_mask);
689 preempt_disable();
690 ret = reset(gt, engine_mask, retry);
691 preempt_enable();
692 }
693 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
694
695 return ret;
696}
697
698bool intel_has_gpu_reset(const struct intel_gt *gt)
699{
700 if (!gt->i915->params.reset)
701 return NULL;
702
703 return intel_get_gpu_reset(gt);
704}
705
706bool intel_has_reset_engine(const struct intel_gt *gt)
707{
708 if (gt->i915->params.reset < 2)
709 return false;
710
711 return INTEL_INFO(gt->i915)->has_reset_engine;
712}
713
714int intel_reset_guc(struct intel_gt *gt)
715{
716 u32 guc_domain =
717 GRAPHICS_VER(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
718 int ret;
719
720 GEM_BUG_ON(!HAS_GT_UC(gt->i915));
721
722 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
723 ret = gen6_hw_domain_reset(gt, guc_domain);
724 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
725
726 return ret;
727}
728
729
730
731
732
733static void reset_prepare_engine(struct intel_engine_cs *engine)
734{
735
736
737
738
739
740
741
742 intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);
743 if (engine->reset.prepare)
744 engine->reset.prepare(engine);
745}
746
747static void revoke_mmaps(struct intel_gt *gt)
748{
749 int i;
750
751 for (i = 0; i < gt->ggtt->num_fences; i++) {
752 struct drm_vma_offset_node *node;
753 struct i915_vma *vma;
754 u64 vma_offset;
755
756 vma = READ_ONCE(gt->ggtt->fence_regs[i].vma);
757 if (!vma)
758 continue;
759
760 if (!i915_vma_has_userfault(vma))
761 continue;
762
763 GEM_BUG_ON(vma->fence != >->ggtt->fence_regs[i]);
764
765 if (!vma->mmo)
766 continue;
767
768 node = &vma->mmo->vma_node;
769 vma_offset = vma->ggtt_view.partial.offset << PAGE_SHIFT;
770
771 unmap_mapping_range(gt->i915->drm.anon_inode->i_mapping,
772 drm_vma_node_offset_addr(node) + vma_offset,
773 vma->size,
774 1);
775 }
776}
777
778static intel_engine_mask_t reset_prepare(struct intel_gt *gt)
779{
780 struct intel_engine_cs *engine;
781 intel_engine_mask_t awake = 0;
782 enum intel_engine_id id;
783
784 for_each_engine(engine, gt, id) {
785 if (intel_engine_pm_get_if_awake(engine))
786 awake |= engine->mask;
787 reset_prepare_engine(engine);
788 }
789
790 intel_uc_reset_prepare(>->uc);
791
792 return awake;
793}
794
795static void gt_revoke(struct intel_gt *gt)
796{
797 revoke_mmaps(gt);
798}
799
800static int gt_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
801{
802 struct intel_engine_cs *engine;
803 enum intel_engine_id id;
804 int err;
805
806
807
808
809
810 err = i915_ggtt_enable_hw(gt->i915);
811 if (err)
812 return err;
813
814 local_bh_disable();
815 for_each_engine(engine, gt, id)
816 __intel_engine_reset(engine, stalled_mask & engine->mask);
817 local_bh_enable();
818
819 intel_uc_reset(>->uc, true);
820
821 intel_ggtt_restore_fences(gt->ggtt);
822
823 return err;
824}
825
826static void reset_finish_engine(struct intel_engine_cs *engine)
827{
828 if (engine->reset.finish)
829 engine->reset.finish(engine);
830 intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL);
831
832 intel_engine_signal_breadcrumbs(engine);
833}
834
835static void reset_finish(struct intel_gt *gt, intel_engine_mask_t awake)
836{
837 struct intel_engine_cs *engine;
838 enum intel_engine_id id;
839
840 for_each_engine(engine, gt, id) {
841 reset_finish_engine(engine);
842 if (awake & engine->mask)
843 intel_engine_pm_put(engine);
844 }
845
846 intel_uc_reset_finish(>->uc);
847}
848
849static void nop_submit_request(struct i915_request *request)
850{
851 RQ_TRACE(request, "-EIO\n");
852
853 request = i915_request_mark_eio(request);
854 if (request) {
855 i915_request_submit(request);
856 intel_engine_signal_breadcrumbs(request->engine);
857
858 i915_request_put(request);
859 }
860}
861
862static void __intel_gt_set_wedged(struct intel_gt *gt)
863{
864 struct intel_engine_cs *engine;
865 intel_engine_mask_t awake;
866 enum intel_engine_id id;
867
868 if (test_bit(I915_WEDGED, >->reset.flags))
869 return;
870
871 GT_TRACE(gt, "start\n");
872
873
874
875
876
877
878 awake = reset_prepare(gt);
879
880
881 if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
882 __intel_gt_reset(gt, ALL_ENGINES);
883
884 for_each_engine(engine, gt, id)
885 engine->submit_request = nop_submit_request;
886
887
888
889
890
891
892 synchronize_rcu_expedited();
893 set_bit(I915_WEDGED, >->reset.flags);
894
895
896 local_bh_disable();
897 for_each_engine(engine, gt, id)
898 if (engine->reset.cancel)
899 engine->reset.cancel(engine);
900 intel_uc_cancel_requests(>->uc);
901 local_bh_enable();
902
903 reset_finish(gt, awake);
904
905 GT_TRACE(gt, "end\n");
906}
907
908void intel_gt_set_wedged(struct intel_gt *gt)
909{
910 intel_wakeref_t wakeref;
911
912 if (test_bit(I915_WEDGED, >->reset.flags))
913 return;
914
915 wakeref = intel_runtime_pm_get(gt->uncore->rpm);
916 mutex_lock(>->reset.mutex);
917
918 if (GEM_SHOW_DEBUG()) {
919 struct drm_printer p = drm_debug_printer(__func__);
920 struct intel_engine_cs *engine;
921 enum intel_engine_id id;
922
923 drm_printf(&p, "called from %pS\n", (void *)_RET_IP_);
924 for_each_engine(engine, gt, id) {
925 if (intel_engine_is_idle(engine))
926 continue;
927
928 intel_engine_dump(engine, &p, "%s\n", engine->name);
929 }
930 }
931
932 __intel_gt_set_wedged(gt);
933
934 mutex_unlock(>->reset.mutex);
935 intel_runtime_pm_put(gt->uncore->rpm, wakeref);
936}
937
938static bool __intel_gt_unset_wedged(struct intel_gt *gt)
939{
940 struct intel_gt_timelines *timelines = >->timelines;
941 struct intel_timeline *tl;
942 bool ok;
943
944 if (!test_bit(I915_WEDGED, >->reset.flags))
945 return true;
946
947
948 if (intel_gt_has_unrecoverable_error(gt))
949 return false;
950
951 GT_TRACE(gt, "start\n");
952
953
954
955
956
957
958
959
960
961
962
963 spin_lock(&timelines->lock);
964 list_for_each_entry(tl, &timelines->active_list, link) {
965 struct dma_fence *fence;
966
967 fence = i915_active_fence_get(&tl->last_request);
968 if (!fence)
969 continue;
970
971 spin_unlock(&timelines->lock);
972
973
974
975
976
977
978
979
980 dma_fence_default_wait(fence, false, MAX_SCHEDULE_TIMEOUT);
981 dma_fence_put(fence);
982
983
984 spin_lock(&timelines->lock);
985 tl = list_entry(&timelines->active_list, typeof(*tl), link);
986 }
987 spin_unlock(&timelines->lock);
988
989
990 ok = !HAS_EXECLISTS(gt->i915);
991 if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
992 ok = __intel_gt_reset(gt, ALL_ENGINES) == 0;
993 if (!ok) {
994
995
996
997
998 add_taint_for_CI(gt->i915, TAINT_WARN);
999 return false;
1000 }
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011 intel_engines_reset_default_submission(gt);
1012
1013 GT_TRACE(gt, "end\n");
1014
1015 smp_mb__before_atomic();
1016 clear_bit(I915_WEDGED, >->reset.flags);
1017
1018 return true;
1019}
1020
1021bool intel_gt_unset_wedged(struct intel_gt *gt)
1022{
1023 bool result;
1024
1025 mutex_lock(>->reset.mutex);
1026 result = __intel_gt_unset_wedged(gt);
1027 mutex_unlock(>->reset.mutex);
1028
1029 return result;
1030}
1031
1032static int do_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
1033{
1034 int err, i;
1035
1036 err = __intel_gt_reset(gt, ALL_ENGINES);
1037 for (i = 0; err && i < RESET_MAX_RETRIES; i++) {
1038 msleep(10 * (i + 1));
1039 err = __intel_gt_reset(gt, ALL_ENGINES);
1040 }
1041 if (err)
1042 return err;
1043
1044 return gt_reset(gt, stalled_mask);
1045}
1046
1047static int resume(struct intel_gt *gt)
1048{
1049 struct intel_engine_cs *engine;
1050 enum intel_engine_id id;
1051 int ret;
1052
1053 for_each_engine(engine, gt, id) {
1054 ret = intel_engine_resume(engine);
1055 if (ret)
1056 return ret;
1057 }
1058
1059 return 0;
1060}
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079void intel_gt_reset(struct intel_gt *gt,
1080 intel_engine_mask_t stalled_mask,
1081 const char *reason)
1082{
1083 intel_engine_mask_t awake;
1084 int ret;
1085
1086 GT_TRACE(gt, "flags=%lx\n", gt->reset.flags);
1087
1088 might_sleep();
1089 GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, >->reset.flags));
1090
1091
1092
1093
1094
1095 gt_revoke(gt);
1096
1097 mutex_lock(>->reset.mutex);
1098
1099
1100 if (!__intel_gt_unset_wedged(gt))
1101 goto unlock;
1102
1103 if (reason)
1104 drm_notice(>->i915->drm,
1105 "Resetting chip for %s\n", reason);
1106 atomic_inc(>->i915->gpu_error.reset_count);
1107
1108 awake = reset_prepare(gt);
1109
1110 if (!intel_has_gpu_reset(gt)) {
1111 if (gt->i915->params.reset)
1112 drm_err(>->i915->drm, "GPU reset not supported\n");
1113 else
1114 drm_dbg(>->i915->drm, "GPU reset disabled\n");
1115 goto error;
1116 }
1117
1118 if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
1119 intel_runtime_pm_disable_interrupts(gt->i915);
1120
1121 if (do_reset(gt, stalled_mask)) {
1122 drm_err(>->i915->drm, "Failed to reset chip\n");
1123 goto taint;
1124 }
1125
1126 if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
1127 intel_runtime_pm_enable_interrupts(gt->i915);
1128
1129 intel_overlay_reset(gt->i915);
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139 ret = intel_gt_init_hw(gt);
1140 if (ret) {
1141 drm_err(>->i915->drm,
1142 "Failed to initialise HW following reset (%d)\n",
1143 ret);
1144 goto taint;
1145 }
1146
1147 ret = resume(gt);
1148 if (ret)
1149 goto taint;
1150
1151finish:
1152 reset_finish(gt, awake);
1153unlock:
1154 mutex_unlock(>->reset.mutex);
1155 return;
1156
1157taint:
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170 add_taint_for_CI(gt->i915, TAINT_WARN);
1171error:
1172 __intel_gt_set_wedged(gt);
1173 goto finish;
1174}
1175
1176static int intel_gt_reset_engine(struct intel_engine_cs *engine)
1177{
1178 return __intel_gt_reset(engine->gt, engine->mask);
1179}
1180
1181int __intel_engine_reset_bh(struct intel_engine_cs *engine, const char *msg)
1182{
1183 struct intel_gt *gt = engine->gt;
1184 int ret;
1185
1186 ENGINE_TRACE(engine, "flags=%lx\n", gt->reset.flags);
1187 GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, >->reset.flags));
1188
1189 if (intel_engine_uses_guc(engine))
1190 return -ENODEV;
1191
1192 if (!intel_engine_pm_get_if_awake(engine))
1193 return 0;
1194
1195 reset_prepare_engine(engine);
1196
1197 if (msg)
1198 drm_notice(&engine->i915->drm,
1199 "Resetting %s for %s\n", engine->name, msg);
1200 atomic_inc(&engine->i915->gpu_error.reset_engine_count[engine->uabi_class]);
1201
1202 ret = intel_gt_reset_engine(engine);
1203 if (ret) {
1204
1205 ENGINE_TRACE(engine, "Failed to reset %s, err: %d\n", engine->name, ret);
1206 goto out;
1207 }
1208
1209
1210
1211
1212
1213
1214 __intel_engine_reset(engine, true);
1215
1216
1217
1218
1219
1220
1221 ret = intel_engine_resume(engine);
1222
1223out:
1224 intel_engine_cancel_stop_cs(engine);
1225 reset_finish_engine(engine);
1226 intel_engine_pm_put_async(engine);
1227 return ret;
1228}
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243int intel_engine_reset(struct intel_engine_cs *engine, const char *msg)
1244{
1245 int err;
1246
1247 local_bh_disable();
1248 err = __intel_engine_reset_bh(engine, msg);
1249 local_bh_enable();
1250
1251 return err;
1252}
1253
1254static void intel_gt_reset_global(struct intel_gt *gt,
1255 u32 engine_mask,
1256 const char *reason)
1257{
1258 struct kobject *kobj = >->i915->drm.primary->kdev->kobj;
1259 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1260 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1261 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
1262 struct intel_wedge_me w;
1263
1264 kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
1265
1266 GT_TRACE(gt, "resetting chip, engines=%x\n", engine_mask);
1267 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
1268
1269
1270 intel_wedge_on_timeout(&w, gt, 5 * HZ) {
1271 intel_display_prepare_reset(gt->i915);
1272
1273
1274 synchronize_srcu_expedited(>->reset.backoff_srcu);
1275
1276 intel_gt_reset(gt, engine_mask, reason);
1277
1278 intel_display_finish_reset(gt->i915);
1279 }
1280
1281 if (!test_bit(I915_WEDGED, >->reset.flags))
1282 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event);
1283}
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298void intel_gt_handle_error(struct intel_gt *gt,
1299 intel_engine_mask_t engine_mask,
1300 unsigned long flags,
1301 const char *fmt, ...)
1302{
1303 struct intel_engine_cs *engine;
1304 intel_wakeref_t wakeref;
1305 intel_engine_mask_t tmp;
1306 char error_msg[80];
1307 char *msg = NULL;
1308
1309 if (fmt) {
1310 va_list args;
1311
1312 va_start(args, fmt);
1313 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
1314 va_end(args);
1315
1316 msg = error_msg;
1317 }
1318
1319
1320
1321
1322
1323
1324
1325
1326 wakeref = intel_runtime_pm_get(gt->uncore->rpm);
1327
1328 engine_mask &= gt->info.engine_mask;
1329
1330 if (flags & I915_ERROR_CAPTURE) {
1331 i915_capture_error_state(gt, engine_mask);
1332 intel_gt_clear_error_registers(gt, engine_mask);
1333 }
1334
1335
1336
1337
1338
1339 if (!intel_uc_uses_guc_submission(>->uc) &&
1340 intel_has_reset_engine(gt) && !intel_gt_is_wedged(gt)) {
1341 local_bh_disable();
1342 for_each_engine_masked(engine, gt, engine_mask, tmp) {
1343 BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
1344 if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
1345 >->reset.flags))
1346 continue;
1347
1348 if (__intel_engine_reset_bh(engine, msg) == 0)
1349 engine_mask &= ~engine->mask;
1350
1351 clear_and_wake_up_bit(I915_RESET_ENGINE + engine->id,
1352 >->reset.flags);
1353 }
1354 local_bh_enable();
1355 }
1356
1357 if (!engine_mask)
1358 goto out;
1359
1360
1361 if (test_and_set_bit(I915_RESET_BACKOFF, >->reset.flags)) {
1362 wait_event(gt->reset.queue,
1363 !test_bit(I915_RESET_BACKOFF, >->reset.flags));
1364 goto out;
1365 }
1366
1367
1368 synchronize_rcu_expedited();
1369
1370
1371 for_each_engine(engine, gt, tmp) {
1372 while (test_and_set_bit(I915_RESET_ENGINE + engine->id,
1373 >->reset.flags))
1374 wait_on_bit(>->reset.flags,
1375 I915_RESET_ENGINE + engine->id,
1376 TASK_UNINTERRUPTIBLE);
1377 }
1378
1379 intel_gt_reset_global(gt, engine_mask, msg);
1380
1381 for_each_engine(engine, gt, tmp)
1382 clear_bit_unlock(I915_RESET_ENGINE + engine->id,
1383 >->reset.flags);
1384 clear_bit_unlock(I915_RESET_BACKOFF, >->reset.flags);
1385 smp_mb__after_atomic();
1386 wake_up_all(>->reset.queue);
1387
1388out:
1389 intel_runtime_pm_put(gt->uncore->rpm, wakeref);
1390}
1391
1392int intel_gt_reset_trylock(struct intel_gt *gt, int *srcu)
1393{
1394 might_lock(>->reset.backoff_srcu);
1395 might_sleep();
1396
1397 rcu_read_lock();
1398 while (test_bit(I915_RESET_BACKOFF, >->reset.flags)) {
1399 rcu_read_unlock();
1400
1401 if (wait_event_interruptible(gt->reset.queue,
1402 !test_bit(I915_RESET_BACKOFF,
1403 >->reset.flags)))
1404 return -EINTR;
1405
1406 rcu_read_lock();
1407 }
1408 *srcu = srcu_read_lock(>->reset.backoff_srcu);
1409 rcu_read_unlock();
1410
1411 return 0;
1412}
1413
1414void intel_gt_reset_unlock(struct intel_gt *gt, int tag)
1415__releases(>->reset.backoff_srcu)
1416{
1417 srcu_read_unlock(>->reset.backoff_srcu, tag);
1418}
1419
1420int intel_gt_terminally_wedged(struct intel_gt *gt)
1421{
1422 might_sleep();
1423
1424 if (!intel_gt_is_wedged(gt))
1425 return 0;
1426
1427 if (intel_gt_has_unrecoverable_error(gt))
1428 return -EIO;
1429
1430
1431 if (wait_event_interruptible(gt->reset.queue,
1432 !test_bit(I915_RESET_BACKOFF,
1433 >->reset.flags)))
1434 return -EINTR;
1435
1436 return intel_gt_is_wedged(gt) ? -EIO : 0;
1437}
1438
1439void intel_gt_set_wedged_on_init(struct intel_gt *gt)
1440{
1441 BUILD_BUG_ON(I915_RESET_ENGINE + I915_NUM_ENGINES >
1442 I915_WEDGED_ON_INIT);
1443 intel_gt_set_wedged(gt);
1444 set_bit(I915_WEDGED_ON_INIT, >->reset.flags);
1445
1446
1447 add_taint_for_CI(gt->i915, TAINT_WARN);
1448}
1449
1450void intel_gt_set_wedged_on_fini(struct intel_gt *gt)
1451{
1452 intel_gt_set_wedged(gt);
1453 set_bit(I915_WEDGED_ON_FINI, >->reset.flags);
1454 intel_gt_retire_requests(gt);
1455}
1456
1457void intel_gt_init_reset(struct intel_gt *gt)
1458{
1459 init_waitqueue_head(>->reset.queue);
1460 mutex_init(>->reset.mutex);
1461 init_srcu_struct(>->reset.backoff_srcu);
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472 i915_gem_shrinker_taints_mutex(gt->i915, >->reset.mutex);
1473
1474
1475 __set_bit(I915_WEDGED, >->reset.flags);
1476}
1477
1478void intel_gt_fini_reset(struct intel_gt *gt)
1479{
1480 cleanup_srcu_struct(>->reset.backoff_srcu);
1481}
1482
1483static void intel_wedge_me(struct work_struct *work)
1484{
1485 struct intel_wedge_me *w = container_of(work, typeof(*w), work.work);
1486
1487 drm_err(&w->gt->i915->drm,
1488 "%s timed out, cancelling all in-flight rendering.\n",
1489 w->name);
1490 intel_gt_set_wedged(w->gt);
1491}
1492
1493void __intel_init_wedge(struct intel_wedge_me *w,
1494 struct intel_gt *gt,
1495 long timeout,
1496 const char *name)
1497{
1498 w->gt = gt;
1499 w->name = name;
1500
1501 INIT_DELAYED_WORK_ONSTACK(&w->work, intel_wedge_me);
1502 schedule_delayed_work(&w->work, timeout);
1503}
1504
1505void __intel_fini_wedge(struct intel_wedge_me *w)
1506{
1507 cancel_delayed_work_sync(&w->work);
1508 destroy_delayed_work_on_stack(&w->work);
1509 w->gt = NULL;
1510}
1511
1512#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1513#include "selftest_reset.c"
1514#include "selftest_hangcheck.c"
1515#endif
1516