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29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31#include <linux/circ_buf.h>
32#include <linux/slab.h>
33#include <linux/sysrq.h>
34
35#include <drm/drm_drv.h>
36
37#include "display/intel_de.h"
38#include "display/intel_display_types.h"
39#include "display/intel_fifo_underrun.h"
40#include "display/intel_hotplug.h"
41#include "display/intel_lpe_audio.h"
42#include "display/intel_psr.h"
43
44#include "gt/intel_breadcrumbs.h"
45#include "gt/intel_gt.h"
46#include "gt/intel_gt_irq.h"
47#include "gt/intel_gt_pm_irq.h"
48#include "gt/intel_rps.h"
49
50#include "i915_drv.h"
51#include "i915_irq.h"
52#include "i915_trace.h"
53#include "intel_pm.h"
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68static inline void pmu_irq_stats(struct drm_i915_private *i915,
69 irqreturn_t res)
70{
71 if (unlikely(res != IRQ_HANDLED))
72 return;
73
74
75
76
77
78 WRITE_ONCE(i915->pmu.irq_count, i915->pmu.irq_count + 1);
79}
80
81typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
82typedef u32 (*hotplug_enables_func)(struct drm_i915_private *i915,
83 enum hpd_pin pin);
84
85static const u32 hpd_ilk[HPD_NUM_PINS] = {
86 [HPD_PORT_A] = DE_DP_A_HOTPLUG,
87};
88
89static const u32 hpd_ivb[HPD_NUM_PINS] = {
90 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
91};
92
93static const u32 hpd_bdw[HPD_NUM_PINS] = {
94 [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
95};
96
97static const u32 hpd_ibx[HPD_NUM_PINS] = {
98 [HPD_CRT] = SDE_CRT_HOTPLUG,
99 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
100 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
101 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
102 [HPD_PORT_D] = SDE_PORTD_HOTPLUG,
103};
104
105static const u32 hpd_cpt[HPD_NUM_PINS] = {
106 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
107 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
108 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
109 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
110 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
111};
112
113static const u32 hpd_spt[HPD_NUM_PINS] = {
114 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
115 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
116 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
117 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
118 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT,
119};
120
121static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
122 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
123 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
124 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
125 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
126 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
127 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN,
128};
129
130static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
131 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
132 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
133 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
134 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
135 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
136 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
137};
138
139static const u32 hpd_status_i915[HPD_NUM_PINS] = {
140 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
141 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
142 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
143 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
144 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
145 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
146};
147
148static const u32 hpd_bxt[HPD_NUM_PINS] = {
149 [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
150 [HPD_PORT_B] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_B),
151 [HPD_PORT_C] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_C),
152};
153
154static const u32 hpd_gen11[HPD_NUM_PINS] = {
155 [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(HPD_PORT_TC1) | GEN11_TBT_HOTPLUG(HPD_PORT_TC1),
156 [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(HPD_PORT_TC2) | GEN11_TBT_HOTPLUG(HPD_PORT_TC2),
157 [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(HPD_PORT_TC3) | GEN11_TBT_HOTPLUG(HPD_PORT_TC3),
158 [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(HPD_PORT_TC4) | GEN11_TBT_HOTPLUG(HPD_PORT_TC4),
159 [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(HPD_PORT_TC5) | GEN11_TBT_HOTPLUG(HPD_PORT_TC5),
160 [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(HPD_PORT_TC6) | GEN11_TBT_HOTPLUG(HPD_PORT_TC6),
161};
162
163static const u32 hpd_icp[HPD_NUM_PINS] = {
164 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
165 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
166 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
167 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1),
168 [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2),
169 [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3),
170 [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4),
171 [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5),
172 [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6),
173};
174
175static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
176 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
177 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
178 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
179 [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),
180};
181
182static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
183{
184 struct i915_hotplug *hpd = &dev_priv->hotplug;
185
186 if (HAS_GMCH(dev_priv)) {
187 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
188 IS_CHERRYVIEW(dev_priv))
189 hpd->hpd = hpd_status_g4x;
190 else
191 hpd->hpd = hpd_status_i915;
192 return;
193 }
194
195 if (DISPLAY_VER(dev_priv) >= 11)
196 hpd->hpd = hpd_gen11;
197 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
198 hpd->hpd = hpd_bxt;
199 else if (DISPLAY_VER(dev_priv) >= 8)
200 hpd->hpd = hpd_bdw;
201 else if (DISPLAY_VER(dev_priv) >= 7)
202 hpd->hpd = hpd_ivb;
203 else
204 hpd->hpd = hpd_ilk;
205
206 if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) &&
207 (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
208 return;
209
210 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
211 hpd->pch_hpd = hpd_sde_dg1;
212 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
213 hpd->pch_hpd = hpd_icp;
214 else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
215 hpd->pch_hpd = hpd_spt;
216 else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_CPT(dev_priv))
217 hpd->pch_hpd = hpd_cpt;
218 else if (HAS_PCH_IBX(dev_priv))
219 hpd->pch_hpd = hpd_ibx;
220 else
221 MISSING_CASE(INTEL_PCH_TYPE(dev_priv));
222}
223
224static void
225intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
226{
227 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
228
229 drm_crtc_handle_vblank(&crtc->base);
230}
231
232void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
233 i915_reg_t iir, i915_reg_t ier)
234{
235 intel_uncore_write(uncore, imr, 0xffffffff);
236 intel_uncore_posting_read(uncore, imr);
237
238 intel_uncore_write(uncore, ier, 0);
239
240
241 intel_uncore_write(uncore, iir, 0xffffffff);
242 intel_uncore_posting_read(uncore, iir);
243 intel_uncore_write(uncore, iir, 0xffffffff);
244 intel_uncore_posting_read(uncore, iir);
245}
246
247void gen2_irq_reset(struct intel_uncore *uncore)
248{
249 intel_uncore_write16(uncore, GEN2_IMR, 0xffff);
250 intel_uncore_posting_read16(uncore, GEN2_IMR);
251
252 intel_uncore_write16(uncore, GEN2_IER, 0);
253
254
255 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
256 intel_uncore_posting_read16(uncore, GEN2_IIR);
257 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
258 intel_uncore_posting_read16(uncore, GEN2_IIR);
259}
260
261
262
263
264static void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
265{
266 u32 val = intel_uncore_read(uncore, reg);
267
268 if (val == 0)
269 return;
270
271 drm_WARN(&uncore->i915->drm, 1,
272 "Interrupt register 0x%x is not zero: 0x%08x\n",
273 i915_mmio_reg_offset(reg), val);
274 intel_uncore_write(uncore, reg, 0xffffffff);
275 intel_uncore_posting_read(uncore, reg);
276 intel_uncore_write(uncore, reg, 0xffffffff);
277 intel_uncore_posting_read(uncore, reg);
278}
279
280static void gen2_assert_iir_is_zero(struct intel_uncore *uncore)
281{
282 u16 val = intel_uncore_read16(uncore, GEN2_IIR);
283
284 if (val == 0)
285 return;
286
287 drm_WARN(&uncore->i915->drm, 1,
288 "Interrupt register 0x%x is not zero: 0x%08x\n",
289 i915_mmio_reg_offset(GEN2_IIR), val);
290 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
291 intel_uncore_posting_read16(uncore, GEN2_IIR);
292 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
293 intel_uncore_posting_read16(uncore, GEN2_IIR);
294}
295
296void gen3_irq_init(struct intel_uncore *uncore,
297 i915_reg_t imr, u32 imr_val,
298 i915_reg_t ier, u32 ier_val,
299 i915_reg_t iir)
300{
301 gen3_assert_iir_is_zero(uncore, iir);
302
303 intel_uncore_write(uncore, ier, ier_val);
304 intel_uncore_write(uncore, imr, imr_val);
305 intel_uncore_posting_read(uncore, imr);
306}
307
308void gen2_irq_init(struct intel_uncore *uncore,
309 u32 imr_val, u32 ier_val)
310{
311 gen2_assert_iir_is_zero(uncore);
312
313 intel_uncore_write16(uncore, GEN2_IER, ier_val);
314 intel_uncore_write16(uncore, GEN2_IMR, imr_val);
315 intel_uncore_posting_read16(uncore, GEN2_IMR);
316}
317
318
319static inline void
320i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
321 u32 mask,
322 u32 bits)
323{
324 u32 val;
325
326 lockdep_assert_held(&dev_priv->irq_lock);
327 drm_WARN_ON(&dev_priv->drm, bits & ~mask);
328
329 val = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_EN);
330 val &= ~mask;
331 val |= bits;
332 intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_EN, val);
333}
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346
347void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
348 u32 mask,
349 u32 bits)
350{
351 spin_lock_irq(&dev_priv->irq_lock);
352 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
353 spin_unlock_irq(&dev_priv->irq_lock);
354}
355
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361
362void ilk_update_display_irq(struct drm_i915_private *dev_priv,
363 u32 interrupt_mask,
364 u32 enabled_irq_mask)
365{
366 u32 new_val;
367
368 lockdep_assert_held(&dev_priv->irq_lock);
369 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
370
371 new_val = dev_priv->irq_mask;
372 new_val &= ~interrupt_mask;
373 new_val |= (~enabled_irq_mask & interrupt_mask);
374
375 if (new_val != dev_priv->irq_mask &&
376 !drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) {
377 dev_priv->irq_mask = new_val;
378 intel_uncore_write(&dev_priv->uncore, DEIMR, dev_priv->irq_mask);
379 intel_uncore_posting_read(&dev_priv->uncore, DEIMR);
380 }
381}
382
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387
388
389static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
390 u32 interrupt_mask,
391 u32 enabled_irq_mask)
392{
393 u32 new_val;
394 u32 old_val;
395
396 lockdep_assert_held(&dev_priv->irq_lock);
397
398 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
399
400 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
401 return;
402
403 old_val = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IMR);
404
405 new_val = old_val;
406 new_val &= ~interrupt_mask;
407 new_val |= (~enabled_irq_mask & interrupt_mask);
408
409 if (new_val != old_val) {
410 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IMR, new_val);
411 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PORT_IMR);
412 }
413}
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420
421
422void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
423 enum pipe pipe,
424 u32 interrupt_mask,
425 u32 enabled_irq_mask)
426{
427 u32 new_val;
428
429 lockdep_assert_held(&dev_priv->irq_lock);
430
431 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
432
433 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
434 return;
435
436 new_val = dev_priv->de_irq_mask[pipe];
437 new_val &= ~interrupt_mask;
438 new_val |= (~enabled_irq_mask & interrupt_mask);
439
440 if (new_val != dev_priv->de_irq_mask[pipe]) {
441 dev_priv->de_irq_mask[pipe] = new_val;
442 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
443 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe));
444 }
445}
446
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450
451
452
453void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
454 u32 interrupt_mask,
455 u32 enabled_irq_mask)
456{
457 u32 sdeimr = intel_uncore_read(&dev_priv->uncore, SDEIMR);
458 sdeimr &= ~interrupt_mask;
459 sdeimr |= (~enabled_irq_mask & interrupt_mask);
460
461 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
462
463 lockdep_assert_held(&dev_priv->irq_lock);
464
465 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
466 return;
467
468 intel_uncore_write(&dev_priv->uncore, SDEIMR, sdeimr);
469 intel_uncore_posting_read(&dev_priv->uncore, SDEIMR);
470}
471
472u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
473 enum pipe pipe)
474{
475 u32 status_mask = dev_priv->pipestat_irq_mask[pipe];
476 u32 enable_mask = status_mask << 16;
477
478 lockdep_assert_held(&dev_priv->irq_lock);
479
480 if (DISPLAY_VER(dev_priv) < 5)
481 goto out;
482
483
484
485
486
487 if (drm_WARN_ON_ONCE(&dev_priv->drm,
488 status_mask & PIPE_A_PSR_STATUS_VLV))
489 return 0;
490
491
492
493
494 if (drm_WARN_ON_ONCE(&dev_priv->drm,
495 status_mask & PIPE_B_PSR_STATUS_VLV))
496 return 0;
497
498 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
499 SPRITE0_FLIP_DONE_INT_EN_VLV |
500 SPRITE1_FLIP_DONE_INT_EN_VLV);
501 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
502 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
503 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
504 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
505
506out:
507 drm_WARN_ONCE(&dev_priv->drm,
508 enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
509 status_mask & ~PIPESTAT_INT_STATUS_MASK,
510 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
511 pipe_name(pipe), enable_mask, status_mask);
512
513 return enable_mask;
514}
515
516void i915_enable_pipestat(struct drm_i915_private *dev_priv,
517 enum pipe pipe, u32 status_mask)
518{
519 i915_reg_t reg = PIPESTAT(pipe);
520 u32 enable_mask;
521
522 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
523 "pipe %c: status_mask=0x%x\n",
524 pipe_name(pipe), status_mask);
525
526 lockdep_assert_held(&dev_priv->irq_lock);
527 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
528
529 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask)
530 return;
531
532 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
533 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
534
535 intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask);
536 intel_uncore_posting_read(&dev_priv->uncore, reg);
537}
538
539void i915_disable_pipestat(struct drm_i915_private *dev_priv,
540 enum pipe pipe, u32 status_mask)
541{
542 i915_reg_t reg = PIPESTAT(pipe);
543 u32 enable_mask;
544
545 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
546 "pipe %c: status_mask=0x%x\n",
547 pipe_name(pipe), status_mask);
548
549 lockdep_assert_held(&dev_priv->irq_lock);
550 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
551
552 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0)
553 return;
554
555 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
556 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
557
558 intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask);
559 intel_uncore_posting_read(&dev_priv->uncore, reg);
560}
561
562static bool i915_has_asle(struct drm_i915_private *dev_priv)
563{
564 if (!dev_priv->opregion.asle)
565 return false;
566
567 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
568}
569
570
571
572
573
574static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
575{
576 if (!i915_has_asle(dev_priv))
577 return;
578
579 spin_lock_irq(&dev_priv->irq_lock);
580
581 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
582 if (DISPLAY_VER(dev_priv) >= 4)
583 i915_enable_pipestat(dev_priv, PIPE_A,
584 PIPE_LEGACY_BLC_EVENT_STATUS);
585
586 spin_unlock_irq(&dev_priv->irq_lock);
587}
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642u32 i915_get_vblank_counter(struct drm_crtc *crtc)
643{
644 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
645 struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
646 const struct drm_display_mode *mode = &vblank->hwmode;
647 enum pipe pipe = to_intel_crtc(crtc)->pipe;
648 i915_reg_t high_frame, low_frame;
649 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
650 unsigned long irqflags;
651
652
653
654
655
656
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658
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660
661
662
663 if (!vblank->max_vblank_count)
664 return 0;
665
666 htotal = mode->crtc_htotal;
667 hsync_start = mode->crtc_hsync_start;
668 vbl_start = mode->crtc_vblank_start;
669 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
670 vbl_start = DIV_ROUND_UP(vbl_start, 2);
671
672
673 vbl_start *= htotal;
674
675
676 vbl_start -= htotal - hsync_start;
677
678 high_frame = PIPEFRAME(pipe);
679 low_frame = PIPEFRAMEPIXEL(pipe);
680
681 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
682
683
684
685
686
687
688 do {
689 high1 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK;
690 low = intel_de_read_fw(dev_priv, low_frame);
691 high2 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK;
692 } while (high1 != high2);
693
694 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
695
696 high1 >>= PIPE_FRAME_HIGH_SHIFT;
697 pixel = low & PIPE_PIXEL_MASK;
698 low >>= PIPE_FRAME_LOW_SHIFT;
699
700
701
702
703
704
705 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
706}
707
708u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
709{
710 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
711 struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
712 enum pipe pipe = to_intel_crtc(crtc)->pipe;
713
714 if (!vblank->max_vblank_count)
715 return 0;
716
717 return intel_uncore_read(&dev_priv->uncore, PIPE_FRMCOUNT_G4X(pipe));
718}
719
720static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc)
721{
722 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
723 struct drm_vblank_crtc *vblank =
724 &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
725 const struct drm_display_mode *mode = &vblank->hwmode;
726 u32 htotal = mode->crtc_htotal;
727 u32 clock = mode->crtc_clock;
728 u32 scan_prev_time, scan_curr_time, scan_post_time;
729
730
731
732
733
734
735
736 do {
737
738
739
740
741
742 scan_prev_time = intel_de_read_fw(dev_priv,
743 PIPE_FRMTMSTMP(crtc->pipe));
744
745
746
747
748
749 scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR);
750
751 scan_post_time = intel_de_read_fw(dev_priv,
752 PIPE_FRMTMSTMP(crtc->pipe));
753 } while (scan_post_time != scan_prev_time);
754
755 return div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
756 clock), 1000 * htotal);
757}
758
759
760
761
762
763
764
765
766
767static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
768{
769 struct drm_vblank_crtc *vblank =
770 &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
771 const struct drm_display_mode *mode = &vblank->hwmode;
772 u32 vblank_start = mode->crtc_vblank_start;
773 u32 vtotal = mode->crtc_vtotal;
774 u32 scanline;
775
776 scanline = intel_crtc_scanlines_since_frame_timestamp(crtc);
777 scanline = min(scanline, vtotal - 1);
778 scanline = (scanline + vblank_start) % vtotal;
779
780 return scanline;
781}
782
783
784
785
786
787static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
788{
789 struct drm_device *dev = crtc->base.dev;
790 struct drm_i915_private *dev_priv = to_i915(dev);
791 const struct drm_display_mode *mode;
792 struct drm_vblank_crtc *vblank;
793 enum pipe pipe = crtc->pipe;
794 int position, vtotal;
795
796 if (!crtc->active)
797 return 0;
798
799 vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
800 mode = &vblank->hwmode;
801
802 if (crtc->mode_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
803 return __intel_get_crtc_scanline_from_timestamp(crtc);
804
805 vtotal = mode->crtc_vtotal;
806 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
807 vtotal /= 2;
808
809 if (DISPLAY_VER(dev_priv) == 2)
810 position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
811 else
812 position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
813
814
815
816
817
818
819
820
821
822
823
824
825
826 if (HAS_DDI(dev_priv) && !position) {
827 int i, temp;
828
829 for (i = 0; i < 100; i++) {
830 udelay(1);
831 temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
832 if (temp != position) {
833 position = temp;
834 break;
835 }
836 }
837 }
838
839
840
841
842
843 return (position + crtc->scanline_offset) % vtotal;
844}
845
846static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
847 bool in_vblank_irq,
848 int *vpos, int *hpos,
849 ktime_t *stime, ktime_t *etime,
850 const struct drm_display_mode *mode)
851{
852 struct drm_device *dev = _crtc->dev;
853 struct drm_i915_private *dev_priv = to_i915(dev);
854 struct intel_crtc *crtc = to_intel_crtc(_crtc);
855 enum pipe pipe = crtc->pipe;
856 int position;
857 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
858 unsigned long irqflags;
859 bool use_scanline_counter = DISPLAY_VER(dev_priv) >= 5 ||
860 IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) == 2 ||
861 crtc->mode_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;
862
863 if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) {
864 drm_dbg(&dev_priv->drm,
865 "trying to get scanoutpos for disabled "
866 "pipe %c\n", pipe_name(pipe));
867 return false;
868 }
869
870 htotal = mode->crtc_htotal;
871 hsync_start = mode->crtc_hsync_start;
872 vtotal = mode->crtc_vtotal;
873 vbl_start = mode->crtc_vblank_start;
874 vbl_end = mode->crtc_vblank_end;
875
876 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
877 vbl_start = DIV_ROUND_UP(vbl_start, 2);
878 vbl_end /= 2;
879 vtotal /= 2;
880 }
881
882
883
884
885
886
887 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
888
889
890
891
892 if (stime)
893 *stime = ktime_get();
894
895 if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
896 int scanlines = intel_crtc_scanlines_since_frame_timestamp(crtc);
897
898 position = __intel_get_crtc_scanline(crtc);
899
900
901
902
903
904
905
906 if (position >= vbl_start && scanlines < position)
907 position = min(crtc->vmax_vblank_start + scanlines, vtotal - 1);
908 } else if (use_scanline_counter) {
909
910
911
912 position = __intel_get_crtc_scanline(crtc);
913 } else {
914
915
916
917
918 position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
919
920
921 vbl_start *= htotal;
922 vbl_end *= htotal;
923 vtotal *= htotal;
924
925
926
927
928
929
930
931
932
933
934 if (position >= vtotal)
935 position = vtotal - 1;
936
937
938
939
940
941
942
943
944
945
946 position = (position + htotal - hsync_start) % vtotal;
947 }
948
949
950 if (etime)
951 *etime = ktime_get();
952
953
954
955 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
956
957
958
959
960
961
962
963 if (position >= vbl_start)
964 position -= vbl_end;
965 else
966 position += vtotal - vbl_end;
967
968 if (use_scanline_counter) {
969 *vpos = position;
970 *hpos = 0;
971 } else {
972 *vpos = position / htotal;
973 *hpos = position - (*vpos * htotal);
974 }
975
976 return true;
977}
978
979bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
980 ktime_t *vblank_time, bool in_vblank_irq)
981{
982 return drm_crtc_vblank_helper_get_vblank_timestamp_internal(
983 crtc, max_error, vblank_time, in_vblank_irq,
984 i915_get_crtc_scanoutpos);
985}
986
987int intel_get_crtc_scanline(struct intel_crtc *crtc)
988{
989 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
990 unsigned long irqflags;
991 int position;
992
993 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
994 position = __intel_get_crtc_scanline(crtc);
995 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
996
997 return position;
998}
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009static void ivb_parity_work(struct work_struct *work)
1010{
1011 struct drm_i915_private *dev_priv =
1012 container_of(work, typeof(*dev_priv), l3_parity.error_work);
1013 struct intel_gt *gt = &dev_priv->gt;
1014 u32 error_status, row, bank, subbank;
1015 char *parity_event[6];
1016 u32 misccpctl;
1017 u8 slice = 0;
1018
1019
1020
1021
1022
1023 mutex_lock(&dev_priv->drm.struct_mutex);
1024
1025
1026 if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice))
1027 goto out;
1028
1029 misccpctl = intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL);
1030 intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1031 intel_uncore_posting_read(&dev_priv->uncore, GEN7_MISCCPCTL);
1032
1033 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1034 i915_reg_t reg;
1035
1036 slice--;
1037 if (drm_WARN_ON_ONCE(&dev_priv->drm,
1038 slice >= NUM_L3_SLICES(dev_priv)))
1039 break;
1040
1041 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1042
1043 reg = GEN7_L3CDERRST1(slice);
1044
1045 error_status = intel_uncore_read(&dev_priv->uncore, reg);
1046 row = GEN7_PARITY_ERROR_ROW(error_status);
1047 bank = GEN7_PARITY_ERROR_BANK(error_status);
1048 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1049
1050 intel_uncore_write(&dev_priv->uncore, reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1051 intel_uncore_posting_read(&dev_priv->uncore, reg);
1052
1053 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1054 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1055 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1056 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1057 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1058 parity_event[5] = NULL;
1059
1060 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1061 KOBJ_CHANGE, parity_event);
1062
1063 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1064 slice, row, bank, subbank);
1065
1066 kfree(parity_event[4]);
1067 kfree(parity_event[3]);
1068 kfree(parity_event[2]);
1069 kfree(parity_event[1]);
1070 }
1071
1072 intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl);
1073
1074out:
1075 drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice);
1076 spin_lock_irq(>->irq_lock);
1077 gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv));
1078 spin_unlock_irq(>->irq_lock);
1079
1080 mutex_unlock(&dev_priv->drm.struct_mutex);
1081}
1082
1083static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1084{
1085 switch (pin) {
1086 case HPD_PORT_TC1:
1087 case HPD_PORT_TC2:
1088 case HPD_PORT_TC3:
1089 case HPD_PORT_TC4:
1090 case HPD_PORT_TC5:
1091 case HPD_PORT_TC6:
1092 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(pin);
1093 default:
1094 return false;
1095 }
1096}
1097
1098static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1099{
1100 switch (pin) {
1101 case HPD_PORT_A:
1102 return val & PORTA_HOTPLUG_LONG_DETECT;
1103 case HPD_PORT_B:
1104 return val & PORTB_HOTPLUG_LONG_DETECT;
1105 case HPD_PORT_C:
1106 return val & PORTC_HOTPLUG_LONG_DETECT;
1107 default:
1108 return false;
1109 }
1110}
1111
1112static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1113{
1114 switch (pin) {
1115 case HPD_PORT_A:
1116 case HPD_PORT_B:
1117 case HPD_PORT_C:
1118 case HPD_PORT_D:
1119 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(pin);
1120 default:
1121 return false;
1122 }
1123}
1124
1125static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1126{
1127 switch (pin) {
1128 case HPD_PORT_TC1:
1129 case HPD_PORT_TC2:
1130 case HPD_PORT_TC3:
1131 case HPD_PORT_TC4:
1132 case HPD_PORT_TC5:
1133 case HPD_PORT_TC6:
1134 return val & ICP_TC_HPD_LONG_DETECT(pin);
1135 default:
1136 return false;
1137 }
1138}
1139
1140static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
1141{
1142 switch (pin) {
1143 case HPD_PORT_E:
1144 return val & PORTE_HOTPLUG_LONG_DETECT;
1145 default:
1146 return false;
1147 }
1148}
1149
1150static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1151{
1152 switch (pin) {
1153 case HPD_PORT_A:
1154 return val & PORTA_HOTPLUG_LONG_DETECT;
1155 case HPD_PORT_B:
1156 return val & PORTB_HOTPLUG_LONG_DETECT;
1157 case HPD_PORT_C:
1158 return val & PORTC_HOTPLUG_LONG_DETECT;
1159 case HPD_PORT_D:
1160 return val & PORTD_HOTPLUG_LONG_DETECT;
1161 default:
1162 return false;
1163 }
1164}
1165
1166static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1167{
1168 switch (pin) {
1169 case HPD_PORT_A:
1170 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1171 default:
1172 return false;
1173 }
1174}
1175
1176static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1177{
1178 switch (pin) {
1179 case HPD_PORT_B:
1180 return val & PORTB_HOTPLUG_LONG_DETECT;
1181 case HPD_PORT_C:
1182 return val & PORTC_HOTPLUG_LONG_DETECT;
1183 case HPD_PORT_D:
1184 return val & PORTD_HOTPLUG_LONG_DETECT;
1185 default:
1186 return false;
1187 }
1188}
1189
1190static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1191{
1192 switch (pin) {
1193 case HPD_PORT_B:
1194 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1195 case HPD_PORT_C:
1196 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1197 case HPD_PORT_D:
1198 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1199 default:
1200 return false;
1201 }
1202}
1203
1204
1205
1206
1207
1208
1209
1210
1211static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
1212 u32 *pin_mask, u32 *long_mask,
1213 u32 hotplug_trigger, u32 dig_hotplug_reg,
1214 const u32 hpd[HPD_NUM_PINS],
1215 bool long_pulse_detect(enum hpd_pin pin, u32 val))
1216{
1217 enum hpd_pin pin;
1218
1219 BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS);
1220
1221 for_each_hpd_pin(pin) {
1222 if ((hpd[pin] & hotplug_trigger) == 0)
1223 continue;
1224
1225 *pin_mask |= BIT(pin);
1226
1227 if (long_pulse_detect(pin, dig_hotplug_reg))
1228 *long_mask |= BIT(pin);
1229 }
1230
1231 drm_dbg(&dev_priv->drm,
1232 "hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n",
1233 hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask);
1234
1235}
1236
1237static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
1238 const u32 hpd[HPD_NUM_PINS])
1239{
1240 struct intel_encoder *encoder;
1241 u32 enabled_irqs = 0;
1242
1243 for_each_intel_encoder(&dev_priv->drm, encoder)
1244 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
1245 enabled_irqs |= hpd[encoder->hpd_pin];
1246
1247 return enabled_irqs;
1248}
1249
1250static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
1251 const u32 hpd[HPD_NUM_PINS])
1252{
1253 struct intel_encoder *encoder;
1254 u32 hotplug_irqs = 0;
1255
1256 for_each_intel_encoder(&dev_priv->drm, encoder)
1257 hotplug_irqs |= hpd[encoder->hpd_pin];
1258
1259 return hotplug_irqs;
1260}
1261
1262static u32 intel_hpd_hotplug_enables(struct drm_i915_private *i915,
1263 hotplug_enables_func hotplug_enables)
1264{
1265 struct intel_encoder *encoder;
1266 u32 hotplug = 0;
1267
1268 for_each_intel_encoder(&i915->drm, encoder)
1269 hotplug |= hotplug_enables(i915, encoder->hpd_pin);
1270
1271 return hotplug;
1272}
1273
1274static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1275{
1276 wake_up_all(&dev_priv->gmbus_wait_queue);
1277}
1278
1279static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1280{
1281 wake_up_all(&dev_priv->gmbus_wait_queue);
1282}
1283
1284#if defined(CONFIG_DEBUG_FS)
1285static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1286 enum pipe pipe,
1287 u32 crc0, u32 crc1,
1288 u32 crc2, u32 crc3,
1289 u32 crc4)
1290{
1291 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1292 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
1293 u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 };
1294
1295 trace_intel_pipe_crc(crtc, crcs);
1296
1297 spin_lock(&pipe_crc->lock);
1298
1299
1300
1301
1302
1303
1304
1305
1306 if (pipe_crc->skipped <= 0 ||
1307 (DISPLAY_VER(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
1308 pipe_crc->skipped++;
1309 spin_unlock(&pipe_crc->lock);
1310 return;
1311 }
1312 spin_unlock(&pipe_crc->lock);
1313
1314 drm_crtc_add_crc_entry(&crtc->base, true,
1315 drm_crtc_accurate_vblank_count(&crtc->base),
1316 crcs);
1317}
1318#else
1319static inline void
1320display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1321 enum pipe pipe,
1322 u32 crc0, u32 crc1,
1323 u32 crc2, u32 crc3,
1324 u32 crc4) {}
1325#endif
1326
1327static void flip_done_handler(struct drm_i915_private *i915,
1328 enum pipe pipe)
1329{
1330 struct intel_crtc *crtc = intel_get_crtc_for_pipe(i915, pipe);
1331 struct drm_crtc_state *crtc_state = crtc->base.state;
1332 struct drm_pending_vblank_event *e = crtc_state->event;
1333 struct drm_device *dev = &i915->drm;
1334 unsigned long irqflags;
1335
1336 spin_lock_irqsave(&dev->event_lock, irqflags);
1337
1338 crtc_state->event = NULL;
1339
1340 drm_crtc_send_vblank_event(&crtc->base, e);
1341
1342 spin_unlock_irqrestore(&dev->event_lock, irqflags);
1343}
1344
1345static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1346 enum pipe pipe)
1347{
1348 display_pipe_crc_irq_handler(dev_priv, pipe,
1349 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)),
1350 0, 0, 0, 0);
1351}
1352
1353static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1354 enum pipe pipe)
1355{
1356 display_pipe_crc_irq_handler(dev_priv, pipe,
1357 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)),
1358 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(pipe)),
1359 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)),
1360 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)),
1361 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe)));
1362}
1363
1364static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1365 enum pipe pipe)
1366{
1367 u32 res1, res2;
1368
1369 if (DISPLAY_VER(dev_priv) >= 3)
1370 res1 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES1_I915(pipe));
1371 else
1372 res1 = 0;
1373
1374 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
1375 res2 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES2_G4X(pipe));
1376 else
1377 res2 = 0;
1378
1379 display_pipe_crc_irq_handler(dev_priv, pipe,
1380 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RED(pipe)),
1381 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_GREEN(pipe)),
1382 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_BLUE(pipe)),
1383 res1, res2);
1384}
1385
1386static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
1387{
1388 enum pipe pipe;
1389
1390 for_each_pipe(dev_priv, pipe) {
1391 intel_uncore_write(&dev_priv->uncore, PIPESTAT(pipe),
1392 PIPESTAT_INT_STATUS_MASK |
1393 PIPE_FIFO_UNDERRUN_STATUS);
1394
1395 dev_priv->pipestat_irq_mask[pipe] = 0;
1396 }
1397}
1398
1399static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1400 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1401{
1402 enum pipe pipe;
1403
1404 spin_lock(&dev_priv->irq_lock);
1405
1406 if (!dev_priv->display_irqs_enabled) {
1407 spin_unlock(&dev_priv->irq_lock);
1408 return;
1409 }
1410
1411 for_each_pipe(dev_priv, pipe) {
1412 i915_reg_t reg;
1413 u32 status_mask, enable_mask, iir_bit = 0;
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424 status_mask = PIPE_FIFO_UNDERRUN_STATUS;
1425
1426 switch (pipe) {
1427 default:
1428 case PIPE_A:
1429 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1430 break;
1431 case PIPE_B:
1432 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1433 break;
1434 case PIPE_C:
1435 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1436 break;
1437 }
1438 if (iir & iir_bit)
1439 status_mask |= dev_priv->pipestat_irq_mask[pipe];
1440
1441 if (!status_mask)
1442 continue;
1443
1444 reg = PIPESTAT(pipe);
1445 pipe_stats[pipe] = intel_uncore_read(&dev_priv->uncore, reg) & status_mask;
1446 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457 if (pipe_stats[pipe]) {
1458 intel_uncore_write(&dev_priv->uncore, reg, pipe_stats[pipe]);
1459 intel_uncore_write(&dev_priv->uncore, reg, enable_mask);
1460 }
1461 }
1462 spin_unlock(&dev_priv->irq_lock);
1463}
1464
1465static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1466 u16 iir, u32 pipe_stats[I915_MAX_PIPES])
1467{
1468 enum pipe pipe;
1469
1470 for_each_pipe(dev_priv, pipe) {
1471 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1472 intel_handle_vblank(dev_priv, pipe);
1473
1474 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1475 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1476
1477 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1478 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1479 }
1480}
1481
1482static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1483 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1484{
1485 bool blc_event = false;
1486 enum pipe pipe;
1487
1488 for_each_pipe(dev_priv, pipe) {
1489 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1490 intel_handle_vblank(dev_priv, pipe);
1491
1492 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1493 blc_event = true;
1494
1495 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1496 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1497
1498 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1499 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1500 }
1501
1502 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1503 intel_opregion_asle_intr(dev_priv);
1504}
1505
1506static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1507 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1508{
1509 bool blc_event = false;
1510 enum pipe pipe;
1511
1512 for_each_pipe(dev_priv, pipe) {
1513 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1514 intel_handle_vblank(dev_priv, pipe);
1515
1516 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1517 blc_event = true;
1518
1519 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1520 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1521
1522 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1523 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1524 }
1525
1526 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1527 intel_opregion_asle_intr(dev_priv);
1528
1529 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1530 gmbus_irq_handler(dev_priv);
1531}
1532
1533static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1534 u32 pipe_stats[I915_MAX_PIPES])
1535{
1536 enum pipe pipe;
1537
1538 for_each_pipe(dev_priv, pipe) {
1539 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1540 intel_handle_vblank(dev_priv, pipe);
1541
1542 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
1543 flip_done_handler(dev_priv, pipe);
1544
1545 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1546 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1547
1548 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1549 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1550 }
1551
1552 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1553 gmbus_irq_handler(dev_priv);
1554}
1555
1556static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1557{
1558 u32 hotplug_status = 0, hotplug_status_mask;
1559 int i;
1560
1561 if (IS_G4X(dev_priv) ||
1562 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1563 hotplug_status_mask = HOTPLUG_INT_STATUS_G4X |
1564 DP_AUX_CHANNEL_MASK_INT_STATUS_G4X;
1565 else
1566 hotplug_status_mask = HOTPLUG_INT_STATUS_I915;
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577 for (i = 0; i < 10; i++) {
1578 u32 tmp = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT) & hotplug_status_mask;
1579
1580 if (tmp == 0)
1581 return hotplug_status;
1582
1583 hotplug_status |= tmp;
1584 intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, hotplug_status);
1585 }
1586
1587 drm_WARN_ONCE(&dev_priv->drm, 1,
1588 "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
1589 intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT));
1590
1591 return hotplug_status;
1592}
1593
1594static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1595 u32 hotplug_status)
1596{
1597 u32 pin_mask = 0, long_mask = 0;
1598 u32 hotplug_trigger;
1599
1600 if (IS_G4X(dev_priv) ||
1601 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1602 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1603 else
1604 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1605
1606 if (hotplug_trigger) {
1607 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1608 hotplug_trigger, hotplug_trigger,
1609 dev_priv->hotplug.hpd,
1610 i9xx_port_hotplug_long_detect);
1611
1612 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1613 }
1614
1615 if ((IS_G4X(dev_priv) ||
1616 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1617 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1618 dp_aux_irq_handler(dev_priv);
1619}
1620
1621static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1622{
1623 struct drm_i915_private *dev_priv = arg;
1624 irqreturn_t ret = IRQ_NONE;
1625
1626 if (!intel_irqs_enabled(dev_priv))
1627 return IRQ_NONE;
1628
1629
1630 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1631
1632 do {
1633 u32 iir, gt_iir, pm_iir;
1634 u32 pipe_stats[I915_MAX_PIPES] = {};
1635 u32 hotplug_status = 0;
1636 u32 ier = 0;
1637
1638 gt_iir = intel_uncore_read(&dev_priv->uncore, GTIIR);
1639 pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR);
1640 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
1641
1642 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1643 break;
1644
1645 ret = IRQ_HANDLED;
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0);
1661 ier = intel_uncore_read(&dev_priv->uncore, VLV_IER);
1662 intel_uncore_write(&dev_priv->uncore, VLV_IER, 0);
1663
1664 if (gt_iir)
1665 intel_uncore_write(&dev_priv->uncore, GTIIR, gt_iir);
1666 if (pm_iir)
1667 intel_uncore_write(&dev_priv->uncore, GEN6_PMIIR, pm_iir);
1668
1669 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1670 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1671
1672
1673
1674 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1675
1676 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1677 I915_LPE_PIPE_B_INTERRUPT))
1678 intel_lpe_audio_irq_handler(dev_priv);
1679
1680
1681
1682
1683
1684 if (iir)
1685 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);
1686
1687 intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
1688 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1689
1690 if (gt_iir)
1691 gen6_gt_irq_handler(&dev_priv->gt, gt_iir);
1692 if (pm_iir)
1693 gen6_rps_irq_handler(&dev_priv->gt.rps, pm_iir);
1694
1695 if (hotplug_status)
1696 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1697
1698 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1699 } while (0);
1700
1701 pmu_irq_stats(dev_priv, ret);
1702
1703 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1704
1705 return ret;
1706}
1707
1708static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1709{
1710 struct drm_i915_private *dev_priv = arg;
1711 irqreturn_t ret = IRQ_NONE;
1712
1713 if (!intel_irqs_enabled(dev_priv))
1714 return IRQ_NONE;
1715
1716
1717 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1718
1719 do {
1720 u32 master_ctl, iir;
1721 u32 pipe_stats[I915_MAX_PIPES] = {};
1722 u32 hotplug_status = 0;
1723 u32 ier = 0;
1724
1725 master_ctl = intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1726 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
1727
1728 if (master_ctl == 0 && iir == 0)
1729 break;
1730
1731 ret = IRQ_HANDLED;
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0);
1747 ier = intel_uncore_read(&dev_priv->uncore, VLV_IER);
1748 intel_uncore_write(&dev_priv->uncore, VLV_IER, 0);
1749
1750 gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
1751
1752 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1753 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1754
1755
1756
1757 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1758
1759 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1760 I915_LPE_PIPE_B_INTERRUPT |
1761 I915_LPE_PIPE_C_INTERRUPT))
1762 intel_lpe_audio_irq_handler(dev_priv);
1763
1764
1765
1766
1767
1768 if (iir)
1769 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);
1770
1771 intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
1772 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1773
1774 if (hotplug_status)
1775 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1776
1777 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1778 } while (0);
1779
1780 pmu_irq_stats(dev_priv, ret);
1781
1782 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1783
1784 return ret;
1785}
1786
1787static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1788 u32 hotplug_trigger)
1789{
1790 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1791
1792
1793
1794
1795
1796
1797
1798 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
1799 if (!hotplug_trigger) {
1800 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
1801 PORTD_HOTPLUG_STATUS_MASK |
1802 PORTC_HOTPLUG_STATUS_MASK |
1803 PORTB_HOTPLUG_STATUS_MASK;
1804 dig_hotplug_reg &= ~mask;
1805 }
1806
1807 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg);
1808 if (!hotplug_trigger)
1809 return;
1810
1811 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1812 hotplug_trigger, dig_hotplug_reg,
1813 dev_priv->hotplug.pch_hpd,
1814 pch_port_hotplug_long_detect);
1815
1816 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1817}
1818
1819static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1820{
1821 enum pipe pipe;
1822 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1823
1824 ibx_hpd_irq_handler(dev_priv, hotplug_trigger);
1825
1826 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1827 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1828 SDE_AUDIO_POWER_SHIFT);
1829 drm_dbg(&dev_priv->drm, "PCH audio power change on port %d\n",
1830 port_name(port));
1831 }
1832
1833 if (pch_iir & SDE_AUX_MASK)
1834 dp_aux_irq_handler(dev_priv);
1835
1836 if (pch_iir & SDE_GMBUS)
1837 gmbus_irq_handler(dev_priv);
1838
1839 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1840 drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n");
1841
1842 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1843 drm_dbg(&dev_priv->drm, "PCH transcoder audio interrupt\n");
1844
1845 if (pch_iir & SDE_POISON)
1846 drm_err(&dev_priv->drm, "PCH poison interrupt\n");
1847
1848 if (pch_iir & SDE_FDI_MASK) {
1849 for_each_pipe(dev_priv, pipe)
1850 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n",
1851 pipe_name(pipe),
1852 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe)));
1853 }
1854
1855 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1856 drm_dbg(&dev_priv->drm, "PCH transcoder CRC done interrupt\n");
1857
1858 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1859 drm_dbg(&dev_priv->drm,
1860 "PCH transcoder CRC error interrupt\n");
1861
1862 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1863 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
1864
1865 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1866 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
1867}
1868
1869static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
1870{
1871 u32 err_int = intel_uncore_read(&dev_priv->uncore, GEN7_ERR_INT);
1872 enum pipe pipe;
1873
1874 if (err_int & ERR_INT_POISON)
1875 drm_err(&dev_priv->drm, "Poison interrupt\n");
1876
1877 for_each_pipe(dev_priv, pipe) {
1878 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1879 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1880
1881 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1882 if (IS_IVYBRIDGE(dev_priv))
1883 ivb_pipe_crc_irq_handler(dev_priv, pipe);
1884 else
1885 hsw_pipe_crc_irq_handler(dev_priv, pipe);
1886 }
1887 }
1888
1889 intel_uncore_write(&dev_priv->uncore, GEN7_ERR_INT, err_int);
1890}
1891
1892static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
1893{
1894 u32 serr_int = intel_uncore_read(&dev_priv->uncore, SERR_INT);
1895 enum pipe pipe;
1896
1897 if (serr_int & SERR_INT_POISON)
1898 drm_err(&dev_priv->drm, "PCH poison interrupt\n");
1899
1900 for_each_pipe(dev_priv, pipe)
1901 if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))
1902 intel_pch_fifo_underrun_irq_handler(dev_priv, pipe);
1903
1904 intel_uncore_write(&dev_priv->uncore, SERR_INT, serr_int);
1905}
1906
1907static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1908{
1909 enum pipe pipe;
1910 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1911
1912 ibx_hpd_irq_handler(dev_priv, hotplug_trigger);
1913
1914 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1915 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1916 SDE_AUDIO_POWER_SHIFT_CPT);
1917 drm_dbg(&dev_priv->drm, "PCH audio power change on port %c\n",
1918 port_name(port));
1919 }
1920
1921 if (pch_iir & SDE_AUX_MASK_CPT)
1922 dp_aux_irq_handler(dev_priv);
1923
1924 if (pch_iir & SDE_GMBUS_CPT)
1925 gmbus_irq_handler(dev_priv);
1926
1927 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1928 drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n");
1929
1930 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1931 drm_dbg(&dev_priv->drm, "Audio CP change interrupt\n");
1932
1933 if (pch_iir & SDE_FDI_MASK_CPT) {
1934 for_each_pipe(dev_priv, pipe)
1935 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n",
1936 pipe_name(pipe),
1937 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe)));
1938 }
1939
1940 if (pch_iir & SDE_ERROR_CPT)
1941 cpt_serr_int_handler(dev_priv);
1942}
1943
1944static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1945{
1946 u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP;
1947 u32 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_MASK_ICP;
1948 u32 pin_mask = 0, long_mask = 0;
1949
1950 if (ddi_hotplug_trigger) {
1951 u32 dig_hotplug_reg;
1952
1953 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_DDI);
1954 intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_DDI, dig_hotplug_reg);
1955
1956 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1957 ddi_hotplug_trigger, dig_hotplug_reg,
1958 dev_priv->hotplug.pch_hpd,
1959 icp_ddi_port_hotplug_long_detect);
1960 }
1961
1962 if (tc_hotplug_trigger) {
1963 u32 dig_hotplug_reg;
1964
1965 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_TC);
1966 intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_TC, dig_hotplug_reg);
1967
1968 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1969 tc_hotplug_trigger, dig_hotplug_reg,
1970 dev_priv->hotplug.pch_hpd,
1971 icp_tc_port_hotplug_long_detect);
1972 }
1973
1974 if (pin_mask)
1975 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1976
1977 if (pch_iir & SDE_GMBUS_ICP)
1978 gmbus_irq_handler(dev_priv);
1979}
1980
1981static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1982{
1983 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
1984 ~SDE_PORTE_HOTPLUG_SPT;
1985 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
1986 u32 pin_mask = 0, long_mask = 0;
1987
1988 if (hotplug_trigger) {
1989 u32 dig_hotplug_reg;
1990
1991 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
1992 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg);
1993
1994 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1995 hotplug_trigger, dig_hotplug_reg,
1996 dev_priv->hotplug.pch_hpd,
1997 spt_port_hotplug_long_detect);
1998 }
1999
2000 if (hotplug2_trigger) {
2001 u32 dig_hotplug_reg;
2002
2003 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG2);
2004 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2005
2006 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2007 hotplug2_trigger, dig_hotplug_reg,
2008 dev_priv->hotplug.pch_hpd,
2009 spt_port_hotplug2_long_detect);
2010 }
2011
2012 if (pin_mask)
2013 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2014
2015 if (pch_iir & SDE_GMBUS_CPT)
2016 gmbus_irq_handler(dev_priv);
2017}
2018
2019static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2020 u32 hotplug_trigger)
2021{
2022 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2023
2024 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL);
2025 intel_uncore_write(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2026
2027 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2028 hotplug_trigger, dig_hotplug_reg,
2029 dev_priv->hotplug.hpd,
2030 ilk_port_hotplug_long_detect);
2031
2032 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2033}
2034
2035static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2036 u32 de_iir)
2037{
2038 enum pipe pipe;
2039 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2040
2041 if (hotplug_trigger)
2042 ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
2043
2044 if (de_iir & DE_AUX_CHANNEL_A)
2045 dp_aux_irq_handler(dev_priv);
2046
2047 if (de_iir & DE_GSE)
2048 intel_opregion_asle_intr(dev_priv);
2049
2050 if (de_iir & DE_POISON)
2051 drm_err(&dev_priv->drm, "Poison interrupt\n");
2052
2053 for_each_pipe(dev_priv, pipe) {
2054 if (de_iir & DE_PIPE_VBLANK(pipe))
2055 intel_handle_vblank(dev_priv, pipe);
2056
2057 if (de_iir & DE_PLANE_FLIP_DONE(pipe))
2058 flip_done_handler(dev_priv, pipe);
2059
2060 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2061 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2062
2063 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2064 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2065 }
2066
2067
2068 if (de_iir & DE_PCH_EVENT) {
2069 u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR);
2070
2071 if (HAS_PCH_CPT(dev_priv))
2072 cpt_irq_handler(dev_priv, pch_iir);
2073 else
2074 ibx_irq_handler(dev_priv, pch_iir);
2075
2076
2077 intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir);
2078 }
2079
2080 if (DISPLAY_VER(dev_priv) == 5 && de_iir & DE_PCU_EVENT)
2081 gen5_rps_irq_handler(&dev_priv->gt.rps);
2082}
2083
2084static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2085 u32 de_iir)
2086{
2087 enum pipe pipe;
2088 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2089
2090 if (hotplug_trigger)
2091 ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
2092
2093 if (de_iir & DE_ERR_INT_IVB)
2094 ivb_err_int_handler(dev_priv);
2095
2096 if (de_iir & DE_EDP_PSR_INT_HSW) {
2097 struct intel_encoder *encoder;
2098
2099 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
2100 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2101
2102 u32 psr_iir = intel_uncore_read(&dev_priv->uncore,
2103 EDP_PSR_IIR);
2104
2105 intel_psr_irq_handler(intel_dp, psr_iir);
2106 intel_uncore_write(&dev_priv->uncore,
2107 EDP_PSR_IIR, psr_iir);
2108 break;
2109 }
2110 }
2111
2112 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2113 dp_aux_irq_handler(dev_priv);
2114
2115 if (de_iir & DE_GSE_IVB)
2116 intel_opregion_asle_intr(dev_priv);
2117
2118 for_each_pipe(dev_priv, pipe) {
2119 if (de_iir & DE_PIPE_VBLANK_IVB(pipe))
2120 intel_handle_vblank(dev_priv, pipe);
2121
2122 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
2123 flip_done_handler(dev_priv, pipe);
2124 }
2125
2126
2127 if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2128 u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR);
2129
2130 cpt_irq_handler(dev_priv, pch_iir);
2131
2132
2133 intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir);
2134 }
2135}
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145static irqreturn_t ilk_irq_handler(int irq, void *arg)
2146{
2147 struct drm_i915_private *i915 = arg;
2148 void __iomem * const regs = i915->uncore.regs;
2149 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2150 irqreturn_t ret = IRQ_NONE;
2151
2152 if (unlikely(!intel_irqs_enabled(i915)))
2153 return IRQ_NONE;
2154
2155
2156 disable_rpm_wakeref_asserts(&i915->runtime_pm);
2157
2158
2159 de_ier = raw_reg_read(regs, DEIER);
2160 raw_reg_write(regs, DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2161
2162
2163
2164
2165
2166
2167 if (!HAS_PCH_NOP(i915)) {
2168 sde_ier = raw_reg_read(regs, SDEIER);
2169 raw_reg_write(regs, SDEIER, 0);
2170 }
2171
2172
2173
2174 gt_iir = raw_reg_read(regs, GTIIR);
2175 if (gt_iir) {
2176 raw_reg_write(regs, GTIIR, gt_iir);
2177 if (GRAPHICS_VER(i915) >= 6)
2178 gen6_gt_irq_handler(&i915->gt, gt_iir);
2179 else
2180 gen5_gt_irq_handler(&i915->gt, gt_iir);
2181 ret = IRQ_HANDLED;
2182 }
2183
2184 de_iir = raw_reg_read(regs, DEIIR);
2185 if (de_iir) {
2186 raw_reg_write(regs, DEIIR, de_iir);
2187 if (DISPLAY_VER(i915) >= 7)
2188 ivb_display_irq_handler(i915, de_iir);
2189 else
2190 ilk_display_irq_handler(i915, de_iir);
2191 ret = IRQ_HANDLED;
2192 }
2193
2194 if (GRAPHICS_VER(i915) >= 6) {
2195 u32 pm_iir = raw_reg_read(regs, GEN6_PMIIR);
2196 if (pm_iir) {
2197 raw_reg_write(regs, GEN6_PMIIR, pm_iir);
2198 gen6_rps_irq_handler(&i915->gt.rps, pm_iir);
2199 ret = IRQ_HANDLED;
2200 }
2201 }
2202
2203 raw_reg_write(regs, DEIER, de_ier);
2204 if (sde_ier)
2205 raw_reg_write(regs, SDEIER, sde_ier);
2206
2207 pmu_irq_stats(i915, ret);
2208
2209
2210 enable_rpm_wakeref_asserts(&i915->runtime_pm);
2211
2212 return ret;
2213}
2214
2215static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2216 u32 hotplug_trigger)
2217{
2218 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2219
2220 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
2221 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg);
2222
2223 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2224 hotplug_trigger, dig_hotplug_reg,
2225 dev_priv->hotplug.hpd,
2226 bxt_port_hotplug_long_detect);
2227
2228 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2229}
2230
2231static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2232{
2233 u32 pin_mask = 0, long_mask = 0;
2234 u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
2235 u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
2236
2237 if (trigger_tc) {
2238 u32 dig_hotplug_reg;
2239
2240 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL);
2241 intel_uncore_write(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
2242
2243 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2244 trigger_tc, dig_hotplug_reg,
2245 dev_priv->hotplug.hpd,
2246 gen11_port_hotplug_long_detect);
2247 }
2248
2249 if (trigger_tbt) {
2250 u32 dig_hotplug_reg;
2251
2252 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL);
2253 intel_uncore_write(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg);
2254
2255 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2256 trigger_tbt, dig_hotplug_reg,
2257 dev_priv->hotplug.hpd,
2258 gen11_port_hotplug_long_detect);
2259 }
2260
2261 if (pin_mask)
2262 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2263 else
2264 drm_err(&dev_priv->drm,
2265 "Unexpected DE HPD interrupt 0x%08x\n", iir);
2266}
2267
2268static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
2269{
2270 u32 mask;
2271
2272 if (DISPLAY_VER(dev_priv) >= 13)
2273 return TGL_DE_PORT_AUX_DDIA |
2274 TGL_DE_PORT_AUX_DDIB |
2275 TGL_DE_PORT_AUX_DDIC |
2276 XELPD_DE_PORT_AUX_DDID |
2277 XELPD_DE_PORT_AUX_DDIE |
2278 TGL_DE_PORT_AUX_USBC1 |
2279 TGL_DE_PORT_AUX_USBC2 |
2280 TGL_DE_PORT_AUX_USBC3 |
2281 TGL_DE_PORT_AUX_USBC4;
2282 else if (DISPLAY_VER(dev_priv) >= 12)
2283 return TGL_DE_PORT_AUX_DDIA |
2284 TGL_DE_PORT_AUX_DDIB |
2285 TGL_DE_PORT_AUX_DDIC |
2286 TGL_DE_PORT_AUX_USBC1 |
2287 TGL_DE_PORT_AUX_USBC2 |
2288 TGL_DE_PORT_AUX_USBC3 |
2289 TGL_DE_PORT_AUX_USBC4 |
2290 TGL_DE_PORT_AUX_USBC5 |
2291 TGL_DE_PORT_AUX_USBC6;
2292
2293
2294 mask = GEN8_AUX_CHANNEL_A;
2295 if (DISPLAY_VER(dev_priv) >= 9)
2296 mask |= GEN9_AUX_CHANNEL_B |
2297 GEN9_AUX_CHANNEL_C |
2298 GEN9_AUX_CHANNEL_D;
2299
2300 if (DISPLAY_VER(dev_priv) == 11) {
2301 mask |= ICL_AUX_CHANNEL_F;
2302 mask |= ICL_AUX_CHANNEL_E;
2303 }
2304
2305 return mask;
2306}
2307
2308static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
2309{
2310 if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
2311 return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
2312 else if (DISPLAY_VER(dev_priv) >= 11)
2313 return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
2314 else if (DISPLAY_VER(dev_priv) >= 9)
2315 return GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2316 else
2317 return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2318}
2319
2320static void
2321gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2322{
2323 bool found = false;
2324
2325 if (iir & GEN8_DE_MISC_GSE) {
2326 intel_opregion_asle_intr(dev_priv);
2327 found = true;
2328 }
2329
2330 if (iir & GEN8_DE_EDP_PSR) {
2331 struct intel_encoder *encoder;
2332 u32 psr_iir;
2333 i915_reg_t iir_reg;
2334
2335 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
2336 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2337
2338 if (DISPLAY_VER(dev_priv) >= 12)
2339 iir_reg = TRANS_PSR_IIR(intel_dp->psr.transcoder);
2340 else
2341 iir_reg = EDP_PSR_IIR;
2342
2343 psr_iir = intel_uncore_read(&dev_priv->uncore, iir_reg);
2344 intel_uncore_write(&dev_priv->uncore, iir_reg, psr_iir);
2345
2346 if (psr_iir)
2347 found = true;
2348
2349 intel_psr_irq_handler(intel_dp, psr_iir);
2350
2351
2352 if (DISPLAY_VER(dev_priv) < 12)
2353 break;
2354 }
2355 }
2356
2357 if (!found)
2358 drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n");
2359}
2360
2361static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
2362 u32 te_trigger)
2363{
2364 enum pipe pipe = INVALID_PIPE;
2365 enum transcoder dsi_trans;
2366 enum port port;
2367 u32 val, tmp;
2368
2369
2370
2371
2372
2373 val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));
2374 val &= PORT_SYNC_MODE_ENABLE;
2375
2376
2377
2378
2379
2380 port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ?
2381 PORT_A : PORT_B;
2382 dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1;
2383
2384
2385 val = intel_uncore_read(&dev_priv->uncore, DSI_TRANS_FUNC_CONF(dsi_trans));
2386 val = val & OP_MODE_MASK;
2387
2388 if (val != CMD_MODE_NO_GATE && val != CMD_MODE_TE_GATE) {
2389 drm_err(&dev_priv->drm, "DSI trancoder not configured in command mode\n");
2390 return;
2391 }
2392
2393
2394 val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL(dsi_trans));
2395 switch (val & TRANS_DDI_EDP_INPUT_MASK) {
2396 case TRANS_DDI_EDP_INPUT_A_ON:
2397 pipe = PIPE_A;
2398 break;
2399 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2400 pipe = PIPE_B;
2401 break;
2402 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2403 pipe = PIPE_C;
2404 break;
2405 default:
2406 drm_err(&dev_priv->drm, "Invalid PIPE\n");
2407 return;
2408 }
2409
2410 intel_handle_vblank(dev_priv, pipe);
2411
2412
2413 port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A;
2414 tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_IDENT_REG(port));
2415 intel_uncore_write(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), tmp);
2416}
2417
2418static u32 gen8_de_pipe_flip_done_mask(struct drm_i915_private *i915)
2419{
2420 if (DISPLAY_VER(i915) >= 9)
2421 return GEN9_PIPE_PLANE1_FLIP_DONE;
2422 else
2423 return GEN8_PIPE_PRIMARY_FLIP_DONE;
2424}
2425
2426u32 gen8_de_pipe_underrun_mask(struct drm_i915_private *dev_priv)
2427{
2428 u32 mask = GEN8_PIPE_FIFO_UNDERRUN;
2429
2430 if (DISPLAY_VER(dev_priv) >= 13)
2431 mask |= XELPD_PIPE_SOFT_UNDERRUN |
2432 XELPD_PIPE_HARD_UNDERRUN;
2433
2434 return mask;
2435}
2436
2437static irqreturn_t
2438gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2439{
2440 irqreturn_t ret = IRQ_NONE;
2441 u32 iir;
2442 enum pipe pipe;
2443
2444 drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DISPLAY(dev_priv));
2445
2446 if (master_ctl & GEN8_DE_MISC_IRQ) {
2447 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_MISC_IIR);
2448 if (iir) {
2449 intel_uncore_write(&dev_priv->uncore, GEN8_DE_MISC_IIR, iir);
2450 ret = IRQ_HANDLED;
2451 gen8_de_misc_irq_handler(dev_priv, iir);
2452 } else {
2453 drm_err(&dev_priv->drm,
2454 "The master control interrupt lied (DE MISC)!\n");
2455 }
2456 }
2457
2458 if (DISPLAY_VER(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
2459 iir = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IIR);
2460 if (iir) {
2461 intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IIR, iir);
2462 ret = IRQ_HANDLED;
2463 gen11_hpd_irq_handler(dev_priv, iir);
2464 } else {
2465 drm_err(&dev_priv->drm,
2466 "The master control interrupt lied, (DE HPD)!\n");
2467 }
2468 }
2469
2470 if (master_ctl & GEN8_DE_PORT_IRQ) {
2471 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IIR);
2472 if (iir) {
2473 bool found = false;
2474
2475 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IIR, iir);
2476 ret = IRQ_HANDLED;
2477
2478 if (iir & gen8_de_port_aux_mask(dev_priv)) {
2479 dp_aux_irq_handler(dev_priv);
2480 found = true;
2481 }
2482
2483 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
2484 u32 hotplug_trigger = iir & BXT_DE_PORT_HOTPLUG_MASK;
2485
2486 if (hotplug_trigger) {
2487 bxt_hpd_irq_handler(dev_priv, hotplug_trigger);
2488 found = true;
2489 }
2490 } else if (IS_BROADWELL(dev_priv)) {
2491 u32 hotplug_trigger = iir & BDW_DE_PORT_HOTPLUG_MASK;
2492
2493 if (hotplug_trigger) {
2494 ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
2495 found = true;
2496 }
2497 }
2498
2499 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
2500 (iir & BXT_DE_PORT_GMBUS)) {
2501 gmbus_irq_handler(dev_priv);
2502 found = true;
2503 }
2504
2505 if (DISPLAY_VER(dev_priv) >= 11) {
2506 u32 te_trigger = iir & (DSI0_TE | DSI1_TE);
2507
2508 if (te_trigger) {
2509 gen11_dsi_te_interrupt_handler(dev_priv, te_trigger);
2510 found = true;
2511 }
2512 }
2513
2514 if (!found)
2515 drm_err(&dev_priv->drm,
2516 "Unexpected DE Port interrupt\n");
2517 }
2518 else
2519 drm_err(&dev_priv->drm,
2520 "The master control interrupt lied (DE PORT)!\n");
2521 }
2522
2523 for_each_pipe(dev_priv, pipe) {
2524 u32 fault_errors;
2525
2526 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2527 continue;
2528
2529 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe));
2530 if (!iir) {
2531 drm_err(&dev_priv->drm,
2532 "The master control interrupt lied (DE PIPE)!\n");
2533 continue;
2534 }
2535
2536 ret = IRQ_HANDLED;
2537 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe), iir);
2538
2539 if (iir & GEN8_PIPE_VBLANK)
2540 intel_handle_vblank(dev_priv, pipe);
2541
2542 if (iir & gen8_de_pipe_flip_done_mask(dev_priv))
2543 flip_done_handler(dev_priv, pipe);
2544
2545 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2546 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2547
2548 if (iir & gen8_de_pipe_underrun_mask(dev_priv))
2549 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2550
2551 fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);
2552 if (fault_errors)
2553 drm_err(&dev_priv->drm,
2554 "Fault errors on pipe %c: 0x%08x\n",
2555 pipe_name(pipe),
2556 fault_errors);
2557 }
2558
2559 if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2560 master_ctl & GEN8_DE_PCH_IRQ) {
2561
2562
2563
2564
2565
2566 iir = intel_uncore_read(&dev_priv->uncore, SDEIIR);
2567 if (iir) {
2568 intel_uncore_write(&dev_priv->uncore, SDEIIR, iir);
2569 ret = IRQ_HANDLED;
2570
2571 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2572 icp_irq_handler(dev_priv, iir);
2573 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
2574 spt_irq_handler(dev_priv, iir);
2575 else
2576 cpt_irq_handler(dev_priv, iir);
2577 } else {
2578
2579
2580
2581
2582 drm_dbg(&dev_priv->drm,
2583 "The master control interrupt lied (SDE)!\n");
2584 }
2585 }
2586
2587 return ret;
2588}
2589
2590static inline u32 gen8_master_intr_disable(void __iomem * const regs)
2591{
2592 raw_reg_write(regs, GEN8_MASTER_IRQ, 0);
2593
2594
2595
2596
2597
2598
2599
2600 return raw_reg_read(regs, GEN8_MASTER_IRQ);
2601}
2602
2603static inline void gen8_master_intr_enable(void __iomem * const regs)
2604{
2605 raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2606}
2607
2608static irqreturn_t gen8_irq_handler(int irq, void *arg)
2609{
2610 struct drm_i915_private *dev_priv = arg;
2611 void __iomem * const regs = dev_priv->uncore.regs;
2612 u32 master_ctl;
2613
2614 if (!intel_irqs_enabled(dev_priv))
2615 return IRQ_NONE;
2616
2617 master_ctl = gen8_master_intr_disable(regs);
2618 if (!master_ctl) {
2619 gen8_master_intr_enable(regs);
2620 return IRQ_NONE;
2621 }
2622
2623
2624 gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
2625
2626
2627 if (master_ctl & ~GEN8_GT_IRQS) {
2628 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2629 gen8_de_irq_handler(dev_priv, master_ctl);
2630 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2631 }
2632
2633 gen8_master_intr_enable(regs);
2634
2635 pmu_irq_stats(dev_priv, IRQ_HANDLED);
2636
2637 return IRQ_HANDLED;
2638}
2639
2640static u32
2641gen11_gu_misc_irq_ack(struct intel_gt *gt, const u32 master_ctl)
2642{
2643 void __iomem * const regs = gt->uncore->regs;
2644 u32 iir;
2645
2646 if (!(master_ctl & GEN11_GU_MISC_IRQ))
2647 return 0;
2648
2649 iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);
2650 if (likely(iir))
2651 raw_reg_write(regs, GEN11_GU_MISC_IIR, iir);
2652
2653 return iir;
2654}
2655
2656static void
2657gen11_gu_misc_irq_handler(struct intel_gt *gt, const u32 iir)
2658{
2659 if (iir & GEN11_GU_MISC_GSE)
2660 intel_opregion_asle_intr(gt->i915);
2661}
2662
2663static inline u32 gen11_master_intr_disable(void __iomem * const regs)
2664{
2665 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0);
2666
2667
2668
2669
2670
2671
2672
2673 return raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
2674}
2675
2676static inline void gen11_master_intr_enable(void __iomem * const regs)
2677{
2678 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
2679}
2680
2681static void
2682gen11_display_irq_handler(struct drm_i915_private *i915)
2683{
2684 void __iomem * const regs = i915->uncore.regs;
2685 const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
2686
2687 disable_rpm_wakeref_asserts(&i915->runtime_pm);
2688
2689
2690
2691
2692 raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0x0);
2693 gen8_de_irq_handler(i915, disp_ctl);
2694 raw_reg_write(regs, GEN11_DISPLAY_INT_CTL,
2695 GEN11_DISPLAY_IRQ_ENABLE);
2696
2697 enable_rpm_wakeref_asserts(&i915->runtime_pm);
2698}
2699
2700static irqreturn_t gen11_irq_handler(int irq, void *arg)
2701{
2702 struct drm_i915_private *i915 = arg;
2703 void __iomem * const regs = i915->uncore.regs;
2704 struct intel_gt *gt = &i915->gt;
2705 u32 master_ctl;
2706 u32 gu_misc_iir;
2707
2708 if (!intel_irqs_enabled(i915))
2709 return IRQ_NONE;
2710
2711 master_ctl = gen11_master_intr_disable(regs);
2712 if (!master_ctl) {
2713 gen11_master_intr_enable(regs);
2714 return IRQ_NONE;
2715 }
2716
2717
2718 gen11_gt_irq_handler(gt, master_ctl);
2719
2720
2721 if (master_ctl & GEN11_DISPLAY_IRQ)
2722 gen11_display_irq_handler(i915);
2723
2724 gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
2725
2726 gen11_master_intr_enable(regs);
2727
2728 gen11_gu_misc_irq_handler(gt, gu_misc_iir);
2729
2730 pmu_irq_stats(i915, IRQ_HANDLED);
2731
2732 return IRQ_HANDLED;
2733}
2734
2735static inline u32 dg1_master_intr_disable(void __iomem * const regs)
2736{
2737 u32 val;
2738
2739
2740 raw_reg_write(regs, DG1_MSTR_TILE_INTR, 0);
2741
2742
2743 val = raw_reg_read(regs, DG1_MSTR_TILE_INTR);
2744 if (unlikely(!val))
2745 return 0;
2746
2747 raw_reg_write(regs, DG1_MSTR_TILE_INTR, val);
2748
2749 return val;
2750}
2751
2752static inline void dg1_master_intr_enable(void __iomem * const regs)
2753{
2754 raw_reg_write(regs, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ);
2755}
2756
2757static irqreturn_t dg1_irq_handler(int irq, void *arg)
2758{
2759 struct drm_i915_private * const i915 = arg;
2760 struct intel_gt *gt = &i915->gt;
2761 void __iomem * const regs = i915->uncore.regs;
2762 u32 master_tile_ctl, master_ctl;
2763 u32 gu_misc_iir;
2764
2765 if (!intel_irqs_enabled(i915))
2766 return IRQ_NONE;
2767
2768 master_tile_ctl = dg1_master_intr_disable(regs);
2769 if (!master_tile_ctl) {
2770 dg1_master_intr_enable(regs);
2771 return IRQ_NONE;
2772 }
2773
2774
2775 if (master_tile_ctl & DG1_MSTR_TILE(0)) {
2776 master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
2777 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, master_ctl);
2778 } else {
2779 DRM_ERROR("Tile not supported: 0x%08x\n", master_tile_ctl);
2780 dg1_master_intr_enable(regs);
2781 return IRQ_NONE;
2782 }
2783
2784 gen11_gt_irq_handler(gt, master_ctl);
2785
2786 if (master_ctl & GEN11_DISPLAY_IRQ)
2787 gen11_display_irq_handler(i915);
2788
2789 gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
2790
2791 dg1_master_intr_enable(regs);
2792
2793 gen11_gu_misc_irq_handler(gt, gu_misc_iir);
2794
2795 pmu_irq_stats(i915, IRQ_HANDLED);
2796
2797 return IRQ_HANDLED;
2798}
2799
2800
2801
2802
2803int i8xx_enable_vblank(struct drm_crtc *crtc)
2804{
2805 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2806 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2807 unsigned long irqflags;
2808
2809 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2810 i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2811 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2812
2813 return 0;
2814}
2815
2816int i915gm_enable_vblank(struct drm_crtc *crtc)
2817{
2818 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2819
2820
2821
2822
2823
2824
2825
2826 if (dev_priv->vblank_enabled++ == 0)
2827 intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
2828
2829 return i8xx_enable_vblank(crtc);
2830}
2831
2832int i965_enable_vblank(struct drm_crtc *crtc)
2833{
2834 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2835 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2836 unsigned long irqflags;
2837
2838 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2839 i915_enable_pipestat(dev_priv, pipe,
2840 PIPE_START_VBLANK_INTERRUPT_STATUS);
2841 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2842
2843 return 0;
2844}
2845
2846int ilk_enable_vblank(struct drm_crtc *crtc)
2847{
2848 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2849 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2850 unsigned long irqflags;
2851 u32 bit = DISPLAY_VER(dev_priv) >= 7 ?
2852 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2853
2854 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2855 ilk_enable_display_irq(dev_priv, bit);
2856 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2857
2858
2859
2860
2861 if (HAS_PSR(dev_priv))
2862 drm_crtc_vblank_restore(crtc);
2863
2864 return 0;
2865}
2866
2867static bool gen11_dsi_configure_te(struct intel_crtc *intel_crtc,
2868 bool enable)
2869{
2870 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
2871 enum port port;
2872 u32 tmp;
2873
2874 if (!(intel_crtc->mode_flags &
2875 (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0)))
2876 return false;
2877
2878
2879 if (intel_crtc->mode_flags & I915_MODE_FLAG_DSI_USE_TE1)
2880 port = PORT_B;
2881 else
2882 port = PORT_A;
2883
2884 tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_MASK_REG(port));
2885 if (enable)
2886 tmp &= ~DSI_TE_EVENT;
2887 else
2888 tmp |= DSI_TE_EVENT;
2889
2890 intel_uncore_write(&dev_priv->uncore, DSI_INTR_MASK_REG(port), tmp);
2891
2892 tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_IDENT_REG(port));
2893 intel_uncore_write(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), tmp);
2894
2895 return true;
2896}
2897
2898int bdw_enable_vblank(struct drm_crtc *_crtc)
2899{
2900 struct intel_crtc *crtc = to_intel_crtc(_crtc);
2901 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2902 enum pipe pipe = crtc->pipe;
2903 unsigned long irqflags;
2904
2905 if (gen11_dsi_configure_te(crtc, true))
2906 return 0;
2907
2908 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2909 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2910 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2911
2912
2913
2914
2915 if (HAS_PSR(dev_priv))
2916 drm_crtc_vblank_restore(&crtc->base);
2917
2918 return 0;
2919}
2920
2921
2922
2923
2924void i8xx_disable_vblank(struct drm_crtc *crtc)
2925{
2926 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2927 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2928 unsigned long irqflags;
2929
2930 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2931 i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2932 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2933}
2934
2935void i915gm_disable_vblank(struct drm_crtc *crtc)
2936{
2937 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2938
2939 i8xx_disable_vblank(crtc);
2940
2941 if (--dev_priv->vblank_enabled == 0)
2942 intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
2943}
2944
2945void i965_disable_vblank(struct drm_crtc *crtc)
2946{
2947 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2948 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2949 unsigned long irqflags;
2950
2951 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2952 i915_disable_pipestat(dev_priv, pipe,
2953 PIPE_START_VBLANK_INTERRUPT_STATUS);
2954 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2955}
2956
2957void ilk_disable_vblank(struct drm_crtc *crtc)
2958{
2959 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2960 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2961 unsigned long irqflags;
2962 u32 bit = DISPLAY_VER(dev_priv) >= 7 ?
2963 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2964
2965 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2966 ilk_disable_display_irq(dev_priv, bit);
2967 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2968}
2969
2970void bdw_disable_vblank(struct drm_crtc *_crtc)
2971{
2972 struct intel_crtc *crtc = to_intel_crtc(_crtc);
2973 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2974 enum pipe pipe = crtc->pipe;
2975 unsigned long irqflags;
2976
2977 if (gen11_dsi_configure_te(crtc, false))
2978 return;
2979
2980 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2981 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2982 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2983}
2984
2985static void ibx_irq_reset(struct drm_i915_private *dev_priv)
2986{
2987 struct intel_uncore *uncore = &dev_priv->uncore;
2988
2989 if (HAS_PCH_NOP(dev_priv))
2990 return;
2991
2992 GEN3_IRQ_RESET(uncore, SDE);
2993
2994 if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
2995 intel_uncore_write(&dev_priv->uncore, SERR_INT, 0xffffffff);
2996}
2997
2998static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
2999{
3000 struct intel_uncore *uncore = &dev_priv->uncore;
3001
3002 if (IS_CHERRYVIEW(dev_priv))
3003 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3004 else
3005 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK);
3006
3007 i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
3008 intel_uncore_write(uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT));
3009
3010 i9xx_pipestat_irq_reset(dev_priv);
3011
3012 GEN3_IRQ_RESET(uncore, VLV_);
3013 dev_priv->irq_mask = ~0u;
3014}
3015
3016static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3017{
3018 struct intel_uncore *uncore = &dev_priv->uncore;
3019
3020 u32 pipestat_mask;
3021 u32 enable_mask;
3022 enum pipe pipe;
3023
3024 pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS;
3025
3026 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3027 for_each_pipe(dev_priv, pipe)
3028 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3029
3030 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3031 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3032 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3033 I915_LPE_PIPE_A_INTERRUPT |
3034 I915_LPE_PIPE_B_INTERRUPT;
3035
3036 if (IS_CHERRYVIEW(dev_priv))
3037 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |
3038 I915_LPE_PIPE_C_INTERRUPT;
3039
3040 drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u);
3041
3042 dev_priv->irq_mask = ~enable_mask;
3043
3044 GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask);
3045}
3046
3047
3048
3049static void ilk_irq_reset(struct drm_i915_private *dev_priv)
3050{
3051 struct intel_uncore *uncore = &dev_priv->uncore;
3052
3053 GEN3_IRQ_RESET(uncore, DE);
3054 dev_priv->irq_mask = ~0u;
3055
3056 if (GRAPHICS_VER(dev_priv) == 7)
3057 intel_uncore_write(uncore, GEN7_ERR_INT, 0xffffffff);
3058
3059 if (IS_HASWELL(dev_priv)) {
3060 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
3061 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
3062 }
3063
3064 gen5_gt_irq_reset(&dev_priv->gt);
3065
3066 ibx_irq_reset(dev_priv);
3067}
3068
3069static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
3070{
3071 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0);
3072 intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);
3073
3074 gen5_gt_irq_reset(&dev_priv->gt);
3075
3076 spin_lock_irq(&dev_priv->irq_lock);
3077 if (dev_priv->display_irqs_enabled)
3078 vlv_display_irq_reset(dev_priv);
3079 spin_unlock_irq(&dev_priv->irq_lock);
3080}
3081
3082static void gen8_display_irq_reset(struct drm_i915_private *dev_priv)
3083{
3084 struct intel_uncore *uncore = &dev_priv->uncore;
3085 enum pipe pipe;
3086
3087 if (!HAS_DISPLAY(dev_priv))
3088 return;
3089
3090 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
3091 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
3092
3093 for_each_pipe(dev_priv, pipe)
3094 if (intel_display_power_is_enabled(dev_priv,
3095 POWER_DOMAIN_PIPE(pipe)))
3096 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3097
3098 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
3099 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
3100}
3101
3102static void gen8_irq_reset(struct drm_i915_private *dev_priv)
3103{
3104 struct intel_uncore *uncore = &dev_priv->uncore;
3105
3106 gen8_master_intr_disable(dev_priv->uncore.regs);
3107
3108 gen8_gt_irq_reset(&dev_priv->gt);
3109 gen8_display_irq_reset(dev_priv);
3110 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3111
3112 if (HAS_PCH_SPLIT(dev_priv))
3113 ibx_irq_reset(dev_priv);
3114
3115}
3116
3117static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
3118{
3119 struct intel_uncore *uncore = &dev_priv->uncore;
3120 enum pipe pipe;
3121 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
3122 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
3123
3124 if (!HAS_DISPLAY(dev_priv))
3125 return;
3126
3127 intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);
3128
3129 if (DISPLAY_VER(dev_priv) >= 12) {
3130 enum transcoder trans;
3131
3132 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
3133 enum intel_display_power_domain domain;
3134
3135 domain = POWER_DOMAIN_TRANSCODER(trans);
3136 if (!intel_display_power_is_enabled(dev_priv, domain))
3137 continue;
3138
3139 intel_uncore_write(uncore, TRANS_PSR_IMR(trans), 0xffffffff);
3140 intel_uncore_write(uncore, TRANS_PSR_IIR(trans), 0xffffffff);
3141 }
3142 } else {
3143 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
3144 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
3145 }
3146
3147 for_each_pipe(dev_priv, pipe)
3148 if (intel_display_power_is_enabled(dev_priv,
3149 POWER_DOMAIN_PIPE(pipe)))
3150 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3151
3152 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
3153 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
3154 GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_);
3155
3156 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3157 GEN3_IRQ_RESET(uncore, SDE);
3158}
3159
3160static void gen11_irq_reset(struct drm_i915_private *dev_priv)
3161{
3162 struct intel_uncore *uncore = &dev_priv->uncore;
3163
3164 gen11_master_intr_disable(dev_priv->uncore.regs);
3165
3166 gen11_gt_irq_reset(&dev_priv->gt);
3167 gen11_display_irq_reset(dev_priv);
3168
3169 GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
3170 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3171}
3172
3173static void dg1_irq_reset(struct drm_i915_private *dev_priv)
3174{
3175 struct intel_uncore *uncore = &dev_priv->uncore;
3176
3177 dg1_master_intr_disable(dev_priv->uncore.regs);
3178
3179 gen11_gt_irq_reset(&dev_priv->gt);
3180 gen11_display_irq_reset(dev_priv);
3181
3182 GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
3183 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3184}
3185
3186void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3187 u8 pipe_mask)
3188{
3189 struct intel_uncore *uncore = &dev_priv->uncore;
3190 u32 extra_ier = GEN8_PIPE_VBLANK |
3191 gen8_de_pipe_underrun_mask(dev_priv) |
3192 gen8_de_pipe_flip_done_mask(dev_priv);
3193 enum pipe pipe;
3194
3195 spin_lock_irq(&dev_priv->irq_lock);
3196
3197 if (!intel_irqs_enabled(dev_priv)) {
3198 spin_unlock_irq(&dev_priv->irq_lock);
3199 return;
3200 }
3201
3202 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3203 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
3204 dev_priv->de_irq_mask[pipe],
3205 ~dev_priv->de_irq_mask[pipe] | extra_ier);
3206
3207 spin_unlock_irq(&dev_priv->irq_lock);
3208}
3209
3210void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3211 u8 pipe_mask)
3212{
3213 struct intel_uncore *uncore = &dev_priv->uncore;
3214 enum pipe pipe;
3215
3216 spin_lock_irq(&dev_priv->irq_lock);
3217
3218 if (!intel_irqs_enabled(dev_priv)) {
3219 spin_unlock_irq(&dev_priv->irq_lock);
3220 return;
3221 }
3222
3223 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3224 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3225
3226 spin_unlock_irq(&dev_priv->irq_lock);
3227
3228
3229 intel_synchronize_irq(dev_priv);
3230}
3231
3232static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
3233{
3234 struct intel_uncore *uncore = &dev_priv->uncore;
3235
3236 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0);
3237 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);
3238
3239 gen8_gt_irq_reset(&dev_priv->gt);
3240
3241 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3242
3243 spin_lock_irq(&dev_priv->irq_lock);
3244 if (dev_priv->display_irqs_enabled)
3245 vlv_display_irq_reset(dev_priv);
3246 spin_unlock_irq(&dev_priv->irq_lock);
3247}
3248
3249static u32 ibx_hotplug_enables(struct drm_i915_private *i915,
3250 enum hpd_pin pin)
3251{
3252 switch (pin) {
3253 case HPD_PORT_A:
3254
3255
3256
3257
3258 return HAS_PCH_LPT_LP(i915) ?
3259 PORTA_HOTPLUG_ENABLE : 0;
3260 case HPD_PORT_B:
3261 return PORTB_HOTPLUG_ENABLE |
3262 PORTB_PULSE_DURATION_2ms;
3263 case HPD_PORT_C:
3264 return PORTC_HOTPLUG_ENABLE |
3265 PORTC_PULSE_DURATION_2ms;
3266 case HPD_PORT_D:
3267 return PORTD_HOTPLUG_ENABLE |
3268 PORTD_PULSE_DURATION_2ms;
3269 default:
3270 return 0;
3271 }
3272}
3273
3274static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
3275{
3276 u32 hotplug;
3277
3278
3279
3280
3281
3282
3283 hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
3284 hotplug &= ~(PORTA_HOTPLUG_ENABLE |
3285 PORTB_HOTPLUG_ENABLE |
3286 PORTC_HOTPLUG_ENABLE |
3287 PORTD_HOTPLUG_ENABLE |
3288 PORTB_PULSE_DURATION_MASK |
3289 PORTC_PULSE_DURATION_MASK |
3290 PORTD_PULSE_DURATION_MASK);
3291 hotplug |= intel_hpd_hotplug_enables(dev_priv, ibx_hotplug_enables);
3292 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug);
3293}
3294
3295static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3296{
3297 u32 hotplug_irqs, enabled_irqs;
3298
3299 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3300 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3301
3302 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3303
3304 ibx_hpd_detection_setup(dev_priv);
3305}
3306
3307static u32 icp_ddi_hotplug_enables(struct drm_i915_private *i915,
3308 enum hpd_pin pin)
3309{
3310 switch (pin) {
3311 case HPD_PORT_A:
3312 case HPD_PORT_B:
3313 case HPD_PORT_C:
3314 case HPD_PORT_D:
3315 return SHOTPLUG_CTL_DDI_HPD_ENABLE(pin);
3316 default:
3317 return 0;
3318 }
3319}
3320
3321static u32 icp_tc_hotplug_enables(struct drm_i915_private *i915,
3322 enum hpd_pin pin)
3323{
3324 switch (pin) {
3325 case HPD_PORT_TC1:
3326 case HPD_PORT_TC2:
3327 case HPD_PORT_TC3:
3328 case HPD_PORT_TC4:
3329 case HPD_PORT_TC5:
3330 case HPD_PORT_TC6:
3331 return ICP_TC_HPD_ENABLE(pin);
3332 default:
3333 return 0;
3334 }
3335}
3336
3337static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv)
3338{
3339 u32 hotplug;
3340
3341 hotplug = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_DDI);
3342 hotplug &= ~(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A) |
3343 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) |
3344 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C) |
3345 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_D));
3346 hotplug |= intel_hpd_hotplug_enables(dev_priv, icp_ddi_hotplug_enables);
3347 intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_DDI, hotplug);
3348}
3349
3350static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
3351{
3352 u32 hotplug;
3353
3354 hotplug = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_TC);
3355 hotplug &= ~(ICP_TC_HPD_ENABLE(HPD_PORT_TC1) |
3356 ICP_TC_HPD_ENABLE(HPD_PORT_TC2) |
3357 ICP_TC_HPD_ENABLE(HPD_PORT_TC3) |
3358 ICP_TC_HPD_ENABLE(HPD_PORT_TC4) |
3359 ICP_TC_HPD_ENABLE(HPD_PORT_TC5) |
3360 ICP_TC_HPD_ENABLE(HPD_PORT_TC6));
3361 hotplug |= intel_hpd_hotplug_enables(dev_priv, icp_tc_hotplug_enables);
3362 intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_TC, hotplug);
3363}
3364
3365static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
3366{
3367 u32 hotplug_irqs, enabled_irqs;
3368
3369 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3370 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3371
3372 if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP)
3373 intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
3374
3375 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3376
3377 icp_ddi_hpd_detection_setup(dev_priv);
3378 icp_tc_hpd_detection_setup(dev_priv);
3379}
3380
3381static u32 gen11_hotplug_enables(struct drm_i915_private *i915,
3382 enum hpd_pin pin)
3383{
3384 switch (pin) {
3385 case HPD_PORT_TC1:
3386 case HPD_PORT_TC2:
3387 case HPD_PORT_TC3:
3388 case HPD_PORT_TC4:
3389 case HPD_PORT_TC5:
3390 case HPD_PORT_TC6:
3391 return GEN11_HOTPLUG_CTL_ENABLE(pin);
3392 default:
3393 return 0;
3394 }
3395}
3396
3397static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
3398{
3399 u32 val;
3400
3401 val = intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN1);
3402 val |= (INVERT_DDIA_HPD |
3403 INVERT_DDIB_HPD |
3404 INVERT_DDIC_HPD |
3405 INVERT_DDID_HPD);
3406 intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN1, val);
3407
3408 icp_hpd_irq_setup(dev_priv);
3409}
3410
3411static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
3412{
3413 u32 hotplug;
3414
3415 hotplug = intel_uncore_read(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL);
3416 hotplug &= ~(GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
3417 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
3418 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
3419 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
3420 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
3421 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6));
3422 hotplug |= intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables);
3423 intel_uncore_write(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, hotplug);
3424}
3425
3426static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3427{
3428 u32 hotplug;
3429
3430 hotplug = intel_uncore_read(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL);
3431 hotplug &= ~(GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
3432 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
3433 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
3434 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
3435 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
3436 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6));
3437 hotplug |= intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables);
3438 intel_uncore_write(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, hotplug);
3439}
3440
3441static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
3442{
3443 u32 hotplug_irqs, enabled_irqs;
3444 u32 val;
3445
3446 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3447 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
3448
3449 val = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IMR);
3450 val &= ~hotplug_irqs;
3451 val |= ~enabled_irqs & hotplug_irqs;
3452 intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IMR, val);
3453 intel_uncore_posting_read(&dev_priv->uncore, GEN11_DE_HPD_IMR);
3454
3455 gen11_tc_hpd_detection_setup(dev_priv);
3456 gen11_tbt_hpd_detection_setup(dev_priv);
3457
3458 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3459 icp_hpd_irq_setup(dev_priv);
3460}
3461
3462static u32 spt_hotplug_enables(struct drm_i915_private *i915,
3463 enum hpd_pin pin)
3464{
3465 switch (pin) {
3466 case HPD_PORT_A:
3467 return PORTA_HOTPLUG_ENABLE;
3468 case HPD_PORT_B:
3469 return PORTB_HOTPLUG_ENABLE;
3470 case HPD_PORT_C:
3471 return PORTC_HOTPLUG_ENABLE;
3472 case HPD_PORT_D:
3473 return PORTD_HOTPLUG_ENABLE;
3474 default:
3475 return 0;
3476 }
3477}
3478
3479static u32 spt_hotplug2_enables(struct drm_i915_private *i915,
3480 enum hpd_pin pin)
3481{
3482 switch (pin) {
3483 case HPD_PORT_E:
3484 return PORTE_HOTPLUG_ENABLE;
3485 default:
3486 return 0;
3487 }
3488}
3489
3490static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3491{
3492 u32 val, hotplug;
3493
3494
3495 if (HAS_PCH_CNP(dev_priv)) {
3496 val = intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN1);
3497 val &= ~CHASSIS_CLK_REQ_DURATION_MASK;
3498 val |= CHASSIS_CLK_REQ_DURATION(0xf);
3499 intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN1, val);
3500 }
3501
3502
3503 hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
3504 hotplug &= ~(PORTA_HOTPLUG_ENABLE |
3505 PORTB_HOTPLUG_ENABLE |
3506 PORTC_HOTPLUG_ENABLE |
3507 PORTD_HOTPLUG_ENABLE);
3508 hotplug |= intel_hpd_hotplug_enables(dev_priv, spt_hotplug_enables);
3509 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug);
3510
3511 hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG2);
3512 hotplug &= ~PORTE_HOTPLUG_ENABLE;
3513 hotplug |= intel_hpd_hotplug_enables(dev_priv, spt_hotplug2_enables);
3514 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG2, hotplug);
3515}
3516
3517static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3518{
3519 u32 hotplug_irqs, enabled_irqs;
3520
3521 if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
3522 intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
3523
3524 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3525 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3526
3527 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3528
3529 spt_hpd_detection_setup(dev_priv);
3530}
3531
3532static u32 ilk_hotplug_enables(struct drm_i915_private *i915,
3533 enum hpd_pin pin)
3534{
3535 switch (pin) {
3536 case HPD_PORT_A:
3537 return DIGITAL_PORTA_HOTPLUG_ENABLE |
3538 DIGITAL_PORTA_PULSE_DURATION_2ms;
3539 default:
3540 return 0;
3541 }
3542}
3543
3544static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
3545{
3546 u32 hotplug;
3547
3548
3549
3550
3551
3552
3553 hotplug = intel_uncore_read(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL);
3554 hotplug &= ~(DIGITAL_PORTA_HOTPLUG_ENABLE |
3555 DIGITAL_PORTA_PULSE_DURATION_MASK);
3556 hotplug |= intel_hpd_hotplug_enables(dev_priv, ilk_hotplug_enables);
3557 intel_uncore_write(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3558}
3559
3560static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3561{
3562 u32 hotplug_irqs, enabled_irqs;
3563
3564 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3565 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
3566
3567 if (DISPLAY_VER(dev_priv) >= 8)
3568 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3569 else
3570 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3571
3572 ilk_hpd_detection_setup(dev_priv);
3573
3574 ibx_hpd_irq_setup(dev_priv);
3575}
3576
3577static u32 bxt_hotplug_enables(struct drm_i915_private *i915,
3578 enum hpd_pin pin)
3579{
3580 u32 hotplug;
3581
3582 switch (pin) {
3583 case HPD_PORT_A:
3584 hotplug = PORTA_HOTPLUG_ENABLE;
3585 if (intel_bios_is_port_hpd_inverted(i915, PORT_A))
3586 hotplug |= BXT_DDIA_HPD_INVERT;
3587 return hotplug;
3588 case HPD_PORT_B:
3589 hotplug = PORTB_HOTPLUG_ENABLE;
3590 if (intel_bios_is_port_hpd_inverted(i915, PORT_B))
3591 hotplug |= BXT_DDIB_HPD_INVERT;
3592 return hotplug;
3593 case HPD_PORT_C:
3594 hotplug = PORTC_HOTPLUG_ENABLE;
3595 if (intel_bios_is_port_hpd_inverted(i915, PORT_C))
3596 hotplug |= BXT_DDIC_HPD_INVERT;
3597 return hotplug;
3598 default:
3599 return 0;
3600 }
3601}
3602
3603static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3604{
3605 u32 hotplug;
3606
3607 hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
3608 hotplug &= ~(PORTA_HOTPLUG_ENABLE |
3609 PORTB_HOTPLUG_ENABLE |
3610 PORTC_HOTPLUG_ENABLE |
3611 BXT_DDIA_HPD_INVERT |
3612 BXT_DDIB_HPD_INVERT |
3613 BXT_DDIC_HPD_INVERT);
3614 hotplug |= intel_hpd_hotplug_enables(dev_priv, bxt_hotplug_enables);
3615 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug);
3616}
3617
3618static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3619{
3620 u32 hotplug_irqs, enabled_irqs;
3621
3622 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3623 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
3624
3625 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3626
3627 bxt_hpd_detection_setup(dev_priv);
3628}
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
3642{
3643 struct intel_uncore *uncore = &dev_priv->uncore;
3644 u32 mask;
3645
3646 if (HAS_PCH_NOP(dev_priv))
3647 return;
3648
3649 if (HAS_PCH_IBX(dev_priv))
3650 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3651 else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
3652 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3653 else
3654 mask = SDE_GMBUS_CPT;
3655
3656 GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
3657}
3658
3659static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
3660{
3661 struct intel_uncore *uncore = &dev_priv->uncore;
3662 u32 display_mask, extra_mask;
3663
3664 if (GRAPHICS_VER(dev_priv) >= 7) {
3665 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3666 DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);
3667 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3668 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3669 DE_PLANE_FLIP_DONE_IVB(PLANE_C) |
3670 DE_PLANE_FLIP_DONE_IVB(PLANE_B) |
3671 DE_PLANE_FLIP_DONE_IVB(PLANE_A) |
3672 DE_DP_A_HOTPLUG_IVB);
3673 } else {
3674 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3675 DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE |
3676 DE_PIPEA_CRC_DONE | DE_POISON);
3677 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK |
3678 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3679 DE_PLANE_FLIP_DONE(PLANE_A) |
3680 DE_PLANE_FLIP_DONE(PLANE_B) |
3681 DE_DP_A_HOTPLUG);
3682 }
3683
3684 if (IS_HASWELL(dev_priv)) {
3685 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
3686 display_mask |= DE_EDP_PSR_INT_HSW;
3687 }
3688
3689 if (IS_IRONLAKE_M(dev_priv))
3690 extra_mask |= DE_PCU_EVENT;
3691
3692 dev_priv->irq_mask = ~display_mask;
3693
3694 ibx_irq_postinstall(dev_priv);
3695
3696 gen5_gt_irq_postinstall(&dev_priv->gt);
3697
3698 GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
3699 display_mask | extra_mask);
3700}
3701
3702void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3703{
3704 lockdep_assert_held(&dev_priv->irq_lock);
3705
3706 if (dev_priv->display_irqs_enabled)
3707 return;
3708
3709 dev_priv->display_irqs_enabled = true;
3710
3711 if (intel_irqs_enabled(dev_priv)) {
3712 vlv_display_irq_reset(dev_priv);
3713 vlv_display_irq_postinstall(dev_priv);
3714 }
3715}
3716
3717void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3718{
3719 lockdep_assert_held(&dev_priv->irq_lock);
3720
3721 if (!dev_priv->display_irqs_enabled)
3722 return;
3723
3724 dev_priv->display_irqs_enabled = false;
3725
3726 if (intel_irqs_enabled(dev_priv))
3727 vlv_display_irq_reset(dev_priv);
3728}
3729
3730
3731static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
3732{
3733 gen5_gt_irq_postinstall(&dev_priv->gt);
3734
3735 spin_lock_irq(&dev_priv->irq_lock);
3736 if (dev_priv->display_irqs_enabled)
3737 vlv_display_irq_postinstall(dev_priv);
3738 spin_unlock_irq(&dev_priv->irq_lock);
3739
3740 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3741 intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);
3742}
3743
3744static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3745{
3746 struct intel_uncore *uncore = &dev_priv->uncore;
3747
3748 u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) |
3749 GEN8_PIPE_CDCLK_CRC_DONE;
3750 u32 de_pipe_enables;
3751 u32 de_port_masked = gen8_de_port_aux_mask(dev_priv);
3752 u32 de_port_enables;
3753 u32 de_misc_masked = GEN8_DE_EDP_PSR;
3754 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
3755 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
3756 enum pipe pipe;
3757
3758 if (!HAS_DISPLAY(dev_priv))
3759 return;
3760
3761 if (DISPLAY_VER(dev_priv) <= 10)
3762 de_misc_masked |= GEN8_DE_MISC_GSE;
3763
3764 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3765 de_port_masked |= BXT_DE_PORT_GMBUS;
3766
3767 if (DISPLAY_VER(dev_priv) >= 11) {
3768 enum port port;
3769
3770 if (intel_bios_is_dsi_present(dev_priv, &port))
3771 de_port_masked |= DSI0_TE | DSI1_TE;
3772 }
3773
3774 de_pipe_enables = de_pipe_masked |
3775 GEN8_PIPE_VBLANK |
3776 gen8_de_pipe_underrun_mask(dev_priv) |
3777 gen8_de_pipe_flip_done_mask(dev_priv);
3778
3779 de_port_enables = de_port_masked;
3780 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3781 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3782 else if (IS_BROADWELL(dev_priv))
3783 de_port_enables |= BDW_DE_PORT_HOTPLUG_MASK;
3784
3785 if (DISPLAY_VER(dev_priv) >= 12) {
3786 enum transcoder trans;
3787
3788 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
3789 enum intel_display_power_domain domain;
3790
3791 domain = POWER_DOMAIN_TRANSCODER(trans);
3792 if (!intel_display_power_is_enabled(dev_priv, domain))
3793 continue;
3794
3795 gen3_assert_iir_is_zero(uncore, TRANS_PSR_IIR(trans));
3796 }
3797 } else {
3798 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
3799 }
3800
3801 for_each_pipe(dev_priv, pipe) {
3802 dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
3803
3804 if (intel_display_power_is_enabled(dev_priv,
3805 POWER_DOMAIN_PIPE(pipe)))
3806 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
3807 dev_priv->de_irq_mask[pipe],
3808 de_pipe_enables);
3809 }
3810
3811 GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3812 GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3813
3814 if (DISPLAY_VER(dev_priv) >= 11) {
3815 u32 de_hpd_masked = 0;
3816 u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK |
3817 GEN11_DE_TBT_HOTPLUG_MASK;
3818
3819 GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
3820 de_hpd_enables);
3821 }
3822}
3823
3824static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
3825{
3826 struct intel_uncore *uncore = &dev_priv->uncore;
3827 u32 mask = SDE_GMBUS_ICP;
3828
3829 GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
3830}
3831
3832static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
3833{
3834 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3835 icp_irq_postinstall(dev_priv);
3836 else if (HAS_PCH_SPLIT(dev_priv))
3837 ibx_irq_postinstall(dev_priv);
3838
3839 gen8_gt_irq_postinstall(&dev_priv->gt);
3840 gen8_de_irq_postinstall(dev_priv);
3841
3842 gen8_master_intr_enable(dev_priv->uncore.regs);
3843}
3844
3845static void gen11_de_irq_postinstall(struct drm_i915_private *dev_priv)
3846{
3847 if (!HAS_DISPLAY(dev_priv))
3848 return;
3849
3850 gen8_de_irq_postinstall(dev_priv);
3851
3852 intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL,
3853 GEN11_DISPLAY_IRQ_ENABLE);
3854}
3855
3856static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
3857{
3858 struct intel_uncore *uncore = &dev_priv->uncore;
3859 u32 gu_misc_masked = GEN11_GU_MISC_GSE;
3860
3861 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3862 icp_irq_postinstall(dev_priv);
3863
3864 gen11_gt_irq_postinstall(&dev_priv->gt);
3865 gen11_de_irq_postinstall(dev_priv);
3866
3867 GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
3868
3869 gen11_master_intr_enable(uncore->regs);
3870 intel_uncore_posting_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ);
3871}
3872
3873static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
3874{
3875 struct intel_uncore *uncore = &dev_priv->uncore;
3876 u32 gu_misc_masked = GEN11_GU_MISC_GSE;
3877
3878 gen11_gt_irq_postinstall(&dev_priv->gt);
3879
3880 GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
3881
3882 if (HAS_DISPLAY(dev_priv)) {
3883 icp_irq_postinstall(dev_priv);
3884 gen8_de_irq_postinstall(dev_priv);
3885 intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL,
3886 GEN11_DISPLAY_IRQ_ENABLE);
3887 }
3888
3889 dg1_master_intr_enable(dev_priv->uncore.regs);
3890 intel_uncore_posting_read(&dev_priv->uncore, DG1_MSTR_TILE_INTR);
3891}
3892
3893static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
3894{
3895 gen8_gt_irq_postinstall(&dev_priv->gt);
3896
3897 spin_lock_irq(&dev_priv->irq_lock);
3898 if (dev_priv->display_irqs_enabled)
3899 vlv_display_irq_postinstall(dev_priv);
3900 spin_unlock_irq(&dev_priv->irq_lock);
3901
3902 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3903 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);
3904}
3905
3906static void i8xx_irq_reset(struct drm_i915_private *dev_priv)
3907{
3908 struct intel_uncore *uncore = &dev_priv->uncore;
3909
3910 i9xx_pipestat_irq_reset(dev_priv);
3911
3912 GEN2_IRQ_RESET(uncore);
3913 dev_priv->irq_mask = ~0u;
3914}
3915
3916static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv)
3917{
3918 struct intel_uncore *uncore = &dev_priv->uncore;
3919 u16 enable_mask;
3920
3921 intel_uncore_write16(uncore,
3922 EMR,
3923 ~(I915_ERROR_PAGE_TABLE |
3924 I915_ERROR_MEMORY_REFRESH));
3925
3926
3927 dev_priv->irq_mask =
3928 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3929 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3930 I915_MASTER_ERROR_INTERRUPT);
3931
3932 enable_mask =
3933 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3934 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3935 I915_MASTER_ERROR_INTERRUPT |
3936 I915_USER_INTERRUPT;
3937
3938 GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask);
3939
3940
3941
3942 spin_lock_irq(&dev_priv->irq_lock);
3943 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3944 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3945 spin_unlock_irq(&dev_priv->irq_lock);
3946}
3947
3948static void i8xx_error_irq_ack(struct drm_i915_private *i915,
3949 u16 *eir, u16 *eir_stuck)
3950{
3951 struct intel_uncore *uncore = &i915->uncore;
3952 u16 emr;
3953
3954 *eir = intel_uncore_read16(uncore, EIR);
3955
3956 if (*eir)
3957 intel_uncore_write16(uncore, EIR, *eir);
3958
3959 *eir_stuck = intel_uncore_read16(uncore, EIR);
3960 if (*eir_stuck == 0)
3961 return;
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973 emr = intel_uncore_read16(uncore, EMR);
3974 intel_uncore_write16(uncore, EMR, 0xffff);
3975 intel_uncore_write16(uncore, EMR, emr | *eir_stuck);
3976}
3977
3978static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv,
3979 u16 eir, u16 eir_stuck)
3980{
3981 DRM_DEBUG("Master Error: EIR 0x%04x\n", eir);
3982
3983 if (eir_stuck)
3984 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%04x, masked\n",
3985 eir_stuck);
3986}
3987
3988static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv,
3989 u32 *eir, u32 *eir_stuck)
3990{
3991 u32 emr;
3992
3993 *eir = intel_uncore_read(&dev_priv->uncore, EIR);
3994
3995 intel_uncore_write(&dev_priv->uncore, EIR, *eir);
3996
3997 *eir_stuck = intel_uncore_read(&dev_priv->uncore, EIR);
3998 if (*eir_stuck == 0)
3999 return;
4000
4001
4002
4003
4004
4005
4006
4007
4008
4009
4010
4011 emr = intel_uncore_read(&dev_priv->uncore, EMR);
4012 intel_uncore_write(&dev_priv->uncore, EMR, 0xffffffff);
4013 intel_uncore_write(&dev_priv->uncore, EMR, emr | *eir_stuck);
4014}
4015
4016static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv,
4017 u32 eir, u32 eir_stuck)
4018{
4019 DRM_DEBUG("Master Error, EIR 0x%08x\n", eir);
4020
4021 if (eir_stuck)
4022 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%08x, masked\n",
4023 eir_stuck);
4024}
4025
4026static irqreturn_t i8xx_irq_handler(int irq, void *arg)
4027{
4028 struct drm_i915_private *dev_priv = arg;
4029 irqreturn_t ret = IRQ_NONE;
4030
4031 if (!intel_irqs_enabled(dev_priv))
4032 return IRQ_NONE;
4033
4034
4035 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4036
4037 do {
4038 u32 pipe_stats[I915_MAX_PIPES] = {};
4039 u16 eir = 0, eir_stuck = 0;
4040 u16 iir;
4041
4042 iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR);
4043 if (iir == 0)
4044 break;
4045
4046 ret = IRQ_HANDLED;
4047
4048
4049
4050 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
4051
4052 if (iir & I915_MASTER_ERROR_INTERRUPT)
4053 i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4054
4055 intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir);
4056
4057 if (iir & I915_USER_INTERRUPT)
4058 intel_engine_cs_irq(dev_priv->gt.engine[RCS0], iir);
4059
4060 if (iir & I915_MASTER_ERROR_INTERRUPT)
4061 i8xx_error_irq_handler(dev_priv, eir, eir_stuck);
4062
4063 i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4064 } while (0);
4065
4066 pmu_irq_stats(dev_priv, ret);
4067
4068 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4069
4070 return ret;
4071}
4072
4073static void i915_irq_reset(struct drm_i915_private *dev_priv)
4074{
4075 struct intel_uncore *uncore = &dev_priv->uncore;
4076
4077 if (I915_HAS_HOTPLUG(dev_priv)) {
4078 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4079 intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT));
4080 }
4081
4082 i9xx_pipestat_irq_reset(dev_priv);
4083
4084 GEN3_IRQ_RESET(uncore, GEN2_);
4085 dev_priv->irq_mask = ~0u;
4086}
4087
4088static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
4089{
4090 struct intel_uncore *uncore = &dev_priv->uncore;
4091 u32 enable_mask;
4092
4093 intel_uncore_write(&dev_priv->uncore, EMR, ~(I915_ERROR_PAGE_TABLE |
4094 I915_ERROR_MEMORY_REFRESH));
4095
4096
4097 dev_priv->irq_mask =
4098 ~(I915_ASLE_INTERRUPT |
4099 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4100 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4101 I915_MASTER_ERROR_INTERRUPT);
4102
4103 enable_mask =
4104 I915_ASLE_INTERRUPT |
4105 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4106 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4107 I915_MASTER_ERROR_INTERRUPT |
4108 I915_USER_INTERRUPT;
4109
4110 if (I915_HAS_HOTPLUG(dev_priv)) {
4111
4112 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
4113
4114 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
4115 }
4116
4117 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
4118
4119
4120
4121 spin_lock_irq(&dev_priv->irq_lock);
4122 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4123 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4124 spin_unlock_irq(&dev_priv->irq_lock);
4125
4126 i915_enable_asle_pipestat(dev_priv);
4127}
4128
4129static irqreturn_t i915_irq_handler(int irq, void *arg)
4130{
4131 struct drm_i915_private *dev_priv = arg;
4132 irqreturn_t ret = IRQ_NONE;
4133
4134 if (!intel_irqs_enabled(dev_priv))
4135 return IRQ_NONE;
4136
4137
4138 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4139
4140 do {
4141 u32 pipe_stats[I915_MAX_PIPES] = {};
4142 u32 eir = 0, eir_stuck = 0;
4143 u32 hotplug_status = 0;
4144 u32 iir;
4145
4146 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
4147 if (iir == 0)
4148 break;
4149
4150 ret = IRQ_HANDLED;
4151
4152 if (I915_HAS_HOTPLUG(dev_priv) &&
4153 iir & I915_DISPLAY_PORT_INTERRUPT)
4154 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4155
4156
4157
4158 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
4159
4160 if (iir & I915_MASTER_ERROR_INTERRUPT)
4161 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4162
4163 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
4164
4165 if (iir & I915_USER_INTERRUPT)
4166 intel_engine_cs_irq(dev_priv->gt.engine[RCS0], iir);
4167
4168 if (iir & I915_MASTER_ERROR_INTERRUPT)
4169 i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
4170
4171 if (hotplug_status)
4172 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4173
4174 i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4175 } while (0);
4176
4177 pmu_irq_stats(dev_priv, ret);
4178
4179 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4180
4181 return ret;
4182}
4183
4184static void i965_irq_reset(struct drm_i915_private *dev_priv)
4185{
4186 struct intel_uncore *uncore = &dev_priv->uncore;
4187
4188 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4189 intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT));
4190
4191 i9xx_pipestat_irq_reset(dev_priv);
4192
4193 GEN3_IRQ_RESET(uncore, GEN2_);
4194 dev_priv->irq_mask = ~0u;
4195}
4196
4197static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
4198{
4199 struct intel_uncore *uncore = &dev_priv->uncore;
4200 u32 enable_mask;
4201 u32 error_mask;
4202
4203
4204
4205
4206
4207 if (IS_G4X(dev_priv)) {
4208 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4209 GM45_ERROR_MEM_PRIV |
4210 GM45_ERROR_CP_PRIV |
4211 I915_ERROR_MEMORY_REFRESH);
4212 } else {
4213 error_mask = ~(I915_ERROR_PAGE_TABLE |
4214 I915_ERROR_MEMORY_REFRESH);
4215 }
4216 intel_uncore_write(&dev_priv->uncore, EMR, error_mask);
4217
4218
4219 dev_priv->irq_mask =
4220 ~(I915_ASLE_INTERRUPT |
4221 I915_DISPLAY_PORT_INTERRUPT |
4222 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4223 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4224 I915_MASTER_ERROR_INTERRUPT);
4225
4226 enable_mask =
4227 I915_ASLE_INTERRUPT |
4228 I915_DISPLAY_PORT_INTERRUPT |
4229 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4230 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4231 I915_MASTER_ERROR_INTERRUPT |
4232 I915_USER_INTERRUPT;
4233
4234 if (IS_G4X(dev_priv))
4235 enable_mask |= I915_BSD_USER_INTERRUPT;
4236
4237 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
4238
4239
4240
4241 spin_lock_irq(&dev_priv->irq_lock);
4242 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4243 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4244 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4245 spin_unlock_irq(&dev_priv->irq_lock);
4246
4247 i915_enable_asle_pipestat(dev_priv);
4248}
4249
4250static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4251{
4252 u32 hotplug_en;
4253
4254 lockdep_assert_held(&dev_priv->irq_lock);
4255
4256
4257
4258 hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4259
4260
4261
4262
4263 if (IS_G4X(dev_priv))
4264 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4265 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4266
4267
4268 i915_hotplug_interrupt_update_locked(dev_priv,
4269 HOTPLUG_INT_EN_MASK |
4270 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4271 CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4272 hotplug_en);
4273}
4274
4275static irqreturn_t i965_irq_handler(int irq, void *arg)
4276{
4277 struct drm_i915_private *dev_priv = arg;
4278 irqreturn_t ret = IRQ_NONE;
4279
4280 if (!intel_irqs_enabled(dev_priv))
4281 return IRQ_NONE;
4282
4283
4284 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4285
4286 do {
4287 u32 pipe_stats[I915_MAX_PIPES] = {};
4288 u32 eir = 0, eir_stuck = 0;
4289 u32 hotplug_status = 0;
4290 u32 iir;
4291
4292 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
4293 if (iir == 0)
4294 break;
4295
4296 ret = IRQ_HANDLED;
4297
4298 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4299 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4300
4301
4302
4303 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
4304
4305 if (iir & I915_MASTER_ERROR_INTERRUPT)
4306 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4307
4308 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
4309
4310 if (iir & I915_USER_INTERRUPT)
4311 intel_engine_cs_irq(dev_priv->gt.engine[RCS0],
4312 iir);
4313
4314 if (iir & I915_BSD_USER_INTERRUPT)
4315 intel_engine_cs_irq(dev_priv->gt.engine[VCS0],
4316 iir >> 25);
4317
4318 if (iir & I915_MASTER_ERROR_INTERRUPT)
4319 i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
4320
4321 if (hotplug_status)
4322 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4323
4324 i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4325 } while (0);
4326
4327 pmu_irq_stats(dev_priv, IRQ_HANDLED);
4328
4329 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4330
4331 return ret;
4332}
4333
4334
4335
4336
4337
4338
4339
4340
4341void intel_irq_init(struct drm_i915_private *dev_priv)
4342{
4343 struct drm_device *dev = &dev_priv->drm;
4344 int i;
4345
4346 INIT_WORK(&dev_priv->l3_parity.error_work, ivb_parity_work);
4347 for (i = 0; i < MAX_L3_SLICES; ++i)
4348 dev_priv->l3_parity.remap_info[i] = NULL;
4349
4350
4351 if (HAS_GT_UC(dev_priv) && GRAPHICS_VER(dev_priv) < 11)
4352 dev_priv->gt.pm_guc_events = GUC_INTR_GUC2HOST << 16;
4353
4354 if (!HAS_DISPLAY(dev_priv))
4355 return;
4356
4357 intel_hpd_init_pins(dev_priv);
4358
4359 intel_hpd_init_work(dev_priv);
4360
4361 dev->vblank_disable_immediate = true;
4362
4363
4364
4365
4366
4367
4368
4369 dev_priv->display_irqs_enabled = true;
4370 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4371 dev_priv->display_irqs_enabled = false;
4372
4373 dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4374
4375
4376
4377
4378
4379
4380 dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);
4381
4382 if (HAS_GMCH(dev_priv)) {
4383 if (I915_HAS_HOTPLUG(dev_priv))
4384 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4385 } else {
4386 if (HAS_PCH_DG1(dev_priv))
4387 dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
4388 else if (DISPLAY_VER(dev_priv) >= 11)
4389 dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
4390 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
4391 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4392 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
4393 dev_priv->display.hpd_irq_setup = icp_hpd_irq_setup;
4394 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
4395 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4396 else
4397 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4398 }
4399}
4400
4401
4402
4403
4404
4405
4406
4407void intel_irq_fini(struct drm_i915_private *i915)
4408{
4409 int i;
4410
4411 for (i = 0; i < MAX_L3_SLICES; ++i)
4412 kfree(i915->l3_parity.remap_info[i]);
4413}
4414
4415static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv)
4416{
4417 if (HAS_GMCH(dev_priv)) {
4418 if (IS_CHERRYVIEW(dev_priv))
4419 return cherryview_irq_handler;
4420 else if (IS_VALLEYVIEW(dev_priv))
4421 return valleyview_irq_handler;
4422 else if (GRAPHICS_VER(dev_priv) == 4)
4423 return i965_irq_handler;
4424 else if (GRAPHICS_VER(dev_priv) == 3)
4425 return i915_irq_handler;
4426 else
4427 return i8xx_irq_handler;
4428 } else {
4429 if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10))
4430 return dg1_irq_handler;
4431 else if (GRAPHICS_VER(dev_priv) >= 11)
4432 return gen11_irq_handler;
4433 else if (GRAPHICS_VER(dev_priv) >= 8)
4434 return gen8_irq_handler;
4435 else
4436 return ilk_irq_handler;
4437 }
4438}
4439
4440static void intel_irq_reset(struct drm_i915_private *dev_priv)
4441{
4442 if (HAS_GMCH(dev_priv)) {
4443 if (IS_CHERRYVIEW(dev_priv))
4444 cherryview_irq_reset(dev_priv);
4445 else if (IS_VALLEYVIEW(dev_priv))
4446 valleyview_irq_reset(dev_priv);
4447 else if (GRAPHICS_VER(dev_priv) == 4)
4448 i965_irq_reset(dev_priv);
4449 else if (GRAPHICS_VER(dev_priv) == 3)
4450 i915_irq_reset(dev_priv);
4451 else
4452 i8xx_irq_reset(dev_priv);
4453 } else {
4454 if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10))
4455 dg1_irq_reset(dev_priv);
4456 else if (GRAPHICS_VER(dev_priv) >= 11)
4457 gen11_irq_reset(dev_priv);
4458 else if (GRAPHICS_VER(dev_priv) >= 8)
4459 gen8_irq_reset(dev_priv);
4460 else
4461 ilk_irq_reset(dev_priv);
4462 }
4463}
4464
4465static void intel_irq_postinstall(struct drm_i915_private *dev_priv)
4466{
4467 if (HAS_GMCH(dev_priv)) {
4468 if (IS_CHERRYVIEW(dev_priv))
4469 cherryview_irq_postinstall(dev_priv);
4470 else if (IS_VALLEYVIEW(dev_priv))
4471 valleyview_irq_postinstall(dev_priv);
4472 else if (GRAPHICS_VER(dev_priv) == 4)
4473 i965_irq_postinstall(dev_priv);
4474 else if (GRAPHICS_VER(dev_priv) == 3)
4475 i915_irq_postinstall(dev_priv);
4476 else
4477 i8xx_irq_postinstall(dev_priv);
4478 } else {
4479 if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10))
4480 dg1_irq_postinstall(dev_priv);
4481 else if (GRAPHICS_VER(dev_priv) >= 11)
4482 gen11_irq_postinstall(dev_priv);
4483 else if (GRAPHICS_VER(dev_priv) >= 8)
4484 gen8_irq_postinstall(dev_priv);
4485 else
4486 ilk_irq_postinstall(dev_priv);
4487 }
4488}
4489
4490
4491
4492
4493
4494
4495
4496
4497
4498
4499
4500
4501int intel_irq_install(struct drm_i915_private *dev_priv)
4502{
4503 int irq = to_pci_dev(dev_priv->drm.dev)->irq;
4504 int ret;
4505
4506
4507
4508
4509
4510
4511 dev_priv->runtime_pm.irqs_enabled = true;
4512
4513 dev_priv->irq_enabled = true;
4514
4515 intel_irq_reset(dev_priv);
4516
4517 ret = request_irq(irq, intel_irq_handler(dev_priv),
4518 IRQF_SHARED, DRIVER_NAME, dev_priv);
4519 if (ret < 0) {
4520 dev_priv->irq_enabled = false;
4521 return ret;
4522 }
4523
4524 intel_irq_postinstall(dev_priv);
4525
4526 return ret;
4527}
4528
4529
4530
4531
4532
4533
4534
4535
4536void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4537{
4538 int irq = to_pci_dev(dev_priv->drm.dev)->irq;
4539
4540
4541
4542
4543
4544
4545
4546 if (!dev_priv->irq_enabled)
4547 return;
4548
4549 dev_priv->irq_enabled = false;
4550
4551 intel_irq_reset(dev_priv);
4552
4553 free_irq(irq, dev_priv);
4554
4555 intel_hpd_cancel_work(dev_priv);
4556 dev_priv->runtime_pm.irqs_enabled = false;
4557}
4558
4559
4560
4561
4562
4563
4564
4565
4566void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4567{
4568 intel_irq_reset(dev_priv);
4569 dev_priv->runtime_pm.irqs_enabled = false;
4570 intel_synchronize_irq(dev_priv);
4571}
4572
4573
4574
4575
4576
4577
4578
4579
4580void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4581{
4582 dev_priv->runtime_pm.irqs_enabled = true;
4583 intel_irq_reset(dev_priv);
4584 intel_irq_postinstall(dev_priv);
4585}
4586
4587bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
4588{
4589 return dev_priv->runtime_pm.irqs_enabled;
4590}
4591
4592void intel_synchronize_irq(struct drm_i915_private *i915)
4593{
4594 synchronize_irq(to_pci_dev(i915->drm.dev)->irq);
4595}
4596
4597void intel_synchronize_hardirq(struct drm_i915_private *i915)
4598{
4599 synchronize_hardirq(to_pci_dev(i915->drm.dev)->irq);
4600}
4601