LXR linux/drivers/gpu/drm/i915/intel_device

   1/*
   2 * Copyright © 2014-2017 Intel Corporation
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice (including the next
  12 * paragraph) shall be included in all copies or substantial portions of the
  13 * Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21 * IN THE SOFTWARE.
  22 *
  23 */
  24
  25#ifndef _INTEL_DEVICE_INFO_H_
  26#define _INTEL_DEVICE_INFO_H_
  27
  28#include <uapi/drm/i915_drm.h>
  29
  30#include "intel_step.h"
  31
  32#include "display/intel_display.h"
  33
  34#include "gt/intel_engine_types.h"
  35#include "gt/intel_context_types.h"
  36#include "gt/intel_sseu.h"
  37
  38struct drm_printer;
  39struct drm_i915_private;
  40
  41/* Keep in gen based order, and chronological order within a gen */
  42enum intel_platform {
  43        INTEL_PLATFORM_UNINITIALIZED = 0,
  44        /* gen2 */
  45        INTEL_I830,
  46        INTEL_I845G,
  47        INTEL_I85X,
  48        INTEL_I865G,
  49        /* gen3 */
  50        INTEL_I915G,
  51        INTEL_I915GM,
  52        INTEL_I945G,
  53        INTEL_I945GM,
  54        INTEL_G33,
  55        INTEL_PINEVIEW,
  56        /* gen4 */
  57        INTEL_I965G,
  58        INTEL_I965GM,
  59        INTEL_G45,
  60        INTEL_GM45,
  61        /* gen5 */
  62        INTEL_IRONLAKE,
  63        /* gen6 */
  64        INTEL_SANDYBRIDGE,
  65        /* gen7 */
  66        INTEL_IVYBRIDGE,
  67        INTEL_VALLEYVIEW,
  68        INTEL_HASWELL,
  69        /* gen8 */
  70        INTEL_BROADWELL,
  71        INTEL_CHERRYVIEW,
  72        /* gen9 */
  73        INTEL_SKYLAKE,
  74        INTEL_BROXTON,
  75        INTEL_KABYLAKE,
  76        INTEL_GEMINILAKE,
  77        INTEL_COFFEELAKE,
  78        INTEL_COMETLAKE,
  79        /* gen11 */
  80        INTEL_ICELAKE,
  81        INTEL_ELKHARTLAKE,
  82        INTEL_JASPERLAKE,
  83        /* gen12 */
  84        INTEL_TIGERLAKE,
  85        INTEL_ROCKETLAKE,
  86        INTEL_DG1,
  87        INTEL_ALDERLAKE_S,
  88        INTEL_ALDERLAKE_P,
  89        INTEL_XEHPSDV,
  90        INTEL_DG2,
  91        INTEL_MAX_PLATFORMS
  92};
  93
  94/*
  95 * Subplatform bits share the same namespace per parent platform. In other words
  96 * it is fine for the same bit to be used on multiple parent platforms.
  97 */
  98
  99#define INTEL_SUBPLATFORM_BITS (2)
 100#define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
 101
 102/* HSW/BDW/SKL/KBL/CFL */
 103#define INTEL_SUBPLATFORM_ULT   (0)
 104#define INTEL_SUBPLATFORM_ULX   (1)
 105
 106/* ICL */
 107#define INTEL_SUBPLATFORM_PORTF (0)
 108
 109/* DG2 */
 110#define INTEL_SUBPLATFORM_G10   0
 111#define INTEL_SUBPLATFORM_G11   1
 112
 113enum intel_ppgtt_type {
 114        INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
 115        INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
 116        INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
 117};
 118
 119#define DEV_INFO_FOR_EACH_FLAG(func) \
 120        func(is_mobile); \
 121        func(is_lp); \
 122        func(require_force_probe); \
 123        func(is_dgfx); \
 124        /* Keep has_* in alphabetical order */ \
 125        func(has_64bit_reloc); \
 126        func(gpu_reset_clobbers_display); \
 127        func(has_reset_engine); \
 128        func(has_global_mocs); \
 129        func(has_gt_uc); \
 130        func(has_l3_dpf); \
 131        func(has_llc); \
 132        func(has_logical_ring_contexts); \
 133        func(has_logical_ring_elsq); \
 134        func(has_mslices); \
 135        func(has_pooled_eu); \
 136        func(has_rc6); \
 137        func(has_rc6p); \
 138        func(has_rps); \
 139        func(has_runtime_pm); \
 140        func(has_snoop); \
 141        func(has_coherent_ggtt); \
 142        func(unfenced_needs_alignment); \
 143        func(hws_needs_physical);
 144
 145#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
 146        /* Keep in alphabetical order */ \
 147        func(cursor_needs_physical); \
 148        func(has_cdclk_crawl); \
 149        func(has_dmc); \
 150        func(has_ddi); \
 151        func(has_dp_mst); \
 152        func(has_dsb); \
 153        func(has_dsc); \
 154        func(has_fbc); \
 155        func(has_fpga_dbg); \
 156        func(has_gmch); \
 157        func(has_hdcp); \
 158        func(has_hotplug); \
 159        func(has_hti); \
 160        func(has_ipc); \
 161        func(has_modular_fia); \
 162        func(has_overlay); \
 163        func(has_psr); \
 164        func(has_psr_hw_tracking); \
 165        func(overlay_needs_physical); \
 166        func(supports_tv);
 167
 168struct intel_device_info {
 169        u8 graphics_ver;
 170        u8 graphics_rel;
 171        u8 media_ver;
 172        u8 media_rel;
 173
 174        intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */
 175
 176        enum intel_platform platform;
 177
 178        unsigned int dma_mask_size; /* available DMA address bits */
 179
 180        enum intel_ppgtt_type ppgtt_type;
 181        unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
 182
 183        unsigned int page_sizes; /* page sizes supported by the HW */
 184
 185        u32 memory_regions; /* regions supported by the HW */
 186
 187        u32 display_mmio_offset;
 188
 189        u8 gt; /* GT number, 0 if undefined */
 190
 191        u8 pipe_mask;
 192        u8 cpu_transcoder_mask;
 193
 194        u8 abox_mask;
 195
 196#define DEFINE_FLAG(name) u8 name:1
 197        DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
 198#undef DEFINE_FLAG
 199
 200        struct {
 201                u8 ver;
 202
 203#define DEFINE_FLAG(name) u8 name:1
 204                DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
 205#undef DEFINE_FLAG
 206        } display;
 207
 208        struct {
 209                u16 size; /* in blocks */
 210                u8 slice_mask;
 211        } dbuf;
 212
 213        /* Register offsets for the various display pipes and transcoders */
 214        int pipe_offsets[I915_MAX_TRANSCODERS];
 215        int trans_offsets[I915_MAX_TRANSCODERS];
 216        int cursor_offsets[I915_MAX_PIPES];
 217
 218        struct color_luts {
 219                u32 degamma_lut_size;
 220                u32 gamma_lut_size;
 221                u32 degamma_lut_tests;
 222                u32 gamma_lut_tests;
 223        } color;
 224};
 225
 226struct intel_runtime_info {
 227        /*
 228         * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
 229         * into single runtime conditionals, and also to provide groundwork
 230         * for future per platform, or per SKU build optimizations.
 231         *
 232         * Array can be extended when necessary if the corresponding
 233         * BUILD_BUG_ON is hit.
 234         */
 235        u32 platform_mask[2];
 236
 237        u16 device_id;
 238
 239        u8 num_sprites[I915_MAX_PIPES];
 240        u8 num_scalers[I915_MAX_PIPES];
 241
 242        u32 rawclk_freq;
 243
 244        struct intel_step_info step;
 245};
 246
 247struct intel_driver_caps {
 248        unsigned int scheduler;
 249        bool has_logical_contexts:1;
 250};
 251
 252const char *intel_platform_name(enum intel_platform platform);
 253
 254void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
 255void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
 256
 257void intel_device_info_print_static(const struct intel_device_info *info,
 258                                    struct drm_printer *p);
 259void intel_device_info_print_runtime(const struct intel_runtime_info *info,
 260                                     struct drm_printer *p);
 261
 262void intel_driver_caps_print(const struct intel_driver_caps *caps,
 263                             struct drm_printer *p);
 264
 265#endif
 266