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7
8#include "ingenic-drm.h"
9#include "ingenic-ipu.h"
10
11#include <linux/clk.h>
12#include <linux/component.h>
13#include <linux/gcd.h>
14#include <linux/interrupt.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/of_device.h>
18#include <linux/regmap.h>
19#include <linux/time.h>
20
21#include <drm/drm_atomic.h>
22#include <drm/drm_atomic_helper.h>
23#include <drm/drm_damage_helper.h>
24#include <drm/drm_drv.h>
25#include <drm/drm_fb_cma_helper.h>
26#include <drm/drm_fourcc.h>
27#include <drm/drm_gem_atomic_helper.h>
28#include <drm/drm_gem_cma_helper.h>
29#include <drm/drm_gem_framebuffer_helper.h>
30#include <drm/drm_plane.h>
31#include <drm/drm_plane_helper.h>
32#include <drm/drm_property.h>
33#include <drm/drm_vblank.h>
34
35struct ingenic_ipu;
36
37struct soc_info {
38 const u32 *formats;
39 size_t num_formats;
40 bool has_bicubic;
41 bool manual_restart;
42
43 void (*set_coefs)(struct ingenic_ipu *ipu, unsigned int reg,
44 unsigned int sharpness, bool downscale,
45 unsigned int weight, unsigned int offset);
46};
47
48struct ingenic_ipu {
49 struct drm_plane plane;
50 struct drm_device *drm;
51 struct device *dev, *master;
52 struct regmap *map;
53 struct clk *clk;
54 const struct soc_info *soc_info;
55 bool clk_enabled;
56
57 unsigned int num_w, num_h, denom_w, denom_h;
58
59 dma_addr_t addr_y, addr_u, addr_v;
60
61 struct drm_property *sharpness_prop;
62 unsigned int sharpness;
63};
64
65
66#define I2F(i) ((s32)(i) * 65536)
67#define F2I(f) ((f) / 65536)
68#define FMUL(fa, fb) ((s32)(((s64)(fa) * (s64)(fb)) / 65536))
69#define SHARPNESS_INCR (I2F(-1) / 8)
70
71static inline struct ingenic_ipu *plane_to_ingenic_ipu(struct drm_plane *plane)
72{
73 return container_of(plane, struct ingenic_ipu, plane);
74}
75
76
77
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79
80
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87
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89
90
91
92static inline s32 cubic_conv(s32 f_a, s32 f_x)
93{
94 const s32 f_1 = I2F(1);
95 const s32 f_2 = I2F(2);
96 const s32 f_3 = I2F(3);
97 const s32 f_4 = I2F(4);
98 const s32 f_x2 = FMUL(f_x, f_x);
99 const s32 f_x3 = FMUL(f_x, f_x2);
100
101 if (f_x <= f_1)
102 return FMUL((f_a + f_2), f_x3) - FMUL((f_a + f_3), f_x2) + f_1;
103 else if (f_x <= f_2)
104 return FMUL(f_a, (f_x3 - 5 * f_x2 + 8 * f_x - f_4));
105 else
106 return 0;
107}
108
109
110
111
112
113
114
115
116
117
118
119static void jz4760_set_coefs(struct ingenic_ipu *ipu, unsigned int reg,
120 unsigned int sharpness, bool downscale,
121 unsigned int weight, unsigned int offset)
122{
123 u32 val;
124 s32 w0, w1, w2, w3;
125
126 weight = clamp_val(weight, 0, 512);
127
128 if (sharpness < 2) {
129
130
131
132
133
134 if (sharpness == 0)
135 weight = weight >= 256 ? 512 : 0;
136 w0 = 0;
137 w1 = weight;
138 w2 = 512 - weight;
139 w3 = 0;
140 } else {
141 const s32 f_a = SHARPNESS_INCR * sharpness;
142 const s32 f_h = I2F(1) / 2;
143
144
145
146
147
148
149
150 weight = 512 - weight;
151 w0 = F2I(f_h + 512 * cubic_conv(f_a, I2F(512 + weight) / 512));
152 w1 = F2I(f_h + 512 * cubic_conv(f_a, I2F(0 + weight) / 512));
153 w2 = F2I(f_h + 512 * cubic_conv(f_a, I2F(512 - weight) / 512));
154 w3 = F2I(f_h + 512 * cubic_conv(f_a, I2F(1024 - weight) / 512));
155 w0 = clamp_val(w0, -1024, 1023);
156 w1 = clamp_val(w1, -1024, 1023);
157 w2 = clamp_val(w2, -1024, 1023);
158 w3 = clamp_val(w3, -1024, 1023);
159 }
160
161 val = ((w1 & JZ4760_IPU_RSZ_COEF_MASK) << JZ4760_IPU_RSZ_COEF31_LSB) |
162 ((w0 & JZ4760_IPU_RSZ_COEF_MASK) << JZ4760_IPU_RSZ_COEF20_LSB);
163 regmap_write(ipu->map, reg, val);
164
165 val = ((w3 & JZ4760_IPU_RSZ_COEF_MASK) << JZ4760_IPU_RSZ_COEF31_LSB) |
166 ((w2 & JZ4760_IPU_RSZ_COEF_MASK) << JZ4760_IPU_RSZ_COEF20_LSB) |
167 ((offset & JZ4760_IPU_RSZ_OFFSET_MASK) << JZ4760_IPU_RSZ_OFFSET_LSB);
168 regmap_write(ipu->map, reg, val);
169}
170
171static void jz4725b_set_coefs(struct ingenic_ipu *ipu, unsigned int reg,
172 unsigned int sharpness, bool downscale,
173 unsigned int weight, unsigned int offset)
174{
175 u32 val = JZ4725B_IPU_RSZ_LUT_OUT_EN;
176 unsigned int i;
177
178 weight = clamp_val(weight, 0, 512);
179
180 if (sharpness == 0)
181 weight = weight >= 256 ? 512 : 0;
182
183 val |= (weight & JZ4725B_IPU_RSZ_LUT_COEF_MASK) << JZ4725B_IPU_RSZ_LUT_COEF_LSB;
184 if (downscale || !!offset)
185 val |= JZ4725B_IPU_RSZ_LUT_IN_EN;
186
187 regmap_write(ipu->map, reg, val);
188
189 if (downscale) {
190 for (i = 1; i < offset; i++)
191 regmap_write(ipu->map, reg, JZ4725B_IPU_RSZ_LUT_IN_EN);
192 }
193}
194
195static void ingenic_ipu_set_downscale_coefs(struct ingenic_ipu *ipu,
196 unsigned int reg,
197 unsigned int num,
198 unsigned int denom)
199{
200 unsigned int i, offset, weight, weight_num = denom;
201
202 for (i = 0; i < num; i++) {
203 weight_num = num + (weight_num - num) % (num * 2);
204 weight = 512 - 512 * (weight_num - num) / (num * 2);
205 weight_num += denom * 2;
206 offset = (weight_num - num) / (num * 2);
207
208 ipu->soc_info->set_coefs(ipu, reg, ipu->sharpness,
209 true, weight, offset);
210 }
211}
212
213static void ingenic_ipu_set_integer_upscale_coefs(struct ingenic_ipu *ipu,
214 unsigned int reg,
215 unsigned int num)
216{
217
218
219
220
221 unsigned int i;
222
223 for (i = 0; i < num; i++)
224 ipu->soc_info->set_coefs(ipu, reg, 0, false, 512, i == num - 1);
225}
226
227static void ingenic_ipu_set_upscale_coefs(struct ingenic_ipu *ipu,
228 unsigned int reg,
229 unsigned int num,
230 unsigned int denom)
231{
232 unsigned int i, offset, weight, weight_num = 0;
233
234 for (i = 0; i < num; i++) {
235 weight = 512 - 512 * weight_num / num;
236 weight_num += denom;
237 offset = weight_num >= num;
238
239 if (offset)
240 weight_num -= num;
241
242 ipu->soc_info->set_coefs(ipu, reg, ipu->sharpness,
243 false, weight, offset);
244 }
245}
246
247static void ingenic_ipu_set_coefs(struct ingenic_ipu *ipu, unsigned int reg,
248 unsigned int num, unsigned int denom)
249{
250
251 regmap_write(ipu->map, reg, -1);
252
253 if (denom > num)
254 ingenic_ipu_set_downscale_coefs(ipu, reg, num, denom);
255 else if (denom == 1)
256 ingenic_ipu_set_integer_upscale_coefs(ipu, reg, num);
257 else
258 ingenic_ipu_set_upscale_coefs(ipu, reg, num, denom);
259}
260
261static int reduce_fraction(unsigned int *num, unsigned int *denom)
262{
263 unsigned long d = gcd(*num, *denom);
264
265
266 if (*num > 31 * d)
267 return -EINVAL;
268
269 *num /= d;
270 *denom /= d;
271 return 0;
272}
273
274static inline bool osd_changed(struct drm_plane_state *state,
275 struct drm_plane_state *oldstate)
276{
277 return state->src_x != oldstate->src_x ||
278 state->src_y != oldstate->src_y ||
279 state->src_w != oldstate->src_w ||
280 state->src_h != oldstate->src_h ||
281 state->crtc_x != oldstate->crtc_x ||
282 state->crtc_y != oldstate->crtc_y ||
283 state->crtc_w != oldstate->crtc_w ||
284 state->crtc_h != oldstate->crtc_h;
285}
286
287static void ingenic_ipu_plane_atomic_update(struct drm_plane *plane,
288 struct drm_atomic_state *state)
289{
290 struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane);
291 struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state, plane);
292 struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, plane);
293 const struct drm_format_info *finfo;
294 u32 ctrl, stride = 0, coef_index = 0, format = 0;
295 bool needs_modeset, upscaling_w, upscaling_h;
296 int err;
297
298 if (!newstate || !newstate->fb)
299 return;
300
301 finfo = drm_format_info(newstate->fb->format->format);
302
303 if (!ipu->clk_enabled) {
304 err = clk_enable(ipu->clk);
305 if (err) {
306 dev_err(ipu->dev, "Unable to enable clock: %d\n", err);
307 return;
308 }
309
310 ipu->clk_enabled = true;
311 }
312
313
314 needs_modeset = drm_atomic_crtc_needs_modeset(newstate->crtc->state);
315 if (needs_modeset) {
316 regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_RST);
317
318
319 regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL,
320 JZ_IPU_CTRL_CHIP_EN | JZ_IPU_CTRL_LCDC_SEL);
321 }
322
323 if (ingenic_drm_map_noncoherent(ipu->master))
324 drm_fb_cma_sync_non_coherent(ipu->drm, oldstate, newstate);
325
326
327 ipu->addr_y = drm_fb_cma_get_gem_addr(newstate->fb, newstate, 0);
328 if (finfo->num_planes > 1)
329 ipu->addr_u = drm_fb_cma_get_gem_addr(newstate->fb, newstate,
330 1);
331 if (finfo->num_planes > 2)
332 ipu->addr_v = drm_fb_cma_get_gem_addr(newstate->fb, newstate,
333 2);
334
335 if (!needs_modeset)
336 return;
337
338
339 regmap_write(ipu->map, JZ_REG_IPU_Y_ADDR, ipu->addr_y);
340 regmap_write(ipu->map, JZ_REG_IPU_U_ADDR, ipu->addr_u);
341 regmap_write(ipu->map, JZ_REG_IPU_V_ADDR, ipu->addr_v);
342
343 if (finfo->num_planes == 1)
344 regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_SPKG_SEL);
345
346 ingenic_drm_plane_config(ipu->master, plane, DRM_FORMAT_XRGB8888);
347
348
349 if (finfo->num_planes > 2)
350 stride = ((newstate->src_w >> 16) * finfo->cpp[2] / finfo->hsub)
351 << JZ_IPU_UV_STRIDE_V_LSB;
352
353 if (finfo->num_planes > 1)
354 stride |= ((newstate->src_w >> 16) * finfo->cpp[1] / finfo->hsub)
355 << JZ_IPU_UV_STRIDE_U_LSB;
356
357 regmap_write(ipu->map, JZ_REG_IPU_UV_STRIDE, stride);
358
359 stride = ((newstate->src_w >> 16) * finfo->cpp[0]) << JZ_IPU_Y_STRIDE_Y_LSB;
360 regmap_write(ipu->map, JZ_REG_IPU_Y_STRIDE, stride);
361
362 regmap_write(ipu->map, JZ_REG_IPU_IN_GS,
363 (stride << JZ_IPU_IN_GS_W_LSB) |
364 ((newstate->src_h >> 16) << JZ_IPU_IN_GS_H_LSB));
365
366 switch (finfo->format) {
367 case DRM_FORMAT_XRGB1555:
368 format = JZ_IPU_D_FMT_IN_FMT_RGB555 |
369 JZ_IPU_D_FMT_RGB_OUT_OFT_RGB;
370 break;
371 case DRM_FORMAT_XBGR1555:
372 format = JZ_IPU_D_FMT_IN_FMT_RGB555 |
373 JZ_IPU_D_FMT_RGB_OUT_OFT_BGR;
374 break;
375 case DRM_FORMAT_RGB565:
376 format = JZ_IPU_D_FMT_IN_FMT_RGB565 |
377 JZ_IPU_D_FMT_RGB_OUT_OFT_RGB;
378 break;
379 case DRM_FORMAT_BGR565:
380 format = JZ_IPU_D_FMT_IN_FMT_RGB565 |
381 JZ_IPU_D_FMT_RGB_OUT_OFT_BGR;
382 break;
383 case DRM_FORMAT_XRGB8888:
384 case DRM_FORMAT_XYUV8888:
385 format = JZ_IPU_D_FMT_IN_FMT_RGB888 |
386 JZ_IPU_D_FMT_RGB_OUT_OFT_RGB;
387 break;
388 case DRM_FORMAT_XBGR8888:
389 format = JZ_IPU_D_FMT_IN_FMT_RGB888 |
390 JZ_IPU_D_FMT_RGB_OUT_OFT_BGR;
391 break;
392 case DRM_FORMAT_YUYV:
393 format = JZ_IPU_D_FMT_IN_FMT_YUV422 |
394 JZ_IPU_D_FMT_YUV_VY1UY0;
395 break;
396 case DRM_FORMAT_YVYU:
397 format = JZ_IPU_D_FMT_IN_FMT_YUV422 |
398 JZ_IPU_D_FMT_YUV_UY1VY0;
399 break;
400 case DRM_FORMAT_UYVY:
401 format = JZ_IPU_D_FMT_IN_FMT_YUV422 |
402 JZ_IPU_D_FMT_YUV_Y1VY0U;
403 break;
404 case DRM_FORMAT_VYUY:
405 format = JZ_IPU_D_FMT_IN_FMT_YUV422 |
406 JZ_IPU_D_FMT_YUV_Y1UY0V;
407 break;
408 case DRM_FORMAT_YUV411:
409 format = JZ_IPU_D_FMT_IN_FMT_YUV411;
410 break;
411 case DRM_FORMAT_YUV420:
412 format = JZ_IPU_D_FMT_IN_FMT_YUV420;
413 break;
414 case DRM_FORMAT_YUV422:
415 format = JZ_IPU_D_FMT_IN_FMT_YUV422;
416 break;
417 case DRM_FORMAT_YUV444:
418 format = JZ_IPU_D_FMT_IN_FMT_YUV444;
419 break;
420 default:
421 WARN_ONCE(1, "Unsupported format");
422 break;
423 }
424
425
426 format |= JZ_IPU_D_FMT_OUT_FMT_RGB888;
427
428
429 regmap_write(ipu->map, JZ_REG_IPU_D_FMT, format);
430
431
432 regmap_write(ipu->map, JZ_REG_IPU_OUT_GS,
433 ((newstate->crtc_w * 4) << JZ_IPU_OUT_GS_W_LSB)
434 | newstate->crtc_h << JZ_IPU_OUT_GS_H_LSB);
435 regmap_write(ipu->map, JZ_REG_IPU_OUT_STRIDE, newstate->crtc_w * 4);
436
437 if (finfo->is_yuv) {
438 regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_CSC_EN);
439
440
441
442
443
444
445
446 regmap_write(ipu->map, JZ_REG_IPU_CSC_OFFSET,
447 128 << JZ_IPU_CSC_OFFSET_CHROMA_LSB |
448 0 << JZ_IPU_CSC_OFFSET_LUMA_LSB);
449
450
451
452
453
454
455
456 regmap_write(ipu->map, JZ_REG_IPU_CSC_C0_COEF, 0x4a8);
457 regmap_write(ipu->map, JZ_REG_IPU_CSC_C1_COEF, 0x662);
458 regmap_write(ipu->map, JZ_REG_IPU_CSC_C2_COEF, 0x191);
459 regmap_write(ipu->map, JZ_REG_IPU_CSC_C3_COEF, 0x341);
460 regmap_write(ipu->map, JZ_REG_IPU_CSC_C4_COEF, 0x811);
461 }
462
463 ctrl = 0;
464
465
466
467
468
469
470 if (ipu->soc_info->has_bicubic)
471 ctrl |= JZ_IPU_CTRL_ZOOM_SEL;
472
473 upscaling_w = ipu->num_w > ipu->denom_w;
474 if (upscaling_w)
475 ctrl |= JZ_IPU_CTRL_HSCALE;
476
477 if (ipu->num_w != 1 || ipu->denom_w != 1) {
478 if (!ipu->soc_info->has_bicubic && !upscaling_w)
479 coef_index |= (ipu->denom_w - 1) << 16;
480 else
481 coef_index |= (ipu->num_w - 1) << 16;
482 ctrl |= JZ_IPU_CTRL_HRSZ_EN;
483 }
484
485 upscaling_h = ipu->num_h > ipu->denom_h;
486 if (upscaling_h)
487 ctrl |= JZ_IPU_CTRL_VSCALE;
488
489 if (ipu->num_h != 1 || ipu->denom_h != 1) {
490 if (!ipu->soc_info->has_bicubic && !upscaling_h)
491 coef_index |= ipu->denom_h - 1;
492 else
493 coef_index |= ipu->num_h - 1;
494 ctrl |= JZ_IPU_CTRL_VRSZ_EN;
495 }
496
497 regmap_update_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_ZOOM_SEL |
498 JZ_IPU_CTRL_HRSZ_EN | JZ_IPU_CTRL_VRSZ_EN |
499 JZ_IPU_CTRL_HSCALE | JZ_IPU_CTRL_VSCALE, ctrl);
500
501
502 regmap_write(ipu->map, JZ_REG_IPU_RSZ_COEF_INDEX, coef_index);
503
504 if (ipu->num_w != 1 || ipu->denom_w != 1)
505 ingenic_ipu_set_coefs(ipu, JZ_REG_IPU_HRSZ_COEF_LUT,
506 ipu->num_w, ipu->denom_w);
507
508 if (ipu->num_h != 1 || ipu->denom_h != 1)
509 ingenic_ipu_set_coefs(ipu, JZ_REG_IPU_VRSZ_COEF_LUT,
510 ipu->num_h, ipu->denom_h);
511
512
513 regmap_write(ipu->map, JZ_REG_IPU_STATUS, 0);
514
515
516 regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL,
517 JZ_IPU_CTRL_RUN | JZ_IPU_CTRL_FM_IRQ_EN);
518
519 dev_dbg(ipu->dev, "Scaling %ux%u to %ux%u (%u:%u horiz, %u:%u vert)\n",
520 newstate->src_w >> 16, newstate->src_h >> 16,
521 newstate->crtc_w, newstate->crtc_h,
522 ipu->num_w, ipu->denom_w, ipu->num_h, ipu->denom_h);
523}
524
525static int ingenic_ipu_plane_atomic_check(struct drm_plane *plane,
526 struct drm_atomic_state *state)
527{
528 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state,
529 plane);
530 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
531 plane);
532 unsigned int num_w, denom_w, num_h, denom_h, xres, yres, max_w, max_h;
533 struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane);
534 struct drm_crtc *crtc = new_plane_state->crtc ?: old_plane_state->crtc;
535 struct drm_crtc_state *crtc_state;
536
537 if (!crtc)
538 return 0;
539
540 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
541 if (WARN_ON(!crtc_state))
542 return -EINVAL;
543
544
545 if (!old_plane_state->crtc ^ !new_plane_state->crtc)
546 crtc_state->mode_changed = true;
547
548 if (!new_plane_state->crtc ||
549 !crtc_state->mode.hdisplay || !crtc_state->mode.vdisplay)
550 goto out_check_damage;
551
552
553 if (new_plane_state->crtc_x < 0 || new_plane_state->crtc_y < 0 ||
554 new_plane_state->crtc_x + new_plane_state->crtc_w > crtc_state->mode.hdisplay ||
555 new_plane_state->crtc_y + new_plane_state->crtc_h > crtc_state->mode.vdisplay)
556 return -EINVAL;
557
558
559 if ((new_plane_state->src_w >> 16) < 4 || (new_plane_state->src_h >> 16) < 4)
560 return -EINVAL;
561
562
563 if (((new_plane_state->src_w >> 16) & 1) || (new_plane_state->crtc_w & 1))
564 return -EINVAL;
565
566 if (!osd_changed(new_plane_state, old_plane_state))
567 goto out_check_damage;
568
569 crtc_state->mode_changed = true;
570
571 xres = new_plane_state->src_w >> 16;
572 yres = new_plane_state->src_h >> 16;
573
574
575
576
577
578
579
580
581 max_w = crtc_state->mode.hdisplay * 102 / 100;
582 max_h = crtc_state->mode.vdisplay * 102 / 100;
583
584 for (denom_w = xres, num_w = new_plane_state->crtc_w; num_w <= max_w; num_w++)
585 if (!reduce_fraction(&num_w, &denom_w))
586 break;
587 if (num_w > max_w)
588 return -EINVAL;
589
590 for (denom_h = yres, num_h = new_plane_state->crtc_h; num_h <= max_h; num_h++)
591 if (!reduce_fraction(&num_h, &denom_h))
592 break;
593 if (num_h > max_h)
594 return -EINVAL;
595
596 ipu->num_w = num_w;
597 ipu->num_h = num_h;
598 ipu->denom_w = denom_w;
599 ipu->denom_h = denom_h;
600
601out_check_damage:
602 if (ingenic_drm_map_noncoherent(ipu->master))
603 drm_atomic_helper_check_plane_damage(state, new_plane_state);
604
605 return 0;
606}
607
608static void ingenic_ipu_plane_atomic_disable(struct drm_plane *plane,
609 struct drm_atomic_state *state)
610{
611 struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane);
612
613 regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_STOP);
614 regmap_clear_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_CHIP_EN);
615
616 ingenic_drm_plane_disable(ipu->master, plane);
617
618 if (ipu->clk_enabled) {
619 clk_disable(ipu->clk);
620 ipu->clk_enabled = false;
621 }
622}
623
624static const struct drm_plane_helper_funcs ingenic_ipu_plane_helper_funcs = {
625 .atomic_update = ingenic_ipu_plane_atomic_update,
626 .atomic_check = ingenic_ipu_plane_atomic_check,
627 .atomic_disable = ingenic_ipu_plane_atomic_disable,
628};
629
630static int
631ingenic_ipu_plane_atomic_get_property(struct drm_plane *plane,
632 const struct drm_plane_state *state,
633 struct drm_property *property, u64 *val)
634{
635 struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane);
636
637 if (property != ipu->sharpness_prop)
638 return -EINVAL;
639
640 *val = ipu->sharpness;
641
642 return 0;
643}
644
645static int
646ingenic_ipu_plane_atomic_set_property(struct drm_plane *plane,
647 struct drm_plane_state *state,
648 struct drm_property *property, u64 val)
649{
650 struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane);
651 struct drm_crtc_state *crtc_state;
652
653 if (property != ipu->sharpness_prop)
654 return -EINVAL;
655
656 ipu->sharpness = val;
657
658 if (state->crtc) {
659 crtc_state = drm_atomic_get_existing_crtc_state(state->state, state->crtc);
660 if (WARN_ON(!crtc_state))
661 return -EINVAL;
662
663 crtc_state->mode_changed = true;
664 }
665
666 return 0;
667}
668
669static const struct drm_plane_funcs ingenic_ipu_plane_funcs = {
670 .update_plane = drm_atomic_helper_update_plane,
671 .disable_plane = drm_atomic_helper_disable_plane,
672 .reset = drm_atomic_helper_plane_reset,
673 .destroy = drm_plane_cleanup,
674
675 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
676 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
677
678 .atomic_get_property = ingenic_ipu_plane_atomic_get_property,
679 .atomic_set_property = ingenic_ipu_plane_atomic_set_property,
680};
681
682static irqreturn_t ingenic_ipu_irq_handler(int irq, void *arg)
683{
684 struct ingenic_ipu *ipu = arg;
685 struct drm_crtc *crtc = drm_crtc_from_index(ipu->drm, 0);
686 unsigned int dummy;
687
688
689 if (ipu->soc_info->manual_restart)
690 regmap_read(ipu->map, JZ_REG_IPU_STATUS, &dummy);
691
692
693 regmap_write(ipu->map, JZ_REG_IPU_STATUS, 0);
694
695
696 regmap_write(ipu->map, JZ_REG_IPU_Y_ADDR, ipu->addr_y);
697 regmap_write(ipu->map, JZ_REG_IPU_U_ADDR, ipu->addr_u);
698 regmap_write(ipu->map, JZ_REG_IPU_V_ADDR, ipu->addr_v);
699
700
701 if (ipu->soc_info->manual_restart)
702 regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_RUN);
703
704 drm_crtc_handle_vblank(crtc);
705
706 return IRQ_HANDLED;
707}
708
709static const struct regmap_config ingenic_ipu_regmap_config = {
710 .reg_bits = 32,
711 .val_bits = 32,
712 .reg_stride = 4,
713
714 .max_register = JZ_REG_IPU_OUT_PHY_T_ADDR,
715};
716
717static int ingenic_ipu_bind(struct device *dev, struct device *master, void *d)
718{
719 struct platform_device *pdev = to_platform_device(dev);
720 const struct soc_info *soc_info;
721 struct drm_device *drm = d;
722 struct drm_plane *plane;
723 struct ingenic_ipu *ipu;
724 void __iomem *base;
725 unsigned int sharpness_max;
726 int err, irq;
727
728 ipu = devm_kzalloc(dev, sizeof(*ipu), GFP_KERNEL);
729 if (!ipu)
730 return -ENOMEM;
731
732 soc_info = of_device_get_match_data(dev);
733 if (!soc_info) {
734 dev_err(dev, "Missing platform data\n");
735 return -EINVAL;
736 }
737
738 ipu->dev = dev;
739 ipu->drm = drm;
740 ipu->master = master;
741 ipu->soc_info = soc_info;
742
743 base = devm_platform_ioremap_resource(pdev, 0);
744 if (IS_ERR(base)) {
745 dev_err(dev, "Failed to get memory resource\n");
746 return PTR_ERR(base);
747 }
748
749 ipu->map = devm_regmap_init_mmio(dev, base, &ingenic_ipu_regmap_config);
750 if (IS_ERR(ipu->map)) {
751 dev_err(dev, "Failed to create regmap\n");
752 return PTR_ERR(ipu->map);
753 }
754
755 irq = platform_get_irq(pdev, 0);
756 if (irq < 0)
757 return irq;
758
759 ipu->clk = devm_clk_get(dev, "ipu");
760 if (IS_ERR(ipu->clk)) {
761 dev_err(dev, "Failed to get pixel clock\n");
762 return PTR_ERR(ipu->clk);
763 }
764
765 err = devm_request_irq(dev, irq, ingenic_ipu_irq_handler, 0,
766 dev_name(dev), ipu);
767 if (err) {
768 dev_err(dev, "Unable to request IRQ\n");
769 return err;
770 }
771
772 plane = &ipu->plane;
773 dev_set_drvdata(dev, plane);
774
775 drm_plane_helper_add(plane, &ingenic_ipu_plane_helper_funcs);
776
777 err = drm_universal_plane_init(drm, plane, 1, &ingenic_ipu_plane_funcs,
778 soc_info->formats, soc_info->num_formats,
779 NULL, DRM_PLANE_TYPE_OVERLAY, NULL);
780 if (err) {
781 dev_err(dev, "Failed to init plane: %i\n", err);
782 return err;
783 }
784
785 if (ingenic_drm_map_noncoherent(master))
786 drm_plane_enable_fb_damage_clips(plane);
787
788
789
790
791
792
793
794 sharpness_max = soc_info->has_bicubic ? 32 : 1;
795 ipu->sharpness_prop = drm_property_create_range(drm, 0, "sharpness",
796 0, sharpness_max);
797 if (!ipu->sharpness_prop) {
798 dev_err(dev, "Unable to create sharpness property\n");
799 return -ENOMEM;
800 }
801
802
803 ipu->sharpness = soc_info->has_bicubic ? 8 : 1;
804 drm_object_attach_property(&plane->base, ipu->sharpness_prop,
805 ipu->sharpness);
806
807 err = clk_prepare(ipu->clk);
808 if (err) {
809 dev_err(dev, "Unable to prepare clock\n");
810 return err;
811 }
812
813 return 0;
814}
815
816static void ingenic_ipu_unbind(struct device *dev,
817 struct device *master, void *d)
818{
819 struct ingenic_ipu *ipu = dev_get_drvdata(dev);
820
821 clk_unprepare(ipu->clk);
822}
823
824static const struct component_ops ingenic_ipu_ops = {
825 .bind = ingenic_ipu_bind,
826 .unbind = ingenic_ipu_unbind,
827};
828
829static int ingenic_ipu_probe(struct platform_device *pdev)
830{
831 return component_add(&pdev->dev, &ingenic_ipu_ops);
832}
833
834static int ingenic_ipu_remove(struct platform_device *pdev)
835{
836 component_del(&pdev->dev, &ingenic_ipu_ops);
837 return 0;
838}
839
840static const u32 jz4725b_ipu_formats[] = {
841
842
843
844
845
846
847
848
849
850
851 DRM_FORMAT_YUV411,
852 DRM_FORMAT_YUV420,
853 DRM_FORMAT_YUV422,
854 DRM_FORMAT_YUV444,
855};
856
857static const struct soc_info jz4725b_soc_info = {
858 .formats = jz4725b_ipu_formats,
859 .num_formats = ARRAY_SIZE(jz4725b_ipu_formats),
860 .has_bicubic = false,
861 .manual_restart = true,
862 .set_coefs = jz4725b_set_coefs,
863};
864
865static const u32 jz4760_ipu_formats[] = {
866 DRM_FORMAT_XRGB1555,
867 DRM_FORMAT_XBGR1555,
868 DRM_FORMAT_RGB565,
869 DRM_FORMAT_BGR565,
870 DRM_FORMAT_XRGB8888,
871 DRM_FORMAT_XBGR8888,
872 DRM_FORMAT_YUYV,
873 DRM_FORMAT_YVYU,
874 DRM_FORMAT_UYVY,
875 DRM_FORMAT_VYUY,
876 DRM_FORMAT_YUV411,
877 DRM_FORMAT_YUV420,
878 DRM_FORMAT_YUV422,
879 DRM_FORMAT_YUV444,
880 DRM_FORMAT_XYUV8888,
881};
882
883static const struct soc_info jz4760_soc_info = {
884 .formats = jz4760_ipu_formats,
885 .num_formats = ARRAY_SIZE(jz4760_ipu_formats),
886 .has_bicubic = true,
887 .manual_restart = false,
888 .set_coefs = jz4760_set_coefs,
889};
890
891static const struct of_device_id ingenic_ipu_of_match[] = {
892 { .compatible = "ingenic,jz4725b-ipu", .data = &jz4725b_soc_info },
893 { .compatible = "ingenic,jz4760-ipu", .data = &jz4760_soc_info },
894 { },
895};
896MODULE_DEVICE_TABLE(of, ingenic_ipu_of_match);
897
898static struct platform_driver ingenic_ipu_driver = {
899 .driver = {
900 .name = "ingenic-ipu",
901 .of_match_table = ingenic_ipu_of_match,
902 },
903 .probe = ingenic_ipu_probe,
904 .remove = ingenic_ipu_remove,
905};
906
907struct platform_driver *ingenic_ipu_driver_ptr = &ingenic_ipu_driver;
908