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5
6#include <linux/clk.h>
7#include <linux/module.h>
8#include <linux/of_graph.h>
9#include <linux/of_platform.h>
10#include <linux/of_reserved_mem.h>
11#include <linux/mfd/syscon.h>
12#include <linux/platform_device.h>
13#include <linux/pm_runtime.h>
14#include <linux/regmap.h>
15
16#include <drm/drm_atomic_helper.h>
17#include <drm/drm_drv.h>
18#include <drm/drm_gem_cma_helper.h>
19#include <drm/drm_gem_framebuffer_helper.h>
20#include <drm/drm_probe_helper.h>
21#include <drm/drm_vblank.h>
22
23#include "kmb_drv.h"
24#include "kmb_dsi.h"
25#include "kmb_regs.h"
26
27static int kmb_display_clk_enable(struct kmb_drm_private *kmb)
28{
29 int ret = 0;
30
31 ret = clk_prepare_enable(kmb->kmb_clk.clk_lcd);
32 if (ret) {
33 drm_err(&kmb->drm, "Failed to enable LCD clock: %d\n", ret);
34 return ret;
35 }
36 DRM_INFO("SUCCESS : enabled LCD clocks\n");
37 return 0;
38}
39
40static int kmb_initialize_clocks(struct kmb_drm_private *kmb, struct device *dev)
41{
42 int ret = 0;
43 struct regmap *msscam;
44
45 kmb->kmb_clk.clk_lcd = devm_clk_get(dev, "clk_lcd");
46 if (IS_ERR(kmb->kmb_clk.clk_lcd)) {
47 drm_err(&kmb->drm, "clk_get() failed clk_lcd\n");
48 return PTR_ERR(kmb->kmb_clk.clk_lcd);
49 }
50
51 kmb->kmb_clk.clk_pll0 = devm_clk_get(dev, "clk_pll0");
52 if (IS_ERR(kmb->kmb_clk.clk_pll0)) {
53 drm_err(&kmb->drm, "clk_get() failed clk_pll0 ");
54 return PTR_ERR(kmb->kmb_clk.clk_pll0);
55 }
56 kmb->sys_clk_mhz = clk_get_rate(kmb->kmb_clk.clk_pll0) / 1000000;
57 drm_info(&kmb->drm, "system clk = %d Mhz", kmb->sys_clk_mhz);
58
59 ret = kmb_dsi_clk_init(kmb->kmb_dsi);
60
61
62 clk_set_rate(kmb->kmb_clk.clk_lcd, KMB_LCD_DEFAULT_CLK);
63 if (clk_get_rate(kmb->kmb_clk.clk_lcd) != KMB_LCD_DEFAULT_CLK) {
64 drm_err(&kmb->drm, "failed to set to clk_lcd to %d\n",
65 KMB_LCD_DEFAULT_CLK);
66 return -1;
67 }
68 drm_dbg(&kmb->drm, "clk_lcd = %ld\n", clk_get_rate(kmb->kmb_clk.clk_lcd));
69
70 ret = kmb_display_clk_enable(kmb);
71 if (ret)
72 return ret;
73
74 msscam = syscon_regmap_lookup_by_compatible("intel,keembay-msscam");
75 if (IS_ERR(msscam)) {
76 drm_err(&kmb->drm, "failed to get msscam syscon");
77 return -1;
78 }
79
80
81 regmap_update_bits(msscam, MSS_CAM_CLK_CTRL, 0x1fff, 0x1fff);
82 regmap_update_bits(msscam, MSS_CAM_RSTN_CTRL, 0xffffffff, 0xffffffff);
83 return 0;
84}
85
86static void kmb_display_clk_disable(struct kmb_drm_private *kmb)
87{
88 clk_disable_unprepare(kmb->kmb_clk.clk_lcd);
89}
90
91static void __iomem *kmb_map_mmio(struct drm_device *drm,
92 struct platform_device *pdev,
93 char *name)
94{
95 struct resource *res;
96 void __iomem *mem;
97
98 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
99 if (!res) {
100 drm_err(drm, "failed to get resource for %s", name);
101 return ERR_PTR(-ENOMEM);
102 }
103 mem = devm_ioremap_resource(drm->dev, res);
104 if (IS_ERR(mem))
105 drm_err(drm, "failed to ioremap %s registers", name);
106 return mem;
107}
108
109static int kmb_hw_init(struct drm_device *drm, unsigned long flags)
110{
111 struct kmb_drm_private *kmb = to_kmb(drm);
112 struct platform_device *pdev = to_platform_device(drm->dev);
113 int irq_lcd;
114 int ret = 0;
115
116
117 kmb->lcd_mmio = kmb_map_mmio(drm, pdev, "lcd");
118 if (IS_ERR(kmb->lcd_mmio)) {
119 drm_err(&kmb->drm, "failed to map LCD registers\n");
120 return -ENOMEM;
121 }
122
123
124 ret = kmb_dsi_map_mmio(kmb->kmb_dsi);
125 if (ret)
126 return ret;
127
128
129 kmb_initialize_clocks(kmb, &pdev->dev);
130
131
132
133
134
135
136
137 irq_lcd = platform_get_irq(pdev, 0);
138 if (irq_lcd < 0) {
139 ret = irq_lcd;
140 drm_err(&kmb->drm, "irq_lcd not found");
141 goto setup_fail;
142 }
143
144
145 ret = of_reserved_mem_device_init(drm->dev);
146 if (ret && ret != -ENODEV)
147 return ret;
148
149 spin_lock_init(&kmb->irq_lock);
150
151 kmb->irq_lcd = irq_lcd;
152
153 return 0;
154
155 setup_fail:
156 of_reserved_mem_device_release(drm->dev);
157
158 return ret;
159}
160
161static const struct drm_mode_config_funcs kmb_mode_config_funcs = {
162 .fb_create = drm_gem_fb_create,
163 .atomic_check = drm_atomic_helper_check,
164 .atomic_commit = drm_atomic_helper_commit,
165};
166
167static int kmb_setup_mode_config(struct drm_device *drm)
168{
169 int ret;
170 struct kmb_drm_private *kmb = to_kmb(drm);
171
172 ret = drmm_mode_config_init(drm);
173 if (ret)
174 return ret;
175 drm->mode_config.min_width = KMB_FB_MIN_WIDTH;
176 drm->mode_config.min_height = KMB_FB_MIN_HEIGHT;
177 drm->mode_config.max_width = KMB_FB_MAX_WIDTH;
178 drm->mode_config.max_height = KMB_FB_MAX_HEIGHT;
179 drm->mode_config.funcs = &kmb_mode_config_funcs;
180
181 ret = kmb_setup_crtc(drm);
182 if (ret < 0) {
183 drm_err(drm, "failed to create crtc\n");
184 return ret;
185 }
186 ret = kmb_dsi_encoder_init(drm, kmb->kmb_dsi);
187
188 kmb->crtc.port = of_graph_get_port_by_id(drm->dev->of_node, 0);
189 ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
190 if (ret < 0) {
191 drm_err(drm, "failed to initialize vblank\n");
192 pm_runtime_disable(drm->dev);
193 return ret;
194 }
195
196 drm_mode_config_reset(drm);
197 return 0;
198}
199
200static irqreturn_t handle_lcd_irq(struct drm_device *dev)
201{
202 unsigned long status, val, val1;
203 int plane_id, dma0_state, dma1_state;
204 struct kmb_drm_private *kmb = to_kmb(dev);
205 u32 ctrl = 0;
206
207 status = kmb_read_lcd(kmb, LCD_INT_STATUS);
208
209 spin_lock(&kmb->irq_lock);
210 if (status & LCD_INT_EOF) {
211 kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_EOF);
212
213
214
215
216
217
218
219 for (plane_id = LAYER_0;
220 plane_id < KMB_MAX_PLANES; plane_id++) {
221 if (kmb->plane_status[plane_id].disable) {
222 kmb_clr_bitmask_lcd(kmb,
223 LCD_LAYERn_DMA_CFG
224 (plane_id),
225 LCD_DMA_LAYER_ENABLE);
226
227 kmb_clr_bitmask_lcd(kmb, LCD_CONTROL,
228 kmb->plane_status[plane_id].ctrl);
229
230 ctrl = kmb_read_lcd(kmb, LCD_CONTROL);
231 if (!(ctrl & (LCD_CTRL_VL1_ENABLE |
232 LCD_CTRL_VL2_ENABLE |
233 LCD_CTRL_GL1_ENABLE |
234 LCD_CTRL_GL2_ENABLE))) {
235
236
237
238
239 kmb_clr_bitmask_lcd(kmb, LCD_CONTROL,
240 LCD_CTRL_PIPELINE_DMA);
241 }
242
243 kmb->plane_status[plane_id].disable = false;
244 }
245 }
246 if (kmb->kmb_under_flow) {
247
248 dma0_state = (kmb->layer_no == 0) ?
249 LCD_VIDEO0_DMA0_STATE : LCD_VIDEO1_DMA0_STATE;
250 dma1_state = (kmb->layer_no == 0) ?
251 LCD_VIDEO0_DMA1_STATE : LCD_VIDEO1_DMA1_STATE;
252
253 do {
254 kmb_write_lcd(kmb, LCD_FIFO_FLUSH, 1);
255 val = kmb_read_lcd(kmb, dma0_state)
256 & LCD_DMA_STATE_ACTIVE;
257 val1 = kmb_read_lcd(kmb, dma1_state)
258 & LCD_DMA_STATE_ACTIVE;
259 } while ((val || val1));
260
261 kmb_clr_bitmask_lcd(kmb,
262 LCD_LAYERn_DMA_CFG(kmb->layer_no),
263 LCD_DMA_LAYER_ENABLE);
264 kmb_write_lcd(kmb, LCD_FIFO_FLUSH, 1);
265 kmb->kmb_flush_done = 1;
266 kmb->kmb_under_flow = 0;
267 }
268 }
269
270 if (status & LCD_INT_LINE_CMP) {
271
272 kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_LINE_CMP);
273 }
274
275 if (status & LCD_INT_VERT_COMP) {
276
277 val = kmb_read_lcd(kmb, LCD_VSTATUS);
278 val = (val & LCD_VSTATUS_VERTICAL_STATUS_MASK);
279 switch (val) {
280 case LCD_VSTATUS_COMPARE_VSYNC:
281
282 kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_VERT_COMP);
283 if (kmb->kmb_flush_done) {
284 kmb_set_bitmask_lcd(kmb,
285 LCD_LAYERn_DMA_CFG
286 (kmb->layer_no),
287 LCD_DMA_LAYER_ENABLE);
288 kmb->kmb_flush_done = 0;
289 }
290 drm_crtc_handle_vblank(&kmb->crtc);
291 break;
292 case LCD_VSTATUS_COMPARE_BACKPORCH:
293 case LCD_VSTATUS_COMPARE_ACTIVE:
294 case LCD_VSTATUS_COMPARE_FRONT_PORCH:
295 kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_VERT_COMP);
296 break;
297 }
298 }
299 if (status & LCD_INT_DMA_ERR) {
300 val =
301 (status & LCD_INT_DMA_ERR &
302 kmb_read_lcd(kmb, LCD_INT_ENABLE));
303
304 if (val & (LAYER0_DMA_FIFO_UNDERFLOW |
305 LAYER0_DMA_CB_FIFO_UNDERFLOW |
306 LAYER0_DMA_CR_FIFO_UNDERFLOW)) {
307 kmb->kmb_under_flow++;
308 drm_info(&kmb->drm,
309 "!LAYER0:VL0 DMA UNDERFLOW val = 0x%lx,under_flow=%d",
310 val, kmb->kmb_under_flow);
311
312 kmb_clr_bitmask_lcd(kmb, LCD_INT_ENABLE,
313 LAYER0_DMA_FIFO_UNDERFLOW |
314 LAYER0_DMA_CB_FIFO_UNDERFLOW |
315 LAYER0_DMA_CR_FIFO_UNDERFLOW);
316 kmb_set_bitmask_lcd(kmb, LCD_INT_CLEAR,
317 LAYER0_DMA_CB_FIFO_UNDERFLOW |
318 LAYER0_DMA_FIFO_UNDERFLOW |
319 LAYER0_DMA_CR_FIFO_UNDERFLOW);
320
321 kmb_clr_bitmask_lcd(kmb, LCD_LAYERn_DMA_CFG(0),
322 LCD_DMA_LAYER_CONT_PING_PONG_UPDATE);
323
324 kmb->layer_no = 0;
325 }
326
327 if (val & LAYER0_DMA_FIFO_OVERFLOW)
328 drm_dbg(&kmb->drm,
329 "LAYER0:VL0 DMA OVERFLOW val = 0x%lx", val);
330 if (val & LAYER0_DMA_CB_FIFO_OVERFLOW)
331 drm_dbg(&kmb->drm,
332 "LAYER0:VL0 DMA CB OVERFLOW val = 0x%lx", val);
333 if (val & LAYER0_DMA_CR_FIFO_OVERFLOW)
334 drm_dbg(&kmb->drm,
335 "LAYER0:VL0 DMA CR OVERFLOW val = 0x%lx", val);
336
337
338 if (val & (LAYER1_DMA_FIFO_UNDERFLOW |
339 LAYER1_DMA_CB_FIFO_UNDERFLOW |
340 LAYER1_DMA_CR_FIFO_UNDERFLOW)) {
341 kmb->kmb_under_flow++;
342 drm_info(&kmb->drm,
343 "!LAYER1:VL1 DMA UNDERFLOW val = 0x%lx, under_flow=%d",
344 val, kmb->kmb_under_flow);
345
346 kmb_clr_bitmask_lcd(kmb, LCD_INT_ENABLE,
347 LAYER1_DMA_FIFO_UNDERFLOW |
348 LAYER1_DMA_CB_FIFO_UNDERFLOW |
349 LAYER1_DMA_CR_FIFO_UNDERFLOW);
350 kmb_set_bitmask_lcd(kmb, LCD_INT_CLEAR,
351 LAYER1_DMA_CB_FIFO_UNDERFLOW |
352 LAYER1_DMA_FIFO_UNDERFLOW |
353 LAYER1_DMA_CR_FIFO_UNDERFLOW);
354
355 kmb_clr_bitmask_lcd(kmb, LCD_LAYERn_DMA_CFG(1),
356 LCD_DMA_LAYER_CONT_PING_PONG_UPDATE);
357 kmb->layer_no = 1;
358 }
359
360
361 if (val & LAYER1_DMA_FIFO_OVERFLOW)
362 drm_dbg(&kmb->drm,
363 "LAYER1:VL1 DMA OVERFLOW val = 0x%lx", val);
364 if (val & LAYER1_DMA_CB_FIFO_OVERFLOW)
365 drm_dbg(&kmb->drm,
366 "LAYER1:VL1 DMA CB OVERFLOW val = 0x%lx", val);
367 if (val & LAYER1_DMA_CR_FIFO_OVERFLOW)
368 drm_dbg(&kmb->drm,
369 "LAYER1:VL1 DMA CR OVERFLOW val = 0x%lx", val);
370
371
372 if (val & LAYER2_DMA_FIFO_UNDERFLOW)
373 drm_dbg(&kmb->drm,
374 "LAYER2:GL0 DMA UNDERFLOW val = 0x%lx", val);
375 if (val & LAYER2_DMA_FIFO_OVERFLOW)
376 drm_dbg(&kmb->drm,
377 "LAYER2:GL0 DMA OVERFLOW val = 0x%lx", val);
378
379
380 if (val & LAYER3_DMA_FIFO_UNDERFLOW)
381 drm_dbg(&kmb->drm,
382 "LAYER3:GL1 DMA UNDERFLOW val = 0x%lx", val);
383 if (val & LAYER3_DMA_FIFO_OVERFLOW)
384 drm_dbg(&kmb->drm,
385 "LAYER3:GL1 DMA OVERFLOW val = 0x%lx", val);
386 }
387
388 spin_unlock(&kmb->irq_lock);
389
390 if (status & LCD_INT_LAYER) {
391
392 kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_LAYER);
393 }
394
395
396 kmb_set_bitmask_lcd(kmb, LCD_INT_CLEAR, 1);
397 return IRQ_HANDLED;
398}
399
400
401static irqreturn_t kmb_isr(int irq, void *arg)
402{
403 struct drm_device *dev = (struct drm_device *)arg;
404
405 handle_lcd_irq(dev);
406 return IRQ_HANDLED;
407}
408
409static void kmb_irq_reset(struct drm_device *drm)
410{
411 kmb_write_lcd(to_kmb(drm), LCD_INT_CLEAR, 0xFFFF);
412 kmb_write_lcd(to_kmb(drm), LCD_INT_ENABLE, 0);
413}
414
415static int kmb_irq_install(struct drm_device *drm, unsigned int irq)
416{
417 if (irq == IRQ_NOTCONNECTED)
418 return -ENOTCONN;
419
420 kmb_irq_reset(drm);
421
422 return request_irq(irq, kmb_isr, 0, drm->driver->name, drm);
423}
424
425static void kmb_irq_uninstall(struct drm_device *drm)
426{
427 struct kmb_drm_private *kmb = to_kmb(drm);
428
429 kmb_irq_reset(drm);
430 free_irq(kmb->irq_lcd, drm);
431}
432
433DEFINE_DRM_GEM_CMA_FOPS(fops);
434
435static const struct drm_driver kmb_driver = {
436 .driver_features = DRIVER_GEM |
437 DRIVER_MODESET | DRIVER_ATOMIC,
438
439 .fops = &fops,
440 DRM_GEM_CMA_DRIVER_OPS_VMAP,
441 .name = "kmb-drm",
442 .desc = "KEEMBAY DISPLAY DRIVER",
443 .date = DRIVER_DATE,
444 .major = DRIVER_MAJOR,
445 .minor = DRIVER_MINOR,
446};
447
448static int kmb_remove(struct platform_device *pdev)
449{
450 struct device *dev = &pdev->dev;
451 struct drm_device *drm = dev_get_drvdata(dev);
452 struct kmb_drm_private *kmb = to_kmb(drm);
453
454 drm_dev_unregister(drm);
455 drm_kms_helper_poll_fini(drm);
456 of_node_put(kmb->crtc.port);
457 kmb->crtc.port = NULL;
458 pm_runtime_get_sync(drm->dev);
459 kmb_irq_uninstall(drm);
460 pm_runtime_put_sync(drm->dev);
461 pm_runtime_disable(drm->dev);
462
463 of_reserved_mem_device_release(drm->dev);
464
465
466 kmb_display_clk_disable(kmb);
467
468 dev_set_drvdata(dev, NULL);
469
470
471 kmb_dsi_host_unregister(kmb->kmb_dsi);
472 drm_atomic_helper_shutdown(drm);
473 return 0;
474}
475
476static int kmb_probe(struct platform_device *pdev)
477{
478 struct device *dev = get_device(&pdev->dev);
479 struct kmb_drm_private *kmb;
480 int ret = 0;
481 struct device_node *dsi_in;
482 struct device_node *dsi_node;
483 struct platform_device *dsi_pdev;
484
485
486
487
488
489
490
491
492 dsi_in = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0);
493 if (!dsi_in) {
494 DRM_ERROR("Failed to get dsi_in node info from DT");
495 return -EINVAL;
496 }
497 dsi_node = of_graph_get_remote_port_parent(dsi_in);
498 if (!dsi_node) {
499 of_node_put(dsi_in);
500 DRM_ERROR("Failed to get dsi node from DT\n");
501 return -EINVAL;
502 }
503
504 dsi_pdev = of_find_device_by_node(dsi_node);
505 if (!dsi_pdev) {
506 of_node_put(dsi_in);
507 of_node_put(dsi_node);
508 DRM_ERROR("Failed to get dsi platform device\n");
509 return -EINVAL;
510 }
511
512 of_node_put(dsi_in);
513 of_node_put(dsi_node);
514 ret = kmb_dsi_host_bridge_init(get_device(&dsi_pdev->dev));
515
516 if (ret == -EPROBE_DEFER) {
517 return -EPROBE_DEFER;
518 } else if (ret) {
519 DRM_ERROR("probe failed to initialize DSI host bridge\n");
520 return ret;
521 }
522
523
524 kmb = devm_drm_dev_alloc(dev, &kmb_driver,
525 struct kmb_drm_private, drm);
526 if (IS_ERR(kmb))
527 return PTR_ERR(kmb);
528
529 dev_set_drvdata(dev, &kmb->drm);
530
531
532 kmb->kmb_dsi = kmb_dsi_init(dsi_pdev);
533 if (IS_ERR(kmb->kmb_dsi)) {
534 drm_err(&kmb->drm, "failed to initialize DSI\n");
535 ret = PTR_ERR(kmb->kmb_dsi);
536 goto err_free1;
537 }
538
539 kmb->kmb_dsi->dev = &dsi_pdev->dev;
540 kmb->kmb_dsi->pdev = dsi_pdev;
541 ret = kmb_hw_init(&kmb->drm, 0);
542 if (ret)
543 goto err_free1;
544
545 ret = kmb_setup_mode_config(&kmb->drm);
546 if (ret)
547 goto err_free;
548
549 ret = kmb_irq_install(&kmb->drm, kmb->irq_lcd);
550 if (ret < 0) {
551 drm_err(&kmb->drm, "failed to install IRQ handler\n");
552 goto err_irq;
553 }
554
555 drm_kms_helper_poll_init(&kmb->drm);
556
557
558 ret = drm_dev_register(&kmb->drm, 0);
559 if (ret)
560 goto err_register;
561
562 return 0;
563
564 err_register:
565 drm_kms_helper_poll_fini(&kmb->drm);
566 err_irq:
567 pm_runtime_disable(kmb->drm.dev);
568 err_free:
569 drm_crtc_cleanup(&kmb->crtc);
570 drm_mode_config_cleanup(&kmb->drm);
571 err_free1:
572 dev_set_drvdata(dev, NULL);
573 kmb_dsi_host_unregister(kmb->kmb_dsi);
574
575 return ret;
576}
577
578static const struct of_device_id kmb_of_match[] = {
579 {.compatible = "intel,keembay-display"},
580 {},
581};
582
583MODULE_DEVICE_TABLE(of, kmb_of_match);
584
585static int __maybe_unused kmb_pm_suspend(struct device *dev)
586{
587 struct drm_device *drm = dev_get_drvdata(dev);
588 struct kmb_drm_private *kmb = to_kmb(drm);
589
590 drm_kms_helper_poll_disable(drm);
591
592 kmb->state = drm_atomic_helper_suspend(drm);
593 if (IS_ERR(kmb->state)) {
594 drm_kms_helper_poll_enable(drm);
595 return PTR_ERR(kmb->state);
596 }
597
598 return 0;
599}
600
601static int __maybe_unused kmb_pm_resume(struct device *dev)
602{
603 struct drm_device *drm = dev_get_drvdata(dev);
604 struct kmb_drm_private *kmb = drm ? to_kmb(drm) : NULL;
605
606 if (!kmb)
607 return 0;
608
609 drm_atomic_helper_resume(drm, kmb->state);
610 drm_kms_helper_poll_enable(drm);
611
612 return 0;
613}
614
615static SIMPLE_DEV_PM_OPS(kmb_pm_ops, kmb_pm_suspend, kmb_pm_resume);
616
617static struct platform_driver kmb_platform_driver = {
618 .probe = kmb_probe,
619 .remove = kmb_remove,
620 .driver = {
621 .name = "kmb-drm",
622 .pm = &kmb_pm_ops,
623 .of_match_table = kmb_of_match,
624 },
625};
626
627module_platform_driver(kmb_platform_driver);
628
629MODULE_AUTHOR("Intel Corporation");
630MODULE_DESCRIPTION("Keembay Display driver");
631MODULE_LICENSE("GPL v2");
632
