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6#ifndef __KMB_DSI_H__
7#define __KMB_DSI_H__
8
9#include <drm/drm_encoder.h>
10#include <drm/drm_mipi_dsi.h>
11
12
13#define MIPI_TX_LANE_DATA_RATE_MBPS 891
14#define MIPI_TX_REF_CLK_KHZ 24000
15#define MIPI_TX_CFG_CLK_KHZ 24000
16#define MIPI_TX_BPP 24
17
18
19#define TEST_CODE_FSM_CONTROL 0x03
20#define TEST_CODE_MULTIPLE_PHY_CTRL 0x0C
21#define TEST_CODE_PLL_PROPORTIONAL_CHARGE_PUMP_CTRL 0x0E
22#define TEST_CODE_PLL_INTEGRAL_CHARGE_PUMP_CTRL 0x0F
23#define TEST_CODE_PLL_VCO_CTRL 0x12
24#define TEST_CODE_PLL_GMP_CTRL 0x13
25#define TEST_CODE_PLL_PHASE_ERR_CTRL 0x14
26#define TEST_CODE_PLL_LOCK_FILTER 0x15
27#define TEST_CODE_PLL_UNLOCK_FILTER 0x16
28#define TEST_CODE_PLL_INPUT_DIVIDER 0x17
29#define TEST_CODE_PLL_FEEDBACK_DIVIDER 0x18
30#define PLL_FEEDBACK_DIVIDER_HIGH BIT(7)
31#define TEST_CODE_PLL_OUTPUT_CLK_SEL 0x19
32#define PLL_N_OVR_EN BIT(4)
33#define PLL_M_OVR_EN BIT(5)
34#define TEST_CODE_VOD_LEVEL 0x24
35#define TEST_CODE_PLL_CHARGE_PUMP_BIAS 0x1C
36#define TEST_CODE_PLL_LOCK_DETECTOR 0x1D
37#define TEST_CODE_HS_FREQ_RANGE_CFG 0x44
38#define TEST_CODE_PLL_ANALOG_PROG 0x1F
39#define TEST_CODE_SLEW_RATE_OVERRIDE_CTRL 0xA0
40#define TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL 0xA3
41#define TEST_CODE_SLEW_RATE_DDL_CYCLES 0xA4
42
43
44#define PLL_N_MIN 0
45#define PLL_N_MAX 15
46#define PLL_M_MIN 62
47#define PLL_M_MAX 623
48#define PLL_FVCO_MAX 1250
49
50#define TIMEOUT 600
51
52#define MIPI_TX_FRAME_GEN 4
53#define MIPI_TX_FRAME_GEN_SECTIONS 4
54#define MIPI_CTRL_VIRTUAL_CHANNELS 4
55#define MIPI_D_LANES_PER_DPHY 2
56#define MIPI_CTRL_2LANE_MAX_MC_FIFO_LOC 255
57#define MIPI_CTRL_4LANE_MAX_MC_FIFO_LOC 511
58
59#define MIPI_DPHY_D_LANES 2
60#define MIPI_DPHY_DEFAULT_BIT_RATES 63
61
62#define KMB_MIPI_DEFAULT_CLK 24000000
63#define KMB_MIPI_DEFAULT_CFG_CLK 24000000
64
65#define to_kmb_dsi(x) container_of(x, struct kmb_dsi, base)
66
67struct kmb_dsi {
68 struct drm_encoder base;
69 struct device *dev;
70 struct platform_device *pdev;
71 struct mipi_dsi_host *host;
72 struct mipi_dsi_device *device;
73 struct drm_bridge *adv_bridge;
74 void __iomem *mipi_mmio;
75 struct clk *clk_mipi;
76 struct clk *clk_mipi_ecfg;
77 struct clk *clk_mipi_cfg;
78 int sys_clk_mhz;
79};
80
81
82
83enum mipi_ctrl_num {
84 MIPI_CTRL0 = 0,
85 MIPI_CTRL1,
86 MIPI_CTRL2,
87 MIPI_CTRL3,
88 MIPI_CTRL4,
89 MIPI_CTRL5,
90 MIPI_CTRL6,
91 MIPI_CTRL7,
92 MIPI_CTRL8,
93 MIPI_CTRL9,
94 MIPI_CTRL_NA
95};
96
97enum mipi_dphy_num {
98 MIPI_DPHY0 = 0,
99 MIPI_DPHY1,
100 MIPI_DPHY2,
101 MIPI_DPHY3,
102 MIPI_DPHY4,
103 MIPI_DPHY5,
104 MIPI_DPHY6,
105 MIPI_DPHY7,
106 MIPI_DPHY8,
107 MIPI_DPHY9,
108 MIPI_DPHY_NA
109};
110
111enum mipi_dir {
112 MIPI_RX,
113 MIPI_TX
114};
115
116enum mipi_ctrl_type {
117 MIPI_DSI,
118 MIPI_CSI
119};
120
121enum mipi_data_if {
122 MIPI_IF_DMA,
123 MIPI_IF_PARALLEL
124};
125
126enum mipi_data_mode {
127 MIPI_DATA_MODE0,
128 MIPI_DATA_MODE1,
129 MIPI_DATA_MODE2,
130 MIPI_DATA_MODE3
131};
132
133enum mipi_dsi_video_mode {
134 DSI_VIDEO_MODE_NO_BURST_PULSE,
135 DSI_VIDEO_MODE_NO_BURST_EVENT,
136 DSI_VIDEO_MODE_BURST
137};
138
139enum mipi_dsi_blanking_mode {
140 TRANSITION_TO_LOW_POWER,
141 SEND_BLANK_PACKET
142};
143
144enum mipi_dsi_eotp {
145 DSI_EOTP_DISABLED,
146 DSI_EOTP_ENABLES
147};
148
149enum mipi_dsi_data_type {
150 DSI_SP_DT_RESERVED_00 = 0x00,
151 DSI_SP_DT_VSYNC_START = 0x01,
152 DSI_SP_DT_COLOR_MODE_OFF = 0x02,
153 DSI_SP_DT_GENERIC_SHORT_WR = 0x03,
154 DSI_SP_DT_GENERIC_RD = 0x04,
155 DSI_SP_DT_DCS_SHORT_WR = 0x05,
156 DSI_SP_DT_DCS_RD = 0x06,
157 DSI_SP_DT_EOTP = 0x08,
158 DSI_LP_DT_NULL = 0x09,
159 DSI_LP_DT_RESERVED_0A = 0x0a,
160 DSI_LP_DT_RESERVED_0B = 0x0b,
161 DSI_LP_DT_LPPS_YCBCR422_20B = 0x0c,
162 DSI_LP_DT_PPS_RGB101010_30B = 0x0d,
163 DSI_LP_DT_PPS_RGB565_16B = 0x0e,
164 DSI_LP_DT_RESERVED_0F = 0x0f,
165
166 DSI_SP_DT_RESERVED_10 = 0x10,
167 DSI_SP_DT_VSYNC_END = 0x11,
168 DSI_SP_DT_COLOR_MODE_ON = 0x12,
169 DSI_SP_DT_GENERIC_SHORT_WR_1PAR = 0x13,
170 DSI_SP_DT_GENERIC_RD_1PAR = 0x14,
171 DSI_SP_DT_DCS_SHORT_WR_1PAR = 0x15,
172 DSI_SP_DT_RESERVED_16 = 0x16,
173 DSI_SP_DT_RESERVED_17 = 0x17,
174 DSI_SP_DT_RESERVED_18 = 0x18,
175 DSI_LP_DT_BLANK = 0x19,
176 DSI_LP_DT_RESERVED_1A = 0x1a,
177 DSI_LP_DT_RESERVED_1B = 0x1b,
178 DSI_LP_DT_PPS_YCBCR422_24B = 0x1c,
179 DSI_LP_DT_PPS_RGB121212_36B = 0x1d,
180 DSI_LP_DT_PPS_RGB666_18B = 0x1e,
181 DSI_LP_DT_RESERVED_1F = 0x1f,
182
183 DSI_SP_DT_RESERVED_20 = 0x20,
184 DSI_SP_DT_HSYNC_START = 0x21,
185 DSI_SP_DT_SHUT_DOWN_PERIPH_CMD = 0x22,
186 DSI_SP_DT_GENERIC_SHORT_WR_2PAR = 0x23,
187 DSI_SP_DT_GENERIC_RD_2PAR = 0x24,
188 DSI_SP_DT_RESERVED_25 = 0x25,
189 DSI_SP_DT_RESERVED_26 = 0x26,
190 DSI_SP_DT_RESERVED_27 = 0x27,
191 DSI_SP_DT_RESERVED_28 = 0x28,
192 DSI_LP_DT_GENERIC_LONG_WR = 0x29,
193 DSI_LP_DT_RESERVED_2A = 0x2a,
194 DSI_LP_DT_RESERVED_2B = 0x2b,
195 DSI_LP_DT_PPS_YCBCR422_16B = 0x2c,
196 DSI_LP_DT_RESERVED_2D = 0x2d,
197 DSI_LP_DT_LPPS_RGB666_18B = 0x2e,
198 DSI_LP_DT_RESERVED_2F = 0x2f,
199
200 DSI_SP_DT_RESERVED_30 = 0x30,
201 DSI_SP_DT_HSYNC_END = 0x31,
202 DSI_SP_DT_TURN_ON_PERIPH_CMD = 0x32,
203 DSI_SP_DT_RESERVED_33 = 0x33,
204 DSI_SP_DT_RESERVED_34 = 0x34,
205 DSI_SP_DT_RESERVED_35 = 0x35,
206 DSI_SP_DT_RESERVED_36 = 0x36,
207 DSI_SP_DT_SET_MAX_RETURN_PKT_SIZE = 0x37,
208 DSI_SP_DT_RESERVED_38 = 0x38,
209 DSI_LP_DT_DSC_LONG_WR = 0x39,
210 DSI_LP_DT_RESERVED_3A = 0x3a,
211 DSI_LP_DT_RESERVED_3B = 0x3b,
212 DSI_LP_DT_RESERVED_3C = 0x3c,
213 DSI_LP_DT_PPS_YCBCR420_12B = 0x3d,
214 DSI_LP_DT_PPS_RGB888_24B = 0x3e,
215 DSI_LP_DT_RESERVED_3F = 0x3f
216};
217
218enum mipi_tx_hs_tp_sel {
219 MIPI_TX_HS_TP_WHOLE_FRAME_COLOR0 = 0,
220 MIPI_TX_HS_TP_WHOLE_FRAME_COLOR1,
221 MIPI_TX_HS_TP_V_STRIPES,
222 MIPI_TX_HS_TP_H_STRIPES,
223};
224
225enum dphy_mode {
226 MIPI_DPHY_SLAVE = 0,
227 MIPI_DPHY_MASTER
228};
229
230enum dphy_tx_fsm {
231 DPHY_TX_POWERDWN = 0,
232 DPHY_TX_BGPON,
233 DPHY_TX_TERMCAL,
234 DPHY_TX_TERMCALUP,
235 DPHY_TX_OFFSETCAL,
236 DPHY_TX_LOCK,
237 DPHY_TX_SRCAL,
238 DPHY_TX_IDLE,
239 DPHY_TX_ULP,
240 DPHY_TX_LANESTART,
241 DPHY_TX_CLKALIGN,
242 DPHY_TX_DDLTUNNING,
243 DPHY_TX_ULP_FORCE_PLL,
244 DPHY_TX_LOCK_LOSS
245};
246
247struct mipi_data_type_params {
248 u8 size_constraint_pixels;
249 u8 size_constraint_bytes;
250 u8 pixels_per_pclk;
251 u8 bits_per_pclk;
252};
253
254struct mipi_tx_dsi_cfg {
255 u8 hfp_blank_en;
256 u8 eotp_en;
257
258 u8 lpm_last_vfp_line;
259
260 u8 lpm_first_vsa_line;
261 u8 sync_pulse_eventn;
262 u8 hfp_blanking;
263 u8 hbp_blanking;
264 u8 hsa_blanking;
265 u8 v_blanking;
266};
267
268struct mipi_tx_frame_section_cfg {
269 u32 dma_v_stride;
270 u16 dma_v_scale_cfg;
271 u16 width_pixels;
272 u16 height_lines;
273 u8 dma_packed;
274 u8 bpp;
275 u8 bpp_unpacked;
276 u8 dma_h_stride;
277 u8 data_type;
278 u8 data_mode;
279 u8 dma_flip_rotate_sel;
280};
281
282struct mipi_tx_frame_timing_cfg {
283 u32 bpp;
284 u32 lane_rate_mbps;
285 u32 hsync_width;
286 u32 h_backporch;
287 u32 h_frontporch;
288 u32 h_active;
289 u16 vsync_width;
290 u16 v_backporch;
291 u16 v_frontporch;
292 u16 v_active;
293 u8 active_lanes;
294};
295
296struct mipi_tx_frame_sect_phcfg {
297 u32 wc;
298 enum mipi_data_mode data_mode;
299 enum mipi_dsi_data_type data_type;
300 u8 vchannel;
301 u8 dma_packed;
302};
303
304struct mipi_tx_frame_cfg {
305 struct mipi_tx_frame_section_cfg *sections[MIPI_TX_FRAME_GEN_SECTIONS];
306 u32 hsync_width;
307 u32 h_backporch;
308 u32 h_frontporch;
309 u16 vsync_width;
310 u16 v_backporch;
311 u16 v_frontporch;
312};
313
314struct mipi_tx_ctrl_cfg {
315 struct mipi_tx_frame_cfg *frames[MIPI_TX_FRAME_GEN];
316 const struct mipi_tx_dsi_cfg *tx_dsi_cfg;
317 u8 line_sync_pkt_en;
318 u8 line_counter_active;
319 u8 frame_counter_active;
320 u8 tx_hsclkkidle_cnt;
321 u8 tx_hsexit_cnt;
322 u8 tx_crc_en;
323 u8 tx_hact_wait_stop;
324 u8 tx_always_use_hact;
325 u8 tx_wait_trig;
326 u8 tx_wait_all_sect;
327};
328
329
330struct mipi_ctrl_cfg {
331 u8 active_lanes;
332 u32 lane_rate_mbps;
333 u32 ref_clk_khz;
334 u32 cfg_clk_khz;
335 struct mipi_tx_ctrl_cfg tx_ctrl_cfg;
336};
337
338static inline void kmb_write_mipi(struct kmb_dsi *kmb_dsi,
339 unsigned int reg, u32 value)
340{
341 writel(value, (kmb_dsi->mipi_mmio + reg));
342}
343
344static inline u32 kmb_read_mipi(struct kmb_dsi *kmb_dsi, unsigned int reg)
345{
346 return readl(kmb_dsi->mipi_mmio + reg);
347}
348
349static inline void kmb_write_bits_mipi(struct kmb_dsi *kmb_dsi,
350 unsigned int reg, u32 offset,
351 u32 num_bits, u32 value)
352{
353 u32 reg_val = kmb_read_mipi(kmb_dsi, reg);
354 u32 mask = (1 << num_bits) - 1;
355
356 value &= mask;
357 mask <<= offset;
358 reg_val &= (~mask);
359 reg_val |= (value << offset);
360 kmb_write_mipi(kmb_dsi, reg, reg_val);
361}
362
363static inline void kmb_set_bit_mipi(struct kmb_dsi *kmb_dsi,
364 unsigned int reg, u32 offset)
365{
366 u32 reg_val = kmb_read_mipi(kmb_dsi, reg);
367
368 kmb_write_mipi(kmb_dsi, reg, reg_val | (1 << offset));
369}
370
371static inline void kmb_clr_bit_mipi(struct kmb_dsi *kmb_dsi,
372 unsigned int reg, u32 offset)
373{
374 u32 reg_val = kmb_read_mipi(kmb_dsi, reg);
375
376 kmb_write_mipi(kmb_dsi, reg, reg_val & (~(1 << offset)));
377}
378
379int kmb_dsi_host_bridge_init(struct device *dev);
380struct kmb_dsi *kmb_dsi_init(struct platform_device *pdev);
381void kmb_dsi_host_unregister(struct kmb_dsi *kmb_dsi);
382int kmb_dsi_mode_set(struct kmb_dsi *kmb_dsi, struct drm_display_mode *mode,
383 int sys_clk_mhz, struct drm_atomic_state *old_state);
384int kmb_dsi_map_mmio(struct kmb_dsi *kmb_dsi);
385int kmb_dsi_clk_init(struct kmb_dsi *kmb_dsi);
386int kmb_dsi_encoder_init(struct drm_device *dev, struct kmb_dsi *kmb_dsi);
387#endif
388
