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5
6#include <linux/clk.h>
7#include <linux/component.h>
8#include <linux/module.h>
9#include <linux/of_device.h>
10#include <linux/of_irq.h>
11#include <linux/platform_device.h>
12#include <linux/soc/mediatek/mtk-cmdq.h>
13
14#include "mtk_disp_drv.h"
15#include "mtk_drm_crtc.h"
16#include "mtk_drm_ddp_comp.h"
17
18#define DISP_CCORR_EN 0x0000
19#define CCORR_EN BIT(0)
20#define DISP_CCORR_CFG 0x0020
21#define CCORR_RELAY_MODE BIT(0)
22#define CCORR_ENGINE_EN BIT(1)
23#define CCORR_GAMMA_OFF BIT(2)
24#define CCORR_WGAMUT_SRC_CLIP BIT(3)
25#define DISP_CCORR_SIZE 0x0030
26#define DISP_CCORR_COEF_0 0x0080
27#define DISP_CCORR_COEF_1 0x0084
28#define DISP_CCORR_COEF_2 0x0088
29#define DISP_CCORR_COEF_3 0x008C
30#define DISP_CCORR_COEF_4 0x0090
31
32struct mtk_disp_ccorr_data {
33 u32 matrix_bits;
34};
35
36
37
38
39
40
41struct mtk_disp_ccorr {
42 struct clk *clk;
43 void __iomem *regs;
44 struct cmdq_client_reg cmdq_reg;
45 const struct mtk_disp_ccorr_data *data;
46};
47
48int mtk_ccorr_clk_enable(struct device *dev)
49{
50 struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
51
52 return clk_prepare_enable(ccorr->clk);
53}
54
55void mtk_ccorr_clk_disable(struct device *dev)
56{
57 struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
58
59 clk_disable_unprepare(ccorr->clk);
60}
61
62void mtk_ccorr_config(struct device *dev, unsigned int w,
63 unsigned int h, unsigned int vrefresh,
64 unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
65{
66 struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
67
68 mtk_ddp_write(cmdq_pkt, w << 16 | h, &ccorr->cmdq_reg, ccorr->regs,
69 DISP_CCORR_SIZE);
70 mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs,
71 DISP_CCORR_CFG);
72}
73
74void mtk_ccorr_start(struct device *dev)
75{
76 struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
77
78 writel(CCORR_EN, ccorr->regs + DISP_CCORR_EN);
79}
80
81void mtk_ccorr_stop(struct device *dev)
82{
83 struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
84
85 writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN);
86}
87
88
89static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n)
90{
91 u16 r;
92
93
94 r = in & BIT_ULL(63) ? BIT(n + 1) : 0;
95
96 if ((in & GENMASK_ULL(62, 33)) > 0) {
97
98
99
100 r |= GENMASK(n, 0);
101 } else {
102
103 r |= (in >> (32 - n)) & GENMASK(n, 0);
104 }
105
106 return r;
107}
108
109void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state)
110{
111 struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
112 struct drm_property_blob *blob = state->ctm;
113 struct drm_color_ctm *ctm;
114 const u64 *input;
115 uint16_t coeffs[9] = { 0 };
116 int i;
117 struct cmdq_pkt *cmdq_pkt = NULL;
118 u32 matrix_bits = ccorr->data->matrix_bits;
119
120 if (!blob)
121 return;
122
123 ctm = (struct drm_color_ctm *)blob->data;
124 input = ctm->matrix;
125
126 for (i = 0; i < ARRAY_SIZE(coeffs); i++)
127 coeffs[i] = mtk_ctm_s31_32_to_s1_n(input[i], matrix_bits);
128
129 mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
130 &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0);
131 mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
132 &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_1);
133 mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
134 &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_2);
135 mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
136 &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_3);
137 mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
138 &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_4);
139}
140
141static int mtk_disp_ccorr_bind(struct device *dev, struct device *master,
142 void *data)
143{
144 return 0;
145}
146
147static void mtk_disp_ccorr_unbind(struct device *dev, struct device *master,
148 void *data)
149{
150}
151
152static const struct component_ops mtk_disp_ccorr_component_ops = {
153 .bind = mtk_disp_ccorr_bind,
154 .unbind = mtk_disp_ccorr_unbind,
155};
156
157static int mtk_disp_ccorr_probe(struct platform_device *pdev)
158{
159 struct device *dev = &pdev->dev;
160 struct mtk_disp_ccorr *priv;
161 struct resource *res;
162 int ret;
163
164 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
165 if (!priv)
166 return -ENOMEM;
167
168 priv->clk = devm_clk_get(dev, NULL);
169 if (IS_ERR(priv->clk)) {
170 dev_err(dev, "failed to get ccorr clk\n");
171 return PTR_ERR(priv->clk);
172 }
173
174 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
175 priv->regs = devm_ioremap_resource(dev, res);
176 if (IS_ERR(priv->regs)) {
177 dev_err(dev, "failed to ioremap ccorr\n");
178 return PTR_ERR(priv->regs);
179 }
180
181#if IS_REACHABLE(CONFIG_MTK_CMDQ)
182 ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
183 if (ret)
184 dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
185#endif
186
187 priv->data = of_device_get_match_data(dev);
188 platform_set_drvdata(pdev, priv);
189
190 ret = component_add(dev, &mtk_disp_ccorr_component_ops);
191 if (ret)
192 dev_err(dev, "Failed to add component: %d\n", ret);
193
194 return ret;
195}
196
197static int mtk_disp_ccorr_remove(struct platform_device *pdev)
198{
199 component_del(&pdev->dev, &mtk_disp_ccorr_component_ops);
200
201 return 0;
202}
203
204static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = {
205 .matrix_bits = 10,
206};
207
208static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = {
209 { .compatible = "mediatek,mt8183-disp-ccorr",
210 .data = &mt8183_ccorr_driver_data},
211 {},
212};
213MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match);
214
215struct platform_driver mtk_disp_ccorr_driver = {
216 .probe = mtk_disp_ccorr_probe,
217 .remove = mtk_disp_ccorr_remove,
218 .driver = {
219 .name = "mediatek-disp-ccorr",
220 .owner = THIS_MODULE,
221 .of_match_table = mtk_disp_ccorr_driver_dt_match,
222 },
223};
224
