linux/drivers/gpu/drm/mediatek/mtk_dsi.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2015 MediaTek Inc.
   4 */
   5
   6#include <linux/clk.h>
   7#include <linux/component.h>
   8#include <linux/iopoll.h>
   9#include <linux/irq.h>
  10#include <linux/of.h>
  11#include <linux/of_platform.h>
  12#include <linux/phy/phy.h>
  13#include <linux/platform_device.h>
  14
  15#include <video/mipi_display.h>
  16#include <video/videomode.h>
  17
  18#include <drm/drm_atomic_helper.h>
  19#include <drm/drm_mipi_dsi.h>
  20#include <drm/drm_of.h>
  21#include <drm/drm_panel.h>
  22#include <drm/drm_print.h>
  23#include <drm/drm_probe_helper.h>
  24
  25#include "mtk_drm_ddp_comp.h"
  26
  27#define DSI_START               0x00
  28
  29#define DSI_INTEN               0x08
  30
  31#define DSI_INTSTA              0x0c
  32#define LPRX_RD_RDY_INT_FLAG            BIT(0)
  33#define CMD_DONE_INT_FLAG               BIT(1)
  34#define TE_RDY_INT_FLAG                 BIT(2)
  35#define VM_DONE_INT_FLAG                BIT(3)
  36#define EXT_TE_RDY_INT_FLAG             BIT(4)
  37#define DSI_BUSY                        BIT(31)
  38
  39#define DSI_CON_CTRL            0x10
  40#define DSI_RESET                       BIT(0)
  41#define DSI_EN                          BIT(1)
  42
  43#define DSI_MODE_CTRL           0x14
  44#define MODE                            (3)
  45#define CMD_MODE                        0
  46#define SYNC_PULSE_MODE                 1
  47#define SYNC_EVENT_MODE                 2
  48#define BURST_MODE                      3
  49#define FRM_MODE                        BIT(16)
  50#define MIX_MODE                        BIT(17)
  51
  52#define DSI_TXRX_CTRL           0x18
  53#define VC_NUM                          BIT(1)
  54#define LANE_NUM                        (0xf << 2)
  55#define DIS_EOT                         BIT(6)
  56#define NULL_EN                         BIT(7)
  57#define TE_FREERUN                      BIT(8)
  58#define EXT_TE_EN                       BIT(9)
  59#define EXT_TE_EDGE                     BIT(10)
  60#define MAX_RTN_SIZE                    (0xf << 12)
  61#define HSTX_CKLP_EN                    BIT(16)
  62
  63#define DSI_PSCTRL              0x1c
  64#define DSI_PS_WC                       0x3fff
  65#define DSI_PS_SEL                      (3 << 16)
  66#define PACKED_PS_16BIT_RGB565          (0 << 16)
  67#define LOOSELY_PS_18BIT_RGB666         (1 << 16)
  68#define PACKED_PS_18BIT_RGB666          (2 << 16)
  69#define PACKED_PS_24BIT_RGB888          (3 << 16)
  70
  71#define DSI_VSA_NL              0x20
  72#define DSI_VBP_NL              0x24
  73#define DSI_VFP_NL              0x28
  74#define DSI_VACT_NL             0x2C
  75#define DSI_HSA_WC              0x50
  76#define DSI_HBP_WC              0x54
  77#define DSI_HFP_WC              0x58
  78
  79#define DSI_CMDQ_SIZE           0x60
  80#define CMDQ_SIZE                       0x3f
  81
  82#define DSI_HSTX_CKL_WC         0x64
  83
  84#define DSI_RX_DATA0            0x74
  85#define DSI_RX_DATA1            0x78
  86#define DSI_RX_DATA2            0x7c
  87#define DSI_RX_DATA3            0x80
  88
  89#define DSI_RACK                0x84
  90#define RACK                            BIT(0)
  91
  92#define DSI_PHY_LCCON           0x104
  93#define LC_HS_TX_EN                     BIT(0)
  94#define LC_ULPM_EN                      BIT(1)
  95#define LC_WAKEUP_EN                    BIT(2)
  96
  97#define DSI_PHY_LD0CON          0x108
  98#define LD0_HS_TX_EN                    BIT(0)
  99#define LD0_ULPM_EN                     BIT(1)
 100#define LD0_WAKEUP_EN                   BIT(2)
 101
 102#define DSI_PHY_TIMECON0        0x110
 103#define LPX                             (0xff << 0)
 104#define HS_PREP                         (0xff << 8)
 105#define HS_ZERO                         (0xff << 16)
 106#define HS_TRAIL                        (0xff << 24)
 107
 108#define DSI_PHY_TIMECON1        0x114
 109#define TA_GO                           (0xff << 0)
 110#define TA_SURE                         (0xff << 8)
 111#define TA_GET                          (0xff << 16)
 112#define DA_HS_EXIT                      (0xff << 24)
 113
 114#define DSI_PHY_TIMECON2        0x118
 115#define CONT_DET                        (0xff << 0)
 116#define CLK_ZERO                        (0xff << 16)
 117#define CLK_TRAIL                       (0xff << 24)
 118
 119#define DSI_PHY_TIMECON3        0x11c
 120#define CLK_HS_PREP                     (0xff << 0)
 121#define CLK_HS_POST                     (0xff << 8)
 122#define CLK_HS_EXIT                     (0xff << 16)
 123
 124#define DSI_VM_CMD_CON          0x130
 125#define VM_CMD_EN                       BIT(0)
 126#define TS_VFP_EN                       BIT(5)
 127
 128#define DSI_CMDQ0               0x180
 129#define CONFIG                          (0xff << 0)
 130#define SHORT_PACKET                    0
 131#define LONG_PACKET                     2
 132#define BTA                             BIT(2)
 133#define DATA_ID                         (0xff << 8)
 134#define DATA_0                          (0xff << 16)
 135#define DATA_1                          (0xff << 24)
 136
 137#define T_LPX           5
 138#define T_HS_PREP       6
 139#define T_HS_TRAIL      8
 140#define T_HS_EXIT       7
 141#define T_HS_ZERO       10
 142
 143#define NS_TO_CYCLE(n, c)    ((n) / (c) + (((n) % (c)) ? 1 : 0))
 144
 145#define MTK_DSI_HOST_IS_READ(type) \
 146        ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
 147        (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
 148        (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
 149        (type == MIPI_DSI_DCS_READ))
 150
 151struct phy;
 152
 153struct mtk_dsi {
 154        struct mtk_ddp_comp ddp_comp;
 155        struct device *dev;
 156        struct mipi_dsi_host host;
 157        struct drm_encoder encoder;
 158        struct drm_connector conn;
 159        struct drm_panel *panel;
 160        struct drm_bridge *bridge;
 161        struct phy *phy;
 162
 163        void __iomem *regs;
 164
 165        struct clk *engine_clk;
 166        struct clk *digital_clk;
 167        struct clk *hs_clk;
 168
 169        u32 data_rate;
 170
 171        unsigned long mode_flags;
 172        enum mipi_dsi_pixel_format format;
 173        unsigned int lanes;
 174        struct videomode vm;
 175        int refcount;
 176        bool enabled;
 177        u32 irq_data;
 178        wait_queue_head_t irq_wait_queue;
 179};
 180
 181static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e)
 182{
 183        return container_of(e, struct mtk_dsi, encoder);
 184}
 185
 186static inline struct mtk_dsi *connector_to_dsi(struct drm_connector *c)
 187{
 188        return container_of(c, struct mtk_dsi, conn);
 189}
 190
 191static inline struct mtk_dsi *host_to_dsi(struct mipi_dsi_host *h)
 192{
 193        return container_of(h, struct mtk_dsi, host);
 194}
 195
 196static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data)
 197{
 198        u32 temp = readl(dsi->regs + offset);
 199
 200        writel((temp & ~mask) | (data & mask), dsi->regs + offset);
 201}
 202
 203static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
 204{
 205        u32 timcon0, timcon1, timcon2, timcon3;
 206        u32 ui, cycle_time;
 207
 208        ui = 1000 / dsi->data_rate + 0x01;
 209        cycle_time = 8000 / dsi->data_rate + 0x01;
 210
 211        timcon0 = T_LPX | T_HS_PREP << 8 | T_HS_ZERO << 16 | T_HS_TRAIL << 24;
 212        timcon1 = 4 * T_LPX | (3 * T_LPX / 2) << 8 | 5 * T_LPX << 16 |
 213                  T_HS_EXIT << 24;
 214        timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
 215                  (NS_TO_CYCLE(0x150, cycle_time) << 16);
 216        timcon3 = NS_TO_CYCLE(0x40, cycle_time) | (2 * T_LPX) << 16 |
 217                  NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8;
 218
 219        writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
 220        writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
 221        writel(timcon2, dsi->regs + DSI_PHY_TIMECON2);
 222        writel(timcon3, dsi->regs + DSI_PHY_TIMECON3);
 223}
 224
 225static void mtk_dsi_enable(struct mtk_dsi *dsi)
 226{
 227        mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, DSI_EN);
 228}
 229
 230static void mtk_dsi_disable(struct mtk_dsi *dsi)
 231{
 232        mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0);
 233}
 234
 235static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
 236{
 237        mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);
 238        mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
 239}
 240
 241static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
 242{
 243        mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
 244        mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
 245}
 246
 247static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi)
 248{
 249        mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
 250        mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN);
 251        mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0);
 252}
 253
 254static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi)
 255{
 256        mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0);
 257        mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
 258}
 259
 260static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)
 261{
 262        mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
 263        mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN);
 264        mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0);
 265}
 266
 267static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi)
 268{
 269        u32 tmp_reg1;
 270
 271        tmp_reg1 = readl(dsi->regs + DSI_PHY_LCCON);
 272        return ((tmp_reg1 & LC_HS_TX_EN) == 1) ? true : false;
 273}
 274
 275static void mtk_dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter)
 276{
 277        if (enter && !mtk_dsi_clk_hs_state(dsi))
 278                mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN);
 279        else if (!enter && mtk_dsi_clk_hs_state(dsi))
 280                mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
 281}
 282
 283static void mtk_dsi_set_mode(struct mtk_dsi *dsi)
 284{
 285        u32 vid_mode = CMD_MODE;
 286
 287        if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
 288                if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
 289                        vid_mode = BURST_MODE;
 290                else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
 291                        vid_mode = SYNC_PULSE_MODE;
 292                else
 293                        vid_mode = SYNC_EVENT_MODE;
 294        }
 295
 296        writel(vid_mode, dsi->regs + DSI_MODE_CTRL);
 297}
 298
 299static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi)
 300{
 301        mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN);
 302        mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN);
 303}
 304
 305static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi)
 306{
 307        struct videomode *vm = &dsi->vm;
 308        u32 dsi_buf_bpp, ps_wc;
 309        u32 ps_bpp_mode;
 310
 311        if (dsi->format == MIPI_DSI_FMT_RGB565)
 312                dsi_buf_bpp = 2;
 313        else
 314                dsi_buf_bpp = 3;
 315
 316        ps_wc = vm->hactive * dsi_buf_bpp;
 317        ps_bpp_mode = ps_wc;
 318
 319        switch (dsi->format) {
 320        case MIPI_DSI_FMT_RGB888:
 321                ps_bpp_mode |= PACKED_PS_24BIT_RGB888;
 322                break;
 323        case MIPI_DSI_FMT_RGB666:
 324                ps_bpp_mode |= PACKED_PS_18BIT_RGB666;
 325                break;
 326        case MIPI_DSI_FMT_RGB666_PACKED:
 327                ps_bpp_mode |= LOOSELY_PS_18BIT_RGB666;
 328                break;
 329        case MIPI_DSI_FMT_RGB565:
 330                ps_bpp_mode |= PACKED_PS_16BIT_RGB565;
 331                break;
 332        }
 333
 334        writel(vm->vactive, dsi->regs + DSI_VACT_NL);
 335        writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL);
 336        writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC);
 337}
 338
 339static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi)
 340{
 341        u32 tmp_reg;
 342
 343        switch (dsi->lanes) {
 344        case 1:
 345                tmp_reg = 1 << 2;
 346                break;
 347        case 2:
 348                tmp_reg = 3 << 2;
 349                break;
 350        case 3:
 351                tmp_reg = 7 << 2;
 352                break;
 353        case 4:
 354                tmp_reg = 0xf << 2;
 355                break;
 356        default:
 357                tmp_reg = 0xf << 2;
 358                break;
 359        }
 360
 361        tmp_reg |= (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6;
 362        tmp_reg |= (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3;
 363
 364        writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL);
 365}
 366
 367static void mtk_dsi_ps_control(struct mtk_dsi *dsi)
 368{
 369        u32 dsi_tmp_buf_bpp;
 370        u32 tmp_reg;
 371
 372        switch (dsi->format) {
 373        case MIPI_DSI_FMT_RGB888:
 374                tmp_reg = PACKED_PS_24BIT_RGB888;
 375                dsi_tmp_buf_bpp = 3;
 376                break;
 377        case MIPI_DSI_FMT_RGB666:
 378                tmp_reg = LOOSELY_PS_18BIT_RGB666;
 379                dsi_tmp_buf_bpp = 3;
 380                break;
 381        case MIPI_DSI_FMT_RGB666_PACKED:
 382                tmp_reg = PACKED_PS_18BIT_RGB666;
 383                dsi_tmp_buf_bpp = 3;
 384                break;
 385        case MIPI_DSI_FMT_RGB565:
 386                tmp_reg = PACKED_PS_16BIT_RGB565;
 387                dsi_tmp_buf_bpp = 2;
 388                break;
 389        default:
 390                tmp_reg = PACKED_PS_24BIT_RGB888;
 391                dsi_tmp_buf_bpp = 3;
 392                break;
 393        }
 394
 395        tmp_reg += dsi->vm.hactive * dsi_tmp_buf_bpp & DSI_PS_WC;
 396        writel(tmp_reg, dsi->regs + DSI_PSCTRL);
 397}
 398
 399static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
 400{
 401        u32 horizontal_sync_active_byte;
 402        u32 horizontal_backporch_byte;
 403        u32 horizontal_frontporch_byte;
 404        u32 dsi_tmp_buf_bpp;
 405
 406        struct videomode *vm = &dsi->vm;
 407
 408        if (dsi->format == MIPI_DSI_FMT_RGB565)
 409                dsi_tmp_buf_bpp = 2;
 410        else
 411                dsi_tmp_buf_bpp = 3;
 412
 413        writel(vm->vsync_len, dsi->regs + DSI_VSA_NL);
 414        writel(vm->vback_porch, dsi->regs + DSI_VBP_NL);
 415        writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
 416        writel(vm->vactive, dsi->regs + DSI_VACT_NL);
 417
 418        horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
 419
 420        if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
 421                horizontal_backporch_byte =
 422                        (vm->hback_porch * dsi_tmp_buf_bpp - 10);
 423        else
 424                horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *
 425                        dsi_tmp_buf_bpp - 10);
 426
 427        horizontal_frontporch_byte = (vm->hfront_porch * dsi_tmp_buf_bpp - 12);
 428
 429        writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
 430        writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
 431        writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
 432
 433        mtk_dsi_ps_control(dsi);
 434}
 435
 436static void mtk_dsi_start(struct mtk_dsi *dsi)
 437{
 438        writel(0, dsi->regs + DSI_START);
 439        writel(1, dsi->regs + DSI_START);
 440}
 441
 442static void mtk_dsi_stop(struct mtk_dsi *dsi)
 443{
 444        writel(0, dsi->regs + DSI_START);
 445}
 446
 447static void mtk_dsi_set_cmd_mode(struct mtk_dsi *dsi)
 448{
 449        writel(CMD_MODE, dsi->regs + DSI_MODE_CTRL);
 450}
 451
 452static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi)
 453{
 454        u32 inten = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
 455
 456        writel(inten, dsi->regs + DSI_INTEN);
 457}
 458
 459static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit)
 460{
 461        dsi->irq_data |= irq_bit;
 462}
 463
 464static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit)
 465{
 466        dsi->irq_data &= ~irq_bit;
 467}
 468
 469static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag,
 470                                     unsigned int timeout)
 471{
 472        s32 ret = 0;
 473        unsigned long jiffies = msecs_to_jiffies(timeout);
 474
 475        ret = wait_event_interruptible_timeout(dsi->irq_wait_queue,
 476                                               dsi->irq_data & irq_flag,
 477                                               jiffies);
 478        if (ret == 0) {
 479                DRM_WARN("Wait DSI IRQ(0x%08x) Timeout\n", irq_flag);
 480
 481                mtk_dsi_enable(dsi);
 482                mtk_dsi_reset_engine(dsi);
 483        }
 484
 485        return ret;
 486}
 487
 488static irqreturn_t mtk_dsi_irq(int irq, void *dev_id)
 489{
 490        struct mtk_dsi *dsi = dev_id;
 491        u32 status, tmp;
 492        u32 flag = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
 493
 494        status = readl(dsi->regs + DSI_INTSTA) & flag;
 495
 496        if (status) {
 497                do {
 498                        mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK);
 499                        tmp = readl(dsi->regs + DSI_INTSTA);
 500                } while (tmp & DSI_BUSY);
 501
 502                mtk_dsi_mask(dsi, DSI_INTSTA, status, 0);
 503                mtk_dsi_irq_data_set(dsi, status);
 504                wake_up_interruptible(&dsi->irq_wait_queue);
 505        }
 506
 507        return IRQ_HANDLED;
 508}
 509
 510static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t)
 511{
 512        mtk_dsi_irq_data_clear(dsi, irq_flag);
 513        mtk_dsi_set_cmd_mode(dsi);
 514
 515        if (!mtk_dsi_wait_for_irq_done(dsi, irq_flag, t)) {
 516                DRM_ERROR("failed to switch cmd mode\n");
 517                return -ETIME;
 518        } else {
 519                return 0;
 520        }
 521}
 522
 523static int mtk_dsi_poweron(struct mtk_dsi *dsi)
 524{
 525        struct device *dev = dsi->dev;
 526        int ret;
 527        u64 pixel_clock, total_bits;
 528        u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
 529
 530        if (++dsi->refcount != 1)
 531                return 0;
 532
 533        switch (dsi->format) {
 534        case MIPI_DSI_FMT_RGB565:
 535                bit_per_pixel = 16;
 536                break;
 537        case MIPI_DSI_FMT_RGB666_PACKED:
 538                bit_per_pixel = 18;
 539                break;
 540        case MIPI_DSI_FMT_RGB666:
 541        case MIPI_DSI_FMT_RGB888:
 542        default:
 543                bit_per_pixel = 24;
 544                break;
 545        }
 546
 547        /**
 548         * htotal_time = htotal * byte_per_pixel / num_lanes
 549         * overhead_time = lpx + hs_prepare + hs_zero + hs_trail + hs_exit
 550         * mipi_ratio = (htotal_time + overhead_time) / htotal_time
 551         * data_rate = pixel_clock * bit_per_pixel * mipi_ratio / num_lanes;
 552         */
 553        pixel_clock = dsi->vm.pixelclock;
 554        htotal = dsi->vm.hactive + dsi->vm.hback_porch + dsi->vm.hfront_porch +
 555                        dsi->vm.hsync_len;
 556        htotal_bits = htotal * bit_per_pixel;
 557
 558        overhead_cycles = T_LPX + T_HS_PREP + T_HS_ZERO + T_HS_TRAIL +
 559                        T_HS_EXIT;
 560        overhead_bits = overhead_cycles * dsi->lanes * 8;
 561        total_bits = htotal_bits + overhead_bits;
 562
 563        dsi->data_rate = DIV_ROUND_UP_ULL(pixel_clock * total_bits,
 564                                          htotal * dsi->lanes);
 565
 566        ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
 567        if (ret < 0) {
 568                dev_err(dev, "Failed to set data rate: %d\n", ret);
 569                goto err_refcount;
 570        }
 571
 572        phy_power_on(dsi->phy);
 573
 574        ret = clk_prepare_enable(dsi->engine_clk);
 575        if (ret < 0) {
 576                dev_err(dev, "Failed to enable engine clock: %d\n", ret);
 577                goto err_phy_power_off;
 578        }
 579
 580        ret = clk_prepare_enable(dsi->digital_clk);
 581        if (ret < 0) {
 582                dev_err(dev, "Failed to enable digital clock: %d\n", ret);
 583                goto err_disable_engine_clk;
 584        }
 585
 586        mtk_dsi_enable(dsi);
 587        mtk_dsi_reset_engine(dsi);
 588        mtk_dsi_phy_timconfig(dsi);
 589
 590        mtk_dsi_rxtx_control(dsi);
 591        mtk_dsi_ps_control_vact(dsi);
 592        mtk_dsi_set_vm_cmd(dsi);
 593        mtk_dsi_config_vdo_timing(dsi);
 594        mtk_dsi_set_interrupt_enable(dsi);
 595
 596        mtk_dsi_clk_ulp_mode_leave(dsi);
 597        mtk_dsi_lane0_ulp_mode_leave(dsi);
 598        mtk_dsi_clk_hs_mode(dsi, 0);
 599
 600        if (dsi->panel) {
 601                if (drm_panel_prepare(dsi->panel)) {
 602                        DRM_ERROR("failed to prepare the panel\n");
 603                        goto err_disable_digital_clk;
 604                }
 605        }
 606
 607        return 0;
 608err_disable_digital_clk:
 609        clk_disable_unprepare(dsi->digital_clk);
 610err_disable_engine_clk:
 611        clk_disable_unprepare(dsi->engine_clk);
 612err_phy_power_off:
 613        phy_power_off(dsi->phy);
 614err_refcount:
 615        dsi->refcount--;
 616        return ret;
 617}
 618
 619static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
 620{
 621        if (WARN_ON(dsi->refcount == 0))
 622                return;
 623
 624        if (--dsi->refcount != 0)
 625                return;
 626
 627        /*
 628         * mtk_dsi_stop() and mtk_dsi_start() is asymmetric, since
 629         * mtk_dsi_stop() should be called after mtk_drm_crtc_atomic_disable(),
 630         * which needs irq for vblank, and mtk_dsi_stop() will disable irq.
 631         * mtk_dsi_start() needs to be called in mtk_output_dsi_enable(),
 632         * after dsi is fully set.
 633         */
 634        mtk_dsi_stop(dsi);
 635
 636        if (!mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500)) {
 637                if (dsi->panel) {
 638                        if (drm_panel_unprepare(dsi->panel)) {
 639                                DRM_ERROR("failed to unprepare the panel\n");
 640                                return;
 641                        }
 642                }
 643        }
 644
 645        mtk_dsi_reset_engine(dsi);
 646        mtk_dsi_lane0_ulp_mode_enter(dsi);
 647        mtk_dsi_clk_ulp_mode_enter(dsi);
 648
 649        mtk_dsi_disable(dsi);
 650
 651        clk_disable_unprepare(dsi->engine_clk);
 652        clk_disable_unprepare(dsi->digital_clk);
 653
 654        phy_power_off(dsi->phy);
 655}
 656
 657static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
 658{
 659        int ret;
 660
 661        if (dsi->enabled)
 662                return;
 663
 664        ret = mtk_dsi_poweron(dsi);
 665        if (ret < 0) {
 666                DRM_ERROR("failed to power on dsi\n");
 667                return;
 668        }
 669
 670        mtk_dsi_set_mode(dsi);
 671        mtk_dsi_clk_hs_mode(dsi, 1);
 672
 673        mtk_dsi_start(dsi);
 674
 675        if (dsi->panel) {
 676                if (drm_panel_enable(dsi->panel)) {
 677                        DRM_ERROR("failed to enable the panel\n");
 678                        goto err_dsi_power_off;
 679                }
 680        }
 681
 682        dsi->enabled = true;
 683
 684        return;
 685err_dsi_power_off:
 686        mtk_dsi_stop(dsi);
 687        mtk_dsi_poweroff(dsi);
 688}
 689
 690static void mtk_output_dsi_disable(struct mtk_dsi *dsi)
 691{
 692        if (!dsi->enabled)
 693                return;
 694
 695        if (dsi->panel) {
 696                if (drm_panel_disable(dsi->panel)) {
 697                        DRM_ERROR("failed to disable the panel\n");
 698                        return;
 699                }
 700        }
 701
 702        mtk_dsi_poweroff(dsi);
 703
 704        dsi->enabled = false;
 705}
 706
 707static void mtk_dsi_encoder_destroy(struct drm_encoder *encoder)
 708{
 709        drm_encoder_cleanup(encoder);
 710}
 711
 712static const struct drm_encoder_funcs mtk_dsi_encoder_funcs = {
 713        .destroy = mtk_dsi_encoder_destroy,
 714};
 715
 716static bool mtk_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
 717                                       const struct drm_display_mode *mode,
 718                                       struct drm_display_mode *adjusted_mode)
 719{
 720        return true;
 721}
 722
 723static void mtk_dsi_encoder_mode_set(struct drm_encoder *encoder,
 724                                     struct drm_display_mode *mode,
 725                                     struct drm_display_mode *adjusted)
 726{
 727        struct mtk_dsi *dsi = encoder_to_dsi(encoder);
 728
 729        drm_display_mode_to_videomode(adjusted, &dsi->vm);
 730}
 731
 732static void mtk_dsi_encoder_disable(struct drm_encoder *encoder)
 733{
 734        struct mtk_dsi *dsi = encoder_to_dsi(encoder);
 735
 736        mtk_output_dsi_disable(dsi);
 737}
 738
 739static void mtk_dsi_encoder_enable(struct drm_encoder *encoder)
 740{
 741        struct mtk_dsi *dsi = encoder_to_dsi(encoder);
 742
 743        mtk_output_dsi_enable(dsi);
 744}
 745
 746static int mtk_dsi_connector_get_modes(struct drm_connector *connector)
 747{
 748        struct mtk_dsi *dsi = connector_to_dsi(connector);
 749
 750        return drm_panel_get_modes(dsi->panel);
 751}
 752
 753static const struct drm_encoder_helper_funcs mtk_dsi_encoder_helper_funcs = {
 754        .mode_fixup = mtk_dsi_encoder_mode_fixup,
 755        .mode_set = mtk_dsi_encoder_mode_set,
 756        .disable = mtk_dsi_encoder_disable,
 757        .enable = mtk_dsi_encoder_enable,
 758};
 759
 760static const struct drm_connector_funcs mtk_dsi_connector_funcs = {
 761        .fill_modes = drm_helper_probe_single_connector_modes,
 762        .destroy = drm_connector_cleanup,
 763        .reset = drm_atomic_helper_connector_reset,
 764        .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 765        .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 766};
 767
 768static const struct drm_connector_helper_funcs
 769        mtk_dsi_connector_helper_funcs = {
 770        .get_modes = mtk_dsi_connector_get_modes,
 771};
 772
 773static int mtk_dsi_create_connector(struct drm_device *drm, struct mtk_dsi *dsi)
 774{
 775        int ret;
 776
 777        ret = drm_connector_init(drm, &dsi->conn, &mtk_dsi_connector_funcs,
 778                                 DRM_MODE_CONNECTOR_DSI);
 779        if (ret) {
 780                DRM_ERROR("Failed to connector init to drm\n");
 781                return ret;
 782        }
 783
 784        drm_connector_helper_add(&dsi->conn, &mtk_dsi_connector_helper_funcs);
 785
 786        dsi->conn.dpms = DRM_MODE_DPMS_OFF;
 787        drm_connector_attach_encoder(&dsi->conn, &dsi->encoder);
 788
 789        if (dsi->panel) {
 790                ret = drm_panel_attach(dsi->panel, &dsi->conn);
 791                if (ret) {
 792                        DRM_ERROR("Failed to attach panel to drm\n");
 793                        goto err_connector_cleanup;
 794                }
 795        }
 796
 797        return 0;
 798
 799err_connector_cleanup:
 800        drm_connector_cleanup(&dsi->conn);
 801        return ret;
 802}
 803
 804static int mtk_dsi_create_conn_enc(struct drm_device *drm, struct mtk_dsi *dsi)
 805{
 806        int ret;
 807
 808        ret = drm_encoder_init(drm, &dsi->encoder, &mtk_dsi_encoder_funcs,
 809                               DRM_MODE_ENCODER_DSI, NULL);
 810        if (ret) {
 811                DRM_ERROR("Failed to encoder init to drm\n");
 812                return ret;
 813        }
 814        drm_encoder_helper_add(&dsi->encoder, &mtk_dsi_encoder_helper_funcs);
 815
 816        /*
 817         * Currently display data paths are statically assigned to a crtc each.
 818         * crtc 0 is OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0
 819         */
 820        dsi->encoder.possible_crtcs = 1;
 821
 822        /* If there's a bridge, attach to it and let it create the connector */
 823        if (dsi->bridge) {
 824                ret = drm_bridge_attach(&dsi->encoder, dsi->bridge, NULL);
 825                if (ret) {
 826                        DRM_ERROR("Failed to attach bridge to drm\n");
 827                        goto err_encoder_cleanup;
 828                }
 829        } else {
 830                /* Otherwise create our own connector and attach to a panel */
 831                ret = mtk_dsi_create_connector(drm, dsi);
 832                if (ret)
 833                        goto err_encoder_cleanup;
 834        }
 835
 836        return 0;
 837
 838err_encoder_cleanup:
 839        drm_encoder_cleanup(&dsi->encoder);
 840        return ret;
 841}
 842
 843static void mtk_dsi_destroy_conn_enc(struct mtk_dsi *dsi)
 844{
 845        drm_encoder_cleanup(&dsi->encoder);
 846        /* Skip connector cleanup if creation was delegated to the bridge */
 847        if (dsi->conn.dev)
 848                drm_connector_cleanup(&dsi->conn);
 849        if (dsi->panel)
 850                drm_panel_detach(dsi->panel);
 851}
 852
 853static void mtk_dsi_ddp_start(struct mtk_ddp_comp *comp)
 854{
 855        struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp);
 856
 857        mtk_dsi_poweron(dsi);
 858}
 859
 860static void mtk_dsi_ddp_stop(struct mtk_ddp_comp *comp)
 861{
 862        struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp);
 863
 864        mtk_dsi_poweroff(dsi);
 865}
 866
 867static const struct mtk_ddp_comp_funcs mtk_dsi_funcs = {
 868        .start = mtk_dsi_ddp_start,
 869        .stop = mtk_dsi_ddp_stop,
 870};
 871
 872static int mtk_dsi_host_attach(struct mipi_dsi_host *host,
 873                               struct mipi_dsi_device *device)
 874{
 875        struct mtk_dsi *dsi = host_to_dsi(host);
 876
 877        dsi->lanes = device->lanes;
 878        dsi->format = device->format;
 879        dsi->mode_flags = device->mode_flags;
 880
 881        if (dsi->conn.dev)
 882                drm_helper_hpd_irq_event(dsi->conn.dev);
 883
 884        return 0;
 885}
 886
 887static int mtk_dsi_host_detach(struct mipi_dsi_host *host,
 888                               struct mipi_dsi_device *device)
 889{
 890        struct mtk_dsi *dsi = host_to_dsi(host);
 891
 892        if (dsi->conn.dev)
 893                drm_helper_hpd_irq_event(dsi->conn.dev);
 894
 895        return 0;
 896}
 897
 898static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi)
 899{
 900        int ret;
 901        u32 val;
 902
 903        ret = readl_poll_timeout(dsi->regs + DSI_INTSTA, val, !(val & DSI_BUSY),
 904                                 4, 2000000);
 905        if (ret) {
 906                DRM_WARN("polling dsi wait not busy timeout!\n");
 907
 908                mtk_dsi_enable(dsi);
 909                mtk_dsi_reset_engine(dsi);
 910        }
 911}
 912
 913static u32 mtk_dsi_recv_cnt(u8 type, u8 *read_data)
 914{
 915        switch (type) {
 916        case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
 917        case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
 918                return 1;
 919        case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
 920        case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
 921                return 2;
 922        case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
 923        case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
 924                return read_data[1] + read_data[2] * 16;
 925        case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
 926                DRM_INFO("type is 0x02, try again\n");
 927                break;
 928        default:
 929                DRM_INFO("type(0x%x) not recognized\n", type);
 930                break;
 931        }
 932
 933        return 0;
 934}
 935
 936static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)
 937{
 938        const char *tx_buf = msg->tx_buf;
 939        u8 config, cmdq_size, cmdq_off, type = msg->type;
 940        u32 reg_val, cmdq_mask, i;
 941
 942        if (MTK_DSI_HOST_IS_READ(type))
 943                config = BTA;
 944        else
 945                config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET;
 946
 947        if (msg->tx_len > 2) {
 948                cmdq_size = 1 + (msg->tx_len + 3) / 4;
 949                cmdq_off = 4;
 950                cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1;
 951                reg_val = (msg->tx_len << 16) | (type << 8) | config;
 952        } else {
 953                cmdq_size = 1;
 954                cmdq_off = 2;
 955                cmdq_mask = CONFIG | DATA_ID;
 956                reg_val = (type << 8) | config;
 957        }
 958
 959        for (i = 0; i < msg->tx_len; i++)
 960                writeb(tx_buf[i], dsi->regs + DSI_CMDQ0 + cmdq_off + i);
 961
 962        mtk_dsi_mask(dsi, DSI_CMDQ0, cmdq_mask, reg_val);
 963        mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
 964}
 965
 966static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi,
 967                                     const struct mipi_dsi_msg *msg, u8 flag)
 968{
 969        mtk_dsi_wait_for_idle(dsi);
 970        mtk_dsi_irq_data_clear(dsi, flag);
 971        mtk_dsi_cmdq(dsi, msg);
 972        mtk_dsi_start(dsi);
 973
 974        if (!mtk_dsi_wait_for_irq_done(dsi, flag, 2000))
 975                return -ETIME;
 976        else
 977                return 0;
 978}
 979
 980static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host,
 981                                     const struct mipi_dsi_msg *msg)
 982{
 983        struct mtk_dsi *dsi = host_to_dsi(host);
 984        u32 recv_cnt, i;
 985        u8 read_data[16];
 986        void *src_addr;
 987        u8 irq_flag = CMD_DONE_INT_FLAG;
 988
 989        if (readl(dsi->regs + DSI_MODE_CTRL) & MODE) {
 990                DRM_ERROR("dsi engine is not command mode\n");
 991                return -EINVAL;
 992        }
 993
 994        if (MTK_DSI_HOST_IS_READ(msg->type))
 995                irq_flag |= LPRX_RD_RDY_INT_FLAG;
 996
 997        if (mtk_dsi_host_send_cmd(dsi, msg, irq_flag) < 0)
 998                return -ETIME;
 999
1000        if (!MTK_DSI_HOST_IS_READ(msg->type))
1001                return 0;
1002
1003        if (!msg->rx_buf) {
1004                DRM_ERROR("dsi receive buffer size may be NULL\n");
1005                return -EINVAL;
1006        }
1007
1008        for (i = 0; i < 16; i++)
1009                *(read_data + i) = readb(dsi->regs + DSI_RX_DATA0 + i);
1010
1011        recv_cnt = mtk_dsi_recv_cnt(read_data[0], read_data);
1012
1013        if (recv_cnt > 2)
1014                src_addr = &read_data[4];
1015        else
1016                src_addr = &read_data[1];
1017
1018        if (recv_cnt > 10)
1019                recv_cnt = 10;
1020
1021        if (recv_cnt > msg->rx_len)
1022                recv_cnt = msg->rx_len;
1023
1024        if (recv_cnt)
1025                memcpy(msg->rx_buf, src_addr, recv_cnt);
1026
1027        DRM_INFO("dsi get %d byte data from the panel address(0x%x)\n",
1028                 recv_cnt, *((u8 *)(msg->tx_buf)));
1029
1030        return recv_cnt;
1031}
1032
1033static const struct mipi_dsi_host_ops mtk_dsi_ops = {
1034        .attach = mtk_dsi_host_attach,
1035        .detach = mtk_dsi_host_detach,
1036        .transfer = mtk_dsi_host_transfer,
1037};
1038
1039static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)
1040{
1041        int ret;
1042        struct drm_device *drm = data;
1043        struct mtk_dsi *dsi = dev_get_drvdata(dev);
1044
1045        ret = mtk_ddp_comp_register(drm, &dsi->ddp_comp);
1046        if (ret < 0) {
1047                dev_err(dev, "Failed to register component %pOF: %d\n",
1048                        dev->of_node, ret);
1049                return ret;
1050        }
1051
1052        ret = mipi_dsi_host_register(&dsi->host);
1053        if (ret < 0) {
1054                dev_err(dev, "failed to register DSI host: %d\n", ret);
1055                goto err_ddp_comp_unregister;
1056        }
1057
1058        ret = mtk_dsi_create_conn_enc(drm, dsi);
1059        if (ret) {
1060                DRM_ERROR("Encoder create failed with %d\n", ret);
1061                goto err_unregister;
1062        }
1063
1064        return 0;
1065
1066err_unregister:
1067        mipi_dsi_host_unregister(&dsi->host);
1068err_ddp_comp_unregister:
1069        mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
1070        return ret;
1071}
1072
1073static void mtk_dsi_unbind(struct device *dev, struct device *master,
1074                           void *data)
1075{
1076        struct drm_device *drm = data;
1077        struct mtk_dsi *dsi = dev_get_drvdata(dev);
1078
1079        mtk_dsi_destroy_conn_enc(dsi);
1080        mipi_dsi_host_unregister(&dsi->host);
1081        mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
1082}
1083
1084static const struct component_ops mtk_dsi_component_ops = {
1085        .bind = mtk_dsi_bind,
1086        .unbind = mtk_dsi_unbind,
1087};
1088
1089static int mtk_dsi_probe(struct platform_device *pdev)
1090{
1091        struct mtk_dsi *dsi;
1092        struct device *dev = &pdev->dev;
1093        struct resource *regs;
1094        int irq_num;
1095        int comp_id;
1096        int ret;
1097
1098        dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1099        if (!dsi)
1100                return -ENOMEM;
1101
1102        dsi->host.ops = &mtk_dsi_ops;
1103        dsi->host.dev = dev;
1104
1105        ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
1106                                          &dsi->panel, &dsi->bridge);
1107        if (ret)
1108                return ret;
1109
1110        dsi->engine_clk = devm_clk_get(dev, "engine");
1111        if (IS_ERR(dsi->engine_clk)) {
1112                ret = PTR_ERR(dsi->engine_clk);
1113                dev_err(dev, "Failed to get engine clock: %d\n", ret);
1114                return ret;
1115        }
1116
1117        dsi->digital_clk = devm_clk_get(dev, "digital");
1118        if (IS_ERR(dsi->digital_clk)) {
1119                ret = PTR_ERR(dsi->digital_clk);
1120                dev_err(dev, "Failed to get digital clock: %d\n", ret);
1121                return ret;
1122        }
1123
1124        dsi->hs_clk = devm_clk_get(dev, "hs");
1125        if (IS_ERR(dsi->hs_clk)) {
1126                ret = PTR_ERR(dsi->hs_clk);
1127                dev_err(dev, "Failed to get hs clock: %d\n", ret);
1128                return ret;
1129        }
1130
1131        regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1132        dsi->regs = devm_ioremap_resource(dev, regs);
1133        if (IS_ERR(dsi->regs)) {
1134                ret = PTR_ERR(dsi->regs);
1135                dev_err(dev, "Failed to ioremap memory: %d\n", ret);
1136                return ret;
1137        }
1138
1139        dsi->phy = devm_phy_get(dev, "dphy");
1140        if (IS_ERR(dsi->phy)) {
1141                ret = PTR_ERR(dsi->phy);
1142                dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret);
1143                return ret;
1144        }
1145
1146        comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI);
1147        if (comp_id < 0) {
1148                dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
1149                return comp_id;
1150        }
1151
1152        ret = mtk_ddp_comp_init(dev, dev->of_node, &dsi->ddp_comp, comp_id,
1153                                &mtk_dsi_funcs);
1154        if (ret) {
1155                dev_err(dev, "Failed to initialize component: %d\n", ret);
1156                return ret;
1157        }
1158
1159        irq_num = platform_get_irq(pdev, 0);
1160        if (irq_num < 0) {
1161                dev_err(&pdev->dev, "failed to request dsi irq resource\n");
1162                return -EPROBE_DEFER;
1163        }
1164
1165        irq_set_status_flags(irq_num, IRQ_TYPE_LEVEL_LOW);
1166        ret = devm_request_irq(&pdev->dev, irq_num, mtk_dsi_irq,
1167                               IRQF_TRIGGER_LOW, dev_name(&pdev->dev), dsi);
1168        if (ret) {
1169                dev_err(&pdev->dev, "failed to request mediatek dsi irq\n");
1170                return -EPROBE_DEFER;
1171        }
1172
1173        init_waitqueue_head(&dsi->irq_wait_queue);
1174
1175        platform_set_drvdata(pdev, dsi);
1176
1177        return component_add(&pdev->dev, &mtk_dsi_component_ops);
1178}
1179
1180static int mtk_dsi_remove(struct platform_device *pdev)
1181{
1182        struct mtk_dsi *dsi = platform_get_drvdata(pdev);
1183
1184        mtk_output_dsi_disable(dsi);
1185        component_del(&pdev->dev, &mtk_dsi_component_ops);
1186
1187        return 0;
1188}
1189
1190static const struct of_device_id mtk_dsi_of_match[] = {
1191        { .compatible = "mediatek,mt2701-dsi" },
1192        { .compatible = "mediatek,mt8173-dsi" },
1193        { },
1194};
1195
1196struct platform_driver mtk_dsi_driver = {
1197        .probe = mtk_dsi_probe,
1198        .remove = mtk_dsi_remove,
1199        .driver = {
1200                .name = "mtk-dsi",
1201                .of_match_table = mtk_dsi_of_match,
1202        },
1203};
1204