LXR linux/drivers/gpu/drm/msm/adreno/a6xx

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/* Copyright (c) 2017 The Linux Foundation. All rights reserved. */
   3
   4#ifndef _A6XX_GMU_H_
   5#define _A6XX_GMU_H_
   6
   7#include <linux/iopoll.h>
   8#include <linux/interrupt.h>
   9#include "msm_drv.h"
  10#include "a6xx_hfi.h"
  11
  12struct a6xx_gmu_bo {
  13        struct drm_gem_object *obj;
  14        void *virt;
  15        size_t size;
  16        u64 iova;
  17};
  18
  19/*
  20 * These define the different GMU wake up options - these define how both the
  21 * CPU and the GMU bring up the hardware
  22 */
  23
  24/* THe GMU has already been booted and the rentention registers are active */
  25#define GMU_WARM_BOOT 0
  26
  27/* the GMU is coming up for the first time or back from a power collapse */
  28#define GMU_COLD_BOOT 1
  29
  30/*
  31 * These define the level of control that the GMU has - the higher the number
  32 * the more things that the GMU hardware controls on its own.
  33 */
  34
  35/* The GMU does not do any idle state management */
  36#define GMU_IDLE_STATE_ACTIVE 0
  37
  38/* The GMU manages SPTP power collapse */
  39#define GMU_IDLE_STATE_SPTP 2
  40
  41/* The GMU does automatic IFPC (intra-frame power collapse) */
  42#define GMU_IDLE_STATE_IFPC 3
  43
  44struct a6xx_gmu {
  45        struct device *dev;
  46
  47        /* For serializing communication with the GMU: */
  48        struct mutex lock;
  49
  50        struct msm_gem_address_space *aspace;
  51
  52        void * __iomem mmio;
  53        void * __iomem rscc;
  54
  55        int hfi_irq;
  56        int gmu_irq;
  57
  58        struct device *gxpd;
  59
  60        int idle_level;
  61
  62        struct a6xx_gmu_bo hfi;
  63        struct a6xx_gmu_bo debug;
  64        struct a6xx_gmu_bo icache;
  65        struct a6xx_gmu_bo dcache;
  66        struct a6xx_gmu_bo dummy;
  67        struct a6xx_gmu_bo log;
  68
  69        int nr_clocks;
  70        struct clk_bulk_data *clocks;
  71        struct clk *core_clk;
  72        struct clk *hub_clk;
  73
  74        /* current performance index set externally */
  75        int current_perf_index;
  76
  77        int nr_gpu_freqs;
  78        unsigned long gpu_freqs[16];
  79        u32 gx_arc_votes[16];
  80
  81        int nr_gmu_freqs;
  82        unsigned long gmu_freqs[4];
  83        u32 cx_arc_votes[4];
  84
  85        unsigned long freq;
  86
  87        struct a6xx_hfi_queue queues[2];
  88
  89        bool initialized;
  90        bool hung;
  91        bool legacy; /* a618 or a630 */
  92};
  93
  94static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)
  95{
  96        return msm_readl(gmu->mmio + (offset << 2));
  97}
  98
  99static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value)
 100{
 101        return msm_writel(value, gmu->mmio + (offset << 2));
 102}
 103
 104static inline void
 105gmu_write_bulk(struct a6xx_gmu *gmu, u32 offset, const u32 *data, u32 size)
 106{
 107        memcpy_toio(gmu->mmio + (offset << 2), data, size);
 108        wmb();
 109}
 110
 111static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or)
 112{
 113        u32 val = gmu_read(gmu, reg);
 114
 115        val &= ~mask;
 116
 117        gmu_write(gmu, reg, val | or);
 118}
 119
 120static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi)
 121{
 122        u64 val;
 123
 124        val = (u64) msm_readl(gmu->mmio + (lo << 2));
 125        val |= ((u64) msm_readl(gmu->mmio + (hi << 2)) << 32);
 126
 127        return val;
 128}
 129
 130#define gmu_poll_timeout(gmu, addr, val, cond, interval, timeout) \
 131        readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \
 132                interval, timeout)
 133
 134static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset)
 135{
 136        return msm_readl(gmu->rscc + (offset << 2));
 137}
 138
 139static inline void gmu_write_rscc(struct a6xx_gmu *gmu, u32 offset, u32 value)
 140{
 141        return msm_writel(value, gmu->rscc + (offset << 2));
 142}
 143
 144#define gmu_poll_timeout_rscc(gmu, addr, val, cond, interval, timeout) \
 145        readl_poll_timeout((gmu)->rscc + ((addr) << 2), val, cond, \
 146                interval, timeout)
 147
 148/*
 149 * These are the available OOB (out of band requests) to the GMU where "out of
 150 * band" means that the CPU talks to the GMU directly and not through HFI.
 151 * Normally this works by writing a ITCM/DTCM register and then triggering a
 152 * interrupt (the "request" bit) and waiting for an acknowledgment (the "ack"
 153 * bit). The state is cleared by writing the "clear' bit to the GMU interrupt.
 154 *
 155 * These are used to force the GMU/GPU to stay on during a critical sequence or
 156 * for hardware workarounds.
 157 */
 158
 159enum a6xx_gmu_oob_state {
 160        /*
 161         * Let the GMU know that a boot or slumber operation has started. The value in
 162         * REG_A6XX_GMU_BOOT_SLUMBER_OPTION lets the GMU know which operation we are
 163         * doing
 164         */
 165        GMU_OOB_BOOT_SLUMBER = 0,
 166        /*
 167         * Let the GMU know to not turn off any GPU registers while the CPU is in a
 168         * critical section
 169         */
 170        GMU_OOB_GPU_SET,
 171        /*
 172         * Set a new power level for the GPU when the CPU is doing frequency scaling
 173         */
 174        GMU_OOB_DCVS_SET,
 175        /*
 176         * Used to keep the GPU on for CPU-side reads of performance counters.
 177         */
 178        GMU_OOB_PERFCOUNTER_SET,
 179};
 180
 181void a6xx_hfi_init(struct a6xx_gmu *gmu);
 182int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state);
 183void a6xx_hfi_stop(struct a6xx_gmu *gmu);
 184int a6xx_hfi_send_prep_slumber(struct a6xx_gmu *gmu);
 185int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, int index);
 186
 187bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu);
 188bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu);
 189
 190#endif
 191