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9#ifndef __ADRENO_GPU_H__
10#define __ADRENO_GPU_H__
11
12#include <linux/firmware.h>
13#include <linux/iopoll.h>
14
15#include "msm_gpu.h"
16
17#include "adreno_common.xml.h"
18#include "adreno_pm4.xml.h"
19
20extern bool snapshot_debugbus;
21extern bool allow_vram_carveout;
22
23enum {
24 ADRENO_FW_PM4 = 0,
25 ADRENO_FW_SQE = 0,
26 ADRENO_FW_PFP = 1,
27 ADRENO_FW_GMU = 1,
28 ADRENO_FW_GPMU = 2,
29 ADRENO_FW_MAX,
30};
31
32enum adreno_quirks {
33 ADRENO_QUIRK_TWO_PASS_USE_WFI = 1,
34 ADRENO_QUIRK_FAULT_DETECT_MASK = 2,
35 ADRENO_QUIRK_LMLOADKILL_DISABLE = 3,
36};
37
38struct adreno_rev {
39 uint8_t core;
40 uint8_t major;
41 uint8_t minor;
42 uint8_t patchid;
43};
44
45#define ANY_ID 0xff
46
47#define ADRENO_REV(core, major, minor, patchid) \
48 ((struct adreno_rev){ core, major, minor, patchid })
49
50struct adreno_gpu_funcs {
51 struct msm_gpu_funcs base;
52 int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
53};
54
55struct adreno_reglist {
56 u32 offset;
57 u32 value;
58};
59
60extern const struct adreno_reglist a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[];
61
62struct adreno_info {
63 struct adreno_rev rev;
64 uint32_t revn;
65 const char *name;
66 const char *fw[ADRENO_FW_MAX];
67 uint32_t gmem;
68 enum adreno_quirks quirks;
69 struct msm_gpu *(*init)(struct drm_device *dev);
70 const char *zapfw;
71 u32 inactive_period;
72 const struct adreno_reglist *hwcg;
73};
74
75const struct adreno_info *adreno_info(struct adreno_rev rev);
76
77struct adreno_gpu {
78 struct msm_gpu base;
79 struct adreno_rev rev;
80 const struct adreno_info *info;
81 uint32_t gmem;
82 uint32_t revn;
83 const struct adreno_gpu_funcs *funcs;
84
85
86 const unsigned int *registers;
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100
101
102 enum {
103 FW_LOCATION_UNKNOWN = 0,
104 FW_LOCATION_NEW,
105 FW_LOCATION_LEGACY,
106 FW_LOCATION_HELPER,
107 } fwloc;
108
109
110 const struct firmware *fw[ADRENO_FW_MAX];
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115
116
117 const unsigned int *reg_offsets;
118};
119#define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
120
121struct adreno_ocmem {
122 struct ocmem *ocmem;
123 unsigned long base;
124 void *hdl;
125};
126
127
128struct adreno_platform_config {
129 struct adreno_rev rev;
130};
131
132#define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
133
134#define spin_until(X) ({ \
135 int __ret = -ETIMEDOUT; \
136 unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
137 do { \
138 if (X) { \
139 __ret = 0; \
140 break; \
141 } \
142 } while (time_before(jiffies, __t)); \
143 __ret; \
144})
145
146bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2);
147
148static inline bool adreno_is_a2xx(struct adreno_gpu *gpu)
149{
150 return (gpu->revn < 300);
151}
152
153static inline bool adreno_is_a20x(struct adreno_gpu *gpu)
154{
155 return (gpu->revn < 210);
156}
157
158static inline bool adreno_is_a225(struct adreno_gpu *gpu)
159{
160 return gpu->revn == 225;
161}
162
163static inline bool adreno_is_a305(struct adreno_gpu *gpu)
164{
165 return gpu->revn == 305;
166}
167
168static inline bool adreno_is_a306(struct adreno_gpu *gpu)
169{
170
171 return gpu->revn == 307;
172}
173
174static inline bool adreno_is_a320(struct adreno_gpu *gpu)
175{
176 return gpu->revn == 320;
177}
178
179static inline bool adreno_is_a330(struct adreno_gpu *gpu)
180{
181 return gpu->revn == 330;
182}
183
184static inline bool adreno_is_a330v2(struct adreno_gpu *gpu)
185{
186 return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
187}
188
189static inline int adreno_is_a405(struct adreno_gpu *gpu)
190{
191 return gpu->revn == 405;
192}
193
194static inline int adreno_is_a420(struct adreno_gpu *gpu)
195{
196 return gpu->revn == 420;
197}
198
199static inline int adreno_is_a430(struct adreno_gpu *gpu)
200{
201 return gpu->revn == 430;
202}
203
204static inline int adreno_is_a508(struct adreno_gpu *gpu)
205{
206 return gpu->revn == 508;
207}
208
209static inline int adreno_is_a509(struct adreno_gpu *gpu)
210{
211 return gpu->revn == 509;
212}
213
214static inline int adreno_is_a510(struct adreno_gpu *gpu)
215{
216 return gpu->revn == 510;
217}
218
219static inline int adreno_is_a512(struct adreno_gpu *gpu)
220{
221 return gpu->revn == 512;
222}
223
224static inline int adreno_is_a530(struct adreno_gpu *gpu)
225{
226 return gpu->revn == 530;
227}
228
229static inline int adreno_is_a540(struct adreno_gpu *gpu)
230{
231 return gpu->revn == 540;
232}
233
234static inline int adreno_is_a618(struct adreno_gpu *gpu)
235{
236 return gpu->revn == 618;
237}
238
239static inline int adreno_is_a630(struct adreno_gpu *gpu)
240{
241 return gpu->revn == 630;
242}
243
244static inline int adreno_is_a640_family(struct adreno_gpu *gpu)
245{
246 return (gpu->revn == 640) || (gpu->revn == 680);
247}
248
249static inline int adreno_is_a650(struct adreno_gpu *gpu)
250{
251 return gpu->revn == 650;
252}
253
254static inline int adreno_is_7c3(struct adreno_gpu *gpu)
255{
256
257 return adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), gpu->rev);
258}
259
260static inline int adreno_is_a660(struct adreno_gpu *gpu)
261{
262 return gpu->revn == 660;
263}
264
265static inline int adreno_is_a660_family(struct adreno_gpu *gpu)
266{
267 return adreno_is_a660(gpu) || adreno_is_7c3(gpu);
268}
269
270
271static inline int adreno_is_a650_family(struct adreno_gpu *gpu)
272{
273 return gpu->revn == 650 || gpu->revn == 620 ||
274 adreno_is_a660_family(gpu);
275}
276
277int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
278const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
279 const char *fwname);
280struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
281 const struct firmware *fw, u64 *iova);
282int adreno_hw_init(struct msm_gpu *gpu);
283void adreno_recover(struct msm_gpu *gpu);
284void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg);
285bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
286#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
287void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
288 struct drm_printer *p);
289#endif
290void adreno_dump_info(struct msm_gpu *gpu);
291void adreno_dump(struct msm_gpu *gpu);
292void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords);
293struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu);
294
295int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
296 struct adreno_ocmem *ocmem);
297void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *ocmem);
298
299int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
300 struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
301 int nr_rings);
302void adreno_gpu_cleanup(struct adreno_gpu *gpu);
303int adreno_load_fw(struct adreno_gpu *adreno_gpu);
304
305void adreno_gpu_state_destroy(struct msm_gpu_state *state);
306
307int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state);
308int adreno_gpu_state_put(struct msm_gpu_state *state);
309
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312
313
314struct msm_gem_address_space *
315adreno_iommu_create_address_space(struct msm_gpu *gpu,
316 struct platform_device *pdev);
317
318void adreno_set_llc_attributes(struct iommu_domain *iommu);
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323
324int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid);
325
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327
328static inline void
329OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
330{
331 adreno_wait_ring(ring, cnt+1);
332 OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
333}
334
335
336static inline void
337OUT_PKT2(struct msm_ringbuffer *ring)
338{
339 adreno_wait_ring(ring, 1);
340 OUT_RING(ring, CP_TYPE2_PKT);
341}
342
343static inline void
344OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
345{
346 adreno_wait_ring(ring, cnt+1);
347 OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
348}
349
350static inline u32 PM4_PARITY(u32 val)
351{
352 return (0x9669 >> (0xF & (val ^
353 (val >> 4) ^ (val >> 8) ^ (val >> 12) ^
354 (val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^
355 (val >> 28)))) & 1;
356}
357
358
359#define TYPE4_MAX_PAYLOAD 127
360
361#define PKT4(_reg, _cnt) \
362 (CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \
363 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27))
364
365static inline void
366OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
367{
368 adreno_wait_ring(ring, cnt + 1);
369 OUT_RING(ring, PKT4(regindx, cnt));
370}
371
372static inline void
373OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
374{
375 adreno_wait_ring(ring, cnt + 1);
376 OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) |
377 ((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23));
378}
379
380struct msm_gpu *a2xx_gpu_init(struct drm_device *dev);
381struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
382struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
383struct msm_gpu *a5xx_gpu_init(struct drm_device *dev);
384struct msm_gpu *a6xx_gpu_init(struct drm_device *dev);
385
386static inline uint32_t get_wptr(struct msm_ringbuffer *ring)
387{
388 return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2);
389}
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401
402#define ADRENO_PROTECT_RW(_reg, _len) \
403 ((1 << 30) | (1 << 29) | \
404 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
405
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410
411#define ADRENO_PROTECT_RDONLY(_reg, _len) \
412 ((1 << 29) \
413 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
414
415
416#define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \
417 readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \
418 interval, timeout)
419
420#endif
421