linux/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h
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   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
   3 */
   4
   5#ifndef _DPU_CORE_PERF_H_
   6#define _DPU_CORE_PERF_H_
   7
   8#include <linux/types.h>
   9#include <linux/dcache.h>
  10#include <linux/mutex.h>
  11#include <drm/drm_crtc.h>
  12
  13#include "dpu_hw_catalog.h"
  14
  15#define DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE      412500000
  16
  17/**
  18 * enum dpu_core_perf_data_bus_id - data bus identifier
  19 * @DPU_CORE_PERF_DATA_BUS_ID_MNOC: DPU/MNOC data bus
  20 * @DPU_CORE_PERF_DATA_BUS_ID_LLCC: MNOC/LLCC data bus
  21 * @DPU_CORE_PERF_DATA_BUS_ID_EBI: LLCC/EBI data bus
  22 */
  23enum dpu_core_perf_data_bus_id {
  24        DPU_CORE_PERF_DATA_BUS_ID_MNOC,
  25        DPU_CORE_PERF_DATA_BUS_ID_LLCC,
  26        DPU_CORE_PERF_DATA_BUS_ID_EBI,
  27        DPU_CORE_PERF_DATA_BUS_ID_MAX,
  28};
  29
  30/**
  31 * struct dpu_core_perf_params - definition of performance parameters
  32 * @max_per_pipe_ib: maximum instantaneous bandwidth request
  33 * @bw_ctl: arbitrated bandwidth request
  34 * @core_clk_rate: core clock rate request
  35 */
  36struct dpu_core_perf_params {
  37        u64 max_per_pipe_ib;
  38        u64 bw_ctl;
  39        u64 core_clk_rate;
  40};
  41
  42/**
  43 * struct dpu_core_perf_tune - definition of performance tuning control
  44 * @mode: performance mode
  45 * @min_core_clk: minimum core clock
  46 * @min_bus_vote: minimum bus vote
  47 */
  48struct dpu_core_perf_tune {
  49        u32 mode;
  50        u64 min_core_clk;
  51        u64 min_bus_vote;
  52};
  53
  54/**
  55 * struct dpu_core_perf - definition of core performance context
  56 * @dev: Pointer to drm device
  57 * @debugfs_root: top level debug folder
  58 * @catalog: Pointer to catalog configuration
  59 * @core_clk: Pointer to core clock structure
  60 * @core_clk_rate: current core clock rate
  61 * @max_core_clk_rate: maximum allowable core clock rate
  62 * @perf_tune: debug control for performance tuning
  63 * @enable_bw_release: debug control for bandwidth release
  64 * @fix_core_clk_rate: fixed core clock request in Hz used in mode 2
  65 * @fix_core_ib_vote: fixed core ib vote in bps used in mode 2
  66 * @fix_core_ab_vote: fixed core ab vote in bps used in mode 2
  67 */
  68struct dpu_core_perf {
  69        struct drm_device *dev;
  70        struct dentry *debugfs_root;
  71        struct dpu_mdss_cfg *catalog;
  72        struct dss_clk *core_clk;
  73        u64 core_clk_rate;
  74        u64 max_core_clk_rate;
  75        struct dpu_core_perf_tune perf_tune;
  76        u32 enable_bw_release;
  77        u64 fix_core_clk_rate;
  78        u64 fix_core_ib_vote;
  79        u64 fix_core_ab_vote;
  80};
  81
  82/**
  83 * dpu_core_perf_crtc_check - validate performance of the given crtc state
  84 * @crtc: Pointer to crtc
  85 * @state: Pointer to new crtc state
  86 * return: zero if success, or error code otherwise
  87 */
  88int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
  89                struct drm_crtc_state *state);
  90
  91/**
  92 * dpu_core_perf_crtc_update - update performance of the given crtc
  93 * @crtc: Pointer to crtc
  94 * @params_changed: true if crtc parameters are modified
  95 * @stop_req: true if this is a stop request
  96 * return: zero if success, or error code otherwise
  97 */
  98int dpu_core_perf_crtc_update(struct drm_crtc *crtc,
  99                int params_changed, bool stop_req);
 100
 101/**
 102 * dpu_core_perf_crtc_release_bw - release bandwidth of the given crtc
 103 * @crtc: Pointer to crtc
 104 */
 105void dpu_core_perf_crtc_release_bw(struct drm_crtc *crtc);
 106
 107/**
 108 * dpu_core_perf_destroy - destroy the given core performance context
 109 * @perf: Pointer to core performance context
 110 */
 111void dpu_core_perf_destroy(struct dpu_core_perf *perf);
 112
 113/**
 114 * dpu_core_perf_init - initialize the given core performance context
 115 * @perf: Pointer to core performance context
 116 * @dev: Pointer to drm device
 117 * @catalog: Pointer to catalog
 118 * @core_clk: pointer to core clock
 119 */
 120int dpu_core_perf_init(struct dpu_core_perf *perf,
 121                struct drm_device *dev,
 122                struct dpu_mdss_cfg *catalog,
 123                struct dss_clk *core_clk);
 124
 125struct dpu_kms;
 126
 127/**
 128 * dpu_core_perf_debugfs_init - initialize debugfs for core performance context
 129 * @dpu_kms: Pointer to the dpu_kms struct
 130 * @debugfs_parent: Pointer to parent debugfs
 131 */
 132int dpu_core_perf_debugfs_init(struct dpu_kms *dpu_kms, struct dentry *parent);
 133
 134#endif /* _DPU_CORE_PERF_H_ */
 135