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5#ifndef _DPU_HW_INTF_H
6#define _DPU_HW_INTF_H
7
8#include "dpu_hw_catalog.h"
9#include "dpu_hw_mdss.h"
10#include "dpu_hw_util.h"
11#include "dpu_hw_blk.h"
12
13struct dpu_hw_intf;
14
15
16struct intf_timing_params {
17 u32 width;
18 u32 height;
19 u32 xres;
20 u32 yres;
21
22 u32 h_back_porch;
23 u32 h_front_porch;
24 u32 v_back_porch;
25 u32 v_front_porch;
26 u32 hsync_pulse_width;
27 u32 vsync_pulse_width;
28 u32 hsync_polarity;
29 u32 vsync_polarity;
30 u32 border_clr;
31 u32 underflow_clr;
32 u32 hsync_skew;
33};
34
35struct intf_prog_fetch {
36 u8 enable;
37
38 u32 fetch_start;
39};
40
41struct intf_status {
42 u8 is_en;
43 u8 is_prog_fetch_en;
44 u32 frame_count;
45 u32 line_count;
46};
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58
59struct dpu_hw_intf_ops {
60 void (*setup_timing_gen)(struct dpu_hw_intf *intf,
61 const struct intf_timing_params *p,
62 const struct dpu_format *fmt);
63
64 void (*setup_prg_fetch)(struct dpu_hw_intf *intf,
65 const struct intf_prog_fetch *fetch);
66
67 void (*enable_timing)(struct dpu_hw_intf *intf,
68 u8 enable);
69
70 void (*get_status)(struct dpu_hw_intf *intf,
71 struct intf_status *status);
72
73 u32 (*get_line_count)(struct dpu_hw_intf *intf);
74
75 void (*bind_pingpong_blk)(struct dpu_hw_intf *intf,
76 bool enable,
77 const enum dpu_pingpong pp);
78};
79
80struct dpu_hw_intf {
81 struct dpu_hw_blk base;
82 struct dpu_hw_blk_reg_map hw;
83
84
85 enum dpu_intf idx;
86 const struct dpu_intf_cfg *cap;
87 const struct dpu_mdss_cfg *mdss;
88
89
90 struct dpu_hw_intf_ops ops;
91};
92
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96
97
98static inline struct dpu_hw_intf *to_dpu_hw_intf(struct dpu_hw_blk *hw)
99{
100 return container_of(hw, struct dpu_hw_intf, base);
101}
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110struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx,
111 void __iomem *addr,
112 const struct dpu_mdss_cfg *m);
113
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116
117
118void dpu_hw_intf_destroy(struct dpu_hw_intf *intf);
119
120#endif
121