LXR linux/drivers/gpu/drm/msm/disp/dpu1/dpu_hw

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
   3 */
   4
   5#ifndef _DPU_HW_MDSS_H
   6#define _DPU_HW_MDSS_H
   7
   8#include <linux/kernel.h>
   9#include <linux/err.h>
  10
  11#include "msm_drv.h"
  12
  13#define DPU_DBG_NAME                    "dpu"
  14
  15#define DPU_NONE                        0
  16
  17#ifndef DPU_CSC_MATRIX_COEFF_SIZE
  18#define DPU_CSC_MATRIX_COEFF_SIZE       9
  19#endif
  20
  21#ifndef DPU_CSC_CLAMP_SIZE
  22#define DPU_CSC_CLAMP_SIZE              6
  23#endif
  24
  25#ifndef DPU_CSC_BIAS_SIZE
  26#define DPU_CSC_BIAS_SIZE               3
  27#endif
  28
  29#ifndef DPU_MAX_PLANES
  30#define DPU_MAX_PLANES                  4
  31#endif
  32
  33#define PIPES_PER_STAGE                 2
  34#ifndef DPU_MAX_DE_CURVES
  35#define DPU_MAX_DE_CURVES               3
  36#endif
  37
  38enum dpu_format_flags {
  39        DPU_FORMAT_FLAG_YUV_BIT,
  40        DPU_FORMAT_FLAG_DX_BIT,
  41        DPU_FORMAT_FLAG_COMPRESSED_BIT,
  42        DPU_FORMAT_FLAG_BIT_MAX,
  43};
  44
  45#define DPU_FORMAT_FLAG_YUV             BIT(DPU_FORMAT_FLAG_YUV_BIT)
  46#define DPU_FORMAT_FLAG_DX              BIT(DPU_FORMAT_FLAG_DX_BIT)
  47#define DPU_FORMAT_FLAG_COMPRESSED      BIT(DPU_FORMAT_FLAG_COMPRESSED_BIT)
  48#define DPU_FORMAT_IS_YUV(X)            \
  49        (test_bit(DPU_FORMAT_FLAG_YUV_BIT, (X)->flag))
  50#define DPU_FORMAT_IS_DX(X)             \
  51        (test_bit(DPU_FORMAT_FLAG_DX_BIT, (X)->flag))
  52#define DPU_FORMAT_IS_LINEAR(X)         ((X)->fetch_mode == DPU_FETCH_LINEAR)
  53#define DPU_FORMAT_IS_TILE(X) \
  54        (((X)->fetch_mode == DPU_FETCH_UBWC) && \
  55                        !test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag))
  56#define DPU_FORMAT_IS_UBWC(X) \
  57        (((X)->fetch_mode == DPU_FETCH_UBWC) && \
  58                        test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag))
  59
  60#define DPU_BLEND_FG_ALPHA_FG_CONST     (0 << 0)
  61#define DPU_BLEND_FG_ALPHA_BG_CONST     (1 << 0)
  62#define DPU_BLEND_FG_ALPHA_FG_PIXEL     (2 << 0)
  63#define DPU_BLEND_FG_ALPHA_BG_PIXEL     (3 << 0)
  64#define DPU_BLEND_FG_INV_ALPHA          (1 << 2)
  65#define DPU_BLEND_FG_MOD_ALPHA          (1 << 3)
  66#define DPU_BLEND_FG_INV_MOD_ALPHA      (1 << 4)
  67#define DPU_BLEND_FG_TRANSP_EN          (1 << 5)
  68#define DPU_BLEND_BG_ALPHA_FG_CONST     (0 << 8)
  69#define DPU_BLEND_BG_ALPHA_BG_CONST     (1 << 8)
  70#define DPU_BLEND_BG_ALPHA_FG_PIXEL     (2 << 8)
  71#define DPU_BLEND_BG_ALPHA_BG_PIXEL     (3 << 8)
  72#define DPU_BLEND_BG_INV_ALPHA          (1 << 10)
  73#define DPU_BLEND_BG_MOD_ALPHA          (1 << 11)
  74#define DPU_BLEND_BG_INV_MOD_ALPHA      (1 << 12)
  75#define DPU_BLEND_BG_TRANSP_EN          (1 << 13)
  76
  77#define DPU_VSYNC0_SOURCE_GPIO          0
  78#define DPU_VSYNC1_SOURCE_GPIO          1
  79#define DPU_VSYNC2_SOURCE_GPIO          2
  80#define DPU_VSYNC_SOURCE_INTF_0         3
  81#define DPU_VSYNC_SOURCE_INTF_1         4
  82#define DPU_VSYNC_SOURCE_INTF_2         5
  83#define DPU_VSYNC_SOURCE_INTF_3         6
  84#define DPU_VSYNC_SOURCE_WD_TIMER_4     11
  85#define DPU_VSYNC_SOURCE_WD_TIMER_3     12
  86#define DPU_VSYNC_SOURCE_WD_TIMER_2     13
  87#define DPU_VSYNC_SOURCE_WD_TIMER_1     14
  88#define DPU_VSYNC_SOURCE_WD_TIMER_0     15
  89
  90enum dpu_hw_blk_type {
  91        DPU_HW_BLK_TOP = 0,
  92        DPU_HW_BLK_SSPP,
  93        DPU_HW_BLK_LM,
  94        DPU_HW_BLK_CTL,
  95        DPU_HW_BLK_PINGPONG,
  96        DPU_HW_BLK_INTF,
  97        DPU_HW_BLK_WB,
  98        DPU_HW_BLK_DSPP,
  99        DPU_HW_BLK_MERGE_3D,
 100        DPU_HW_BLK_MAX,
 101};
 102
 103enum dpu_mdp {
 104        MDP_TOP = 0x1,
 105        MDP_MAX,
 106};
 107
 108enum dpu_sspp {
 109        SSPP_NONE,
 110        SSPP_VIG0,
 111        SSPP_VIG1,
 112        SSPP_VIG2,
 113        SSPP_VIG3,
 114        SSPP_RGB0,
 115        SSPP_RGB1,
 116        SSPP_RGB2,
 117        SSPP_RGB3,
 118        SSPP_DMA0,
 119        SSPP_DMA1,
 120        SSPP_DMA2,
 121        SSPP_DMA3,
 122        SSPP_CURSOR0,
 123        SSPP_CURSOR1,
 124        SSPP_MAX
 125};
 126
 127enum dpu_sspp_type {
 128        SSPP_TYPE_VIG,
 129        SSPP_TYPE_RGB,
 130        SSPP_TYPE_DMA,
 131        SSPP_TYPE_CURSOR,
 132        SSPP_TYPE_MAX
 133};
 134
 135enum dpu_lm {
 136        LM_0 = 1,
 137        LM_1,
 138        LM_2,
 139        LM_3,
 140        LM_4,
 141        LM_5,
 142        LM_6,
 143        LM_MAX
 144};
 145
 146enum dpu_stage {
 147        DPU_STAGE_BASE = 0,
 148        DPU_STAGE_0,
 149        DPU_STAGE_1,
 150        DPU_STAGE_2,
 151        DPU_STAGE_3,
 152        DPU_STAGE_4,
 153        DPU_STAGE_5,
 154        DPU_STAGE_6,
 155        DPU_STAGE_7,
 156        DPU_STAGE_8,
 157        DPU_STAGE_9,
 158        DPU_STAGE_10,
 159        DPU_STAGE_MAX
 160};
 161enum dpu_dspp {
 162        DSPP_0 = 1,
 163        DSPP_1,
 164        DSPP_2,
 165        DSPP_3,
 166        DSPP_MAX
 167};
 168
 169enum dpu_ctl {
 170        CTL_0 = 1,
 171        CTL_1,
 172        CTL_2,
 173        CTL_3,
 174        CTL_4,
 175        CTL_5,
 176        CTL_MAX
 177};
 178
 179enum dpu_pingpong {
 180        PINGPONG_0 = 1,
 181        PINGPONG_1,
 182        PINGPONG_2,
 183        PINGPONG_3,
 184        PINGPONG_4,
 185        PINGPONG_5,
 186        PINGPONG_S0,
 187        PINGPONG_MAX
 188};
 189
 190enum dpu_merge_3d {
 191        MERGE_3D_0 = 1,
 192        MERGE_3D_1,
 193        MERGE_3D_2,
 194        MERGE_3D_MAX
 195};
 196
 197enum dpu_intf {
 198        INTF_0 = 1,
 199        INTF_1,
 200        INTF_2,
 201        INTF_3,
 202        INTF_4,
 203        INTF_5,
 204        INTF_6,
 205        INTF_MAX
 206};
 207
 208enum dpu_intf_type {
 209        INTF_NONE = 0x0,
 210        INTF_DSI = 0x1,
 211        INTF_HDMI = 0x3,
 212        INTF_LCDC = 0x5,
 213        INTF_EDP = 0x9,
 214        INTF_DP = 0xa,
 215        INTF_TYPE_MAX,
 216
 217        /* virtual interfaces */
 218        INTF_WB = 0x100,
 219};
 220
 221enum dpu_intf_mode {
 222        INTF_MODE_NONE = 0,
 223        INTF_MODE_CMD,
 224        INTF_MODE_VIDEO,
 225        INTF_MODE_WB_BLOCK,
 226        INTF_MODE_WB_LINE,
 227        INTF_MODE_MAX
 228};
 229
 230enum dpu_wb {
 231        WB_0 = 1,
 232        WB_1,
 233        WB_2,
 234        WB_3,
 235        WB_MAX
 236};
 237
 238enum dpu_cwb {
 239        CWB_0 = 0x1,
 240        CWB_1,
 241        CWB_2,
 242        CWB_3,
 243        CWB_MAX
 244};
 245
 246enum dpu_wd_timer {
 247        WD_TIMER_0 = 0x1,
 248        WD_TIMER_1,
 249        WD_TIMER_2,
 250        WD_TIMER_3,
 251        WD_TIMER_4,
 252        WD_TIMER_5,
 253        WD_TIMER_MAX
 254};
 255
 256enum dpu_vbif {
 257        VBIF_0,
 258        VBIF_1,
 259        VBIF_MAX,
 260        VBIF_RT = VBIF_0,
 261        VBIF_NRT = VBIF_1
 262};
 263
 264/**
 265 * DPU HW,Component order color map
 266 */
 267enum {
 268        C0_G_Y = 0,
 269        C1_B_Cb = 1,
 270        C2_R_Cr = 2,
 271        C3_ALPHA = 3
 272};
 273
 274/**
 275 * enum dpu_plane_type - defines how the color component pixel packing
 276 * @DPU_PLANE_INTERLEAVED   : Color components in single plane
 277 * @DPU_PLANE_PLANAR        : Color component in separate planes
 278 * @DPU_PLANE_PSEUDO_PLANAR : Chroma components interleaved in separate plane
 279 */
 280enum dpu_plane_type {
 281        DPU_PLANE_INTERLEAVED,
 282        DPU_PLANE_PLANAR,
 283        DPU_PLANE_PSEUDO_PLANAR,
 284};
 285
 286/**
 287 * enum dpu_chroma_samp_type - chroma sub-samplng type
 288 * @DPU_CHROMA_RGB   : No chroma subsampling
 289 * @DPU_CHROMA_H2V1  : Chroma pixels are horizontally subsampled
 290 * @DPU_CHROMA_H1V2  : Chroma pixels are vertically subsampled
 291 * @DPU_CHROMA_420   : 420 subsampling
 292 */
 293enum dpu_chroma_samp_type {
 294        DPU_CHROMA_RGB,
 295        DPU_CHROMA_H2V1,
 296        DPU_CHROMA_H1V2,
 297        DPU_CHROMA_420
 298};
 299
 300/**
 301 * dpu_fetch_type - Defines How DPU HW fetches data
 302 * @DPU_FETCH_LINEAR   : fetch is line by line
 303 * @DPU_FETCH_TILE     : fetches data in Z order from a tile
 304 * @DPU_FETCH_UBWC     : fetch and decompress data
 305 */
 306enum dpu_fetch_type {
 307        DPU_FETCH_LINEAR,
 308        DPU_FETCH_TILE,
 309        DPU_FETCH_UBWC
 310};
 311
 312/**
 313 * Value of enum chosen to fit the number of bits
 314 * expected by the HW programming.
 315 */
 316enum {
 317        COLOR_ALPHA_1BIT = 0,
 318        COLOR_ALPHA_4BIT = 1,
 319        COLOR_4BIT = 0,
 320        COLOR_5BIT = 1, /* No 5-bit Alpha */
 321        COLOR_6BIT = 2, /* 6-Bit Alpha also = 2 */
 322        COLOR_8BIT = 3, /* 8-Bit Alpha also = 3 */
 323};
 324
 325/**
 326 * enum dpu_3d_blend_mode
 327 * Desribes how the 3d data is blended
 328 * @BLEND_3D_NONE      : 3d blending not enabled
 329 * @BLEND_3D_FRAME_INT : Frame interleaving
 330 * @BLEND_3D_H_ROW_INT : Horizontal row interleaving
 331 * @BLEND_3D_V_ROW_INT : vertical row interleaving
 332 * @BLEND_3D_COL_INT   : column interleaving
 333 * @BLEND_3D_MAX       :
 334 */
 335enum dpu_3d_blend_mode {
 336        BLEND_3D_NONE = 0,
 337        BLEND_3D_FRAME_INT,
 338        BLEND_3D_H_ROW_INT,
 339        BLEND_3D_V_ROW_INT,
 340        BLEND_3D_COL_INT,
 341        BLEND_3D_MAX
 342};
 343
 344/** struct dpu_format - defines the format configuration which
 345 * allows DPU HW to correctly fetch and decode the format
 346 * @base: base msm_format structure containing fourcc code
 347 * @fetch_planes: how the color components are packed in pixel format
 348 * @element: element color ordering
 349 * @bits: element bit widths
 350 * @chroma_sample: chroma sub-samplng type
 351 * @unpack_align_msb: unpack aligned, 0 to LSB, 1 to MSB
 352 * @unpack_tight: 0 for loose, 1 for tight
 353 * @unpack_count: 0 = 1 component, 1 = 2 component
 354 * @bpp: bytes per pixel
 355 * @alpha_enable: whether the format has an alpha channel
 356 * @num_planes: number of planes (including meta data planes)
 357 * @fetch_mode: linear, tiled, or ubwc hw fetch behavior
 358 * @flag: usage bit flags
 359 * @tile_width: format tile width
 360 * @tile_height: format tile height
 361 */
 362struct dpu_format {
 363        struct msm_format base;
 364        enum dpu_plane_type fetch_planes;
 365        u8 element[DPU_MAX_PLANES];
 366        u8 bits[DPU_MAX_PLANES];
 367        enum dpu_chroma_samp_type chroma_sample;
 368        u8 unpack_align_msb;
 369        u8 unpack_tight;
 370        u8 unpack_count;
 371        u8 bpp;
 372        u8 alpha_enable;
 373        u8 num_planes;
 374        enum dpu_fetch_type fetch_mode;
 375        DECLARE_BITMAP(flag, DPU_FORMAT_FLAG_BIT_MAX);
 376        u16 tile_width;
 377        u16 tile_height;
 378};
 379#define to_dpu_format(x) container_of(x, struct dpu_format, base)
 380
 381/**
 382 * struct dpu_hw_fmt_layout - format information of the source pixel data
 383 * @format: pixel format parameters
 384 * @num_planes: number of planes (including meta data planes)
 385 * @width: image width
 386 * @height: image height
 387 * @total_size: total size in bytes
 388 * @plane_addr: address of each plane
 389 * @plane_size: length of each plane
 390 * @plane_pitch: pitch of each plane
 391 */
 392struct dpu_hw_fmt_layout {
 393        const struct dpu_format *format;
 394        uint32_t num_planes;
 395        uint32_t width;
 396        uint32_t height;
 397        uint32_t total_size;
 398        uint32_t plane_addr[DPU_MAX_PLANES];
 399        uint32_t plane_size[DPU_MAX_PLANES];
 400        uint32_t plane_pitch[DPU_MAX_PLANES];
 401};
 402
 403struct dpu_csc_cfg {
 404        /* matrix coefficients in S15.16 format */
 405        uint32_t csc_mv[DPU_CSC_MATRIX_COEFF_SIZE];
 406        uint32_t csc_pre_bv[DPU_CSC_BIAS_SIZE];
 407        uint32_t csc_post_bv[DPU_CSC_BIAS_SIZE];
 408        uint32_t csc_pre_lv[DPU_CSC_CLAMP_SIZE];
 409        uint32_t csc_post_lv[DPU_CSC_CLAMP_SIZE];
 410};
 411
 412/**
 413 * struct dpu_mdss_color - mdss color description
 414 * color 0 : green
 415 * color 1 : blue
 416 * color 2 : red
 417 * color 3 : alpha
 418 */
 419struct dpu_mdss_color {
 420        u32 color_0;
 421        u32 color_1;
 422        u32 color_2;
 423        u32 color_3;
 424};
 425
 426/*
 427 * Define bit masks for h/w logging.
 428 */
 429#define DPU_DBG_MASK_NONE     (1 << 0)
 430#define DPU_DBG_MASK_INTF     (1 << 1)
 431#define DPU_DBG_MASK_LM       (1 << 2)
 432#define DPU_DBG_MASK_CTL      (1 << 3)
 433#define DPU_DBG_MASK_PINGPONG (1 << 4)
 434#define DPU_DBG_MASK_SSPP     (1 << 5)
 435#define DPU_DBG_MASK_WB       (1 << 6)
 436#define DPU_DBG_MASK_TOP      (1 << 7)
 437#define DPU_DBG_MASK_VBIF     (1 << 8)
 438#define DPU_DBG_MASK_ROT      (1 << 9)
 439#define DPU_DBG_MASK_DSPP     (1 << 10)
 440
 441#endif  /* _DPU_HW_MDSS_H */
 442