1
2
3
4
5#include <linux/iopoll.h>
6
7#include "dpu_hw_mdss.h"
8#include "dpu_hwio.h"
9#include "dpu_hw_catalog.h"
10#include "dpu_hw_pingpong.h"
11#include "dpu_kms.h"
12#include "dpu_trace.h"
13
14#define PP_TEAR_CHECK_EN 0x000
15#define PP_SYNC_CONFIG_VSYNC 0x004
16#define PP_SYNC_CONFIG_HEIGHT 0x008
17#define PP_SYNC_WRCOUNT 0x00C
18#define PP_VSYNC_INIT_VAL 0x010
19#define PP_INT_COUNT_VAL 0x014
20#define PP_SYNC_THRESH 0x018
21#define PP_START_POS 0x01C
22#define PP_RD_PTR_IRQ 0x020
23#define PP_WR_PTR_IRQ 0x024
24#define PP_OUT_LINE_COUNT 0x028
25#define PP_LINE_COUNT 0x02C
26#define PP_AUTOREFRESH_CONFIG 0x030
27
28#define PP_FBC_MODE 0x034
29#define PP_FBC_BUDGET_CTL 0x038
30#define PP_FBC_LOSSY_MODE 0x03C
31
32#define PP_DITHER_EN 0x000
33#define PP_DITHER_BITDEPTH 0x004
34#define PP_DITHER_MATRIX 0x008
35
36#define DITHER_DEPTH_MAP_INDEX 9
37
38static u32 dither_depth_map[DITHER_DEPTH_MAP_INDEX] = {
39 0, 0, 0, 0, 0, 0, 0, 1, 2
40};
41
42static const struct dpu_pingpong_cfg *_pingpong_offset(enum dpu_pingpong pp,
43 const struct dpu_mdss_cfg *m,
44 void __iomem *addr,
45 struct dpu_hw_blk_reg_map *b)
46{
47 int i;
48
49 for (i = 0; i < m->pingpong_count; i++) {
50 if (pp == m->pingpong[i].id) {
51 b->base_off = addr;
52 b->blk_off = m->pingpong[i].base;
53 b->length = m->pingpong[i].len;
54 b->hwversion = m->hwversion;
55 b->log_mask = DPU_DBG_MASK_PINGPONG;
56 return &m->pingpong[i];
57 }
58 }
59
60 return ERR_PTR(-EINVAL);
61}
62
63static void dpu_hw_pp_setup_dither(struct dpu_hw_pingpong *pp,
64 struct dpu_hw_dither_cfg *cfg)
65{
66 struct dpu_hw_blk_reg_map *c;
67 u32 i, base, data = 0;
68
69 c = &pp->hw;
70 base = pp->caps->sblk->dither.base;
71 if (!cfg) {
72 DPU_REG_WRITE(c, base + PP_DITHER_EN, 0);
73 return;
74 }
75
76 data = dither_depth_map[cfg->c0_bitdepth] & REG_MASK(2);
77 data |= (dither_depth_map[cfg->c1_bitdepth] & REG_MASK(2)) << 2;
78 data |= (dither_depth_map[cfg->c2_bitdepth] & REG_MASK(2)) << 4;
79 data |= (dither_depth_map[cfg->c3_bitdepth] & REG_MASK(2)) << 6;
80 data |= (cfg->temporal_en) ? (1 << 8) : 0;
81
82 DPU_REG_WRITE(c, base + PP_DITHER_BITDEPTH, data);
83
84 for (i = 0; i < DITHER_MATRIX_SZ - 3; i += 4) {
85 data = (cfg->matrix[i] & REG_MASK(4)) |
86 ((cfg->matrix[i + 1] & REG_MASK(4)) << 4) |
87 ((cfg->matrix[i + 2] & REG_MASK(4)) << 8) |
88 ((cfg->matrix[i + 3] & REG_MASK(4)) << 12);
89 DPU_REG_WRITE(c, base + PP_DITHER_MATRIX + i, data);
90 }
91 DPU_REG_WRITE(c, base + PP_DITHER_EN, 1);
92}
93
94static int dpu_hw_pp_setup_te_config(struct dpu_hw_pingpong *pp,
95 struct dpu_hw_tear_check *te)
96{
97 struct dpu_hw_blk_reg_map *c;
98 int cfg;
99
100 if (!pp || !te)
101 return -EINVAL;
102 c = &pp->hw;
103
104 cfg = BIT(19);
105 if (te->hw_vsync_mode)
106 cfg |= BIT(20);
107
108 cfg |= te->vsync_count;
109
110 DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg);
111 DPU_REG_WRITE(c, PP_SYNC_CONFIG_HEIGHT, te->sync_cfg_height);
112 DPU_REG_WRITE(c, PP_VSYNC_INIT_VAL, te->vsync_init_val);
113 DPU_REG_WRITE(c, PP_RD_PTR_IRQ, te->rd_ptr_irq);
114 DPU_REG_WRITE(c, PP_START_POS, te->start_pos);
115 DPU_REG_WRITE(c, PP_SYNC_THRESH,
116 ((te->sync_threshold_continue << 16) |
117 te->sync_threshold_start));
118 DPU_REG_WRITE(c, PP_SYNC_WRCOUNT,
119 (te->start_pos + te->sync_threshold_start + 1));
120
121 return 0;
122}
123
124static void dpu_hw_pp_setup_autorefresh_config(struct dpu_hw_pingpong *pp,
125 u32 frame_count, bool enable)
126{
127 DPU_REG_WRITE(&pp->hw, PP_AUTOREFRESH_CONFIG,
128 enable ? (BIT(31) | frame_count) : 0);
129}
130
131
132
133
134
135
136
137
138static bool dpu_hw_pp_get_autorefresh_config(struct dpu_hw_pingpong *pp,
139 u32 *frame_count)
140{
141 u32 val = DPU_REG_READ(&pp->hw, PP_AUTOREFRESH_CONFIG);
142 if (frame_count != NULL)
143 *frame_count = val & 0xffff;
144 return !!((val & BIT(31)) >> 31);
145}
146
147static int dpu_hw_pp_poll_timeout_wr_ptr(struct dpu_hw_pingpong *pp,
148 u32 timeout_us)
149{
150 struct dpu_hw_blk_reg_map *c;
151 u32 val;
152 int rc;
153
154 if (!pp)
155 return -EINVAL;
156
157 c = &pp->hw;
158 rc = readl_poll_timeout(c->base_off + c->blk_off + PP_LINE_COUNT,
159 val, (val & 0xffff) >= 1, 10, timeout_us);
160
161 return rc;
162}
163
164static int dpu_hw_pp_enable_te(struct dpu_hw_pingpong *pp, bool enable)
165{
166 struct dpu_hw_blk_reg_map *c;
167
168 if (!pp)
169 return -EINVAL;
170 c = &pp->hw;
171
172 DPU_REG_WRITE(c, PP_TEAR_CHECK_EN, enable);
173 return 0;
174}
175
176static int dpu_hw_pp_connect_external_te(struct dpu_hw_pingpong *pp,
177 bool enable_external_te)
178{
179 struct dpu_hw_blk_reg_map *c = &pp->hw;
180 u32 cfg;
181 int orig;
182
183 if (!pp)
184 return -EINVAL;
185
186 c = &pp->hw;
187 cfg = DPU_REG_READ(c, PP_SYNC_CONFIG_VSYNC);
188 orig = (bool)(cfg & BIT(20));
189 if (enable_external_te)
190 cfg |= BIT(20);
191 else
192 cfg &= ~BIT(20);
193 DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg);
194 trace_dpu_pp_connect_ext_te(pp->idx - PINGPONG_0, cfg);
195
196 return orig;
197}
198
199static int dpu_hw_pp_get_vsync_info(struct dpu_hw_pingpong *pp,
200 struct dpu_hw_pp_vsync_info *info)
201{
202 struct dpu_hw_blk_reg_map *c;
203 u32 val;
204
205 if (!pp || !info)
206 return -EINVAL;
207 c = &pp->hw;
208
209 val = DPU_REG_READ(c, PP_VSYNC_INIT_VAL);
210 info->rd_ptr_init_val = val & 0xffff;
211
212 val = DPU_REG_READ(c, PP_INT_COUNT_VAL);
213 info->rd_ptr_frame_count = (val & 0xffff0000) >> 16;
214 info->rd_ptr_line_count = val & 0xffff;
215
216 val = DPU_REG_READ(c, PP_LINE_COUNT);
217 info->wr_ptr_line_count = val & 0xffff;
218
219 return 0;
220}
221
222static u32 dpu_hw_pp_get_line_count(struct dpu_hw_pingpong *pp)
223{
224 struct dpu_hw_blk_reg_map *c = &pp->hw;
225 u32 height, init;
226 u32 line = 0xFFFF;
227
228 if (!pp)
229 return 0;
230 c = &pp->hw;
231
232 init = DPU_REG_READ(c, PP_VSYNC_INIT_VAL) & 0xFFFF;
233 height = DPU_REG_READ(c, PP_SYNC_CONFIG_HEIGHT) & 0xFFFF;
234
235 if (height < init)
236 return line;
237
238 line = DPU_REG_READ(c, PP_INT_COUNT_VAL) & 0xFFFF;
239
240 if (line < init)
241 line += (0xFFFF - init);
242 else
243 line -= init;
244
245 return line;
246}
247
248static void _setup_pingpong_ops(struct dpu_hw_pingpong *c,
249 unsigned long features)
250{
251 c->ops.setup_tearcheck = dpu_hw_pp_setup_te_config;
252 c->ops.enable_tearcheck = dpu_hw_pp_enable_te;
253 c->ops.connect_external_te = dpu_hw_pp_connect_external_te;
254 c->ops.get_vsync_info = dpu_hw_pp_get_vsync_info;
255 c->ops.setup_autorefresh = dpu_hw_pp_setup_autorefresh_config;
256 c->ops.get_autorefresh = dpu_hw_pp_get_autorefresh_config;
257 c->ops.poll_timeout_wr_ptr = dpu_hw_pp_poll_timeout_wr_ptr;
258 c->ops.get_line_count = dpu_hw_pp_get_line_count;
259
260 if (test_bit(DPU_PINGPONG_DITHER, &features))
261 c->ops.setup_dither = dpu_hw_pp_setup_dither;
262};
263
264struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx,
265 void __iomem *addr,
266 const struct dpu_mdss_cfg *m)
267{
268 struct dpu_hw_pingpong *c;
269 const struct dpu_pingpong_cfg *cfg;
270
271 c = kzalloc(sizeof(*c), GFP_KERNEL);
272 if (!c)
273 return ERR_PTR(-ENOMEM);
274
275 cfg = _pingpong_offset(idx, m, addr, &c->hw);
276 if (IS_ERR_OR_NULL(cfg)) {
277 kfree(c);
278 return ERR_PTR(-EINVAL);
279 }
280
281 c->idx = idx;
282 c->caps = cfg;
283 _setup_pingpong_ops(c, c->caps->features);
284
285 return c;
286}
287
288void dpu_hw_pingpong_destroy(struct dpu_hw_pingpong *pp)
289{
290 kfree(pp);
291}
292
