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6#include <linux/irq.h>
7#include <linux/irqchip.h>
8#include <linux/irqdesc.h>
9#include <linux/irqchip/chained_irq.h>
10#include "dpu_kms.h"
11
12#define to_dpu_mdss(x) container_of(x, struct dpu_mdss, base)
13
14#define HW_REV 0x0
15#define HW_INTR_STATUS 0x0010
16
17#define UBWC_STATIC 0x144
18#define UBWC_CTRL_2 0x150
19#define UBWC_PREDICTION_MODE 0x154
20
21
22#define MAX_BW 6800000
23
24struct dpu_irq_controller {
25 unsigned long enabled_mask;
26 struct irq_domain *domain;
27};
28
29struct dpu_mdss {
30 struct msm_mdss base;
31 void __iomem *mmio;
32 struct dss_module_power mp;
33 struct dpu_irq_controller irq_controller;
34};
35
36static void dpu_mdss_irq(struct irq_desc *desc)
37{
38 struct dpu_mdss *dpu_mdss = irq_desc_get_handler_data(desc);
39 struct irq_chip *chip = irq_desc_get_chip(desc);
40 u32 interrupts;
41
42 chained_irq_enter(chip, desc);
43
44 interrupts = readl_relaxed(dpu_mdss->mmio + HW_INTR_STATUS);
45
46 while (interrupts) {
47 irq_hw_number_t hwirq = fls(interrupts) - 1;
48 int rc;
49
50 rc = generic_handle_domain_irq(dpu_mdss->irq_controller.domain,
51 hwirq);
52 if (rc < 0) {
53 DRM_ERROR("handle irq fail: irq=%lu rc=%d\n",
54 hwirq, rc);
55 break;
56 }
57
58 interrupts &= ~(1 << hwirq);
59 }
60
61 chained_irq_exit(chip, desc);
62}
63
64static void dpu_mdss_irq_mask(struct irq_data *irqd)
65{
66 struct dpu_mdss *dpu_mdss = irq_data_get_irq_chip_data(irqd);
67
68
69 smp_mb__before_atomic();
70 clear_bit(irqd->hwirq, &dpu_mdss->irq_controller.enabled_mask);
71
72 smp_mb__after_atomic();
73}
74
75static void dpu_mdss_irq_unmask(struct irq_data *irqd)
76{
77 struct dpu_mdss *dpu_mdss = irq_data_get_irq_chip_data(irqd);
78
79
80 smp_mb__before_atomic();
81 set_bit(irqd->hwirq, &dpu_mdss->irq_controller.enabled_mask);
82
83 smp_mb__after_atomic();
84}
85
86static struct irq_chip dpu_mdss_irq_chip = {
87 .name = "dpu_mdss",
88 .irq_mask = dpu_mdss_irq_mask,
89 .irq_unmask = dpu_mdss_irq_unmask,
90};
91
92static struct lock_class_key dpu_mdss_lock_key, dpu_mdss_request_key;
93
94static int dpu_mdss_irqdomain_map(struct irq_domain *domain,
95 unsigned int irq, irq_hw_number_t hwirq)
96{
97 struct dpu_mdss *dpu_mdss = domain->host_data;
98
99 irq_set_lockdep_class(irq, &dpu_mdss_lock_key, &dpu_mdss_request_key);
100 irq_set_chip_and_handler(irq, &dpu_mdss_irq_chip, handle_level_irq);
101 return irq_set_chip_data(irq, dpu_mdss);
102}
103
104static const struct irq_domain_ops dpu_mdss_irqdomain_ops = {
105 .map = dpu_mdss_irqdomain_map,
106 .xlate = irq_domain_xlate_onecell,
107};
108
109static int _dpu_mdss_irq_domain_add(struct dpu_mdss *dpu_mdss)
110{
111 struct device *dev;
112 struct irq_domain *domain;
113
114 dev = dpu_mdss->base.dev->dev;
115
116 domain = irq_domain_add_linear(dev->of_node, 32,
117 &dpu_mdss_irqdomain_ops, dpu_mdss);
118 if (!domain) {
119 DPU_ERROR("failed to add irq_domain\n");
120 return -EINVAL;
121 }
122
123 dpu_mdss->irq_controller.enabled_mask = 0;
124 dpu_mdss->irq_controller.domain = domain;
125
126 return 0;
127}
128
129static void _dpu_mdss_irq_domain_fini(struct dpu_mdss *dpu_mdss)
130{
131 if (dpu_mdss->irq_controller.domain) {
132 irq_domain_remove(dpu_mdss->irq_controller.domain);
133 dpu_mdss->irq_controller.domain = NULL;
134 }
135}
136static int dpu_mdss_enable(struct msm_mdss *mdss)
137{
138 struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
139 struct dss_module_power *mp = &dpu_mdss->mp;
140 int ret;
141
142 ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true);
143 if (ret) {
144 DPU_ERROR("clock enable failed, ret:%d\n", ret);
145 return ret;
146 }
147
148
149
150
151
152 switch (readl_relaxed(dpu_mdss->mmio + HW_REV)) {
153 case DPU_HW_VER_500:
154 case DPU_HW_VER_501:
155 writel_relaxed(0x420, dpu_mdss->mmio + UBWC_STATIC);
156 break;
157 case DPU_HW_VER_600:
158
159 writel_relaxed(0x103e, dpu_mdss->mmio + UBWC_STATIC);
160 writel_relaxed(2, dpu_mdss->mmio + UBWC_CTRL_2);
161 writel_relaxed(1, dpu_mdss->mmio + UBWC_PREDICTION_MODE);
162 break;
163 case DPU_HW_VER_620:
164 writel_relaxed(0x1e, dpu_mdss->mmio + UBWC_STATIC);
165 break;
166 case DPU_HW_VER_720:
167 writel_relaxed(0x101e, dpu_mdss->mmio + UBWC_STATIC);
168 break;
169 }
170
171 return ret;
172}
173
174static int dpu_mdss_disable(struct msm_mdss *mdss)
175{
176 struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
177 struct dss_module_power *mp = &dpu_mdss->mp;
178 int ret;
179
180 ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false);
181 if (ret)
182 DPU_ERROR("clock disable failed, ret:%d\n", ret);
183
184 return ret;
185}
186
187static void dpu_mdss_destroy(struct drm_device *dev)
188{
189 struct platform_device *pdev = to_platform_device(dev->dev);
190 struct msm_drm_private *priv = dev->dev_private;
191 struct dpu_mdss *dpu_mdss = to_dpu_mdss(priv->mdss);
192 struct dss_module_power *mp = &dpu_mdss->mp;
193 int irq;
194
195 pm_runtime_suspend(dev->dev);
196 pm_runtime_disable(dev->dev);
197 _dpu_mdss_irq_domain_fini(dpu_mdss);
198 irq = platform_get_irq(pdev, 0);
199 irq_set_chained_handler_and_data(irq, NULL, NULL);
200 msm_dss_put_clk(mp->clk_config, mp->num_clk);
201 devm_kfree(&pdev->dev, mp->clk_config);
202
203 if (dpu_mdss->mmio)
204 devm_iounmap(&pdev->dev, dpu_mdss->mmio);
205 dpu_mdss->mmio = NULL;
206 priv->mdss = NULL;
207}
208
209static const struct msm_mdss_funcs mdss_funcs = {
210 .enable = dpu_mdss_enable,
211 .disable = dpu_mdss_disable,
212 .destroy = dpu_mdss_destroy,
213};
214
215int dpu_mdss_init(struct drm_device *dev)
216{
217 struct platform_device *pdev = to_platform_device(dev->dev);
218 struct msm_drm_private *priv = dev->dev_private;
219 struct dpu_mdss *dpu_mdss;
220 struct dss_module_power *mp;
221 int ret;
222 int irq;
223
224 dpu_mdss = devm_kzalloc(dev->dev, sizeof(*dpu_mdss), GFP_KERNEL);
225 if (!dpu_mdss)
226 return -ENOMEM;
227
228 dpu_mdss->mmio = msm_ioremap(pdev, "mdss", "mdss");
229 if (IS_ERR(dpu_mdss->mmio))
230 return PTR_ERR(dpu_mdss->mmio);
231
232 DRM_DEBUG("mapped mdss address space @%pK\n", dpu_mdss->mmio);
233
234 mp = &dpu_mdss->mp;
235 ret = msm_dss_parse_clock(pdev, mp);
236 if (ret) {
237 DPU_ERROR("failed to parse clocks, ret=%d\n", ret);
238 goto clk_parse_err;
239 }
240
241 dpu_mdss->base.dev = dev;
242 dpu_mdss->base.funcs = &mdss_funcs;
243
244 ret = _dpu_mdss_irq_domain_add(dpu_mdss);
245 if (ret)
246 goto irq_domain_error;
247
248 irq = platform_get_irq(pdev, 0);
249 if (irq < 0) {
250 ret = irq;
251 goto irq_error;
252 }
253
254 irq_set_chained_handler_and_data(irq, dpu_mdss_irq,
255 dpu_mdss);
256
257 priv->mdss = &dpu_mdss->base;
258
259 pm_runtime_enable(dev->dev);
260
261 return 0;
262
263irq_error:
264 _dpu_mdss_irq_domain_fini(dpu_mdss);
265irq_domain_error:
266 msm_dss_put_clk(mp->clk_config, mp->num_clk);
267clk_parse_err:
268 devm_kfree(&pdev->dev, mp->clk_config);
269 if (dpu_mdss->mmio)
270 devm_iounmap(&pdev->dev, dpu_mdss->mmio);
271 dpu_mdss->mmio = NULL;
272 return ret;
273}
274
