LXR linux/drivers/gpu/drm/msm/disp/dpu1/dpu

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
   4 */
   5
   6#ifndef __DPU_RM_H__
   7#define __DPU_RM_H__
   8
   9#include <linux/list.h>
  10
  11#include "msm_kms.h"
  12#include "dpu_hw_top.h"
  13
  14struct dpu_global_state;
  15
  16/**
  17 * struct dpu_rm - DPU dynamic hardware resource manager
  18 * @pingpong_blks: array of pingpong hardware resources
  19 * @mixer_blks: array of layer mixer hardware resources
  20 * @ctl_blks: array of ctl hardware resources
  21 * @intf_blks: array of intf hardware resources
  22 * @dspp_blks: array of dspp hardware resources
  23 * @lm_max_width: cached layer mixer maximum width
  24 * @rm_lock: resource manager mutex
  25 */
  26struct dpu_rm {
  27        struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0];
  28        struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0];
  29        struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0];
  30        struct dpu_hw_blk *intf_blks[INTF_MAX - INTF_0];
  31        struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
  32        struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
  33
  34        uint32_t lm_max_width;
  35};
  36
  37/**
  38 * dpu_rm_init - Read hardware catalog and create reservation tracking objects
  39 *      for all HW blocks.
  40 * @rm: DPU Resource Manager handle
  41 * @cat: Pointer to hardware catalog
  42 * @mmio: mapped register io address of MDP
  43 * @Return: 0 on Success otherwise -ERROR
  44 */
  45int dpu_rm_init(struct dpu_rm *rm,
  46                struct dpu_mdss_cfg *cat,
  47                void __iomem *mmio);
  48
  49/**
  50 * dpu_rm_destroy - Free all memory allocated by dpu_rm_init
  51 * @rm: DPU Resource Manager handle
  52 * @Return: 0 on Success otherwise -ERROR
  53 */
  54int dpu_rm_destroy(struct dpu_rm *rm);
  55
  56/**
  57 * dpu_rm_reserve - Given a CRTC->Encoder->Connector display chain, analyze
  58 *      the use connections and user requirements, specified through related
  59 *      topology control properties, and reserve hardware blocks to that
  60 *      display chain.
  61 *      HW blocks can then be accessed through dpu_rm_get_* functions.
  62 *      HW Reservations should be released via dpu_rm_release_hw.
  63 * @rm: DPU Resource Manager handle
  64 * @drm_enc: DRM Encoder handle
  65 * @crtc_state: Proposed Atomic DRM CRTC State handle
  66 * @topology: Pointer to topology info for the display
  67 * @Return: 0 on Success otherwise -ERROR
  68 */
  69int dpu_rm_reserve(struct dpu_rm *rm,
  70                struct dpu_global_state *global_state,
  71                struct drm_encoder *drm_enc,
  72                struct drm_crtc_state *crtc_state,
  73                struct msm_display_topology topology);
  74
  75/**
  76 * dpu_rm_reserve - Given the encoder for the display chain, release any
  77 *      HW blocks previously reserved for that use case.
  78 * @rm: DPU Resource Manager handle
  79 * @enc: DRM Encoder handle
  80 * @Return: 0 on Success otherwise -ERROR
  81 */
  82void dpu_rm_release(struct dpu_global_state *global_state,
  83                struct drm_encoder *enc);
  84
  85/**
  86 * Get hw resources of the given type that are assigned to this encoder.
  87 */
  88int dpu_rm_get_assigned_resources(struct dpu_rm *rm,
  89        struct dpu_global_state *global_state, uint32_t enc_id,
  90        enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size);
  91#endif /* __DPU_RM_H__ */
  92
  93