1
2
3
4
5
6#define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__
7
8#include <linux/types.h>
9#include <linux/completion.h>
10#include <linux/delay.h>
11#include <linux/phy/phy.h>
12#include <linux/phy/phy-dp.h>
13#include <linux/pm_opp.h>
14#include <drm/drm_fixed.h>
15#include <drm/drm_dp_helper.h>
16#include <drm/drm_print.h>
17
18#include "dp_reg.h"
19#include "dp_ctrl.h"
20#include "dp_link.h"
21
22#define DP_KHZ_TO_HZ 1000
23#define IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES (30 * HZ / 1000)
24#define WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES (HZ / 2)
25
26#define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0)
27#define DP_CTRL_INTR_IDLE_PATTERN_SENT BIT(3)
28
29#define MR_LINK_TRAINING1 0x8
30#define MR_LINK_SYMBOL_ERM 0x80
31#define MR_LINK_PRBS7 0x100
32#define MR_LINK_CUSTOM80 0x200
33#define MR_LINK_TRAINING4 0x40
34
35enum {
36 DP_TRAINING_NONE,
37 DP_TRAINING_1,
38 DP_TRAINING_2,
39};
40
41struct dp_tu_calc_input {
42 u64 lclk;
43 u64 pclk_khz;
44 u64 hactive;
45 u64 hporch;
46 int nlanes;
47 int bpp;
48 int pixel_enc;
49 int dsc_en;
50 int async_en;
51 int fec_en;
52 int compress_ratio;
53 int num_of_dsc_slices;
54};
55
56struct dp_vc_tu_mapping_table {
57 u32 vic;
58 u8 lanes;
59 u8 lrate;
60 u8 bpp;
61 u8 valid_boundary_link;
62 u16 delay_start_link;
63 bool boundary_moderation_en;
64 u8 valid_lower_boundary_link;
65 u8 upper_boundary_count;
66 u8 lower_boundary_count;
67 u8 tu_size_minus1;
68};
69
70struct dp_ctrl_private {
71 struct dp_ctrl dp_ctrl;
72 struct device *dev;
73 struct drm_dp_aux *aux;
74 struct dp_panel *panel;
75 struct dp_link *link;
76 struct dp_power *power;
77 struct dp_parser *parser;
78 struct dp_catalog *catalog;
79
80 struct completion idle_comp;
81 struct completion video_comp;
82};
83
84static int dp_aux_link_configure(struct drm_dp_aux *aux,
85 struct dp_link_info *link)
86{
87 u8 values[2];
88 int err;
89
90 values[0] = drm_dp_link_rate_to_bw_code(link->rate);
91 values[1] = link->num_lanes;
92
93 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
94 values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
95
96 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
97 if (err < 0)
98 return err;
99
100 return 0;
101}
102
103void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl)
104{
105 struct dp_ctrl_private *ctrl;
106
107 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
108
109 reinit_completion(&ctrl->idle_comp);
110 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_PUSH_IDLE);
111
112 if (!wait_for_completion_timeout(&ctrl->idle_comp,
113 IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES))
114 pr_warn("PUSH_IDLE pattern timedout\n");
115
116 DRM_DEBUG_DP("mainlink off done\n");
117}
118
119static void dp_ctrl_config_ctrl(struct dp_ctrl_private *ctrl)
120{
121 u32 config = 0, tbd;
122 u8 *dpcd = ctrl->panel->dpcd;
123
124
125 config |= (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT);
126
127
128 if (dpcd[DP_EDP_CONFIGURATION_CAP] & DP_ALTERNATE_SCRAMBLER_RESET_CAP)
129 config |= DP_CONFIGURATION_CTRL_ASSR;
130
131 tbd = dp_link_get_test_bits_depth(ctrl->link,
132 ctrl->panel->dp_mode.bpp);
133
134 if (tbd == DP_TEST_BIT_DEPTH_UNKNOWN) {
135 pr_debug("BIT_DEPTH not set. Configure default\n");
136 tbd = DP_TEST_BIT_DEPTH_8;
137 }
138
139 config |= tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT;
140
141
142 config |= ((ctrl->link->link_params.num_lanes - 1)
143 << DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT);
144
145 if (drm_dp_enhanced_frame_cap(dpcd))
146 config |= DP_CONFIGURATION_CTRL_ENHANCED_FRAMING;
147
148 config |= DP_CONFIGURATION_CTRL_P_INTERLACED;
149
150
151 config |= DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN;
152 config |= DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK;
153
154 dp_catalog_ctrl_config_ctrl(ctrl->catalog, config);
155}
156
157static void dp_ctrl_configure_source_params(struct dp_ctrl_private *ctrl)
158{
159 u32 cc, tb;
160
161 dp_catalog_ctrl_lane_mapping(ctrl->catalog);
162 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true);
163
164 dp_ctrl_config_ctrl(ctrl);
165
166 tb = dp_link_get_test_bits_depth(ctrl->link,
167 ctrl->panel->dp_mode.bpp);
168 cc = dp_link_get_colorimetry_config(ctrl->link);
169 dp_catalog_ctrl_config_misc(ctrl->catalog, cc, tb);
170 dp_panel_timing_cfg(ctrl->panel);
171}
172
173
174
175
176
177
178struct tu_algo_data {
179 s64 lclk_fp;
180 s64 pclk_fp;
181 s64 lwidth;
182 s64 lwidth_fp;
183 s64 hbp_relative_to_pclk;
184 s64 hbp_relative_to_pclk_fp;
185 int nlanes;
186 int bpp;
187 int pixelEnc;
188 int dsc_en;
189 int async_en;
190 int bpc;
191
192 uint delay_start_link_extra_pixclk;
193 int extra_buffer_margin;
194 s64 ratio_fp;
195 s64 original_ratio_fp;
196
197 s64 err_fp;
198 s64 n_err_fp;
199 s64 n_n_err_fp;
200 int tu_size;
201 int tu_size_desired;
202 int tu_size_minus1;
203
204 int valid_boundary_link;
205 s64 resulting_valid_fp;
206 s64 total_valid_fp;
207 s64 effective_valid_fp;
208 s64 effective_valid_recorded_fp;
209 int n_tus;
210 int n_tus_per_lane;
211 int paired_tus;
212 int remainder_tus;
213 int remainder_tus_upper;
214 int remainder_tus_lower;
215 int extra_bytes;
216 int filler_size;
217 int delay_start_link;
218
219 int extra_pclk_cycles;
220 int extra_pclk_cycles_in_link_clk;
221 s64 ratio_by_tu_fp;
222 s64 average_valid2_fp;
223 int new_valid_boundary_link;
224 int remainder_symbols_exist;
225 int n_symbols;
226 s64 n_remainder_symbols_per_lane_fp;
227 s64 last_partial_tu_fp;
228 s64 TU_ratio_err_fp;
229
230 int n_tus_incl_last_incomplete_tu;
231 int extra_pclk_cycles_tmp;
232 int extra_pclk_cycles_in_link_clk_tmp;
233 int extra_required_bytes_new_tmp;
234 int filler_size_tmp;
235 int lower_filler_size_tmp;
236 int delay_start_link_tmp;
237
238 bool boundary_moderation_en;
239 int boundary_mod_lower_err;
240 int upper_boundary_count;
241 int lower_boundary_count;
242 int i_upper_boundary_count;
243 int i_lower_boundary_count;
244 int valid_lower_boundary_link;
245 int even_distribution_BF;
246 int even_distribution_legacy;
247 int even_distribution;
248 int min_hblank_violated;
249 s64 delay_start_time_fp;
250 s64 hbp_time_fp;
251 s64 hactive_time_fp;
252 s64 diff_abs_fp;
253
254 s64 ratio;
255};
256
257static int _tu_param_compare(s64 a, s64 b)
258{
259 u32 a_sign;
260 u32 b_sign;
261 s64 a_temp, b_temp, minus_1;
262
263 if (a == b)
264 return 0;
265
266 minus_1 = drm_fixp_from_fraction(-1, 1);
267
268 a_sign = (a >> 32) & 0x80000000 ? 1 : 0;
269
270 b_sign = (b >> 32) & 0x80000000 ? 1 : 0;
271
272 if (a_sign > b_sign)
273 return 2;
274 else if (b_sign > a_sign)
275 return 1;
276
277 if (!a_sign && !b_sign) {
278 if (a > b)
279 return 1;
280 else
281 return 2;
282 } else {
283 a_temp = drm_fixp_mul(a, minus_1);
284 b_temp = drm_fixp_mul(b, minus_1);
285
286 if (a_temp > b_temp)
287 return 2;
288 else
289 return 1;
290 }
291}
292
293static void dp_panel_update_tu_timings(struct dp_tu_calc_input *in,
294 struct tu_algo_data *tu)
295{
296 int nlanes = in->nlanes;
297 int dsc_num_slices = in->num_of_dsc_slices;
298 int dsc_num_bytes = 0;
299 int numerator;
300 s64 pclk_dsc_fp;
301 s64 dwidth_dsc_fp;
302 s64 hbp_dsc_fp;
303
304 int tot_num_eoc_symbols = 0;
305 int tot_num_hor_bytes = 0;
306 int tot_num_dummy_bytes = 0;
307 int dwidth_dsc_bytes = 0;
308 int eoc_bytes = 0;
309
310 s64 temp1_fp, temp2_fp, temp3_fp;
311
312 tu->lclk_fp = drm_fixp_from_fraction(in->lclk, 1);
313 tu->pclk_fp = drm_fixp_from_fraction(in->pclk_khz, 1000);
314 tu->lwidth = in->hactive;
315 tu->hbp_relative_to_pclk = in->hporch;
316 tu->nlanes = in->nlanes;
317 tu->bpp = in->bpp;
318 tu->pixelEnc = in->pixel_enc;
319 tu->dsc_en = in->dsc_en;
320 tu->async_en = in->async_en;
321 tu->lwidth_fp = drm_fixp_from_fraction(in->hactive, 1);
322 tu->hbp_relative_to_pclk_fp = drm_fixp_from_fraction(in->hporch, 1);
323
324 if (tu->pixelEnc == 420) {
325 temp1_fp = drm_fixp_from_fraction(2, 1);
326 tu->pclk_fp = drm_fixp_div(tu->pclk_fp, temp1_fp);
327 tu->lwidth_fp = drm_fixp_div(tu->lwidth_fp, temp1_fp);
328 tu->hbp_relative_to_pclk_fp =
329 drm_fixp_div(tu->hbp_relative_to_pclk_fp, 2);
330 }
331
332 if (tu->pixelEnc == 422) {
333 switch (tu->bpp) {
334 case 24:
335 tu->bpp = 16;
336 tu->bpc = 8;
337 break;
338 case 30:
339 tu->bpp = 20;
340 tu->bpc = 10;
341 break;
342 default:
343 tu->bpp = 16;
344 tu->bpc = 8;
345 break;
346 }
347 } else {
348 tu->bpc = tu->bpp/3;
349 }
350
351 if (!in->dsc_en)
352 goto fec_check;
353
354 temp1_fp = drm_fixp_from_fraction(in->compress_ratio, 100);
355 temp2_fp = drm_fixp_from_fraction(in->bpp, 1);
356 temp3_fp = drm_fixp_div(temp2_fp, temp1_fp);
357 temp2_fp = drm_fixp_mul(tu->lwidth_fp, temp3_fp);
358
359 temp1_fp = drm_fixp_from_fraction(8, 1);
360 temp3_fp = drm_fixp_div(temp2_fp, temp1_fp);
361
362 numerator = drm_fixp2int(temp3_fp);
363
364 dsc_num_bytes = numerator / dsc_num_slices;
365 eoc_bytes = dsc_num_bytes % nlanes;
366 tot_num_eoc_symbols = nlanes * dsc_num_slices;
367 tot_num_hor_bytes = dsc_num_bytes * dsc_num_slices;
368 tot_num_dummy_bytes = (nlanes - eoc_bytes) * dsc_num_slices;
369
370 if (dsc_num_bytes == 0)
371 pr_info("incorrect no of bytes per slice=%d\n", dsc_num_bytes);
372
373 dwidth_dsc_bytes = (tot_num_hor_bytes +
374 tot_num_eoc_symbols +
375 (eoc_bytes == 0 ? 0 : tot_num_dummy_bytes));
376
377 dwidth_dsc_fp = drm_fixp_from_fraction(dwidth_dsc_bytes, 3);
378
379 temp2_fp = drm_fixp_mul(tu->pclk_fp, dwidth_dsc_fp);
380 temp1_fp = drm_fixp_div(temp2_fp, tu->lwidth_fp);
381 pclk_dsc_fp = temp1_fp;
382
383 temp1_fp = drm_fixp_div(pclk_dsc_fp, tu->pclk_fp);
384 temp2_fp = drm_fixp_mul(tu->hbp_relative_to_pclk_fp, temp1_fp);
385 hbp_dsc_fp = temp2_fp;
386
387
388 tu->pclk_fp = pclk_dsc_fp;
389 tu->lwidth_fp = dwidth_dsc_fp;
390 tu->hbp_relative_to_pclk_fp = hbp_dsc_fp;
391
392fec_check:
393 if (in->fec_en) {
394 temp1_fp = drm_fixp_from_fraction(976, 1000);
395 tu->lclk_fp = drm_fixp_mul(tu->lclk_fp, temp1_fp);
396 }
397}
398
399static void _tu_valid_boundary_calc(struct tu_algo_data *tu)
400{
401 s64 temp1_fp, temp2_fp, temp, temp1, temp2;
402 int compare_result_1, compare_result_2, compare_result_3;
403
404 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
405 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
406
407 tu->new_valid_boundary_link = drm_fixp2int_ceil(temp2_fp);
408
409 temp = (tu->i_upper_boundary_count *
410 tu->new_valid_boundary_link +
411 tu->i_lower_boundary_count *
412 (tu->new_valid_boundary_link-1));
413 tu->average_valid2_fp = drm_fixp_from_fraction(temp,
414 (tu->i_upper_boundary_count +
415 tu->i_lower_boundary_count));
416
417 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
418 temp2_fp = tu->lwidth_fp;
419 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
420 temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp);
421 tu->n_tus = drm_fixp2int(temp2_fp);
422 if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000)
423 tu->n_tus += 1;
424
425 temp1_fp = drm_fixp_from_fraction(tu->n_tus, 1);
426 temp2_fp = drm_fixp_mul(temp1_fp, tu->average_valid2_fp);
427 temp1_fp = drm_fixp_from_fraction(tu->n_symbols, 1);
428 temp2_fp = temp1_fp - temp2_fp;
429 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
430 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp);
431 tu->n_remainder_symbols_per_lane_fp = temp2_fp;
432
433 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
434 tu->last_partial_tu_fp =
435 drm_fixp_div(tu->n_remainder_symbols_per_lane_fp,
436 temp1_fp);
437
438 if (tu->n_remainder_symbols_per_lane_fp != 0)
439 tu->remainder_symbols_exist = 1;
440 else
441 tu->remainder_symbols_exist = 0;
442
443 temp1_fp = drm_fixp_from_fraction(tu->n_tus, tu->nlanes);
444 tu->n_tus_per_lane = drm_fixp2int(temp1_fp);
445
446 tu->paired_tus = (int)((tu->n_tus_per_lane) /
447 (tu->i_upper_boundary_count +
448 tu->i_lower_boundary_count));
449
450 tu->remainder_tus = tu->n_tus_per_lane - tu->paired_tus *
451 (tu->i_upper_boundary_count +
452 tu->i_lower_boundary_count);
453
454 if ((tu->remainder_tus - tu->i_upper_boundary_count) > 0) {
455 tu->remainder_tus_upper = tu->i_upper_boundary_count;
456 tu->remainder_tus_lower = tu->remainder_tus -
457 tu->i_upper_boundary_count;
458 } else {
459 tu->remainder_tus_upper = tu->remainder_tus;
460 tu->remainder_tus_lower = 0;
461 }
462
463 temp = tu->paired_tus * (tu->i_upper_boundary_count *
464 tu->new_valid_boundary_link +
465 tu->i_lower_boundary_count *
466 (tu->new_valid_boundary_link - 1)) +
467 (tu->remainder_tus_upper *
468 tu->new_valid_boundary_link) +
469 (tu->remainder_tus_lower *
470 (tu->new_valid_boundary_link - 1));
471 tu->total_valid_fp = drm_fixp_from_fraction(temp, 1);
472
473 if (tu->remainder_symbols_exist) {
474 temp1_fp = tu->total_valid_fp +
475 tu->n_remainder_symbols_per_lane_fp;
476 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1);
477 temp2_fp = temp2_fp + tu->last_partial_tu_fp;
478 temp1_fp = drm_fixp_div(temp1_fp, temp2_fp);
479 } else {
480 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1);
481 temp1_fp = drm_fixp_div(tu->total_valid_fp, temp2_fp);
482 }
483 tu->effective_valid_fp = temp1_fp;
484
485 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
486 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
487 tu->n_n_err_fp = tu->effective_valid_fp - temp2_fp;
488
489 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
490 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
491 tu->n_err_fp = tu->average_valid2_fp - temp2_fp;
492
493 tu->even_distribution = tu->n_tus % tu->nlanes == 0 ? 1 : 0;
494
495 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
496 temp2_fp = tu->lwidth_fp;
497 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
498 temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp);
499
500 if (temp2_fp)
501 tu->n_tus_incl_last_incomplete_tu = drm_fixp2int_ceil(temp2_fp);
502 else
503 tu->n_tus_incl_last_incomplete_tu = 0;
504
505 temp1 = 0;
506 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
507 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
508 temp1_fp = tu->average_valid2_fp - temp2_fp;
509 temp2_fp = drm_fixp_from_fraction(tu->n_tus_incl_last_incomplete_tu, 1);
510 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
511
512 if (temp1_fp)
513 temp1 = drm_fixp2int_ceil(temp1_fp);
514
515 temp = tu->i_upper_boundary_count * tu->nlanes;
516 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
517 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
518 temp1_fp = drm_fixp_from_fraction(tu->new_valid_boundary_link, 1);
519 temp2_fp = temp1_fp - temp2_fp;
520 temp1_fp = drm_fixp_from_fraction(temp, 1);
521 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp);
522
523 if (temp2_fp)
524 temp2 = drm_fixp2int_ceil(temp2_fp);
525 else
526 temp2 = 0;
527 tu->extra_required_bytes_new_tmp = (int)(temp1 + temp2);
528
529 temp1_fp = drm_fixp_from_fraction(8, tu->bpp);
530 temp2_fp = drm_fixp_from_fraction(
531 tu->extra_required_bytes_new_tmp, 1);
532 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
533
534 if (temp1_fp)
535 tu->extra_pclk_cycles_tmp = drm_fixp2int_ceil(temp1_fp);
536 else
537 tu->extra_pclk_cycles_tmp = 0;
538
539 temp1_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles_tmp, 1);
540 temp2_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp);
541 temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp);
542
543 if (temp1_fp)
544 tu->extra_pclk_cycles_in_link_clk_tmp =
545 drm_fixp2int_ceil(temp1_fp);
546 else
547 tu->extra_pclk_cycles_in_link_clk_tmp = 0;
548
549 tu->filler_size_tmp = tu->tu_size - tu->new_valid_boundary_link;
550
551 tu->lower_filler_size_tmp = tu->filler_size_tmp + 1;
552
553 tu->delay_start_link_tmp = tu->extra_pclk_cycles_in_link_clk_tmp +
554 tu->lower_filler_size_tmp +
555 tu->extra_buffer_margin;
556
557 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link_tmp, 1);
558 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp);
559
560 compare_result_1 = _tu_param_compare(tu->n_n_err_fp, tu->diff_abs_fp);
561 if (compare_result_1 == 2)
562 compare_result_1 = 1;
563 else
564 compare_result_1 = 0;
565
566 compare_result_2 = _tu_param_compare(tu->n_n_err_fp, tu->err_fp);
567 if (compare_result_2 == 2)
568 compare_result_2 = 1;
569 else
570 compare_result_2 = 0;
571
572 compare_result_3 = _tu_param_compare(tu->hbp_time_fp,
573 tu->delay_start_time_fp);
574 if (compare_result_3 == 2)
575 compare_result_3 = 0;
576 else
577 compare_result_3 = 1;
578
579 if (((tu->even_distribution == 1) ||
580 ((tu->even_distribution_BF == 0) &&
581 (tu->even_distribution_legacy == 0))) &&
582 tu->n_err_fp >= 0 && tu->n_n_err_fp >= 0 &&
583 compare_result_2 &&
584 (compare_result_1 || (tu->min_hblank_violated == 1)) &&
585 (tu->new_valid_boundary_link - 1) > 0 &&
586 compare_result_3 &&
587 (tu->delay_start_link_tmp <= 1023)) {
588 tu->upper_boundary_count = tu->i_upper_boundary_count;
589 tu->lower_boundary_count = tu->i_lower_boundary_count;
590 tu->err_fp = tu->n_n_err_fp;
591 tu->boundary_moderation_en = true;
592 tu->tu_size_desired = tu->tu_size;
593 tu->valid_boundary_link = tu->new_valid_boundary_link;
594 tu->effective_valid_recorded_fp = tu->effective_valid_fp;
595 tu->even_distribution_BF = 1;
596 tu->delay_start_link = tu->delay_start_link_tmp;
597 } else if (tu->boundary_mod_lower_err == 0) {
598 compare_result_1 = _tu_param_compare(tu->n_n_err_fp,
599 tu->diff_abs_fp);
600 if (compare_result_1 == 2)
601 tu->boundary_mod_lower_err = 1;
602 }
603}
604
605static void _dp_ctrl_calc_tu(struct dp_tu_calc_input *in,
606 struct dp_vc_tu_mapping_table *tu_table)
607{
608 struct tu_algo_data *tu;
609 int compare_result_1, compare_result_2;
610 u64 temp = 0;
611 s64 temp_fp = 0, temp1_fp = 0, temp2_fp = 0;
612
613 s64 LCLK_FAST_SKEW_fp = drm_fixp_from_fraction(6, 10000);
614 s64 const_p49_fp = drm_fixp_from_fraction(49, 100);
615 s64 const_p56_fp = drm_fixp_from_fraction(56, 100);
616 s64 RATIO_SCALE_fp = drm_fixp_from_fraction(1001, 1000);
617
618 u8 DP_BRUTE_FORCE = 1;
619 s64 BRUTE_FORCE_THRESHOLD_fp = drm_fixp_from_fraction(1, 10);
620 uint EXTRA_PIXCLK_CYCLE_DELAY = 4;
621 uint HBLANK_MARGIN = 4;
622
623 tu = kzalloc(sizeof(*tu), GFP_KERNEL);
624 if (!tu)
625 return;
626
627 dp_panel_update_tu_timings(in, tu);
628
629 tu->err_fp = drm_fixp_from_fraction(1000, 1);
630
631 temp1_fp = drm_fixp_from_fraction(4, 1);
632 temp2_fp = drm_fixp_mul(temp1_fp, tu->lclk_fp);
633 temp_fp = drm_fixp_div(temp2_fp, tu->pclk_fp);
634 tu->extra_buffer_margin = drm_fixp2int_ceil(temp_fp);
635
636 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
637 temp2_fp = drm_fixp_mul(tu->pclk_fp, temp1_fp);
638 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
639 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp);
640 tu->ratio_fp = drm_fixp_div(temp2_fp, tu->lclk_fp);
641
642 tu->original_ratio_fp = tu->ratio_fp;
643 tu->boundary_moderation_en = false;
644 tu->upper_boundary_count = 0;
645 tu->lower_boundary_count = 0;
646 tu->i_upper_boundary_count = 0;
647 tu->i_lower_boundary_count = 0;
648 tu->valid_lower_boundary_link = 0;
649 tu->even_distribution_BF = 0;
650 tu->even_distribution_legacy = 0;
651 tu->even_distribution = 0;
652 tu->delay_start_time_fp = 0;
653
654 tu->err_fp = drm_fixp_from_fraction(1000, 1);
655 tu->n_err_fp = 0;
656 tu->n_n_err_fp = 0;
657
658 tu->ratio = drm_fixp2int(tu->ratio_fp);
659 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
660 div64_u64_rem(tu->lwidth_fp, temp1_fp, &temp2_fp);
661 if (temp2_fp != 0 &&
662 !tu->ratio && tu->dsc_en == 0) {
663 tu->ratio_fp = drm_fixp_mul(tu->ratio_fp, RATIO_SCALE_fp);
664 tu->ratio = drm_fixp2int(tu->ratio_fp);
665 if (tu->ratio)
666 tu->ratio_fp = drm_fixp_from_fraction(1, 1);
667 }
668
669 if (tu->ratio > 1)
670 tu->ratio = 1;
671
672 if (tu->ratio == 1)
673 goto tu_size_calc;
674
675 compare_result_1 = _tu_param_compare(tu->ratio_fp, const_p49_fp);
676 if (!compare_result_1 || compare_result_1 == 1)
677 compare_result_1 = 1;
678 else
679 compare_result_1 = 0;
680
681 compare_result_2 = _tu_param_compare(tu->ratio_fp, const_p56_fp);
682 if (!compare_result_2 || compare_result_2 == 2)
683 compare_result_2 = 1;
684 else
685 compare_result_2 = 0;
686
687 if (tu->dsc_en && compare_result_1 && compare_result_2) {
688 HBLANK_MARGIN += 4;
689 DRM_DEBUG_DP("Info: increase HBLANK_MARGIN to %d\n",
690 HBLANK_MARGIN);
691 }
692
693tu_size_calc:
694 for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) {
695 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
696 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
697 temp = drm_fixp2int_ceil(temp2_fp);
698 temp1_fp = drm_fixp_from_fraction(temp, 1);
699 tu->n_err_fp = temp1_fp - temp2_fp;
700
701 if (tu->n_err_fp < tu->err_fp) {
702 tu->err_fp = tu->n_err_fp;
703 tu->tu_size_desired = tu->tu_size;
704 }
705 }
706
707 tu->tu_size_minus1 = tu->tu_size_desired - 1;
708
709 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
710 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
711 tu->valid_boundary_link = drm_fixp2int_ceil(temp2_fp);
712
713 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
714 temp2_fp = tu->lwidth_fp;
715 temp2_fp = drm_fixp_mul(temp2_fp, temp1_fp);
716
717 temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1);
718 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp);
719 tu->n_tus = drm_fixp2int(temp2_fp);
720 if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000)
721 tu->n_tus += 1;
722
723 tu->even_distribution_legacy = tu->n_tus % tu->nlanes == 0 ? 1 : 0;
724 DRM_DEBUG_DP("Info: n_sym = %d, num_of_tus = %d\n",
725 tu->valid_boundary_link, tu->n_tus);
726
727 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
728 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
729 temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1);
730 temp2_fp = temp1_fp - temp2_fp;
731 temp1_fp = drm_fixp_from_fraction(tu->n_tus + 1, 1);
732 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp);
733
734 temp = drm_fixp2int(temp2_fp);
735 if (temp && temp2_fp)
736 tu->extra_bytes = drm_fixp2int_ceil(temp2_fp);
737 else
738 tu->extra_bytes = 0;
739
740 temp1_fp = drm_fixp_from_fraction(tu->extra_bytes, 1);
741 temp2_fp = drm_fixp_from_fraction(8, tu->bpp);
742 temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp);
743
744 if (temp && temp1_fp)
745 tu->extra_pclk_cycles = drm_fixp2int_ceil(temp1_fp);
746 else
747 tu->extra_pclk_cycles = drm_fixp2int(temp1_fp);
748
749 temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp);
750 temp2_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles, 1);
751 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
752
753 if (temp1_fp)
754 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int_ceil(temp1_fp);
755 else
756 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int(temp1_fp);
757
758 tu->filler_size = tu->tu_size_desired - tu->valid_boundary_link;
759
760 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
761 tu->ratio_by_tu_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
762
763 tu->delay_start_link = tu->extra_pclk_cycles_in_link_clk +
764 tu->filler_size + tu->extra_buffer_margin;
765
766 tu->resulting_valid_fp =
767 drm_fixp_from_fraction(tu->valid_boundary_link, 1);
768
769 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
770 temp2_fp = drm_fixp_div(tu->resulting_valid_fp, temp1_fp);
771 tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp;
772
773 temp1_fp = drm_fixp_from_fraction(HBLANK_MARGIN, 1);
774 temp1_fp = tu->hbp_relative_to_pclk_fp - temp1_fp;
775 tu->hbp_time_fp = drm_fixp_div(temp1_fp, tu->pclk_fp);
776
777 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1);
778 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp);
779
780 compare_result_1 = _tu_param_compare(tu->hbp_time_fp,
781 tu->delay_start_time_fp);
782 if (compare_result_1 == 2)
783 tu->min_hblank_violated = 1;
784
785 tu->hactive_time_fp = drm_fixp_div(tu->lwidth_fp, tu->pclk_fp);
786
787 compare_result_2 = _tu_param_compare(tu->hactive_time_fp,
788 tu->delay_start_time_fp);
789 if (compare_result_2 == 2)
790 tu->min_hblank_violated = 1;
791
792 tu->delay_start_time_fp = 0;
793
794
795
796 tu->delay_start_link_extra_pixclk = EXTRA_PIXCLK_CYCLE_DELAY;
797 tu->diff_abs_fp = tu->resulting_valid_fp - tu->ratio_by_tu_fp;
798
799 temp = drm_fixp2int(tu->diff_abs_fp);
800 if (!temp && tu->diff_abs_fp <= 0xffff)
801 tu->diff_abs_fp = 0;
802
803
804 if (tu->diff_abs_fp < 0)
805 tu->diff_abs_fp = drm_fixp_mul(tu->diff_abs_fp, -1);
806
807 tu->boundary_mod_lower_err = 0;
808 if ((tu->diff_abs_fp != 0 &&
809 ((tu->diff_abs_fp > BRUTE_FORCE_THRESHOLD_fp) ||
810 (tu->even_distribution_legacy == 0) ||
811 (DP_BRUTE_FORCE == 1))) ||
812 (tu->min_hblank_violated == 1)) {
813 do {
814 tu->err_fp = drm_fixp_from_fraction(1000, 1);
815
816 temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp);
817 temp2_fp = drm_fixp_from_fraction(
818 tu->delay_start_link_extra_pixclk, 1);
819 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
820
821 if (temp1_fp)
822 tu->extra_buffer_margin =
823 drm_fixp2int_ceil(temp1_fp);
824 else
825 tu->extra_buffer_margin = 0;
826
827 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
828 temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp);
829
830 if (temp1_fp)
831 tu->n_symbols = drm_fixp2int_ceil(temp1_fp);
832 else
833 tu->n_symbols = 0;
834
835 for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) {
836 for (tu->i_upper_boundary_count = 1;
837 tu->i_upper_boundary_count <= 15;
838 tu->i_upper_boundary_count++) {
839 for (tu->i_lower_boundary_count = 1;
840 tu->i_lower_boundary_count <= 15;
841 tu->i_lower_boundary_count++) {
842 _tu_valid_boundary_calc(tu);
843 }
844 }
845 }
846 tu->delay_start_link_extra_pixclk--;
847 } while (tu->boundary_moderation_en != true &&
848 tu->boundary_mod_lower_err == 1 &&
849 tu->delay_start_link_extra_pixclk != 0);
850
851 if (tu->boundary_moderation_en == true) {
852 temp1_fp = drm_fixp_from_fraction(
853 (tu->upper_boundary_count *
854 tu->valid_boundary_link +
855 tu->lower_boundary_count *
856 (tu->valid_boundary_link - 1)), 1);
857 temp2_fp = drm_fixp_from_fraction(
858 (tu->upper_boundary_count +
859 tu->lower_boundary_count), 1);
860 tu->resulting_valid_fp =
861 drm_fixp_div(temp1_fp, temp2_fp);
862
863 temp1_fp = drm_fixp_from_fraction(
864 tu->tu_size_desired, 1);
865 tu->ratio_by_tu_fp =
866 drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
867
868 tu->valid_lower_boundary_link =
869 tu->valid_boundary_link - 1;
870
871 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
872 temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp);
873 temp2_fp = drm_fixp_div(temp1_fp,
874 tu->resulting_valid_fp);
875 tu->n_tus = drm_fixp2int(temp2_fp);
876
877 tu->tu_size_minus1 = tu->tu_size_desired - 1;
878 tu->even_distribution_BF = 1;
879
880 temp1_fp =
881 drm_fixp_from_fraction(tu->tu_size_desired, 1);
882 temp2_fp =
883 drm_fixp_div(tu->resulting_valid_fp, temp1_fp);
884 tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp;
885 }
886 }
887
888 temp2_fp = drm_fixp_mul(LCLK_FAST_SKEW_fp, tu->lwidth_fp);
889
890 if (temp2_fp)
891 temp = drm_fixp2int_ceil(temp2_fp);
892 else
893 temp = 0;
894
895 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
896 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
897 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
898 temp2_fp = drm_fixp_div(temp1_fp, temp2_fp);
899 temp1_fp = drm_fixp_from_fraction(temp, 1);
900 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp);
901 temp = drm_fixp2int(temp2_fp);
902
903 if (tu->async_en)
904 tu->delay_start_link += (int)temp;
905
906 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1);
907 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp);
908
909
910 tu_table->valid_boundary_link = tu->valid_boundary_link;
911 tu_table->delay_start_link = tu->delay_start_link;
912 tu_table->boundary_moderation_en = tu->boundary_moderation_en;
913 tu_table->valid_lower_boundary_link = tu->valid_lower_boundary_link;
914 tu_table->upper_boundary_count = tu->upper_boundary_count;
915 tu_table->lower_boundary_count = tu->lower_boundary_count;
916 tu_table->tu_size_minus1 = tu->tu_size_minus1;
917
918 DRM_DEBUG_DP("TU: valid_boundary_link: %d\n",
919 tu_table->valid_boundary_link);
920 DRM_DEBUG_DP("TU: delay_start_link: %d\n",
921 tu_table->delay_start_link);
922 DRM_DEBUG_DP("TU: boundary_moderation_en: %d\n",
923 tu_table->boundary_moderation_en);
924 DRM_DEBUG_DP("TU: valid_lower_boundary_link: %d\n",
925 tu_table->valid_lower_boundary_link);
926 DRM_DEBUG_DP("TU: upper_boundary_count: %d\n",
927 tu_table->upper_boundary_count);
928 DRM_DEBUG_DP("TU: lower_boundary_count: %d\n",
929 tu_table->lower_boundary_count);
930 DRM_DEBUG_DP("TU: tu_size_minus1: %d\n", tu_table->tu_size_minus1);
931
932 kfree(tu);
933}
934
935static void dp_ctrl_calc_tu_parameters(struct dp_ctrl_private *ctrl,
936 struct dp_vc_tu_mapping_table *tu_table)
937{
938 struct dp_tu_calc_input in;
939 struct drm_display_mode *drm_mode;
940
941 drm_mode = &ctrl->panel->dp_mode.drm_mode;
942
943 in.lclk = ctrl->link->link_params.rate / 1000;
944 in.pclk_khz = drm_mode->clock;
945 in.hactive = drm_mode->hdisplay;
946 in.hporch = drm_mode->htotal - drm_mode->hdisplay;
947 in.nlanes = ctrl->link->link_params.num_lanes;
948 in.bpp = ctrl->panel->dp_mode.bpp;
949 in.pixel_enc = 444;
950 in.dsc_en = 0;
951 in.async_en = 0;
952 in.fec_en = 0;
953 in.num_of_dsc_slices = 0;
954 in.compress_ratio = 100;
955
956 _dp_ctrl_calc_tu(&in, tu_table);
957}
958
959static void dp_ctrl_setup_tr_unit(struct dp_ctrl_private *ctrl)
960{
961 u32 dp_tu = 0x0;
962 u32 valid_boundary = 0x0;
963 u32 valid_boundary2 = 0x0;
964 struct dp_vc_tu_mapping_table tu_calc_table;
965
966 dp_ctrl_calc_tu_parameters(ctrl, &tu_calc_table);
967
968 dp_tu |= tu_calc_table.tu_size_minus1;
969 valid_boundary |= tu_calc_table.valid_boundary_link;
970 valid_boundary |= (tu_calc_table.delay_start_link << 16);
971
972 valid_boundary2 |= (tu_calc_table.valid_lower_boundary_link << 1);
973 valid_boundary2 |= (tu_calc_table.upper_boundary_count << 16);
974 valid_boundary2 |= (tu_calc_table.lower_boundary_count << 20);
975
976 if (tu_calc_table.boundary_moderation_en)
977 valid_boundary2 |= BIT(0);
978
979 pr_debug("dp_tu=0x%x, valid_boundary=0x%x, valid_boundary2=0x%x\n",
980 dp_tu, valid_boundary, valid_boundary2);
981
982 dp_catalog_ctrl_update_transfer_unit(ctrl->catalog,
983 dp_tu, valid_boundary, valid_boundary2);
984}
985
986static int dp_ctrl_wait4video_ready(struct dp_ctrl_private *ctrl)
987{
988 int ret = 0;
989
990 if (!wait_for_completion_timeout(&ctrl->video_comp,
991 WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES)) {
992 DRM_ERROR("wait4video timedout\n");
993 ret = -ETIMEDOUT;
994 }
995 return ret;
996}
997
998static int dp_ctrl_update_vx_px(struct dp_ctrl_private *ctrl)
999{
1000 struct dp_link *link = ctrl->link;
1001 int ret = 0, lane, lane_cnt;
1002 u8 buf[4];
1003 u32 max_level_reached = 0;
1004 u32 voltage_swing_level = link->phy_params.v_level;
1005 u32 pre_emphasis_level = link->phy_params.p_level;
1006
1007 DRM_DEBUG_DP("voltage level: %d emphasis level: %d\n", voltage_swing_level,
1008 pre_emphasis_level);
1009 ret = dp_catalog_ctrl_update_vx_px(ctrl->catalog,
1010 voltage_swing_level, pre_emphasis_level);
1011
1012 if (ret)
1013 return ret;
1014
1015 if (voltage_swing_level >= DP_TRAIN_VOLTAGE_SWING_MAX) {
1016 DRM_DEBUG_DP("max. voltage swing level reached %d\n",
1017 voltage_swing_level);
1018 max_level_reached |= DP_TRAIN_MAX_SWING_REACHED;
1019 }
1020
1021 if (pre_emphasis_level >= DP_TRAIN_PRE_EMPHASIS_MAX) {
1022 DRM_DEBUG_DP("max. pre-emphasis level reached %d\n",
1023 pre_emphasis_level);
1024 max_level_reached |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1025 }
1026
1027 pre_emphasis_level <<= DP_TRAIN_PRE_EMPHASIS_SHIFT;
1028
1029 lane_cnt = ctrl->link->link_params.num_lanes;
1030 for (lane = 0; lane < lane_cnt; lane++)
1031 buf[lane] = voltage_swing_level | pre_emphasis_level
1032 | max_level_reached;
1033
1034 DRM_DEBUG_DP("sink: p|v=0x%x\n", voltage_swing_level
1035 | pre_emphasis_level);
1036 ret = drm_dp_dpcd_write(ctrl->aux, DP_TRAINING_LANE0_SET,
1037 buf, lane_cnt);
1038 if (ret == lane_cnt)
1039 ret = 0;
1040
1041 return ret;
1042}
1043
1044static bool dp_ctrl_train_pattern_set(struct dp_ctrl_private *ctrl,
1045 u8 pattern)
1046{
1047 u8 buf;
1048 int ret = 0;
1049
1050 DRM_DEBUG_DP("sink: pattern=%x\n", pattern);
1051
1052 buf = pattern;
1053
1054 if (pattern && pattern != DP_TRAINING_PATTERN_4)
1055 buf |= DP_LINK_SCRAMBLING_DISABLE;
1056
1057 ret = drm_dp_dpcd_writeb(ctrl->aux, DP_TRAINING_PATTERN_SET, buf);
1058 return ret == 1;
1059}
1060
1061static int dp_ctrl_read_link_status(struct dp_ctrl_private *ctrl,
1062 u8 *link_status)
1063{
1064 int ret = 0, len;
1065
1066 len = drm_dp_dpcd_read_link_status(ctrl->aux, link_status);
1067 if (len != DP_LINK_STATUS_SIZE) {
1068 DRM_ERROR("DP link status read failed, err: %d\n", len);
1069 ret = -EINVAL;
1070 }
1071
1072 return ret;
1073}
1074
1075static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl,
1076 int *training_step)
1077{
1078 int tries, old_v_level, ret = 0;
1079 u8 link_status[DP_LINK_STATUS_SIZE];
1080 int const maximum_retries = 4;
1081
1082 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1083
1084 *training_step = DP_TRAINING_1;
1085
1086 ret = dp_catalog_ctrl_set_pattern(ctrl->catalog, DP_TRAINING_PATTERN_1);
1087 if (ret)
1088 return ret;
1089 dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 |
1090 DP_LINK_SCRAMBLING_DISABLE);
1091
1092 ret = dp_ctrl_update_vx_px(ctrl);
1093 if (ret)
1094 return ret;
1095
1096 tries = 0;
1097 old_v_level = ctrl->link->phy_params.v_level;
1098 for (tries = 0; tries < maximum_retries; tries++) {
1099 drm_dp_link_train_clock_recovery_delay(ctrl->aux, ctrl->panel->dpcd);
1100
1101 ret = dp_ctrl_read_link_status(ctrl, link_status);
1102 if (ret)
1103 return ret;
1104
1105 if (drm_dp_clock_recovery_ok(link_status,
1106 ctrl->link->link_params.num_lanes)) {
1107 return 0;
1108 }
1109
1110 if (ctrl->link->phy_params.v_level >=
1111 DP_TRAIN_VOLTAGE_SWING_MAX) {
1112 DRM_ERROR_RATELIMITED("max v_level reached\n");
1113 return -EAGAIN;
1114 }
1115
1116 if (old_v_level != ctrl->link->phy_params.v_level) {
1117 tries = 0;
1118 old_v_level = ctrl->link->phy_params.v_level;
1119 }
1120
1121 DRM_DEBUG_DP("clock recovery not done, adjusting vx px\n");
1122
1123 dp_link_adjust_levels(ctrl->link, link_status);
1124 ret = dp_ctrl_update_vx_px(ctrl);
1125 if (ret)
1126 return ret;
1127 }
1128
1129 DRM_ERROR("max tries reached\n");
1130 return -ETIMEDOUT;
1131}
1132
1133static int dp_ctrl_link_rate_down_shift(struct dp_ctrl_private *ctrl)
1134{
1135 int ret = 0;
1136
1137 switch (ctrl->link->link_params.rate) {
1138 case 810000:
1139 ctrl->link->link_params.rate = 540000;
1140 break;
1141 case 540000:
1142 ctrl->link->link_params.rate = 270000;
1143 break;
1144 case 270000:
1145 ctrl->link->link_params.rate = 162000;
1146 break;
1147 case 162000:
1148 default:
1149 ret = -EINVAL;
1150 break;
1151 }
1152
1153 if (!ret)
1154 DRM_DEBUG_DP("new rate=0x%x\n", ctrl->link->link_params.rate);
1155
1156 return ret;
1157}
1158
1159static int dp_ctrl_link_lane_down_shift(struct dp_ctrl_private *ctrl)
1160{
1161
1162 if (ctrl->link->link_params.num_lanes == 1)
1163 return -1;
1164
1165 ctrl->link->link_params.num_lanes /= 2;
1166 ctrl->link->link_params.rate = ctrl->panel->link_info.rate;
1167
1168 ctrl->link->phy_params.p_level = 0;
1169 ctrl->link->phy_params.v_level = 0;
1170
1171 return 0;
1172}
1173
1174static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl)
1175{
1176 dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE);
1177 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd);
1178}
1179
1180static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl,
1181 int *training_step)
1182{
1183 int tries = 0, ret = 0;
1184 char pattern;
1185 int const maximum_retries = 5;
1186 u8 link_status[DP_LINK_STATUS_SIZE];
1187
1188 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1189
1190 *training_step = DP_TRAINING_2;
1191
1192 if (drm_dp_tps3_supported(ctrl->panel->dpcd))
1193 pattern = DP_TRAINING_PATTERN_3;
1194 else
1195 pattern = DP_TRAINING_PATTERN_2;
1196
1197 ret = dp_catalog_ctrl_set_pattern(ctrl->catalog, pattern);
1198 if (ret)
1199 return ret;
1200
1201 dp_ctrl_train_pattern_set(ctrl, pattern | DP_RECOVERED_CLOCK_OUT_EN);
1202
1203 for (tries = 0; tries <= maximum_retries; tries++) {
1204 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd);
1205
1206 ret = dp_ctrl_read_link_status(ctrl, link_status);
1207 if (ret)
1208 return ret;
1209
1210 if (drm_dp_channel_eq_ok(link_status,
1211 ctrl->link->link_params.num_lanes)) {
1212 return 0;
1213 }
1214
1215 dp_link_adjust_levels(ctrl->link, link_status);
1216 ret = dp_ctrl_update_vx_px(ctrl);
1217 if (ret)
1218 return ret;
1219
1220 }
1221
1222 return -ETIMEDOUT;
1223}
1224
1225static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl);
1226
1227static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl,
1228 int *training_step)
1229{
1230 int ret = 0;
1231 u8 encoding = DP_SET_ANSI_8B10B;
1232 struct dp_link_info link_info = {0};
1233
1234 dp_ctrl_config_ctrl(ctrl);
1235
1236 link_info.num_lanes = ctrl->link->link_params.num_lanes;
1237 link_info.rate = ctrl->link->link_params.rate;
1238 link_info.capabilities = DP_LINK_CAP_ENHANCED_FRAMING;
1239
1240 dp_aux_link_configure(ctrl->aux, &link_info);
1241 drm_dp_dpcd_write(ctrl->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
1242 &encoding, 1);
1243
1244 ret = dp_ctrl_link_train_1(ctrl, training_step);
1245 if (ret) {
1246 DRM_ERROR("link training #1 failed. ret=%d\n", ret);
1247 goto end;
1248 }
1249
1250
1251 DRM_DEBUG_DP("link training #1 successful\n");
1252
1253 ret = dp_ctrl_link_train_2(ctrl, training_step);
1254 if (ret) {
1255 DRM_ERROR("link training #2 failed. ret=%d\n", ret);
1256 goto end;
1257 }
1258
1259
1260 DRM_DEBUG_DP("link training #2 successful\n");
1261
1262end:
1263 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1264
1265 return ret;
1266}
1267
1268static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl,
1269 int *training_step)
1270{
1271 int ret = 0;
1272
1273 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true);
1274
1275 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN)
1276 return ret;
1277
1278
1279
1280
1281
1282
1283
1284 ret = dp_ctrl_link_train(ctrl, training_step);
1285
1286 return ret;
1287}
1288
1289static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl,
1290 enum dp_pm_type module, char *name, unsigned long rate)
1291{
1292 u32 num = ctrl->parser->mp[module].num_clk;
1293 struct dss_clk *cfg = ctrl->parser->mp[module].clk_config;
1294
1295 while (num && strcmp(cfg->clk_name, name)) {
1296 num--;
1297 cfg++;
1298 }
1299
1300 DRM_DEBUG_DP("setting rate=%lu on clk=%s\n", rate, name);
1301
1302 if (num)
1303 cfg->rate = rate;
1304 else
1305 DRM_ERROR("%s clock doesn't exit to set rate %lu\n",
1306 name, rate);
1307}
1308
1309static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl)
1310{
1311 int ret = 0;
1312 struct dp_io *dp_io = &ctrl->parser->io;
1313 struct phy *phy = dp_io->phy;
1314 struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
1315
1316 opts_dp->lanes = ctrl->link->link_params.num_lanes;
1317 opts_dp->link_rate = ctrl->link->link_params.rate / 100;
1318 dp_ctrl_set_clock_rate(ctrl, DP_CTRL_PM, "ctrl_link",
1319 ctrl->link->link_params.rate * 1000);
1320
1321 phy_configure(phy, &dp_io->phy_opts);
1322 phy_power_on(phy);
1323
1324 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, true);
1325 if (ret)
1326 DRM_ERROR("Unable to start link clocks. ret=%d\n", ret);
1327
1328 DRM_DEBUG_DP("link rate=%d pixel_clk=%d\n",
1329 ctrl->link->link_params.rate, ctrl->dp_ctrl.pixel_rate);
1330
1331 return ret;
1332}
1333
1334static int dp_ctrl_enable_stream_clocks(struct dp_ctrl_private *ctrl)
1335{
1336 int ret = 0;
1337
1338 dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel",
1339 ctrl->dp_ctrl.pixel_rate * 1000);
1340
1341 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true);
1342 if (ret)
1343 DRM_ERROR("Unabled to start pixel clocks. ret=%d\n", ret);
1344
1345 DRM_DEBUG_DP("link rate=%d pixel_clk=%d\n",
1346 ctrl->link->link_params.rate, ctrl->dp_ctrl.pixel_rate);
1347
1348 return ret;
1349}
1350
1351int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip, bool reset)
1352{
1353 struct dp_ctrl_private *ctrl;
1354 struct dp_io *dp_io;
1355 struct phy *phy;
1356
1357 if (!dp_ctrl) {
1358 DRM_ERROR("Invalid input data\n");
1359 return -EINVAL;
1360 }
1361
1362 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1363 dp_io = &ctrl->parser->io;
1364 phy = dp_io->phy;
1365
1366 ctrl->dp_ctrl.orientation = flip;
1367
1368 if (reset)
1369 dp_catalog_ctrl_reset(ctrl->catalog);
1370
1371 DRM_DEBUG_DP("flip=%d\n", flip);
1372 dp_catalog_ctrl_phy_reset(ctrl->catalog);
1373 phy_init(phy);
1374 dp_catalog_ctrl_enable_irq(ctrl->catalog, true);
1375
1376 return 0;
1377}
1378
1379
1380
1381
1382
1383
1384
1385
1386void dp_ctrl_host_deinit(struct dp_ctrl *dp_ctrl)
1387{
1388 struct dp_ctrl_private *ctrl;
1389 struct dp_io *dp_io;
1390 struct phy *phy;
1391
1392 if (!dp_ctrl) {
1393 DRM_ERROR("Invalid input data\n");
1394 return;
1395 }
1396
1397 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1398 dp_io = &ctrl->parser->io;
1399 phy = dp_io->phy;
1400
1401 dp_catalog_ctrl_enable_irq(ctrl->catalog, false);
1402 phy_exit(phy);
1403
1404 DRM_DEBUG_DP("Host deinitialized successfully\n");
1405}
1406
1407static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl)
1408{
1409 u8 *dpcd = ctrl->panel->dpcd;
1410
1411
1412
1413
1414
1415 if (drm_dp_is_branch(dpcd))
1416 return (drm_dp_has_quirk(&ctrl->panel->desc,
1417 DP_DPCD_QUIRK_CONSTANT_N));
1418
1419 return false;
1420}
1421
1422static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl)
1423{
1424 int ret = 0;
1425 struct dp_io *dp_io = &ctrl->parser->io;
1426 struct phy *phy = dp_io->phy;
1427 struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
1428
1429 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1430 opts_dp->lanes = ctrl->link->link_params.num_lanes;
1431 phy_configure(phy, &dp_io->phy_opts);
1432
1433
1434
1435
1436
1437 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1438 if (ret) {
1439 DRM_ERROR("Failed to disable clocks. ret=%d\n", ret);
1440 return ret;
1441 }
1442 phy_power_off(phy);
1443
1444 msleep(20);
1445
1446 ret = dp_ctrl_enable_mainlink_clocks(ctrl);
1447 if (ret) {
1448 DRM_ERROR("Failed to enable mainlink clks. ret=%d\n", ret);
1449 return ret;
1450 }
1451
1452 return ret;
1453}
1454
1455static int dp_ctrl_deinitialize_mainlink(struct dp_ctrl_private *ctrl)
1456{
1457 struct dp_io *dp_io;
1458 struct phy *phy;
1459 int ret;
1460
1461 dp_io = &ctrl->parser->io;
1462 phy = dp_io->phy;
1463
1464 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1465
1466 dp_catalog_ctrl_reset(ctrl->catalog);
1467
1468 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1469 if (ret) {
1470 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
1471 }
1472
1473 phy_power_off(phy);
1474 phy_exit(phy);
1475
1476 return 0;
1477}
1478
1479static int dp_ctrl_link_maintenance(struct dp_ctrl_private *ctrl)
1480{
1481 int ret = 0;
1482 int training_step = DP_TRAINING_NONE;
1483
1484 dp_ctrl_push_idle(&ctrl->dp_ctrl);
1485
1486 ctrl->link->phy_params.p_level = 0;
1487 ctrl->link->phy_params.v_level = 0;
1488
1489 ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
1490
1491 ret = dp_ctrl_setup_main_link(ctrl, &training_step);
1492 if (ret)
1493 goto end;
1494
1495 dp_ctrl_clear_training_pattern(ctrl);
1496
1497 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO);
1498
1499 ret = dp_ctrl_wait4video_ready(ctrl);
1500end:
1501 return ret;
1502}
1503
1504static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl)
1505{
1506 int ret = 0;
1507
1508 if (!ctrl->link->phy_params.phy_test_pattern_sel) {
1509 DRM_DEBUG_DP("no test pattern selected by sink\n");
1510 return ret;
1511 }
1512
1513
1514
1515
1516
1517
1518 ret = dp_ctrl_off_link_stream(&ctrl->dp_ctrl);
1519 if (ret) {
1520 DRM_ERROR("failed to disable DP controller\n");
1521 return ret;
1522 }
1523
1524 ret = dp_ctrl_on_link(&ctrl->dp_ctrl);
1525 if (!ret)
1526 ret = dp_ctrl_on_stream(&ctrl->dp_ctrl);
1527 else
1528 DRM_ERROR("failed to enable DP link controller\n");
1529
1530 return ret;
1531}
1532
1533static bool dp_ctrl_send_phy_test_pattern(struct dp_ctrl_private *ctrl)
1534{
1535 bool success = false;
1536 u32 pattern_sent = 0x0;
1537 u32 pattern_requested = ctrl->link->phy_params.phy_test_pattern_sel;
1538
1539 DRM_DEBUG_DP("request: 0x%x\n", pattern_requested);
1540
1541 if (dp_catalog_ctrl_update_vx_px(ctrl->catalog,
1542 ctrl->link->phy_params.v_level,
1543 ctrl->link->phy_params.p_level)) {
1544 DRM_ERROR("Failed to set v/p levels\n");
1545 return false;
1546 }
1547 dp_catalog_ctrl_send_phy_pattern(ctrl->catalog, pattern_requested);
1548 dp_ctrl_update_vx_px(ctrl);
1549 dp_link_send_test_response(ctrl->link);
1550
1551 pattern_sent = dp_catalog_ctrl_read_phy_pattern(ctrl->catalog);
1552
1553 switch (pattern_sent) {
1554 case MR_LINK_TRAINING1:
1555 success = (pattern_requested ==
1556 DP_PHY_TEST_PATTERN_D10_2);
1557 break;
1558 case MR_LINK_SYMBOL_ERM:
1559 success = ((pattern_requested ==
1560 DP_PHY_TEST_PATTERN_ERROR_COUNT) ||
1561 (pattern_requested ==
1562 DP_PHY_TEST_PATTERN_CP2520));
1563 break;
1564 case MR_LINK_PRBS7:
1565 success = (pattern_requested ==
1566 DP_PHY_TEST_PATTERN_PRBS7);
1567 break;
1568 case MR_LINK_CUSTOM80:
1569 success = (pattern_requested ==
1570 DP_PHY_TEST_PATTERN_80BIT_CUSTOM);
1571 break;
1572 case MR_LINK_TRAINING4:
1573 success = (pattern_requested ==
1574 DP_PHY_TEST_PATTERN_SEL_MASK);
1575 break;
1576 default:
1577 success = false;
1578 }
1579
1580 DRM_DEBUG_DP("%s: test->0x%x\n", success ? "success" : "failed",
1581 pattern_requested);
1582 return success;
1583}
1584
1585void dp_ctrl_handle_sink_request(struct dp_ctrl *dp_ctrl)
1586{
1587 struct dp_ctrl_private *ctrl;
1588 u32 sink_request = 0x0;
1589
1590 if (!dp_ctrl) {
1591 DRM_ERROR("invalid input\n");
1592 return;
1593 }
1594
1595 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1596 sink_request = ctrl->link->sink_request;
1597
1598 if (sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
1599 DRM_DEBUG_DP("PHY_TEST_PATTERN request\n");
1600 if (dp_ctrl_process_phy_test_request(ctrl)) {
1601 DRM_ERROR("process phy_test_req failed\n");
1602 return;
1603 }
1604 }
1605
1606 if (sink_request & DP_LINK_STATUS_UPDATED) {
1607 if (dp_ctrl_link_maintenance(ctrl)) {
1608 DRM_ERROR("LM failed: TEST_LINK_TRAINING\n");
1609 return;
1610 }
1611 }
1612
1613 if (sink_request & DP_TEST_LINK_TRAINING) {
1614 dp_link_send_test_response(ctrl->link);
1615 if (dp_ctrl_link_maintenance(ctrl)) {
1616 DRM_ERROR("LM failed: TEST_LINK_TRAINING\n");
1617 return;
1618 }
1619 }
1620}
1621
1622static bool dp_ctrl_clock_recovery_any_ok(
1623 const u8 link_status[DP_LINK_STATUS_SIZE],
1624 int lane_count)
1625{
1626 int reduced_cnt;
1627
1628 if (lane_count <= 1)
1629 return false;
1630
1631
1632
1633
1634
1635
1636 reduced_cnt = lane_count >> 1;
1637
1638 return drm_dp_clock_recovery_ok(link_status, reduced_cnt);
1639}
1640
1641static bool dp_ctrl_channel_eq_ok(struct dp_ctrl_private *ctrl)
1642{
1643 u8 link_status[DP_LINK_STATUS_SIZE];
1644 int num_lanes = ctrl->link->link_params.num_lanes;
1645
1646 dp_ctrl_read_link_status(ctrl, link_status);
1647
1648 return drm_dp_channel_eq_ok(link_status, num_lanes);
1649}
1650
1651int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl)
1652{
1653 int rc = 0;
1654 struct dp_ctrl_private *ctrl;
1655 u32 rate = 0;
1656 int link_train_max_retries = 5;
1657 u32 const phy_cts_pixel_clk_khz = 148500;
1658 u8 link_status[DP_LINK_STATUS_SIZE];
1659 unsigned int training_step;
1660
1661 if (!dp_ctrl)
1662 return -EINVAL;
1663
1664 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1665
1666 rate = ctrl->panel->link_info.rate;
1667
1668 dp_power_clk_enable(ctrl->power, DP_CORE_PM, true);
1669
1670 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
1671 DRM_DEBUG_DP("using phy test link parameters\n");
1672 if (!ctrl->panel->dp_mode.drm_mode.clock)
1673 ctrl->dp_ctrl.pixel_rate = phy_cts_pixel_clk_khz;
1674 } else {
1675 ctrl->link->link_params.rate = rate;
1676 ctrl->link->link_params.num_lanes =
1677 ctrl->panel->link_info.num_lanes;
1678 ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
1679 }
1680
1681 DRM_DEBUG_DP("rate=%d, num_lanes=%d, pixel_rate=%d\n",
1682 ctrl->link->link_params.rate,
1683 ctrl->link->link_params.num_lanes, ctrl->dp_ctrl.pixel_rate);
1684
1685 ctrl->link->phy_params.p_level = 0;
1686 ctrl->link->phy_params.v_level = 0;
1687
1688 rc = dp_ctrl_enable_mainlink_clocks(ctrl);
1689 if (rc)
1690 return rc;
1691
1692 while (--link_train_max_retries) {
1693 rc = dp_ctrl_reinitialize_mainlink(ctrl);
1694 if (rc) {
1695 DRM_ERROR("Failed to reinitialize mainlink. rc=%d\n",
1696 rc);
1697 break;
1698 }
1699
1700 training_step = DP_TRAINING_NONE;
1701 rc = dp_ctrl_setup_main_link(ctrl, &training_step);
1702 if (rc == 0) {
1703
1704 break;
1705 } else if (training_step == DP_TRAINING_1) {
1706
1707 if (!dp_catalog_link_is_connected(ctrl->catalog))
1708 break;
1709
1710 dp_ctrl_read_link_status(ctrl, link_status);
1711
1712 rc = dp_ctrl_link_rate_down_shift(ctrl);
1713 if (rc < 0) {
1714 if (dp_ctrl_clock_recovery_any_ok(link_status,
1715 ctrl->link->link_params.num_lanes)) {
1716
1717
1718
1719
1720 rc = dp_ctrl_link_lane_down_shift(ctrl);
1721 if (rc < 0) {
1722
1723 break;
1724 }
1725 } else {
1726
1727 break;
1728 }
1729 }
1730 } else if (training_step == DP_TRAINING_2) {
1731
1732 if (!dp_catalog_link_is_connected(ctrl->catalog))
1733 break;
1734
1735 dp_ctrl_read_link_status(ctrl, link_status);
1736
1737 if (!drm_dp_clock_recovery_ok(link_status,
1738 ctrl->link->link_params.num_lanes))
1739 rc = dp_ctrl_link_rate_down_shift(ctrl);
1740 else
1741 rc = dp_ctrl_link_lane_down_shift(ctrl);
1742
1743 if (rc < 0) {
1744
1745 break;
1746 }
1747 }
1748 }
1749
1750 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN)
1751 return rc;
1752
1753 if (rc == 0) {
1754
1755
1756
1757
1758
1759 } else {
1760
1761
1762
1763
1764 dp_ctrl_clear_training_pattern(ctrl);
1765
1766 dp_ctrl_deinitialize_mainlink(ctrl);
1767 rc = -ECONNRESET;
1768 }
1769
1770 return rc;
1771}
1772
1773static int dp_ctrl_link_retrain(struct dp_ctrl_private *ctrl)
1774{
1775 int training_step = DP_TRAINING_NONE;
1776
1777 return dp_ctrl_setup_main_link(ctrl, &training_step);
1778}
1779
1780int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl)
1781{
1782 int ret = 0;
1783 bool mainlink_ready = false;
1784 struct dp_ctrl_private *ctrl;
1785
1786 if (!dp_ctrl)
1787 return -EINVAL;
1788
1789 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1790
1791 ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
1792
1793 DRM_DEBUG_DP("rate=%d, num_lanes=%d, pixel_rate=%d\n",
1794 ctrl->link->link_params.rate,
1795 ctrl->link->link_params.num_lanes, ctrl->dp_ctrl.pixel_rate);
1796
1797 if (!dp_power_clk_status(ctrl->power, DP_CTRL_PM)) {
1798 ret = dp_ctrl_enable_mainlink_clocks(ctrl);
1799 if (ret) {
1800 DRM_ERROR("Failed to start link clocks. ret=%d\n", ret);
1801 goto end;
1802 }
1803 }
1804
1805 if (!dp_ctrl_channel_eq_ok(ctrl))
1806 dp_ctrl_link_retrain(ctrl);
1807
1808
1809 dp_ctrl_clear_training_pattern(ctrl);
1810
1811 ret = dp_ctrl_enable_stream_clocks(ctrl);
1812 if (ret) {
1813 DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret);
1814 goto end;
1815 }
1816
1817 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
1818 dp_ctrl_send_phy_test_pattern(ctrl);
1819 return 0;
1820 }
1821
1822
1823
1824
1825
1826 reinit_completion(&ctrl->video_comp);
1827
1828 dp_ctrl_configure_source_params(ctrl);
1829
1830 dp_catalog_ctrl_config_msa(ctrl->catalog,
1831 ctrl->link->link_params.rate,
1832 ctrl->dp_ctrl.pixel_rate, dp_ctrl_use_fixed_nvid(ctrl));
1833
1834 dp_ctrl_setup_tr_unit(ctrl);
1835
1836 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO);
1837
1838 ret = dp_ctrl_wait4video_ready(ctrl);
1839 if (ret)
1840 return ret;
1841
1842 mainlink_ready = dp_catalog_ctrl_mainlink_ready(ctrl->catalog);
1843 DRM_DEBUG_DP("mainlink %s\n", mainlink_ready ? "READY" : "NOT READY");
1844
1845end:
1846 return ret;
1847}
1848
1849int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl)
1850{
1851 struct dp_ctrl_private *ctrl;
1852 struct dp_io *dp_io;
1853 struct phy *phy;
1854 int ret;
1855
1856 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1857 dp_io = &ctrl->parser->io;
1858 phy = dp_io->phy;
1859
1860
1861 dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true);
1862
1863 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1864
1865 if (dp_power_clk_status(ctrl->power, DP_STREAM_PM)) {
1866 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false);
1867 if (ret) {
1868 DRM_ERROR("Failed to disable pclk. ret=%d\n", ret);
1869 return ret;
1870 }
1871 }
1872
1873 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1874 if (ret) {
1875 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
1876 return ret;
1877 }
1878
1879 phy_power_off(phy);
1880
1881
1882 phy_exit(phy);
1883 phy_init(phy);
1884
1885 DRM_DEBUG_DP("DP off link/stream done\n");
1886 return ret;
1887}
1888
1889void dp_ctrl_off_phy(struct dp_ctrl *dp_ctrl)
1890{
1891 struct dp_ctrl_private *ctrl;
1892 struct dp_io *dp_io;
1893 struct phy *phy;
1894
1895 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1896 dp_io = &ctrl->parser->io;
1897 phy = dp_io->phy;
1898
1899 dp_catalog_ctrl_reset(ctrl->catalog);
1900
1901 phy_exit(phy);
1902
1903 DRM_DEBUG_DP("DP off phy done\n");
1904}
1905
1906int dp_ctrl_off(struct dp_ctrl *dp_ctrl)
1907{
1908 struct dp_ctrl_private *ctrl;
1909 struct dp_io *dp_io;
1910 struct phy *phy;
1911 int ret = 0;
1912
1913 if (!dp_ctrl)
1914 return -EINVAL;
1915
1916 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1917 dp_io = &ctrl->parser->io;
1918 phy = dp_io->phy;
1919
1920 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1921
1922 dp_catalog_ctrl_reset(ctrl->catalog);
1923
1924 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false);
1925 if (ret)
1926 DRM_ERROR("Failed to disable pixel clocks. ret=%d\n", ret);
1927
1928 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1929 if (ret) {
1930 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
1931 }
1932
1933 phy_power_off(phy);
1934 phy_exit(phy);
1935
1936 DRM_DEBUG_DP("DP off done\n");
1937 return ret;
1938}
1939
1940void dp_ctrl_isr(struct dp_ctrl *dp_ctrl)
1941{
1942 struct dp_ctrl_private *ctrl;
1943 u32 isr;
1944
1945 if (!dp_ctrl)
1946 return;
1947
1948 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1949
1950 isr = dp_catalog_ctrl_get_interrupt(ctrl->catalog);
1951
1952 if (isr & DP_CTRL_INTR_READY_FOR_VIDEO) {
1953 DRM_DEBUG_DP("dp_video_ready\n");
1954 complete(&ctrl->video_comp);
1955 }
1956
1957 if (isr & DP_CTRL_INTR_IDLE_PATTERN_SENT) {
1958 DRM_DEBUG_DP("idle_patterns_sent\n");
1959 complete(&ctrl->idle_comp);
1960 }
1961}
1962
1963struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link,
1964 struct dp_panel *panel, struct drm_dp_aux *aux,
1965 struct dp_power *power, struct dp_catalog *catalog,
1966 struct dp_parser *parser)
1967{
1968 struct dp_ctrl_private *ctrl;
1969 int ret;
1970
1971 if (!dev || !panel || !aux ||
1972 !link || !catalog) {
1973 DRM_ERROR("invalid input\n");
1974 return ERR_PTR(-EINVAL);
1975 }
1976
1977 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1978 if (!ctrl) {
1979 DRM_ERROR("Mem allocation failure\n");
1980 return ERR_PTR(-ENOMEM);
1981 }
1982
1983 ret = devm_pm_opp_set_clkname(dev, "ctrl_link");
1984 if (ret) {
1985 dev_err(dev, "invalid DP OPP table in device tree\n");
1986
1987 return (struct dp_ctrl *)ERR_PTR(ret);
1988 }
1989
1990
1991 ret = devm_pm_opp_of_add_table(dev);
1992 if (ret)
1993 dev_err(dev, "failed to add DP OPP table\n");
1994
1995 init_completion(&ctrl->idle_comp);
1996 init_completion(&ctrl->video_comp);
1997
1998
1999 ctrl->parser = parser;
2000 ctrl->panel = panel;
2001 ctrl->power = power;
2002 ctrl->aux = aux;
2003 ctrl->link = link;
2004 ctrl->catalog = catalog;
2005 ctrl->dev = dev;
2006
2007 return &ctrl->dp_ctrl;
2008}
2009
