LXR linux/drivers/gpu/drm/msm/dp/dp

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
   4 */
   5
   6#ifndef _DP_PANEL_H_
   7#define _DP_PANEL_H_
   8
   9#include <drm/msm_drm.h>
  10
  11#include "dp_aux.h"
  12#include "dp_link.h"
  13#include "dp_hpd.h"
  14
  15struct edid;
  16
  17#define DPRX_EXTENDED_DPCD_FIELD        0x2200
  18
  19#define DP_DOWNSTREAM_PORTS             4
  20#define DP_DOWNSTREAM_CAP_SIZE          4
  21
  22struct dp_display_mode {
  23        struct drm_display_mode drm_mode;
  24        u32 capabilities;
  25        u32 bpp;
  26        u32 h_active_low;
  27        u32 v_active_low;
  28};
  29
  30struct dp_panel_in {
  31        struct device *dev;
  32        struct drm_dp_aux *aux;
  33        struct dp_link *link;
  34        struct dp_catalog *catalog;
  35};
  36
  37struct dp_panel {
  38        /* dpcd raw data */
  39        u8 dpcd[DP_RECEIVER_CAP_SIZE + 1];
  40        u8 ds_cap_info[DP_DOWNSTREAM_PORTS * DP_DOWNSTREAM_CAP_SIZE];
  41        u32 ds_port_cnt;
  42        u32 dfp_present;
  43
  44        struct dp_link_info link_info;
  45        struct drm_dp_desc desc;
  46        struct edid *edid;
  47        struct drm_connector *connector;
  48        struct dp_display_mode dp_mode;
  49        bool video_test;
  50
  51        u32 vic;
  52        u32 max_pclk_khz;
  53        u32 max_dp_lanes;
  54
  55        u32 max_bw_code;
  56};
  57
  58int dp_panel_init_panel_info(struct dp_panel *dp_panel);
  59int dp_panel_deinit(struct dp_panel *dp_panel);
  60int dp_panel_timing_cfg(struct dp_panel *dp_panel);
  61void dp_panel_dump_regs(struct dp_panel *dp_panel);
  62int dp_panel_read_sink_caps(struct dp_panel *dp_panel,
  63                struct drm_connector *connector);
  64u32 dp_panel_get_mode_bpp(struct dp_panel *dp_panel, u32 mode_max_bpp,
  65                        u32 mode_pclk_khz);
  66int dp_panel_get_modes(struct dp_panel *dp_panel,
  67                struct drm_connector *connector, struct dp_display_mode *mode);
  68void dp_panel_handle_sink_request(struct dp_panel *dp_panel);
  69void dp_panel_tpg_config(struct dp_panel *dp_panel, bool enable);
  70
  71/**
  72 * is_link_rate_valid() - validates the link rate
  73 * @lane_rate: link rate requested by the sink
  74 *
  75 * Returns true if the requested link rate is supported.
  76 */
  77static inline bool is_link_rate_valid(u32 bw_code)
  78{
  79        return (bw_code == DP_LINK_BW_1_62 ||
  80                bw_code == DP_LINK_BW_2_7 ||
  81                bw_code == DP_LINK_BW_5_4 ||
  82                bw_code == DP_LINK_BW_8_1);
  83}
  84
  85/**
  86 * dp_link_is_lane_count_valid() - validates the lane count
  87 * @lane_count: lane count requested by the sink
  88 *
  89 * Returns true if the requested lane count is supported.
  90 */
  91static inline bool is_lane_count_valid(u32 lane_count)
  92{
  93        return (lane_count == 1 ||
  94                lane_count == 2 ||
  95                lane_count == 4);
  96}
  97
  98struct dp_panel *dp_panel_get(struct dp_panel_in *in);
  99void dp_panel_put(struct dp_panel *dp_panel);
 100#endif /* _DP_PANEL_H_ */
 101