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6#include "dsi_cfg.h"
7
8static const char * const dsi_v2_bus_clk_names[] = {
9 "core_mmss", "iface", "bus",
10};
11
12static const struct msm_dsi_config apq8064_dsi_cfg = {
13 .io_offset = 0,
14 .reg_cfg = {
15 .num = 3,
16 .regs = {
17 {"vdda", 100000, 100},
18 {"avdd", 10000, 100},
19 {"vddio", 100000, 100},
20 },
21 },
22 .bus_clk_names = dsi_v2_bus_clk_names,
23 .num_bus_clks = ARRAY_SIZE(dsi_v2_bus_clk_names),
24 .io_start = { 0x4700000, 0x5800000 },
25 .num_dsi = 2,
26};
27
28static const char * const dsi_6g_bus_clk_names[] = {
29 "mdp_core", "iface", "bus", "core_mmss",
30};
31
32static const struct msm_dsi_config msm8974_apq8084_dsi_cfg = {
33 .io_offset = DSI_6G_REG_SHIFT,
34 .reg_cfg = {
35 .num = 3,
36 .regs = {
37 {"vdd", 150000, 100},
38 {"vdda", 100000, 100},
39 {"vddio", 100000, 100},
40 },
41 },
42 .bus_clk_names = dsi_6g_bus_clk_names,
43 .num_bus_clks = ARRAY_SIZE(dsi_6g_bus_clk_names),
44 .io_start = { 0xfd922800, 0xfd922b00 },
45 .num_dsi = 2,
46};
47
48static const char * const dsi_8916_bus_clk_names[] = {
49 "mdp_core", "iface", "bus",
50};
51
52static const struct msm_dsi_config msm8916_dsi_cfg = {
53 .io_offset = DSI_6G_REG_SHIFT,
54 .reg_cfg = {
55 .num = 2,
56 .regs = {
57 {"vdda", 100000, 100},
58 {"vddio", 100000, 100},
59 },
60 },
61 .bus_clk_names = dsi_8916_bus_clk_names,
62 .num_bus_clks = ARRAY_SIZE(dsi_8916_bus_clk_names),
63 .io_start = { 0x1a98000 },
64 .num_dsi = 1,
65};
66
67static const char * const dsi_8976_bus_clk_names[] = {
68 "mdp_core", "iface", "bus",
69};
70
71static const struct msm_dsi_config msm8976_dsi_cfg = {
72 .io_offset = DSI_6G_REG_SHIFT,
73 .reg_cfg = {
74 .num = 2,
75 .regs = {
76 {"vdda", 100000, 100},
77 {"vddio", 100000, 100},
78 },
79 },
80 .bus_clk_names = dsi_8976_bus_clk_names,
81 .num_bus_clks = ARRAY_SIZE(dsi_8976_bus_clk_names),
82 .io_start = { 0x1a94000, 0x1a96000 },
83 .num_dsi = 2,
84};
85
86static const struct msm_dsi_config msm8994_dsi_cfg = {
87 .io_offset = DSI_6G_REG_SHIFT,
88 .reg_cfg = {
89 .num = 6,
90 .regs = {
91 {"vdda", 100000, 100},
92 {"vddio", 100000, 100},
93 {"vcca", 10000, 100},
94 {"vdd", 100000, 100},
95 {"lab_reg", -1, -1},
96 {"ibb_reg", -1, -1},
97 },
98 },
99 .bus_clk_names = dsi_6g_bus_clk_names,
100 .num_bus_clks = ARRAY_SIZE(dsi_6g_bus_clk_names),
101 .io_start = { 0xfd998000, 0xfd9a0000 },
102 .num_dsi = 2,
103};
104
105static const char * const dsi_8996_bus_clk_names[] = {
106 "mdp_core", "iface", "bus", "core_mmss",
107};
108
109static const struct msm_dsi_config msm8996_dsi_cfg = {
110 .io_offset = DSI_6G_REG_SHIFT,
111 .reg_cfg = {
112 .num = 2,
113 .regs = {
114 {"vdda", 18160, 1 },
115 {"vcca", 17000, 32 },
116 {"vddio", 100000, 100 },
117 },
118 },
119 .bus_clk_names = dsi_8996_bus_clk_names,
120 .num_bus_clks = ARRAY_SIZE(dsi_8996_bus_clk_names),
121 .io_start = { 0x994000, 0x996000 },
122 .num_dsi = 2,
123};
124
125static const char * const dsi_msm8998_bus_clk_names[] = {
126 "iface", "bus", "core",
127};
128
129static const struct msm_dsi_config msm8998_dsi_cfg = {
130 .io_offset = DSI_6G_REG_SHIFT,
131 .reg_cfg = {
132 .num = 2,
133 .regs = {
134 {"vdd", 367000, 16 },
135 {"vdda", 62800, 2 },
136 },
137 },
138 .bus_clk_names = dsi_msm8998_bus_clk_names,
139 .num_bus_clks = ARRAY_SIZE(dsi_msm8998_bus_clk_names),
140 .io_start = { 0xc994000, 0xc996000 },
141 .num_dsi = 2,
142};
143
144static const char * const dsi_sdm660_bus_clk_names[] = {
145 "iface", "bus", "core", "core_mmss",
146};
147
148static const struct msm_dsi_config sdm660_dsi_cfg = {
149 .io_offset = DSI_6G_REG_SHIFT,
150 .reg_cfg = {
151 .num = 2,
152 .regs = {
153 {"vdda", 12560, 4 },
154 },
155 },
156 .bus_clk_names = dsi_sdm660_bus_clk_names,
157 .num_bus_clks = ARRAY_SIZE(dsi_sdm660_bus_clk_names),
158 .io_start = { 0xc994000, 0xc996000 },
159 .num_dsi = 2,
160};
161
162static const char * const dsi_sdm845_bus_clk_names[] = {
163 "iface", "bus",
164};
165
166static const char * const dsi_sc7180_bus_clk_names[] = {
167 "iface", "bus",
168};
169
170static const struct msm_dsi_config sdm845_dsi_cfg = {
171 .io_offset = DSI_6G_REG_SHIFT,
172 .reg_cfg = {
173 .num = 1,
174 .regs = {
175 {"vdda", 21800, 4 },
176 },
177 },
178 .bus_clk_names = dsi_sdm845_bus_clk_names,
179 .num_bus_clks = ARRAY_SIZE(dsi_sdm845_bus_clk_names),
180 .io_start = { 0xae94000, 0xae96000 },
181 .num_dsi = 2,
182};
183
184static const struct msm_dsi_config sc7180_dsi_cfg = {
185 .io_offset = DSI_6G_REG_SHIFT,
186 .reg_cfg = {
187 .num = 1,
188 .regs = {
189 {"vdda", 21800, 4 },
190 },
191 },
192 .bus_clk_names = dsi_sc7180_bus_clk_names,
193 .num_bus_clks = ARRAY_SIZE(dsi_sc7180_bus_clk_names),
194 .io_start = { 0xae94000 },
195 .num_dsi = 1,
196};
197
198static const char * const dsi_sc7280_bus_clk_names[] = {
199 "iface", "bus",
200};
201
202static const struct msm_dsi_config sc7280_dsi_cfg = {
203 .io_offset = DSI_6G_REG_SHIFT,
204 .reg_cfg = {
205 .num = 1,
206 .regs = {
207 {"vdda", 8350, 0 },
208 },
209 },
210 .bus_clk_names = dsi_sc7280_bus_clk_names,
211 .num_bus_clks = ARRAY_SIZE(dsi_sc7280_bus_clk_names),
212 .io_start = { 0xae94000 },
213 .num_dsi = 1,
214};
215
216static const struct msm_dsi_host_cfg_ops msm_dsi_v2_host_ops = {
217 .link_clk_set_rate = dsi_link_clk_set_rate_v2,
218 .link_clk_enable = dsi_link_clk_enable_v2,
219 .link_clk_disable = dsi_link_clk_disable_v2,
220 .clk_init_ver = dsi_clk_init_v2,
221 .tx_buf_alloc = dsi_tx_buf_alloc_v2,
222 .tx_buf_get = dsi_tx_buf_get_v2,
223 .tx_buf_put = NULL,
224 .dma_base_get = dsi_dma_base_get_v2,
225 .calc_clk_rate = dsi_calc_clk_rate_v2,
226};
227
228static const struct msm_dsi_host_cfg_ops msm_dsi_6g_host_ops = {
229 .link_clk_set_rate = dsi_link_clk_set_rate_6g,
230 .link_clk_enable = dsi_link_clk_enable_6g,
231 .link_clk_disable = dsi_link_clk_disable_6g,
232 .clk_init_ver = NULL,
233 .tx_buf_alloc = dsi_tx_buf_alloc_6g,
234 .tx_buf_get = dsi_tx_buf_get_6g,
235 .tx_buf_put = dsi_tx_buf_put_6g,
236 .dma_base_get = dsi_dma_base_get_6g,
237 .calc_clk_rate = dsi_calc_clk_rate_6g,
238};
239
240static const struct msm_dsi_host_cfg_ops msm_dsi_6g_v2_host_ops = {
241 .link_clk_set_rate = dsi_link_clk_set_rate_6g,
242 .link_clk_enable = dsi_link_clk_enable_6g,
243 .link_clk_disable = dsi_link_clk_disable_6g,
244 .clk_init_ver = dsi_clk_init_6g_v2,
245 .tx_buf_alloc = dsi_tx_buf_alloc_6g,
246 .tx_buf_get = dsi_tx_buf_get_6g,
247 .tx_buf_put = dsi_tx_buf_put_6g,
248 .dma_base_get = dsi_dma_base_get_6g,
249 .calc_clk_rate = dsi_calc_clk_rate_6g,
250};
251
252static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
253 {MSM_DSI_VER_MAJOR_V2, MSM_DSI_V2_VER_MINOR_8064,
254 &apq8064_dsi_cfg, &msm_dsi_v2_host_ops},
255 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_0,
256 &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
257 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1,
258 &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
259 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1_1,
260 &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
261 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_2,
262 &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
263 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3,
264 &msm8994_dsi_cfg, &msm_dsi_6g_host_ops},
265 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3_1,
266 &msm8916_dsi_cfg, &msm_dsi_6g_host_ops},
267 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_4_1,
268 &msm8996_dsi_cfg, &msm_dsi_6g_host_ops},
269 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_4_2,
270 &msm8976_dsi_cfg, &msm_dsi_6g_host_ops},
271 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_1_0,
272 &sdm660_dsi_cfg, &msm_dsi_6g_v2_host_ops},
273 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_0,
274 &msm8998_dsi_cfg, &msm_dsi_6g_v2_host_ops},
275 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_1,
276 &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
277 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_3_0,
278 &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
279 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_0,
280 &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
281 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_1,
282 &sc7180_dsi_cfg, &msm_dsi_6g_v2_host_ops},
283 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_5_0,
284 &sc7280_dsi_cfg, &msm_dsi_6g_v2_host_ops},
285};
286
287const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)
288{
289 const struct msm_dsi_cfg_handler *cfg_hnd = NULL;
290 int i;
291
292 for (i = ARRAY_SIZE(dsi_cfg_handlers) - 1; i >= 0; i--) {
293 if ((dsi_cfg_handlers[i].major == major) &&
294 (dsi_cfg_handlers[i].minor == minor)) {
295 cfg_hnd = &dsi_cfg_handlers[i];
296 break;
297 }
298 }
299
300 return cfg_hnd;
301}
302
303
