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6#ifndef __DSI_PHY_H__
7#define __DSI_PHY_H__
8
9#include <linux/clk-provider.h>
10#include <linux/delay.h>
11#include <linux/regulator/consumer.h>
12
13#include "dsi.h"
14
15#define dsi_phy_read(offset) msm_readl((offset))
16#define dsi_phy_write(offset, data) msm_writel((data), (offset))
17#define dsi_phy_write_udelay(offset, data, delay_us) { msm_writel((data), (offset)); udelay(delay_us); }
18#define dsi_phy_write_ndelay(offset, data, delay_ns) { msm_writel((data), (offset)); ndelay(delay_ns); }
19
20struct msm_dsi_phy_ops {
21 int (*pll_init)(struct msm_dsi_phy *phy);
22 int (*enable)(struct msm_dsi_phy *phy,
23 struct msm_dsi_phy_clk_request *clk_req);
24 void (*disable)(struct msm_dsi_phy *phy);
25 void (*save_pll_state)(struct msm_dsi_phy *phy);
26 int (*restore_pll_state)(struct msm_dsi_phy *phy);
27 bool (*set_continuous_clock)(struct msm_dsi_phy *phy, bool enable);
28};
29
30struct msm_dsi_phy_cfg {
31 struct dsi_reg_config reg_cfg;
32 struct msm_dsi_phy_ops ops;
33
34 unsigned long min_pll_rate;
35 unsigned long max_pll_rate;
36
37 const resource_size_t io_start[DSI_MAX];
38 const int num_dsi_phy;
39 const int quirks;
40 bool has_phy_regulator;
41 bool has_phy_lane;
42};
43
44extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs;
45extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs;
46extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs;
47extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
48extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
49extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
50extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs;
51extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;
52extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
53extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs;
54extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
55extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
56
57struct msm_dsi_dphy_timing {
58 u32 clk_zero;
59 u32 clk_trail;
60 u32 clk_prepare;
61 u32 hs_exit;
62 u32 hs_zero;
63 u32 hs_prepare;
64 u32 hs_trail;
65 u32 hs_rqst;
66 u32 ta_go;
67 u32 ta_sure;
68 u32 ta_get;
69
70 struct msm_dsi_phy_shared_timings shared_timings;
71
72
73 u32 hs_rqst_ckln;
74 u32 hs_prep_dly;
75 u32 hs_prep_dly_ckln;
76 u8 hs_halfbyte_en;
77 u8 hs_halfbyte_en_ckln;
78};
79
80#define DSI_BYTE_PLL_CLK 0
81#define DSI_PIXEL_PLL_CLK 1
82#define NUM_PROVIDED_CLKS 2
83
84struct msm_dsi_phy {
85 struct platform_device *pdev;
86 void __iomem *base;
87 void __iomem *pll_base;
88 void __iomem *reg_base;
89 void __iomem *lane_base;
90 phys_addr_t base_size;
91 phys_addr_t pll_size;
92 phys_addr_t reg_size;
93 phys_addr_t lane_size;
94 int id;
95
96 struct clk *ahb_clk;
97 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
98
99 struct msm_dsi_dphy_timing timing;
100 const struct msm_dsi_phy_cfg *cfg;
101
102 enum msm_dsi_phy_usecase usecase;
103 bool regulator_ldo_mode;
104 bool cphy_mode;
105
106 struct clk_hw *vco_hw;
107 bool pll_on;
108
109 struct clk_hw_onecell_data *provided_clocks;
110
111 bool state_saved;
112};
113
114
115
116
117int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
118 struct msm_dsi_phy_clk_request *clk_req);
119int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
120 struct msm_dsi_phy_clk_request *clk_req);
121int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
122 struct msm_dsi_phy_clk_request *clk_req);
123int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
124 struct msm_dsi_phy_clk_request *clk_req);
125int msm_dsi_cphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
126 struct msm_dsi_phy_clk_request *clk_req);
127
128#endif
129
