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7#include "msm_ringbuffer.h"
8#include "msm_gpu.h"
9
10static uint num_hw_submissions = 8;
11MODULE_PARM_DESC(num_hw_submissions, "The max # of jobs to write into ringbuffer (default 8)");
12module_param(num_hw_submissions, uint, 0600);
13
14static struct dma_fence *msm_job_dependency(struct drm_sched_job *job,
15 struct drm_sched_entity *s_entity)
16{
17 struct msm_gem_submit *submit = to_msm_submit(job);
18
19 if (!xa_empty(&submit->deps))
20 return xa_erase(&submit->deps, submit->last_dep++);
21
22 return NULL;
23}
24
25static struct dma_fence *msm_job_run(struct drm_sched_job *job)
26{
27 struct msm_gem_submit *submit = to_msm_submit(job);
28 struct msm_gpu *gpu = submit->gpu;
29
30 submit->hw_fence = msm_fence_alloc(submit->ring->fctx);
31
32 pm_runtime_get_sync(&gpu->pdev->dev);
33
34
35 mutex_lock(&gpu->dev->struct_mutex);
36
37 msm_gpu_submit(gpu, submit);
38
39 mutex_unlock(&gpu->dev->struct_mutex);
40
41 pm_runtime_put(&gpu->pdev->dev);
42
43 return dma_fence_get(submit->hw_fence);
44}
45
46static void msm_job_free(struct drm_sched_job *job)
47{
48 struct msm_gem_submit *submit = to_msm_submit(job);
49
50 drm_sched_job_cleanup(job);
51 msm_gem_submit_put(submit);
52}
53
54const struct drm_sched_backend_ops msm_sched_ops = {
55 .dependency = msm_job_dependency,
56 .run_job = msm_job_run,
57 .free_job = msm_job_free
58};
59
60struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id,
61 void *memptrs, uint64_t memptrs_iova)
62{
63 struct msm_ringbuffer *ring;
64 long sched_timeout;
65 char name[32];
66 int ret;
67
68
69 BUILD_BUG_ON(!is_power_of_2(MSM_GPU_RINGBUFFER_SZ));
70
71 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
72 if (!ring) {
73 ret = -ENOMEM;
74 goto fail;
75 }
76
77 ring->gpu = gpu;
78 ring->id = id;
79
80 ring->start = msm_gem_kernel_new(gpu->dev, MSM_GPU_RINGBUFFER_SZ,
81 check_apriv(gpu, MSM_BO_WC | MSM_BO_GPU_READONLY),
82 gpu->aspace, &ring->bo, &ring->iova);
83
84 if (IS_ERR(ring->start)) {
85 ret = PTR_ERR(ring->start);
86 ring->start = NULL;
87 goto fail;
88 }
89
90 msm_gem_object_set_name(ring->bo, "ring%d", id);
91
92 ring->end = ring->start + (MSM_GPU_RINGBUFFER_SZ >> 2);
93 ring->next = ring->start;
94 ring->cur = ring->start;
95
96 ring->memptrs = memptrs;
97 ring->memptrs_iova = memptrs_iova;
98
99
100 sched_timeout = MAX_SCHEDULE_TIMEOUT;
101
102 ret = drm_sched_init(&ring->sched, &msm_sched_ops,
103 num_hw_submissions, 0, sched_timeout,
104 NULL, NULL, to_msm_bo(ring->bo)->name);
105 if (ret) {
106 goto fail;
107 }
108
109 INIT_LIST_HEAD(&ring->submits);
110 spin_lock_init(&ring->submit_lock);
111 spin_lock_init(&ring->preempt_lock);
112
113 snprintf(name, sizeof(name), "gpu-ring-%d", ring->id);
114
115 ring->fctx = msm_fence_context_alloc(gpu->dev, &ring->memptrs->fence, name);
116
117 return ring;
118
119fail:
120 msm_ringbuffer_destroy(ring);
121 return ERR_PTR(ret);
122}
123
124void msm_ringbuffer_destroy(struct msm_ringbuffer *ring)
125{
126 if (IS_ERR_OR_NULL(ring))
127 return;
128
129 drm_sched_fini(&ring->sched);
130
131 msm_fence_context_free(ring->fctx);
132
133 msm_gem_kernel_put(ring->bo, ring->gpu->aspace);
134
135 kfree(ring);
136}
137