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25#include <drm/drm_crtc_helper.h>
26#include <drm/drm_fourcc.h>
27#include <drm/drm_plane_helper.h>
28#include <drm/drm_vblank.h>
29
30#include "nouveau_drv.h"
31#include "nouveau_reg.h"
32#include "nouveau_ttm.h"
33#include "nouveau_bo.h"
34#include "nouveau_gem.h"
35#include "nouveau_encoder.h"
36#include "nouveau_connector.h"
37#include "nouveau_crtc.h"
38#include "hw.h"
39#include "nvreg.h"
40#include "nouveau_fbcon.h"
41#include "disp.h"
42#include "nouveau_dma.h"
43
44#include <subdev/bios/pll.h>
45#include <subdev/clk.h>
46
47#include <nvif/push006c.h>
48
49#include <nvif/event.h>
50#include <nvif/cl0046.h>
51
52static int
53nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
54 struct drm_framebuffer *old_fb);
55
56static void
57crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)
58{
59 NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index,
60 crtcstate->CRTC[index]);
61}
62
63static void nv_crtc_set_digital_vibrance(struct drm_crtc *crtc, int level)
64{
65 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
66 struct drm_device *dev = crtc->dev;
67 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
68
69 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level;
70 if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) {
71 regp->CRTC[NV_CIO_CRE_CSB] = 0x80;
72 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2;
73 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B);
74 }
75 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB);
76}
77
78static void nv_crtc_set_image_sharpening(struct drm_crtc *crtc, int level)
79{
80 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
81 struct drm_device *dev = crtc->dev;
82 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
83
84 nv_crtc->sharpness = level;
85 if (level < 0)
86 level += 0x40;
87 regp->ramdac_634 = level;
88 NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634);
89}
90
91#define PLLSEL_VPLL1_MASK \
92 (NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL \
93 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2)
94#define PLLSEL_VPLL2_MASK \
95 (NV_PRAMDAC_PLL_COEFF_SELECT_PLL_SOURCE_VPLL2 \
96 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB2)
97#define PLLSEL_TV_MASK \
98 (NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1 \
99 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1 \
100 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2 \
101 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2)
102
103
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111
112
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114
115
116
117static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_clock)
118{
119 struct drm_device *dev = crtc->dev;
120 struct nouveau_drm *drm = nouveau_drm(dev);
121 struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
122 struct nvkm_clk *clk = nvxx_clk(&drm->client.device);
123 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
124 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
125 struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index];
126 struct nvkm_pll_vals *pv = ®p->pllvals;
127 struct nvbios_pll pll_lim;
128
129 if (nvbios_pll_parse(bios, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0,
130 &pll_lim))
131 return;
132
133
134 pv->NM2 = 0;
135
136
137
138
139
140
141
142
143
144
145
146 if (drm->client.device.info.chipset > 0x40 && dot_clock <= (pll_lim.vco1.max_freq / 2))
147 memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2));
148
149
150 if (!clk->pll_calc(clk, &pll_lim, dot_clock, pv))
151 return;
152
153 state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK;
154
155
156 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
157 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE;
158
159 if (drm->client.device.info.chipset < 0x41)
160 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL |
161 NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL;
162 state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK;
163
164 if (pv->NM2)
165 NV_DEBUG(drm, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n",
166 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P);
167 else
168 NV_DEBUG(drm, "vpll: n %d m %d log2p %d\n",
169 pv->N1, pv->M1, pv->log2P);
170
171 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
172}
173
174static void
175nv_crtc_dpms(struct drm_crtc *crtc, int mode)
176{
177 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
178 struct drm_device *dev = crtc->dev;
179 struct nouveau_drm *drm = nouveau_drm(dev);
180 unsigned char seq1 = 0, crtc17 = 0;
181 unsigned char crtc1A;
182
183 NV_DEBUG(drm, "Setting dpms mode %d on CRTC %d\n", mode,
184 nv_crtc->index);
185
186 if (nv_crtc->last_dpms == mode)
187 return;
188
189 nv_crtc->last_dpms = mode;
190
191 if (nv_two_heads(dev))
192 NVSetOwner(dev, nv_crtc->index);
193
194
195 crtc1A = NVReadVgaCrtc(dev, nv_crtc->index,
196 NV_CIO_CRE_RPC1_INDEX) & ~0xC0;
197 switch (mode) {
198 case DRM_MODE_DPMS_STANDBY:
199
200 seq1 = 0x20;
201 crtc17 = 0x80;
202 crtc1A |= 0x80;
203 break;
204 case DRM_MODE_DPMS_SUSPEND:
205
206 seq1 = 0x20;
207 crtc17 = 0x80;
208 crtc1A |= 0x40;
209 break;
210 case DRM_MODE_DPMS_OFF:
211
212 seq1 = 0x20;
213 crtc17 = 0x00;
214 crtc1A |= 0xC0;
215 break;
216 case DRM_MODE_DPMS_ON:
217 default:
218
219 seq1 = 0x00;
220 crtc17 = 0x80;
221 break;
222 }
223
224 NVVgaSeqReset(dev, nv_crtc->index, true);
225
226 seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20);
227 NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1);
228 crtc17 |= (NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX) & ~0x80);
229 mdelay(10);
230 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17);
231 NVVgaSeqReset(dev, nv_crtc->index, false);
232
233 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A);
234}
235
236static void
237nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode)
238{
239 struct drm_device *dev = crtc->dev;
240 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
241 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
242 struct drm_framebuffer *fb = crtc->primary->fb;
243
244
245 int horizDisplay = (mode->crtc_hdisplay >> 3) - 1;
246 int horizStart = (mode->crtc_hsync_start >> 3) + 1;
247 int horizEnd = (mode->crtc_hsync_end >> 3) + 1;
248 int horizTotal = (mode->crtc_htotal >> 3) - 5;
249 int horizBlankStart = (mode->crtc_hdisplay >> 3) - 1;
250 int horizBlankEnd = (mode->crtc_htotal >> 3) - 1;
251 int vertDisplay = mode->crtc_vdisplay - 1;
252 int vertStart = mode->crtc_vsync_start - 1;
253 int vertEnd = mode->crtc_vsync_end - 1;
254 int vertTotal = mode->crtc_vtotal - 2;
255 int vertBlankStart = mode->crtc_vdisplay - 1;
256 int vertBlankEnd = mode->crtc_vtotal - 1;
257
258 struct drm_encoder *encoder;
259 bool fp_output = false;
260
261 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
262 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
263
264 if (encoder->crtc == crtc &&
265 (nv_encoder->dcb->type == DCB_OUTPUT_LVDS ||
266 nv_encoder->dcb->type == DCB_OUTPUT_TMDS))
267 fp_output = true;
268 }
269
270 if (fp_output) {
271 vertStart = vertTotal - 3;
272 vertEnd = vertTotal - 2;
273 vertBlankStart = vertStart;
274 horizStart = horizTotal - 5;
275 horizEnd = horizTotal - 2;
276 horizBlankEnd = horizTotal + 4;
277#if 0
278 if (dev->overlayAdaptor && drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
279
280 horizTotal += 2;
281#endif
282 }
283
284 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
285 vertTotal |= 1;
286
287#if 0
288 ErrorF("horizDisplay: 0x%X \n", horizDisplay);
289 ErrorF("horizStart: 0x%X \n", horizStart);
290 ErrorF("horizEnd: 0x%X \n", horizEnd);
291 ErrorF("horizTotal: 0x%X \n", horizTotal);
292 ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
293 ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
294 ErrorF("vertDisplay: 0x%X \n", vertDisplay);
295 ErrorF("vertStart: 0x%X \n", vertStart);
296 ErrorF("vertEnd: 0x%X \n", vertEnd);
297 ErrorF("vertTotal: 0x%X \n", vertTotal);
298 ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
299 ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
300#endif
301
302
303
304
305 if ((mode->flags & (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))
306 && (mode->flags & (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) {
307
308 regp->MiscOutReg = 0x23;
309 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
310 regp->MiscOutReg |= 0x40;
311 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
312 regp->MiscOutReg |= 0x80;
313 } else {
314 int vdisplay = mode->vdisplay;
315 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
316 vdisplay *= 2;
317 if (mode->vscan > 1)
318 vdisplay *= mode->vscan;
319 if (vdisplay < 400)
320 regp->MiscOutReg = 0xA3;
321 else if (vdisplay < 480)
322 regp->MiscOutReg = 0x63;
323 else if (vdisplay < 768)
324 regp->MiscOutReg = 0xE3;
325 else
326 regp->MiscOutReg = 0x23;
327 }
328
329
330
331
332 regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00;
333
334 if (mode->flags & DRM_MODE_FLAG_CLKDIV2)
335 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29;
336 else
337 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21;
338 regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F;
339 regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00;
340 regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E;
341
342
343
344
345 regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal;
346 regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay;
347 regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart;
348 regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) |
349 XLATE(horizBlankEnd, 0, NV_CIO_CR_HBE_4_0);
350 regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart;
351 regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) |
352 XLATE(horizEnd, 0, NV_CIO_CR_HRE_4_0);
353 regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal;
354 regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) |
355 XLATE(vertDisplay, 9, NV_CIO_CR_OVL_VDE_9) |
356 XLATE(vertTotal, 9, NV_CIO_CR_OVL_VDT_9) |
357 (1 << 4) |
358 XLATE(vertBlankStart, 8, NV_CIO_CR_OVL_VBS_8) |
359 XLATE(vertStart, 8, NV_CIO_CR_OVL_VRS_8) |
360 XLATE(vertDisplay, 8, NV_CIO_CR_OVL_VDE_8) |
361 XLATE(vertTotal, 8, NV_CIO_CR_OVL_VDT_8);
362 regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00;
363 regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) |
364 1 << 6 |
365 XLATE(vertBlankStart, 9, NV_CIO_CR_CELL_HT_VBS_9);
366 regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00;
367 regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00;
368 regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00;
369 regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00;
370 regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00;
371 regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00;
372 regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart;
373 regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0);
374 regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay;
375
376 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8;
377 regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00;
378 regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart;
379 regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd;
380 regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43;
381 regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff;
382
383
384
385
386
387
388 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
389 XLATE(fb->pitches[0] / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
390 regp->CRTC[NV_CIO_CRE_42] =
391 XLATE(fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11);
392 regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ?
393 MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00;
394 regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) |
395 XLATE(vertBlankStart, 10, NV_CIO_CRE_LSR_VBS_10) |
396 XLATE(vertStart, 10, NV_CIO_CRE_LSR_VRS_10) |
397 XLATE(vertDisplay, 10, NV_CIO_CRE_LSR_VDE_10) |
398 XLATE(vertTotal, 10, NV_CIO_CRE_LSR_VDT_10);
399 regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) |
400 XLATE(horizBlankStart, 8, NV_CIO_CRE_HEB_HBS_8) |
401 XLATE(horizDisplay, 8, NV_CIO_CRE_HEB_HDE_8) |
402 XLATE(horizTotal, 8, NV_CIO_CRE_HEB_HDT_8);
403 regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) |
404 XLATE(vertStart, 11, NV_CIO_CRE_EBR_VRS_11) |
405 XLATE(vertDisplay, 11, NV_CIO_CRE_EBR_VDE_11) |
406 XLATE(vertTotal, 11, NV_CIO_CRE_EBR_VDT_11);
407
408 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
409 horizTotal = (horizTotal >> 1) & ~1;
410 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal;
411 regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8);
412 } else
413 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff;
414
415
416
417
418 regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00;
419 regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00;
420 regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00;
421 regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00;
422 regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00;
423 regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40;
424 regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05;
425 regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F;
426 regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF;
427
428 regp->Attribute[0] = 0x00;
429 regp->Attribute[1] = 0x01;
430 regp->Attribute[2] = 0x02;
431 regp->Attribute[3] = 0x03;
432 regp->Attribute[4] = 0x04;
433 regp->Attribute[5] = 0x05;
434 regp->Attribute[6] = 0x06;
435 regp->Attribute[7] = 0x07;
436 regp->Attribute[8] = 0x08;
437 regp->Attribute[9] = 0x09;
438 regp->Attribute[10] = 0x0A;
439 regp->Attribute[11] = 0x0B;
440 regp->Attribute[12] = 0x0C;
441 regp->Attribute[13] = 0x0D;
442 regp->Attribute[14] = 0x0E;
443 regp->Attribute[15] = 0x0F;
444 regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01;
445
446 regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00;
447 regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F;
448 regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00;
449 regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00;
450}
451
452
453
454
455
456
457
458
459
460static void
461nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode)
462{
463 struct drm_device *dev = crtc->dev;
464 struct nouveau_drm *drm = nouveau_drm(dev);
465 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
466 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
467 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
468 const struct drm_framebuffer *fb = crtc->primary->fb;
469 struct drm_encoder *encoder;
470 bool lvds_output = false, tmds_output = false, tv_output = false,
471 off_chip_digital = false;
472
473 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
474 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
475 bool digital = false;
476
477 if (encoder->crtc != crtc)
478 continue;
479
480 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS)
481 digital = lvds_output = true;
482 if (nv_encoder->dcb->type == DCB_OUTPUT_TV)
483 tv_output = true;
484 if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS)
485 digital = tmds_output = true;
486 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && digital)
487 off_chip_digital = true;
488 }
489
490
491
492
493
494 regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5);
495
496 regp->crtc_eng_ctrl = 0;
497
498 if (nv_crtc->index == 0)
499 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_I2C;
500#if 0
501
502 if (dev->overlayAdaptor) {
503 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(dev);
504 if (pPriv->overlayCRTC == nv_crtc->index)
505 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_OVERLAY;
506 }
507#endif
508
509
510 regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 |
511 NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 |
512 NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM;
513 if (drm->client.device.info.chipset >= 0x11)
514 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32;
515 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
516 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE;
517
518
519 regp->CRTC[NV_CIO_CRE_53] = 0;
520 regp->CRTC[NV_CIO_CRE_54] = 0;
521
522
523 if (lvds_output)
524 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11;
525 else if (tmds_output)
526 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88;
527 else
528 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22;
529
530
531
532 regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX];
533
534 nv_crtc_set_digital_vibrance(crtc, nv_crtc->saturation);
535
536
537
538
539
540
541 if (nv_crtc->index == 0)
542 regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80;
543
544
545
546 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY];
547 if (!nv_crtc->index)
548 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4;
549
550
551
552 regp->CRTC[NV_CIO_CRE_59] = off_chip_digital;
553
554 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
555 regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1;
556
557 regp->crtc_830 = mode->crtc_vdisplay - 3;
558 regp->crtc_834 = mode->crtc_vdisplay - 1;
559
560 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
561
562 regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850);
563
564 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
565 regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT);
566
567 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
568 regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC;
569 else
570 regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC;
571
572
573 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) {
574 regp->CRTC[NV_CIO_CRE_85] = 0xFF;
575 regp->CRTC[NV_CIO_CRE_86] = 0x1;
576 }
577
578 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (fb->format->depth + 1) / 8;
579
580 if (lvds_output || tmds_output || tv_output)
581 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7);
582
583
584
585 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
586
587 regp->nv10_cursync = (1 << 25);
588
589 regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS |
590 NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL |
591 NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON;
592 if (fb->format->depth == 16)
593 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
594 if (drm->client.device.info.chipset >= 0x11)
595 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG;
596
597 regp->ramdac_630 = 0;
598 regp->tv_setup = 0;
599
600 nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness);
601
602
603 regp->ramdac_8c0 = 0x100;
604 regp->ramdac_a20 = 0x0;
605 regp->ramdac_a24 = 0xfffff;
606 regp->ramdac_a34 = 0x1;
607}
608
609static int
610nv_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
611{
612 struct nv04_display *disp = nv04_display(crtc->dev);
613 struct drm_framebuffer *fb = crtc->primary->fb;
614 struct nouveau_bo *nvbo = nouveau_gem_object(fb->obj[0]);
615 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
616 int ret;
617
618 ret = nouveau_bo_pin(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, false);
619 if (ret == 0) {
620 if (disp->image[nv_crtc->index])
621 nouveau_bo_unpin(disp->image[nv_crtc->index]);
622 nouveau_bo_ref(nvbo, &disp->image[nv_crtc->index]);
623 }
624
625 return ret;
626}
627
628
629
630
631
632
633
634
635
636static int
637nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
638 struct drm_display_mode *adjusted_mode,
639 int x, int y, struct drm_framebuffer *old_fb)
640{
641 struct drm_device *dev = crtc->dev;
642 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
643 struct nouveau_drm *drm = nouveau_drm(dev);
644 int ret;
645
646 NV_DEBUG(drm, "CTRC mode on CRTC %d:\n", nv_crtc->index);
647 drm_mode_debug_printmodeline(adjusted_mode);
648
649 ret = nv_crtc_swap_fbs(crtc, old_fb);
650 if (ret)
651 return ret;
652
653
654 nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1);
655
656 nv_crtc_mode_set_vga(crtc, adjusted_mode);
657
658 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
659 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk);
660 nv_crtc_mode_set_regs(crtc, adjusted_mode);
661 nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock);
662 return 0;
663}
664
665static void nv_crtc_save(struct drm_crtc *crtc)
666{
667 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
668 struct drm_device *dev = crtc->dev;
669 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
670 struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index];
671 struct nv04_mode_state *saved = &nv04_display(dev)->saved_reg;
672 struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index];
673
674 if (nv_two_heads(crtc->dev))
675 NVSetOwner(crtc->dev, nv_crtc->index);
676
677 nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved);
678
679
680 state->sel_clk = saved->sel_clk & ~(0x5 << 16);
681 crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX];
682 state->pllsel = saved->pllsel & ~(PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK);
683 crtc_state->gpio_ext = crtc_saved->gpio_ext;
684}
685
686static void nv_crtc_restore(struct drm_crtc *crtc)
687{
688 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
689 struct drm_device *dev = crtc->dev;
690 int head = nv_crtc->index;
691 uint8_t saved_cr21 = nv04_display(dev)->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21];
692
693 if (nv_two_heads(crtc->dev))
694 NVSetOwner(crtc->dev, head);
695
696 nouveau_hw_load_state(crtc->dev, head, &nv04_display(dev)->saved_reg);
697 nv_lock_vga_crtc_shadow(crtc->dev, head, saved_cr21);
698
699 nv_crtc->last_dpms = NV_DPMS_CLEARED;
700}
701
702static void nv_crtc_prepare(struct drm_crtc *crtc)
703{
704 struct drm_device *dev = crtc->dev;
705 struct nouveau_drm *drm = nouveau_drm(dev);
706 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
707 const struct drm_crtc_helper_funcs *funcs = crtc->helper_private;
708
709 if (nv_two_heads(dev))
710 NVSetOwner(dev, nv_crtc->index);
711
712 drm_crtc_vblank_off(crtc);
713 funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
714
715 NVBlankScreen(dev, nv_crtc->index, true);
716
717
718 NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA);
719 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) {
720 uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900);
721 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000);
722 }
723}
724
725static void nv_crtc_commit(struct drm_crtc *crtc)
726{
727 struct drm_device *dev = crtc->dev;
728 const struct drm_crtc_helper_funcs *funcs = crtc->helper_private;
729 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
730
731 nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);
732 nv04_crtc_mode_set_base(crtc, crtc->x, crtc->y, NULL);
733
734#ifdef __BIG_ENDIAN
735
736 {
737 uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR);
738 tmp |= MASK(NV_CIO_CRE_RCR_ENDIAN_BIG);
739 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp);
740 }
741#endif
742
743 funcs->dpms(crtc, DRM_MODE_DPMS_ON);
744 drm_crtc_vblank_on(crtc);
745}
746
747static void nv_crtc_destroy(struct drm_crtc *crtc)
748{
749 struct nv04_display *disp = nv04_display(crtc->dev);
750 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
751
752 if (!nv_crtc)
753 return;
754
755 drm_crtc_cleanup(crtc);
756
757 if (disp->image[nv_crtc->index])
758 nouveau_bo_unpin(disp->image[nv_crtc->index]);
759 nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]);
760
761 nouveau_bo_unmap(nv_crtc->cursor.nvbo);
762 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
763 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
764 nvif_notify_dtor(&nv_crtc->vblank);
765 kfree(nv_crtc);
766}
767
768static void
769nv_crtc_gamma_load(struct drm_crtc *crtc)
770{
771 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
772 struct drm_device *dev = nv_crtc->base.dev;
773 struct rgb { uint8_t r, g, b; } __attribute__((packed)) *rgbs;
774 u16 *r, *g, *b;
775 int i;
776
777 rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC;
778 r = crtc->gamma_store;
779 g = r + crtc->gamma_size;
780 b = g + crtc->gamma_size;
781
782 for (i = 0; i < 256; i++) {
783 rgbs[i].r = *r++ >> 8;
784 rgbs[i].g = *g++ >> 8;
785 rgbs[i].b = *b++ >> 8;
786 }
787
788 nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);
789}
790
791static void
792nv_crtc_disable(struct drm_crtc *crtc)
793{
794 struct nv04_display *disp = nv04_display(crtc->dev);
795 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
796 if (disp->image[nv_crtc->index])
797 nouveau_bo_unpin(disp->image[nv_crtc->index]);
798 nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]);
799}
800
801static int
802nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
803 uint32_t size,
804 struct drm_modeset_acquire_ctx *ctx)
805{
806 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
807
808
809
810
811
812
813 if (!nv_crtc->base.primary->fb) {
814 nv_crtc->lut.depth = 0;
815 return 0;
816 }
817
818 nv_crtc_gamma_load(crtc);
819
820 return 0;
821}
822
823static int
824nv04_crtc_do_mode_set_base(struct drm_crtc *crtc,
825 struct drm_framebuffer *passed_fb,
826 int x, int y, bool atomic)
827{
828 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
829 struct drm_device *dev = crtc->dev;
830 struct nouveau_drm *drm = nouveau_drm(dev);
831 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
832 struct nouveau_bo *nvbo;
833 struct drm_framebuffer *drm_fb;
834 int arb_burst, arb_lwm;
835
836 NV_DEBUG(drm, "index %d\n", nv_crtc->index);
837
838
839 if (!atomic && !crtc->primary->fb) {
840 NV_DEBUG(drm, "No FB bound\n");
841 return 0;
842 }
843
844
845
846
847 if (atomic) {
848 drm_fb = passed_fb;
849 } else {
850 drm_fb = crtc->primary->fb;
851 }
852
853 nvbo = nouveau_gem_object(drm_fb->obj[0]);
854 nv_crtc->fb.offset = nvbo->offset;
855
856 if (nv_crtc->lut.depth != drm_fb->format->depth) {
857 nv_crtc->lut.depth = drm_fb->format->depth;
858 nv_crtc_gamma_load(crtc);
859 }
860
861
862 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3;
863 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (drm_fb->format->depth + 1) / 8;
864 regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
865 if (drm_fb->format->depth == 16)
866 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
867 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX);
868 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL,
869 regp->ramdac_gen_ctrl);
870
871 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3;
872 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
873 XLATE(drm_fb->pitches[0] >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
874 regp->CRTC[NV_CIO_CRE_42] =
875 XLATE(drm_fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11);
876 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX);
877 crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX);
878 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42);
879
880
881 regp->fb_start = nv_crtc->fb.offset & ~3;
882 regp->fb_start += (y * drm_fb->pitches[0]) + (x * drm_fb->format->cpp[0]);
883 nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start);
884
885
886 nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->format->cpp[0] * 8,
887 &arb_burst, &arb_lwm);
888
889 regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst;
890 regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff;
891 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX);
892 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX);
893
894 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN) {
895 regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8;
896 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47);
897 }
898
899 return 0;
900}
901
902static int
903nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
904 struct drm_framebuffer *old_fb)
905{
906 int ret = nv_crtc_swap_fbs(crtc, old_fb);
907 if (ret)
908 return ret;
909 return nv04_crtc_do_mode_set_base(crtc, old_fb, x, y, false);
910}
911
912static int
913nv04_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
914 struct drm_framebuffer *fb,
915 int x, int y, enum mode_set_atomic state)
916{
917 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
918 struct drm_device *dev = drm->dev;
919
920 if (state == ENTER_ATOMIC_MODE_SET)
921 nouveau_fbcon_accel_save_disable(dev);
922 else
923 nouveau_fbcon_accel_restore(dev);
924
925 return nv04_crtc_do_mode_set_base(crtc, fb, x, y, true);
926}
927
928static void nv04_cursor_upload(struct drm_device *dev, struct nouveau_bo *src,
929 struct nouveau_bo *dst)
930{
931 int width = nv_cursor_width(dev);
932 uint32_t pixel;
933 int i, j;
934
935 for (i = 0; i < width; i++) {
936 for (j = 0; j < width; j++) {
937 pixel = nouveau_bo_rd32(src, i*64 + j);
938
939 nouveau_bo_wr16(dst, i*width + j, (pixel & 0x80000000) >> 16
940 | (pixel & 0xf80000) >> 9
941 | (pixel & 0xf800) >> 6
942 | (pixel & 0xf8) >> 3);
943 }
944 }
945}
946
947static void nv11_cursor_upload(struct drm_device *dev, struct nouveau_bo *src,
948 struct nouveau_bo *dst)
949{
950 uint32_t pixel;
951 int alpha, i;
952
953
954
955
956
957
958
959 for (i = 0; i < 64 * 64; i++) {
960 pixel = nouveau_bo_rd32(src, i);
961
962
963
964
965
966
967 alpha = pixel >> 24;
968 if (alpha > 0 && alpha < 255)
969 pixel = (pixel & 0x00ffffff) | ((alpha + 1) << 24);
970
971#ifdef __BIG_ENDIAN
972 {
973 struct nouveau_drm *drm = nouveau_drm(dev);
974
975 if (drm->client.device.info.chipset == 0x11) {
976 pixel = ((pixel & 0x000000ff) << 24) |
977 ((pixel & 0x0000ff00) << 8) |
978 ((pixel & 0x00ff0000) >> 8) |
979 ((pixel & 0xff000000) >> 24);
980 }
981 }
982#endif
983
984 nouveau_bo_wr32(dst, i, pixel);
985 }
986}
987
988static int
989nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
990 uint32_t buffer_handle, uint32_t width, uint32_t height)
991{
992 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
993 struct drm_device *dev = drm->dev;
994 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
995 struct nouveau_bo *cursor = NULL;
996 struct drm_gem_object *gem;
997 int ret = 0;
998
999 if (!buffer_handle) {
1000 nv_crtc->cursor.hide(nv_crtc, true);
1001 return 0;
1002 }
1003
1004 if (width != 64 || height != 64)
1005 return -EINVAL;
1006
1007 gem = drm_gem_object_lookup(file_priv, buffer_handle);
1008 if (!gem)
1009 return -ENOENT;
1010 cursor = nouveau_gem_object(gem);
1011
1012 ret = nouveau_bo_map(cursor);
1013 if (ret)
1014 goto out;
1015
1016 if (drm->client.device.info.chipset >= 0x11)
1017 nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
1018 else
1019 nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
1020
1021 nouveau_bo_unmap(cursor);
1022 nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->offset;
1023 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
1024 nv_crtc->cursor.show(nv_crtc, true);
1025out:
1026 drm_gem_object_put(gem);
1027 return ret;
1028}
1029
1030static int
1031nv04_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1032{
1033 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1034
1035 nv_crtc->cursor.set_pos(nv_crtc, x, y);
1036 return 0;
1037}
1038
1039struct nv04_page_flip_state {
1040 struct list_head head;
1041 struct drm_pending_vblank_event *event;
1042 struct drm_crtc *crtc;
1043 int bpp, pitch;
1044 u64 offset;
1045};
1046
1047static int
1048nv04_finish_page_flip(struct nouveau_channel *chan,
1049 struct nv04_page_flip_state *ps)
1050{
1051 struct nouveau_fence_chan *fctx = chan->fence;
1052 struct nouveau_drm *drm = chan->drm;
1053 struct drm_device *dev = drm->dev;
1054 struct nv04_page_flip_state *s;
1055 unsigned long flags;
1056
1057 spin_lock_irqsave(&dev->event_lock, flags);
1058
1059 if (list_empty(&fctx->flip)) {
1060 NV_ERROR(drm, "unexpected pageflip\n");
1061 spin_unlock_irqrestore(&dev->event_lock, flags);
1062 return -EINVAL;
1063 }
1064
1065 s = list_first_entry(&fctx->flip, struct nv04_page_flip_state, head);
1066 if (s->event) {
1067 drm_crtc_arm_vblank_event(s->crtc, s->event);
1068 } else {
1069
1070 drm_crtc_vblank_put(s->crtc);
1071 }
1072
1073 list_del(&s->head);
1074 if (ps)
1075 *ps = *s;
1076 kfree(s);
1077
1078 spin_unlock_irqrestore(&dev->event_lock, flags);
1079 return 0;
1080}
1081
1082int
1083nv04_flip_complete(struct nvif_notify *notify)
1084{
1085 struct nouveau_cli *cli = (void *)notify->object->client;
1086 struct nouveau_drm *drm = cli->drm;
1087 struct nouveau_channel *chan = drm->channel;
1088 struct nv04_page_flip_state state;
1089
1090 if (!nv04_finish_page_flip(chan, &state)) {
1091 nv_set_crtc_base(drm->dev, drm_crtc_index(state.crtc),
1092 state.offset + state.crtc->y *
1093 state.pitch + state.crtc->x *
1094 state.bpp / 8);
1095 }
1096
1097 return NVIF_NOTIFY_KEEP;
1098}
1099
1100static int
1101nv04_page_flip_emit(struct nouveau_channel *chan,
1102 struct nouveau_bo *old_bo,
1103 struct nouveau_bo *new_bo,
1104 struct nv04_page_flip_state *s,
1105 struct nouveau_fence **pfence)
1106{
1107 struct nouveau_fence_chan *fctx = chan->fence;
1108 struct nouveau_drm *drm = chan->drm;
1109 struct drm_device *dev = drm->dev;
1110 struct nvif_push *push = chan->chan.push;
1111 unsigned long flags;
1112 int ret;
1113
1114
1115 spin_lock_irqsave(&dev->event_lock, flags);
1116 list_add_tail(&s->head, &fctx->flip);
1117 spin_unlock_irqrestore(&dev->event_lock, flags);
1118
1119
1120 ret = nouveau_fence_sync(old_bo, chan, false, false);
1121 if (ret)
1122 goto fail;
1123
1124
1125 ret = PUSH_WAIT(push, 2);
1126 if (ret)
1127 goto fail;
1128
1129 PUSH_NVSQ(push, NV_SW, NV_SW_PAGE_FLIP, 0x00000000);
1130 PUSH_KICK(push);
1131
1132 ret = nouveau_fence_new(chan, false, pfence);
1133 if (ret)
1134 goto fail;
1135
1136 return 0;
1137fail:
1138 spin_lock_irqsave(&dev->event_lock, flags);
1139 list_del(&s->head);
1140 spin_unlock_irqrestore(&dev->event_lock, flags);
1141 return ret;
1142}
1143
1144static int
1145nv04_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1146 struct drm_pending_vblank_event *event, u32 flags,
1147 struct drm_modeset_acquire_ctx *ctx)
1148{
1149 const int swap_interval = (flags & DRM_MODE_PAGE_FLIP_ASYNC) ? 0 : 1;
1150 struct drm_device *dev = crtc->dev;
1151 struct nouveau_drm *drm = nouveau_drm(dev);
1152 struct drm_framebuffer *old_fb = crtc->primary->fb;
1153 struct nouveau_bo *old_bo = nouveau_gem_object(old_fb->obj[0]);
1154 struct nouveau_bo *new_bo = nouveau_gem_object(fb->obj[0]);
1155 struct nv04_page_flip_state *s;
1156 struct nouveau_channel *chan;
1157 struct nouveau_cli *cli;
1158 struct nouveau_fence *fence;
1159 struct nv04_display *dispnv04 = nv04_display(dev);
1160 struct nvif_push *push;
1161 int head = nouveau_crtc(crtc)->index;
1162 int ret;
1163
1164 chan = drm->channel;
1165 if (!chan)
1166 return -ENODEV;
1167 cli = (void *)chan->user.client;
1168 push = chan->chan.push;
1169
1170 s = kzalloc(sizeof(*s), GFP_KERNEL);
1171 if (!s)
1172 return -ENOMEM;
1173
1174 if (new_bo != old_bo) {
1175 ret = nouveau_bo_pin(new_bo, NOUVEAU_GEM_DOMAIN_VRAM, true);
1176 if (ret)
1177 goto fail_free;
1178 }
1179
1180 mutex_lock(&cli->mutex);
1181 ret = ttm_bo_reserve(&new_bo->bo, true, false, NULL);
1182 if (ret)
1183 goto fail_unpin;
1184
1185
1186 ret = nouveau_fence_sync(new_bo, chan, false, true);
1187 if (ret) {
1188 ttm_bo_unreserve(&new_bo->bo);
1189 goto fail_unpin;
1190 }
1191
1192 if (new_bo != old_bo) {
1193 ttm_bo_unreserve(&new_bo->bo);
1194
1195 ret = ttm_bo_reserve(&old_bo->bo, true, false, NULL);
1196 if (ret)
1197 goto fail_unpin;
1198 }
1199
1200
1201 *s = (struct nv04_page_flip_state)
1202 { { }, event, crtc, fb->format->cpp[0] * 8, fb->pitches[0],
1203 new_bo->offset };
1204
1205
1206 drm_crtc_vblank_get(crtc);
1207
1208
1209 if (swap_interval) {
1210 ret = PUSH_WAIT(push, 8);
1211 if (ret)
1212 goto fail_unreserve;
1213
1214 PUSH_NVSQ(push, NV05F, 0x012c, 0);
1215 PUSH_NVSQ(push, NV05F, 0x0134, head);
1216 PUSH_NVSQ(push, NV05F, 0x0100, 0);
1217 PUSH_NVSQ(push, NV05F, 0x0130, 0);
1218 }
1219
1220 nouveau_bo_ref(new_bo, &dispnv04->image[head]);
1221
1222 ret = nv04_page_flip_emit(chan, old_bo, new_bo, s, &fence);
1223 if (ret)
1224 goto fail_unreserve;
1225 mutex_unlock(&cli->mutex);
1226
1227
1228 crtc->primary->fb = fb;
1229
1230 nouveau_bo_fence(old_bo, fence, false);
1231 ttm_bo_unreserve(&old_bo->bo);
1232 if (old_bo != new_bo)
1233 nouveau_bo_unpin(old_bo);
1234 nouveau_fence_unref(&fence);
1235 return 0;
1236
1237fail_unreserve:
1238 drm_crtc_vblank_put(crtc);
1239 ttm_bo_unreserve(&old_bo->bo);
1240fail_unpin:
1241 mutex_unlock(&cli->mutex);
1242 if (old_bo != new_bo)
1243 nouveau_bo_unpin(new_bo);
1244fail_free:
1245 kfree(s);
1246 return ret;
1247}
1248
1249static const struct drm_crtc_funcs nv04_crtc_funcs = {
1250 .cursor_set = nv04_crtc_cursor_set,
1251 .cursor_move = nv04_crtc_cursor_move,
1252 .gamma_set = nv_crtc_gamma_set,
1253 .set_config = drm_crtc_helper_set_config,
1254 .page_flip = nv04_crtc_page_flip,
1255 .destroy = nv_crtc_destroy,
1256 .enable_vblank = nouveau_display_vblank_enable,
1257 .disable_vblank = nouveau_display_vblank_disable,
1258 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
1259};
1260
1261static const struct drm_crtc_helper_funcs nv04_crtc_helper_funcs = {
1262 .dpms = nv_crtc_dpms,
1263 .prepare = nv_crtc_prepare,
1264 .commit = nv_crtc_commit,
1265 .mode_set = nv_crtc_mode_set,
1266 .mode_set_base = nv04_crtc_mode_set_base,
1267 .mode_set_base_atomic = nv04_crtc_mode_set_base_atomic,
1268 .disable = nv_crtc_disable,
1269 .get_scanout_position = nouveau_display_scanoutpos,
1270};
1271
1272static const uint32_t modeset_formats[] = {
1273 DRM_FORMAT_XRGB8888,
1274 DRM_FORMAT_RGB565,
1275 DRM_FORMAT_XRGB1555,
1276};
1277
1278static struct drm_plane *
1279create_primary_plane(struct drm_device *dev)
1280{
1281 struct drm_plane *primary;
1282 int ret;
1283
1284 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
1285 if (primary == NULL) {
1286 DRM_DEBUG_KMS("Failed to allocate primary plane\n");
1287 return NULL;
1288 }
1289
1290
1291 ret = drm_universal_plane_init(dev, primary, 0,
1292 &drm_primary_helper_funcs,
1293 modeset_formats,
1294 ARRAY_SIZE(modeset_formats), NULL,
1295 DRM_PLANE_TYPE_PRIMARY, NULL);
1296 if (ret) {
1297 kfree(primary);
1298 primary = NULL;
1299 }
1300
1301 return primary;
1302}
1303
1304static int nv04_crtc_vblank_handler(struct nvif_notify *notify)
1305{
1306 struct nouveau_crtc *nv_crtc =
1307 container_of(notify, struct nouveau_crtc, vblank);
1308
1309 drm_crtc_handle_vblank(&nv_crtc->base);
1310 return NVIF_NOTIFY_KEEP;
1311}
1312
1313int
1314nv04_crtc_create(struct drm_device *dev, int crtc_num)
1315{
1316 struct nouveau_display *disp = nouveau_display(dev);
1317 struct nouveau_crtc *nv_crtc;
1318 int ret;
1319
1320 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
1321 if (!nv_crtc)
1322 return -ENOMEM;
1323
1324 nv_crtc->lut.depth = 0;
1325
1326 nv_crtc->index = crtc_num;
1327 nv_crtc->last_dpms = NV_DPMS_CLEARED;
1328
1329 nv_crtc->save = nv_crtc_save;
1330 nv_crtc->restore = nv_crtc_restore;
1331
1332 drm_crtc_init_with_planes(dev, &nv_crtc->base,
1333 create_primary_plane(dev), NULL,
1334 &nv04_crtc_funcs, NULL);
1335 drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs);
1336 drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256);
1337
1338 ret = nouveau_bo_new(&nouveau_drm(dev)->client, 64*64*4, 0x100,
1339 NOUVEAU_GEM_DOMAIN_VRAM, 0, 0x0000, NULL, NULL,
1340 &nv_crtc->cursor.nvbo);
1341 if (!ret) {
1342 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo,
1343 NOUVEAU_GEM_DOMAIN_VRAM, false);
1344 if (!ret) {
1345 ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
1346 if (ret)
1347 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
1348 }
1349 if (ret)
1350 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
1351 }
1352
1353 nv04_cursor_init(nv_crtc);
1354
1355 ret = nvif_notify_ctor(&disp->disp.object, "kmsVbl", nv04_crtc_vblank_handler,
1356 false, NV04_DISP_NTFY_VBLANK,
1357 &(struct nvif_notify_head_req_v0) {
1358 .head = nv_crtc->index,
1359 },
1360 sizeof(struct nvif_notify_head_req_v0),
1361 sizeof(struct nvif_notify_head_rep_v0),
1362 &nv_crtc->vblank);
1363
1364 return ret;
1365}
1366