linux/drivers/gpu/drm/nouveau/dispnv50/atom.h
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   1#ifndef __NV50_KMS_ATOM_H__
   2#define __NV50_KMS_ATOM_H__
   3#define nv50_atom(p) container_of((p), struct nv50_atom, state)
   4#include <drm/drm_atomic.h>
   5#include "crc.h"
   6
   7struct nouveau_encoder;
   8
   9struct nv50_atom {
  10        struct drm_atomic_state state;
  11
  12        struct list_head outp;
  13        bool lock_core;
  14        bool flush_disable;
  15};
  16
  17#define nv50_head_atom(p) container_of((p), struct nv50_head_atom, state)
  18
  19struct nv50_head_atom {
  20        struct drm_crtc_state state;
  21
  22        struct {
  23                u32 mask;
  24                u32 owned;
  25                u32 olut;
  26        } wndw;
  27
  28        struct {
  29                u16 iW;
  30                u16 iH;
  31                u16 oW;
  32                u16 oH;
  33        } view;
  34
  35        struct nv50_head_mode {
  36                bool interlace;
  37                u32 clock;
  38                struct {
  39                        u16 active;
  40                        u16 synce;
  41                        u16 blanke;
  42                        u16 blanks;
  43                } h;
  44                struct {
  45                        u32 active;
  46                        u16 synce;
  47                        u16 blanke;
  48                        u16 blanks;
  49                        u16 blank2s;
  50                        u16 blank2e;
  51                        u16 blankus;
  52                } v;
  53        } mode;
  54
  55        struct {
  56                bool visible;
  57                u32 handle;
  58                u64 offset:40;
  59                u8 buffer:1;
  60                u8 mode:4;
  61                u16 size:11;
  62                u8 range:2;
  63                u8 output_mode:2;
  64                void (*load)(struct drm_color_lut *, int size, void __iomem *);
  65        } olut;
  66
  67        struct {
  68                bool visible;
  69                u32 handle;
  70                u64 offset:40;
  71                u8  format;
  72                u8  kind:7;
  73                u8  layout:1;
  74                u8  blockh:4;
  75                u16 blocks:12;
  76                u32 pitch:20;
  77                u16 x;
  78                u16 y;
  79                u16 w;
  80                u16 h;
  81        } core;
  82
  83        struct {
  84                bool visible;
  85                u32 handle;
  86                u64 offset:40;
  87                u8  layout:2;
  88                u8  format:8;
  89        } curs;
  90
  91        struct {
  92                u8  depth;
  93                u8  cpp;
  94                u16 x;
  95                u16 y;
  96                u16 w;
  97                u16 h;
  98        } base;
  99
 100        struct {
 101                u8 cpp;
 102        } ovly;
 103
 104        struct {
 105                bool enable:1;
 106                u8 bits:2;
 107                u8 mode:4;
 108        } dither;
 109
 110        struct {
 111                struct {
 112                        u16 cos:12;
 113                        u16 sin:12;
 114                } sat;
 115        } procamp;
 116
 117        struct {
 118                u8 nhsync:1;
 119                u8 nvsync:1;
 120                u8 depth:4;
 121                u8 crc_raster:2;
 122                u8 bpc;
 123        } or;
 124
 125        struct nv50_crc_atom crc;
 126
 127        /* Currently only used for MST */
 128        struct {
 129                int pbn;
 130                u8 tu:6;
 131        } dp;
 132
 133        union nv50_head_atom_mask {
 134                struct {
 135                        bool olut:1;
 136                        bool core:1;
 137                        bool curs:1;
 138                        bool view:1;
 139                        bool mode:1;
 140                        bool base:1;
 141                        bool ovly:1;
 142                        bool dither:1;
 143                        bool procamp:1;
 144                        bool crc:1;
 145                        bool or:1;
 146                };
 147                u16 mask;
 148        } set, clr;
 149};
 150
 151static inline struct nv50_head_atom *
 152nv50_head_atom_get(struct drm_atomic_state *state, struct drm_crtc *crtc)
 153{
 154        struct drm_crtc_state *statec = drm_atomic_get_crtc_state(state, crtc);
 155        if (IS_ERR(statec))
 156                return (void *)statec;
 157        return nv50_head_atom(statec);
 158}
 159
 160static inline struct drm_encoder *
 161nv50_head_atom_get_encoder(struct nv50_head_atom *atom)
 162{
 163        struct drm_encoder *encoder = NULL;
 164
 165        /* We only ever have a single encoder */
 166        drm_for_each_encoder_mask(encoder, atom->state.crtc->dev,
 167                                  atom->state.encoder_mask)
 168                break;
 169
 170        return encoder;
 171}
 172
 173#define nv50_wndw_atom(p) container_of((p), struct nv50_wndw_atom, state)
 174
 175struct nv50_wndw_atom {
 176        struct drm_plane_state state;
 177
 178        struct drm_property_blob *ilut;
 179        bool visible;
 180
 181        struct {
 182                u32  handle;
 183                u16  offset:12;
 184                bool awaken:1;
 185        } ntfy;
 186
 187        struct {
 188                u32 handle;
 189                u16 offset:12;
 190                u32 acquire;
 191                u32 release;
 192        } sema;
 193
 194        struct {
 195                u32 handle;
 196                struct {
 197                        u64 offset:40;
 198                        u8  buffer:1;
 199                        u8  enable:2;
 200                        u8  mode:4;
 201                        u16 size:11;
 202                        u8  range:2;
 203                        u8  output_mode:2;
 204                        void (*load)(struct drm_color_lut *, int size,
 205                                     void __iomem *);
 206                } i;
 207        } xlut;
 208
 209        struct {
 210                u32 matrix[12];
 211                bool valid;
 212        } csc;
 213
 214        struct {
 215                u8  mode:2;
 216                u8  interval:4;
 217
 218                u8  colorspace:2;
 219                u8  format;
 220                u8  kind:7;
 221                u8  layout:1;
 222                u8  blockh:4;
 223                u16 blocks[3];
 224                u32 pitch[3];
 225                u16 w;
 226                u16 h;
 227
 228                u32 handle[6];
 229                u64 offset[6];
 230        } image;
 231
 232        struct {
 233                u16 sx;
 234                u16 sy;
 235                u16 sw;
 236                u16 sh;
 237                u16 dw;
 238                u16 dh;
 239        } scale;
 240
 241        struct {
 242                u16 x;
 243                u16 y;
 244        } point;
 245
 246        struct {
 247                u8 depth;
 248                u8 k1;
 249                u8 src_color:4;
 250                u8 dst_color:4;
 251        } blend;
 252
 253        union nv50_wndw_atom_mask {
 254                struct {
 255                        bool ntfy:1;
 256                        bool sema:1;
 257                        bool xlut:1;
 258                        bool csc:1;
 259                        bool image:1;
 260                        bool scale:1;
 261                        bool point:1;
 262                        bool blend:1;
 263                };
 264                u8 mask;
 265        } set, clr;
 266};
 267#endif
 268