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22#include "wndw.h"
23#include "wimm.h"
24#include "handles.h"
25
26#include <nvif/class.h>
27#include <nvif/cl0002.h>
28
29#include <nvhw/class/cl507c.h>
30#include <nvhw/class/cl507e.h>
31#include <nvhw/class/clc37e.h>
32
33#include <drm/drm_atomic.h>
34#include <drm/drm_atomic_helper.h>
35#include <drm/drm_fourcc.h>
36
37#include "nouveau_bo.h"
38#include "nouveau_gem.h"
39
40static void
41nv50_wndw_ctxdma_del(struct nv50_wndw_ctxdma *ctxdma)
42{
43 nvif_object_dtor(&ctxdma->object);
44 list_del(&ctxdma->head);
45 kfree(ctxdma);
46}
47
48static struct nv50_wndw_ctxdma *
49nv50_wndw_ctxdma_new(struct nv50_wndw *wndw, struct drm_framebuffer *fb)
50{
51 struct nouveau_drm *drm = nouveau_drm(fb->dev);
52 struct nv50_wndw_ctxdma *ctxdma;
53 u32 handle;
54 u32 unused;
55 u8 kind;
56 struct {
57 struct nv_dma_v0 base;
58 union {
59 struct nv50_dma_v0 nv50;
60 struct gf100_dma_v0 gf100;
61 struct gf119_dma_v0 gf119;
62 };
63 } args = {};
64 u32 argc = sizeof(args.base);
65 int ret;
66
67 nouveau_framebuffer_get_layout(fb, &unused, &kind);
68 handle = NV50_DISP_HANDLE_WNDW_CTX(kind);
69
70 list_for_each_entry(ctxdma, &wndw->ctxdma.list, head) {
71 if (ctxdma->object.handle == handle)
72 return ctxdma;
73 }
74
75 if (!(ctxdma = kzalloc(sizeof(*ctxdma), GFP_KERNEL)))
76 return ERR_PTR(-ENOMEM);
77 list_add(&ctxdma->head, &wndw->ctxdma.list);
78
79 args.base.target = NV_DMA_V0_TARGET_VRAM;
80 args.base.access = NV_DMA_V0_ACCESS_RDWR;
81 args.base.start = 0;
82 args.base.limit = drm->client.device.info.ram_user - 1;
83
84 if (drm->client.device.info.chipset < 0x80) {
85 args.nv50.part = NV50_DMA_V0_PART_256;
86 argc += sizeof(args.nv50);
87 } else
88 if (drm->client.device.info.chipset < 0xc0) {
89 args.nv50.part = NV50_DMA_V0_PART_256;
90 args.nv50.kind = kind;
91 argc += sizeof(args.nv50);
92 } else
93 if (drm->client.device.info.chipset < 0xd0) {
94 args.gf100.kind = kind;
95 argc += sizeof(args.gf100);
96 } else {
97 args.gf119.page = GF119_DMA_V0_PAGE_LP;
98 args.gf119.kind = kind;
99 argc += sizeof(args.gf119);
100 }
101
102 ret = nvif_object_ctor(wndw->ctxdma.parent, "kmsFbCtxDma", handle,
103 NV_DMA_IN_MEMORY, &args, argc, &ctxdma->object);
104 if (ret) {
105 nv50_wndw_ctxdma_del(ctxdma);
106 return ERR_PTR(ret);
107 }
108
109 return ctxdma;
110}
111
112int
113nv50_wndw_wait_armed(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
114{
115 struct nv50_disp *disp = nv50_disp(wndw->plane.dev);
116 if (asyw->set.ntfy) {
117 return wndw->func->ntfy_wait_begun(disp->sync,
118 asyw->ntfy.offset,
119 wndw->wndw.base.device);
120 }
121 return 0;
122}
123
124void
125nv50_wndw_flush_clr(struct nv50_wndw *wndw, u32 *interlock, bool flush,
126 struct nv50_wndw_atom *asyw)
127{
128 union nv50_wndw_atom_mask clr = {
129 .mask = asyw->clr.mask & ~(flush ? 0 : asyw->set.mask),
130 };
131 if (clr.sema ) wndw->func-> sema_clr(wndw);
132 if (clr.ntfy ) wndw->func-> ntfy_clr(wndw);
133 if (clr.xlut ) wndw->func-> xlut_clr(wndw);
134 if (clr.csc ) wndw->func-> csc_clr(wndw);
135 if (clr.image) wndw->func->image_clr(wndw);
136
137 interlock[wndw->interlock.type] |= wndw->interlock.data;
138}
139
140void
141nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 *interlock,
142 struct nv50_wndw_atom *asyw)
143{
144 if (interlock[NV50_DISP_INTERLOCK_CORE]) {
145 asyw->image.mode = NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING;
146 asyw->image.interval = 1;
147 }
148
149 if (asyw->set.sema ) wndw->func->sema_set (wndw, asyw);
150 if (asyw->set.ntfy ) wndw->func->ntfy_set (wndw, asyw);
151 if (asyw->set.image) wndw->func->image_set(wndw, asyw);
152
153 if (asyw->set.xlut ) {
154 if (asyw->ilut) {
155 asyw->xlut.i.offset =
156 nv50_lut_load(&wndw->ilut, asyw->xlut.i.buffer,
157 asyw->ilut, asyw->xlut.i.load);
158 }
159 wndw->func->xlut_set(wndw, asyw);
160 }
161
162 if (asyw->set.csc ) wndw->func->csc_set (wndw, asyw);
163 if (asyw->set.scale) wndw->func->scale_set(wndw, asyw);
164 if (asyw->set.blend) wndw->func->blend_set(wndw, asyw);
165 if (asyw->set.point) {
166 if (asyw->set.point = false, asyw->set.mask)
167 interlock[wndw->interlock.type] |= wndw->interlock.data;
168 interlock[NV50_DISP_INTERLOCK_WIMM] |= wndw->interlock.wimm;
169
170 wndw->immd->point(wndw, asyw);
171 wndw->immd->update(wndw, interlock);
172 } else {
173 interlock[wndw->interlock.type] |= wndw->interlock.data;
174 }
175}
176
177void
178nv50_wndw_ntfy_enable(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
179{
180 struct nv50_disp *disp = nv50_disp(wndw->plane.dev);
181
182 asyw->ntfy.handle = wndw->wndw.sync.handle;
183 asyw->ntfy.offset = wndw->ntfy;
184 asyw->ntfy.awaken = false;
185 asyw->set.ntfy = true;
186
187 wndw->func->ntfy_reset(disp->sync, wndw->ntfy);
188 wndw->ntfy ^= 0x10;
189}
190
191static void
192nv50_wndw_atomic_check_release(struct nv50_wndw *wndw,
193 struct nv50_wndw_atom *asyw,
194 struct nv50_head_atom *asyh)
195{
196 struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
197 NV_ATOMIC(drm, "%s release\n", wndw->plane.name);
198 wndw->func->release(wndw, asyw, asyh);
199 asyw->ntfy.handle = 0;
200 asyw->sema.handle = 0;
201 asyw->xlut.handle = 0;
202 memset(asyw->image.handle, 0x00, sizeof(asyw->image.handle));
203}
204
205static int
206nv50_wndw_atomic_check_acquire_yuv(struct nv50_wndw_atom *asyw)
207{
208 switch (asyw->state.fb->format->format) {
209 case DRM_FORMAT_YUYV:
210 asyw->image.format = NV507E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8;
211 break;
212 case DRM_FORMAT_UYVY:
213 asyw->image.format = NV507E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8;
214 break;
215 default:
216 WARN_ON(1);
217 return -EINVAL;
218 }
219
220 asyw->image.colorspace = NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601;
221 return 0;
222}
223
224static int
225nv50_wndw_atomic_check_acquire_rgb(struct nv50_wndw_atom *asyw)
226{
227 switch (asyw->state.fb->format->format) {
228 case DRM_FORMAT_C8:
229 asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_I8;
230 break;
231 case DRM_FORMAT_XRGB8888:
232 case DRM_FORMAT_ARGB8888:
233 asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8;
234 break;
235 case DRM_FORMAT_RGB565:
236 asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_R5G6B5;
237 break;
238 case DRM_FORMAT_XRGB1555:
239 case DRM_FORMAT_ARGB1555:
240 asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5;
241 break;
242 case DRM_FORMAT_XBGR2101010:
243 case DRM_FORMAT_ABGR2101010:
244 asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10;
245 break;
246 case DRM_FORMAT_XBGR8888:
247 case DRM_FORMAT_ABGR8888:
248 asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8;
249 break;
250 case DRM_FORMAT_XRGB2101010:
251 case DRM_FORMAT_ARGB2101010:
252 asyw->image.format = NVC37E_SET_PARAMS_FORMAT_A2R10G10B10;
253 break;
254 case DRM_FORMAT_XBGR16161616F:
255 case DRM_FORMAT_ABGR16161616F:
256 asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16;
257 break;
258 default:
259 return -EINVAL;
260 }
261
262 asyw->image.colorspace = NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB;
263 return 0;
264}
265
266static int
267nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, bool modeset,
268 struct nv50_wndw_atom *armw,
269 struct nv50_wndw_atom *asyw,
270 struct nv50_head_atom *asyh)
271{
272 struct drm_framebuffer *fb = asyw->state.fb;
273 struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
274 uint8_t kind;
275 uint32_t tile_mode;
276 int ret;
277
278 NV_ATOMIC(drm, "%s acquire\n", wndw->plane.name);
279
280 if (fb != armw->state.fb || !armw->visible || modeset) {
281 nouveau_framebuffer_get_layout(fb, &tile_mode, &kind);
282
283 asyw->image.w = fb->width;
284 asyw->image.h = fb->height;
285 asyw->image.kind = kind;
286
287 ret = nv50_wndw_atomic_check_acquire_rgb(asyw);
288 if (ret) {
289 ret = nv50_wndw_atomic_check_acquire_yuv(asyw);
290 if (ret)
291 return ret;
292 }
293
294 if (asyw->image.kind) {
295 asyw->image.layout = NV507C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR;
296 if (drm->client.device.info.chipset >= 0xc0)
297 asyw->image.blockh = tile_mode >> 4;
298 else
299 asyw->image.blockh = tile_mode;
300 asyw->image.blocks[0] = fb->pitches[0] / 64;
301 asyw->image.pitch[0] = 0;
302 } else {
303 asyw->image.layout = NV507C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH;
304 asyw->image.blockh = NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB;
305 asyw->image.blocks[0] = 0;
306 asyw->image.pitch[0] = fb->pitches[0];
307 }
308
309 if (!asyh->state.async_flip)
310 asyw->image.interval = 1;
311 else
312 asyw->image.interval = 0;
313
314 if (asyw->image.interval)
315 asyw->image.mode = NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING;
316 else
317 asyw->image.mode = NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE;
318
319 asyw->set.image = wndw->func->image_set != NULL;
320 }
321
322 if (wndw->func->scale_set) {
323 asyw->scale.sx = asyw->state.src_x >> 16;
324 asyw->scale.sy = asyw->state.src_y >> 16;
325 asyw->scale.sw = asyw->state.src_w >> 16;
326 asyw->scale.sh = asyw->state.src_h >> 16;
327 asyw->scale.dw = asyw->state.crtc_w;
328 asyw->scale.dh = asyw->state.crtc_h;
329 if (memcmp(&armw->scale, &asyw->scale, sizeof(asyw->scale)))
330 asyw->set.scale = true;
331 }
332
333 if (wndw->func->blend_set) {
334 asyw->blend.depth = 255 - asyw->state.normalized_zpos;
335 asyw->blend.k1 = asyw->state.alpha >> 8;
336 switch (asyw->state.pixel_blend_mode) {
337 case DRM_MODE_BLEND_PREMULTI:
338 asyw->blend.src_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1;
339 asyw->blend.dst_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC;
340 break;
341 case DRM_MODE_BLEND_COVERAGE:
342 asyw->blend.src_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC;
343 asyw->blend.dst_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC;
344 break;
345 case DRM_MODE_BLEND_PIXEL_NONE:
346 default:
347 asyw->blend.src_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1;
348 asyw->blend.dst_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1;
349 break;
350 }
351 if (memcmp(&armw->blend, &asyw->blend, sizeof(asyw->blend)))
352 asyw->set.blend = true;
353 }
354
355 if (wndw->immd) {
356 asyw->point.x = asyw->state.crtc_x;
357 asyw->point.y = asyw->state.crtc_y;
358 if (memcmp(&armw->point, &asyw->point, sizeof(asyw->point)))
359 asyw->set.point = true;
360 }
361
362 return wndw->func->acquire(wndw, asyw, asyh);
363}
364
365static int
366nv50_wndw_atomic_check_lut(struct nv50_wndw *wndw,
367 struct nv50_wndw_atom *armw,
368 struct nv50_wndw_atom *asyw,
369 struct nv50_head_atom *asyh)
370{
371 struct drm_property_blob *ilut = asyh->state.degamma_lut;
372
373
374
375
376
377
378
379 if (!ilut && asyw->state.fb->format->format == DRM_FORMAT_C8) {
380
381
382
383
384
385 if (!(ilut = asyh->state.gamma_lut)) {
386 asyw->visible = false;
387 return 0;
388 }
389
390 if (wndw->func->ilut)
391 asyh->wndw.olut |= BIT(wndw->id);
392 } else {
393 asyh->wndw.olut &= ~BIT(wndw->id);
394 }
395
396 if (!ilut && wndw->func->ilut_identity &&
397 asyw->state.fb->format->format != DRM_FORMAT_XBGR16161616F &&
398 asyw->state.fb->format->format != DRM_FORMAT_ABGR16161616F) {
399 static struct drm_property_blob dummy = {};
400 ilut = &dummy;
401 }
402
403
404 memset(&asyw->xlut, 0x00, sizeof(asyw->xlut));
405 if ((asyw->ilut = wndw->func->ilut ? ilut : NULL)) {
406 if (!wndw->func->ilut(wndw, asyw, drm_color_lut_size(ilut))) {
407 DRM_DEBUG_KMS("Invalid ilut\n");
408 return -EINVAL;
409 }
410 asyw->xlut.handle = wndw->wndw.vram.handle;
411 asyw->xlut.i.buffer = !asyw->xlut.i.buffer;
412 asyw->set.xlut = true;
413 } else {
414 asyw->clr.xlut = armw->xlut.handle != 0;
415 }
416
417
418 if (wndw->func->olut_core &&
419 (!armw->visible || (armw->xlut.handle && !asyw->xlut.handle)))
420 asyw->set.xlut = true;
421
422 if (wndw->func->csc && asyh->state.ctm) {
423 const struct drm_color_ctm *ctm = asyh->state.ctm->data;
424 wndw->func->csc(wndw, asyw, ctm);
425 asyw->csc.valid = true;
426 asyw->set.csc = true;
427 } else {
428 asyw->csc.valid = false;
429 asyw->clr.csc = armw->csc.valid;
430 }
431
432
433 asyh->state.async_flip = false;
434 return 0;
435}
436
437static int
438nv50_wndw_atomic_check(struct drm_plane *plane,
439 struct drm_atomic_state *state)
440{
441 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
442 plane);
443 struct nouveau_drm *drm = nouveau_drm(plane->dev);
444 struct nv50_wndw *wndw = nv50_wndw(plane);
445 struct nv50_wndw_atom *armw = nv50_wndw_atom(wndw->plane.state);
446 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
447 struct nv50_head_atom *harm = NULL, *asyh = NULL;
448 bool modeset = false;
449 int ret;
450
451 NV_ATOMIC(drm, "%s atomic_check\n", plane->name);
452
453
454
455
456 if (asyw->state.crtc) {
457 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc);
458 if (IS_ERR(asyh))
459 return PTR_ERR(asyh);
460 modeset = drm_atomic_crtc_needs_modeset(&asyh->state);
461 asyw->visible = asyh->state.active;
462 } else {
463 asyw->visible = false;
464 }
465
466
467 if (armw->state.crtc) {
468 harm = nv50_head_atom_get(asyw->state.state, armw->state.crtc);
469 if (IS_ERR(harm))
470 return PTR_ERR(harm);
471 }
472
473
474 if (asyw->visible && wndw->func->xlut_set &&
475 (!armw->visible ||
476 asyh->state.color_mgmt_changed ||
477 asyw->state.fb->format->format !=
478 armw->state.fb->format->format)) {
479 ret = nv50_wndw_atomic_check_lut(wndw, armw, asyw, asyh);
480 if (ret)
481 return ret;
482 }
483
484
485 if (asyw->visible) {
486 ret = nv50_wndw_atomic_check_acquire(wndw, modeset,
487 armw, asyw, asyh);
488 if (ret)
489 return ret;
490
491 asyh->wndw.mask |= BIT(wndw->id);
492 } else
493 if (armw->visible) {
494 nv50_wndw_atomic_check_release(wndw, asyw, harm);
495 harm->wndw.mask &= ~BIT(wndw->id);
496 } else {
497 return 0;
498 }
499
500
501
502
503
504 if (!asyw->visible || modeset) {
505 asyw->clr.ntfy = armw->ntfy.handle != 0;
506 asyw->clr.sema = armw->sema.handle != 0;
507 asyw->clr.xlut = armw->xlut.handle != 0;
508 if (asyw->clr.xlut && asyw->visible)
509 asyw->set.xlut = asyw->xlut.handle != 0;
510 asyw->clr.csc = armw->csc.valid;
511 if (wndw->func->image_clr)
512 asyw->clr.image = armw->image.handle[0] != 0;
513 }
514
515 return 0;
516}
517
518static void
519nv50_wndw_cleanup_fb(struct drm_plane *plane, struct drm_plane_state *old_state)
520{
521 struct nouveau_drm *drm = nouveau_drm(plane->dev);
522 struct nouveau_bo *nvbo;
523
524 NV_ATOMIC(drm, "%s cleanup: %p\n", plane->name, old_state->fb);
525 if (!old_state->fb)
526 return;
527
528 nvbo = nouveau_gem_object(old_state->fb->obj[0]);
529 nouveau_bo_unpin(nvbo);
530}
531
532static int
533nv50_wndw_prepare_fb(struct drm_plane *plane, struct drm_plane_state *state)
534{
535 struct drm_framebuffer *fb = state->fb;
536 struct nouveau_drm *drm = nouveau_drm(plane->dev);
537 struct nv50_wndw *wndw = nv50_wndw(plane);
538 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
539 struct nouveau_bo *nvbo;
540 struct nv50_head_atom *asyh;
541 struct nv50_wndw_ctxdma *ctxdma;
542 int ret;
543
544 NV_ATOMIC(drm, "%s prepare: %p\n", plane->name, fb);
545 if (!asyw->state.fb)
546 return 0;
547
548 nvbo = nouveau_gem_object(fb->obj[0]);
549 ret = nouveau_bo_pin(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, true);
550 if (ret)
551 return ret;
552
553 if (wndw->ctxdma.parent) {
554 ctxdma = nv50_wndw_ctxdma_new(wndw, fb);
555 if (IS_ERR(ctxdma)) {
556 nouveau_bo_unpin(nvbo);
557 return PTR_ERR(ctxdma);
558 }
559
560 if (asyw->visible)
561 asyw->image.handle[0] = ctxdma->object.handle;
562 }
563
564 asyw->state.fence = dma_resv_get_excl_unlocked(nvbo->bo.base.resv);
565 asyw->image.offset[0] = nvbo->offset;
566
567 if (wndw->func->prepare) {
568 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc);
569 if (IS_ERR(asyh))
570 return PTR_ERR(asyh);
571
572 wndw->func->prepare(wndw, asyh, asyw);
573 }
574
575 return 0;
576}
577
578static const struct drm_plane_helper_funcs
579nv50_wndw_helper = {
580 .prepare_fb = nv50_wndw_prepare_fb,
581 .cleanup_fb = nv50_wndw_cleanup_fb,
582 .atomic_check = nv50_wndw_atomic_check,
583};
584
585static void
586nv50_wndw_atomic_destroy_state(struct drm_plane *plane,
587 struct drm_plane_state *state)
588{
589 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
590 __drm_atomic_helper_plane_destroy_state(&asyw->state);
591 kfree(asyw);
592}
593
594static struct drm_plane_state *
595nv50_wndw_atomic_duplicate_state(struct drm_plane *plane)
596{
597 struct nv50_wndw_atom *armw = nv50_wndw_atom(plane->state);
598 struct nv50_wndw_atom *asyw;
599 if (!(asyw = kmalloc(sizeof(*asyw), GFP_KERNEL)))
600 return NULL;
601 __drm_atomic_helper_plane_duplicate_state(plane, &asyw->state);
602 asyw->sema = armw->sema;
603 asyw->ntfy = armw->ntfy;
604 asyw->ilut = NULL;
605 asyw->xlut = armw->xlut;
606 asyw->csc = armw->csc;
607 asyw->image = armw->image;
608 asyw->point = armw->point;
609 asyw->clr.mask = 0;
610 asyw->set.mask = 0;
611 return &asyw->state;
612}
613
614static int
615nv50_wndw_zpos_default(struct drm_plane *plane)
616{
617 return (plane->type == DRM_PLANE_TYPE_PRIMARY) ? 0 :
618 (plane->type == DRM_PLANE_TYPE_OVERLAY) ? 1 : 255;
619}
620
621static void
622nv50_wndw_reset(struct drm_plane *plane)
623{
624 struct nv50_wndw_atom *asyw;
625
626 if (WARN_ON(!(asyw = kzalloc(sizeof(*asyw), GFP_KERNEL))))
627 return;
628
629 if (plane->state)
630 plane->funcs->atomic_destroy_state(plane, plane->state);
631
632 __drm_atomic_helper_plane_reset(plane, &asyw->state);
633 plane->state->zpos = nv50_wndw_zpos_default(plane);
634 plane->state->normalized_zpos = nv50_wndw_zpos_default(plane);
635}
636
637static void
638nv50_wndw_destroy(struct drm_plane *plane)
639{
640 struct nv50_wndw *wndw = nv50_wndw(plane);
641 struct nv50_wndw_ctxdma *ctxdma, *ctxtmp;
642
643 list_for_each_entry_safe(ctxdma, ctxtmp, &wndw->ctxdma.list, head) {
644 nv50_wndw_ctxdma_del(ctxdma);
645 }
646
647 nvif_notify_dtor(&wndw->notify);
648 nv50_dmac_destroy(&wndw->wimm);
649 nv50_dmac_destroy(&wndw->wndw);
650
651 nv50_lut_fini(&wndw->ilut);
652
653 drm_plane_cleanup(&wndw->plane);
654 kfree(wndw);
655}
656
657
658
659
660
661static bool nv50_plane_format_mod_supported(struct drm_plane *plane,
662 u32 format, u64 modifier)
663{
664 struct nouveau_drm *drm = nouveau_drm(plane->dev);
665 uint8_t i;
666
667 if (drm->client.device.info.chipset < 0xc0) {
668 const struct drm_format_info *info = drm_format_info(format);
669 const uint8_t kind = (modifier >> 12) & 0xff;
670
671 if (!format) return false;
672
673 for (i = 0; i < info->num_planes; i++)
674 if ((info->cpp[i] != 4) && kind != 0x70) return false;
675 }
676
677 return true;
678}
679
680const struct drm_plane_funcs
681nv50_wndw = {
682 .update_plane = drm_atomic_helper_update_plane,
683 .disable_plane = drm_atomic_helper_disable_plane,
684 .destroy = nv50_wndw_destroy,
685 .reset = nv50_wndw_reset,
686 .atomic_duplicate_state = nv50_wndw_atomic_duplicate_state,
687 .atomic_destroy_state = nv50_wndw_atomic_destroy_state,
688 .format_mod_supported = nv50_plane_format_mod_supported,
689};
690
691static int
692nv50_wndw_notify(struct nvif_notify *notify)
693{
694 return NVIF_NOTIFY_KEEP;
695}
696
697void
698nv50_wndw_fini(struct nv50_wndw *wndw)
699{
700 nvif_notify_put(&wndw->notify);
701}
702
703void
704nv50_wndw_init(struct nv50_wndw *wndw)
705{
706 nvif_notify_get(&wndw->notify);
707}
708
709static const u64 nv50_cursor_format_modifiers[] = {
710 DRM_FORMAT_MOD_LINEAR,
711 DRM_FORMAT_MOD_INVALID,
712};
713
714int
715nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev,
716 enum drm_plane_type type, const char *name, int index,
717 const u32 *format, u32 heads,
718 enum nv50_disp_interlock_type interlock_type, u32 interlock_data,
719 struct nv50_wndw **pwndw)
720{
721 struct nouveau_drm *drm = nouveau_drm(dev);
722 struct nvif_mmu *mmu = &drm->client.mmu;
723 struct nv50_disp *disp = nv50_disp(dev);
724 struct nv50_wndw *wndw;
725 const u64 *format_modifiers;
726 int nformat;
727 int ret;
728
729 if (!(wndw = *pwndw = kzalloc(sizeof(*wndw), GFP_KERNEL)))
730 return -ENOMEM;
731 wndw->func = func;
732 wndw->id = index;
733 wndw->interlock.type = interlock_type;
734 wndw->interlock.data = interlock_data;
735
736 wndw->ctxdma.parent = &wndw->wndw.base.user;
737 INIT_LIST_HEAD(&wndw->ctxdma.list);
738
739 for (nformat = 0; format[nformat]; nformat++);
740
741 if (type == DRM_PLANE_TYPE_CURSOR)
742 format_modifiers = nv50_cursor_format_modifiers;
743 else
744 format_modifiers = nouveau_display(dev)->format_modifiers;
745
746 ret = drm_universal_plane_init(dev, &wndw->plane, heads, &nv50_wndw, format, nformat,
747 format_modifiers, type, "%s-%d", name, index);
748 if (ret) {
749 kfree(*pwndw);
750 *pwndw = NULL;
751 return ret;
752 }
753
754 drm_plane_helper_add(&wndw->plane, &nv50_wndw_helper);
755
756 if (wndw->func->ilut) {
757 ret = nv50_lut_init(disp, mmu, &wndw->ilut);
758 if (ret)
759 return ret;
760 }
761
762 wndw->notify.func = nv50_wndw_notify;
763
764 if (wndw->func->blend_set) {
765 ret = drm_plane_create_zpos_property(&wndw->plane,
766 nv50_wndw_zpos_default(&wndw->plane), 0, 254);
767 if (ret)
768 return ret;
769
770 ret = drm_plane_create_alpha_property(&wndw->plane);
771 if (ret)
772 return ret;
773
774 ret = drm_plane_create_blend_mode_property(&wndw->plane,
775 BIT(DRM_MODE_BLEND_PIXEL_NONE) |
776 BIT(DRM_MODE_BLEND_PREMULTI) |
777 BIT(DRM_MODE_BLEND_COVERAGE));
778 if (ret)
779 return ret;
780 } else {
781 ret = drm_plane_create_zpos_immutable_property(&wndw->plane,
782 nv50_wndw_zpos_default(&wndw->plane));
783 if (ret)
784 return ret;
785 }
786
787 return 0;
788}
789
790int
791nv50_wndw_new(struct nouveau_drm *drm, enum drm_plane_type type, int index,
792 struct nv50_wndw **pwndw)
793{
794 struct {
795 s32 oclass;
796 int version;
797 int (*new)(struct nouveau_drm *, enum drm_plane_type,
798 int, s32, struct nv50_wndw **);
799 } wndws[] = {
800 { GA102_DISP_WINDOW_CHANNEL_DMA, 0, wndwc67e_new },
801 { TU102_DISP_WINDOW_CHANNEL_DMA, 0, wndwc57e_new },
802 { GV100_DISP_WINDOW_CHANNEL_DMA, 0, wndwc37e_new },
803 {}
804 };
805 struct nv50_disp *disp = nv50_disp(drm->dev);
806 int cid, ret;
807
808 cid = nvif_mclass(&disp->disp->object, wndws);
809 if (cid < 0) {
810 NV_ERROR(drm, "No supported window class\n");
811 return cid;
812 }
813
814 ret = wndws[cid].new(drm, type, index, wndws[cid].oclass, pwndw);
815 if (ret)
816 return ret;
817
818 return nv50_wimm_init(drm, *pwndw);
819}
820
