linux/drivers/gpu/drm/nouveau/include/nvfw/acr.h
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   1#ifndef __NVFW_ACR_H__
   2#define __NVFW_ACR_H__
   3
   4struct wpr_header {
   5#define WPR_HEADER_V0_FALCON_ID_INVALID                              0xffffffff
   6        u32 falcon_id;
   7        u32 lsb_offset;
   8        u32 bootstrap_owner;
   9        u32 lazy_bootstrap;
  10#define WPR_HEADER_V0_STATUS_NONE                                             0
  11#define WPR_HEADER_V0_STATUS_COPY                                             1
  12#define WPR_HEADER_V0_STATUS_VALIDATION_CODE_FAILED                           2
  13#define WPR_HEADER_V0_STATUS_VALIDATION_DATA_FAILED                           3
  14#define WPR_HEADER_V0_STATUS_VALIDATION_DONE                                  4
  15#define WPR_HEADER_V0_STATUS_VALIDATION_SKIPPED                               5
  16#define WPR_HEADER_V0_STATUS_BOOTSTRAP_READY                                  6
  17        u32 status;
  18};
  19
  20void wpr_header_dump(struct nvkm_subdev *, const struct wpr_header *);
  21
  22struct wpr_header_v1 {
  23#define WPR_HEADER_V1_FALCON_ID_INVALID                              0xffffffff
  24        u32 falcon_id;
  25        u32 lsb_offset;
  26        u32 bootstrap_owner;
  27        u32 lazy_bootstrap;
  28        u32 bin_version;
  29#define WPR_HEADER_V1_STATUS_NONE                                             0
  30#define WPR_HEADER_V1_STATUS_COPY                                             1
  31#define WPR_HEADER_V1_STATUS_VALIDATION_CODE_FAILED                           2
  32#define WPR_HEADER_V1_STATUS_VALIDATION_DATA_FAILED                           3
  33#define WPR_HEADER_V1_STATUS_VALIDATION_DONE                                  4
  34#define WPR_HEADER_V1_STATUS_VALIDATION_SKIPPED                               5
  35#define WPR_HEADER_V1_STATUS_BOOTSTRAP_READY                                  6
  36#define WPR_HEADER_V1_STATUS_REVOCATION_CHECK_FAILED                          7
  37        u32 status;
  38};
  39
  40void wpr_header_v1_dump(struct nvkm_subdev *, const struct wpr_header_v1 *);
  41
  42struct lsf_signature {
  43        u8 prd_keys[2][16];
  44        u8 dbg_keys[2][16];
  45        u32 b_prd_present;
  46        u32 b_dbg_present;
  47        u32 falcon_id;
  48};
  49
  50struct lsf_signature_v1 {
  51        u8 prd_keys[2][16];
  52        u8 dbg_keys[2][16];
  53        u32 b_prd_present;
  54        u32 b_dbg_present;
  55        u32 falcon_id;
  56        u32 supports_versioning;
  57        u32 version;
  58        u32 depmap_count;
  59        u8 depmap[11/*LSF_LSB_DEPMAP_SIZE*/ * 2 * 4];
  60        u8 kdf[16];
  61};
  62
  63struct lsb_header_tail {
  64        u32 ucode_off;
  65        u32 ucode_size;
  66        u32 data_size;
  67        u32 bl_code_size;
  68        u32 bl_imem_off;
  69        u32 bl_data_off;
  70        u32 bl_data_size;
  71        u32 app_code_off;
  72        u32 app_code_size;
  73        u32 app_data_off;
  74        u32 app_data_size;
  75        u32 flags;
  76};
  77
  78struct lsb_header {
  79        struct lsf_signature signature;
  80        struct lsb_header_tail tail;
  81};
  82
  83void lsb_header_dump(struct nvkm_subdev *, struct lsb_header *);
  84
  85struct lsb_header_v1 {
  86        struct lsf_signature_v1 signature;
  87        struct lsb_header_tail tail;
  88};
  89
  90void lsb_header_v1_dump(struct nvkm_subdev *, struct lsb_header_v1 *);
  91
  92struct flcn_acr_desc {
  93        union {
  94                u8 reserved_dmem[0x200];
  95                u32 signatures[4];
  96        } ucode_reserved_space;
  97        u32 wpr_region_id;
  98        u32 wpr_offset;
  99        u32 mmu_mem_range;
 100        struct {
 101                u32 no_regions;
 102                struct {
 103                        u32 start_addr;
 104                        u32 end_addr;
 105                        u32 region_id;
 106                        u32 read_mask;
 107                        u32 write_mask;
 108                        u32 client_mask;
 109                } region_props[2];
 110        } regions;
 111        u32 ucode_blob_size;
 112        u64 ucode_blob_base __aligned(8);
 113        struct {
 114                u32 vpr_enabled;
 115                u32 vpr_start;
 116                u32 vpr_end;
 117                u32 hdcp_policies;
 118        } vpr_desc;
 119};
 120
 121void flcn_acr_desc_dump(struct nvkm_subdev *, struct flcn_acr_desc *);
 122
 123struct flcn_acr_desc_v1 {
 124        u8 reserved_dmem[0x200];
 125        u32 signatures[4];
 126        u32 wpr_region_id;
 127        u32 wpr_offset;
 128        u32 mmu_memory_range;
 129        struct {
 130                u32 no_regions;
 131                struct {
 132                        u32 start_addr;
 133                        u32 end_addr;
 134                        u32 region_id;
 135                        u32 read_mask;
 136                        u32 write_mask;
 137                        u32 client_mask;
 138                        u32 shadow_mem_start_addr;
 139                } region_props[2];
 140        } regions;
 141        u32 ucode_blob_size;
 142        u64 ucode_blob_base __aligned(8);
 143        struct {
 144                u32 vpr_enabled;
 145                u32 vpr_start;
 146                u32 vpr_end;
 147                u32 hdcp_policies;
 148        } vpr_desc;
 149};
 150
 151void flcn_acr_desc_v1_dump(struct nvkm_subdev *, struct flcn_acr_desc_v1 *);
 152#endif
 153